rpms/kernel/F-10 drm-next.patch,1.12,1.13

Chuck Ebbert cebbert at fedoraproject.org
Sun Mar 1 04:01:31 UTC 2009


Author: cebbert

Update of /cvs/pkgs/rpms/kernel/F-10
In directory cvs1.fedora.phx.redhat.com:/tmp/cvs-serv5383

Added Files:
	drm-next.patch 
Log Message:
add drm-next

drm-next.patch:

View full diff with command:
/usr/bin/cvs -f diff  -kk -u -N -r 1.12 -r 1.13 drm-next.patch
Index: drm-next.patch
===================================================================
RCS file: drm-next.patch
diff -N drm-next.patch
--- /dev/null	1 Jan 1970 00:00:00 -0000
+++ drm-next.patch	1 Mar 2009 04:01:30 -0000	1.13
@@ -0,0 +1,31664 @@
+commit afdecdb151030e719a95896b610fdbde0ad4ca9f
+Author: Dave Airlie <airlied at redhat.com>
+Date:   Thu Feb 26 10:15:24 2009 +1000
+
+    drm/r600: fix rptr address along lines of previous fixes to radeon.
+    
+    Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit cc35bf2855020c4067e298cbd50fa5494b82ab7f
+Author: Dave Airlie <airlied at redhat.com>
+Date:   Thu Feb 26 10:14:40 2009 +1000
+
+    drm/r600: fixup r600 gart table accessor like ati_pcigart.c
+    
+    This attempts to fixup the r600 GART accessors so they work on other arches.
+    
+    Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit 0101c60cfa2d6bd9e86524f267f8ba092bc7b0ae
+Author: Dave Airlie <airlied at redhat.com>
+Date:   Thu Feb 26 10:13:47 2009 +1000
+
+    drm/ati_pcigart: use memset_io to reset the memory
+    
+    Also don't setup pci_gart if we aren't going to need it.
+    
+    Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit c455abd7d1f5ed1815d692f37b317f8eab358ced
+Author: Dave Airlie <airlied at redhat.com>
+Date:   Thu Feb 26 10:12:10 2009 +1000
+
+    drm: add DRM_READ/WRITE64 wrappers around readq/writeq.
+    
+    The readq/writeq stuff is from Dave Miller, and he
+    warns users to be careful about using these. Plans are only
+    r600 to use it so far.
+    
+    Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit 89de134be815fe9e30ca42aeac8a4ef5c8db8d30
+Author: Alex Deucher <alexdeucher at gmail.com>
+Date:   Wed Feb 25 17:02:19 2009 -0500
+
+    radeon: add RS600 pci ids
+    
+    Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
+    Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit 8dba4f2bd6d91a38a732dc3417187b75a6607e62
+Author: Alex Deucher <alexdeucher at gmail.com>
+Date:   Wed Feb 25 16:57:49 2009 -0500
+
+    radeon: add support for rs600 GPUs
+    
+    RS600s are an AMD IGP for Intel CPUs, that look like RS690s from
+    a lot of perspectives but look like r600s from a memory controller
+    point of view.
+    
+    Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
+    Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit e482e2e2c5dab12db6f1aa032c30993ca36d77b9
+Author: Alex Deucher <alexdeucher at gmail.com>
+Date:   Wed Feb 25 15:55:01 2009 -0500
+
+    radeon: fix r600 AGP support
+    
+    This fixes the ioremap issues with r600 AGP.
+    
+    Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
+    Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit dbcce50efba41272d795b64edd06b1261dbdc5b8
+Author: Alex Deucher <alexdeucher at gmail.com>
+Date:   Tue Feb 24 17:13:42 2009 -0500
+
+    radeon: add R6xx/R7xx pci ids
+    
+    Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
+    Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit 69184db08c49fd54d4e3a197dae64581c35a144f
+Author: Alex Deucher <alexdeucher at gmail.com>
+Date:   Tue Feb 24 16:22:29 2009 -0500
+
+    drm/radeon: add initial support for R6xx/R7xx GPUs
+    
+    This adds support for 2D/Xv acceleration in the X.org 2D driver,
+    to the drm. It doesn't yet provide any 3D support hooks.
+    
+    Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
+    Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit b95ec10efe0bb8a106c6ab4edc019033c5081d3d
+Author: Alex Deucher <alexdeucher at gmail.com>
+Date:   Tue Feb 24 14:28:34 2009 -0500
+
+    drm/radeon: add r6xx/r7xx microcode
+    
+    This uses the same microcode system as the current radeon code.
+    
+    It should be converted to the new microcode loader I suppose,
+    though really I need a lot more proof of the worth of me maintaining
+    firmware blobs externally.
+    
+    Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
+    Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit 1e7e66e6dce44a77d4042b80de23c8ba4346c459
+Author: Alex Deucher <alexdeucher at gmail.com>
+Date:   Tue Feb 24 14:02:13 2009 -0500
+
+    drm/radeon: prep for r6xx/r7xx support
+    
+    - add r6xx/r7xx regs and macros
+    - add r6xx/r7xx chip families
+    - fix register access for regs with offsets >= 0x10000
+    
+    Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
+    Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit 9cb39ece1f32fe75e7c34b193022650108d4bf0f
+Author: Owain G. Ainsworth <oga at openbsd.org>
+Date:   Fri Feb 20 08:30:19 2009 +0000
+
+    i915/drm: Remove two redundant agp_chipset_flushes
+    
+    agp_chipset_flush() is for flushing the intel GMCH write cache via the
+    IFP, these two uses are for when we're getting the object into the cpu
+    READ domain, and thus should not be needed. This confused me when I was
+    getting my head around the code.
+    
+    With thanks to airlied for helping me check my mental picture of how the
+    flushes and clflushes are supposed to be used.
+    
+    Signed-off-by: Owain G. Ainsworth <oga at openbsd.org>
+    Signed-off-by: Eric Anholt <eric at anholt.net>
+    Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit 5e60aaba5c9d226ec49f4c1030fc871bcea86048
+Author: Chris Wilson <chris at chris-wilson.co.uk>
+Date:   Wed Feb 11 14:26:38 2009 +0000
+
+    drm/i915: Display fence register state in debugfs i915_gem_fence_regs node.
+    
+    Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
+    Signed-off-by: Eric Anholt <eric at anholt.net>
+    Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit 475f933c677b8c59f34744aed2fc3bdcbec24c6e
+Author: Eric Anholt <eric at anholt.net>
+Date:   Tue Feb 17 23:53:41 2009 -0800
+
+    drm/i915: Add information on pinning and fencing to the i915 list debug.
+    
+    This was inspired by a patch by Chris Wilson, though none of it applied in any
+    way due to the debugfs work and I decided to change the formatting of the
+    new information anyway.
+    
+    Signed-off-by: Eric Anholt <eric at anholt.net>
+    Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit b4212836fef1ef28c6070f43d70fc73f9f5687f6
+Author: Ben Gamari <bgamari at gmail.com>
+Date:   Tue Feb 17 20:08:51 2009 -0500
+
+    drm/i915: Consolidate gem object list dumping
+    
+    Here we eliminate a few functions in favor of using a single function
+    to dump from all of the object lists.
+    
+    Signed-Off-By: Ben Gamari <bgamari at gmail.com>
+    Signed-off-by: Eric Anholt <eric at anholt.net>
+    Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit a584bb1ed4de35a9206a8ed42fc7de18b3d46b5a
+Author: Ben Gamari <bgamari at gmail.com>
+Date:   Tue Feb 17 20:08:49 2009 -0500
+
+    drm: Convert proc files to seq_file and introduce debugfs
+    
+    The old mechanism to formatting proc files is extremely ugly. The
+    seq_file API was designed specifically for cases like this and greatly
+    simplifies the process.
+    
+    Also, most of the files in /proc really don't belong there. This patch
+    introduces the infrastructure for putting these into debugfs and exposes
+    all of the proc files in debugfs as well.
+    
+    This contains the i915 hooks rewrite as well, to make bisectability better.
+    
+    Signed-off-by: Ben Gamari <bgamari at gmail.com>
[...31271 lines suppressed...]
+ 
+diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
+index 5ded1ac..33ae98c 100644
+--- a/include/drm/drm_crtc.h
++++ b/include/drm/drm_crtc.h
+@@ -550,7 +550,7 @@ struct drm_mode_config {
+ 	int min_width, min_height;
+ 	int max_width, max_height;
+ 	struct drm_mode_config_funcs *funcs;
+-	unsigned long fb_base;
++	resource_size_t fb_base;
+ 
+ 	/* pointers to standard properties */
+ 	struct list_head property_blob_list;
+diff --git a/include/drm/drm_os_linux.h b/include/drm/drm_os_linux.h
+index 8dbd257..013551d 100644
+--- a/include/drm/drm_os_linux.h
++++ b/include/drm/drm_os_linux.h
+@@ -6,6 +6,19 @@
+ #include <linux/interrupt.h>	/* For task queue support */
+ #include <linux/delay.h>
+ 
++#ifndef readq
++static u64 readq(void __iomem *reg)
++{
++	return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32);
++}
++
++static void writeq(u64 val, void __iomem *reg)
++{
++	writel(val & 0xffffffff, reg);
++	writel(val >> 32, reg + 0x4UL);
++}
++#endif
++
+ /** Current process ID */
+ #define DRM_CURRENTPID			task_pid_nr(current)
+ #define DRM_SUSER(p)			capable(CAP_SYS_ADMIN)
+@@ -23,6 +36,12 @@
+ /** Write a dword into a MMIO region */
+ #define DRM_WRITE32(map, offset, val)	writel(val, ((void __iomem *)(map)->handle) + (offset))
+ /** Read memory barrier */
++
++/** Read a qword from a MMIO region - be careful using these unless you really understand them */
++#define DRM_READ64(map, offset)		readq(((void __iomem *)(map)->handle) + (offset))
++/** Write a qword into a MMIO region */
++#define DRM_WRITE64(map, offset, val)	writeq(val, ((void __iomem *)(map)->handle) + (offset))
++
+ #define DRM_READMEMORYBARRIER()		rmb()
+ /** Write memory barrier */
+ #define DRM_WRITEMEMORYBARRIER()	wmb()
+diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h
+index 5165f24..c2fd3c5 100644
+--- a/include/drm/drm_pciids.h
++++ b/include/drm/drm_pciids.h
+@@ -239,10 +239,121 @@
+ 	{0x1002, 0x7835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ 	{0x1002, 0x791e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
+ 	{0x1002, 0x791f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
++	{0x1002, 0x793f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS600|RADEON_IS_IGP|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x7941, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS600|RADEON_IS_IGP|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x7942, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS600|RADEON_IS_IGP|RADEON_NEW_MEMMAP}, \
+ 	{0x1002, 0x796c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
+ 	{0x1002, 0x796d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
+ 	{0x1002, 0x796e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
+ 	{0x1002, 0x796f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
++	{0x1002, 0x9400, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9401, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9402, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9403, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x940A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x940B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x940F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9441, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9442, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9444, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9446, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x944A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x944B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x944C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x944E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9450, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9452, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9456, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x945A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x945B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x946A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x946B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x947A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x947B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9480, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9487, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9488, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9489, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x948F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9490, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9491, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9498, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x949C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x949E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x949F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV730|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x94C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x94C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x94C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x94C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x94C5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x94C6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x94C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x94C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x94C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x94CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x94CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x94CD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV610|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9501, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9504, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9505, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9506, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9507, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9508, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9509, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x950F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9511, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9515, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9517, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9519, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV670|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9540, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9541, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9542, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x954E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x954F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9552, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9553, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9555, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV710|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9580, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9581, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9583, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9586, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9587, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9588, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9589, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x958A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x958B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x958C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x958D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x958E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x958F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV630|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9590, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9591, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9593, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9595, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9596, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9597, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9598, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9599, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x959B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV635|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x95C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x95C5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x95C6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x95C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x95C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x95C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x95C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x95CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x95CD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x95CE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x95CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV620|RADEON_NEW_MEMMAP}, \
++	{0x1002, 0x9610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
++	{0x1002, 0x9611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
++	{0x1002, 0x9612, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
++	{0x1002, 0x9613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
++	{0x1002, 0x9614, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS780|RADEON_NEW_MEMMAP|RADEON_IS_IGP}, \
+ 	{0, 0, 0}
+ 
+ #define r128_PCI_IDS \
+diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h
+index 73ff51f..937a275 100644
+--- a/include/drm/radeon_drm.h
++++ b/include/drm/radeon_drm.h
+@@ -304,6 +304,8 @@ typedef union {
+ 
+ #define RADEON_SCRATCH_REG_OFFSET	32
+ 
++#define R600_SCRATCH_REG_OFFSET         256
++
+ #define RADEON_NR_SAREA_CLIPRECTS	12
+ 
+ /* There are 2 heaps (local/GART).  Each region within a heap is a
+@@ -526,7 +528,8 @@ typedef struct drm_radeon_init {
+ 		RADEON_INIT_CP = 0x01,
+ 		RADEON_CLEANUP_CP = 0x02,
+ 		RADEON_INIT_R200_CP = 0x03,
+-		RADEON_INIT_R300_CP = 0x04
++		RADEON_INIT_R300_CP = 0x04,
++		RADEON_INIT_R600_CP = 0x05
+ 	} func;
+ 	unsigned long sarea_priv_offset;
+ 	int is_pci;




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