rpms/kernel/F-13 drm-i915-fix-non-ironlake-965-class-crashes.patch, NONE, 1.1 drm-i915-use-pipe_control-instruction-on-ironlake-and-sandy-bridge.patch, NONE, 1.1 patch-2.6.33.5.bz2.sign, NONE, 1.1 .cvsignore, 1.1177, 1.1178 kernel.spec, 1.2047, 1.2048 linux-2.6-upstream-reverts.patch, 1.10, 1.11 linux-2.6-utrace.patch, 1.123, 1.124 sources, 1.1136, 1.1137 upstream, 1.1049, 1.1050 btrfs-check-for-read-permission-on-src-file-in-clone-ioctl.patch, 1.1, NONE iwlwifi_-check-for-aggregation-frame-and-queue.patch, 1.1, NONE iwlwifi_-clear-all-the-stop_queue-flag-after-load-firmware.patch, 1.1, NONE patch-2.6.33.4.bz2.sign, 1.1, NONE revert-ath9k_-fix-lockdep-warning-when-unloading-module.patch, 1.1, NONE
Chuck Ebbert
cebbert at fedoraproject.org
Thu May 27 01:37:58 UTC 2010
Author: cebbert
Update of /cvs/pkgs/rpms/kernel/F-13
In directory cvs01.phx2.fedoraproject.org:/tmp/cvs-serv15485
Modified Files:
.cvsignore kernel.spec linux-2.6-upstream-reverts.patch
linux-2.6-utrace.patch sources upstream
Added Files:
drm-i915-fix-non-ironlake-965-class-crashes.patch
drm-i915-use-pipe_control-instruction-on-ironlake-and-sandy-bridge.patch
patch-2.6.33.5.bz2.sign
Removed Files:
btrfs-check-for-read-permission-on-src-file-in-clone-ioctl.patch
iwlwifi_-check-for-aggregation-frame-and-queue.patch
iwlwifi_-clear-all-the-stop_queue-flag-after-load-firmware.patch
patch-2.6.33.4.bz2.sign
revert-ath9k_-fix-lockdep-warning-when-unloading-module.patch
Log Message:
Linux 2.6.33.5
Drop patches merged in -stable:
iwlwifi_-check-for-aggregation-frame-and-queue.patch
iwlwifi_-clear-all-the-stop_queue-flag-after-load-firmware.patch
revert-ath9k_-fix-lockdep-warning-when-unloading-module.patch
btrfs-check-for-read-permission-on-src-file-in-clone-ioctl.patch
Revert drm patch already in F-13: drm-i915-disable-fbc-on-915gm-and-945gm.patch
Apply DRM patches from -stable on top of F-13 DRM updates:
drm-i915-use-pipe_control-instruction-on-ironlake-and-sandy-bridge.patch
drm-i915-fix-non-ironlake-965-class-crashes.patch
drm-i915-fix-non-ironlake-965-class-crashes.patch:
i915_gem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- NEW FILE drm-i915-fix-non-ironlake-965-class-crashes.patch ---
>From 1918ad77f7f908ed67cf37c505c6ad4ac52f1ecf Mon Sep 17 00:00:00 2001
From: Jesse Barnes <jbarnes at virtuousgeek.org>
Date: Fri, 23 Apr 2010 09:32:23 -0700
Subject: drm/i915: fix non-Ironlake 965 class crashes
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
From: Jesse Barnes <jbarnes at virtuousgeek.org>
commit 1918ad77f7f908ed67cf37c505c6ad4ac52f1ecf upstream.
My PIPE_CONTROL fix (just sent via Eric's tree) was buggy; I was
testing a whole set of patches together and missed a conversion to the
new HAS_PIPE_CONTROL macro, which will cause breakage on non-Ironlake
965 class chips. Fortunately, the fix is trivial and has been tested.
Be sure to use the HAS_PIPE_CONTROL macro in i915_get_gem_seqno, or
we'll end up reading the wrong graphics memory, likely causing hangs,
crashes, or worse.
Reported-by: Zdenek Kabelac <zdenek.kabelac at gmail.com>
Reported-by: Toralf Förster <toralf.foerster at gmx.de>
Tested-by: Toralf Förster <toralf.foerster at gmx.de>
Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
Signed-off-by: Linus Torvalds <torvalds at linux-foundation.org>
Signed-off-by: Greg Kroah-Hartman <gregkh at suse.de>
---
drivers/gpu/drm/i915/i915_gem.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1785,7 +1785,7 @@ i915_get_gem_seqno(struct drm_device *de
{
drm_i915_private_t *dev_priv = dev->dev_private;
- if (IS_I965G(dev))
+ if (HAS_PIPE_CONTROL(dev))
return ((volatile u32 *)(dev_priv->seqno_page))[0];
else
return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
drm-i915-use-pipe_control-instruction-on-ironlake-and-sandy-bridge.patch:
i915_drv.h | 4 +
i915_gem.c | 145 +++++++++++++++++++++++++++++++++++++++++++++++++++++++------
i915_irq.c | 8 +--
i915_reg.h | 11 ++++
4 files changed, 152 insertions(+), 16 deletions(-)
--- NEW FILE drm-i915-use-pipe_control-instruction-on-ironlake-and-sandy-bridge.patch ---
>From e552eb7038a36d9b18860f525aa02875e313fe16 Mon Sep 17 00:00:00 2001
From: Jesse Barnes <jbarnes at virtuousgeek.org>
Date: Wed, 21 Apr 2010 11:39:23 -0700
Subject: drm/i915: use PIPE_CONTROL instruction on Ironlake and Sandy Bridge
From: Jesse Barnes <jbarnes at virtuousgeek.org>
commit e552eb7038a36d9b18860f525aa02875e313fe16 upstream.
Since 965, the hardware has supported the PIPE_CONTROL command, which
provides fine grained GPU cache flushing control. On recent chipsets,
this instruction is required for reliable interrupt and sequence number
reporting in the driver.
So add support for this instruction, including workarounds, on Ironlake
and Sandy Bridge hardware.
https://bugs.freedesktop.org/show_bug.cgi?id=27108
Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
Tested-by: Chris Wilson <chris at chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric at anholt.net>
Signed-off-by: Greg Kroah-Hartman <gregkh at suse.de>
---
drivers/gpu/drm/i915/i915_drv.h | 4 +
drivers/gpu/drm/i915/i915_gem.c | 145 ++++++++++++++++++++++++++++++++++++----
drivers/gpu/drm/i915/i915_irq.c | 8 +-
drivers/gpu/drm/i915/i915_reg.h | 11 +++
4 files changed, 152 insertions(+), 16 deletions(-)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -206,11 +206,14 @@ typedef struct drm_i915_private {
drm_dma_handle_t *status_page_dmah;
void *hw_status_page;
+ void *seqno_page;
dma_addr_t dma_status_page;
uint32_t counter;
unsigned int status_gfx_addr;
+ unsigned int seqno_gfx_addr;
drm_local_map_t hws_map;
struct drm_gem_object *hws_obj;
+ struct drm_gem_object *seqno_obj;
struct drm_gem_object *pwrctx;
struct resource mch_res;
@@ -1090,6 +1093,7 @@ extern int i915_wait_ring(struct drm_dev
#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
+#define HAS_PIPE_CONTROL(dev) (IS_IRONLAKE(dev) || IS_GEN6(dev))
#define PRIMARY_RINGBUFFER_SIZE (128*1024)
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -1559,6 +1559,13 @@ i915_gem_object_move_to_inactive(struct
i915_verify_inactive(dev, __FILE__, __LINE__);
}
+#define PIPE_CONTROL_FLUSH(addr) \
+ OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | \
+ PIPE_CONTROL_DEPTH_STALL); \
+ OUT_RING(addr | PIPE_CONTROL_GLOBAL_GTT); \
+ OUT_RING(0); \
+ OUT_RING(0); \
+
/**
* Creates a new sequence number, emitting a write of it to the status page
* plus an interrupt, which will trigger i915_user_interrupt_handler.
@@ -1593,13 +1600,47 @@ i915_add_request(struct drm_device *dev,
if (dev_priv->mm.next_gem_seqno == 0)
dev_priv->mm.next_gem_seqno++;
- BEGIN_LP_RING(4);
- OUT_RING(MI_STORE_DWORD_INDEX);
- OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
- OUT_RING(seqno);
+ if (HAS_PIPE_CONTROL(dev)) {
+ u32 scratch_addr = dev_priv->seqno_gfx_addr + 128;
- OUT_RING(MI_USER_INTERRUPT);
- ADVANCE_LP_RING();
+ /*
+ * Workaround qword write incoherence by flushing the
+ * PIPE_NOTIFY buffers out to memory before requesting
+ * an interrupt.
+ */
+ BEGIN_LP_RING(32);
+ OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
+ PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH);
+ OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
+ OUT_RING(seqno);
+ OUT_RING(0);
+ PIPE_CONTROL_FLUSH(scratch_addr);
+ scratch_addr += 128; /* write to separate cachelines */
+ PIPE_CONTROL_FLUSH(scratch_addr);
+ scratch_addr += 128;
+ PIPE_CONTROL_FLUSH(scratch_addr);
+ scratch_addr += 128;
+ PIPE_CONTROL_FLUSH(scratch_addr);
+ scratch_addr += 128;
+ PIPE_CONTROL_FLUSH(scratch_addr);
+ scratch_addr += 128;
+ PIPE_CONTROL_FLUSH(scratch_addr);
+ OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
+ PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH |
+ PIPE_CONTROL_NOTIFY);
+ OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
+ OUT_RING(seqno);
+ OUT_RING(0);
+ ADVANCE_LP_RING();
+ } else {
+ BEGIN_LP_RING(4);
+ OUT_RING(MI_STORE_DWORD_INDEX);
+ OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
+ OUT_RING(seqno);
+
+ OUT_RING(MI_USER_INTERRUPT);
+ ADVANCE_LP_RING();
+ }
DRM_DEBUG_DRIVER("%d\n", seqno);
@@ -1744,7 +1785,10 @@ i915_get_gem_seqno(struct drm_device *de
{
drm_i915_private_t *dev_priv = dev->dev_private;
- return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
+ if (IS_I965G(dev))
+ return ((volatile u32 *)(dev_priv->seqno_page))[0];
+ else
+ return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
}
/**
@@ -4576,6 +4620,49 @@ i915_gem_idle(struct drm_device *dev)
return 0;
}
+/*
+ * 965+ support PIPE_CONTROL commands, which provide finer grained control
+ * over cache flushing.
+ */
+static int
+i915_gem_init_pipe_control(struct drm_device *dev)
+{
+ drm_i915_private_t *dev_priv = dev->dev_private;
+ struct drm_gem_object *obj;
+ struct drm_i915_gem_object *obj_priv;
+ int ret;
+
+ obj = drm_gem_object_alloc(dev, 4096);
+ if (obj == NULL) {
+ DRM_ERROR("Failed to allocate seqno page\n");
+ ret = -ENOMEM;
+ goto err;
+ }
+ obj_priv = obj->driver_private;
+ obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
+
+ ret = i915_gem_object_pin(obj, 4096);
+ if (ret)
+ goto err_unref;
+
+ dev_priv->seqno_gfx_addr = obj_priv->gtt_offset;
+ dev_priv->seqno_page = kmap(obj_priv->pages[0]);
+ if (dev_priv->seqno_page == NULL)
+ goto err_unpin;
+
+ dev_priv->seqno_obj = obj;
+ memset(dev_priv->seqno_page, 0, PAGE_SIZE);
+
+ return 0;
+
+err_unpin:
+ i915_gem_object_unpin(obj);
+err_unref:
+ drm_gem_object_unreference(obj);
+err:
+ return ret;
+}
+
static int
i915_gem_init_hws(struct drm_device *dev)
{
@@ -4593,7 +4680,8 @@ i915_gem_init_hws(struct drm_device *dev
obj = drm_gem_object_alloc(dev, 4096);
if (obj == NULL) {
DRM_ERROR("Failed to allocate status page\n");
- return -ENOMEM;
+ ret = -ENOMEM;
+ goto err;
}
obj_priv = to_intel_bo(obj);
obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
@@ -4601,7 +4689,7 @@ i915_gem_init_hws(struct drm_device *dev
ret = i915_gem_object_pin(obj, 4096);
if (ret != 0) {
drm_gem_object_unreference(obj);
- return ret;
+ goto err_unref;
}
dev_priv->status_gfx_addr = obj_priv->gtt_offset;
@@ -4610,10 +4698,16 @@ i915_gem_init_hws(struct drm_device *dev
if (dev_priv->hw_status_page == NULL) {
DRM_ERROR("Failed to map status page.\n");
memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
- i915_gem_object_unpin(obj);
- drm_gem_object_unreference(obj);
- return -EINVAL;
+ ret = -EINVAL;
+ goto err_unpin;
}
+
+ if (HAS_PIPE_CONTROL(dev)) {
+ ret = i915_gem_init_pipe_control(dev);
+ if (ret)
+ goto err_unpin;
+ }
+
dev_priv->hws_obj = obj;
memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
@@ -4621,6 +4715,30 @@ i915_gem_init_hws(struct drm_device *dev
DRM_DEBUG_DRIVER("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
return 0;
+
+err_unpin:
+ i915_gem_object_unpin(obj);
+err_unref:
+ drm_gem_object_unreference(obj);
+err:
+ return 0;
+}
+
+static void
+i915_gem_cleanup_pipe_control(struct drm_device *dev)
+{
+ drm_i915_private_t *dev_priv = dev->dev_private;
+ struct drm_gem_object *obj;
+ struct drm_i915_gem_object *obj_priv;
+
+ obj = dev_priv->seqno_obj;
+ obj_priv = obj->driver_private;
+ kunmap(obj_priv->pages[0]);
+ i915_gem_object_unpin(obj);
+ drm_gem_object_unreference(obj);
+ dev_priv->seqno_obj = NULL;
+
+ dev_priv->seqno_page = NULL;
}
static void
@@ -4644,6 +4762,9 @@ i915_gem_cleanup_hws(struct drm_device *
memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
dev_priv->hw_status_page = NULL;
+ if (HAS_PIPE_CONTROL(dev))
+ i915_gem_cleanup_pipe_control(dev);
+
/* Write high address into HWS_PGA when disabling. */
I915_WRITE(HWS_PGA, 0x1ffff000);
}
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -297,7 +297,7 @@ irqreturn_t ironlake_irq_handler(struct
READ_BREADCRUMB(dev_priv);
}
- if (gt_iir & GT_USER_INTERRUPT) {
+ if (gt_iir & GT_PIPE_NOTIFY) {
u32 seqno = i915_get_gem_seqno(dev);
dev_priv->mm.irq_gem_seqno = seqno;
trace_i915_gem_request_complete(dev, seqno);
@@ -738,7 +738,7 @@ void i915_user_irq_get(struct drm_device
spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) {
if (HAS_PCH_SPLIT(dev))
- ironlake_enable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
+ ironlake_enable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
else
i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
}
@@ -754,7 +754,7 @@ void i915_user_irq_put(struct drm_device
BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
if (HAS_PCH_SPLIT(dev))
- ironlake_disable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
+ ironlake_disable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
else
i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
}
@@ -1034,7 +1034,7 @@ static int ironlake_irq_postinstall(stru
/* enable kind of interrupts always enabled */
u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
- u32 render_mask = GT_USER_INTERRUPT;
+ u32 render_mask = GT_PIPE_NOTIFY;
u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -210,6 +210,16 @@
#define ASYNC_FLIP (1<<22)
#define DISPLAY_PLANE_A (0<<20)
#define DISPLAY_PLANE_B (1<<20)
+#define GFX_OP_PIPE_CONTROL ((0x3<<29)|(0x3<<27)|(0x2<<24)|2)
+#define PIPE_CONTROL_QW_WRITE (1<<14)
+#define PIPE_CONTROL_DEPTH_STALL (1<<13)
+#define PIPE_CONTROL_WC_FLUSH (1<<12)
+#define PIPE_CONTROL_IS_FLUSH (1<<11) /* MBZ on Ironlake */
+#define PIPE_CONTROL_TC_FLUSH (1<<10) /* GM45+ only */
+#define PIPE_CONTROL_ISP_DIS (1<<9)
+#define PIPE_CONTROL_NOTIFY (1<<8)
+#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
+#define PIPE_CONTROL_STALL_EN (1<<1) /* in addr word, Ironlake+ only */
/*
* Fence registers
@@ -2111,6 +2121,7 @@
#define DEIER 0x4400c
/* GT interrupt */
+#define GT_PIPE_NOTIFY (1 << 4)
#define GT_SYNC_STATUS (1 << 2)
#define GT_USER_INTERRUPT (1 << 0)
--- NEW FILE patch-2.6.33.5.bz2.sign ---
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.9 (GNU/Linux)
Comment: See http://www.kernel.org/signature.html for info
iD8DBQBL/Z3cyGugalF9Dw4RAvPDAJ9pR9ZEJFh3ZnoMvsOXE9Vz7CVKCQCghmui
raEVqS9BBV+fw12yUHqepjc=
=yj1H
-----END PGP SIGNATURE-----
Index: .cvsignore
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/F-13/.cvsignore,v
retrieving revision 1.1177
retrieving revision 1.1178
diff -u -p -r1.1177 -r1.1178
--- .cvsignore 12 May 2010 23:39:18 -0000 1.1177
+++ .cvsignore 27 May 2010 01:37:50 -0000 1.1178
@@ -5,4 +5,4 @@ kernel-2.6.*.config
temp-*
kernel-2.6.33
linux-2.6.33.tar.bz2
-patch-2.6.33.4.bz2
+patch-2.6.33.5.bz2
Index: kernel.spec
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/F-13/kernel.spec,v
retrieving revision 1.2047
retrieving revision 1.2048
diff -u -p -r1.2047 -r1.2048
--- kernel.spec 27 May 2010 00:25:54 -0000 1.2047
+++ kernel.spec 27 May 2010 01:37:52 -0000 1.2048
@@ -61,7 +61,7 @@ Summary: The Linux kernel
%if 0%{?released_kernel}
# Do we have a -stable update to apply?
-%define stable_update 4
+%define stable_update 5
# Is it a -stable RC?
%define stable_rc 0
# Set rpm version accordingly
@@ -745,6 +745,9 @@ Patch1828: drm-intel-gen5-dither.patch
# thanks for the untested sdvo rework guys
Patch1829: drm-intel-sdvo-fix.patch
Patch1830: drm-intel-sdvo-fix-2.patch
+# from 2.6.33.5
+Patch1840: drm-i915-use-pipe_control-instruction-on-ironlake-and-sandy-bridge.patch
+Patch1841: drm-i915-fix-non-ironlake-965-class-crashes.patch
Patch2100: linux-2.6-phylib-autoload.patch
@@ -809,8 +812,6 @@ Patch12103: linux-2.6-p54pci.patch
Patch12200: acpi-ec-add-delay-before-write.patch
# patches from Intel to address intermittent firmware failures with iwlagn
-Patch12401: iwlwifi_-check-for-aggregation-frame-and-queue.patch
-Patch12403: iwlwifi_-clear-all-the-stop_queue-flag-after-load-firmware.patch
Patch12404: iwlwifi_-add-function-to-reset_tune-radio-if-needed.patch
Patch12405: iwlwifi_-Logic-to-control-how-frequent-radio-should-be-reset-if-needed.patch
Patch12406: iwlwifi_-Tune-radio-to-prevent-unexpected-behavior.patch
@@ -827,9 +828,6 @@ Patch12416: iwlwifi_-iwl_good_ack_health
# fix possible corruption with ssd
Patch12700: ext4-issue-discard-operation-before-releasing-blocks.patch
-# Revert "ath9k: fix lockdep warning when unloading module"
-Patch12800: revert-ath9k_-fix-lockdep-warning-when-unloading-module.patch
-
Patch12820: ibmvscsi-fix-DMA-API-misuse.patch
Patch12830: disable-i8042-check-on-apple-mac.patch
@@ -842,9 +840,6 @@ Patch12850: crypto-aesni-kill-module_ali
# automatically mount debugfs when perf needs it
Patch12851: perf-mount-debugfs-automatically.patch
-# upstream 5dc6416414fb3ec6e2825fd4d20c8bf1d7fe0395 (#593226)
-Patch12900: btrfs-check-for-read-permission-on-src-file-in-clone-ioctl.patch
-
# iwlwifi: fix scan races
Patch12910: iwlwifi-fix-scan-races.patch
# iwlwifi: fix internal scan race
@@ -1460,6 +1455,9 @@ ApplyPatch linux-2.6-intel-iommu-igfx.pa
ApplyPatch drm-intel-gen5-dither.patch
ApplyPatch drm-intel-sdvo-fix.patch
ApplyPatch drm-intel-sdvo-fix-2.patch
+# from 2.6.33.5
+ApplyPatch drm-i915-use-pipe_control-instruction-on-ironlake-and-sandy-bridge.patch
+ApplyPatch drm-i915-fix-non-ironlake-965-class-crashes.patch
ApplyPatch linux-2.6-phylib-autoload.patch
@@ -1503,8 +1501,6 @@ ApplyPatch iwlwifi-reset-card-during-pro
ApplyPatch linux-2.6-p54pci.patch
# patches from Intel to address intermittent firmware failures with iwlagn
-ApplyPatch iwlwifi_-check-for-aggregation-frame-and-queue.patch
-ApplyPatch iwlwifi_-clear-all-the-stop_queue-flag-after-load-firmware.patch
ApplyPatch iwlwifi_-add-function-to-reset_tune-radio-if-needed.patch
ApplyPatch iwlwifi_-Logic-to-control-how-frequent-radio-should-be-reset-if-needed.patch
ApplyPatch iwlwifi_-Tune-radio-to-prevent-unexpected-behavior.patch
@@ -1521,9 +1517,6 @@ ApplyPatch iwlwifi_-iwl_good_ack_health-
# fix possible corruption with ssd
ApplyPatch ext4-issue-discard-operation-before-releasing-blocks.patch
-# Revert "ath9k: fix lockdep warning when unloading module"
-ApplyPatch revert-ath9k_-fix-lockdep-warning-when-unloading-module.patch
-
ApplyPatch ibmvscsi-fix-DMA-API-misuse.patch
ApplyPatch disable-i8042-check-on-apple-mac.patch
@@ -1536,9 +1529,6 @@ ApplyPatch crypto-aesni-kill-module_alia
# automagically mount debugfs for perf
ApplyPatch perf-mount-debugfs-automatically.patch
-# upstream 5dc6416414fb3ec6e2825fd4d20c8bf1d7fe0395 (#593226)
-ApplyPatch btrfs-check-for-read-permission-on-src-file-in-clone-ioctl.patch
-
# iwlwifi: fix scan races
ApplyPatch iwlwifi-fix-scan-races.patch
# iwlwifi: fix internal scan race
@@ -2195,6 +2185,18 @@ fi
# and build.
%changelog
+* Wed May 27 2010 Chuck Ebbert <cebbert at redhat.com> 2.6.33.5-111
+- Linux 2.6.33.5
+- Drop patches merged in -stable:
+ iwlwifi_-check-for-aggregation-frame-and-queue.patch
+ iwlwifi_-clear-all-the-stop_queue-flag-after-load-firmware.patch
+ revert-ath9k_-fix-lockdep-warning-when-unloading-module.patch
+ btrfs-check-for-read-permission-on-src-file-in-clone-ioctl.patch
+- Revert drm patch already in F-13: drm-i915-disable-fbc-on-915gm-and-945gm.patch
+- Apply DRM patches from -stable on top of F-13 DRM updates:
+ drm-i915-use-pipe_control-instruction-on-ironlake-and-sandy-bridge.patch
+ drm-i915-fix-non-ironlake-965-class-crashes.patch
+
* Thu May 27 2010 Ben Skeggs <bskeggs at redhat.com>
- drm-nouveau-updates.patch: add nv50 gpio fix (rh#582621)
linux-2.6-upstream-reverts.patch:
b/drivers/pci/pci.c | 43 ++++-----
drivers/gpu/drm/drm_crtc_helper.c | 1
drivers/gpu/drm/drm_edid.c | 11 --
drivers/gpu/drm/drm_fops.c | 16 +--
drivers/gpu/drm/i915/i915_debugfs.c | 2
drivers/gpu/drm/i915/i915_dma.c | 16 ++-
drivers/gpu/drm/i915/i915_drv.c | 4
drivers/gpu/drm/i915/i915_drv.h | 30 ++++++
drivers/gpu/drm/i915/i915_gem.c | 155 ++++++++++++++++++++++++++++++---
drivers/gpu/drm/i915/i915_gem_tiling.c | 24 ++---
drivers/gpu/drm/i915/i915_irq.c | 26 ++---
drivers/gpu/drm/i915/i915_reg.h | 13 ++
drivers/gpu/drm/i915/intel_bios.c | 3
drivers/gpu/drm/i915/intel_crt.c | 14 +-
drivers/gpu/drm/i915/intel_display.c | 58 ++++++------
drivers/gpu/drm/i915/intel_lvds.c | 2
drivers/gpu/drm/i915/intel_overlay.c | 2
drivers/gpu/drm/radeon/rs600.c | 2
drivers/media/video/gspca/mr97310a.c | 6 +
drivers/usb/serial/qcserial.c | 29 ++++++
include/drm/drm_pciids.h | 1
21 files changed, 328 insertions(+), 130 deletions(-)
Index: linux-2.6-upstream-reverts.patch
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/F-13/linux-2.6-upstream-reverts.patch,v
retrieving revision 1.10
retrieving revision 1.11
diff -u -p -r1.10 -r1.11
--- linux-2.6-upstream-reverts.patch 12 May 2010 23:39:21 -0000 1.10
+++ linux-2.6-upstream-reverts.patch 27 May 2010 01:37:53 -0000 1.11
@@ -1,3 +1,432 @@
+From 8d06a1e1e9c69244f08beb7d17146483f9dcd120 Mon Sep 17 00:00:00 2001
+From: Robert Hooker <sarvatt at ubuntu.com>
+Date: Fri, 19 Mar 2010 15:13:27 -0400
+Subject: drm/i915: Disable FBC on 915GM and 945GM.
+
+From: Robert Hooker <sarvatt at ubuntu.com>
+
+commit 8d06a1e1e9c69244f08beb7d17146483f9dcd120 upstream.
+
+It is causing hangs after a suspend/resume cycle with the default
+powersave=1 module option on these chipsets since 2.6.32-rc.
+
+BugLink: http://bugs.launchpad.net/bugs/492392
+Signed-off-by: Robert Hooker <sarvatt at ubuntu.com>
+Acked-by: Jesse Barnes <jbarnes at virtuousgeek.org>
+Signed-off-by: Eric Anholt <eric at anholt.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh at suse.de>
+
+---
+ drivers/gpu/drm/i915/i915_drv.c | 4 ++--
+ drivers/gpu/drm/i915/intel_display.c | 2 +-
+ 2 files changed, 3 insertions(+), 3 deletions(-)
+
+--- a/drivers/gpu/drm/i915/i915_drv.c
++++ b/drivers/gpu/drm/i915/i915_drv.c
+@@ -79,14 +79,14 @@ const static struct intel_device_info in
+ .is_i915g = 1, .is_i9xx = 1, .cursor_needs_physical = 1,
+ };
+ const static struct intel_device_info intel_i915gm_info = {
+- .is_i9xx = 1, .is_mobile = 1, .has_fbc = 1,
++ .is_i9xx = 1, .is_mobile = 1,
+ .cursor_needs_physical = 1,
+ };
+ const static struct intel_device_info intel_i945g_info = {
+ .is_i9xx = 1, .has_hotplug = 1, .cursor_needs_physical = 1,
+ };
+ const static struct intel_device_info intel_i945gm_info = {
+- .is_i945gm = 1, .is_i9xx = 1, .is_mobile = 1, .has_fbc = 1,
++ .is_i945gm = 1, .is_i9xx = 1, .is_mobile = 1,
+ .has_hotplug = 1, .cursor_needs_physical = 1,
+ };
+
+--- a/drivers/gpu/drm/i915/intel_display.c
++++ b/drivers/gpu/drm/i915/intel_display.c
+@@ -4683,7 +4683,7 @@ static void intel_init_display(struct dr
+ dev_priv->display.fbc_enabled = g4x_fbc_enabled;
+ dev_priv->display.enable_fbc = g4x_enable_fbc;
+ dev_priv->display.disable_fbc = g4x_disable_fbc;
+- } else if (IS_I965GM(dev) || IS_I945GM(dev) || IS_I915GM(dev)) {
++ } else if (IS_I965GM(dev)) {
+ dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
+ dev_priv->display.enable_fbc = i8xx_enable_fbc;
+ dev_priv->display.disable_fbc = i8xx_disable_fbc;
+From 1918ad77f7f908ed67cf37c505c6ad4ac52f1ecf Mon Sep 17 00:00:00 2001
+From: Jesse Barnes <jbarnes at virtuousgeek.org>
+Date: Fri, 23 Apr 2010 09:32:23 -0700
+Subject: drm/i915: fix non-Ironlake 965 class crashes
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+From: Jesse Barnes <jbarnes at virtuousgeek.org>
+
+commit 1918ad77f7f908ed67cf37c505c6ad4ac52f1ecf upstream.
+
+My PIPE_CONTROL fix (just sent via Eric's tree) was buggy; I was
+testing a whole set of patches together and missed a conversion to the
+new HAS_PIPE_CONTROL macro, which will cause breakage on non-Ironlake
+965 class chips. Fortunately, the fix is trivial and has been tested.
+
+Be sure to use the HAS_PIPE_CONTROL macro in i915_get_gem_seqno, or
+we'll end up reading the wrong graphics memory, likely causing hangs,
+crashes, or worse.
+
+Reported-by: Zdenek Kabelac <zdenek.kabelac at gmail.com>
+Reported-by: Toralf Förster <toralf.foerster at gmx.de>
+Tested-by: Toralf Förster <toralf.foerster at gmx.de>
+Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
+Signed-off-by: Linus Torvalds <torvalds at linux-foundation.org>
+Signed-off-by: Greg Kroah-Hartman <gregkh at suse.de>
+
+---
+ drivers/gpu/drm/i915/i915_gem.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/i915/i915_gem.c
++++ b/drivers/gpu/drm/i915/i915_gem.c
+@@ -1785,7 +1785,7 @@ i915_get_gem_seqno(struct drm_device *de
+ {
+ drm_i915_private_t *dev_priv = dev->dev_private;
+
+- if (IS_I965G(dev))
++ if (HAS_PIPE_CONTROL(dev))
+ return ((volatile u32 *)(dev_priv->seqno_page))[0];
+ else
+ return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
+From e552eb7038a36d9b18860f525aa02875e313fe16 Mon Sep 17 00:00:00 2001
+From: Jesse Barnes <jbarnes at virtuousgeek.org>
+Date: Wed, 21 Apr 2010 11:39:23 -0700
+Subject: drm/i915: use PIPE_CONTROL instruction on Ironlake and Sandy Bridge
+
+From: Jesse Barnes <jbarnes at virtuousgeek.org>
+
+commit e552eb7038a36d9b18860f525aa02875e313fe16 upstream.
+
+Since 965, the hardware has supported the PIPE_CONTROL command, which
+provides fine grained GPU cache flushing control. On recent chipsets,
+this instruction is required for reliable interrupt and sequence number
+reporting in the driver.
+
+So add support for this instruction, including workarounds, on Ironlake
+and Sandy Bridge hardware.
+
+https://bugs.freedesktop.org/show_bug.cgi?id=27108
+
+Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
+Tested-by: Chris Wilson <chris at chris-wilson.co.uk>
+Signed-off-by: Eric Anholt <eric at anholt.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh at suse.de>
+
+---
+ drivers/gpu/drm/i915/i915_drv.h | 4 +
+ drivers/gpu/drm/i915/i915_gem.c | 145 ++++++++++++++++++++++++++++++++++++----
+ drivers/gpu/drm/i915/i915_irq.c | 8 +-
+ drivers/gpu/drm/i915/i915_reg.h | 11 +++
+ 4 files changed, 152 insertions(+), 16 deletions(-)
+
+--- a/drivers/gpu/drm/i915/i915_drv.h
++++ b/drivers/gpu/drm/i915/i915_drv.h
+@@ -206,11 +206,14 @@ typedef struct drm_i915_private {
+
+ drm_dma_handle_t *status_page_dmah;
+ void *hw_status_page;
++ void *seqno_page;
+ dma_addr_t dma_status_page;
+ uint32_t counter;
+ unsigned int status_gfx_addr;
++ unsigned int seqno_gfx_addr;
+ drm_local_map_t hws_map;
+ struct drm_gem_object *hws_obj;
++ struct drm_gem_object *seqno_obj;
+ struct drm_gem_object *pwrctx;
+
+ struct resource mch_res;
+@@ -1090,6 +1093,7 @@ extern int i915_wait_ring(struct drm_dev
+
+ #define HAS_PCH_SPLIT(dev) (IS_IRONLAKE(dev) || \
+ IS_GEN6(dev))
++#define HAS_PIPE_CONTROL(dev) (IS_IRONLAKE(dev) || IS_GEN6(dev))
+
+ #define PRIMARY_RINGBUFFER_SIZE (128*1024)
+
+--- a/drivers/gpu/drm/i915/i915_gem.c
++++ b/drivers/gpu/drm/i915/i915_gem.c
+@@ -1559,6 +1559,13 @@ i915_gem_object_move_to_inactive(struct
+ i915_verify_inactive(dev, __FILE__, __LINE__);
+ }
+
++#define PIPE_CONTROL_FLUSH(addr) \
++ OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | \
++ PIPE_CONTROL_DEPTH_STALL); \
++ OUT_RING(addr | PIPE_CONTROL_GLOBAL_GTT); \
++ OUT_RING(0); \
++ OUT_RING(0); \
++
+ /**
+ * Creates a new sequence number, emitting a write of it to the status page
+ * plus an interrupt, which will trigger i915_user_interrupt_handler.
+@@ -1593,13 +1600,47 @@ i915_add_request(struct drm_device *dev,
+ if (dev_priv->mm.next_gem_seqno == 0)
+ dev_priv->mm.next_gem_seqno++;
+
+- BEGIN_LP_RING(4);
+- OUT_RING(MI_STORE_DWORD_INDEX);
+- OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
+- OUT_RING(seqno);
++ if (HAS_PIPE_CONTROL(dev)) {
++ u32 scratch_addr = dev_priv->seqno_gfx_addr + 128;
+
+- OUT_RING(MI_USER_INTERRUPT);
+- ADVANCE_LP_RING();
++ /*
++ * Workaround qword write incoherence by flushing the
++ * PIPE_NOTIFY buffers out to memory before requesting
++ * an interrupt.
++ */
++ BEGIN_LP_RING(32);
++ OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
++ PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH);
++ OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
++ OUT_RING(seqno);
++ OUT_RING(0);
++ PIPE_CONTROL_FLUSH(scratch_addr);
++ scratch_addr += 128; /* write to separate cachelines */
++ PIPE_CONTROL_FLUSH(scratch_addr);
++ scratch_addr += 128;
++ PIPE_CONTROL_FLUSH(scratch_addr);
++ scratch_addr += 128;
++ PIPE_CONTROL_FLUSH(scratch_addr);
++ scratch_addr += 128;
++ PIPE_CONTROL_FLUSH(scratch_addr);
++ scratch_addr += 128;
++ PIPE_CONTROL_FLUSH(scratch_addr);
++ OUT_RING(GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
++ PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH |
++ PIPE_CONTROL_NOTIFY);
++ OUT_RING(dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
++ OUT_RING(seqno);
++ OUT_RING(0);
++ ADVANCE_LP_RING();
++ } else {
++ BEGIN_LP_RING(4);
++ OUT_RING(MI_STORE_DWORD_INDEX);
++ OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
++ OUT_RING(seqno);
++
++ OUT_RING(MI_USER_INTERRUPT);
++ ADVANCE_LP_RING();
++ }
+
+ DRM_DEBUG_DRIVER("%d\n", seqno);
+
+@@ -1744,7 +1785,10 @@ i915_get_gem_seqno(struct drm_device *de
+ {
+ drm_i915_private_t *dev_priv = dev->dev_private;
+
+- return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
++ if (IS_I965G(dev))
++ return ((volatile u32 *)(dev_priv->seqno_page))[0];
++ else
++ return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
+ }
+
+ /**
+@@ -4576,6 +4620,49 @@ i915_gem_idle(struct drm_device *dev)
+ return 0;
+ }
+
++/*
++ * 965+ support PIPE_CONTROL commands, which provide finer grained control
++ * over cache flushing.
++ */
++static int
++i915_gem_init_pipe_control(struct drm_device *dev)
++{
++ drm_i915_private_t *dev_priv = dev->dev_private;
++ struct drm_gem_object *obj;
++ struct drm_i915_gem_object *obj_priv;
++ int ret;
++
++ obj = drm_gem_object_alloc(dev, 4096);
++ if (obj == NULL) {
++ DRM_ERROR("Failed to allocate seqno page\n");
++ ret = -ENOMEM;
++ goto err;
++ }
++ obj_priv = obj->driver_private;
++ obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
++
++ ret = i915_gem_object_pin(obj, 4096);
++ if (ret)
++ goto err_unref;
++
++ dev_priv->seqno_gfx_addr = obj_priv->gtt_offset;
++ dev_priv->seqno_page = kmap(obj_priv->pages[0]);
++ if (dev_priv->seqno_page == NULL)
++ goto err_unpin;
++
++ dev_priv->seqno_obj = obj;
++ memset(dev_priv->seqno_page, 0, PAGE_SIZE);
++
++ return 0;
++
++err_unpin:
++ i915_gem_object_unpin(obj);
++err_unref:
++ drm_gem_object_unreference(obj);
++err:
++ return ret;
++}
++
+ static int
+ i915_gem_init_hws(struct drm_device *dev)
+ {
+@@ -4593,7 +4680,8 @@ i915_gem_init_hws(struct drm_device *dev
+ obj = drm_gem_object_alloc(dev, 4096);
+ if (obj == NULL) {
+ DRM_ERROR("Failed to allocate status page\n");
+- return -ENOMEM;
++ ret = -ENOMEM;
++ goto err;
+ }
+ obj_priv = obj->driver_private;
+ obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
+@@ -4601,7 +4689,7 @@ i915_gem_init_hws(struct drm_device *dev
+ ret = i915_gem_object_pin(obj, 4096);
+ if (ret != 0) {
+ drm_gem_object_unreference(obj);
+- return ret;
++ goto err_unref;
+ }
+
+ dev_priv->status_gfx_addr = obj_priv->gtt_offset;
+@@ -4610,10 +4698,16 @@ i915_gem_init_hws(struct drm_device *dev
+ if (dev_priv->hw_status_page == NULL) {
+ DRM_ERROR("Failed to map status page.\n");
+ memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
+- i915_gem_object_unpin(obj);
+- drm_gem_object_unreference(obj);
+- return -EINVAL;
++ ret = -EINVAL;
++ goto err_unpin;
+ }
++
++ if (HAS_PIPE_CONTROL(dev)) {
++ ret = i915_gem_init_pipe_control(dev);
++ if (ret)
++ goto err_unpin;
++ }
++
+ dev_priv->hws_obj = obj;
+ memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
+ I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
+@@ -4621,6 +4715,30 @@ i915_gem_init_hws(struct drm_device *dev
+ DRM_DEBUG_DRIVER("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
+
+ return 0;
++
++err_unpin:
++ i915_gem_object_unpin(obj);
++err_unref:
++ drm_gem_object_unreference(obj);
++err:
++ return 0;
++}
++
++static void
++i915_gem_cleanup_pipe_control(struct drm_device *dev)
++{
++ drm_i915_private_t *dev_priv = dev->dev_private;
++ struct drm_gem_object *obj;
++ struct drm_i915_gem_object *obj_priv;
++
++ obj = dev_priv->seqno_obj;
++ obj_priv = obj->driver_private;
++ kunmap(obj_priv->pages[0]);
++ i915_gem_object_unpin(obj);
++ drm_gem_object_unreference(obj);
++ dev_priv->seqno_obj = NULL;
++
++ dev_priv->seqno_page = NULL;
+ }
+
+ static void
+@@ -4644,6 +4762,9 @@ i915_gem_cleanup_hws(struct drm_device *
+ memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
+ dev_priv->hw_status_page = NULL;
+
++ if (HAS_PIPE_CONTROL(dev))
++ i915_gem_cleanup_pipe_control(dev);
++
+ /* Write high address into HWS_PGA when disabling. */
+ I915_WRITE(HWS_PGA, 0x1ffff000);
+ }
+--- a/drivers/gpu/drm/i915/i915_irq.c
++++ b/drivers/gpu/drm/i915/i915_irq.c
+@@ -297,7 +297,7 @@ irqreturn_t ironlake_irq_handler(struct
+ READ_BREADCRUMB(dev_priv);
+ }
+
+- if (gt_iir & GT_USER_INTERRUPT) {
++ if (gt_iir & GT_PIPE_NOTIFY) {
+ u32 seqno = i915_get_gem_seqno(dev);
+ dev_priv->mm.irq_gem_seqno = seqno;
+ trace_i915_gem_request_complete(dev, seqno);
+@@ -738,7 +738,7 @@ void i915_user_irq_get(struct drm_device
+ spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
+ if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1)) {
+ if (HAS_PCH_SPLIT(dev))
+- ironlake_enable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
++ ironlake_enable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
+ else
+ i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
+ }
+@@ -754,7 +754,7 @@ void i915_user_irq_put(struct drm_device
+ BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
+ if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0)) {
+ if (HAS_PCH_SPLIT(dev))
+- ironlake_disable_graphics_irq(dev_priv, GT_USER_INTERRUPT);
++ ironlake_disable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
+ else
+ i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
+ }
+@@ -1034,7 +1034,7 @@ static int ironlake_irq_postinstall(stru
+ /* enable kind of interrupts always enabled */
+ u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
+ DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
+- u32 render_mask = GT_USER_INTERRUPT;
++ u32 render_mask = GT_PIPE_NOTIFY;
+ u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG |
+ SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG;
+
+--- a/drivers/gpu/drm/i915/i915_reg.h
++++ b/drivers/gpu/drm/i915/i915_reg.h
+@@ -210,6 +210,16 @@
+ #define ASYNC_FLIP (1<<22)
+ #define DISPLAY_PLANE_A (0<<20)
+ #define DISPLAY_PLANE_B (1<<20)
++#define GFX_OP_PIPE_CONTROL ((0x3<<29)|(0x3<<27)|(0x2<<24)|2)
++#define PIPE_CONTROL_QW_WRITE (1<<14)
++#define PIPE_CONTROL_DEPTH_STALL (1<<13)
++#define PIPE_CONTROL_WC_FLUSH (1<<12)
++#define PIPE_CONTROL_IS_FLUSH (1<<11) /* MBZ on Ironlake */
++#define PIPE_CONTROL_TC_FLUSH (1<<10) /* GM45+ only */
++#define PIPE_CONTROL_ISP_DIS (1<<9)
++#define PIPE_CONTROL_NOTIFY (1<<8)
++#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
++#define PIPE_CONTROL_STALL_EN (1<<1) /* in addr word, Ironlake+ only */
+
+ /*
+ * Fence registers
+@@ -2111,6 +2121,7 @@
+ #define DEIER 0x4400c
+
+ /* GT interrupt */
++#define GT_PIPE_NOTIFY (1 << 4)
+ #define GT_SYNC_STATUS (1 << 2)
+ #define GT_USER_INTERRUPT (1 << 0)
+
From c36a2a6de59e4a141a68b7575de837d3b0bd96b3 Mon Sep 17 00:00:00 2001
From: Daniel Vetter <daniel.vetter at ffwll.ch>
Date: Sat, 17 Apr 2010 15:12:03 +0200
linux-2.6-utrace.patch:
Documentation/DocBook/Makefile | 2
Documentation/DocBook/utrace.tmpl | 590 +++++++++
fs/proc/array.c | 3
include/linux/sched.h | 5
include/linux/tracehook.h | 87 +
include/linux/utrace.h | 692 ++++++++++
init/Kconfig | 9
kernel/Makefile | 1
kernel/fork.c | 3
kernel/ptrace.c | 14
kernel/utrace.c | 2436 ++++++++++++++++++++++++++++++++++++++
11 files changed, 3840 insertions(+), 2 deletions(-)
Index: linux-2.6-utrace.patch
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/F-13/linux-2.6-utrace.patch,v
retrieving revision 1.123
retrieving revision 1.124
diff -u -p -r1.123 -r1.124
--- linux-2.6-utrace.patch 21 May 2010 22:41:00 -0000 1.123
+++ linux-2.6-utrace.patch 27 May 2010 01:37:54 -0000 1.124
@@ -656,9 +656,9 @@ index 13b5d07..cda9489 100644
#include <linux/ptrace.h>
#include <linux/tracehook.h>
+#include <linux/utrace.h>
- #include <linux/swapops.h>
#include <asm/pgtable.h>
+ #include <asm/processor.h>
@@ -194,6 +195,8 @@ static inline void task_state(struct seq
cred->uid, cred->euid, cred->suid, cred->fsuid,
cred->gid, cred->egid, cred->sgid, cred->fsgid);
Index: sources
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/F-13/sources,v
retrieving revision 1.1136
retrieving revision 1.1137
diff -u -p -r1.1136 -r1.1137
--- sources 12 May 2010 23:39:21 -0000 1.1136
+++ sources 27 May 2010 01:37:57 -0000 1.1137
@@ -1,2 +1,2 @@
c3883760b18d50e8d78819c54d579b00 linux-2.6.33.tar.bz2
-27ea162c4a508d368fad9c6e4530ee43 patch-2.6.33.4.bz2
+9711dce3141d9fd38e15bceadc20f9f4 patch-2.6.33.5.bz2
Index: upstream
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/F-13/upstream,v
retrieving revision 1.1049
retrieving revision 1.1050
diff -u -p -r1.1049 -r1.1050
--- upstream 12 May 2010 23:39:21 -0000 1.1049
+++ upstream 27 May 2010 01:37:57 -0000 1.1050
@@ -1,2 +1,2 @@
linux-2.6.33.tar.bz2
-patch-2.6.33.4.bz2
+patch-2.6.33.5.bz2
--- btrfs-check-for-read-permission-on-src-file-in-clone-ioctl.patch DELETED ---
--- iwlwifi_-check-for-aggregation-frame-and-queue.patch DELETED ---
--- iwlwifi_-clear-all-the-stop_queue-flag-after-load-firmware.patch DELETED ---
--- patch-2.6.33.4.bz2.sign DELETED ---
--- revert-ath9k_-fix-lockdep-warning-when-unloading-module.patch DELETED ---
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