The package rpms/yosys.git has added or updated architecture specific content in its
spec file (ExclusiveArch/ExcludeArch or %ifarch/%ifnarch) in commit(s):
https://src.fedoraproject.org/cgit/rpms/yosys.git/commit/?id=0e9054853de0....
Change:
+ExcludeArch: s390x
Thanks.
Full change:
============
commit 0e9054853de0d46251bd5d1670f6bfc405db8c5b
Author: Gabriel Somlo <gsomlo(a)gmail.com>
Date: Wed Mar 10 11:59:17 2021 -0500
excludearch s390x (BZ 1937362, 1937395)
diff --git a/.gitignore b/.gitignore
index d0956f1..d345406 100644
--- a/.gitignore
+++ b/.gitignore
@@ -4,3 +4,4 @@
/yosys-0.9.tar.gz
/yosys_0.9-1.debian.tar.xz
/yosys-9cdc6b5.tar.gz
+/yosys-26e01a6.tar.gz
diff --git a/sources b/sources
index 3a3a728..c343ae2 100644
--- a/sources
+++ b/sources
@@ -1,2 +1,2 @@
-SHA512 (yosys-9cdc6b5.tar.gz) =
3c7e1f2736d6291d07470dc4e6b312de2852934afe98880566290730d3da2d3e51425daf03ad529c45ea0f9dd7d2850ca6fd051f92e586ecf95d91a44042ffc2
+SHA512 (yosys-26e01a6.tar.gz) =
3c6b1927a2ea9ffbba9e9c9fcb79dd07968b3a1aabf970bc978bc3041c4fad0ddf5c2ac788dcc79bed89402ca76110460735284d1444be5e451c8e79c718773b
SHA512 (yosys_0.9-1.debian.tar.xz) =
d9df5637efc730b2b681daa8a5933803dba70dca5b31fe4ac13601032eccd9105c001563cf627fbdd2d4ebad8551f2647e882fbf107a7df98badb2d200e2b4dc
diff --git a/yosys.spec b/yosys.spec
index b7b8e25..7c05f3a 100644
--- a/yosys.spec
+++ b/yosys.spec
@@ -1,13 +1,13 @@
-%global commit0 9cdc6b5f2e416cd469a2480460986189f61b10a7
+%global commit0 26e01a67db4135196b1d25ed89e9e6ceb536f4e3
%global shortcommit0 %%(c=%%{commit0}; echo ${c:0:7})
-%global snapdate 20210307
+%global snapdate 20210310
%global __python %{__python3}
Name: yosys
Version: 0.9
-Release: 10.%{snapdate}git%{shortcommit0}%{?dist}
+Release: 11.%{snapdate}git%{shortcommit0}%{?dist}
Summary: Yosys Open SYnthesis Suite, including Verilog synthesizer
License: ISC and MIT
URL:
http://www.clifford.at/yosys/
@@ -53,6 +53,8 @@ Requires: %{name}-share = %{version}-%{release}
Requires: graphviz python-xdot
Requires: abc >= 1.01-9
+# abc use broken on all Big Endian CPUs, specifically s390x (see BZ 1937362, 1937395):
+ExcludeArch: s390x
%description
Yosys is a framework for Verilog RTL synthesis. It currently has
@@ -167,6 +169,9 @@ make test ABCEXTERNAL=%{_bindir}/abc SEED=314159265359
%changelog
+* Wed Mar 10 2021 Gabriel Somlo <gsomlo(a)gmail.com> - 0.9-11.20210310git26e01a6
+- exclude arch s390x (abc use broken on all Big Endian CPUs, see BZ 1937362, 1937395)
+
* Sun Mar 07 2021 Gabriel Somlo <gsomlo(a)gmail.com> - 0.9-10.20210307git9cdc6b5
- Switch to snapshots (releases are too infrequent w.r.t. development speed)