[I'm hoping not to make too many announcements about this, but this is
significant because I've finally reached a stage where other people
can pitch in.]
RISC-V is a new open processor architecture. The instruction set is
patent free and freely implementable, and implementations are
distributed under a BSD license. Wouldn't it be great to have open
source all the way down to the transistors?
There are some projects aiming to create RISC-V processors /
development boards. I will point to a couple of the more promising
Fedora/RISC-V is a project to bootstrap Fedora on RISC-V.
The plan to bootstrap Fedora/RISC-V is outlined in the README file
here (also attached to this email).
I have now reached Stage 4 in the bootstrapping process, which is
significant because it means everyone can help to rebuild source RPMs
All you will need is:
* Fedora 24
* fast x86_64 hardware
* experience with C / compilers / architectures
* time and patience, because our emulator is a bit slow :-(
To take this further, please join the IRC channel:
#fedora-riscv on FreeNode
Read the README.
git clone git://git.annexia.org/git/fedora-riscv.git
Read the Makefile carefully and compare it to the README to understand
the bootstrapping process.
Enable copr and install the development packages:
sudo dnf copr enable rjones/riscv
sudo dnf install riscv-isa-sim riscv-qemu riscv-pk riscv-gnu-toolchain
(These can also be built from source if you prefer.)
You can either run the Makefile steps to try to build everything from
source, or you can use the binary stage 3 disk image from:
Boot the disk image:
And start using rpmbuild. At this point it's a good idea to
chat with us on #fedora-riscv
Richard Jones, Virtualization Group, Red Hat http://people.redhat.com/~rjones
Read my programming and virtualization blog: http://rwmj.wordpress.com
libguestfs lets you edit virtual machines. Supports shell scripting,
bindings from many languages. http://libguestfs.org