#20: package myHDL
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Reporter: chitlesh | Owner: chitlesh
Type: task | Status: new
Priority: major | Milestone: Fedora 12
Component: FEL | Version: devel
Keywords: |
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Upstream was contacted to encourage them to package myHDL for FEL.
Upstream responded by saying he will ask his community.
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Ticket URL: <https://fedorahosted.org/fedora-electronic-lab/ticket/20>
Fedora Electronic Lab <https://fedorahosted.org/fedora-electronic-lab>
Design, Simulate and Program electronics.
Hi guys,
Have you ever heard about Pinguino[1]?
It is an Arduino like board based on Microchip PICs. It is aimed to
provide easy tools for usb communication.
Just to let you know that I have just started to package it (0.9 beta
5). Let me know if someone is already working on it...
I plan to speak about it and FEL during the "Solution Linux"[2] forum
held in May at Paris. There are around 10,000 visitors in 3 days.
[1] http://www.hackinglab.org/pinguino/index_pinguino.html
[2] http://fedoraproject.org/wiki/Solutions_Linux_2011
Regards,
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Kévin Raymond (shaiton)
GPG-Key: A5BCB3A2
Hi,
I wrote some verilog code and from this I generated an equivaltent
VHDL code using Icarus Verilog's VHDL code generator. vasy didn't take
this so I made some changes going by the errors it gave. The last time
I tried it, it gave a Segmentation fault. I ran the following
commands:
iverilog -t vhdl alu8.v -o alu8.vhdl
vasy -Vao alu8.vhdl
I have attached my verilog code and the code generated by Icarus (with
the changes I made). Is there something in the VHDL code that
shouldn't be there? Is there a way to get around this or fix it?
Thanks
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Ashwith J. Rego
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