#105: Package : Aeneas - 3D Monte Carlo Semiconductor Device Simulator
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Reporter: chitlesh | Owner: chitlesh
Type: task | Status: new
Priority: major | Milestone: EPEL-6
Component: TCAD | Version: devel
Keywords: monte_carlo |
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= phenomenon =
Missing a 3D Monte Carlo Semiconductor Device Simulator. We do have a 2D
Monte Carlo Semiconductor Device Simulator : Achimedes.
Aeneas fills this gap.
http://www.gnu.org/software/aeneas/
= background analysis =
It can take into account all the relevant quantum effects, thank to the
implementation of the Bohm effective potential method.
The physics and geometry of a general device is introduced by typing a
simple script, which makes, in this sense, Aeneas a powerfull tool for the
simulation of quite general semiconductor devices. Furthermore, it is
possible to simulate device of every shape covered by tetrahedra which
makes the choice of 3D shapes practically endless. This is the first world
simulator with the caracteristic of coupling MC transport to 3D tetrahedra
meshes.
= implementation recommendation =
Simple package to prepare.
--
Ticket URL: <https://fedorahosted.org/fedora-electronic-lab/ticket/105>
Free Electronic Lab <https://fedorahosted.org/fedora-electronic-lab>
Design, Simulate and Program electronics.
#32: package Fritzing (draft spec included)
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Reporter: chitlesh | Owner: chitlesh
Type: task | Status: new
Priority: major | Milestone: Fedora 12 'Constantine'
Component: PCB Layout | Version: 12
Keywords: |
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Fritzing will also interest the Education Spin.
It is rather impressive though for a new EDA software.
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Ticket URL: <https://fedorahosted.org/fedora-electronic-lab/ticket/32>
Fedora Electronic Lab <https://fedorahosted.org/fedora-electronic-lab>
Design, Simulate and Program electronics.
#102: Inclusion of Automatic Device Model Synthesizer (ADMS) to improve Verilog-
AMS support
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Reporter: chitlesh | Owner: chitlesh
Type: defect | Status: new
Priority: major | Milestone: Fedora 13
Component: ASIC | Version: devel
Keywords: verilog-ams |
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= bug description =
FEL lacks Verilog-AMS support
= bug analysis =
mot-adms provides an Automatic Device Model Synthesizer (ADMS) which turns
Verilog-A models into a C API for any simulator to understand and process
the behavioral description.
That said, the QUCS and ngspice packages currently available under the FEL
umbrella can be used to import Verilog-A description from admsXml's
outputs.
= fix recommendation =
- 1- package mot-adms
- 2- tweak FEL's QUCS to include *.xml
- 3- talk to ngspice's upstream to seek a possible plugin like behavioral
of adms usage for the user.
--
Ticket URL: <https://fedorahosted.org/fedora-electronic-lab/ticket/102>
Free Electronic Lab <https://fedorahosted.org/fedora-electronic-lab>
Design, Simulate and Program electronics.
#103: Develop a script which translates Modelsim.do file into a gtkwave tcl
script
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Reporter: chitlesh | Owner: akurnya(a)gmail.com
Type: task | Status: new
Priority: major | Milestone: EPEL-6
Component: FEL | Version: devel
Keywords: modelsim gtkwave |
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= bug description =
Many opencores projects use modelsim and provide modelsim *.do files, we
ought to provide a simple equivalent at least.
= fix recommendation =
create a Tcl script converts modelsim .do files into .do files which
GTKwave can understand. The idea in itself is very simple - Ensure that
GTKwave can read the same waves as Modelsim would do.
Thus you will need to create a Tcl script, which takes in[[BR]]
- as input a Modelsim .do file[[BR]]
- and output a Tcl script which GTKwave will read.
It is basically a script which renames Modelsim commands into GTKwave
commands. That's it.
== References ==
* see GTKwaves examples for a possible tcl script
--
Ticket URL: <https://fedorahosted.org/fedora-electronic-lab/ticket/103>
Free Electronic Lab <https://fedorahosted.org/fedora-electronic-lab>
Design, Simulate and Program electronics.