Draft SVP64 and SFFS OpenPOWER Foundation ISA Working Group RFCs
(please distribute widely to all FOSSHW Power-related mailing lists,
but reply to libre-soc-isa - many many thanks for patience and understanding)
the Libre-SOC Project's NLnet-funded work of the past three years
has reached the point where it's time to submit RFCs to the OpenPOWER
Foundation ISA Working Group, through its recently-established "External"
Contribution Process.
what has been developed thanks to NLnet funding is the biggest upgrade
to the Power ISA since Motorola's VLE Book of over 12 years ago: almost
100 new instructions, a large proportion of which have existed in other ISAs
in some cases for 15 years, others (bmask) synthesise an entire suite
of instructions (x86 TBM) into one instruction, and others are completely
new and innovative.
categories include bitmanipulation cryptography AV AI DCT/FFT GPU
Biginteger all as general-purpose instructions.
to get an idea of both the workload, opcode allocation, and the priorities,
a "summary" RFC has been created which will be submitted shortly, and
followed up (routinely) with updated versions keeping track of status.
this represents an opportunity for *everyone* interested in the future of the
Power ISA to both have the opportunity and also take responsibility for
defining its direction. this is a huge task!
https://ftp.libre-soc.org/opf_ext_rfc/ls012.pdf
questions comments feedback greatly appreciated - gentle reminder please
do utilise the libre-soc-isa mailing list so that the cc distribution
list is not
overwhelmed.
with thanks,
l.