Hi;
For anyone, but particularly Les H.
I have been re-reading some notes I have made on how DRAM works. As a result I have a couple of unanswered questions?
1) This question is for personal visualization purposes. I fully realize it makes no real difference on how DRAM works.
What is the most common arrangement of memory cells (??) within a memory stick. It seems to be proprietary information? I have seen schematics of two possibilities; a) with each stored bit side-by-side for the length of a 'word' or in my case a 'double word' (i.e. 64 bits), or, b) in a 4 X 4 arrangement. Is there some place in the DRAM manufacturer's specification I could be looking to determine this?
As I said, this question is for no technical reason. When I am thinking about DRAM memory, I use a visualizations in my mind about what is happening in memory. I would like my mental vision of the process to be as close to physical reality as possible.
2) When referring to DRAM memory, what is a 'cell'; is it physically one bit (capacitor, transistor, lines and all) or is a cell a group of them? If it is a group, from what I have read it is a bit ambiguous whether 'cell' refers to one 4 X 4 ( or one 16 bit linear) arrangement, one 'word' or one 'double word'?
On 09/28/2009 01:07 AM, William Case wrote:
I have been re-reading some notes I have made on how DRAM works. As a result I have a couple of unanswered questions?
http://en.wikipedia.org/wiki/Dynamic_random_access_memory has some pretty pictures, surely you found/searched that already ?
Hi David;
On Mon, 2009-09-28 at 08:17 +1000, David Timms wrote:
On 09/28/2009 01:07 AM, William Case wrote:
I have been re-reading some notes I have made on how DRAM works. As a result I have a couple of unanswered questions?
http://en.wikipedia.org/wiki/Dynamic_random_access_memory has some pretty pictures, surely you found/searched that already ?
Yes. Found that a while ago. It is a good example of why I am asking.
The second diagram shows a set of 4 X 4 arrays -- with a major disclaimer about its accuracy at the bottom. I have also seen other sites plus a couple of text books I own that show the cell arrangement as a linear setup. But only for 32 bit machines. I found nothing for 64 bit DRAM. I do have the schematics for my CPU which has 64 bit SRAM (latch) registers.
As I tried to explain, both probably exist, although I don't know that for sure. The actual operation of the DRAM isn't altered under either arrangement. The word line (row) and the bit line (column) are just organized slightly differently. The real problem is that the caption on any diagram I view is never clear on whether I am being shown just a concept or an actual arrangement.
I tend to visualize, in order to understand things better, such operations as reading from and writing to memory . It would help if I could have in my mind's eye the actual arrangement of cells for the most commonly used, current, DRAM for a 64 bit machine.
I have searched, on and off, over the last six months for something definitive. I have tried DRAM manufacturers sites for specifications that would be helpful. It seems that internal arrangements of memory cells must be proprietary.
So I turned to the mail list to see if there where any engineers who knew what the typical DRAM cell arrangement usually is.
William Case kirjoitti viestissään (lähetysaika keskiviikko, 30. syyskuuta 2009):
The second diagram shows a set of 4 X 4 arrays -- with a major disclaimer about its accuracy at the bottom. I have also seen other sites plus a couple of text books I own that show the cell arrangement as a linear setup. But only for 32 bit machines. I found nothing for 64 bit DRAM.
The bit width of the CPU has no effect on the DRAM chip layout. You simply connect enough chips in parallel to achieve the desired data bus width. A typical 64-bit DIMM "stick" has eight 8-bit wide chips.
Thank you Markku;
The cell arrangement of DRAM has been frustrating me for a long time now. Probably more because I set out to find an answer than because it was something I needed to know.
The additional questions below simply sprung to mind as I was reading your response and are only secondary.
On Wed, 2009-09-30 at 12:07 +0300, Markku Kolkka wrote:
William Case kirjoitti viestissään (lähetysaika keskiviikko, 30. syyskuuta 2009):
The second diagram shows a set of 4 X 4 arrays -- with a major disclaimer about its accuracy at the bottom. I have also seen other sites plus a couple of text books I own that show the cell arrangement as a linear setup. But only for 32 bit machines. I found nothing for 64 bit DRAM.
The bit width of the CPU has no effect on the DRAM chip layout.
I know. I only mentioned the CPU registers to avoid someone taking a lot of time explaining the difference between SRAM and DRAM. Perhaps mentioning latches only confused the issue.
You simply connect enough chips in parallel to achieve the desired data bus width. A typical 64-bit DIMM "stick" has eight 8-bit wide chips.
I'll take that information to the bank. To state it another way just to make sure I've got it. A typical physical address goes to, or points to, 8 + 8 + 8 + 8 + 8 + 8 + 8 + 8 cells arranged side-by-side in a line on an individual DIMM/DRAM stick.
I suspect that by thinking of address as divided into bytes rather than a single 64 bit word (dword, qword, -- pick your author) there is a natural division for instructions, numbers and characters within the 'word'. Or, is there some physical reason why it is thought of as 8 + 8 ...
When you say "chips" above I assume you mean cell, i.e. chip = cell = 1 capacitor and 1 transistor for storage of 1 bit.
On Wed, 2009-09-30 at 10:55 -0400, William Case wrote:
I'll take that information to the bank. To state it another way just to make sure I've got it. A typical physical address goes to, or points to, 8 + 8 + 8 + 8 + 8 + 8 + 8 + 8 cells arranged side-by-side in a line on an individual DIMM/DRAM stick.
+8 more if it's parity memory, or more for ECC memory.
I suspect that by thinking of address as divided into bytes rather than a single 64 bit word (dword, qword, -- pick your author) there is a natural division for instructions, numbers and characters within the 'word'. Or, is there some physical reason why it is thought of as 8 + 8 ...
It's the data that's stored in units of 8 bits. When addresses are stored then of course the same applies. When they're on the address lines of the memory bus, they may be in groups of 16 or 32 or 64 (depends on the bus design). None of this matters to you as a programmer.
Note that the pedantic name for a group of 8 bits is "octet". A "byte" is the number of bits required to represent a character in some encoding. Nearly all modern machines have 8-bit bytes and are byte-addressed, so we tend to equate "byte" with "8 bits", but I've used machines where addresses refer to 12-bit words, and the DEC-10 famously had 36-bit words and a configurable byte size, usually set to 6.
When you say "chips" above I assume you mean cell, i.e. chip = cell = 1 capacitor and 1 transistor for storage of 1 bit.
A chip has a whole bunch of cells (in the millions these days). They aren't the same.
poc
Thanks poc;
Then it gets confusing again!
On Wed, 2009-09-30 at 10:53 -0430, Patrick O'Callaghan wrote:
On Wed, 2009-09-30 at 10:55 -0400, William Case wrote:
It's the data that's stored in units of 8 bits. When addresses are stored then of course the same applies. When they're on the address lines of the memory bus, they may be in groups of 16 or 32 or 64 (depends on the bus design). None of this matters to you as a programmer.
Understood -- I think. Put another way, on a 64 bit machine if the memory bus is 32 lines wide the data, or whatever, would flow with the first 32 bits immediately followed by the second 32 bits -- right?
(I am trying to avoid discussing whether data flows on the rising edge or falling edge of a clock tick etc.)
Note that the pedantic name for a group of 8 bits is "octet". A "byte" is the number of bits required to represent a character in some encoding.
When you say "chips" above I assume you mean cell, i.e. chip = cell = 1 capacitor and 1 transistor for storage of 1 bit.
A chip has a whole bunch of cells (in the millions these days). They aren't the same.
Then what was Markku referring to when he said "A typical 64-bit DIMM "stick" has eight 8-bit wide chips." The chip is one of the minute black chips I can just barely see on a RAM stick --? That is what I originally thought.
Markku's statement then implies that a 64 bit qword is stored in an 8 x 8 array of cells. True?
By the Way: The definition of a 'word' seems to be all over the place.
With Intel, the definition I have read says a 'word' is 16 bits, a 'double word (dword)' is 32 bits, and a 'quadruple word (qword)' is 64 bits.
The specs for the 64 bit AMD CPU I used to have defined a 'word' as whatever the machine said it was. In my case at the time, a 'word' would have been 64 bits. ????
I raised the question of 'words' with my local Linux Users Group and simply got caught in a long debate amongst them with huge digressions that resolved nothing to my satisfaction.
On Wed, 2009-09-30 at 12:03 -0400, William Case wrote:
Thanks poc;
Then it gets confusing again!
On Wed, 2009-09-30 at 10:53 -0430, Patrick O'Callaghan wrote:
On Wed, 2009-09-30 at 10:55 -0400, William Case wrote:
It's the data that's stored in units of 8 bits. When addresses are stored then of course the same applies. When they're on the address lines of the memory bus, they may be in groups of 16 or 32 or 64 (depends on the bus design). None of this matters to you as a programmer.
Understood -- I think. Put another way, on a 64 bit machine if the memory bus is 32 lines wide the data, or whatever, would flow with the first 32 bits immediately followed by the second 32 bits -- right?
Right. Some implementations might have a bus with two cycles per word, i.e. it's cheaper but slower. Intel has done that on occasion.
(I am trying to avoid discussing whether data flows on the rising edge or falling edge of a clock tick etc.)
Please :-)
Note that the pedantic name for a group of 8 bits is "octet". A "byte" is the number of bits required to represent a character in some encoding.
When you say "chips" above I assume you mean cell, i.e. chip = cell = 1 capacitor and 1 transistor for storage of 1 bit.
A chip has a whole bunch of cells (in the millions these days). They aren't the same.
Then what was Markku referring to when he said "A typical 64-bit DIMM "stick" has eight 8-bit wide chips." The chip is one of the minute black chips I can just barely see on a RAM stick --? That is what I originally thought.
Yes.
Markku's statement then implies that a 64 bit qword is stored in an 8 x 8 array of cells. True?
No. If a 64-bit wide DIMM has 8 chips on it you can be highly confident in saying the chips are 8 bits wide, but their depth is another matter. And the fact that the chip presents an 8-bit wide interface doesn't mean that the internal organization is in 8x8 bit arrays, though it might be.
Furthermore, the 64 bits in a word will pretty much *never* be stored in a single 8x8 array. They'll be stored in a number of parallel arrays for speed of access, usually across 8 separate chips.
Again: this level of detail (the array size) is essentially invisible to the programmer.
By the Way: The definition of a 'word' seems to be all over the place.
With Intel, the definition I have read says a 'word' is 16 bits, a 'double word (dword)' is 32 bits, and a 'quadruple word (qword)' is 64 bits.
That's true of Intel. It's not necessarily true across all computer architectures (in fact it isn't, as I mentioned in my previous reply).
The specs for the 64 bit AMD CPU I used to have defined a 'word' as whatever the machine said it was. In my case at the time, a 'word' would have been 64 bits. ????
A word is normally considered to be the unit of the bus cycle of the machine (but see the above discussion of dual-cycle implementations) and coincides with the maximum addressable range of virtual memory (physical memory can be less, or even more in some cases). It usually also coincides with the size of the most common machine instructions, those these can also vary depending on the architecture.
Good introductions to this stuff are Hennessy and Patterson, or Tanenbaum's Computer Organization book.
I raised the question of 'words' with my local Linux Users Group and simply got caught in a long debate amongst them with huge digressions that resolved nothing to my satisfaction.
That's because only hardware nuts and operating system geeks really care :-)
poc
Hi poc, Markku.
I think I have what I wanted. Thanks for taking the time.
On Wed, 2009-09-30 at 12:02 -0430, Patrick O'Callaghan wrote:
On Wed, 2009-09-30 at 12:03 -0400, William Case wrote:
Thanks poc;
Then what was Markku referring to when he said "A typical 64-bit DIMM "stick" has eight 8-bit wide chips." The chip is one of the minute black chips I can just barely see on a RAM stick --? That is what I originally thought.
Yes.
Markku's statement then implies that a 64 bit qword is stored in an 8 x 8 array of cells. True?
No. If a 64-bit wide DIMM has 8 chips on it you can be highly confident in saying the chips are 8 bits wide, but their depth is another matter. And the fact that the chip presents an 8-bit wide interface doesn't mean that the internal organization is in 8x8 bit arrays, though it might be.
Furthermore, the 64 bits in a word will pretty much *never* be stored in a single 8x8 array. They'll be stored in a number of parallel arrays for speed of access, usually across 8 separate chips.
Ah, back to 8 + 8 + 8 + 8 + 8 + 8 + 8 + 8 cells arranged side-by-side in a line on an individual DIMM/DRAM stick. OK, that's good enough for the personal visualization I wanted. I understand that this can vary, but once one has a basic configuration in mind, it only requires mild mental gymnastics to move the parts and pieces around in one's head as long as the parts and pieces are still all there,
Again: this level of detail (the array size) is essentially invisible to the programmer.
I know. My objective is not primarily for programming but for understanding how a machine (basically an appliance) plugged into a wall socket can do so much.
By the Way: The definition of a 'word' seems to be all over the place.
With Intel, the definition I have read says a 'word' is 16 bits, a 'double word (dword)' is 32 bits, and a 'quadruple word (qword)' is 64 bits.
That's true of Intel. It's not necessarily true across all computer architectures (in fact it isn't, as I mentioned in my previous reply).
The specs for the 64 bit AMD CPU I used to have defined a 'word' as whatever the machine said it was. In my case at the time, a 'word' would have been 64 bits. ????
A word is normally considered to be the unit of the bus cycle of the machine (but see the above discussion of dual-cycle implementations) and coincides with the maximum addressable range of virtual memory (physical memory can be less, or even more in some cases). It usually also coincides with the size of the most common machine instructions, those these can also vary depending on the architecture.
Good introductions to this stuff are Hennessy and Patterson, or Tanenbaum's Computer Organization book.
I have both books and read them a couple of years ago, cover to cover. You would be surprised how much I was able to understand and retain. I made copious notes at the time. I am presently re-reading and putting those notes into a meaningful form for myself. But learning is an iterative process. Any questions I ask now are fill-in questions or questions I didn't think to ask at the time. Now that I know better where and how to look, I can do MOST of the research myself, but an occasional hand is greatly appreciated.
The advantage of being able to mentally visualize a process is that I find it easier to see logic gaps; to ask myself questions like "hey wait a minute; how did that get from here to there?".
I raised the question of 'words' with my local Linux Users Group and simply got caught in a long debate amongst them with huge digressions that resolved nothing to my satisfaction.
That's because only hardware nuts and operating system geeks really care :-)
Thanks again for your time.
Patrick O'Callaghan wrote:
On Wed, 2009-09-30 at 10:55 -0400, William Case wrote:
I'll take that information to the bank. To state it another way just to make sure I've got it. A typical physical address goes to, or points to, 8 + 8 + 8 + 8 + 8 + 8 + 8 + 8 cells arranged side-by-side in a line on an individual DIMM/DRAM stick.
+8 more if it's parity memory, or more for ECC memory.
I suspect that by thinking of address as divided into bytes rather than a single 64 bit word (dword, qword, -- pick your author) there is a natural division for instructions, numbers and characters within the 'word'. Or, is there some physical reason why it is thought of as 8 + 8 ...
It's the data that's stored in units of 8 bits. When addresses are stored then of course the same applies. When they're on the address lines of the memory bus, they may be in groups of 16 or 32 or 64 (depends on the bus design). None of this matters to you as a programmer.
Note that the pedantic name for a group of 8 bits is "octet". A "byte" is the number of bits required to represent a character in some encoding. Nearly all modern machines have 8-bit bytes and are byte-addressed, so we tend to equate "byte" with "8 bits", but I've used machines where addresses refer to 12-bit words, and the DEC-10 famously had 36-bit words and a configurable byte size, usually set to 6.
The GE-600/6000 line had 36 bits also, and could use 6 or 9 bit characters. We used ASCII with the unused high bit as end of string. MULTICS was developed on a GE-645, leading to UNIX, leading to Linux. Sort of.
Nomenclature: 8 bits is a byte, 4 bits is a nybble, 2 bits is a quarter. That's probably only funny to old programmers in the USA, sorry.
-
Bill Case -
Bill Davidsen -
Development discussions related to Fedora -
Markku Kolkka -
Patrick O'Callaghan