Orphaned packages seeking new point of contact

Jitka Plesníková jplesnik at redhat.com
Thu Oct 8 07:29:55 UTC 2015


> perl-Hardware-Verilog-Parser -- Complete grammar for parsing Verilog code using perl ( master f23 f22 f21 el6 el5 )
> perl-Hardware-Vhdl-Lexer -- Split VHDL code into lexical tokens ( master f23 f22 f21 el6 el5 )
> perl-Hardware-Vhdl-Parser -- Complete grammar for parsing VHDL code using perl ( master f23 f22 f21 el6 el5 )
> perl-Hardware-Vhdl-Tidy -- VHDL code prettifier ( master f23 f22 f21 el6 el5 )
> perl-ModelSim-List -- Analyse the 'list' output of the ModelSim simulator ( master f23 f22 f21 el6 el5 )
> perl-Perlilog -- Verilog environment and IP core handling in Perl ( master f23 f22 f21 el5 )
> perl-SystemC-Vregs -- Utility routines used by vregs ( master f23 f22 f21 el6 el5 )
> perl-SystemPerl -- SystemPerl Perl module ( master f23 f22 f21 el6 el5 )
> perl-Verilog-CodeGen -- Verilog code generator ( master f23 f22 f21 el6 el5 )
> perl-Verilog-Perl -- Verilog parsing routines ( master f23 f22 f21 el6 el5 )
> perl-Verilog-Readmem -- Parse Verilog $readmemh or $readmemb text file ( master f23 f22 f21 el6 el5 )
I took this one.
Jitka


More information about the devel mailing list