Fedora 12 Update: verilator-3.804-1.fc12

[updates at fedoraproject.org]

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Fedora Update Notification
FEDORA-2010-15339
2010-09-28 05:01:41
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Name        : verilator
Product     : Fedora 12
Version     : 3.804
Release     : 1.fc12
URL         : http://www.veripool.com/verilator.html
Summary     : A fast simulator for synthesizable Verilog
Description :

Verilator is the fastest free Verilog HDL simulator. It compiles
synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis
assertions into C++ or SystemC code. It is designed for large projects
where fast simulation performance is of primary concern, and is
especially well suited to create executable models of CPUs for
embedded software design teams.

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Update Information:

FEL: Bugfix release of Verilator 3.804

Support tracing/coverage of underscore signals, bug280. [by Jason McMullan]
Fix preprocessor “ of existing base define, bug283. [Usha Priyadharshini]
Increase define recursions before error. [Paul Liu]
On core dump, print debug suggestions.
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ChangeLog:

* Sat Sep 25 2010 Chitlesh Goorah <chitlesh [AT] fedoraproject DOT org> - 3.804-1
- updated to 3.804
* Sun Jul 11 2010 Chitlesh Goorah <chitlesh [AT] fedoraproject DOT org> - 3.803-1
- updated to 3.803
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This update can be installed with the "yum" update program.  Use 
su -c 'yum update verilator' at the command line.
For more information, refer to "Managing Software with yum",
available at http://docs.fedoraproject.org/yum/.

All packages are signed with the Fedora Project GPG key.  More details on the
GPG keys used by the Fedora Project can be found at
https://fedoraproject.org/keys
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