[Bug 468516] Review Request: verilator - A fast simulator of synthesizable Verilog HDL

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https://bugzilla.redhat.com/show_bug.cgi?id=468516





--- Comment #5 from Lane <dirjud at gmail.com>  2008-10-26 11:14:00 EDT ---
I have incorporated Chitlesh's feedbackc into an updated spec file and have a
new release "3" available for download from:

http://www.brooks.nu/~lane/verilator.spec
http://www.brooks.nu/~lane/verilator-3.680-3.fc10.src.rpm 

The previous release was "2" but was not documented in the changelog.  I added
the correct changelog entry to document releases "1", "2", and now "3".  We
have been using these releases at my work, thus I do not want to reset to "1"
or it will cause problems for our users.

I have built and tested this new release 3 on our project regression test suite
at work on F10 rawhide, F8, and Centos 5.2.

Lane

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