[Bug 468516] Review Request: verilator - A fast simulator of synthesizable Verilog HDL

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https://bugzilla.redhat.com/show_bug.cgi?id=468516





--- Comment #19 from Chitlesh GOORAH <cgoorah at yahoo.com.au>  2009-01-03 18:35:56 EDT ---
Lane, you have commented perl-verilog on

#BuildRequires:  perl-verilog, perl-systemc, systemc

I'm packaging perl-Verilog https://bugzilla.redhat.com/show_bug.cgi?id=476386

I haven't yet looked at the details, do you think enabling perl-Verilog our
verilator will provide more "features" ?

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