[Bug 474980] Review Request: ovm - Open Verification Methodology : IEEE 1800 SystemVerilog standard

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https://bugzilla.redhat.com/show_bug.cgi?id=474980





--- Comment #14 from Chitlesh GOORAH <cgoorah at yahoo.com.au>  2009-01-23 20:58:42 EDT ---
Yes, this is the current status.

--- Forget "software" for a moment :

For any hardware designer, the basic design methodology is  :

      design <-> home made customized scripts <-> EDA tools
                      this combination gives
          =>           developing hardware  
(with at least 12 different EDA tools to sign off a project)

This somehow differs from the popular "software" methodology: code, compile and
run.

The questions you might be asking are :
- why complain when companies have opensourced their libraries ? (forget the
opensource community, the later will _never_ give you such verification
methodology before the next 20 years, because it costs millions of euros to
develop it) 
- can these libraries(text files) be incorporated directly into the user's HDL
design?

You may have heard "open hardware" and opensource community are proud of it.

If you look closer (opensparcT2 for example) at the code, this open hardware
was designed under proprietary eda tools, same applies to opencores designs.

I believe building an opensource design and simulation platform -FEL-
(providing software), with inclusion of ovm and vmm, will encourage digital
designers extend their "open" hardware desire to "design open hardware with
open source software".

This is a problem and a lack in the current opensource software and hardware
communities. The only way to solve it is "someone has to step in first and take
the lead". 

With our FEL we have already taken this leadership to promote open source
_content_ and ovm is an open source _content_.

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