[Bug 468516] Review Request: verilator - A fast simulator of synthesizable Verilog HDL

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https://bugzilla.redhat.com/show_bug.cgi?id=468516





--- Comment #29 from wsnyder at wsnyder.org  2009-03-28 11:19:13 EDT ---
FYI Verilator 3.702 allows you to set and compile SYSTEMPERL_INCLUDE into
verilator so the src/ suffix hack (see the earlier comments here) isn't needed.

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