jplesnik pushed to perl-Verilog-Perl (master). "3.414 bump"

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Tue Sep 22 12:46:42 UTC 2015


From 1d970e38dadf4fbe1534969cbe0549f91dd52668 Mon Sep 17 00:00:00 2001
From: Jitka Plesnikova <jplesnik at redhat.com>
Date: Tue, 22 Sep 2015 14:46:26 +0200
Subject: 3.414 bump


diff --git a/.gitignore b/.gitignore
index 96c06b5..b2ffb09 100644
--- a/.gitignore
+++ b/.gitignore
@@ -7,3 +7,4 @@ Verilog-Perl-3.301.tar.gz
 /Verilog-Perl-3.401.tar.gz
 /Verilog-Perl-3.408.tar.gz
 /Verilog-Perl-3.412.tar.gz
+/Verilog-Perl-3.414.tar.gz
diff --git a/Verilog-Perl-3.414-Fix-dumpcheck-test-sort-order-failures.patch b/Verilog-Perl-3.414-Fix-dumpcheck-test-sort-order-failures.patch
new file mode 100644
index 0000000..8df4c63
--- /dev/null
+++ b/Verilog-Perl-3.414-Fix-dumpcheck-test-sort-order-failures.patch
@@ -0,0 +1,146 @@
+From a74b61de6485e1208305a2c2a9737c25582bfe16 Mon Sep 17 00:00:00 2001
+From: Wilson Snyder <wsnyder at wsnyder.org>
+Date: Fri, 24 Jul 2015 23:33:28 -0400
+Subject: [PATCH] Fix dumpcheck test sort order failures, bug939.
+
+---
+ t/42_dumpcheck.t       |  4 ++--
+ t/42_dumpcheck_1.out   | 58 +++++++++++++++++++++++++-------------------------
+ t/42_dumpcheck_2.out   | 10 ++++-----
+ t/42_dumpcheck_v2k.out |  4 ++--
+ 4 files changed, 38 insertions(+), 38 deletions(-)
+
+diff --git a/t/42_dumpcheck.t b/t/42_dumpcheck.t
+index b021c67..3050f9d 100755
+--- a/t/42_dumpcheck.t
++++ b/t/42_dumpcheck.t
+@@ -78,8 +78,8 @@ sub check {
+ 	$nl->dump;
+ 
+ 	print STDOUT "#### Commentary:\n";
+-	foreach my $mod ($nl->modules) {
+-	    foreach my $net ($mod->nets) {
++	foreach my $mod ($nl->modules_sorted) {
++	    foreach my $net ($mod->nets_sorted) {
+ 		my $cmt = $net->comment||'';
+ 		$cmt =~ s/\n/\\n/g;
+ 		$cmt = qq{"$cmt"};
+diff --git a/t/42_dumpcheck_1.out b/t/42_dumpcheck_1.out
+index a0555aa..ffe58d7 100644
+--- a/t/42_dumpcheck_1.out
++++ b/t/42_dumpcheck_1.out
+@@ -98,42 +98,42 @@ Module:v_recursive  Kwd:module  File:verilog/v_recursive.v
+   Cell:recurse  is-a:v_recursive .DEPTH(DEPTH-1)
+             Module:v_recursive  Kwd:module  File:verilog/v_recursive.v
+ #### Commentary:
+-verilog/v_recursive.v:0002: DEPTH   cmt=""
+-verilog/v_hier_subsub.v:0012: a   cmt=""
+-verilog/v_hier_subsub.v:0011: IGNORED   cmt=""
+-verilog/v_hier_subsub.v:0013: q   cmt=""
++verilog/v_hier_top.v:0042: GLOBAL_PARAM   cmt="// Local Variables:\n// eval:(verilog-read-defines)\n// End:"
++verilog/v_comments.v:0022: a   cmt="// a-First"
++verilog/v_comments.v:0025: b   cmt="// b-Third\n// Third"
++verilog/v_comments.v:0023: m   cmt="// m-Second"
+ verilog/v_comments.v:0031: a   cmt="// a-First"
+ verilog/v_comments.v:0032: b   cmt="// b-Secondparen\n// Third"
+-verilog/v_hier_top.v:0042: GLOBAL_PARAM   cmt="// Local Variables:\n// eval:(verilog-read-defines)\n// End:"
+-verilog/v_hier_top2.v:0013: iosig   cmt="/* synthesis useioff = 1 //*synthesis fpga_attr = "BLAH=ON"//* synthesis fpga_pin = "A22"*/\n/* synthesis aftersemi*/\n// NetListName=F12_IO"
+-verilog/v_hier_top2.v:0009: clk   cmt=""
+-verilog/v_hier_noport.v:0006: internal   cmt=""
+-verilog/v_comments.v:0016: e   cmt="// Comment for e"
+-verilog/v_comments.v:0011: d1   cmt=""
+-verilog/v_comments.v:0012: d2   cmt=""
+ verilog/v_comments.v:0007: a   cmt="// comment for a"
++verilog/v_comments.v:0008: b   cmt=""
++verilog/v_comments.v:0009: c   cmt="// comment for c"
+ verilog/v_comments.v:0010: d   cmt=""
++verilog/v_comments.v:0011: d1   cmt=""
++verilog/v_comments.v:0012: d2   cmt=""
+ verilog/v_comments.v:0013: d3   cmt=""
+-verilog/v_comments.v:0009: c   cmt="// comment for c"
+-verilog/v_comments.v:0008: b   cmt=""
+-verilog/v_comments.v:0022: a   cmt="// a-First"
+-verilog/v_comments.v:0025: b   cmt="// b-Third\n// Third"
+-verilog/v_comments.v:0023: m   cmt="// m-Second"
+-verilog/v_hier_sub.v:0009: qvec   cmt="/* Comment for v_hier_sub, qvec */"
+-verilog/v_hier_sub.v:0027: K_UNUSED   cmt=""
+-verilog/v_hier_sub.v:0007: clk   cmt=""
++verilog/v_comments.v:0016: e   cmt="// Comment for e"
++verilog/v_hier_noport.v:0006: internal   cmt=""
++verilog/v_hier_sub.v:0012: FROM_DEFPARAM   cmt=""
+ verilog/v_hier_sub.v:0027: K   cmt=""
+-verilog/v_hier_sub.v:0008: avec   cmt="// Comment for v_hier_sub, avec"
++verilog/v_hier_sub.v:0027: K_UNUSED   cmt=""
+ verilog/v_hier_sub.v:0014: a1   cmt="// Outputs"
+-verilog/v_hier_sub.v:0012: FROM_DEFPARAM   cmt=""
+-verilog/v_hier_top.v:0033: WC_p4   cmt=""
++verilog/v_hier_sub.v:0008: avec   cmt="// Comment for v_hier_sub, avec"
++verilog/v_hier_sub.v:0007: clk   cmt=""
++verilog/v_hier_sub.v:0009: qvec   cmt="/* Comment for v_hier_sub, qvec */"
++verilog/v_hier_subsub.v:0011: IGNORED   cmt=""
++verilog/v_hier_subsub.v:0012: a   cmt=""
++verilog/v_hier_subsub.v:0013: q   cmt=""
+ verilog/v_hier_top.v:0031: WC_p1   cmt=""
+-verilog/v_hier_top.v:0037: asn_clk   cmt=""
+-verilog/v_hier_top.v:0029: WC_w4   cmt=""
+-verilog/v_hier_top.v:0027: WC_w1b   cmt=""
+-verilog/v_hier_top.v:0026: WC_w1   cmt=""
+-verilog/v_hier_top.v:0034: WC_pint   cmt="// Assignments"
+-verilog/v_hier_top.v:0011: clk   cmt="/* pragma jsc_clk */"
++verilog/v_hier_top.v:0032: WC_p3   cmt=""
+ verilog/v_hier_top.v:0030: WC_p32   cmt=""
++verilog/v_hier_top.v:0033: WC_p4   cmt=""
++verilog/v_hier_top.v:0034: WC_pint   cmt="// Assignments"
++verilog/v_hier_top.v:0026: WC_w1   cmt=""
++verilog/v_hier_top.v:0027: WC_w1b   cmt=""
+ verilog/v_hier_top.v:0028: WC_w3   cmt=""
+-verilog/v_hier_top.v:0032: WC_p3   cmt=""
++verilog/v_hier_top.v:0029: WC_w4   cmt=""
++verilog/v_hier_top.v:0037: asn_clk   cmt=""
++verilog/v_hier_top.v:0011: clk   cmt="/* pragma jsc_clk */"
++verilog/v_hier_top2.v:0009: clk   cmt=""
++verilog/v_hier_top2.v:0013: iosig   cmt="/* synthesis useioff = 1 //*synthesis fpga_attr = "BLAH=ON"//* synthesis fpga_pin = "A22"*/\n/* synthesis aftersemi*/\n// NetListName=F12_IO"
++verilog/v_recursive.v:0002: DEPTH   cmt=""
+diff --git a/t/42_dumpcheck_2.out b/t/42_dumpcheck_2.out
+index e04018e..edf4059 100644
+--- a/t/42_dumpcheck_2.out
++++ b/t/42_dumpcheck_2.out
+@@ -72,15 +72,15 @@ Module:pinorder4  Kwd:module  File:verilog/pinorder.v
+ verilog/pinorder.v:0049: iow   cmt=""
+ verilog/pinorder.v:0050: iw   cmt=""
+ verilog/pinorder.v:0048: ow   cmt=""
+-verilog/pinorder.v:0039: y   cmt=""
+-verilog/pinorder.v:0042: noconnect   cmt=""
+ verilog/pinorder.v:0041: abcconst   cmt=""
+ verilog/pinorder.v:0043: def   cmt=""
++verilog/pinorder.v:0042: noconnect   cmt=""
+ verilog/pinorder.v:0040: x   cmt=""
+-verilog/pinorder.v:0029: y   cmt=""
++verilog/pinorder.v:0039: y   cmt=""
+ verilog/pinorder.v:0030: x   cmt=""
++verilog/pinorder.v:0029: y   cmt=""
+ verilog/pinorder.v:0028: z   cmt=""
+ verilog/pinorder.v:0010: IPCD_const   cmt=""
+-verilog/pinorder.v:0008: d_o   cmt=""
+-verilog/pinorder.v:0007: b_i   cmt=""
+ verilog/pinorder.v:0009: a_i   cmt=""
++verilog/pinorder.v:0007: b_i   cmt=""
++verilog/pinorder.v:0008: d_o   cmt=""
+diff --git a/t/42_dumpcheck_v2k.out b/t/42_dumpcheck_v2k.out
+index e8fdffe..f17faf2 100644
+--- a/t/42_dumpcheck_v2k.out
++++ b/t/42_dumpcheck_v2k.out
+@@ -9,8 +9,8 @@ Module:v_v2k  Kwd:module  File:verilog/v_v2k.v
+   Net:sig1  O  DeclT:port  NetT:  DataT:[WIDTH:0]  Array:  WIDTH:0
+   Net:sig2  I  DeclT:port  NetT:  DataT:reg [WIDTH:0]  Array:  WIDTH:0
+ #### Commentary:
+-verilog/v_v2k.v:0007: clk   cmt=""
+ verilog/v_v2k.v:0006: WIDTH   cmt=""
+-verilog/v_v2k.v:0009: sig1   cmt=""
++verilog/v_v2k.v:0007: clk   cmt=""
+ verilog/v_v2k.v:0008: rst   cmt=""
++verilog/v_v2k.v:0009: sig1   cmt=""
+ verilog/v_v2k.v:0010: sig2   cmt=""
+-- 
+2.4.3
+
diff --git a/perl-Verilog-Perl.spec b/perl-Verilog-Perl.spec
index 0006c64..666068a 100644
--- a/perl-Verilog-Perl.spec
+++ b/perl-Verilog-Perl.spec
@@ -1,5 +1,5 @@
 Name:          perl-Verilog-Perl
-Version:       3.412
+Version:       3.414
 Release:       1%{?dist}
 Summary:       Verilog parsing routines
 
@@ -9,6 +9,9 @@ Group:         Applications/Engineering
 URL:           http://www.veripool.org/wiki/verilog-perl
 Source0:       http://search.cpan.org/CPAN/authors/id/W/WS/WSNYDER/Verilog-Perl-%{version}.tar.gz
 
+# Fixed a failing test 42_dumpcheck.t
+Patch0:        Verilog-Perl-3.414-Fix-dumpcheck-test-sort-order-failures.patch
+
 BuildRoot:     %{_tmppath}/%{name}-%{version}-%{release}-root-%(id -nu)
 
 BuildRequires: bison
@@ -64,6 +67,7 @@ that use the Verilog language.
 
 %prep
 %setup -q -n Verilog-Perl-%{version}
+%patch0 -p1
 
 
 %build
@@ -104,6 +108,9 @@ rm -rf %{buildroot}
 
 
 %changelog
+* Tue Sep 22 2015 Jitka Plesnikova <jplesnik at redhat.com> - 3.414-1
+- 3.414 bump
+
 * Tue Jun 23 2015 Petr Pisar <ppisar at redhat.com> - 3.412-1
 - 3.412 bump
 
diff --git a/sources b/sources
index 901e5ee..a7896ba 100644
--- a/sources
+++ b/sources
@@ -1 +1 @@
-91d318b133d5d4b19173169133f0b7a8  Verilog-Perl-3.412.tar.gz
+4d55697cabb51538fcf4cd2fbf129150  Verilog-Perl-3.414.tar.gz
-- 
cgit v0.10.2


	http://pkgs.fedoraproject.org/cgit/perl-Verilog-Perl.git/commit/?h=master&id=1d970e38dadf4fbe1534969cbe0549f91dd52668


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