Mon Aug 27 11:09:27 UTC 2007

Author: jakub

Update of /cvs/pkgs/rpms/gcc/F-7
In directory cvs-int.fedora.redhat.com:/tmp/cvs-serv14782

Modified Files:
	.cvsignore gcc41.spec libgcc_post_upgrade.c sources 
Added Files:
	gcc41-build-id.patch gcc41-ppc-tramp.patch gcc41-pr22244.patch 
	gcc41-pr28690.patch gcc41-pr32139.patch gcc41-pr32678.patch 
	gcc41-pr32912.patch gcc41-rh247256.patch gcc41-rh253102.patch 
	gcc41-sparc-niagara.patch 
Removed Files:
	gcc41-amdfam10.patch gcc41-dtor-relro.patch 
	gcc41-libgomp-ncpus.patch gcc41-multi32-hack.patch 
	gcc41-objc-rh185398.patch gcc41-pr24036-revert.patch 
	gcc41-pr27567.patch gcc41-pr28482.patch gcc41-pr28709.patch 
	gcc41-pr29059.patch gcc41-pr29272.patch gcc41-pr29299.patch 
	gcc41-pr31187.patch gcc41-pr31748.patch gcc41-rh234515.patch 
	gcc41-strncat-chk.patch gcc41-tests.patch 
	gcc41-tls-data-alignment.patch 
Log Message:
4.1.2-18.fc7

gcc41-build-id.patch:

--- NEW FILE gcc41-build-id.patch ---
2007-07-22  Roland McGrath  <roland at redhat.com>

	* config/rs6000/sysv4.h (LINK_EH_SPEC): Add --build-id for
	non-relocatable link.
	* config/linux.h (LINK_EH_SPEC): Likewise.
	* config/sparc/linux.h (LINK_EH_SPEC): Likewise.
	* config/sparc/linux64.h (LINK_EH_SPEC): Likewise.
	* config/alpha/elf.h (LINK_EH_SPEC): Likewise.
	* config/ia64/linux.h (LINK_EH_SPEC): Likewise.

--- gcc/config/rs6000/sysv4.h.~1~
+++ gcc/config/rs6000/sysv4.h
@@ -1044,7 +1044,7 @@ extern int fixuplabelno;
   %{!dynamic-linker:-dynamic-linker /lib/ld.so.1}}}"
 
 #if defined(HAVE_LD_EH_FRAME_HDR)
-# define LINK_EH_SPEC "%{!static:--eh-frame-hdr} "
+# define LINK_EH_SPEC "%{!static:--eh-frame-hdr} %{!r:--build-id} "
 #endif
 
 #define CPP_OS_LINUX_SPEC "-D__unix__ -D__gnu_linux__ -D__linux__ \
--- gcc/config/linux.h.~1~
+++ gcc/config/linux.h
@@ -85,7 +85,7 @@ Boston, MA 02110-1301, USA.  */
     } while (0)
 
 #if defined(HAVE_LD_EH_FRAME_HDR)
-#define LINK_EH_SPEC "%{!static:--eh-frame-hdr} "
+#define LINK_EH_SPEC "%{!static:--eh-frame-hdr} %{!r:--build-id} "
 #endif
 
 /* Define this so we can compile MS code for use with WINE.  */
--- gcc/config/sparc/linux64.h.~1~
+++ gcc/config/sparc/linux64.h
@@ -316,7 +316,7 @@ do {									\
 #define DITF_CONVERSION_LIBFUNCS 1
 
 #if defined(HAVE_LD_EH_FRAME_HDR)
-#define LINK_EH_SPEC "%{!static:--eh-frame-hdr} "
+#define LINK_EH_SPEC "%{!static:--eh-frame-hdr} %{!r:--build-id} "
 #endif
 
 #ifdef HAVE_AS_TLS
--- gcc/config/sparc/linux.h.~1~
+++ gcc/config/sparc/linux.h
@@ -188,7 +188,7 @@ do {									\
 #define DITF_CONVERSION_LIBFUNCS 1
 
 #if defined(HAVE_LD_EH_FRAME_HDR)
-#define LINK_EH_SPEC "%{!static:--eh-frame-hdr} "
+#define LINK_EH_SPEC "%{!static:--eh-frame-hdr} %{!r:--build-id} "
 #endif
 
 #ifdef HAVE_AS_TLS
--- gcc/config/alpha/elf.h.~1~
+++ gcc/config/alpha/elf.h
@@ -453,5 +453,5 @@ extern int alpha_this_gpdisp_sequence_nu
    I imagine that other systems will catch up.  In the meantime, it
    doesn't harm to make sure that the data exists to be used later.  */
 #if defined(HAVE_LD_EH_FRAME_HDR)
-#define LINK_EH_SPEC "%{!static:--eh-frame-hdr} "
+#define LINK_EH_SPEC "%{!static:--eh-frame-hdr} %{!r:--build-id} "
 #endif
--- gcc/config/ia64/linux.h.~1~
+++ gcc/config/ia64/linux.h
@@ -56,7 +56,7 @@ do {						\
    Signalize that because we have fde-glibc, we don't need all C shared libs
    linked against -lgcc_s.  */
 #undef LINK_EH_SPEC
-#define LINK_EH_SPEC ""
+#define LINK_EH_SPEC "%{!r:--build-id} "
 
 #define MD_UNWIND_SUPPORT "config/ia64/linux-unwind.h"
 

gcc41-ppc-tramp.patch:

--- NEW FILE gcc41-ppc-tramp.patch ---
2007-08-20  Jakub Jelinek  <jakub at redhat.com>

	* config/rs6000/tramp.asm: Include config.h.
	Check __PIC__ or __pic__ macro instead of SHARED.

--- gcc/config/rs6000/tramp.asm.jj	2006-10-05 00:28:33.000000000 +0200
+++ gcc/config/rs6000/tramp.asm	2007-08-20 23:20:52.000000000 +0200
@@ -1,6 +1,6 @@
 /*  Special support for trampolines
  *
- *   Copyright (C) 1996, 1997, 2000 Free Software Foundation, Inc.
+ *   Copyright (C) 1996, 1997, 2000, 2007 Free Software Foundation, Inc.
  *   Written By Michael Meissner
  * 
  * This file is free software; you can redistribute it and/or modify it
@@ -37,7 +37,8 @@
 
 	.file	"tramp.asm"
 	.section ".text"
-	#include "ppc-asm.h"
+#include "ppc-asm.h"
+#include "config.h"
 
 #ifndef __powerpc64__
 	.type	trampoline_initial, at object
@@ -105,7 +106,7 @@ FUNC_START(__trampoline_setup)
 	blr
 
 .Labort:
-#if defined SHARED && defined HAVE_AS_REL16
+#if (defined __PIC__ || defined __pic__) && defined HAVE_AS_REL16
 	bcl	20,31,1f
 1:	mflr	r30
 	addis	r30,r30,_GLOBAL_OFFSET_TABLE_-1b at ha

gcc41-pr22244.patch:

--- NEW FILE gcc41-pr22244.patch ---
2007-08-14  Jakub Jelinek  <jakub at redhat.com>

	PR fortran/22244
	* Make-lang.in (fortran/trans-types.o): Depend on $(FLAGS_H).
	* trans-types.c: Include flags.h.
	(gfc_get_nodesc_array_type): Add TYPE_DECL TYPE_NAME with
	correct bounds and dimensions for packed arrays.

--- gcc/fortran/Make-lang.in	(revision 127395)
+++ gcc/fortran/Make-lang.in	(working copy)
@@ -292,7 +292,7 @@ fortran/trans-decl.o: $(GFORTRAN_TRANS_D
   cgraph.h $(TARGET_H) function.h $(FLAGS_H) $(RTL_H) tree-gimple.h \
   tree-dump.h
 fortran/trans-types.o: $(GFORTRAN_TRANS_DEPS) gt-fortran-trans-types.h \
-  real.h toplev.h $(TARGET_H)
+  real.h toplev.h $(TARGET_H) $(FLAGS_H)
 fortran/trans-const.o: $(GFORTRAN_TRANS_DEPS)
 fortran/trans-expr.o: $(GFORTRAN_TRANS_DEPS) fortran/dependency.h
 fortran/trans-stmt.o: $(GFORTRAN_TRANS_DEPS) fortran/dependency.h
--- gcc/fortran/trans-types.c	(revision 127395)
+++ gcc/fortran/trans-types.c	(working copy)
@@ -35,6 +35,7 @@ Software Foundation, 51 Franklin Street,
 #include "trans-types.h"
 #include "trans-const.h"
 #include "real.h"
+#include "flags.h"
 
 
 #if (GFC_MAX_DIMENSIONS < 10)
@@ -1005,7 +1006,7 @@ gfc_get_nodesc_array_type (tree etype, g
     {
       /* Fill in the stride and bound components of the type.  */
       if (known_stride)
-	tmp =  gfc_conv_mpz_to_tree (stride, gfc_index_integer_kind);
+	tmp = gfc_conv_mpz_to_tree (stride, gfc_index_integer_kind);
       else
         tmp = NULL_TREE;
       GFC_TYPE_ARRAY_STRIDE (type, n) = tmp;
@@ -1103,6 +1104,24 @@ gfc_get_nodesc_array_type (tree etype, g
   mpz_clear (stride);
   mpz_clear (delta);
 
+  /* In debug info represent packed arrays as multi-dimensional
+     if they have rank > 1 and with proper bounds, instead of flat
+     arrays.  */
+  if (known_stride && write_symbols != NO_DEBUG)
+    {
+      tree gtype = etype, rtype, type_decl;
+
+      for (n = as->rank - 1; n >= 0; n--)
+	{
+	  rtype = build_range_type (gfc_array_index_type,
+				    GFC_TYPE_ARRAY_LBOUND (type, n),
+				    GFC_TYPE_ARRAY_UBOUND (type, n));
+	  gtype = build_array_type (gtype, rtype);
+	}
+      TYPE_NAME (type) = type_decl = build_decl (TYPE_DECL, NULL, gtype);
+      DECL_ORIGINAL_TYPE (type_decl) = gtype;
+    }
+
   if (packed < 3 || !known_stride)
     {
       /* For dummy arrays and automatic (heap allocated) arrays we

gcc41-pr28690.patch:

--- NEW FILE gcc41-pr28690.patch ---
2007-06-26  Jakub Jelinek  <jakub at redhat.com>

	* defaults.h (TARGET_INDEX_OPERAND_FIRST): Define.
	* config/rs6000/rs6000.h (TARGET_INDEX_OPERAND_FIRST): Define.
	* optabs.c (emit_cmp_and_jump_insns): Don't call swap_operand
	twice.
	* rtlanal.c (commutative_operand_precedence): Only prefer
	REG_POINTER and MEM_POINTER operands over REG and MEM operands
	if TARGET_INDEX_OPERAND_FIRST.
	(swap_commutative_operands_p): Only sort on REGNO if
	TARGET_INDEX_OPERAND_FIRST.
	* tree-ssa-address.c (gen_addr_rtx): Only use simplify_gen_binary
	instead of gen_rtx_PLUS if TARGET_INDEX_OPERAND_FIRST.

2007-06-20  Peter Bergner  <bergner at vnet.ibm.com>

	PR middle-end/28690
	* optabs.c (emit_cmp_and_jump_insns): Allow EQ compares.
	* rtlanal.c (commutative_operand_precedence): Prefer both REG_POINTER
	and MEM_POINTER operands over REG and MEM operands.
	(swap_commutative_operands_p): In case of a tie, sort on REGNO.
	* tree-ssa-address.c (gen_addr_rtx): Use simplify_gen_binary
	instead of gen_rtx_PLUS.

--- gcc/defaults.h.jj	2007-02-20 22:39:12.000000000 +0100
+++ gcc/defaults.h	2007-06-26 00:32:16.000000000 +0200
@@ -785,6 +785,10 @@ Software Foundation, 51 Franklin Street,
 #define TARGET_C99_FUNCTIONS 0
 #endif
 
+#ifndef TARGET_INDEX_OPERAND_FIRST
+#define TARGET_INDEX_OPERAND_FIRST 0
+#endif
+
 /* Indicate that CLZ and CTZ are undefined at zero.  */
 #ifndef CLZ_DEFINED_VALUE_AT_ZERO
 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE)  0
--- gcc/config/rs6000/rs6000.h.jj	2007-02-20 22:39:00.000000000 +0100
+++ gcc/config/rs6000/rs6000.h	2007-06-26 00:33:32.000000000 +0200
@@ -57,6 +57,8 @@
 #define PPC405_ERRATUM77 0
 #endif
 
+#define TARGET_INDEX_OPERAND_FIRST (rs6000_cpu == PROCESSOR_POWER6)
+
 /* Common ASM definitions used by ASM_SPEC among the various targets
    for handling -mcpu=xxx switches.  */
 #define ASM_CPU_SPEC \
--- gcc/optabs.c.jj	2007-02-20 22:39:12.000000000 +0100
+++ gcc/optabs.c	2007-06-26 00:30:27.000000000 +0200
@@ -3673,12 +3673,16 @@ emit_cmp_and_jump_insns (rtx x, rtx y, e
   /* Swap operands and condition to ensure canonical RTL.  */
   if (swap_commutative_operands_p (x, y))
     {
-      /* If we're not emitting a branch, this means some caller
-         is out of sync.  */
-      gcc_assert (label);
+      enum rtx_code swapped_comparison = swap_condition (comparison);
+
+      /* If we're not emitting a branch, callers are required to pass
+	 operands in an order conforming to canonical RTL.  We relax this
+	 for commutative comparsions so callers using EQ don't need to do
+	 swapping by hand.  */
+      gcc_assert (label || swapped_comparison == comparison);
 
       op0 = y, op1 = x;
-      comparison = swap_condition (comparison);
+      comparison = swapped_comparison;
     }
 
 #ifdef HAVE_cc0
--- gcc/rtlanal.c.jj	2007-02-20 22:39:12.000000000 +0100
+++ gcc/rtlanal.c	2007-06-26 00:28:56.000000000 +0200
@@ -2890,9 +2890,9 @@ commutative_operand_precedence (rtx op)
   
   /* Constants always come the second operand.  Prefer "nice" constants.  */
   if (code == CONST_INT)
-    return -7;
+    return -10;
   if (code == CONST_DOUBLE)
-    return -6;
+    return -9;
   op = avoid_constant_pool_reference (op);
   code = GET_CODE (op);
 
@@ -2900,26 +2900,31 @@ commutative_operand_precedence (rtx op)
     {
     case RTX_CONST_OBJ:
       if (code == CONST_INT)
-        return -5;
+	return -8;
       if (code == CONST_DOUBLE)
-        return -4;
-      return -3;
+	return -7;
+      return -6;
 
     case RTX_EXTRA:
       /* SUBREGs of objects should come second.  */
       if (code == SUBREG && OBJECT_P (SUBREG_REG (op)))
-        return -2;
+	return -5;
 
       if (!CONSTANT_P (op))
         return 0;
       else
 	/* As for RTX_CONST_OBJ.  */
-	return -3;
+	return -6;
 
     case RTX_OBJ:
       /* Complex expressions should be the first, so decrease priority
          of objects.  */
-      return -1;
+      if (!TARGET_INDEX_OPERAND_FIRST)
+	return -1;
+      if (REG_P (op))
+	return (REG_POINTER (op)) ? -1 : -3;
+      else
+	return (MEM_P (op) && MEM_POINTER (op)) ? -2 : -4;
 
     case RTX_COMM_ARITH:
       /* Prefer operands that are themselves commutative to be first.
@@ -2949,8 +2954,16 @@ commutative_operand_precedence (rtx op)
 int
 swap_commutative_operands_p (rtx x, rtx y)
 {
-  return (commutative_operand_precedence (x)
-	  < commutative_operand_precedence (y));
+  int result = (commutative_operand_precedence (x)
+		- commutative_operand_precedence (y));
+  if (!TARGET_INDEX_OPERAND_FIRST || result)
+    return result < 0;
+
+  /* Group together equal REGs to do more simplification.  */
+  if (REG_P (x) && REG_P (y))
+    return REGNO (x) > REGNO (y);
+
+  return 0;
 }
 
 /* Return 1 if X is an autoincrement side effect and the register is
--- gcc/tree-ssa-address.c.jj	2007-02-20 22:39:12.000000000 +0100
+++ gcc/tree-ssa-address.c	2007-06-26 00:29:49.000000000 +0200
@@ -124,7 +124,9 @@ gen_addr_rtx (rtx symbol, rtx base, rtx 
   if (base)
     {
       if (*addr)
-	*addr = gen_rtx_PLUS (Pmode, *addr, base);
+	*addr = (TARGET_INDEX_OPERAND_FIRST
+		 ? simplify_gen_binary (PLUS, Pmode, base, *addr)
+		 : gen_rtx_PLUS (Pmode, *addr, base));
       else
 	*addr = base;
     }

gcc41-pr32139.patch:

--- NEW FILE gcc41-pr32139.patch ---
2007-06-01  Jakub Jelinek  <jakub at redhat.com>

	PR tree-optimization/32139
	* c-typeck.c (common_pointer_type): Set TYPE_READONLY
	and TYPE_VOLATILE on the merged pointed to FUNCTION_TYPE
	only if both pointed_to_1 and pointed_to_2 are TYPE_READONLY
	resp. TYPE_VOLATILE.

	* gcc.c-torture/compile/20070531-1.c: New test.

--- gcc/c-typeck.c.jj	2007-04-25 10:13:52.000000000 +0200
+++ gcc/c-typeck.c	2007-06-01 10:51:53.000000000 +0200
@@ -499,6 +499,7 @@ common_pointer_type (tree t1, tree t2)
   tree pointed_to_1, mv1;
   tree pointed_to_2, mv2;
   tree target;
+  int type_quals;
 
   /* Save time if the two types are the same.  */
 
@@ -526,10 +527,19 @@ common_pointer_type (tree t1, tree t2)
   if (TREE_CODE (mv2) != ARRAY_TYPE)
     mv2 = TYPE_MAIN_VARIANT (pointed_to_2);
   target = composite_type (mv1, mv2);
-  t1 = build_pointer_type (c_build_qualified_type
-			   (target,
-			    TYPE_QUALS (pointed_to_1) |
-			    TYPE_QUALS (pointed_to_2)));
+  type_quals = TYPE_QUALS (pointed_to_1) | TYPE_QUALS (pointed_to_2);
+  if (TREE_CODE (pointed_to_1) == FUNCTION_TYPE)
+    {
+      /* TYPE_READONLY and TYPE_VOLATILE on FUNCTION_TYPE should be
+	 logically ANDed, not ORed, as if one function is
+	 __attribute__((const)) and the other is not, the common type
+	 must be conservatively not __attribute__((const))
+	 and similarly for __attribute__((noreturn)).  */
+      type_quals &= ~(TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE);
+      type_quals |= (TYPE_QUALS (pointed_to_1) & TYPE_QUALS (pointed_to_2))
+		    & (TYPE_QUAL_CONST | TYPE_QUAL_VOLATILE);
+    }
+  t1 = build_pointer_type (c_build_qualified_type (target, type_quals));
   return build_type_attribute_variant (t1, attributes);
 }
 
--- gcc/testsuite/gcc.c-torture/compile/20070531-1.c.jj	2007-05-31 13:47:22.000000000 +0200
+++ gcc/testsuite/gcc.c-torture/compile/20070531-1.c	2007-06-01 10:57:15.000000000 +0200
@@ -0,0 +1,11 @@
+/* PR tree-optimization/32139 */
+int foo (void);
+int bar (void) __attribute__ ((const));
+
+int
+test (int x)
+{
+  int a = (x == 10000 ? foo : bar) ();
+  int b = (x == 10000 ? foo : bar) ();
+  return a + b;
+}

gcc41-pr32678.patch:

--- NEW FILE gcc41-pr32678.patch ---
2007-07-21  Jerry DeLisle  <jvdelisle at gcc.gnu.org>

	PR libgfortran/32678
	* io/transfer.c (formatted_transfer_scalar): Fix off by one error in
	calculation of pos and skips. Don't allow pending_spaces to go
	negative.

	PR fortran/32678
	* gfortran.dg/fmt_t_5.f90: New test.

--- libgfortran/io/transfer.c	(revision 126821)
+++ libgfortran/io/transfer.c	(revision 126823)
@@ -893,9 +893,9 @@ formatted_transfer_scalar (st_parameter_
 	case FMT_TR:
 	  consume_data_flag = 0 ;
 
-	  pos = bytes_used + f->u.n + dtp->u.p.skips;
-	  dtp->u.p.skips = f->u.n + dtp->u.p.skips;
-	  dtp->u.p.pending_spaces = pos - dtp->u.p.max_pos;
+	  dtp->u.p.skips += f->u.n;
+	  pos = bytes_used + dtp->u.p.skips - 1;
+	  dtp->u.p.pending_spaces = pos - dtp->u.p.max_pos + 1;
 
 	  /* Writes occur just before the switch on f->format, above, so
 	     that trailing blanks are suppressed, unless we are doing a
@@ -922,8 +922,6 @@ formatted_transfer_scalar (st_parameter_
 	      if (bytes_used == 0)
 		{
 		  dtp->u.p.pending_spaces -= f->u.n;
-		  dtp->u.p.pending_spaces = dtp->u.p.pending_spaces < 0 ? 0
-					    : dtp->u.p.pending_spaces;
 		  dtp->u.p.skips -= f->u.n;
 		  dtp->u.p.skips = dtp->u.p.skips < 0 ? 0 : dtp->u.p.skips;
 		}
@@ -945,6 +943,8 @@ formatted_transfer_scalar (st_parameter_
 	  dtp->u.p.skips = dtp->u.p.skips + pos - bytes_used;
 	  dtp->u.p.pending_spaces = dtp->u.p.pending_spaces
 				    + pos - dtp->u.p.max_pos;
+	  dtp->u.p.pending_spaces = dtp->u.p.pending_spaces < 0
+				    ? 0 : dtp->u.p.pending_spaces;
 
 	  if (dtp->u.p.skips == 0)
 	    break;
--- gcc/testsuite/gfortran.dg/fmt_t_5.f90	(revision 126821)
+++ gcc/testsuite/gfortran.dg/fmt_t_5.f90	(revision 126823)
@@ -0,0 +1,17 @@
+! { dg-do run }
+! PR32678 GFortan works incorrectly when writing with FORMAT Tx
+! Before patch, NULLs were inserted in output.
+! Test case from reporter enhanced to detect this problem.
+      character(25) :: output
+      character(1)  :: c
+      output = ""
+      open (unit=10, file="pr32678testfile", status="replace")
+      write (10,10) '12','a','b'
+      close (10, status="keep")
+      open (unit=10, file="pr32678testfile")
+      read(10,20) output(1:21)
+      if (output(1:21).ne."ab                  x") call abort
+      close (10, status="delete")
+ 10   format (a2,t1,a1,t2,a1,t20,' x')
+ 20   format (a21)
+      end

gcc41-pr32912.patch:

--- NEW FILE gcc41-pr32912.patch ---
2007-08-20  Jakub Jelinek  <jakub at redhat.com>

	PR middle-end/32912
	* fold-const.c (fold_binary): Only optimize X | ~X and X ^ ~X for
	integral types.

	* gcc.dg/pr32912-1.c: New test.
	* gcc.dg/pr32912-2.c: New test.

--- gcc/fold-const.c.jj	2007-08-13 15:11:18.000000000 +0200
+++ gcc/fold-const.c	2007-08-20 15:49:05.000000000 +0200
@@ -8079,6 +8079,7 @@ fold_binary (enum tree_code code, tree t
 
       /* ~X | X is -1.  */
       if (TREE_CODE (arg0) == BIT_NOT_EXPR
+	  && INTEGRAL_TYPE_P (TREE_TYPE (arg1))
 	  && operand_equal_p (TREE_OPERAND (arg0, 0), arg1, 0))
 	{
 	  t1 = build_int_cst (type, -1);
@@ -8088,6 +8089,7 @@ fold_binary (enum tree_code code, tree t
 
       /* X | ~X is -1.  */
       if (TREE_CODE (arg1) == BIT_NOT_EXPR
+	  && INTEGRAL_TYPE_P (TREE_TYPE (arg0))
 	  && operand_equal_p (arg0, TREE_OPERAND (arg1, 0), 0))
 	{
 	  t1 = build_int_cst (type, -1);
@@ -8175,6 +8177,7 @@ fold_binary (enum tree_code code, tree t
 
       /* ~X ^ X is -1.  */
       if (TREE_CODE (arg0) == BIT_NOT_EXPR
+	  && INTEGRAL_TYPE_P (TREE_TYPE (arg1))
 	  && operand_equal_p (TREE_OPERAND (arg0, 0), arg1, 0))
 	{
 	  t1 = build_int_cst (type, -1);
@@ -8184,6 +8187,7 @@ fold_binary (enum tree_code code, tree t
 
       /* X ^ ~X is -1.  */
       if (TREE_CODE (arg1) == BIT_NOT_EXPR
+	  && INTEGRAL_TYPE_P (TREE_TYPE (arg0))
 	  && operand_equal_p (arg0, TREE_OPERAND (arg1, 0), 0))
 	{
 	  t1 = build_int_cst (type, -1);
--- gcc/testsuite/gcc.dg/pr32912-1.c.jj	2007-08-20 14:43:05.000000000 +0200
+++ gcc/testsuite/gcc.dg/pr32912-1.c	2007-08-20 14:43:23.000000000 +0200
@@ -0,0 +1,44 @@
+/* PR middle-end/32912 */
+/* { dg-do run } */
+/* { dg-options "-O2 -w" } */
+
+extern void abort (void);
+
+typedef int __m128i __attribute__ ((__vector_size__ (16)));
+
+__m128i a, b, c, d, e, f;
+
+void
+foo (__m128i x)
+{
+  a = x ^ ~x;
+  b = ~x ^ x;
+  c = x | ~x;
+  d = ~x | x;
+  e = x & ~x;
+  f = ~x & x;
+}
+
+int
+main (void)
+{
+  union { __m128i v; int i[sizeof (__m128i) / sizeof (int)]; } u;
+  int i;
+
+  for (i = 0; i < sizeof (u.i) / sizeof (u.i[0]); i++)
+    u.i[i] = i * 49 - 36;
+  foo (u.v);
+#define check(x, val) \
+  u.v = (x); \
+  for (i = 0; i < sizeof (u.i) / sizeof (u.i[0]); i++) \
+    if (u.i[i] != (val)) \
+      abort ()
+
+  check (a, ~0);
+  check (b, ~0);
+  check (c, ~0);
+  check (d, ~0);
+  check (e, 0);
+  check (f, 0);
+  return 0;
+}
--- gcc/testsuite/gcc.dg/pr32912-2.c.jj	2007-08-20 15:58:47.000000000 +0200
+++ gcc/testsuite/gcc.dg/pr32912-2.c	2007-08-20 15:55:32.000000000 +0200
@@ -0,0 +1,45 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -w" } */
+
+extern void abort (void);
+
+typedef int __m128i __attribute__ ((__vector_size__ (16)));
+
+__m128i a, b, c, d, e, f;
+
+__m128i
+foo (void)
+{
+  __m128i x = { 0x11111111, 0x22222222, 0x44444444 };
+  return x;
+}
+
+__m128i
+bar (void)
+{
+  __m128i x = { 0x11111111, 0x22222222, 0x44444444 };
+  return ~x;
+}
+
+int
+main (void)
+{
+  union { __m128i v; int i[sizeof (__m128i) / sizeof (int)]; } u, v;
+  int i;
+
+  u.v = foo ();
+  v.v = bar ();
+  for (i = 0; i < sizeof (u.i) / sizeof (u.i[0]); i++)
+    {
+      if (u.i[i] != ~v.i[i])
+	abort ();
+      if (i < 3)
+	{
+	  if (u.i[i] != (0x11111111 << i))
+	    abort ();
+	}
+      else if (u.i[i])
+	abort ();
+    }
+  return 0;
+}

gcc41-rh247256.patch:

--- NEW FILE gcc41-rh247256.patch ---
2007-07-10  Jakub Jelinek  <jakub at redhat.com>

	* simplify-rtx.c (simplify_plus_minus_op_data_cmp): If both operands
	are REGs and TARGET_INDEX_OPERAND_FIRST, sort lower REGNOs first.

	* gcc.dg/20070710-1.c: New test.

--- gcc/simplify-rtx.c.jj	2006-08-11 17:32:05.000000000 +0200
+++ gcc/simplify-rtx.c	2007-07-09 22:53:26.000000000 +0200
@@ -2608,6 +2608,12 @@ simplify_plus_minus_op_data_cmp (const v
 	    - commutative_operand_precedence (d1->op));
   if (result)
     return result;
+
+  /* Group together equal REGs to do more simplification.  */
+  if (TARGET_INDEX_OPERAND_FIRST && REG_P (d1->op) && REG_P (d2->op)
+      && REGNO (d1->op) != REGNO (d2->op))
+    return REGNO (d1->op) - REGNO (d2->op);
+
   return d1->ix - d2->ix;
 }
 
--- gcc/testsuite/gcc.dg/20070710-1.c.jj	2007-07-10 09:32:43.000000000 +0200
+++ gcc/testsuite/gcc.dg/20070710-1.c	2007-07-10 09:31:39.000000000 +0200
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -ffast-math" } */
+
+extern float sqrtf (float);
+
+float
+foo (const float *m)
+{
+  float x = m[0] + m[1] + m[2] + 1.0f;
+  float s;
+
+  if (x > 0.001)
+    s = 0.5f / sqrtf (x);
+  else
+    s = 2.0f * sqrtf (1.0f + m[0] - m[1] - m[2]);
+  return s;
+}

gcc41-rh253102.patch:

--- NEW FILE gcc41-rh253102.patch ---
2007-08-17  Jakub Jelinek  <jakub at redhat.com>

	* decl.c (variable_decl): Don't share charlen structs if
	length == NULL.
	* trans-decl.c (create_function_arglist): Assert
	f->sym->ts.cl->backend_decl is NULL instead of unsharing
	charlen struct here.

	* gfortran.dg/assumed_charlen_sharing.f90: New test.

--- gcc/fortran/decl.c.jj	2007-02-20 22:38:20.000000000 +0100
+++ gcc/fortran/decl.c	2007-08-21 20:50:33.000000000 +0200
@@ -1086,10 +1086,11 @@ variable_decl (int elem)
 	  break;
 
 	/* Non-constant lengths need to be copied after the first
-	   element.  */
+	   element.  Also copy assumed lengths.  */
 	case MATCH_NO:
-	  if (elem > 1 && current_ts.cl->length
-		&& current_ts.cl->length->expr_type != EXPR_CONSTANT)
+	  if (elem > 1
+	      && (current_ts.cl->length == NULL
+		  || current_ts.cl->length->expr_type != EXPR_CONSTANT))
 	    {
 	      cl = gfc_get_charlen ();
 	      cl->next = gfc_current_ns->cl_list;
--- gcc/fortran/trans-decl.c.jj	2007-03-12 08:28:13.000000000 +0100
+++ gcc/fortran/trans-decl.c	2007-08-21 20:50:33.000000000 +0200
@@ -1417,25 +1417,8 @@ create_function_arglist (gfc_symbol * sy
 	  if (!f->sym->ts.cl->length)
 	    {
 	      TREE_USED (length) = 1;
-	      if (!f->sym->ts.cl->backend_decl)
-		f->sym->ts.cl->backend_decl = length;
-	      else
-		{
-		  /* there is already another variable using this
-		     gfc_charlen node, build a new one for this variable
-		     and chain it into the list of gfc_charlens.
-		     This happens for e.g. in the case
-		     CHARACTER(*)::c1,c2
-		     since CHARACTER declarations on the same line share
-		     the same gfc_charlen node.  */
-		  gfc_charlen *cl;
-	      
-		  cl = gfc_get_charlen ();
-		  cl->backend_decl = length;
-		  cl->next = f->sym->ts.cl->next;
-		  f->sym->ts.cl->next = cl;
-		  f->sym->ts.cl = cl;
-		}
+	      gcc_assert (!f->sym->ts.cl->backend_decl);
+	      f->sym->ts.cl->backend_decl = length;
 	    }
 
 	  hidden_typelist = TREE_CHAIN (hidden_typelist);
--- gcc/testsuite/gfortran.dg/assumed_charlen_sharing.f90.jj	2007-08-21 08:29:57.000000000 +0200
+++ gcc/testsuite/gfortran.dg/assumed_charlen_sharing.f90	2007-08-21 08:29:57.000000000 +0200
@@ -0,0 +1,29 @@
+! This testcase was miscompiled, because ts.cl
+! in function bar was initially shared between both
+! dummy arguments.  Although it was later unshared,
+! all expressions which copied ts.cl from bar2
+! before that used incorrectly bar1's length
+! instead of bar2.
+! { dg-do run }
+
+subroutine foo (foo1, foo2)
+  implicit none
+  integer, intent(in) :: foo2
+  character(*), intent(in) :: foo1(foo2)
+end subroutine foo
+
+subroutine bar (bar1, bar2)
+  implicit none
+  character(*), intent(in) :: bar1, bar2
+
+  call foo ((/ bar2 /), 1)
+end subroutine bar
+
+program test
+  character(80) :: str1
+  character(5) :: str2
+
+  str1 = 'String'
+  str2 = 'Strng'
+  call bar (str2, str1)
+end program test

gcc41-sparc-niagara.patch:

--- NEW FILE gcc41-sparc-niagara.patch ---
2006-03-02  David S. Miller  <davem at sunset.davemloft.net>

	Sun Niagara specific optimizations.
	* config.gcc: Recognize niagara as target.
	* config/sparc/sparc.h (SPARC_RELAXED_ORDERING): Mention Niagara.
	(TARGET_CPU_niagara): Define.
	(CPP_CPU64_DEFAULT_SPEC): Define __sparc_v9__ for Niagara.
	(ASM_CPU64_DEFAULT_SPEC): Pass -Av9b for Niagara.
	(CPP_CPU_SPEC): Handle -mcpu=niagara.
	(ASM_CPU_SPEC): Likewise.
	(PROCESSOR_NIAGARA): New enum entry.
	(REGISTER_MOVE_COST): Handle Niagara.
	(BRANCH_COST, PREFETCH_BLOCK, SIMULTANEOUS_PREFETCHES): Likewise.
	* config/sparc/sparc.c (niagara_costs): New processor_costs entry.
	(sparc_override_options): Recognize "niagara", set appropriate
	default MASK_* values for it, and align functions to 32-bytes
	by default just like ULTRASPARC/ULTRASPARC3.
	(sparc_initialize_trampoline): Handle niagara like ultrasparc.
	(sparc64_initialize_trampoline): Likewise.
	(sparc_use_sched_lookahead): Use zero for niagara.
	(sparc_issue_rate): Use one for niagara.
	* config/sparc/niagara.md: New file.
	* config/sparc/sparc.md: Include it.
	* config/sparc/sol2-bi.h (CPP_CPU64_DEFAULT_SPEC,
	ASM_CPU32_DEFAULT_SPEC, ASM_CPU64_DEFAULT_SPEC): Set appropriately
	when default cpu is niagara.
	(CPP_CPU_SPEC): Handle -mcpu=niagara.
	(ASM_CPU_SPEC): Likewise.
	* config/sparc/sol2.h (ASM_CPU_DEFAULT_SPEC): Set appropriately
	when default cpu is niagara.
	(ASM_CPU_SPEC): Handle -mcpu=niagara.
	* config/sparc/linux64.h: Handle a default of TARGET_CPU_niagara
	just like v9/ultrasparc/ultrasparc3.
	* doc/invoke.texi: Add documentation for "niagara" and improve
	existing documentation for ultrasparc variants.

--- gcc/doc/invoke.texi	(revision 111647)
+++ gcc/doc/invoke.texi	(revision 111648)
@@ -12268,8 +12268,8 @@ Set the instruction set, register set, a
 for machine type @var{cpu_type}.  Supported values for @var{cpu_type} are
 @samp{v7}, @samp{cypress}, @samp{v8}, @samp{supersparc}, @samp{sparclite},
 @samp{f930}, @samp{f934}, @samp{hypersparc}, @samp{sparclite86x},
- at samp{sparclet}, @samp{tsc701}, @samp{v9}, @samp{ultrasparc}, and
- at samp{ultrasparc3}.
+ at samp{sparclet}, @samp{tsc701}, @samp{v9}, @samp{ultrasparc},
+ at samp{ultrasparc3}, and @samp{niagara}.
 
 Default instruction scheduling parameters are used for values that select
 an architecture and not an implementation.  These are @samp{v7}, @samp{v8},
@@ -12283,7 +12283,7 @@ implementations.
     v8:             supersparc, hypersparc
     sparclite:      f930, f934, sparclite86x
     sparclet:       tsc701
-    v9:             ultrasparc, ultrasparc3
+    v9:             ultrasparc, ultrasparc3, niagara
 @end smallexample
 
 By default (unless configured otherwise), GCC generates code for the V7
@@ -12317,9 +12317,11 @@ With @option{-mcpu=v9}, GCC generates co
 architecture.  This adds 64-bit integer and floating-point move instructions,
 3 additional floating-point condition code registers and conditional move
 instructions.  With @option{-mcpu=ultrasparc}, the compiler additionally
-optimizes it for the Sun UltraSPARC I/II chips.  With
+optimizes it for the Sun UltraSPARC I/II/IIi chips.  With
 @option{-mcpu=ultrasparc3}, the compiler additionally optimizes it for the
-Sun UltraSPARC III chip.
+Sun UltraSPARC III/III+/IIIi/IIIi+/IV/IV+ chips.  With
+ at option{-mcpu=niagara}, the compiler additionally optimizes it for
+Sun UltraSPARC T1 chips.
 
 @item -mtune=@var{cpu_type}
 @opindex mtune
@@ -12331,8 +12333,8 @@ The same values for @option{-mcpu=@var{c
 @option{-mtune=@var{cpu_type}}, but the only useful values are those
 that select a particular cpu implementation.  Those are @samp{cypress},
 @samp{supersparc}, @samp{hypersparc}, @samp{f930}, @samp{f934},
- at samp{sparclite86x}, @samp{tsc701}, @samp{ultrasparc}, and
- at samp{ultrasparc3}.
+ at samp{sparclite86x}, @samp{tsc701}, @samp{ultrasparc},
+ at samp{ultrasparc3}, and @samp{niagara}.
 
 @item -mv8plus
 @itemx -mno-v8plus
--- gcc/config.gcc	(revision 111647)
+++ gcc/config.gcc	(revision 111648)
@@ -2830,7 +2830,7 @@ case "${target}" in
 			"" | sparc | sparcv9 | sparc64 | sparc86x \
 			| v7 | cypress | v8 | supersparc | sparclite | f930 \
 			| f934 | hypersparc | sparclite86x | sparclet | tsc701 \
-			| v9 | ultrasparc | ultrasparc3)
+			| v9 | ultrasparc | ultrasparc3 | niagara)
 				# OK
 				;;
 			*)
--- gcc/config/sparc/niagara.md	(revision 0)
+++ gcc/config/sparc/niagara.md	(revision 111648)
@@ -0,0 +1,119 @@
+;; Scheduling description for Niagara.
+;;   Copyright (C) 2006 Free Software Foundation, Inc.
+;;
+;; This file is part of GCC.
+;;
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 2, or (at your option)
+;; any later version.
+;;
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+;;
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING.  If not, write to
+;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
+;; Boston, MA 02110-1301, USA.
+
+;; Niagara is a single-issue processor.
+
+(define_automaton "niagara_0")
+
+(define_cpu_unit "niag_pipe" "niagara_0")
+
+(define_insn_reservation "niag_5cycle" 5
+  (and (eq_attr "cpu" "niagara")
+    (eq_attr "type" "multi,flushw,iflush,trap"))
+  "niag_pipe*5")
+
+(define_insn_reservation "niag_4cycle" 4
+  (and (eq_attr "cpu" "niagara")
+    (eq_attr "type" "savew"))
+  "niag_pipe*4")
+
+/* Most basic operations are single-cycle. */
+(define_insn_reservation "niag_ialu" 1
+ (and (eq_attr "cpu" "niagara")
+   (eq_attr "type" "ialu,shift,compare,cmove"))
+ "niag_pipe")
+
+(define_insn_reservation "niag_imul" 11
+ (and (eq_attr "cpu" "niagara")
+   (eq_attr "type" "imul"))
+ "niag_pipe*11")
+
+(define_insn_reservation "niag_idiv" 72
+ (and (eq_attr "cpu" "niagara")
+   (eq_attr "type" "idiv"))
+ "niag_pipe*72")
+
+(define_insn_reservation "niag_branch" 3
+  (and (eq_attr "cpu" "niagara")
+    (eq_attr "type" "call,sibcall,call_no_delay_slot,uncond_branch,branch"))
+  "niag_pipe*3")
+
+(define_insn_reservation "niag_3cycle_load" 3
+  (and (eq_attr "cpu" "niagara")
+    (eq_attr "type" "load"))
+  "niag_pipe*3")
+
+(define_insn_reservation "niag_9cycle_load" 9
+  (and (eq_attr "cpu" "niagara")
+    (eq_attr "type" "fpload"))
+  "niag_pipe*9")
+
+(define_insn_reservation "niag_1cycle_store" 1
+  (and (eq_attr "cpu" "niagara")
+    (eq_attr "type" "store"))
+  "niag_pipe")
+
+(define_insn_reservation "niag_8cycle_store" 8
+  (and (eq_attr "cpu" "niagara")
+    (eq_attr "type" "fpstore"))
+  "niag_pipe*8")
+
+/* Things incorrectly modelled here:
+ *  FPADD{s,d}: 26 cycles
+ *  FPSUB{s,d}: 26 cycles
+ *  FABSD: 26 cycles
+ *  F{s,d}TO{s,d}: 26 cycles
+ *  F{s,d}TO{i,x}: 26 cycles
+ *  FSMULD: 29 cycles
+ */
+(define_insn_reservation "niag_fmov" 8
+  (and (eq_attr "cpu" "niagara")
+    (eq_attr "type" "fpmove,fpcmove,fpcrmove"))
+  "niag_pipe*8")
+
+(define_insn_reservation "niag_fpcmp" 26
+  (and (eq_attr "cpu" "niagara")
+    (eq_attr "type" "fpcmp"))
+  "niag_pipe*26")
+
+(define_insn_reservation "niag_fmult" 29
+ (and (eq_attr "cpu" "niagara")
+    (eq_attr "type" "fpmul"))
+  "niag_pipe*29")
+
+(define_insn_reservation "niag_fdivs" 54
+  (and (eq_attr "cpu" "niagara")
+    (eq_attr "type" "fpdivs"))
+  "niag_pipe*54")
+
+(define_insn_reservation "niag_fdivd" 83
+  (and (eq_attr "cpu" "niagara")
+    (eq_attr "type" "fpdivd"))
+  "niag_pipe*83")
+
+/* Things incorrectly modelled here:
+ *  FPADD{16,32}: 10 cycles
+ *  FPSUB{16,32}: 10 cycles
+ *  FALIGNDATA: 10 cycles
+ */
+(define_insn_reservation "niag_vis" 8
+  (and (eq_attr "cpu" "niagara")
+    (eq_attr "type" "fga,fgm_pack,fgm_mul,fgm_cmp,fgm_pdist"))
+  "niag_pipe*8")
--- gcc/config/sparc/sparc.md	(revision 111647)
+++ gcc/config/sparc/sparc.md	(revision 111648)
@@ -94,7 +94,8 @@ (define_attr "cpu"
    sparclet,tsc701,
    v9,
    ultrasparc,
-   ultrasparc3"
+   ultrasparc3,
+   niagara"
   (const (symbol_ref "sparc_cpu_attr")))
 
 ;; Attribute for the instruction set.
@@ -315,6 +316,7 @@ (define_delay (eq_attr "type" "return")
 (include "sparclet.md")
 (include "ultra1_2.md")
 (include "ultra3.md")
+(include "niagara.md")
 
 
 ;; Operand and operator predicates.
--- gcc/config/sparc/sparc.c	(revision 111647)
+++ gcc/config/sparc/sparc.c	(revision 111648)
@@ -197,6 +197,30 @@ struct processor_costs ultrasparc3_costs
   0, /* shift penalty */
 };
 
+static const
+struct processor_costs niagara_costs = {
+  COSTS_N_INSNS (3), /* int load */
+  COSTS_N_INSNS (3), /* int signed load */
+  COSTS_N_INSNS (3), /* int zeroed load */
+  COSTS_N_INSNS (9), /* float load */
+  COSTS_N_INSNS (8), /* fmov, fneg, fabs */
+  COSTS_N_INSNS (8), /* fadd, fsub */
+  COSTS_N_INSNS (26), /* fcmp */
+  COSTS_N_INSNS (8), /* fmov, fmovr */
+  COSTS_N_INSNS (29), /* fmul */
+  COSTS_N_INSNS (54), /* fdivs */
+  COSTS_N_INSNS (83), /* fdivd */
+  COSTS_N_INSNS (100), /* fsqrts - not implemented in hardware */
+  COSTS_N_INSNS (100), /* fsqrtd - not implemented in hardware */
+  COSTS_N_INSNS (11), /* imul */
+  COSTS_N_INSNS (11), /* imulX */
+  0, /* imul bit factor */
+  COSTS_N_INSNS (72), /* idiv */
+  COSTS_N_INSNS (72), /* idivX */
+  COSTS_N_INSNS (1), /* movcc/movr */
+  0, /* shift penalty */
+};
+
 const struct processor_costs *sparc_costs = &cypress_costs;
 
 #ifdef HAVE_AS_RELAX_OPTION
@@ -597,6 +621,7 @@ sparc_override_options (void)
     { TARGET_CPU_v9, "v9" },
     { TARGET_CPU_ultrasparc, "ultrasparc" },
     { TARGET_CPU_ultrasparc3, "ultrasparc3" },
+    { TARGET_CPU_niagara, "niagara" },
     { 0, 0 }
   };
   const struct cpu_default *def;
@@ -632,6 +657,8 @@ sparc_override_options (void)
     /* TI ultrasparc III */
     /* ??? Check if %y issue still holds true in ultra3.  */
     { "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
+    /* UltraSPARC T1 */
+    { "niagara", PROCESSOR_NIAGARA, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
     { 0, 0, 0, 0 }
   };
   const struct cpu_table *cpu;
@@ -741,7 +768,8 @@ sparc_override_options (void)
   /* Supply a default value for align_functions.  */
   if (align_functions == 0
       && (sparc_cpu == PROCESSOR_ULTRASPARC
-	  || sparc_cpu == PROCESSOR_ULTRASPARC3))
+	  || sparc_cpu == PROCESSOR_ULTRASPARC3
+	  || sparc_cpu == PROCESSOR_NIAGARA))
     align_functions = 32;
 
   /* Validate PCC_STRUCT_RETURN.  */
@@ -790,6 +818,9 @@ sparc_override_options (void)
     case PROCESSOR_ULTRASPARC3:
       sparc_costs = &ultrasparc3_costs;
       break;
+    case PROCESSOR_NIAGARA:
+      sparc_costs = &niagara_costs;
+      break;
     };
 
 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128
@@ -7099,7 +7130,8 @@ sparc_initialize_trampoline (rtx tramp, 
      aligned on a 16 byte boundary so one flush clears it all.  */
   emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
   if (sparc_cpu != PROCESSOR_ULTRASPARC
-      && sparc_cpu != PROCESSOR_ULTRASPARC3)
+      && sparc_cpu != PROCESSOR_ULTRASPARC3
+      && sparc_cpu != PROCESSOR_NIAGARA)
     emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
 						     plus_constant (tramp, 8)))));
 
@@ -7141,7 +7173,8 @@ sparc64_initialize_trampoline (rtx tramp
   emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp))));
 
   if (sparc_cpu != PROCESSOR_ULTRASPARC
-      && sparc_cpu != PROCESSOR_ULTRASPARC3)
+      && sparc_cpu != PROCESSOR_ULTRASPARC3
+      && sparc_cpu != PROCESSOR_NIAGARA)
     emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
 
   /* Call __enable_execute_stack after writing onto the stack to make sure
@@ -7321,6 +7354,8 @@ sparc_sched_init (FILE *dump ATTRIBUTE_U
 static int
 sparc_use_sched_lookahead (void)
 {
+  if (sparc_cpu == PROCESSOR_NIAGARA)
+    return 0;
   if (sparc_cpu == PROCESSOR_ULTRASPARC
       || sparc_cpu == PROCESSOR_ULTRASPARC3)
     return 4;
@@ -7336,6 +7371,7 @@ sparc_issue_rate (void)
 {
   switch (sparc_cpu)
     {
+    case PROCESSOR_NIAGARA:
     default:
       return 1;
     case PROCESSOR_V9:
--- gcc/config/sparc/sol2-bi.h	(revision 111647)
+++ gcc/config/sparc/sol2-bi.h	(revision 111648)
@@ -39,6 +39,15 @@
 #define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG "b"
 #endif
 
+#if TARGET_CPU_DEFAULT == TARGET_CPU_niagara
+#undef CPP_CPU64_DEFAULT_SPEC
+#define CPP_CPU64_DEFAULT_SPEC ""
+#undef ASM_CPU32_DEFAULT_SPEC
+#define ASM_CPU32_DEFAULT_SPEC "-xarch=v8plusb"
+#undef ASM_CPU64_DEFAULT_SPEC
+#define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG "b"
+#endif
+
 #if DEFAULT_ARCH32_P
 #define DEF_ARCH32_SPEC(__str) "%{!m64:" __str "}"
 #define DEF_ARCH64_SPEC(__str) "%{m64:" __str "}"
@@ -57,7 +66,7 @@
 %{mcpu=sparclite|mcpu-f930|mcpu=f934:-D__sparclite__} \
 %{mcpu=v8:" DEF_ARCH32_SPEC("-D__sparcv8") "} \
 %{mcpu=supersparc:-D__supersparc__ " DEF_ARCH32_SPEC("-D__sparcv8") "} \
-%{mcpu=v9|mcpu=ultrasparc|mcpu=ultrasparc3:" DEF_ARCH32_SPEC("-D__sparcv8") "} \
+%{mcpu=v9|mcpu=ultrasparc|mcpu=ultrasparc3|mcpu=niagara:" DEF_ARCH32_SPEC("-D__sparcv8") "} \
 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \
 "
 
@@ -66,7 +75,8 @@
 %{mcpu=v9:" DEF_ARCH32_SPEC("-xarch=v8plus") DEF_ARCH64_SPEC(AS_SPARC64_FLAG) "} \
 %{mcpu=ultrasparc:" DEF_ARCH32_SPEC("-xarch=v8plusa") DEF_ARCH64_SPEC(AS_SPARC64_FLAG "a") "} \
 %{mcpu=ultrasparc3:" DEF_ARCH32_SPEC("-xarch=v8plusb") DEF_ARCH64_SPEC(AS_SPARC64_FLAG "b") "} \
-%{!mcpu=ultrasparc3:%{!mcpu=ultrasparc:%{!mcpu=v9:%{mcpu*:" DEF_ARCH32_SPEC("-xarch=v8") DEF_ARCH64_SPEC(AS_SPARC64_FLAG) "}}}} \
+%{mcpu=niagara:" DEF_ARCH32_SPEC("-xarch=v8plusb") DEF_ARCH64_SPEC(AS_SPARC64_FLAG "b") "} \
+%{!mcpu=niagara:%{!mcpu=ultrasparc3:%{!mcpu=ultrasparc:%{!mcpu=v9:%{mcpu*:" DEF_ARCH32_SPEC("-xarch=v8") DEF_ARCH64_SPEC(AS_SPARC64_FLAG) "}}}}} \
 %{!mcpu*:%(asm_cpu_default)} \
 "
 
--- gcc/config/sparc/sparc.h	(revision 111647)
+++ gcc/config/sparc/sparc.h	(revision 111648)
@@ -206,7 +206,7 @@ extern enum cmodel sparc_cmodel;
    which requires the following macro to be true if enabled.  Prior to V9,
    there are no instructions to even talk about memory synchronization.
    Note that the UltraSPARC III processors don't implement RMO, unlike the
-   UltraSPARC II processors.
+   UltraSPARC II processors.  Niagara does not implement RMO either.
 
    Default to false; for example, Solaris never enables RMO, only ever uses
    total memory ordering (TMO).  */
@@ -238,10 +238,12 @@ extern enum cmodel sparc_cmodel;
 #define TARGET_CPU_sparc64	7	/* alias */
 #define TARGET_CPU_ultrasparc	8
 #define TARGET_CPU_ultrasparc3	9
+#define TARGET_CPU_niagara	10
 
 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
  || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \
- || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3
+ || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 \
+ || TARGET_CPU_DEFAULT == TARGET_CPU_niagara
 
 #define CPP_CPU32_DEFAULT_SPEC ""
 #define ASM_CPU32_DEFAULT_SPEC ""
@@ -262,6 +264,10 @@ extern enum cmodel sparc_cmodel;
 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
 #define ASM_CPU64_DEFAULT_SPEC "-Av9b"
 #endif
+#if TARGET_CPU_DEFAULT == TARGET_CPU_niagara
+#define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
+#define ASM_CPU64_DEFAULT_SPEC "-Av9b"
+#endif
 
 #else
 
@@ -352,6 +358,7 @@ extern enum cmodel sparc_cmodel;
 %{mcpu=v9:-D__sparc_v9__} \
 %{mcpu=ultrasparc:-D__sparc_v9__} \
 %{mcpu=ultrasparc3:-D__sparc_v9__} \
+%{mcpu=niagara:-D__sparc_v9__} \
 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \
 "
 #define CPP_ARCH32_SPEC ""
@@ -401,6 +408,7 @@ extern enum cmodel sparc_cmodel;
 %{mcpu=v9:-Av9} \
 %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \
 %{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \
+%{mcpu=niagara:%{!mv8plus:-Av9b}} \
 %{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \
 "
 
@@ -524,7 +532,8 @@ enum processor_type {
   PROCESSOR_TSC701,
   PROCESSOR_V9,
   PROCESSOR_ULTRASPARC,
-  PROCESSOR_ULTRASPARC3
+  PROCESSOR_ULTRASPARC3,
+  PROCESSOR_NIAGARA
 };
 
 /* This is set from -m{cpu,tune}=xxx.  */
@@ -2137,7 +2146,8 @@ do {                                    
     || (GENERAL_OR_I64 (CLASS1) && FP_REG_CLASS_P (CLASS2)) \
     || (CLASS1) == FPCC_REGS || (CLASS2) == FPCC_REGS)		\
    ? ((sparc_cpu == PROCESSOR_ULTRASPARC \
-       || sparc_cpu == PROCESSOR_ULTRASPARC3) ? 12 : 6) : 2)
+       || sparc_cpu == PROCESSOR_ULTRASPARC3 \
+       || sparc_cpu == PROCESSOR_NIAGARA) ? 12 : 6) : 2)
 
 /* Provide the cost of a branch.  For pre-v9 processors we use
    a value of 3 to take into account the potential annulling of
@@ -2147,22 +2157,30 @@ do {                                    
 
    On v9 and later, which have branch prediction facilities, we set
    it to the depth of the pipeline as that is the cost of a
-   mispredicted branch.  */
+   mispredicted branch.
+
+   On Niagara, normal branches insert 3 bubbles into the pipe
+   and annulled branches insert 4 bubbles.  */
 
 #define BRANCH_COST \
 	((sparc_cpu == PROCESSOR_V9 \
 	  || sparc_cpu == PROCESSOR_ULTRASPARC) \
 	 ? 7 \
          : (sparc_cpu == PROCESSOR_ULTRASPARC3 \
-            ? 9 : 3))
+            ? 9 \
+	 : (sparc_cpu == PROCESSOR_NIAGARA \
+	    ? 4 \
+	 : 3)))
 
 #define PREFETCH_BLOCK \
 	((sparc_cpu == PROCESSOR_ULTRASPARC \
-          || sparc_cpu == PROCESSOR_ULTRASPARC3) \
+          || sparc_cpu == PROCESSOR_ULTRASPARC3 \
+	  || sparc_cpu == PROCESSOR_NIAGARA) \
          ? 64 : 32)
 
 #define SIMULTANEOUS_PREFETCHES \
-	((sparc_cpu == PROCESSOR_ULTRASPARC) \
+	((sparc_cpu == PROCESSOR_ULTRASPARC \
+	  || sparc_cpu == PROCESSOR_NIAGARA) \
          ? 2 \
          : (sparc_cpu == PROCESSOR_ULTRASPARC3 \
             ? 8 : 3))
--- gcc/config/sparc/linux64.h	(revision 111647)
+++ gcc/config/sparc/linux64.h	(revision 111648)
@@ -43,7 +43,8 @@ Boston, MA 02110-1301, USA.  */
 
 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
     || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \
-    || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3
+    || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 \
+    || TARGET_CPU_DEFAULT == TARGET_CPU_niagara
 /* A 64 bit v9 compiler with stack-bias,
    in a Medium/Low code model environment.  */
 
--- gcc/config/sparc/sol2.h	(revision 111647)
+++ gcc/config/sparc/sol2.h	(revision 111648)
@@ -41,11 +41,17 @@ Boston, MA 02110-1301, USA.  */
 #define ASM_CPU_DEFAULT_SPEC "-xarch=v8plusb"
 #endif
 
+#if TARGET_CPU_DEFAULT == TARGET_CPU_niagara
+#undef ASM_CPU_DEFAULT_SPEC
+#define ASM_CPU_DEFAULT_SPEC "-xarch=v8plusb"
+#endif
+
 #undef ASM_CPU_SPEC
 #define ASM_CPU_SPEC "\
 %{mcpu=v9:-xarch=v8plus} \
 %{mcpu=ultrasparc:-xarch=v8plusa} \
 %{mcpu=ultrasparc3:-xarch=v8plusb} \
+%{mcpu=niagara:-xarch=v8plusb} \
 %{!mcpu*:%(asm_cpu_default)} \
 "
 


Index: .cvsignore
===================================================================
RCS file: /cvs/pkgs/rpms/gcc/F-7/.cvsignore,v
retrieving revision 1.206
retrieving revision 1.207
diff -u -r1.206 -r1.207
--- .cvsignore	3 May 2007 21:56:10 -0000	1.206
+++ .cvsignore	27 Aug 2007 11:08:53 -0000	1.207
@@ -1 +1 @@
-gcc-4.1.2-20070503.tar.bz2
+gcc-4.1.2-20070821.tar.bz2


Index: gcc41.spec
===================================================================
RCS file: /cvs/pkgs/rpms/gcc/F-7/gcc41.spec,v
retrieving revision 1.160
retrieving revision 1.161
diff -u -r1.160 -r1.161
--- gcc41.spec	3 May 2007 21:56:10 -0000	1.160
+++ gcc41.spec	27 Aug 2007 11:08:53 -0000	1.161
@@ -1,6 +1,6 @@
-%define DATE 20070503
+%define DATE 20070821
 %define gcc_version 4.1.2
-%define gcc_release 12
+%define gcc_release 18
 %define _unpackaged_files_terminate_build 0
 %define multilib_64_archs sparc64 ppc64 s390x x86_64
 %define include_gappletviewer 1
@@ -25,8 +25,11 @@
 Summary: Various compilers (C, C++, Objective-C, Java, ...)
 Name: gcc
 Version: %{gcc_version}
-Release: %{gcc_release}
-License: GPL
+Release: %{gcc_release}%{?dist}
+# libgcc, libgfortran, libmudflap and crtstuff have an exception which allows
+# linking it into any kind of programs or shared libraries without
+# restrictions.
+License: GPLv2+ and GPLv2+ with exceptions
 Group: Development/Languages
 Source0: gcc-%{version}-%{DATE}.tar.bz2
 Source1: libgcc_post_upgrade.c
@@ -118,35 +121,33 @@
 Patch7: gcc41-ada-tweaks.patch
 Patch8: gcc41-java-slow_pthread_self.patch
 Patch9: gcc41-ppc32-retaddr.patch
-Patch10: gcc41-amdfam10.patch
-Patch11: gcc41-dsohandle.patch
-Patch12: gcc41-rh184446.patch
-Patch13: gcc41-pr20297-test.patch
-Patch14: gcc41-objc-rh185398.patch
-Patch15: gcc41-tests.patch
-Patch16: gcc41-hash-style-gnu.patch
-Patch17: gcc41-java-libdotdotlib.patch
-Patch18: gcc41-pr28709.patch
-Patch19: gcc41-pr28755.patch
-Patch20: gcc41-pr27898.patch
-Patch21: gcc41-pr27567.patch
-Patch22: gcc41-pr29272.patch
-Patch23: gcc41-pr29059.patch
-Patch24: gcc41-strncat-chk.patch
-Patch25: gcc41-pr29299.patch
-Patch26: gcc41-java-bogus-debugline.patch
-Patch27: gcc41-libjava-visibility.patch
-Patch28: gcc41-pr31187.patch
-Patch29: gcc41-dtor-relro.patch
-Patch30: gcc41-rh234515.patch
-Patch31: gcc41-libgomp-ncpus.patch
-Patch32: gcc41-rh236895.patch
-Patch33: gcc41-pr28482.patch
-Patch34: gcc41-rh235008.patch
-Patch35: gcc41-pr31748.patch
-Patch36: gcc41-tls-data-alignment.patch
-
+Patch10: gcc41-dsohandle.patch
+Patch11: gcc41-rh184446.patch
+Patch12: gcc41-pr20297-test.patch
+Patch13: gcc41-hash-style-gnu.patch
+Patch14: gcc41-java-libdotdotlib.patch
+Patch15: gcc41-pr28755.patch
+Patch16: gcc41-pr27898.patch
+Patch17: gcc41-java-bogus-debugline.patch
+Patch18: gcc41-libjava-visibility.patch
+Patch19: gcc41-pr32139.patch
+Patch20: gcc41-rh236895.patch
+Patch21: gcc41-rh235008.patch
+Patch22: gcc41-build-id.patch
+Patch23: gcc41-pr28690.patch
+Patch24: gcc41-rh247256.patch
+Patch25: gcc41-pr22244.patch
+Patch26: gcc41-pr32678.patch
+Patch27: gcc41-pr32912.patch
+Patch28: gcc41-sparc-niagara.patch
+Patch29: gcc41-ppc-tramp.patch
+Patch30: gcc41-rh253102.patch
+
+# On ARM EABI systems, we do want -gnueabi to be part of the
+# target triple.
+%ifnarch %{arm}
 %define _gnu %{nil}
+%endif
 %ifarch sparc
 %define gcc_target_platform sparc64-%{_vendor}-%{_target_os}
 %endif
@@ -433,33 +434,27 @@
 %patch7 -p0 -b .ada-tweaks~
 %patch8 -p0 -b .java-slow_pthread_self~
 %patch9 -p0 -b .ppc32-retaddr~
-%patch10 -p0 -b .amdfam10~
-%patch11 -p0 -b .dsohandle~
-%patch12 -p0 -b .rh184446~
-%patch13 -p0 -E -b .pr20297-test~
-%patch14 -p0 -b .objc-rh185398~
-%patch15 -p0 -b .tests~
-%patch16 -p0 -b .hash-style-gnu~
-%patch17 -p0 -b .java-libdotdotlib~
-%patch18 -p0 -b .pr28709~
-%patch19 -p0 -b .pr28755~
-%patch20 -p0 -b .pr27898~
-%patch21 -p0 -b .pr27567~
-%patch22 -p0 -b .pr29272~
-%patch23 -p0 -b .pr29059~
-%patch24 -p0 -b .strncat-chk~
-%patch25 -p0 -b .pr29299~
-%patch26 -p0 -b .java-bogus-debugline~
-%patch27 -p0 -b .libjava-visibility~
-%patch28 -p0 -b .pr31187~
-%patch29 -p0 -b .dtor-relro~
-%patch30 -p0 -b .rh234515~
-%patch31 -p0 -b .libgomp-ncpus~
-%patch32 -p0 -b .rh236895~
-%patch33 -p0 -b .pr28482~
-%patch34 -p0 -b .rh235008~
-%patch35 -p0 -b .pr31748~
-%patch36 -p0 -b .tls-data-alignment~
+%patch10 -p0 -b .dsohandle~
+%patch11 -p0 -b .rh184446~
+%patch12 -p0 -E -b .pr20297-test~
+%patch13 -p0 -b .hash-style-gnu~
+%patch14 -p0 -b .java-libdotdotlib~
+%patch15 -p0 -b .pr28755~
+%patch16 -p0 -b .pr27898~
+%patch17 -p0 -b .java-bogus-debugline~
+%patch18 -p0 -b .libjava-visibility~
+%patch19 -p0 -b .pr32139~
+%patch20 -p0 -b .rh236895~
+%patch21 -p0 -b .rh235008~
+#%patch22 -p0 -b .build-id~
+%patch23 -p0 -b .pr28690~
+%patch24 -p0 -b .rh247256~
+%patch25 -p0 -b .pr22244~
+%patch26 -p0 -b .pr32678~
+%patch27 -p0 -b .pr32912~
+%patch28 -p0 -b .sparc-niagara~
+%patch29 -p0 -b .ppc-tramp~
+%patch30 -p0 -b .rh253102~
 
 sed -i -e 's/4\.1\.3/4.1.2/' gcc/BASE-VER gcc/version.c
 sed -i -e 's/" (Red Hat[^)]*)"/" (Red Hat %{version}-%{gcc_release})"/' gcc/version.c
@@ -752,6 +747,17 @@
   fi
 done
 
+# Nuke bits/stdc++.h.gch dirs
+# 1) there is no bits/stdc++.h header installed, so when gch file can't be
+#    used, compilation fails
+# 2) sometimes it is hard to match the exact options used for building
+#    libstdc++-v3 or they aren't desirable
+# 3) there are multilib issues, conflicts etc. with this
+# 4) it is huge
+# People can always precompile on their own whatever they want, but
+# shipping this for everybody is unnecessary.
+rm -rf $RPM_BUILD_ROOT%{_prefix}/include/c++/%{gcc_version}/%{gcc_target_platform}/bits/stdc++.h.gch
+
 %ifarch sparc sparc64
 ln -f $RPM_BUILD_ROOT%{_prefix}/bin/%{gcc_target_platform}-gcc \
   $RPM_BUILD_ROOT%{_prefix}/bin/sparc-%{_vendor}-%{_target_os}-gcc
@@ -1583,6 +1589,57 @@
 %doc rpm.doc/changelogs/libmudflap/ChangeLog*
 
 %changelog
+* Mon Aug 27 2007 Jakub Jelinek <jakub at redhat.com> 4.1.2-18.fc7
+- update from gcc-4_1-branch (-r124365:127672)
+  - PRs c++/32112, c++/17763, rtl-optimization/32450, target/31331,
+	target/32641, target/32660, tree-optimization/32681,
+	boehm-gc/21940, boehm-gc/21942, target/28307, target/32506,
+	tree-optimization/31966, tree-optimization/32533,
+	inline-asm/32109, rtl-optimization/28011, target/32389,
+	libfortran/31409, libfortran/31880, libfortran/31964,
+	rtl-optimization/31691, target/31022, target/31480, target/31701,
+	target/31876, target/32163, tree-optimization/26998
+- fix ppc32 libgcc.a(tramp.o), so that binaries using trampolines
+  aren't forced to use bss PLT
+- fix a fortran charlen sharing bug (#253102)
+- fix ICE with X|~X or X^~X with vectors (PR middle-end/32912)
+- nuke bits/stdc++.gch directories from libstdc++-devel (#253304)
+- fix fortran Tx format handling (Jerry DeLisle, #252152,
+  PR libgfortran/32678)
+- add support for Sun UltraSPARC T1 chips - -mcpu=niagara (David S. Miller)
+- don't NRV optimize fields inside anonymous unions (PR c++/32992)
+- fortran debuginfo improvements for constant bound arrays (#248541,
+  PR fortran/22244)
+- update License tag
+- backport ARM fixes from trunk (#246800)
+  - PRs middle-end/24998, target/28516, target/30486
+- fix simplify_plus_minus with ppc{,64} power6 tuning (regression from
+  4.1.1-52.el5.2, #247256)
+- fix OpenMP handling of Fortran POINTER non-array vars (PR fortran/32550)
+- gomp update from gcc-4_2-branch (-r125917:125918)
+  - PR middle-end/32362
+- on ppc{,64} when tuning for power6{,x}, try to put the base
+  register as first operand in instructions to improve
+  performance (Peter Bergner, #225425, PR middle-end/28690)
+- on ppc64 emit nop after a call and disallow sibling calls
+  if the target function is not defined in the same object file
+  (David Edelsohn, #245424)
+- gomp parallel sections fix and fix for checking whether combined
+  parallel can be used (PR libgomp/32468)
+- gomp updates from the trunk (-r125541:125542, -r125543:125544) and
+  from gcc-4_2-branch (-r125184:125185)
+  - PRs tree-optimization/31769, c++/32177
+- don't set TREE_READONLY on C++ objects that need runtime initialization
+  (PRs c++/31806, c++/31809)
+- fix computation of common pointer type (PR tree-optimization/32139)
+- precompute const and pure fn calls inside another fn call arguments
+  with accumulating outgoing args
+  (PRs middle-end/32285, tree-optimization/30493)
+- fix handling of RESULT_DECLs in points-to analysis
+  (#243438, PR tree-optimization/32353)
+- work around java.lang.reflect.Modifier.INTERPRETED clash with
+  java.lang.reflect.Modifier.SYNTHETIC (Andrew Haley, #240720)
+
 * Thu May  3 2007 Jakub Jelinek <jakub at redhat.com> 4.1.2-12
 - update from gcc-4_1-branch (-r124100:124365)
   - PRs c++/30016, c++/30221, middle-end/30761, target/18989,


Index: libgcc_post_upgrade.c
===================================================================
RCS file: /cvs/pkgs/rpms/gcc/F-7/libgcc_post_upgrade.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -r1.4 -r1.5
--- libgcc_post_upgrade.c	12 May 2005 13:26:05 -0000	1.4
+++ libgcc_post_upgrade.c	27 Aug 2007 11:08:53 -0000	1.5
@@ -387,6 +387,35 @@
 	   : inline_syscall_clobbers, "$20", "$21");		\
 	_sc_ret = _sc_0, _sc_err = _sc_19;			\
 }
+#elif defined __arm__ && defined __ARM_EABI__
+# define INTERNAL_SYSCALL_DECL(err) do { } while (0)
+# define INTERNAL_SYSCALL(name, err, nr, args...)		\
+  ({								\
+	register int _r0 __asm__("r0");				\
+	register int _nr __asm__("r7");				\
+	LOAD_ARGS_##nr(args)					\
+	_nr = __NR_##name;					\
+	asm volatile ("swi\t0\t@ syscall " #name "\n\t"		\
+	: "=r" (_r0)						\
+	: "r" (_nr) ASM_ARGS_##nr				\
+	: "memory");						\
+	_r0; })
+# define INTERNAL_SYSCALL_ERROR_P(val, err) \
+  ((unsigned int) (val) >= 0xfffff001u)
+# define ASM_ARGS_0
+# define ASM_ARGS_1	, "r" (_r0)
+# define ASM_ARGS_2	, "r" (_r0), "r" (_r1)
+# define ASM_ARGS_3	, "r" (_r0), "r" (_r1), "r" (_r2)
+# define LOAD_ARGS_0()
+# define LOAD_ARGS_1(r0)					\
+	_r0 = (int)r0;
+# define LOAD_ARGS_2(r0, r1)					\
+	_r0 = (int)r0;						\
+	register int _r1 __asm__("r1") = (int)r1;
+# define LOAD_ARGS_3(r0, r1, r2)				\
+	_r0 = (int)r0;						\
+	register int _r1 __asm__("r1") = (int)r1;		\
+	register int _r2 __asm__("r2") = (int)r2;
 #endif
 
 int main (int argc, char **argv)


Index: sources
===================================================================
RCS file: /cvs/pkgs/rpms/gcc/F-7/sources,v
retrieving revision 1.208
retrieving revision 1.209
diff -u -r1.208 -r1.209
--- sources	3 May 2007 21:56:10 -0000	1.208
+++ sources	27 Aug 2007 11:08:53 -0000	1.209
@@ -1 +1 @@
-f592f2e4d5779b970a7050a864131e69  gcc-4.1.2-20070503.tar.bz2
+65778706d6b9c029a06fca968a45ab7f  gcc-4.1.2-20070821.tar.bz2


--- gcc41-amdfam10.patch DELETED ---


--- gcc41-dtor-relro.patch DELETED ---


--- gcc41-libgomp-ncpus.patch DELETED ---


--- gcc41-multi32-hack.patch DELETED ---


--- gcc41-objc-rh185398.patch DELETED ---


--- gcc41-pr24036-revert.patch DELETED ---


--- gcc41-pr27567.patch DELETED ---


--- gcc41-pr28482.patch DELETED ---


--- gcc41-pr28709.patch DELETED ---


--- gcc41-pr29059.patch DELETED ---


--- gcc41-pr29272.patch DELETED ---


--- gcc41-pr29299.patch DELETED ---


--- gcc41-pr31187.patch DELETED ---


--- gcc41-pr31748.patch DELETED ---


--- gcc41-rh234515.patch DELETED ---


--- gcc41-strncat-chk.patch DELETED ---


--- gcc41-tests.patch DELETED ---


--- gcc41-tls-data-alignment.patch DELETED ---


