rpms/xorg-x11-drv-ati/devel radeon-6.9.0-to-git.patch, 1.4, 1.5 radeon-modeset.patch, 1.15, 1.16 xorg-x11-drv-ati.spec, 1.122, 1.123 copy-fb-contents.patch, 1.5, NONE radeon-6.9.0-lvds-mapping.patch, 1.1, NONE

Dave Airlie airlied at fedoraproject.org
Fri Oct 10 00:06:35 UTC 2008 

Author: airlied

Update of /cvs/pkgs/rpms/xorg-x11-drv-ati/devel
In directory cvs1.fedora.phx.redhat.com:/tmp/cvs-serv3605

Modified Files:
	radeon-6.9.0-to-git.patch radeon-modeset.patch 
	xorg-x11-drv-ati.spec 
Removed Files:
	copy-fb-contents.patch radeon-6.9.0-lvds-mapping.patch 
Log Message:
- rebase to upstream master
- radeon-6.9.0-lvds-mapping.patch - merged upstream
- copy-fb-contents.patch merged into modesetting tree.


radeon-6.9.0-to-git.patch:

View full diff with command:
/usr/bin/cvs -f diff  -kk -u -N -r 1.4 -r 1.5 radeon-6.9.0-to-git.patch
Index: radeon-6.9.0-to-git.patch
===================================================================
RCS file: /cvs/pkgs/rpms/xorg-x11-drv-ati/devel/radeon-6.9.0-to-git.patch,v
retrieving revision 1.4
retrieving revision 1.5
diff -u -r1.4 -r1.5
--- radeon-6.9.0-to-git.patch	26 Sep 2008 00:53:39 -0000	1.4
+++ radeon-6.9.0-to-git.patch	10 Oct 2008 00:06:04 -0000	1.5
@@ -1,3 +1,31 @@
+diff --git a/man/radeon.man b/man/radeon.man
+index 03622a0..68029ed 100644
+--- a/man/radeon.man
++++ b/man/radeon.man
+@@ -283,7 +283,8 @@ The default value is
+ .BI "Option \*qEnablePageFlip\*q \*q" boolean \*q
+ Enable page flipping for 3D acceleration. This will increase performance
+ but not work correctly in some rare cases, hence the default is
+-.B off.
++.B off.  
++It is currently only supported on r4xx and older hardware.
+ .TP
+ .BI "Option \*qForceMinDotClock\*q \*q" frequency \*q
+ Override minimum dot clock. Some Radeon BIOSes report a minimum dot
+@@ -297,10 +298,9 @@ parameter may be specified as a float value with standard suffixes like
+ "k", "kHz", "M", "MHz".
+ .TP
+ .BI "Option \*qRenderAccel\*q \*q" boolean \*q
+-Enables or disables hardware Render acceleration.  This driver does not
+-support component alpha (subpixel) rendering.  It is only supported on
+-Radeon series up to and including 9200 (9500/9700 and newer
+-unsupported).  The default is to
++Enables or disables hardware Render acceleration.  It is supported on
++Radeon series up to and including r5xx for EXA and up to and 
++including r2xx for XAA.  The default is to
+ .B enable
+ Render acceleration.
+ .TP
 diff --git a/src/AtomBios/CD_Operations.c b/src/AtomBios/CD_Operations.c
 index 509aa0c..58c4ae9 100644
 --- a/src/AtomBios/CD_Operations.c
@@ -590,8 +618,83 @@
  
  #define	SOURCE_ONLY_CMD_TYPE		0//0xFE
  #define SOURCE_DESTINATION_CMD_TYPE	1//0xFD
+diff --git a/src/AtomBios/includes/ObjectID.h b/src/AtomBios/includes/ObjectID.h
+index 4b106cf..f1f18a4 100644
+--- a/src/AtomBios/includes/ObjectID.h
++++ b/src/AtomBios/includes/ObjectID.h
+@@ -78,6 +78,10 @@
+ #define ENCODER_OBJECT_ID_DP_DP501                0x1D
+ #define ENCODER_OBJECT_ID_INTERNAL_UNIPHY         0x1E
+ #define ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA   0x1F
++#define ENCODER_OBJECT_ID_INTERNAL_UNIPHY1        0x20
++#define ENCODER_OBJECT_ID_INTERNAL_UNIPHY2        0x21
++
++#define ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO    0xFF
+ 
+ /****************************************************/
+ /* Connector Object ID Definition                   */
+@@ -118,6 +122,8 @@
+ #define GRAPH_OBJECT_ENUM_ID2                     0x02
+ #define GRAPH_OBJECT_ENUM_ID3                     0x03
+ #define GRAPH_OBJECT_ENUM_ID4                     0x04
++#define GRAPH_OBJECT_ENUM_ID5                     0x05
++#define GRAPH_OBJECT_ENUM_ID6                     0x06
+ 
+ /****************************************************/
+ /* Graphics Object ID Bit definition                */
+@@ -173,7 +179,7 @@
+ #define ENCODER_SI178_ENUM_ID1                   0x2117 
+ #define ENCODER_MVPU_FPGA_ENUM_ID1               0x2118
+ #define ENCODER_INTERNAL_DDI_ENUM_ID1            0x2119
+-#define ENCODER_VT1625_ENUM_ID1               0x211A
++#define ENCODER_VT1625_ENUM_ID1                  0x211A
+ #define ENCODER_HDMI_SI1932_ENUM_ID1             0x211B
+ #define ENCODER_ENCODER_DP_AN9801_ENUM_ID1       0x211C
+ #define ENCODER_DP_DP501_ENUM_ID1                0x211D
+@@ -323,6 +329,26 @@
+                                                  GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
+                                                  ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA << OBJECT_ID_SHIFT)  
+ 
++#define ENCODER_INTERNAL_UNIPHY1_ENUM_ID1         ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                 ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 << OBJECT_ID_SHIFT)
++
++#define ENCODER_INTERNAL_UNIPHY1_ENUM_ID2         ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
++                                                 ENCODER_OBJECT_ID_INTERNAL_UNIPHY1 << OBJECT_ID_SHIFT)
++
++#define ENCODER_INTERNAL_UNIPHY2_ENUM_ID1         ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                 ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 << OBJECT_ID_SHIFT)
++
++#define ENCODER_INTERNAL_UNIPHY2_ENUM_ID2         ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
++                                                 ENCODER_OBJECT_ID_INTERNAL_UNIPHY2 << OBJECT_ID_SHIFT)
++
++#define ENCODER_GENERAL_EXTERNAL_DVO_ENUM_ID1    ( GRAPH_OBJECT_TYPE_ENCODER << OBJECT_TYPE_SHIFT |\
++                                                  GRAPH_OBJECT_ENUM_ID1 << ENUM_ID_SHIFT |\
++                                                  ENCODER_OBJECT_ID_GENERAL_EXTERNAL_DVO << OBJECT_ID_SHIFT)
++
+ /****************************************************/
+ /* Connector Object ID definition - Shared with BIOS */
+ /****************************************************/
+@@ -453,6 +479,14 @@
+                                                  GRAPH_OBJECT_ENUM_ID2 << ENUM_ID_SHIFT |\
+                                                  CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
+ 
++#define CONNECTOR_DISPLAYPORT_ENUM_ID3         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID3 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
++
++#define CONNECTOR_DISPLAYPORT_ENUM_ID4         ( GRAPH_OBJECT_TYPE_CONNECTOR << OBJECT_TYPE_SHIFT |\
++                                                 GRAPH_OBJECT_ENUM_ID4 << ENUM_ID_SHIFT |\
++                                                 CONNECTOR_OBJECT_ID_DISPLAYPORT << OBJECT_ID_SHIFT)
++
+ /****************************************************/
+ /* Router Object ID definition - Shared with BIOS   */
+ /****************************************************/
 diff --git a/src/AtomBios/includes/atombios.h b/src/AtomBios/includes/atombios.h
-index 17483a6..2e7dc6c 100644
+index 17483a6..9932b09 100644
 --- a/src/AtomBios/includes/atombios.h
 +++ b/src/AtomBios/includes/atombios.h
 @@ -34,6 +34,12 @@
@@ -607,8 +710,49 @@
  
  #ifdef _H2INC
    #ifndef ULONG 
-@@ -304,7 +310,7 @@ typedef struct _ATOM_MASTER_COMMAND_TABLE
+@@ -260,7 +266,7 @@ typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{
+   USHORT SetCRTC_UsingDTDTiming;                 //Atomic Table,  directly used by various SW components,latest version 1.1
+   USHORT ExternalEncoderControl;                 //Atomic Table,  directly used by various SW components,latest version 2.1
+   USHORT LVTMAOutputControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1
+-  USHORT VRAM_BlockDetectionByStrap;
++  USHORT VRAM_BlockDetectionByStrap;             //Atomic Table,  used only by Bios
+   USHORT MemoryCleanUp;                          //Atomic Table,  only used by Bios    
+   USHORT ProcessI2cChannelTransaction;           //Function Table,only used by Bios
+   USHORT WriteOneByteToHWAssistedI2C;            //Function Table,indirectly used by various SW components 
+@@ -270,9 +276,9 @@ typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{
+   USHORT MC_Synchronization;                     //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
+   USHORT ComputeMemoryEnginePLL;                 //Atomic Table,  indirectly used by various SW components,called from SetMemory/EngineClock
+   USHORT MemoryRefreshConversion;                //Atomic Table,  indirectly used by various SW components,called from SetMemory or SetEngineClock
+-  USHORT VRAM_GetCurrentInfoBlock;
++  USHORT VRAM_GetCurrentInfoBlock;               //Atomic Table,  used only by Bios
+   USHORT DynamicMemorySettings;                  //Atomic Table,  indirectly used by various SW components,called from SetMemoryClock
+-  USHORT MemoryTraining;
++  USHORT MemoryTraining;                         //Atomic Table,  used only by Bios
+   USHORT EnableSpreadSpectrumOnPPLL;             //Atomic Table,  directly used by various SW components,latest version 1.2
+   USHORT TMDSAOutputControl;                     //Atomic Table,  directly used by various SW components,latest version 1.1
+   USHORT SetVoltage;                             //Function Table,directly and/or indirectly used by various SW components,latest version 1.1
+@@ -290,11 +296,12 @@ typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{
+   USHORT DPEncoderService;											 //Function Table,only used by Bios
+ }ATOM_MASTER_LIST_OF_COMMAND_TABLES;   
  
++// For backward compatible 
+ #define ReadEDIDFromHWAssistedI2C                ProcessI2cChannelTransaction
+-
+ #define UNIPHYTransmitterControl						     DIG1TransmitterControl
+ #define LVTMATransmitterControl							     DIG2TransmitterControl
+-#define SetCRTC_DPM_State                                    GetConditionalGoldenSetting
++#define SetCRTC_DPM_State                        GetConditionalGoldenSetting
++#define SetUniphyInstance                        ASIC_StaticPwrMgtStatusChange
+ 
+ typedef struct _ATOM_MASTER_COMMAND_TABLE
+ {
+@@ -302,9 +309,12 @@ typedef struct _ATOM_MASTER_COMMAND_TABLE
+   ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables;
+ }ATOM_MASTER_COMMAND_TABLE;
+ 
++/****************************************************************************/	
++// Structures used in every command table
++/****************************************************************************/	
  typedef struct _ATOM_TABLE_ATTRIBUTE
  {
 -#if X_BYTE_ORDER == X_BIG_ENDIAN
@@ -616,20 +760,718 @@
    USHORT  UpdatedByUtility:1;         //[15]=Table updated by utility flag
    USHORT  PS_SizeInBytes:7;           //[14:8]=Size of parameter space in Bytes (multiple of a dword), 
    USHORT  WS_SizeInBytes:8;           //[7:0]=Size of workspace in Bytes (in multiple of a dword), 
-@@ -315,6 +321,12 @@ typedef struct _ATOM_TABLE_ATTRIBUTE
+@@ -315,23 +325,26 @@ typedef struct _ATOM_TABLE_ATTRIBUTE
  #endif
  }ATOM_TABLE_ATTRIBUTE;
  
+-// Common header for all command tables.
+-//Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. 
+-//And the pointer actually points to this header.
 +typedef union _ATOM_TABLE_ATTRIBUTE_ACCESS
 +{
 +  ATOM_TABLE_ATTRIBUTE sbfAccess;
 +  USHORT               susAccess;
 +}ATOM_TABLE_ATTRIBUTE_ACCESS;
+ 
++/****************************************************************************/	
++// Common header for all command tables.
++// Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header. 
++// And the pointer actually points to this header.
++/****************************************************************************/	
+ typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER
[...13684 lines suppressed...]
 +     * The base address must be aligned to a multiple of 4 MB.
 +     */
-+    base_offset = ((info->fbLocation +
-+		    min(offset1, min(offset2, min(offset3, min(offset4,
-+			min(offset5, offset6)))))) & (~0 << 22)) -
++    base_offset = ((info->fbLocation + base_offset) & (~0 << 22)) -
 +	info->fbLocation;
 +
 +    offset1 -= base_offset;
@@ -6719,30 +16980,140 @@
      /* keep everything in 16.16 */
  
      if (is_planar) {
-@@ -2846,6 +2856,10 @@ RADEONDisplayVideo(
+@@ -2846,6 +2739,12 @@ RADEONDisplayVideo(
  	src_w >>= 1;
      OUTREG(RADEON_OV0_P2_X_START_END, (src_w + leftuv - 1) | (leftuv << 16));
      OUTREG(RADEON_OV0_P3_X_START_END, (src_w + leftuv - 1) | (leftuv << 16));
 +    if (info->ModeReg->ov0_base_addr != (info->fbLocation + base_offset)) {
++	ErrorF("Changing OV0_BASE_ADDR from 0x%08x to 0x%08x\n",
++	       info->ModeReg->ov0_base_addr, info->fbLocation + base_offset);
 +	info->ModeReg->ov0_base_addr = info->fbLocation + base_offset;
 +	OUTREG(RADEON_OV0_BASE_ADDR, info->ModeReg->ov0_base_addr);
 +    }
      OUTREG(RADEON_OV0_VID_BUF0_BASE_ADRS, offset1);
      OUTREG(RADEON_OV0_VID_BUF1_BASE_ADRS, offset2);
      OUTREG(RADEON_OV0_VID_BUF2_BASE_ADRS, offset3);
-@@ -3236,6 +3250,10 @@ RADEONVideoTimerCallback(ScrnInfoPtr pScrn, Time now)
- 		    RADEONFreeMemory(pScrn, pPriv->video_memory);
+@@ -3038,9 +2937,9 @@ RADEONPutImage(
+    if (idconv == FOURCC_YV12 || id == FOURCC_I420) {
+       new_size += (dstPitch >> 1) * ((height + 1) & ~1);
+    }
+-   pPriv->video_offset = RADEONAllocateMemory(pScrn, &pPriv->video_memory,
+-					      (pPriv->doubleBuffer ?
+-					       (new_size * 2) : new_size));
++   pPriv->video_offset = radeon_legacy_allocate_memory(pScrn, &pPriv->video_memory,
++						       (pPriv->doubleBuffer ?
++						       (new_size * 2) : new_size), 64);
+    if (pPriv->video_offset == 0)
+       return BadAlloc;
+ 
+@@ -3150,9 +3049,10 @@ RADEONPutImage(
+ 
+     /* FIXME: someone should look at these offsets, I don't think it makes sense how
+               they are handled throughout the source. */
+-    RADEONDisplayVideo(pScrn, crtc, pPriv, idconv, offset, offset + d2line, offset + d3line,
+-		     offset, offset + d2line, offset + d3line, width, height, dstPitch,
+-		     xa, xb, ya, &dstBox, src_w, src_h, drw_w, drw_h, METHOD_BOB);
++    RADEONDisplayVideo(pScrn, crtc, pPriv, idconv, pPriv->video_offset, offset,
++		       offset + d2line, offset + d3line, offset, offset + d2line,
++		       offset + d3line, width, height, dstPitch, xa, xb, ya,
++		       &dstBox, src_w, src_h, drw_w, drw_h, METHOD_BOB);
+ 
+     pPriv->videoStatus = CLIENT_VIDEO_ON;
+ 
+@@ -3233,7 +3133,7 @@ RADEONVideoTimerCallback(ScrnInfoPtr pScrn, Time now)
+ 	} else {  /* FREE_TIMER */
+ 	    if(pPriv->freeTime < now) {
+ 		if (pPriv->video_memory != NULL) {
+-		    RADEONFreeMemory(pScrn, pPriv->video_memory);
++		    radeon_legacy_free_memory(pScrn, pPriv->video_memory);
  		    pPriv->video_memory = NULL;
  		}
-+		if (pPriv->bicubic_memory != NULL) {
-+		    RADEONFreeMemory(pScrn, pPriv->bicubic_memory);
-+		    pPriv->bicubic_memory = NULL;
-+		}
  		pPriv->videoStatus = 0;
- 		info->VideoTimerCallback = NULL;
- 	    }
+@@ -3268,7 +3168,7 @@ RADEONAllocateSurface(
+     pitch = ((w << 1) + 15) & ~15;
+     size = pitch * h;
+ 
+-    offset = RADEONAllocateMemory(pScrn, &surface_memory, size);
++    offset = radeon_legacy_allocate_memory(pScrn, &surface_memory, size, 64);
+     if (offset == 0)
+ 	return BadAlloc;
+ 
+@@ -3276,18 +3176,18 @@ RADEONAllocateSurface(
+     surface->height = h;
+ 
+     if(!(surface->pitches = xalloc(sizeof(int)))) {
+-	RADEONFreeMemory(pScrn, surface_memory);
++	radeon_legacy_free_memory(pScrn, surface_memory);
+ 	return BadAlloc;
+     }
+     if(!(surface->offsets = xalloc(sizeof(int)))) {
+ 	xfree(surface->pitches);
+-	RADEONFreeMemory(pScrn, surface_memory);
++	radeon_legacy_free_memory(pScrn, surface_memory);
+ 	return BadAlloc;
+     }
+     if(!(pPriv = xalloc(sizeof(OffscreenPrivRec)))) {
+ 	xfree(surface->pitches);
+ 	xfree(surface->offsets);
+-	RADEONFreeMemory(pScrn, surface_memory);
++	radeon_legacy_free_memory(pScrn, surface_memory);
+ 	return BadAlloc;
+     }
+ 
+@@ -3328,7 +3228,8 @@ RADEONFreeSurface(
+ 
+     if(pPriv->isOn)
+ 	RADEONStopSurface(surface);
+-    RADEONFreeMemory(pScrn, pPriv->surface_memory);
++    radeon_legacy_free_memory(pScrn, pPriv->surface_memory);
++    pPriv->surface_memory = NULL;
+     xfree(surface->pitches);
+     xfree(surface->offsets);
+     xfree(surface->devPrivate.ptr);
+@@ -3417,8 +3318,9 @@ RADEONDisplaySurface(
+ 		       surface->offsets[0], surface->offsets[0],
+ 		       surface->offsets[0], surface->offsets[0],
+ 		       surface->offsets[0], surface->offsets[0],
+-		       surface->width, surface->height, surface->pitches[0],
+-		       xa, xb, ya, &dstBox, src_w, src_h, drw_w, drw_h, METHOD_BOB);
++		       surface->offsets[0], surface->width, surface->height,
++		       surface->pitches[0], xa, xb, ya, &dstBox, src_w, src_h,
++		       drw_w, drw_h, METHOD_BOB);
+ 
+     if (portPriv->autopaint_colorkey)
+ 	xf86XVFillKeyHelper(pScrn->pScreen, portPriv->colorKey, clipBoxes);
+@@ -3602,9 +3504,9 @@ RADEONPutVideo(
+    if (pPriv->capture_vbi_data)
+       alloc_size += 2 * 2 * vbi_line_width * 21;
+ 
+-   pPriv->video_offset = RADEONAllocateMemory(pScrn, &pPriv->video_memory,
+-					      (pPriv->doubleBuffer ?
+-					       (new_size * 2) : new_size));
++   pPriv->video_offset = radeon_legacy_allocate_memory(pScrn, &pPriv->video_memory,
++						      (pPriv->doubleBuffer ?
++						      (new_size * 2) : new_size), 64);
+    if (pPriv->video_offset == 0)
+       return BadAlloc;
+ 
+@@ -3705,10 +3607,12 @@ RADEONPutVideo(
+ 	    RADEONFillKeyHelper(pDraw, pPriv->colorKey, clipBoxes);
+    }
+ 
+-   RADEONDisplayVideo(pScrn, crtc, pPriv, id, offset1+top*srcPitch, offset2+top*srcPitch,
+-		offset3+top*srcPitch, offset4+top*srcPitch, offset1+top*srcPitch,
+-		offset2+top*srcPitch, width, height, dstPitch*mult/2,
+-                     xa, xb, ya, &dstBox, src_w, src_h*mult/2, drw_w, drw_h, pPriv->overlay_deinterlacing_method);
++   RADEONDisplayVideo(pScrn, crtc, pPriv, id, pPriv->video_offset,
++		      offset1+top*srcPitch, offset2+top*srcPitch,
++		      offset3+top*srcPitch, offset4+top*srcPitch,
++		      offset1+top*srcPitch, offset2+top*srcPitch, width, height,
++		      dstPitch*mult/2, xa, xb, ya, &dstBox, src_w, src_h*mult/2,
++		      drw_w, drw_h, pPriv->overlay_deinterlacing_method);
+ 
+    RADEONWaitForFifo(pScrn, 1);
+    OUTREG(RADEON_OV0_REG_LOAD_CNTL,  RADEON_REG_LD_CTL_LOCK);
 diff --git a/src/radeon_video.h b/src/radeon_video.h
-index 096de37..b9d900d 100644
+index 096de37..11b8029 100644
 --- a/src/radeon_video.h
 +++ b/src/radeon_video.h
 @@ -13,6 +13,10 @@
@@ -6783,7 +17154,14 @@
  #define METHOD_BOB      0
  #define METHOD_SINGLE   1
  #define METHOD_WEAVE    2
-@@ -89,6 +93,12 @@ typedef struct {
+@@ -82,13 +86,16 @@ typedef struct {
+    xf86CrtcPtr   desired_crtc;
+ 
+    int           size;
+-#ifdef USE_EXA
+-   ExaOffscreenArea *off_screen;
+-#endif
+ 
     void         *video_memory;
     int           video_offset;
  
@@ -6796,7 +17174,7 @@
     Atom          device_id, location_id, instance_id;
  
      /* textured video */
-@@ -106,7 +116,6 @@ typedef struct {
+@@ -106,18 +113,12 @@ typedef struct {
      int drw_x, drw_y;
  } RADEONPortPrivRec, *RADEONPortPrivPtr;
  
@@ -6804,3 +17182,14 @@
  void RADEONInitI2C(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv);
  void RADEONResetI2C(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv);
  
+ void RADEONVIP_init(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv);
+ void RADEONVIP_reset(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv);
+ 
+-uint32_t
+-RADEONAllocateMemory(ScrnInfoPtr pScrn, void **mem_struct, int size);
+-void
+-RADEONFreeMemory(ScrnInfoPtr pScrn, void *mem_struct);
+-
+ int  RADEONSetPortAttribute(ScrnInfoPtr, Atom, INT32, pointer);
+ int  RADEONGetPortAttribute(ScrnInfoPtr, Atom ,INT32 *, pointer);
+ void RADEONStopVideo(ScrnInfoPtr, pointer, Bool);

radeon-modeset.patch:

View full diff with command:
/usr/bin/cvs -f diff  -kk -u -N -r 1.15 -r 1.16 radeon-modeset.patch
Index: radeon-modeset.patch
===================================================================
RCS file: /cvs/pkgs/rpms/xorg-x11-drv-ati/devel/radeon-modeset.patch,v
retrieving revision 1.15
retrieving revision 1.16
diff -u -r1.15 -r1.16
--- radeon-modeset.patch	1 Oct 2008 06:15:58 -0000	1.15
+++ radeon-modeset.patch	10 Oct 2008 00:06:04 -0000	1.16
@@ -1,8 +1,8 @@
 diff --git a/configure.ac b/configure.ac
-index b8c18a6..a7e954d 100644
+index b8c18a6..8b126b5 100644
 --- a/configure.ac
 +++ b/configure.ac
-@@ -115,6 +115,14 @@ if test "$DRI" = yes; then
+@@ -115,6 +115,15 @@ if test "$DRI" = yes; then
  	if test "$have_damage_h" = yes; then
  		AC_DEFINE(DAMAGE,1,[Use Damage extension])
  	fi
@@ -14,16 +14,17 @@
 +        if test "x$DRM_MODE" = xyes; then
 +                AC_DEFINE(XF86DRM_MODE,1,[DRM kernel modesetting])
 +        fi
++	CFLAGS="$save_CFLAGS"
  fi
  
  save_CFLAGS="$CFLAGS"
 diff --git a/src/Makefile.am b/src/Makefile.am
-index 97c686b..b8d09bb 100644
+index d65a3e4..ff54329 100644
 --- a/src/Makefile.am
 +++ b/src/Makefile.am
 @@ -90,12 +90,13 @@ radeon_drv_ladir = @moduledir@/drivers
  radeon_drv_la_SOURCES = \
- 	radeon_accel.c radeon_cursor.c radeon_dga.c \
+ 	radeon_accel.c radeon_cursor.c radeon_dga.c radeon_legacy_memory.c \
  	radeon_driver.c radeon_video.c radeon_bios.c radeon_mm_i2c.c \
 -	radeon_vip.c radeon_misc.c radeon_probe.c \
 +	radeon_vip.c radeon_misc.c radeon_probe.c radeon_memory.c \
@@ -37,7 +38,7 @@
  
  if XMODES
  radeon_drv_la_SOURCES += \
-@@ -160,4 +161,6 @@ EXTRA_DIST = \
+@@ -159,4 +160,6 @@ EXTRA_DIST = \
  	radeon_pci_device_match_gen.h \
  	pcidb/ati_pciids.csv \
  	pcidb/parse_pci_ids.pl \
@@ -47,10 +48,10 @@
 +	radeon_dri_bufmgr.h
 diff --git a/src/drmmode_display.c b/src/drmmode_display.c
 new file mode 100644
-index 0000000..3073c15
+index 0000000..644978e
 --- /dev/null
 +++ b/src/drmmode_display.c
-@@ -0,0 +1,685 @@
+@@ -0,0 +1,752 @@
 +/*
 + * Copyright © 2007 Red Hat, Inc.
 + *
@@ -84,6 +85,7 @@
 +
 +#ifdef XF86DRM_MODE
 +#include "radeon.h"
++#include "radeon_reg.h"
 +#include "sarea.h"
 +
 +static Bool drmmode_resize_fb(ScrnInfoPtr scrn, drmmode_ptr drmmode, int width, int height);
@@ -172,6 +174,71 @@
 +
 +}
 +
++static PixmapPtr
++create_pixmap_for_fb(drmmode_ptr drmmode, ScrnInfoPtr pScrn, drmModeFBPtr fb)
++{
++	ScreenPtr pScreen = pScrn->pScreen;
++	PixmapPtr pPixmap;
++	struct radeon_exa_pixmap_priv *driver_priv;
++	dri_bo *bo;
++
++	pPixmap = (*pScreen->CreatePixmap)(pScreen, 0, 0, fb->depth, 0);
++	driver_priv = exaGetPixmapDriverPrivate(pPixmap);
++	if (!driver_priv) {
++		(*pScreen->DestroyPixmap)(pPixmap);
++		return NULL;
++	}
++
++	miModifyPixmapHeader(pPixmap, fb->width, fb->height, fb->depth,
++                             pScrn->bitsPerPixel, fb->pitch, NULL);
++
++	bo = radeon_bo_gem_create_from_handle(drmmode->bufmgr,
++					      fb->handle,
++					      fb->pitch * fb->height);
++	driver_priv->bo = bo;
++	if (bo == NULL) {
++		(*pScreen->DestroyPixmap)(pPixmap);
++		return NULL;
++	}
++
++    	return pPixmap;
++}
++
++static void
++copy_fb_contents (drmmode_ptr drmmode,
++		  ScrnInfoPtr pScrn,
++		  unsigned int dest_id, int x, int y, unsigned int src_id)
++{
++	RADEONInfoPtr info = RADEONPTR(pScrn);
++	drmModeFBPtr dest_fb, src_fb;
++	dri_bo *dest_bo, *src_bo;
++	PixmapPtr src_pixmap, dest_pixmap;
++	ScreenPtr pScreen = pScrn->pScreen;
++
++	dest_fb = drmModeGetFB(drmmode->fd, dest_id);
++	src_fb = drmModeGetFB(drmmode->fd, src_id);
++	if (src_fb == NULL) {
++		ErrorF("failed to get old fb, id %d\n", src_id);
++		return;
++	}
++
++	dest_pixmap = create_pixmap_for_fb(drmmode, pScrn, dest_fb);
++	src_pixmap = create_pixmap_for_fb(drmmode, pScrn, src_fb);
++
++	info->accel_state->exa->PrepareCopy (src_pixmap, dest_pixmap,
++					     0, 0, GXcopy, 0xffffff);
++	info->accel_state->exa->Copy (dest_pixmap, 0, 0, x, y,
++			 	      src_fb->width, src_fb->height);
++	info->accel_state->exa->DoneCopy (dest_pixmap);
++	RADEONCPFlushIndirect(pScrn, 0);
++
++	(*pScreen->DestroyPixmap)(dest_pixmap);
++	(*pScreen->DestroyPixmap)(src_pixmap);
++
++	drmFree(dest_fb);
++	drmFree(src_fb);
++}
++
 +static Bool
 +drmmode_set_mode_major(xf86CrtcPtr crtc, DisplayModePtr mode,
 +		     Rotation rotation, int x, int y)
@@ -227,7 +294,8 @@
 +	fb_id = drmmode->fb_id;
 +	if (drmmode_crtc->rotate_fb_id)
 +		fb_id = drmmode_crtc->rotate_fb_id;
-+	ErrorF("fb id is %d\n", fb_id);
++ 	copy_fb_contents (drmmode, crtc->scrn, fb_id, x, y,
++ 			  drmmode_crtc->mode_crtc->buffer_id);
 +	drmModeSetCrtc(drmmode->fd, drmmode_crtc->mode_crtc->crtc_id,
 +		       fb_id, x, y, output_ids, output_count, &kmode);
 +
@@ -817,7 +885,7 @@
 +#endif
 +#endif
 diff --git a/src/radeon.h b/src/radeon.h
-index 2348e7c..aeea221 100644
+index f7ae1a8..b179421 100644
 --- a/src/radeon.h
 +++ b/src/radeon.h
 @@ -46,6 +46,8 @@
@@ -829,7 +897,7 @@
  				/* PCI support */
  #include "xf86Pci.h"
  
-@@ -84,6 +86,7 @@
+@@ -85,6 +87,7 @@
  #include "xf86Crtc.h"
  #include "X11/Xatom.h"
  
@@ -837,7 +905,7 @@
  				/* Render support */
  #ifdef RENDER
  #include "picturestr.h"
-@@ -403,6 +406,14 @@ typedef enum {
+@@ -404,6 +407,14 @@ typedef enum {
  
  typedef struct _atomBiosHandle *atomBiosHandlePtr;
  
@@ -852,7 +920,7 @@
  typedef struct {
      uint32_t pci_device_id;
      RADEONChipFamily chip_family;
-@@ -413,6 +424,25 @@ typedef struct {
+@@ -414,6 +425,25 @@ typedef struct {
      int singledac;
  } RADEONCardInfo;
  
@@ -875,10 +943,20 @@
 +    dri_bo *src_bo;
 +};
 +    
- typedef struct {
-     EntityInfoPtr     pEnt;
-     pciVideoPtr       PciInfo;
-@@ -612,13 +642,13 @@ typedef struct {
+ #ifdef XF86DRI
+ struct radeon_cp {
+     Bool              CPRuns;           /* CP is running */
+@@ -428,6 +458,9 @@ struct radeon_cp {
+     drmBufPtr         indirectBuffer;
[...3733 lines suppressed...]
+ 	OUT_ACCEL_REG(R300_TX_FORMAT2_0, txpitch);
+-	OUT_ACCEL_REG(R300_TX_OFFSET_0, txoffset);
 +	if (info->new_cs) {
-+	    OUT_VIDEO_REG(R300_TX_OFFSET_0, 0);
++	    OUT_ACCEL_REG(R300_TX_OFFSET_0, 0);
 +	    OUT_RELOC(pPriv->src_bo, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
 +	} else {
 +	    txoffset += info->fbLocation + pScrn->fbOffset;
-+	    OUT_VIDEO_REG(R300_TX_OFFSET_0, txoffset);
++	    OUT_ACCEL_REG(R300_TX_OFFSET_0, txoffset);
 +	}
- 	FINISH_VIDEO();
+ 	FINISH_ACCEL();
  
  	txenable = R300_TEX_0_ENABLE;
-@@ -237,13 +253,20 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
+@@ -237,13 +252,19 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
  			    R300_TX_MAG_FILTER_NEAREST |
  			    (1 << R300_TX_ID_SHIFT));
  
--		BEGIN_VIDEO(6);
+-		BEGIN_ACCEL(6);
 +		qwords = info->new_cs ? 8 : 6;
-+		BEGIN_VIDEO(qwords);
- 		OUT_VIDEO_REG(R300_TX_FILTER0_1, txfilter);
- 		OUT_VIDEO_REG(R300_TX_FILTER1_1, 0);
- 		OUT_VIDEO_REG(R300_TX_FORMAT0_1, txformat0);
- 		OUT_VIDEO_REG(R300_TX_FORMAT1_1, txformat1);
- 		OUT_VIDEO_REG(R300_TX_FORMAT2_1, txpitch);
--		OUT_VIDEO_REG(R300_TX_OFFSET_1, pPriv->bicubic_src_offset);
-+
++		BEGIN_ACCEL(qwords);
+ 		OUT_ACCEL_REG(R300_TX_FILTER0_1, txfilter);
+ 		OUT_ACCEL_REG(R300_TX_FILTER1_1, 0);
+ 		OUT_ACCEL_REG(R300_TX_FORMAT0_1, txformat0);
+ 		OUT_ACCEL_REG(R300_TX_FORMAT1_1, txformat1);
+ 		OUT_ACCEL_REG(R300_TX_FORMAT2_1, txpitch);
+-		OUT_ACCEL_REG(R300_TX_OFFSET_1, pPriv->bicubic_src_offset);
 +		if (info->new_cs) {
-+		    OUT_VIDEO_REG(R300_TX_OFFSET_1, 0);
++		    OUT_ACCEL_REG(R300_TX_OFFSET_1, 0);
 +		    OUT_RELOC(pPriv->bicubic_bo, RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT, 0);
 +		} else {
-+		    OUT_VIDEO_REG(R300_TX_OFFSET_1, pPriv->bicubic_src_offset);
++		    OUT_ACCEL_REG(R300_TX_OFFSET_1, pPriv->bicubic_src_offset);
 +		}
- 		FINISH_VIDEO();
+ 		FINISH_ACCEL();
  
  		/* Enable tex 1 */
-@@ -980,11 +1003,18 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
+@@ -980,11 +1001,18 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
  	    }
  	}
  
--	BEGIN_VIDEO(6);
+-	BEGIN_ACCEL(6);
 +	qwords = info->new_cs ? 8 : 6;
-+	BEGIN_VIDEO(qwords);
- 	OUT_VIDEO_REG(R300_TX_INVALTAGS, 0);
- 	OUT_VIDEO_REG(R300_TX_ENABLE, txenable);
++	BEGIN_ACCEL(qwords);
+ 	OUT_ACCEL_REG(R300_TX_INVALTAGS, 0);
+ 	OUT_ACCEL_REG(R300_TX_ENABLE, txenable);
  
--	OUT_VIDEO_REG(R300_RB3D_COLOROFFSET0, dst_offset);
+-	OUT_ACCEL_REG(R300_RB3D_COLOROFFSET0, dst_offset);
 +	if (info->new_cs) {
-+	    OUT_VIDEO_REG(R300_RB3D_COLOROFFSET0, 0);
++	    OUT_ACCEL_REG(R300_RB3D_COLOROFFSET0, 0);
 +	    OUT_RELOC(dst_bo, 0, RADEON_GEM_DOMAIN_VRAM);
 +	} else {
 +	    dst_offset += info->fbLocation + pScrn->fbOffset;
-+	    OUT_VIDEO_REG(R300_RB3D_COLOROFFSET0, dst_offset);
++	    OUT_ACCEL_REG(R300_RB3D_COLOROFFSET0, dst_offset);
 +	}
- 	OUT_VIDEO_REG(R300_RB3D_COLORPITCH0, colorpitch);
+ 	OUT_ACCEL_REG(R300_RB3D_COLORPITCH0, colorpitch);
  
  	blendcntl = RADEON_SRC_BLEND_GL_ONE | RADEON_DST_BLEND_GL_ZERO;
-@@ -1029,6 +1059,7 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
+@@ -1029,6 +1057,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
  		      RADEON_TEX_0_ENABLE | RADEON_TEX_BLEND_0_ENABLE);
- 	OUT_VIDEO_REG(RADEON_RB3D_CNTL,
+ 	OUT_ACCEL_REG(RADEON_RB3D_CNTL,
  		      dst_format | RADEON_ALPHA_BLEND_ENABLE);
++
 +	dst_offset += info->fbLocation + pScrn->fbOffset;
- 	OUT_VIDEO_REG(RADEON_RB3D_COLOROFFSET, dst_offset);
+ 	OUT_ACCEL_REG(RADEON_RB3D_COLOROFFSET, dst_offset);
  
- 	OUT_VIDEO_REG(RADEON_RB3D_COLORPITCH, colorpitch);
-@@ -1066,7 +1097,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
+ 	OUT_ACCEL_REG(RADEON_RB3D_COLORPITCH, colorpitch);
+@@ -1066,7 +1096,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
  			  ((pPriv->h - 1) << RADEON_TEX_VSIZE_SHIFT));
- 	    OUT_VIDEO_REG(R200_PP_TXPITCH_0, pPriv->src_pitch - 32);
+ 	    OUT_ACCEL_REG(R200_PP_TXPITCH_0, pPriv->src_pitch - 32);
  
--	    OUT_VIDEO_REG(R200_PP_TXOFFSET_0, pPriv->src_offset);
-+	    OUT_VIDEO_REG(R200_PP_TXOFFSET_0, pPriv->src_offset +
+-	    OUT_ACCEL_REG(R200_PP_TXOFFSET_0, pPriv->src_offset);
++	    OUT_ACCEL_REG(R200_PP_TXOFFSET_0, pPriv->src_offset +
 +			  info->fbLocation + pScrn->fbOffset);
  
- 	    OUT_VIDEO_REG(R200_PP_TXCBLEND_0,
+ 	    OUT_ACCEL_REG(R200_PP_TXCBLEND_0,
  			  R200_TXC_ARG_A_ZERO |
-@@ -1100,7 +1132,8 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
+@@ -1099,8 +1130,10 @@ FUNC_NAME(RADEONDisplayTexturedVideo)(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv
+ 			  RADEON_CLAMP_S_CLAMP_LAST |
  			  RADEON_CLAMP_T_CLAMP_LAST |
  			  RADEON_YUV_TO_RGB);
- 	    OUT_VIDEO_REG(RADEON_PP_TXFORMAT_0, txformat);
--	    OUT_VIDEO_REG(RADEON_PP_TXOFFSET_0, pPriv->src_offset);
-+	    OUT_VIDEO_REG(RADEON_PP_TXOFFSET_0, pPriv->src_offset +
++
+ 	    OUT_ACCEL_REG(RADEON_PP_TXFORMAT_0, txformat);
+-	    OUT_ACCEL_REG(RADEON_PP_TXOFFSET_0, pPriv->src_offset);
++	    OUT_ACCEL_REG(RADEON_PP_TXOFFSET_0, pPriv->src_offset +
 +			  info->fbLocation + pScrn->fbOffset);
- 	    OUT_VIDEO_REG(RADEON_PP_TXCBLEND_0,
+ 	    OUT_ACCEL_REG(RADEON_PP_TXCBLEND_0,
  			  RADEON_COLOR_ARG_A_ZERO |
  			  RADEON_COLOR_ARG_B_ZERO |
 diff --git a/src/radeon_video.c b/src/radeon_video.c
-index e71f0f8..aba8884 100644
+index 6249cea..5874335 100644
 --- a/src/radeon_video.c
 +++ b/src/radeon_video.c
-@@ -270,7 +270,7 @@ void RADEONInitVideo(ScreenPtr pScreen)
+@@ -257,7 +257,7 @@ void RADEONInitVideo(ScreenPtr pScreen)
      memcpy(newAdaptors, adaptors, num_adaptors * sizeof(XF86VideoAdaptorPtr));
      adaptors = newAdaptors;
  
@@ -6616,7 +6913,7 @@
  	overlayAdaptor = RADEONSetupImageVideo(pScreen);
  	if (overlayAdaptor != NULL) {
  	    adaptors[num_adaptors++] = overlayAdaptor;
-@@ -283,7 +283,7 @@ void RADEONInitVideo(ScreenPtr pScreen)
+@@ -270,7 +270,7 @@ void RADEONInitVideo(ScreenPtr pScreen)
      if (info->ChipFamily != CHIP_FAMILY_RV250) {
  	if ((info->ChipFamily < CHIP_FAMILY_RS400)
  #ifdef XF86DRI
@@ -6625,7 +6922,7 @@
  #endif
  	    ) {
  	    texturedAdaptor = RADEONSetupImageTexturedVideo(pScreen);
-@@ -2180,7 +2180,7 @@ RADEONCopyData(
+@@ -2173,7 +2173,7 @@ RADEONCopyData(
  
  #ifdef XF86DRI
  
@@ -6634,44 +6931,11 @@
      {
  	uint8_t *buf;
  	uint32_t bufPitch, dstPitchOff;
-@@ -2443,6 +2443,20 @@ RADEONAllocateMemory(
-     int offset = 0;
- 
-     pScreen = screenInfo.screens[pScrn->scrnIndex];
-+
-+    if (info->new_cs) {
-+	dri_bo *video_bo;
-+
-+	video_bo = dri_bo_alloc(info->bufmgr, "xv pixmap", size, 4096, 0);
-+
-+	*mem_struct = video_bo;
-+
-+	if (!video_bo)
-+	    return 0;
-+	
-+	return (uint32_t)-1;
-+
-+    }
- #ifdef USE_EXA
-     if (info->useEXA) {
- 	ExaOffscreenArea *area = *mem_struct;
-@@ -2516,6 +2530,11 @@ RADEONFreeMemory(
- ){
-     RADEONInfoPtr info = RADEONPTR(pScrn);
- 
-+    if (info->new_cs) {
-+	struct dri_bo *bo = mem_struct;
-+	dri_bo_unreference(bo);
-+	return;
-+    }
- #ifdef USE_EXA
-     if (info->useEXA) {
- 	ExaOffscreenArea *area = mem_struct;
 diff --git a/src/radeon_video.h b/src/radeon_video.h
-index b9d900d..0687969 100644
+index 11b8029..a1bd20c 100644
 --- a/src/radeon_video.h
 +++ b/src/radeon_video.h
-@@ -114,6 +114,9 @@ typedef struct {
+@@ -111,6 +111,9 @@ typedef struct {
      int src_w, src_h, dst_w, dst_h;
      int w, h;
      int drw_x, drw_y;


Index: xorg-x11-drv-ati.spec
===================================================================
RCS file: /cvs/pkgs/rpms/xorg-x11-drv-ati/devel/xorg-x11-drv-ati.spec,v
retrieving revision 1.122
retrieving revision 1.123
diff -u -r1.122 -r1.123
--- xorg-x11-drv-ati.spec	8 Oct 2008 20:43:29 -0000	1.122
+++ xorg-x11-drv-ati.spec	10 Oct 2008 00:06:05 -0000	1.123
@@ -5,7 +5,7 @@
 Summary:   Xorg X11 ati video driver
 Name:      xorg-x11-drv-ati
 Version:   6.9.0
-Release:   22%{?dist}
+Release:   23%{?dist}
 URL:       http://www.x.org
 License:   MIT
 Group:     User Interface/X Hardware Support
@@ -18,8 +18,6 @@
 Patch1:     radeon-modeset.patch
 Patch4:     radeon-6.9.0-remove-limit-heuristics.patch
 Patch5:	    radeon-6.9.0-panel-size-sanity.patch
-Patch6:     copy-fb-contents.patch
-Patch7:	    radeon-6.9.0-lvds-mapping.patch
 
 ExcludeArch: s390 s390x
 
@@ -43,8 +41,6 @@
 %patch1 -p1 -b .modeset
 %patch4 -p1 -b .remove-limit-heuristics
 %patch5 -p1 -b .panel-size
-%patch6 -p1 -b .copy-fb-contents
-%patch7 -p1 -b .lvds-mapping
 
 %build
 autoreconf
@@ -76,6 +72,11 @@
 %{_mandir}/man4/radeon.4*
 
 %changelog
+* Fri Oct 10 2008 Dave Airlie <airlied at redhat.com> 6.9.0-23
+- rebase to upstream master
+- radeon-6.9.0-lvds-mapping.patch - merged upstream
+- copy-fb-contents.patch merged into modesetting tree.
+
 * Wed Oct 08 2008 Adam Jackson <ajax at redhat.com> 6.9.0-22
 - radeon-6.9.0-lvds-mapping.patch: Fix connector mapping on LVDS.
 


--- copy-fb-contents.patch DELETED ---


--- radeon-6.9.0-lvds-mapping.patch DELETED ---

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