rpms/kernel/devel drm-modesetting-radeon.patch, 1.35, 1.36 kernel.spec, 1.1047, 1.1048
Dave Airlie
airlied at fedoraproject.org
Wed Oct 15 05:14:27 UTC 2008
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Author: airlied
Update of /cvs/pkgs/rpms/kernel/devel
In directory cvs1.fedora.phx.redhat.com:/tmp/cvs-serv31378
Modified Files:
drm-modesetting-radeon.patch kernel.spec
Log Message:
- radeon modesetting agp support
drm-modesetting-radeon.patch:
Index: drm-modesetting-radeon.patch
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/devel/drm-modesetting-radeon.patch,v
retrieving revision 1.35
retrieving revision 1.36
diff -u -r1.35 -r1.36
--- drm-modesetting-radeon.patch 10 Oct 2008 04:30:38 -0000 1.35
+++ drm-modesetting-radeon.patch 15 Oct 2008 05:14:24 -0000 1.36
@@ -1,19 +1,39 @@
-commit c480d530ddd8d6411cff4c1ebbb17621dc84c6c0
+commit 5bbb48ef3cf9d2886dec4cf8506560bf1c0eeae3
Author: Dave Airlie <airlied at redhat.com>
-Date: Fri Oct 10 11:11:06 2008 +1100
+Date: Wed Oct 15 15:12:20 2008 +1000
+
+ radeon: allow r100/r200 modesetting to be forced on by users
+
+commit b7d5b8a9bf2b5ad059e03f228e7656c1bac6a417
+Author: Dave Airlie <airlied at redhat.com>
+Date: Wed Oct 15 15:06:58 2008 +1000
Revert "Export shmem_file_setup and shmem_getpage for DRM-GEM"
This reverts commit 616950d57d97b4ee4cf8e54be7ae64d1837bbf48.
-commit 0fc9fe74e035feeaad18cf85b9377bb156e77f63
+commit 339b030664112ac72fa9375753acb0f663b1ce54
Author: Dave Airlie <airlied at redhat.com>
-Date: Fri Oct 10 11:10:39 2008 +1100
+Date: Wed Oct 15 15:06:46 2008 +1000
Revert "PCI: Add pci_read_base() API"
This reverts commit 7d4742a79c29febe41d9ddd94831de0f1e1ecbbd.
+commit d4df0f3b862429ab80afc93255164a5d087ce6a3
+Author: airlied <airlied at redhat.com>
+Date: Wed Oct 15 23:58:03 2008 +1000
+
+ radeon: add initial agp support.
+
+ This add agpmode command line option.
+
+commit f54e333d81c7436dc787d365b21ba29bf7fbe299
+Author: airlied <airlied at redhat.com>
+Date: Wed Oct 15 23:57:21 2008 +1000
+
+ radeon: add CS support for r100/r200 in 2D driver
+
commit 11ba50314c04266f02968cfeb7b47bf1bf12f02c
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Oct 9 16:37:23 2008 +1100
@@ -19515,10 +19535,18 @@
+ drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
+}
diff --git a/drivers/gpu/drm/radeon/r300_cmdbuf.c b/drivers/gpu/drm/radeon/r300_cmdbuf.c
-index 4b27d9a..422554e 100644
+index 4b27d9a..0269767 100644
--- a/drivers/gpu/drm/radeon/r300_cmdbuf.c
+++ b/drivers/gpu/drm/radeon/r300_cmdbuf.c
-@@ -166,8 +166,6 @@ void r300_init_reg_flags(struct drm_device *dev)
+@@ -35,6 +35,7 @@
+ #include "drm.h"
+ #include "radeon_drm.h"
+ #include "radeon_drv.h"
++#include "radeon_reg.h"
+ #include "r300_reg.h"
+
+ #define R300_SIMULTANEOUS_CLIPRECTS 4
+@@ -166,8 +167,6 @@ void r300_init_reg_flags(struct drm_device *dev)
for(i=((reg)>>2);i<((reg)>>2)+(count);i++)\
r300_reg_flags[i]|=(mark);
@@ -19527,7 +19555,7 @@
#define ADD_RANGE(reg, count) ADD_RANGE_MARK(reg, count, MARK_SAFE)
-@@ -205,7 +203,7 @@ void r300_init_reg_flags(struct drm_device *dev)
+@@ -205,7 +204,7 @@ void r300_init_reg_flags(struct drm_device *dev)
ADD_RANGE(0x42C0, 2);
ADD_RANGE(R300_RS_CNTL_0, 2);
@@ -19536,7 +19564,7 @@
ADD_RANGE(0x43E8, 1);
ADD_RANGE(0x46A4, 5);
-@@ -224,12 +222,14 @@ void r300_init_reg_flags(struct drm_device *dev)
+@@ -224,12 +223,14 @@ void r300_init_reg_flags(struct drm_device *dev)
ADD_RANGE(0x4E50, 9);
ADD_RANGE(0x4E88, 1);
ADD_RANGE(0x4EA0, 2);
@@ -19557,7 +19585,7 @@
ADD_RANGE(R300_TX_FILTER_0, 16);
ADD_RANGE(R300_TX_FILTER1_0, 16);
-@@ -242,11 +242,16 @@ void r300_init_reg_flags(struct drm_device *dev)
+@@ -242,11 +243,16 @@ void r300_init_reg_flags(struct drm_device *dev)
ADD_RANGE(R300_TX_BORDER_COLOR_0, 16);
/* Sporadic registers used as primitives are emitted */
@@ -19575,7 +19603,7 @@
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
ADD_RANGE(R500_VAP_INDEX_OFFSET, 1);
ADD_RANGE(R500_US_CONFIG, 2);
-@@ -256,7 +261,8 @@ void r300_init_reg_flags(struct drm_device *dev)
+@@ -256,7 +262,8 @@ void r300_init_reg_flags(struct drm_device *dev)
ADD_RANGE(R500_RS_INST_0, 16);
ADD_RANGE(R500_RB3D_COLOR_CLEAR_VALUE_AR, 2);
ADD_RANGE(R500_RB3D_CONSTANT_COLOR_AR, 2);
@@ -19585,7 +19613,7 @@
} else {
ADD_RANGE(R300_PFS_CNTL_0, 3);
ADD_RANGE(R300_PFS_NODE_0, 4);
-@@ -269,9 +275,46 @@ void r300_init_reg_flags(struct drm_device *dev)
+@@ -269,9 +276,109 @@ void r300_init_reg_flags(struct drm_device *dev)
ADD_RANGE(R300_RS_ROUTE_0, 8);
}
@@ -19625,6 +19653,69 @@
+ ADD_RANGE(RADEON_RE_WIDTH_HEIGHT, 1);
+ ADD_RANGE(RADEON_AUX_SC_CNTL, 1);
+ ADD_RANGE(RADEON_RB3D_DSTCACHE_CTLSTAT, 1);
++ ADD_RANGE(RADEON_RB3D_PLANEMASK, 1);
++ ADD_RANGE(RADEON_SE_CNTL, 1);
++ ADD_RANGE(RADEON_PP_CNTL, 1);
++ ADD_RANGE(RADEON_RB3D_CNTL, 1);
++ ADD_RANGE_MARK(RADEON_RB3D_COLOROFFSET, 1, MARK_CHECK_OFFSET);
++ ADD_RANGE(RADEON_RB3D_COLORPITCH, 1);
++ ADD_RANGE(RADEON_RB3D_BLENDCNTL, 1);
++
++ if (dev_priv->chip_family >= CHIP_R200) {
++ ADD_RANGE(R200_PP_CNTL_X, 1);
++ ADD_RANGE(R200_PP_TXMULTI_CTL_0, 1);
++ ADD_RANGE(R200_SE_VTX_STATE_CNTL, 1);
++ ADD_RANGE(R200_RE_CNTL, 1);
++ ADD_RANGE(R200_SE_VTE_CNTL, 1);
++ ADD_RANGE(R200_SE_VAP_CNTL, 1);
++
++ ADD_RANGE(R200_PP_TXFILTER_0, 1);
++ ADD_RANGE(R200_PP_TXFORMAT_0, 1);
++ ADD_RANGE(R200_PP_TXFORMAT_X_0, 1);
++ ADD_RANGE(R200_PP_TXSIZE_0, 1);
++ ADD_RANGE(R200_PP_TXPITCH_0, 1);
++ ADD_RANGE(R200_PP_TFACTOR_0, 1);
++
++ ADD_RANGE(R200_PP_TXFILTER_1, 1);
++ ADD_RANGE(R200_PP_TXFORMAT_1, 1);
++ ADD_RANGE(R200_PP_TXFORMAT_X_1, 1);
++ ADD_RANGE(R200_PP_TXSIZE_1, 1);
++ ADD_RANGE(R200_PP_TXPITCH_1, 1);
++ ADD_RANGE(R200_PP_TFACTOR_1, 1);
++
++ ADD_RANGE_MARK(R200_PP_TXOFFSET_0, 1, MARK_CHECK_OFFSET);
++ ADD_RANGE_MARK(R200_PP_TXOFFSET_1, 1, MARK_CHECK_OFFSET);
++ ADD_RANGE_MARK(R200_PP_TXOFFSET_2, 1, MARK_CHECK_OFFSET);
++ ADD_RANGE_MARK(R200_PP_TXOFFSET_3, 1, MARK_CHECK_OFFSET);
++ ADD_RANGE_MARK(R200_PP_TXOFFSET_4, 1, MARK_CHECK_OFFSET);
++ ADD_RANGE_MARK(R200_PP_TXOFFSET_5, 1, MARK_CHECK_OFFSET);
++
++ ADD_RANGE(R200_SE_VTX_FMT_0, 1);
++ ADD_RANGE(R200_SE_VTX_FMT_1, 1);
++ ADD_RANGE(R200_PP_TXCBLEND_0, 1);
++ ADD_RANGE(R200_PP_TXCBLEND2_0, 1);
++ ADD_RANGE(R200_PP_TXABLEND_0, 1);
++ ADD_RANGE(R200_PP_TXABLEND2_0, 1);
++
++ } else {
++
++ ADD_RANGE(RADEON_PP_TXFILTER_0, 1);
++ ADD_RANGE(RADEON_PP_TXFORMAT_0, 1);
++ ADD_RANGE(RADEON_PP_TEX_SIZE_0, 1);
++ ADD_RANGE(RADEON_PP_TEX_PITCH_0, 1);
++
++ ADD_RANGE(RADEON_PP_TXFILTER_1, 1);
++ ADD_RANGE(RADEON_PP_TXFORMAT_1, 1);
++ ADD_RANGE(RADEON_PP_TEX_SIZE_1, 1);
++ ADD_RANGE(RADEON_PP_TEX_PITCH_1, 1);
++
++ ADD_RANGE(RADEON_PP_TXCBLEND_0, 1);
++ ADD_RANGE(RADEON_PP_TXABLEND_0, 1);
++ ADD_RANGE(RADEON_SE_VTX_FMT, 1);
++ ADD_RANGE_MARK(RADEON_PP_TXOFFSET_0, 1, MARK_CHECK_OFFSET);
++ ADD_RANGE_MARK(RADEON_PP_TXOFFSET_1, 1, MARK_CHECK_OFFSET);
++ ADD_RANGE_MARK(RADEON_PP_TXOFFSET_2, 1, MARK_CHECK_OFFSET);
++ }
+ }
}
@@ -19633,7 +19724,7 @@
{
int i;
if (reg & ~0xffff)
-@@ -282,6 +325,13 @@ static __inline__ int r300_check_range(unsigned reg, int count)
+@@ -282,6 +389,13 @@ static __inline__ int r300_check_range(unsigned reg, int count)
return 0;
}
@@ -19647,7 +19738,7 @@
static __inline__ int r300_emit_carefully_checked_packet0(drm_radeon_private_t *
dev_priv,
drm_radeon_kcmd_buffer_t
-@@ -860,12 +910,12 @@ static __inline__ void r300_pacify(drm_radeon_private_t *dev_priv)
+@@ -860,12 +974,12 @@ static __inline__ void r300_pacify(drm_radeon_private_t *dev_priv)
* The actual age emit is done by r300_do_cp_cmdbuf, which is why you must
* be careful about how this function is called.
*/
@@ -19663,7 +19754,7 @@
buf->pending = 1;
buf->used = 0;
}
-@@ -1027,6 +1077,7 @@ int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -1027,6 +1141,7 @@ int r300_do_cp_cmdbuf(struct drm_device *dev,
drm_radeon_kcmd_buffer_t *cmdbuf)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -19671,7 +19762,7 @@
struct drm_device_dma *dma = dev->dma;
struct drm_buf *buf = NULL;
int emit_dispatch_age = 0;
-@@ -1134,7 +1185,7 @@ int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -1134,7 +1249,7 @@ int r300_do_cp_cmdbuf(struct drm_device *dev,
}
emit_dispatch_age = 1;
@@ -19680,7 +19771,7 @@
break;
case R300_CMD_WAIT:
-@@ -1189,7 +1240,7 @@ int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -1189,7 +1304,7 @@ int r300_do_cp_cmdbuf(struct drm_device *dev,
/* Emit the vertex buffer age */
BEGIN_RING(2);
@@ -22943,7 +23034,7 @@
+ return NULL;
+}
diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c
-index 6157cd4..002af21 100644
+index 6157cd4..d81eb0c 100644
--- a/drivers/gpu/drm/radeon/radeon_cp.c
+++ b/drivers/gpu/drm/radeon/radeon_cp.c
@@ -31,6 +31,7 @@
@@ -23092,13 +23183,13 @@
+ RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, save);
+ }
+}
-+
-+u32 RADEON_READ_PLL(struct drm_radeon_private *dev_priv, int addr)
-+{
-+ uint32_t data;
- RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
- return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
++u32 RADEON_READ_PLL(struct drm_radeon_private *dev_priv, int addr)
++{
++ uint32_t data;
++
+ RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x3f);
+ radeon_pll_errata_after_index(dev_priv);
+ data = RADEON_READ(RADEON_CLOCK_CNTL_DATA);
@@ -23719,7 +23810,7 @@
LOCK_TEST_WITH_RETURN(dev, file_priv);
return radeon_do_engine_reset(dev);
-@@ -1689,6 +1882,603 @@ int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_
+@@ -1689,6 +1882,697 @@ int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_
return ret;
}
@@ -24174,7 +24265,6 @@
+int radeon_modeset_cp_resume(struct drm_device *dev)
+{
+ drm_radeon_private_t *dev_priv = dev->dev_private;
-+ uint32_t tmp;
+
+ radeon_do_wait_for_idle(dev_priv);
+#if __OS_HAS_AGP
@@ -24198,6 +24288,95 @@
+ return 0;
+}
+
++#if __OS_HAS_AGP
++int radeon_modeset_agp_init(struct drm_device *dev)
++{
++ drm_radeon_private_t *dev_priv = dev->dev_private;
++ struct drm_agp_mode mode;
++ struct drm_agp_info info;
++ int ret;
++ int default_mode;
++ uint32_t agp_status;
++ bool is_v3;
++
++ /* Acquire AGP. */
++ ret = drm_agp_acquire(dev);
++ if (ret) {
++ DRM_ERROR("Unable to acquire AGP: %d\n", ret);
++ return ret;
++ }
++
++ ret = drm_agp_info(dev, &info);
++ if (ret) {
++ DRM_ERROR("Unable to get AGP info: %d\n", ret);
++ return ret;
++ }
++
++ mode.mode = info.mode;
++
++ agp_status = (RADEON_READ(RADEON_AGP_STATUS) | RADEON_AGPv3_MODE) & mode.mode;
++ is_v3 = !!(agp_status & RADEON_AGPv3_MODE);
++
++ if (is_v3) {
++ default_mode = (agp_status & RADEON_AGPv3_8X_MODE) ? 8 : 4;
++ } else {
++ if (agp_status & RADEON_AGP_4X_MODE) default_mode = 4;
++ else if (agp_status & RADEON_AGP_2X_MODE) default_mode = 2;
++ else default_mode = 1;
++ }
++
++ if (radeon_agpmode > 0) {
++ if ((radeon_agpmode < (is_v3 ? 4 : 1)) ||
++ (radeon_agpmode > (is_v3 ? 8 : 4)) ||
++ (radeon_agpmode & (radeon_agpmode - 1))) {
++ DRM_ERROR("Illegal AGP Mode: %d (valid %s), leaving at %d\n",
++ radeon_agpmode, is_v3 ? "4, 8" : "1, 2, 4",
++ default_mode);
++ radeon_agpmode = default_mode;
++ }
++ else
++ DRM_INFO("AGP mode requested: %d\n", radeon_agpmode);
++ } else
++ radeon_agpmode = default_mode;
++
++ mode.mode &= ~RADEON_AGP_MODE_MASK;
++ if (is_v3) {
++ switch(radeon_agpmode) {
++ case 8:
++ mode.mode |= RADEON_AGPv3_8X_MODE;
++ break;
++ case 4:
++ default:
++ mode.mode |= RADEON_AGPv3_4X_MODE;
++ break;
++ }
++ } else {
++ switch(radeon_agpmode) {
++ case 4: mode.mode |= RADEON_AGP_4X_MODE;
++ case 2: mode.mode |= RADEON_AGP_2X_MODE;
++ case 1:
++ default:
++ mode.mode |= RADEON_AGP_1X_MODE;
++ break;
++ }
++ }
++
++ mode.mode &= ~RADEON_AGP_FW_MODE; /* disable fw */
++
++ ret = drm_agp_enable(dev, mode);
++ if (ret) {
++ DRM_ERROR("Unable to enable AGP (mode = 0x%lx)\n", mode);
++ return ret;
++ }
++
++ /* workaround some hw issues */
++ if (dev_priv->chip_family <= CHIP_R200) {
++ RADEON_WRITE(RADEON_AGP_CNTL, RADEON_READ(RADEON_AGP_CNTL) | 0x000e0000);
++ }
++ return 0;
++}
++#endif
++
+int radeon_modeset_cp_init(struct drm_device *dev)
+{
+ drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -24229,6 +24408,11 @@
+ dev_priv->new_memmap = true;
+
+ r300_init_reg_flags(dev);
++
++#if __OS_HAS_AGP
++ if (dev_priv->flags & RADEON_IS_AGP)
++ radeon_modeset_agp_init(dev);
++#endif
+
+ return radeon_modeset_cp_resume(dev);
+}
@@ -24318,12 +24502,13 @@
+ }
+ }
+ radeon_force_some_clocks(dev);
++ return 0;
+}
+
int radeon_driver_load(struct drm_device *dev, unsigned long flags)
{
drm_radeon_private_t *dev_priv;
-@@ -1702,6 +2492,8 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
+@@ -1702,6 +2586,8 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
dev->dev_private = (void *)dev_priv;
dev_priv->flags = flags;
@@ -24332,14 +24517,14 @@
switch (flags & RADEON_FAMILY_MASK) {
case CHIP_R100:
case CHIP_RV200:
-@@ -1721,18 +2513,126 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
+@@ -1721,18 +2607,132 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
break;
}
+ /* FEDORA HACKS - don't enable modesetting on pre-r300
+ * until we have a mesa driver in place
+ */
-+ if (dev_priv->chip_family <= CHIP_RV280) {
++ if ((radeon_modeset == -1) && (dev_priv->chip_family <= CHIP_RV280)) {
+ dev->driver->driver_features &= ~DRIVER_MODESET;
+ drm_put_minor(&dev->control);
+ }
@@ -24355,6 +24540,12 @@
DRM_DEBUG("%s card detected\n",
((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
+
++ if ((dev_priv->flags & RADEON_IS_AGP) && (radeon_agpmode == -1)) {
++ DRM_INFO("Forcing AGP to PCI mode\n");
++ dev_priv->flags &= ~RADEON_IS_AGP;
++ }
++
++
+ ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
+ drm_get_resource_len(dev, 2), _DRM_REGISTERS,
+ _DRM_DRIVER | _DRM_READ_ONLY, &dev_priv->mmio);
@@ -24460,7 +24651,7 @@
/* Create mappings for registers and framebuffer so userland doesn't necessarily
* have to find them.
*/
-@@ -1744,19 +2644,6 @@ int radeon_driver_firstopen(struct drm_device *dev)
+@@ -1744,19 +2744,6 @@ int radeon_driver_firstopen(struct drm_device *dev)
dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
@@ -24480,7 +24671,7 @@
return 0;
}
-@@ -1764,9 +2651,40 @@ int radeon_driver_unload(struct drm_device *dev)
+@@ -1764,9 +2751,40 @@ int radeon_driver_unload(struct drm_device *dev)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -24523,10 +24714,10 @@
+}
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
new file mode 100644
-index 0000000..b5a2be8
+index 0000000..6b2e09a
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
-@@ -0,0 +1,417 @@
+@@ -0,0 +1,422 @@
+/*
+ * Copyright 2008 Jerome Glisse.
+ * All Rights Reserved.
@@ -24670,8 +24861,13 @@
+ offset >>= 10;
+ val |= offset;
+ break;
++ case RADEON_RB3D_COLOROFFSET:
+ case R300_RB3D_COLOROFFSET0:
+ case R300_RB3D_DEPTHOFFSET:
++ case R200_PP_TXOFFSET_0:
++ case R200_PP_TXOFFSET_1:
++ case RADEON_PP_TXOFFSET_0:
++ case RADEON_PP_TXOFFSET_1:
+ case R300_TX_OFFSET_0:
+ case R300_TX_OFFSET_0+4:
+ ret = dev_priv->cs.relocate(dev, file_priv, packets + offset_dw + 2, &offset);
@@ -25910,10 +26106,10 @@
+ drm_mode_config_cleanup(dev);
+}
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
-index 71af746..2da1537 100644
+index 71af746..e201792 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
-@@ -35,12 +35,24 @@
+@@ -35,12 +35,28 @@
#include "radeon_drv.h"
#include "drm_pciids.h"
@@ -25922,6 +26118,7 @@
int radeon_no_wb;
+int radeon_dynclks = 1;
+int radeon_r4xx_atom = 0;
++int radeon_agpmode = 0;
MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
module_param_named(no_wb, radeon_no_wb, int, 0444);
@@ -25935,10 +26132,13 @@
+MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
+module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
+
++MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
++module_param_named(agpmode, radeon_agpmode, int, 0444);
++
static int dri_library_name(struct drm_device *dev, char *buf)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
-@@ -52,36 +64,35 @@ static int dri_library_name(struct drm_device *dev, char *buf)
+@@ -52,36 +68,35 @@ static int dri_library_name(struct drm_device *dev, char *buf)
"r300"));
}
@@ -25997,7 +26197,7 @@
.dev_priv_size = sizeof(drm_radeon_buf_priv_t),
.load = radeon_driver_load,
.firstopen = radeon_driver_firstopen,
-@@ -104,7 +115,11 @@ static struct drm_driver driver = {
+@@ -104,7 +119,11 @@ static struct drm_driver driver = {
.get_map_ofs = drm_core_get_map_ofs,
.get_reg_ofs = drm_core_get_reg_ofs,
.ioctls = radeon_ioctls,
@@ -26009,7 +26209,7 @@
.fops = {
.owner = THIS_MODULE,
.open = drm_open,
-@@ -123,6 +138,9 @@ static struct drm_driver driver = {
+@@ -123,6 +142,9 @@ static struct drm_driver driver = {
.id_table = pciidlist,
},
@@ -26019,7 +26219,7 @@
.name = DRIVER_NAME,
.desc = DRIVER_DESC,
.date = DRIVER_DATE,
-@@ -134,6 +152,23 @@ static struct drm_driver driver = {
+@@ -134,6 +156,23 @@ static struct drm_driver driver = {
static int __init radeon_init(void)
{
driver.num_ioctls = radeon_max_ioctl;
@@ -26044,7 +26244,7 @@
}
diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
-index d7e9c6c..73e397a 100644
+index d7e9c6c..6c38154 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.h
+++ b/drivers/gpu/drm/radeon/radeon_drv.h
@@ -34,6 +34,8 @@
@@ -26289,7 +26489,7 @@
} drm_radeon_private_t;
typedef struct drm_radeon_buf_priv {
-@@ -329,6 +450,8 @@ typedef struct drm_radeon_kcmd_buffer {
+@@ -329,8 +450,12 @@ typedef struct drm_radeon_kcmd_buffer {
} drm_radeon_kcmd_buffer_t;
extern int radeon_no_wb;
@@ -26297,8 +26497,12 @@
+extern int radeon_r4xx_atom;
extern struct drm_ioctl_desc radeon_ioctls[];
extern int radeon_max_ioctl;
++extern int radeon_agpmode;
++extern int radeon_modeset;
-@@ -364,12 +487,9 @@ extern struct drm_buf *radeon_freelist_get(struct drm_device * dev);
+ /* Check whether the given hardware address is inside the framebuffer or the
+ * GART area.
+@@ -364,12 +489,9 @@ extern struct drm_buf *radeon_freelist_get(struct drm_device * dev);
extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
@@ -26312,7 +26516,7 @@
extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv);
extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv);
extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv);
-@@ -397,16 +517,19 @@ extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
+@@ -397,16 +519,19 @@ extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
extern int radeon_driver_unload(struct drm_device *dev);
extern int radeon_driver_firstopen(struct drm_device *dev);
@@ -26336,7 +26540,7 @@
/* r300_cmdbuf.c */
extern void r300_init_reg_flags(struct drm_device *dev);
-@@ -414,6 +537,11 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -414,6 +539,11 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
struct drm_file *file_priv,
drm_radeon_kcmd_buffer_t *cmdbuf);
@@ -26348,7 +26552,7 @@
/* Flags for stats.boxes
*/
#define RADEON_BOX_DMA_IDLE 0x1
-@@ -422,10 +550,14 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -422,10 +552,14 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define RADEON_BOX_WAIT_IDLE 0x8
#define RADEON_BOX_TEXTURE_LOAD 0x10
@@ -26363,7 +26567,7 @@
#define RADEON_AGP_COMMAND 0x0f60
#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
# define RADEON_AGP_ENABLE (1<<8)
-@@ -528,16 +660,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -528,16 +662,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define R520_MC_IND_WR_EN (1 << 24)
#define R520_MC_IND_DATA 0x74
@@ -26380,7 +26584,7 @@
#define RADEON_MPP_TB_CONFIG 0x01c0
#define RADEON_MEM_CNTL 0x0140
#define RADEON_MEM_SDRAM_MODE_REG 0x0158
-@@ -602,14 +724,23 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -602,14 +726,23 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define RADEON_SCRATCH_REG3 0x15ec
#define RADEON_SCRATCH_REG4 0x15f0
#define RADEON_SCRATCH_REG5 0x15f4
@@ -26407,7 +26611,7 @@
#define RADEON_GEN_INT_CNTL 0x0040
# define RADEON_CRTC_VBLANK_MASK (1 << 0)
-@@ -628,10 +759,11 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -628,10 +761,11 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
# define RADEON_SW_INT_FIRE (1 << 26)
# define R500_DISPLAY_INT_STATUS (1 << 0)
@@ -26423,7 +26627,7 @@
#define RADEON_ISYNC_CNTL 0x1724
# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
-@@ -670,12 +802,17 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -670,12 +804,17 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define RADEON_PP_TXFILTER_1 0x1c6c
#define RADEON_PP_TXFILTER_2 0x1c84
@@ -26447,7 +26651,7 @@
#define RADEON_RB3D_CNTL 0x1c3c
# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
# define RADEON_PLANE_MASK_ENABLE (1 << 1)
-@@ -702,11 +839,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -702,11 +841,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
# define R300_ZC_FLUSH (1 << 0)
# define R300_ZC_FREE (1 << 1)
# define R300_ZC_BUSY (1 << 31)
@@ -26459,7 +26663,7 @@
#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
# define R300_RB3D_DC_FLUSH (2 << 0)
# define R300_RB3D_DC_FREE (2 << 2)
-@@ -714,15 +846,15 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -714,15 +848,15 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
# define RADEON_Z_TEST_MASK (7 << 4)
# define RADEON_Z_TEST_ALWAYS (7 << 4)
@@ -26479,7 +26683,7 @@
#define RADEON_RBBM_SOFT_RESET 0x00f0
# define RADEON_SOFT_RESET_CP (1 << 0)
# define RADEON_SOFT_RESET_HI (1 << 1)
-@@ -982,27 +1114,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -982,27 +1116,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define RADEON_NUM_VERTICES_SHIFT 16
#define RADEON_COLOR_FORMAT_CI8 2
@@ -26507,7 +26711,7 @@
#define R200_PP_TXCBLEND_0 0x2f00
#define R200_PP_TXCBLEND_1 0x2f10
-@@ -1113,16 +1224,44 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -1113,16 +1226,44 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
@@ -26554,7 +26758,7 @@
#define R500_D1CRTC_STATUS 0x609c
#define R500_D2CRTC_STATUS 0x689c
#define R500_CRTC_V_BLANK (1<<0)
-@@ -1163,19 +1302,36 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -1163,19 +1304,36 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define RADEON_RING_HIGH_MARK 128
#define RADEON_PCIGART_TABLE_SIZE (32*1024)
@@ -26598,7 +26802,7 @@
#define RADEON_WRITE_PCIE(addr, val) \
do { \
RADEON_WRITE8(RADEON_PCIE_INDEX, \
-@@ -1231,7 +1387,7 @@ do { \
+@@ -1231,7 +1389,7 @@ do { \
#define RADEON_WAIT_UNTIL_2D_IDLE() do { \
OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
@@ -26607,7 +26811,7 @@
} while (0)
#define RADEON_WAIT_UNTIL_3D_IDLE() do { \
-@@ -1308,8 +1464,9 @@ do { \
+@@ -1308,8 +1466,9 @@ do { \
} while (0)
#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
@@ -26619,7 +26823,7 @@
if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
int __ret = radeon_do_cp_idle( dev_priv ); \
if ( __ret ) return __ret; \
-@@ -1415,4 +1572,142 @@ do { \
+@@ -1415,4 +1574,142 @@ do { \
write &= mask; \
} while (0)
Index: kernel.spec
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/devel/kernel.spec,v
retrieving revision 1.1047
retrieving revision 1.1048
diff -u -r1.1047 -r1.1048
--- kernel.spec 14 Oct 2008 23:37:08 -0000 1.1047
+++ kernel.spec 15 Oct 2008 05:14:26 -0000 1.1048
@@ -1814,6 +1814,9 @@
%changelog
* Wed Oct 15 2008 Dave Airlie <airlied at redhat.com>
+- radeon modesetting agp support
+
+* Wed Oct 15 2008 Dave Airlie <airlied at redhat.com>
- fix cantiga hopefully.
* Tue Oct 14 2008 Kyle McMartin <kyle at redhat.com>
- Previous message: rpms/gnome-settings-daemon/devel gnome-settings-daemon.spec, 1.69, 1.70
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