rpms/kernel/devel drm-modesetting-radeon.patch, 1.37, 1.38 kernel.spec, 1.1064, 1.1065
Dave Airlie
airlied at fedoraproject.org
Mon Oct 20 03:49:52 UTC 2008
Author: airlied
Update of /cvs/pkgs/rpms/kernel/devel
In directory cvs1.fedora.phx.redhat.com:/tmp/cvs-serv14954
Modified Files:
drm-modesetting-radeon.patch kernel.spec
Log Message:
- radeon: fix writeback + some warning fixes
drm-modesetting-radeon.patch:
Index: drm-modesetting-radeon.patch
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/devel/drm-modesetting-radeon.patch,v
retrieving revision 1.37
retrieving revision 1.38
diff -u -r1.37 -r1.38
--- drm-modesetting-radeon.patch 16 Oct 2008 06:35:09 -0000 1.37
+++ drm-modesetting-radeon.patch 20 Oct 2008 03:49:51 -0000 1.38
@@ -1,3 +1,27 @@
+commit c7adf6d25db7fad1d4e58ea64ca08e79a38ed85e
+Author: Dave Airlie <airlied at redhat.com>
+Date: Mon Oct 20 13:41:05 2008 +1000
+
+ radeon: update proper chip family
+
+commit 571d8a8b1d62edd9728f69d4406edbb8deca2762
+Author: Dave Airlie <airlied at redhat.com>
+Date: Mon Oct 20 12:08:50 2008 +1000
+
+ radeon: fixup scratch register interactions properly
+
+commit af249554b177b7d598c25b07dd0425eb91412891
+Author: Dave Airlie <airlied at redhat.com>
+Date: Mon Oct 20 10:27:50 2008 +1000
+
+ radeon: make writeback work again
+
+commit 36c5e5404e914ea4a6836da0e8d3d855b63103a4
+Author: Dave Airlie <airlied at redhat.com>
+Date: Mon Oct 20 09:20:23 2008 +1000
+
+ drm: cleanup some warnings
+
commit a8d1121ef350f48a88dc4b5830d3fedcc86aaaab
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Oct 16 16:29:08 2008 +1000
@@ -1096,7 +1120,7 @@
drm-$(CONFIG_COMPAT) += drm_ioc32.o
diff --git a/drivers/gpu/drm/ati_pcigart.c b/drivers/gpu/drm/ati_pcigart.c
-index c533d0c..802c6e9 100644
+index c533d0c..adc57dd 100644
--- a/drivers/gpu/drm/ati_pcigart.c
+++ b/drivers/gpu/drm/ati_pcigart.c
@@ -34,9 +34,55 @@
@@ -1110,7 +1134,7 @@
+#define ATI_PCIE_WRITE 0x4
+#define ATI_PCIE_READ 0x8
+
-+static __inline__ void gart_insert_page_into_table(struct drm_ati_pcigart_info *gart_info, dma_addr_t addr, u32 *pci_gart)
++static __inline__ void gart_insert_page_into_table(struct drm_ati_pcigart_info *gart_info, dma_addr_t addr, volatile u32 *pci_gart)
+{
+ u32 page_base;
+
@@ -1132,7 +1156,7 @@
+ *pci_gart = cpu_to_le32(page_base);
+}
+
-+static __inline__ dma_addr_t gart_get_page_from_table(struct drm_ati_pcigart_info *gart_info, u32 *pci_gart)
++static __inline__ dma_addr_t gart_get_page_from_table(struct drm_ati_pcigart_info *gart_info, volatile u32 *pci_gart)
+{
+ dma_addr_t retval;
+ switch(gart_info->gart_reg_if) {
@@ -1164,7 +1188,7 @@
+#ifdef CONFIG_X86
+ /* IGPs only exist on x86 in any case */
+ if (gart_info->gart_reg_if == DRM_ATI_GART_IGP)
-+ set_memory_uc(gart_info->table_handle->vaddr, gart_info->table_size >> PAGE_SHIFT);
++ set_memory_uc((unsigned long)gart_info->table_handle->vaddr, gart_info->table_size >> PAGE_SHIFT);
+#endif
+
+ memset(gart_info->table_handle->vaddr, 0, gart_info->table_size);
@@ -1178,7 +1202,7 @@
+#ifdef CONFIG_X86
+ /* IGPs only exist on x86 in any case */
+ if (gart_info->gart_reg_if == DRM_ATI_GART_IGP)
-+ set_memory_wb(gart_info->table_handle->vaddr, gart_info->table_size >> PAGE_SHIFT);
++ set_memory_wb((unsigned long)gart_info->table_handle->vaddr, gart_info->table_size >> PAGE_SHIFT);
+#endif
drm_pci_free(dev, gart_info->table_handle);
gart_info->table_handle = NULL;
@@ -1321,7 +1345,7 @@
+
+ j = offset;
+ while (j < (offset + atipci_be->num_pages)) {
-+ if (gart_get_page_from_table(info, pci_gart+j))
++ if (gart_get_page_from_table(info, pci_gart + j))
+ return -EBUSY;
+ j++;
+ }
@@ -4543,7 +4567,7 @@
+EXPORT_SYMBOL(drm_bo_pfn_prot);
+
diff --git a/drivers/gpu/drm/drm_bufs.c b/drivers/gpu/drm/drm_bufs.c
-index bde64b8..d4e42e0 100644
+index bde64b8..9ed8259 100644
--- a/drivers/gpu/drm/drm_bufs.c
+++ b/drivers/gpu/drm/drm_bufs.c
@@ -54,9 +54,9 @@ static struct drm_map_list *drm_find_matching_map(struct drm_device *dev,
@@ -4641,7 +4665,7 @@
if (request->count >= dma->buf_count) {
if ((drm_core_has_AGP(dev) && (dma->flags & _DRM_DMA_USE_AGP))
|| (drm_core_check_feature(dev, DRIVER_SG)
-@@ -1521,10 +1535,12 @@ int drm_mapbufs(struct drm_device *dev, void *data,
+@@ -1521,6 +1535,7 @@ int drm_mapbufs(struct drm_device *dev, void *data,
unsigned long token = dev->agp_buffer_token;
if (!map) {
@@ -4649,12 +4673,7 @@
retcode = -EINVAL;
goto done;
}
- down_write(¤t->mm->mmap_sem);
-+ DRM_DEBUG("%x %d\n", token, map->size);
- virtual = do_mmap(file_priv->filp, 0, map->size,
- PROT_READ | PROT_WRITE,
- MAP_SHARED,
-@@ -1538,6 +1554,7 @@ int drm_mapbufs(struct drm_device *dev, void *data,
+@@ -1538,6 +1553,7 @@ int drm_mapbufs(struct drm_device *dev, void *data,
up_write(¤t->mm->mmap_sem);
}
if (virtual > -1024UL) {
@@ -19814,7 +19833,7 @@
}
diff --git a/drivers/gpu/drm/radeon/r300_reg.h b/drivers/gpu/drm/radeon/r300_reg.h
-index ee6f811..ae10d30 100644
+index ee6f811..12f4abb 100644
--- a/drivers/gpu/drm/radeon/r300_reg.h
+++ b/drivers/gpu/drm/radeon/r300_reg.h
@@ -126,15 +126,6 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
@@ -19894,6 +19913,15 @@
# define R300_COLORPITCH_MASK 0x00001FF8 /* GUESS */
# define R300_COLOR_TILE_ENABLE (1 << 16) /* GUESS */
# define R300_COLOR_MICROTILE_ENABLE (1 << 17) /* GUESS */
+@@ -1362,7 +1329,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
+ #define R300_RB3D_COLORPITCH2 0x4E40 /* GUESS */
+ #define R300_RB3D_COLORPITCH3 0x4E44 /* GUESS */
+
+-#define R300_RB3D_AARESOLVE_CTL 0x4E88
++//#define R300_RB3D_AARESOLVE_CTL 0x4E88
+ /* gap */
+
+ /* Guess by Vladimir.
@@ -1377,14 +1344,19 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
* for this.
* Bit (1<<8) is the "test" bit. so plain write is 6 - vd
@@ -20035,7 +20063,7 @@
-# define R500_COVERED_PTR_MASKING_DISABLE (0 << 18)
-# define R500_COVERED_PTR_MASKING_ENABLE (1 << 18)
-
-+#define R300_RB3D_ZCACHE_CTLSTAT 0x4F18 /* GUESS */
++//#define R300_RB3D_ZCACHE_CTLSTAT 0x4F18 /* GUESS */
+# define R300_RB3D_ZCACHE_UNKNOWN_01 0x1
+# define R300_RB3D_ZCACHE_UNKNOWN_03 0x3
@@ -20831,10 +20859,10 @@
+}
diff --git a/drivers/gpu/drm/radeon/radeon_buffer.c b/drivers/gpu/drm/radeon/radeon_buffer.c
new file mode 100644
-index 0000000..e5a9089
+index 0000000..e88378a
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_buffer.c
-@@ -0,0 +1,448 @@
+@@ -0,0 +1,446 @@
+/**************************************************************************
+ *
+ * Copyright 2007 Dave Airlie
@@ -21187,7 +21215,6 @@
+ struct drm_bo_mem_reg tmp_mem;
+ struct drm_bo_mem_reg *old_mem = &bo->mem;
+ int ret;
-+ bool was_local = false;
+
+ /* old - LOCAL memory node bo->mem
+ tmp - TT type memory node
@@ -21235,7 +21262,6 @@
+ int evict, int no_wait, struct drm_bo_mem_reg *new_mem)
+{
+ struct drm_device *dev = bo->dev;
-+ struct drm_bo_mem_reg *old_mem = &bo->mem;
+ drm_radeon_private_t *dev_priv = dev->dev_private;
+
+ if (!dev_priv->cp_running)
@@ -23071,7 +23097,7 @@
+ return NULL;
+}
diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c
-index 6157cd4..c42cb7f 100644
+index 6157cd4..faa35b2 100644
--- a/drivers/gpu/drm/radeon/radeon_cp.c
+++ b/drivers/gpu/drm/radeon/radeon_cp.c
@@ -31,6 +31,7 @@
@@ -23196,7 +23222,9 @@
+ (void)RADEON_READ(RADEON_CLOCK_CNTL_DATA);
+ (void)RADEON_READ(RADEON_CRTC_GEN_CNTL);
+}
-+
+
+- RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
+- return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
+void radeon_pll_errata_after_data(struct drm_radeon_private *dev_priv)
+{
+ /* This workarounds is necessary on RV100, RS100 and RS200 chips
@@ -23219,10 +23247,9 @@
+ tmp = RADEON_READ(RADEON_CLOCK_CNTL_DATA);
+ RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, save);
+ }
-+}
+ }
-- RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
-- return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
+-static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
+u32 RADEON_READ_PLL(struct drm_radeon_private *dev_priv, int addr)
+{
+ uint32_t data;
@@ -23232,9 +23259,8 @@
+ data = RADEON_READ(RADEON_CLOCK_CNTL_DATA);
+ radeon_pll_errata_after_data(dev_priv);
+ return data;
- }
-
--static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
++}
++
+void RADEON_WRITE_PLL(struct drm_radeon_private *dev_priv, int addr, uint32_t data)
+{
+ RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, ((addr & 0x3f) | RADEON_PLL_WR_EN));
@@ -23394,7 +23420,7 @@
#if __OS_HAS_AGP
if (dev_priv->flags & RADEON_IS_AGP) {
RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
-@@ -637,9 +781,14 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
+@@ -637,52 +781,81 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
+ RADEON_SCRATCH_REG_OFFSET);
@@ -23410,9 +23436,13 @@
+ dev_priv->ring_rptr->handle +
+ (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
- RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
+- RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
++ if (dev_priv->chip_family >= CHIP_R300)
++ RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7f);
++ else
++ RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x1f);
-@@ -647,30 +796,41 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
+ /* Turn on bus mastering */
tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
RADEON_WRITE(RADEON_BUS_CNTL, tmp);
@@ -23420,17 +23450,26 @@
- RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
+ dev_priv->scratch[0] = 0;
+ RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
++
++ dev_priv->scratch[1] = 0;
++ RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
- dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
- RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
- dev_priv->sarea_priv->last_dispatch);
-+ dev_priv->scratch[1] = 0;
-+ RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
++ dev_priv->scratch[2] = 0;
++ RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
- dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
- RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
-+ dev_priv->scratch[2] = 0;
-+ RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
++ dev_priv->scratch[3] = 0;
++ RADEON_WRITE(RADEON_LAST_SWI_REG, 0);
++
++ dev_priv->scratch[4] = 0;
++ RADEON_WRITE(RADEON_SCRATCH_REG4, 0);
++
++ dev_priv->scratch[6] = 0;
++ RADEON_WRITE(RADEON_SCRATCH_REG6, 0);
radeon_do_wait_for_idle(dev_priv);
@@ -23452,7 +23491,8 @@
static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
{
- u32 tmp;
+- u32 tmp;
++ u32 tmp, scratch1_store;
+ void *ring_read_ptr;
+
+ if (dev_priv->mm.ring_read.bo)
@@ -23462,7 +23502,8 @@
/* Start with assuming that writeback doesn't work */
dev_priv->writeback_works = 0;
-@@ -678,11 +838,11 @@ static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
+
++ scratch1_store = RADEON_READ(RADEON_SCRATCH_REG1);
/* Writeback doesn't seem to work everywhere, test it here and possibly
* enable it if it appears to work
*/
@@ -23476,9 +23517,13 @@
0xdeadbeef)
break;
DRM_UDELAY(1);
-@@ -701,9 +861,8 @@ static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
+@@ -700,10 +873,12 @@ static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
+ DRM_INFO("writeback forced off\n");
}
++ /* write back previous value */
++ RADEON_WRITE(RADEON_SCRATCH_REG1, scratch1_store);
++
if (!dev_priv->writeback_works) {
- /* Disable writeback to avoid unnecessary bus master transfer */
- RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
@@ -23488,7 +23533,7 @@
RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
}
}
-@@ -715,11 +874,12 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
+@@ -715,11 +890,12 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
if (on) {
DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
@@ -23504,7 +23549,7 @@
if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
RS690_BLOCK_GFX_D3_EN));
-@@ -743,13 +903,20 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
+@@ -743,13 +919,20 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
RS480_REQ_TYPE_SNOOP_DIS));
@@ -23529,7 +23574,7 @@
temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
-@@ -760,7 +927,7 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
+@@ -760,7 +943,7 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
break;
DRM_UDELAY(1);
@@ -23538,7 +23583,7 @@
IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
RS480_GART_CACHE_INVALIDATE);
-@@ -770,7 +937,7 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
+@@ -770,7 +953,7 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
break;
DRM_UDELAY(1);
@@ -23547,7 +23592,7 @@
IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
} else {
-@@ -797,7 +964,7 @@ static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
+@@ -797,7 +980,7 @@ static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
dev_priv->gart_vm_start +
dev_priv->gart_size - 1);
@@ -23556,7 +23601,7 @@
RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
RADEON_PCIE_TX_GART_EN);
-@@ -808,7 +975,7 @@ static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
+@@ -808,7 +991,7 @@ static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
}
/* Enable or disable PCI GART on the chip */
@@ -23565,7 +23610,7 @@
{
u32 tmp;
-@@ -841,7 +1008,7 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
+@@ -841,7 +1024,7 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
/* Turn off AGP aperture -- is this required for PCI GART?
*/
@@ -23574,7 +23619,7 @@
RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
} else {
RADEON_WRITE(RADEON_AIC_CNTL,
-@@ -849,9 +1016,11 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
+@@ -849,9 +1032,11 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
}
}
@@ -23587,7 +23632,7 @@
DRM_DEBUG("\n");
-@@ -889,17 +1058,6 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
+@@ -889,17 +1074,6 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
*/
dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
@@ -23605,7 +23650,7 @@
dev_priv->do_boxes = 0;
dev_priv->cp_mode = init->cp_mode;
-@@ -947,9 +1105,8 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
+@@ -947,9 +1121,8 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
*/
dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
(dev_priv->color_fmt << 10) |
@@ -23617,7 +23662,7 @@
dev_priv->depth_clear.rb3d_zstencilcntl =
(dev_priv->depth_fmt |
RADEON_Z_TEST_ALWAYS |
-@@ -976,8 +1133,8 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
+@@ -976,8 +1149,8 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
dev_priv->buffers_offset = init->buffers_offset;
dev_priv->gart_textures_offset = init->gart_textures_offset;
@@ -23628,7 +23673,7 @@
DRM_ERROR("could not find sarea!\n");
radeon_do_cleanup_cp(dev);
return -EINVAL;
-@@ -1013,10 +1170,6 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
+@@ -1013,10 +1186,6 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
}
}
@@ -23639,7 +23684,7 @@
#if __OS_HAS_AGP
if (dev_priv->flags & RADEON_IS_AGP) {
drm_core_ioremap(dev_priv->cp_ring, dev);
-@@ -1146,28 +1299,41 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
+@@ -1146,28 +1315,41 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
/* if we have an offset set from userspace */
if (dev_priv->pcigart_offset_set) {
@@ -23701,7 +23746,7 @@
if (dev_priv->flags & RADEON_IS_IGPGART)
dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
else
-@@ -1176,12 +1342,7 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
+@@ -1176,12 +1358,7 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
DRM_ATI_GART_MAIN;
dev_priv->gart_info.addr = NULL;
dev_priv->gart_info.bus_addr = 0;
@@ -23715,7 +23760,7 @@
}
if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
-@@ -1194,6 +1355,9 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
+@@ -1194,6 +1371,9 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
radeon_set_pcigart(dev_priv, 1);
}
@@ -23725,7 +23770,7 @@
radeon_cp_load_microcode(dev_priv);
radeon_cp_init_ring_buffer(dev, dev_priv);
-@@ -1238,14 +1402,16 @@ static int radeon_do_cleanup_cp(struct drm_device * dev)
+@@ -1238,14 +1418,16 @@ static int radeon_do_cleanup_cp(struct drm_device * dev)
if (dev_priv->gart_info.bus_addr) {
/* Turn off PCI GART */
radeon_set_pcigart(dev_priv, 0);
@@ -23746,7 +23791,7 @@
}
}
/* only clear to the start of flags */
-@@ -1297,6 +1463,10 @@ static int radeon_do_resume_cp(struct drm_device * dev)
+@@ -1297,6 +1479,10 @@ static int radeon_do_resume_cp(struct drm_device * dev)
int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
drm_radeon_init_t *init = data;
@@ -23757,7 +23802,7 @@
LOCK_TEST_WITH_RETURN(dev, file_priv);
-@@ -1307,7 +1477,7 @@ int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_pri
+@@ -1307,7 +1493,7 @@ int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_pri
case RADEON_INIT_CP:
case RADEON_INIT_R200_CP:
case RADEON_INIT_R300_CP:
@@ -23766,7 +23811,7 @@
case RADEON_CLEANUP_CP:
return radeon_do_cleanup_cp(dev);
}
-@@ -1320,6 +1490,9 @@ int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_pr
+@@ -1320,6 +1506,9 @@ int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_pr
drm_radeon_private_t *dev_priv = dev->dev_private;
DRM_DEBUG("\n");
@@ -23776,7 +23821,7 @@
LOCK_TEST_WITH_RETURN(dev, file_priv);
if (dev_priv->cp_running) {
-@@ -1347,6 +1520,9 @@ int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_pri
+@@ -1347,6 +1536,9 @@ int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_pri
int ret;
DRM_DEBUG("\n");
@@ -23786,7 +23831,7 @@
LOCK_TEST_WITH_RETURN(dev, file_priv);
if (!dev_priv->cp_running)
-@@ -1385,6 +1561,9 @@ void radeon_do_release(struct drm_device * dev)
+@@ -1385,6 +1577,9 @@ void radeon_do_release(struct drm_device * dev)
drm_radeon_private_t *dev_priv = dev->dev_private;
int i, ret;
@@ -23796,7 +23841,7 @@
if (dev_priv) {
if (dev_priv->cp_running) {
/* Stop the cp */
-@@ -1418,6 +1597,9 @@ void radeon_do_release(struct drm_device * dev)
+@@ -1418,6 +1613,9 @@ void radeon_do_release(struct drm_device * dev)
radeon_mem_takedown(&(dev_priv->gart_heap));
radeon_mem_takedown(&(dev_priv->fb_heap));
@@ -23806,7 +23851,7 @@
/* deallocate kernel resources */
radeon_do_cleanup_cp(dev);
}
-@@ -1430,6 +1612,9 @@ int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_pr
+@@ -1430,6 +1628,9 @@ int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_pr
drm_radeon_private_t *dev_priv = dev->dev_private;
DRM_DEBUG("\n");
@@ -23816,7 +23861,7 @@
LOCK_TEST_WITH_RETURN(dev, file_priv);
if (!dev_priv) {
-@@ -1450,7 +1635,9 @@ int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_pri
+@@ -1450,7 +1651,9 @@ int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_pri
drm_radeon_private_t *dev_priv = dev->dev_private;
DRM_DEBUG("\n");
@@ -23827,7 +23872,7 @@
return radeon_do_cp_idle(dev_priv);
}
-@@ -1460,6 +1647,9 @@ int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_pri
+@@ -1460,6 +1663,9 @@ int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_pri
int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
@@ -23837,7 +23882,7 @@
return radeon_do_resume_cp(dev);
}
-@@ -1467,6 +1657,9 @@ int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *fil
+@@ -1467,6 +1673,9 @@ int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *fil
{
DRM_DEBUG("\n");
@@ -23847,7 +23892,7 @@
LOCK_TEST_WITH_RETURN(dev, file_priv);
return radeon_do_engine_reset(dev);
-@@ -1689,6 +1882,701 @@ int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_
+@@ -1689,6 +1898,703 @@ int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_
return ret;
}
@@ -24321,6 +24366,8 @@
+
+ radeon_do_engine_reset(dev);
+
++ radeon_test_writeback(dev_priv);
++
+ radeon_do_cp_start(dev_priv);
+ return 0;
+}
@@ -24402,7 +24449,7 @@
+
+ ret = drm_agp_enable(dev, mode);
+ if (ret) {
-+ DRM_ERROR("Unable to enable AGP (mode = 0x%lx)\n", mode);
++ DRM_ERROR("Unable to enable AGP (mode = 0x%lx)\n", mode.mode);
+ return ret;
+ }
+
@@ -24425,7 +24472,7 @@
+ dev_priv->writeback_works = 0;
+
+ if (dev_priv->chip_family > CHIP_R600)
-+ return;
++ return 0;
+
+ dev_priv->usec_timeout = RADEON_DEFAULT_CP_TIMEOUT;
+ dev_priv->ring.size = RADEON_DEFAULT_RING_SIZE;
@@ -24549,7 +24596,7 @@
int radeon_driver_load(struct drm_device *dev, unsigned long flags)
{
drm_radeon_private_t *dev_priv;
-@@ -1702,6 +2590,8 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
+@@ -1702,6 +2608,8 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
dev->dev_private = (void *)dev_priv;
dev_priv->flags = flags;
@@ -24558,7 +24605,7 @@
switch (flags & RADEON_FAMILY_MASK) {
case CHIP_R100:
case CHIP_RV200:
-@@ -1721,6 +2611,14 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
+@@ -1721,6 +2629,14 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
break;
}
@@ -24573,7 +24620,7 @@
if (drm_device_is_agp(dev))
dev_priv->flags |= RADEON_IS_AGP;
else if (drm_device_is_pcie(dev))
-@@ -1730,9 +2628,115 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
+@@ -1730,33 +2646,123 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
DRM_DEBUG("%s card detected\n",
((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
@@ -24668,7 +24715,6 @@
+void radeon_master_destroy(struct drm_device *dev, struct drm_master *master)
+{
+ struct drm_radeon_master_private *master_priv = master->driver_priv;
-+ struct drm_radeon_private *dev_priv = dev->dev_private;
+
+ if (!master_priv)
+ return;
@@ -24689,7 +24735,11 @@
/* Create mappings for registers and framebuffer so userland doesn't necessarily
* have to find them.
*/
-@@ -1744,19 +2748,6 @@ int radeon_driver_firstopen(struct drm_device *dev)
+ int radeon_driver_firstopen(struct drm_device *dev)
+ {
+- int ret;
+- drm_local_map_t *map;
+ drm_radeon_private_t *dev_priv = dev->dev_private;
dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
@@ -24709,7 +24759,7 @@
return 0;
}
-@@ -1764,9 +2755,40 @@ int radeon_driver_unload(struct drm_device *dev)
+@@ -1764,9 +2770,40 @@ int radeon_driver_unload(struct drm_device *dev)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -24752,7 +24802,7 @@
+}
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
new file mode 100644
-index 0000000..5c7b2a5
+index 0000000..d760efe
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -0,0 +1,399 @@
@@ -25128,14 +25178,14 @@
+{
+ drm_radeon_private_t *dev_priv = dev->dev_private;
+
-+ return RADEON_READ(RADEON_SCRATCH_REG4);
++ return GET_SCRATCH(4);
+}
+
+uint32_t r300_cs_id_last_get(struct drm_device *dev)
+{
+ drm_radeon_private_t *dev_priv = dev->dev_private;
+
-+ return RADEON_READ(RADEON_SCRATCH_REG6);
++ return GET_SCRATCH(6);
+}
+
+int radeon_cs_init(struct drm_device *dev)
@@ -26259,7 +26309,7 @@
}
diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
-index d7e9c6c..6c38154 100644
+index d7e9c6c..ffbeed4 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.h
+++ b/drivers/gpu/drm/radeon/radeon_drv.h
@@ -34,6 +34,8 @@
@@ -26612,11 +26662,11 @@
-#define GET_SCRATCH( x ) (dev_priv->writeback_works \
- ? DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(x) ) \
- : RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x) ) )
-+#define GET_SCRATCH( x ) (dev_priv->writeback_works ? \
-+ (dev_priv->mm.ring_read.bo ? \
-+ readl(dev_priv->mm.ring_read.kmap.virtual + RADEON_SCRATCHOFF(x)) : \
-+ DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(x))) : \
-+ RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x)))
++#define GET_SCRATCH( x ) (dev_priv->writeback_works ? \
++ (dev_priv->mm.ring_read.bo ? \
++ readl(dev_priv->mm.ring_read.kmap.virtual + RADEON_SCRATCHOFF(x)) : \
++ DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(x))) : \
++ RADEON_READ( RADEON_SCRATCH_REG0 + 4*(x)))
+
+#define RADEON_CRTC_CRNT_FRAME 0x0214
+#define RADEON_CRTC2_CRNT_FRAME 0x0314
@@ -26656,7 +26706,7 @@
+#define R300_DSTCACHE_CTLSTAT 0x1714
+# define R300_RB2D_DC_FLUSH (3 << 0)
+# define R300_RB2D_DC_FREE (3 << 2)
-+# define R300_RB2D_DC_FLUSH_ALL 0xf
++//# define R300_RB2D_DC_FLUSH_ALL 0xf
+# define R300_RB2D_DC_BUSY (1 << 31)
+#define RADEON_RB2D_DSTCACHE_CTLSTAT 0x342c
+# define RADEON_RB2D_DC_FLUSH (3 << 0)
@@ -26888,7 +26938,7 @@
+#define BREADCRUMB_MASK ((1U << BREADCRUMB_BITS) - 1)
+
+/* Breadcrumb - swi irq */
-+#define READ_BREADCRUMB(dev_priv) RADEON_READ(RADEON_LAST_SWI_REG)
++#define READ_BREADCRUMB(dev_priv) GET_SCRATCH(3)
+
+static inline int radeon_update_breadcrumb(struct drm_device *dev)
+{
Index: kernel.spec
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/devel/kernel.spec,v
retrieving revision 1.1064
retrieving revision 1.1065
diff -u -r1.1064 -r1.1065
--- kernel.spec 19 Oct 2008 19:12:46 -0000 1.1064
+++ kernel.spec 20 Oct 2008 03:49:51 -0000 1.1065
@@ -1840,6 +1840,9 @@
%kernel_variant_files -k vmlinux %{with_kdump} kdump
%changelog
+* Mon Oct 20 2008 Dave Airlie <airlied at redhat.com>
+- radeon: fix writeback + some warning fixes
+
* Sun Oct 19 2008 Dave Jones <davej at redhat.com>
- Disable debug printks in the memstick drivers.
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