rpms/kernel/devel drm-modesetting-radeon.patch, 1.39, 1.40 drm-next.patch, 1.1, 1.2 kernel.spec, 1.1069, 1.1070
Dave Airlie
airlied at fedoraproject.org
Tue Oct 21 04:43:30 UTC 2008
Author: airlied
Update of /cvs/pkgs/rpms/kernel/devel
In directory cvs1.fedora.phx.redhat.com:/tmp/cvs-serv4715
Modified Files:
drm-modesetting-radeon.patch drm-next.patch kernel.spec
Log Message:
- rebase to drm-next from upstream for GEM fixes.
- drop intel modesetting for now - broken by rebase
drm-modesetting-radeon.patch:
View full diff with command:
/usr/bin/cvs -f diff -kk -u -N -r 1.39 -r 1.40 drm-modesetting-radeon.patch
Index: drm-modesetting-radeon.patch
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/devel/drm-modesetting-radeon.patch,v
retrieving revision 1.39
retrieving revision 1.40
diff -u -r1.39 -r1.40
--- drm-modesetting-radeon.patch 20 Oct 2008 04:49:19 -0000 1.39
+++ drm-modesetting-radeon.patch 21 Oct 2008 04:42:59 -0000 1.40
@@ -1,4 +1,16 @@
-commit 9d7a3bf0e8bda9845c6fee4ddc20a4bdd9ec3cf7
+commit 0e05709a0476a4572d5bc5ff44a56fc880781a19
+Author: Dave Airlie <airlied at redhat.com>
+Date: Tue Oct 21 14:15:23 2008 +1000
+
+ radeon: add r423 bits to modesetting
+
+commit b1ce1ffa6e1cef9d5c41d4ec26cc79340305565a
+Author: Dave Airlie <airlied at redhat.com>
+Date: Tue Oct 21 14:12:38 2008 +1000
+
+ radeon: pull bus master enable into its own function
+
+commit 0eff75d4d9349e6e46b8ef63fd16d6dd9269a013
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Oct 20 14:44:23 2008 +1000
@@ -7,55 +19,55 @@
We actually were passing accessible to userspace, but I thought
the code sized it correctly, however it doesn't seem to.
-commit c7adf6d25db7fad1d4e58ea64ca08e79a38ed85e
+commit 04107087a90fe834f6c769d8420b9ed4809ffa6b
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Oct 20 13:41:05 2008 +1000
radeon: update proper chip family
-commit 571d8a8b1d62edd9728f69d4406edbb8deca2762
+commit 6e0dcdb71bcd68f7bd25d0419382ae231a98b8ba
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Oct 20 12:08:50 2008 +1000
radeon: fixup scratch register interactions properly
-commit af249554b177b7d598c25b07dd0425eb91412891
+commit 31c9b81bce79fab9b96c94da4b5fda84deff1f7a
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Oct 20 10:27:50 2008 +1000
radeon: make writeback work again
-commit 36c5e5404e914ea4a6836da0e8d3d855b63103a4
+commit 18c8b4c2267b28ba754d109d9d9a67bf75dfdd2f
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Oct 20 09:20:23 2008 +1000
drm: cleanup some warnings
-commit a8d1121ef350f48a88dc4b5830d3fedcc86aaaab
+commit 78cfff6172963ab4d9bbec7819653302a8bde6d8
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Oct 16 16:29:08 2008 +1000
radeon: fix small typo in agp code
-commit 068d1a6e3523584476cd01e7447de63538ff51e3
+commit c564235fa95857553c35b2f7e2fc0d8f1b5ffbc3
Author: Dave Airlie <airlied at panoply-rh.(none)>
Date: Thu Oct 16 16:17:01 2008 +1000
radeon: workaround failure to parse some rs48x edid
-commit fdced11a334aa933a284cb3bb4062bb2bfb9b976
+commit f804be320ef13c9b96ae084727548a2d8ca01ebf
Author: Dave Airlie <airlied at panoply-rh.(none)>
Date: Thu Oct 16 16:15:08 2008 +1000
radeon: don't enable dynclks on rs48x
-commit b4c0125eef83accaa5940724dd039bfdb97d4631
+commit 98868e03ee02b0cb71108191604ea0f985617354
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Oct 15 15:12:20 2008 +1000
radeon: allow r100/r200 modesetting to be forced on by users
-commit c48d4d72ebb5d9c29cdb46bead02bb3943194c6e
+commit 1e2d567372b8e33b195a1be82afa80dd7e0a6499
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Oct 15 15:06:58 2008 +1000
@@ -63,7 +75,7 @@
This reverts commit 616950d57d97b4ee4cf8e54be7ae64d1837bbf48.
-commit 1060fcfe553cfe252b0c7d690b95b9253a0ade7e
+commit accc2d381f9ed14fa291747fff012204f6a3ad1e
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Oct 15 15:06:46 2008 +1000
@@ -71,19 +83,19 @@
This reverts commit 7d4742a79c29febe41d9ddd94831de0f1e1ecbbd.
-commit 0d707528d36e39bf56e0790afdd0bd4b5756bc18
+commit 13718aa9c51cda7b89875c41693012a01860e42e
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Oct 16 22:06:00 2008 +1000
radeon: fix unused agp functionality
-commit 235069a7d43dafa58c3c7b988c5cb3293d6cecea
+commit 73a3f4da99814dc47c3c5da3247e93fdcebb56f6
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Oct 16 22:05:02 2008 +1000
radeon: add some more r100 support to test AGP
-commit d4df0f3b862429ab80afc93255164a5d087ce6a3
+commit 3c93cff1e09a46435c5f8ecf5368a1e4c67433b6
Author: airlied <airlied at redhat.com>
Date: Wed Oct 15 23:58:03 2008 +1000
@@ -91,55 +103,55 @@
This add agpmode command line option.
-commit f54e333d81c7436dc787d365b21ba29bf7fbe299
+commit 5400f72c4a6f5b4bea6551cb555eb0f8028bcb34
Author: airlied <airlied at redhat.com>
Date: Wed Oct 15 23:57:21 2008 +1000
radeon: add CS support for r100/r200 in 2D driver
-commit 11ba50314c04266f02968cfeb7b47bf1bf12f02c
+commit 4d5b56fd7ecf73a1845153d0b8e419e5231bdae2
Author: Dave Airlie <airlied at redhat.com>
Date: Thu Oct 9 16:37:23 2008 +1100
radeon: fixup interrupt suspend/resume
-commit 1d8889406aae5377fa11dc6f70b1f3779c92859b
+commit d941ac5df83e13eedb9e8b145c125a0462e629a4
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Oct 8 16:57:12 2008 +1000
radeon: fixup suspend/resume bus master enable
-commit e2c0ae4ce8166609ee17b7aec17bf7df262f5604
+commit 0d71b170f7c61b8e1901e9289bd54a305a82c3dc
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Oct 8 16:56:04 2008 +1000
radeon: re-enable hw blits for copying from VRAM
-commit ce39e69bde7f0a4730ce97685ec38d4fd69f430d
+commit f375bd5103f90c8bc2ccca45e45b565689cd397e
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Oct 8 16:53:43 2008 +1000
radeon: fix buffer copying for VRAM->TT
-commit f909028374ba26f555f14f3a3c2e1f685cd4e3ad
+commit c7f64fbe53f8ca5e6a712c0b14672678699a0a68
Author: Dave Airlie <airlied at redhat.com>
Date: Wed Oct 8 16:51:58 2008 +1000
radeon: move memcpy until after CP is stopped
-commit 9fa99ced6f5c3ad1d5eb4dad951d82dd32e172a7
+commit 6aafe86f062830a461b2d094e7249312732758c5
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Oct 7 16:34:12 2008 +1000
drm: remove stray debug code
-commit f82ba426179e2569dbb629babd2eb1a72493a1e4
+commit b83ea550b99b8edf0a9ecda34988ac748e44aa34
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Oct 7 16:31:22 2008 +1000
radeon: use discardable flags on no backing store objects
-commit 4851285dd0d4b2f596f3abc666346190fffbdd8a
+commit 0bf01f29ee13bc5da3ac9560efee7224de9ce6e9
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Oct 7 16:30:09 2008 +1000
@@ -148,7 +160,7 @@
This discards memory contents on suspend/resume with the
hope the upper layers know something we don't.
-commit 1c9d7a0dd67f4f9de1abc0b901b58971d9d1accc
+commit 67e4a78e3fce137cc186287efd65d067fe6de878
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Oct 7 16:27:31 2008 +1000
@@ -157,7 +169,7 @@
This enables the evict code and also sets radeon up
to allow evict from VRAM to LOCAL
[...2005 lines suppressed...]
#define RADEON_PCIGART_TABLE_SIZE (32*1024)
@@ -26876,7 +26920,7 @@
#define RADEON_WRITE_PCIE(addr, val) \
do { \
RADEON_WRITE8(RADEON_PCIE_INDEX, \
-@@ -1231,7 +1389,7 @@ do { \
+@@ -1259,7 +1415,7 @@ do { \
#define RADEON_WAIT_UNTIL_2D_IDLE() do { \
OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
@@ -26885,7 +26929,7 @@
} while (0)
#define RADEON_WAIT_UNTIL_3D_IDLE() do { \
-@@ -1308,8 +1466,9 @@ do { \
+@@ -1336,8 +1492,9 @@ do { \
} while (0)
#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
@@ -26897,7 +26941,7 @@
if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
int __ret = radeon_do_cp_idle( dev_priv ); \
if ( __ret ) return __ret; \
-@@ -1415,4 +1574,142 @@ do { \
+@@ -1443,4 +1600,143 @@ do { \
write &= mask; \
} while (0)
@@ -26984,6 +27028,7 @@
+ (dev_priv->chip_family == CHIP_R350) || \
+ (dev_priv->chip_family == CHIP_RV380) || \
+ (dev_priv->chip_family == CHIP_R420) || \
++ (dev_priv->chip_family == CHIP_R423) || \
+ (dev_priv->chip_family == CHIP_RV410) || \
+ (dev_priv->chip_family == CHIP_RS400) || \
+ (dev_priv->chip_family == CHIP_RS480))
@@ -27031,7 +27076,7 @@
+extern int radeon_cs_init(struct drm_device *dev);
+void radeon_gem_update_offsets(struct drm_device *dev, struct drm_master *master);
+void radeon_init_memory_map(struct drm_device *dev);
-+
++void radeon_enable_bm(struct drm_radeon_private *dev_priv);
+
+#define MARK_SAFE 1
+#define MARK_CHECK_OFFSET 2
@@ -29187,10 +29232,10 @@
+
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
new file mode 100644
-index 0000000..5ecd8c5
+index 0000000..4b15fac
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
-@@ -0,0 +1,1614 @@
+@@ -0,0 +1,1616 @@
+/*
+ * Copyright 2008 Red Hat Inc.
+ *
@@ -29718,6 +29763,7 @@
+ dev_priv->chip_family == CHIP_RV350 ||
+ dev_priv->chip_family == CHIP_RV380 ||
+ dev_priv->chip_family == CHIP_R420 ||
++ dev_priv->chip_family == CHIP_R423 ||
+ dev_priv->chip_family == CHIP_RV410 ||
+ radeon_is_avivo(dev_priv)) {
+ uint32_t temp = RADEON_READ(RADEON_HOST_PATH_CNTL);
@@ -30156,6 +30202,7 @@
+ dev_priv->chip_family == CHIP_RV350 ||
+ dev_priv->chip_family == CHIP_RV380 ||
+ dev_priv->chip_family == CHIP_R420 ||
++ dev_priv->chip_family == CHIP_R423 ||
+ dev_priv->chip_family == CHIP_RV410)
+ aper0_base &= ~(mem_size - 1);
+
@@ -32147,10 +32194,10 @@
+}
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_encoders.c b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
new file mode 100644
-index 0000000..261501d
+index 0000000..3df89d3
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c
-@@ -0,0 +1,1368 @@
+@@ -0,0 +1,1371 @@
+/*
+ * Copyright 2007-8 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
@@ -33223,6 +33270,7 @@
+ crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
+ //tv_master_cntl |= RADEON_TV_ON;
+ if (dev_priv->chip_family == CHIP_R420 ||
++ dev_priv->chip_family == CHIP_R423 ||
+ dev_priv->chip_family == CHIP_RV410)
+ tv_dac_cntl &= ~(R420_TV_DAC_RDACPD |
+ R420_TV_DAC_GDACPD |
@@ -33248,6 +33296,7 @@
+ crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
+ //tv_master_cntl &= ~RADEON_TV_ON;
+ if (dev_priv->chip_family == CHIP_R420 ||
++ dev_priv->chip_family == CHIP_R423 ||
+ dev_priv->chip_family == CHIP_RV410)
+ tv_dac_cntl |= (R420_TV_DAC_RDACPD |
+ R420_TV_DAC_GDACPD |
@@ -33311,6 +33360,7 @@
+ if (dev_priv->chip_family != CHIP_R200) {
+ tv_dac_cntl = RADEON_READ(RADEON_TV_DAC_CNTL);
+ if (dev_priv->chip_family == CHIP_R420 ||
++ dev_priv->chip_family == CHIP_R423 ||
+ dev_priv->chip_family == CHIP_RV410) {
+ tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
+ RADEON_TV_DAC_BGADJ_MASK |
@@ -33890,10 +33940,10 @@
+#endif
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
new file mode 100644
-index 0000000..ee0ae59
+index 0000000..df2739f
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
-@@ -0,0 +1,252 @@
+@@ -0,0 +1,248 @@
+/*
+ * Copyright 2007-8 Advanced Micro Devices, Inc.
+ * Copyright 2008 Red Hat Inc.
@@ -33989,7 +34039,6 @@
+ struct drm_radeon_private *dev_priv = dev->dev_private;
+ struct drm_framebuffer *fb;
+ int i;
-+ u32 tmp;
+
+ if (!drm_core_check_feature(dev, DRIVER_MODESET))
+ return 0;
@@ -34000,10 +34049,7 @@
+ return -1;
+
+ /* Turn on bus mastering -todo fix properly */
-+ if (dev_priv->chip_family < CHIP_RV380) {
-+ tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
-+ RADEON_WRITE(RADEON_BUS_CNTL, tmp);
-+ }
++ radeon_enable_bm(dev_priv);
+
+ DRM_ERROR("\n");
+ /* on atom cards re init the whole card
@@ -40298,7 +40344,7 @@
* Device specific ioctls should only be in their respective headers
* The device specific ioctl range is from 0x40 to 0x99.
diff --git a/include/drm/drmP.h b/include/drm/drmP.h
-index 90a9e02..5e2a174 100644
+index 59c796b..d2bff8e 100644
--- a/include/drm/drmP.h
+++ b/include/drm/drmP.h
@@ -87,6 +87,7 @@ struct drm_device;
@@ -40579,8 +40625,8 @@
static inline int drm_dev_to_irq(struct drm_device *dev)
{
-@@ -1019,6 +1107,17 @@ extern DRM_AGP_MEM *drm_agp_bind_pages(struct drm_device *dev,
- uint32_t gtt_offset);
+@@ -1020,6 +1108,17 @@ extern DRM_AGP_MEM *drm_agp_bind_pages(struct drm_device *dev,
+ uint32_t type);
extern int drm_unbind_agp(DRM_AGP_MEM * handle);
+extern void drm_free_memctl(size_t size);
@@ -40597,7 +40643,7 @@
/* Misc. IOCTL support (drm_ioctl.h) */
extern int drm_irq_by_busid(struct drm_device *dev, void *data,
struct drm_file *file_priv);
-@@ -1189,9 +1288,17 @@ extern DRM_AGP_MEM *drm_agp_allocate_memory(struct agp_bridge_data *bridge, size
+@@ -1190,9 +1289,17 @@ extern DRM_AGP_MEM *drm_agp_allocate_memory(struct agp_bridge_data *bridge, size
extern int drm_agp_free_memory(DRM_AGP_MEM * handle);
extern int drm_agp_bind_memory(DRM_AGP_MEM * handle, off_t start);
extern int drm_agp_unbind_memory(DRM_AGP_MEM * handle);
@@ -40615,7 +40661,7 @@
extern int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent,
struct drm_driver *driver);
extern int drm_put_dev(struct drm_device *dev);
-@@ -1223,6 +1330,8 @@ extern int drm_ati_pcigart_init(struct drm_device *dev,
+@@ -1224,6 +1331,8 @@ extern int drm_ati_pcigart_init(struct drm_device *dev,
struct drm_ati_pcigart_info * gart_info);
extern int drm_ati_pcigart_cleanup(struct drm_device *dev,
struct drm_ati_pcigart_info * gart_info);
@@ -40624,7 +40670,7 @@
extern drm_dma_handle_t *drm_pci_alloc(struct drm_device *dev, size_t size,
size_t align, dma_addr_t maxaddr);
-@@ -1234,7 +1343,11 @@ struct drm_sysfs_class;
+@@ -1235,7 +1344,11 @@ struct drm_sysfs_class;
extern struct class *drm_sysfs_create(struct module *owner, char *name);
extern void drm_sysfs_destroy(void);
extern int drm_sysfs_device_add(struct drm_minor *minor);
@@ -40636,7 +40682,7 @@
/*
* Basic memory manager support (drm_mm.c)
-@@ -1372,6 +1485,39 @@ extern void drm_free(void *pt, size_t size, int area);
+@@ -1373,6 +1486,39 @@ extern void drm_free(void *pt, size_t size, int area);
extern void *drm_calloc(size_t nmemb, size_t size, int area);
#endif
drm-next.patch:
Index: drm-next.patch
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/devel/drm-next.patch,v
retrieving revision 1.1
retrieving revision 1.2
diff -u -r1.1 -r1.2
--- drm-next.patch 10 Oct 2008 04:30:38 -0000 1.1
+++ drm-next.patch 21 Oct 2008 04:43:00 -0000 1.2
@@ -1,3 +1,236 @@
+commit fee392c8fe3e4ad1ddf1c8a373921c672dea9029
+Author: Linus Torvalds <torvalds at linux-foundation.org>
+Date: Fri Oct 17 15:43:02 2008 -0700
+
+ i915: Fix format string warnings on x86-64.
+
+ Signed-off-by: Eric Anholt <eric at anholt.net>
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit 6a4902ee6f3a751595099cd75a8006230bbf5cb9
+Author: Eric Anholt <eric at anholt.net>
+Date: Fri Oct 17 14:41:03 2008 -0700
+
+ i915: Don't dereference HWS in /proc debug files when it isn't initialized.
+
+ Signed-off-by: Eric Anholt <eric at anholt.net>
+ Acked-by: Keith Packard <keithp at keithp.com>
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit de5ef8c7a73ba68c72f8249dc3d592223c8290bd
+Author: Eric Anholt <eric at anholt.net>
+Date: Fri Oct 17 15:41:26 2008 -0700
+
+ i915: Enable IMR passthrough of vblank events before enabling it in pipestat.
+
+ Otherwise, if we lost the race, the pipestat bit would be set without being
+ reflected in IIR, and we would never clear the pipestat bit so the pipe
+ event would never be generated again, and all vblank waits would time out.
+
+ Signed-off-by: Eric Anholt <eric at anholt.net>
+ Acked-by: Keith Packard <keithp at keithp.com>
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit e69431aa8ec6d2cc516d4a4754a705b2e0ffb6c7
+Author: Eric Anholt <eric at anholt.net>
+Date: Fri Oct 17 11:03:53 2008 -0700
+
+ drm: Remove two leaks of vblank reference count in error paths.
+
+ If the failing paths were hit, the vblank IRQ would never get turned off
+ again.
+
+ Signed-off-by: Eric Anholt <eric at anholt.net>
+ Acked-by: Keith Packard <keithp at keithp.com>
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit 7e48965bf92b416dc9299b460b52a32e3a68a457
+Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
+Date: Fri Oct 17 15:48:44 2008 +0800
+
+ drm: fix leak of cliprects in drm_rmdraw()
+
+ Signed-off-by: Zhenyu Wang <zhenyu.z.wang at intel.com>
+ Signed-off-by: Eric Anholt <eric at anholt.net>
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit 2a9120b23eaefb6ab3d6ad6a257e5e19e5c60cbb
+Author: Keith Packard <keithp at keithp.com>
+Date: Fri Oct 17 00:44:42 2008 -0700
+
+ i915: Disable MSI on GM965 (errata says it doesn't work)
+
+ Current Intel errata for the GM965 says that using MSI may cause interrupts
+ to be delayed or lost. The only workaround offered is to not use it.
+
+ Signed-off-by: Keith Packard <keithp at keithp.com>
+ Signed-off-by: Eric Anholt <eric at anholt.net>
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit c42fd2999322cdeabb9df23fea751cff63fe6f49
+Author: Zhenyu Wang <zhenyu.z.wang at intel.com>
+Date: Fri Oct 17 13:15:48 2008 +0800
+
+ drm: Set cliprects to NULL when changing drawable to having 0 cliprects.
+
+ This avoids setting the cliprects pointer to a zero-sized allocation.
+
+ Signed-off-by: Zhenyu Wang <zhenyu.z.wang at intel.com>
+ Signed-off-by: Eric Anholt <eric at anholt.net>
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit 1af059625ac4c053c86b5f05a6e791f5c54cece1
+Author: Keith Packard <keithp at keithp.com>
+Date: Thu Oct 16 11:31:38 2008 -0700
+
+ i915: Protect vblank IRQ reg access with spinlock
+
+ This uses the same spinlock as the user_irq code as it shares the same
+ register, ensuring that interrupt registers are updated atomically.
+
+ Signed-off-by: Keith Packard <keithp at keithp.com>
+ Signed-off-by: Eric Anholt <eric at anholt.net>
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit ab9fd3dc431444995e7a98aab44d0469118b1f9e
+Author: Matthias Hopf <mhopf at suse.de>
+Date: Sat Oct 18 07:18:05 2008 +1000
+
+ drm/i915: fix ioremap of a user address for non-root (CVE-2008-3831)
+
+ Olaf Kirch noticed that the i915_set_status_page() function of the i915
+ kernel driver calls ioremap with an address offset that is supplied by
+ userspace via ioctl. The function zeroes the mapped memory via memset
+ and tells the hardware about the address. Turns out that access to that
+ ioctl is not restricted to root so users could probably exploit that to
+ do nasty things. We haven't tried to write actual exploit code though.
+
+ It only affects the Intel G33 series and newer.
+
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit 9d512dc0c924f3c75e8d8446c32b4ef77fe15913
+Author: Dave Airlie <airlied at redhat.com>
+Date: Fri Oct 17 09:29:14 2008 +1000
+
+ drm: make CONFIG_DRM depend on CONFIG_SHMEM.
+
+ This can be removed later when DRM doesn't depend on shmem.
+
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit e0a92262bdaa9b248a676723cad403285fe35783
+Author: Alex Deucher <alexdeucher at gmail.com>
+Date: Fri Oct 17 09:21:45 2008 +1000
+
+ radeon: fix PCI bus mastering support enables.
+
+ Someone noticed these registers moved around for later chips,
+ so we redo the codepaths per-chip. PCIE chips don't appear to
+ require explicit enables.
+
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit fb2fadbfea214c1d7395beef136761bd22c2d5fb
+Author: Alex Deucher <alexdeucher at gmail.com>
+Date: Fri Oct 17 09:19:33 2008 +1000
+
+ radeon: add RS400 family support.
+
+ This adds support for the RS400 family of IGPs for Intel CPUs.
+
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit 7ade062d9cb62fdaee02fbb88c8a0911659f6e52
+Author: Alex Deucher <alexdeucher at gmail.com>
+Date: Thu Oct 16 17:12:02 2008 +1000
+
+ drm/radeon: add support for RS740 IGP chipsets.
+
+ This adds support for the HS2100 IGP chipset.
+
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit b379ef538c692692a6dd2c60d27e738b06a162b3
+Author: Eric Anholt <eric at anholt.net>
+Date: Wed Oct 15 00:05:58 2008 -0700
+
+ i915: GM45 has GM965-style MCH setup.
+
+ Fixes tiling swizzling mode failures that manifest in glReadPixels().
+
+ Signed-off-by: Eric Anholt <eric at anholt.net>
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit e998d8c1d1773ef074149aff27791139709724c7
+Author: Keith Packard <keithp at keithp.com>
+Date: Tue Oct 14 21:41:13 2008 -0700
+
+ i915: Don't run retire work handler while suspended
+
+ At leavevt and lastclose time, cancel any pending retire work handler
+ invocation, and keep the retire work handler from requeuing itself if it is
+ currently running.
+
+ This patch restructures i915_gem_idle to perform all of these tasks instead
+ of having both leavevt and lastclose call a sequence of functions.
+
+ Signed-off-by: Keith Packard <keithp at keithp.com>
+ Signed-off-by: Eric Anholt <eric at anholt.net>
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit b23f10462fad09bb8c9aa27e0f6ef58df295623b
+Author: Keith Packard <keithp at keithp.com>
+Date: Tue Oct 14 19:55:10 2008 -0700
+
+ i915: Map status page cached for chips with GTT-based HWS location.
+
+ This should improve performance by avoiding uncached reads by the CPU (the
+ point of having a status page), and may improve stability. This patch only
+ affects G33, GM45 and G45 chips as those are the only ones using GTT-based
+ HWS mappings.
+
+ Signed-off-by: Keith Packard <keithp at keithp.com>
+ Signed-off-by: Eric Anholt <eric at anholt.net>
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit 56c994020d1aa2fbcd3457c1f369b18fe14167af
+Author: Keith Packard <keithp at keithp.com>
+Date: Tue Oct 14 17:20:35 2008 -0700
+
+ i915: Fix up ring initialization to cover G45 oddities
+
+ G45 appears quite sensitive to ring initialization register writes,
+ sometimes leaving the HEAD register with the START register contents. Check
+ to make sure HEAD is reset correctly when START is written, and fix it up,
+ screaming loudly.
+
+ Signed-off-by: Keith Packard <keithp at keithp.com>
+ Signed-off-by: Eric Anholt <eric at anholt.net>
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit fc57b4cf6a0f46f2f99065b627a574e788f844c7
+Author: Keith Packard <keithp at keithp.com>
+Date: Tue Oct 14 17:19:38 2008 -0700
+
+ i915: Use non-reserved status page index for breadcrumb
+
+ Dwords 0 through 0x1f are reserved for use by the hardware. Move the GEM
+ breadcrumb from 0x10 to 0x20 to keep out of this area.
+
+ Signed-off-by: Keith Packard <keithp at keithp.com>
+ Signed-off-by: Eric Anholt <eric at anholt.net>
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit cded96bf710f0df960adb64e34f347b955b0b373
+Author: Eric Anholt <eric at anholt.net>
+Date: Mon Oct 6 15:14:12 2008 -0700
+
+ drm: Increment dev_priv->irq_received so i915_gem_interrupts count works.
+
+ Signed-off-by: Eric Anholt <eric at anholt.net>
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
commit 5fed53a040bb697c952f765884f2afb3d89122b7
Author: Jesse Barnes <jbarnes at virtuousgeek.org>
Date: Mon Sep 15 15:00:33 2008 -0700
@@ -424,9 +657,18 @@
struct page *kmap_atomic_to_page(void *ptr)
{
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
-index 610d6fd..bf9003e 100644
+index 610d6fd..9097500 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
+@@ -6,7 +6,7 @@
+ #
+ menuconfig DRM
+ tristate "Direct Rendering Manager (XFree86 4.1.0 and higher DRI support)"
+- depends on (AGP || AGP=n) && PCI && !EMULATED_CMPXCHG
++ depends on (AGP || AGP=n) && PCI && !EMULATED_CMPXCHG && SHMEM
+ help
+ Kernel-level support for the Direct Rendering Infrastructure (DRI)
+ introduced in XFree86 4.0. If you say Y here, you need to select
@@ -87,6 +87,7 @@ config DRM_MGA
config DRM_SIS
tristate "SiS video cards"
@@ -452,7 +694,7 @@
drm_agpsupport.o drm_scatter.o ati_pcigart.o drm_pci.o \
drm_sysfs.o drm_hashtab.o drm_sman.o drm_mm.o
diff --git a/drivers/gpu/drm/drm_agpsupport.c b/drivers/gpu/drm/drm_agpsupport.c
-index aefa5ac..2639be2 100644
+index aefa5ac..3d33b82 100644
--- a/drivers/gpu/drm/drm_agpsupport.c
+++ b/drivers/gpu/drm/drm_agpsupport.c
@@ -33,6 +33,7 @@
@@ -463,7 +705,7 @@
#if __OS_HAS_AGP
-@@ -452,4 +453,52 @@ int drm_agp_unbind_memory(DRM_AGP_MEM * handle)
+@@ -452,4 +453,53 @@ int drm_agp_unbind_memory(DRM_AGP_MEM * handle)
return agp_unbind_memory(handle);
}
@@ -479,7 +721,8 @@
+drm_agp_bind_pages(struct drm_device *dev,
+ struct page **pages,
+ unsigned long num_pages,
-+ uint32_t gtt_offset)
++ uint32_t gtt_offset,
++ u32 type)
+{
+ DRM_AGP_MEM *mem;
+ int ret, i;
@@ -487,7 +730,7 @@
+ DRM_DEBUG("\n");
+
+ mem = drm_agp_allocate_memory(dev->agp->bridge, num_pages,
-+ AGP_USER_MEMORY);
++ type);
+ if (mem == NULL) {
+ DRM_ERROR("Failed to allocate memory for %ld pages\n",
+ num_pages);
@@ -592,6 +835,38 @@
+#endif
+}
+EXPORT_SYMBOL(drm_clflush_pages);
+diff --git a/drivers/gpu/drm/drm_drawable.c b/drivers/gpu/drm/drm_drawable.c
+index 1839c57..4a794d8 100644
+--- a/drivers/gpu/drm/drm_drawable.c
++++ b/drivers/gpu/drm/drm_drawable.c
+@@ -76,11 +76,14 @@ int drm_rmdraw(struct drm_device *dev, void *data, struct drm_file *file_priv)
+ {
+ struct drm_draw *draw = data;
+ unsigned long irqflags;
++ struct drm_drawable_info *info;
+
+ spin_lock_irqsave(&dev->drw_lock, irqflags);
+
+- drm_free(drm_get_drawable_info(dev, draw->handle),
+- sizeof(struct drm_drawable_info), DRM_MEM_BUFS);
++ info = drm_get_drawable_info(dev, draw->handle);
++ drm_free(info->rects, info->num_rects * sizeof(struct drm_clip_rect),
++ DRM_MEM_BUFS);
++ drm_free(info, sizeof(struct drm_drawable_info), DRM_MEM_BUFS);
+
+ idr_remove(&dev->drw_idr, draw->handle);
+
+@@ -111,7 +114,9 @@ int drm_update_drawable_info(struct drm_device *dev, void *data, struct drm_file
+
+ switch (update->type) {
+ case DRM_DRAWABLE_CLIPRECTS:
+- if (update->num != info->num_rects) {
++ if (update->num == 0)
++ rects = NULL;
++ else if (update->num != info->num_rects) {
+ rects = drm_alloc(update->num * sizeof(struct drm_clip_rect),
+ DRM_MEM_BUFS);
+ } else
diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
index 452c2d8..96f416a 100644
--- a/drivers/gpu/drm/drm_drv.c
@@ -1071,7 +1346,7 @@
+EXPORT_SYMBOL(drm_gem_object_handle_free);
+
diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c
-index 53f0e5a..4091b9e 100644
+index 53f0e5a..212a94f 100644
--- a/drivers/gpu/drm/drm_irq.c
+++ b/drivers/gpu/drm/drm_irq.c
@@ -63,7 +63,7 @@ int drm_irq_by_busid(struct drm_device *dev, void *data,
@@ -1543,7 +1818,7 @@
struct drm_vbl_sig *vbl_sig;
spin_lock_irqsave(&dev->vbl_lock, irqflags);
-@@ -298,22 +579,29 @@ int drm_wait_vblank(struct drm_device *dev, void *data, struct drm_file *file_pr
+@@ -298,22 +579,32 @@ int drm_wait_vblank(struct drm_device *dev, void *data, struct drm_file *file_pr
}
}
@@ -1570,11 +1845,14 @@
+ goto done;
+ }
+
++ /* Get a refcount on the vblank, which will be released by
++ * drm_vbl_send_signals().
++ */
+ ret = drm_vblank_get(dev, crtc);
+ if (ret) {
+ drm_free(vbl_sig, sizeof(struct drm_vbl_sig),
+ DRM_MEM_DRIVER);
-+ return ret;
++ goto done;
}
- memset((void *)vbl_sig, 0, sizeof(*vbl_sig));
@@ -1582,7 +1860,7 @@
vbl_sig->sequence = vblwait->request.sequence;
vbl_sig->info.si_signo = vblwait->request.signal;
-@@ -327,20 +615,29 @@ int drm_wait_vblank(struct drm_device *dev, void *data, struct drm_file *file_pr
+@@ -327,20 +618,29 @@ int drm_wait_vblank(struct drm_device *dev, void *data, struct drm_file *file_pr
vblwait->reply.sequence = seq;
} else {
@@ -1624,7 +1902,7 @@
return ret;
}
-@@ -348,44 +645,57 @@ int drm_wait_vblank(struct drm_device *dev, void *data, struct drm_file *file_pr
+@@ -348,44 +648,57 @@ int drm_wait_vblank(struct drm_device *dev, void *data, struct drm_file *file_pr
* Send the VBLANK signals.
*
* \param dev DRM device.
@@ -1760,7 +2038,7 @@
void drm_mm_takedown(struct drm_mm * mm)
{
diff --git a/drivers/gpu/drm/drm_proc.c b/drivers/gpu/drm/drm_proc.c
-index 93b1e04..d490db4 100644
+index 93b1e04..ae73b7f 100644
--- a/drivers/gpu/drm/drm_proc.c
+++ b/drivers/gpu/drm/drm_proc.c
@@ -49,6 +49,10 @@ static int drm_queues_info(char *buf, char **start, off_t offset,
@@ -1889,12 +2167,12 @@
+ struct drm_gem_object *obj = ptr;
+ struct drm_gem_name_info_data *nid = data;
+
-+ DRM_INFO("name %d size %d\n", obj->name, obj->size);
++ DRM_INFO("name %d size %zd\n", obj->name, obj->size);
+ if (nid->eof)
+ return 0;
+
+ nid->len += sprintf(&nid->buf[nid->len],
-+ "%6d%9d%8d%9d\n",
++ "%6d %8zd %7d %8d\n",
+ obj->name, obj->size,
+ atomic_read(&obj->handlecount.refcount),
+ atomic_read(&obj->refcount.refcount));
@@ -2027,7 +2305,7 @@
i915-$(CONFIG_COMPAT) += i915_ioc32.o
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
-index 8897434..593286e 100644
+index 8897434..957c77f 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -40,40 +40,96 @@ int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
@@ -2487,7 +2765,7 @@
dev_priv->status_gfx_addr);
DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
return 0;
-@@ -776,14 +821,38 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
+@@ -776,14 +821,41 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
memset(dev_priv, 0, sizeof(drm_i915_private_t));
dev->dev_private = (void *)dev_priv;
@@ -2517,8 +2795,11 @@
+ * correctly in testing on 945G.
+ * This may be a side effect of MSI having been made available for PEG
+ * and the registers being closely associated.
++ *
++ * According to chipset errata, on the 965GM, MSI interrupts may
++ * be lost or delayed
+ */
-+ if (!IS_I945G(dev) && !IS_I945GM(dev))
++ if (!IS_I945G(dev) && !IS_I945GM(dev) && !IS_I965GM(dev))
+ if (pci_enable_msi(dev->pdev))
+ DRM_ERROR("failed to enable MSI\n");
+
@@ -2529,7 +2810,7 @@
return ret;
}
-@@ -791,8 +860,15 @@ int i915_driver_unload(struct drm_device *dev)
+@@ -791,8 +863,15 @@ int i915_driver_unload(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2547,7 +2828,7 @@
drm_free(dev->dev_private, sizeof(drm_i915_private_t),
DRM_MEM_DRIVER);
-@@ -800,6 +876,25 @@ int i915_driver_unload(struct drm_device *dev)
+@@ -800,6 +879,25 @@ int i915_driver_unload(struct drm_device *dev)
return 0;
}
@@ -2573,7 +2854,7 @@
void i915_driver_lastclose(struct drm_device * dev)
{
drm_i915_private_t *dev_priv = dev->dev_private;
-@@ -807,6 +902,8 @@ void i915_driver_lastclose(struct drm_device * dev)
+@@ -807,6 +905,8 @@ void i915_driver_lastclose(struct drm_device * dev)
if (!dev_priv)
return;
@@ -2582,7 +2863,7 @@
if (dev_priv->agp_heap)
i915_mem_takedown(&(dev_priv->agp_heap));
-@@ -819,6 +916,13 @@ void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
+@@ -819,6 +919,13 @@ void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
i915_mem_release(dev, file_priv, dev_priv->agp_heap);
}
@@ -2596,10 +2877,12 @@
struct drm_ioctl_desc i915_ioctls[] = {
DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
-@@ -837,6 +941,22 @@ struct drm_ioctl_desc i915_ioctls[] = {
+@@ -836,7 +943,23 @@ struct drm_ioctl_desc i915_ioctls[] = {
+ DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ),
DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
- DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH),
+- DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH),
++ DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+ DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
+ DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
+ DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
@@ -3154,7 +3437,7 @@
.fops = {
.owner = THIS_MODULE,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
-index d7326d9..7401123 100644
+index d7326d9..eae4ed3 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -30,6 +30,8 @@
@@ -3325,7 +3608,7 @@
u32 saveMI_ARB_STATE;
u32 saveSWF0[16];
u32 saveSWF1[16];
-@@ -203,8 +239,177 @@ typedef struct drm_i915_private {
+@@ -203,8 +239,180 @@ typedef struct drm_i915_private {
u8 saveDACMASK;
u8 saveDACDATA[256*3]; /* 256 3-byte colors */
u8 saveCR[37];
@@ -3463,6 +3746,9 @@
+ /** Current tiling mode for the object. */
+ uint32_t tiling_mode;
+
++ /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
++ uint32_t agp_type;
++
+ /**
+ * Flagging of which individual pages are valid in GEM_DOMAIN_CPU when
+ * GEM_DOMAIN_CPU is not in the object's read domain.
@@ -3503,7 +3789,7 @@
extern struct drm_ioctl_desc i915_ioctls[];
extern int i915_max_ioctl;
-@@ -212,31 +417,42 @@ extern int i915_max_ioctl;
+@@ -212,31 +420,42 @@ extern int i915_max_ioctl;
extern void i915_kernel_lost_context(struct drm_device * dev);
extern int i915_driver_load(struct drm_device *, unsigned long flags);
extern int i915_driver_unload(struct drm_device *);
@@ -3549,7 +3835,7 @@
/* i915_mem.c */
extern int i915_mem_alloc(struct drm_device *dev, void *data,
-@@ -250,11 +466,99 @@ extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
+@@ -250,11 +469,99 @@ extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
extern void i915_mem_takedown(struct mem_block **heap);
extern void i915_mem_release(struct drm_device * dev,
struct drm_file *file_priv, struct mem_block *heap);
@@ -3653,7 +3939,7 @@
#define I915_VERBOSE 0
-@@ -284,816 +588,27 @@ extern void i915_mem_release(struct drm_device * dev,
+@@ -284,816 +591,29 @@ extern void i915_mem_release(struct drm_device * dev,
if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \
dev_priv->ring.tail = outring; \
dev_priv->ring.space -= outcount * 4; \
@@ -4156,12 +4442,9 @@
-# define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
-# define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
-
- /**
+-/**
- * SDVO multiplier for 945G/GM. Not used on 965.
-+ * Reads a dword out of the status page, which is written to from the command
-+ * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
-+ * MI_STORE_DATA_IMM.
- *
+- *
- * \sa DPLL_MD_UDI_MULTIPLIER_MASK
- */
-# define SDVO_MULTIPLIER_MASK 0x000000ff
@@ -4177,15 +4460,9 @@
-#define DPLL_B_MD 0x06020
-/**
- * UDI pixel divider, controlling how many pixels are stuffed into a packet.
-+ * The following dwords have a reserved meaning:
-+ * 0: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
-+ * 4: ring 0 head pointer
-+ * 5: ring 1 head pointer (915-class)
-+ * 6: ring 2 head pointer (915-class)
- *
+- *
- * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
-+ * The area from dword 0x10 to 0x3ff is available for driver usage.
- */
+- */
-# define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
-# define DPLL_MD_UDI_DIVIDER_SHIFT 24
-/** UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
@@ -4282,9 +4559,12 @@
-#define SDVO_PIPE_B_SELECT (1 << 30)
-#define SDVO_STALL_SELECT (1 << 29)
-#define SDVO_INTERRUPT_ENABLE (1 << 26)
--/**
+ /**
- * 915G/GM SDVO pixel multiplier.
-- *
++ * Reads a dword out of the status page, which is written to from the command
++ * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
++ * MI_STORE_DATA_IMM.
+ *
- * Programmed value is multiplier - 1, up to 5x.
- *
- * \sa DPLL_MD_UDI_MULTIPLIER_MASK
@@ -4308,7 +4588,14 @@
-/**
- * This register controls the LVDS output enable, pipe selection, and data
- * format selection.
-- *
++ * The following dwords have a reserved meaning:
++ * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
++ * 0x04: ring 0 head pointer
++ * 0x05: ring 1 head pointer (915-class)
++ * 0x06: ring 2 head pointer (915-class)
++ * 0x10-0x1b: Context status DWords (GM45)
++ * 0x1f: Last written status offset. (GM45)
+ *
- * All of the clock/data pairs are force powered down by power sequencing.
- */
-#define LVDS 0x61180
@@ -4460,14 +4747,15 @@
-/*
- * Overlay registers. These are overlay registers accessed via MMIO.
- * Those loaded via the overlay register page are defined in i830_video.c.
-- */
++ * The area from dword 0x20 to 0x3ff is available for driver usage.
+ */
-#define OVADD 0x30000
-
-#define DOVSTA 0x30008
-#define OC_BUF (0x3<<20)
+#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
+#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, 5)
-+#define I915_GEM_HWS_INDEX 0x10
++#define I915_GEM_HWS_INDEX 0x20
-#define OGAMC5 0x30010
-#define OGAMC4 0x30014
@@ -4484,7 +4772,7 @@
#define IS_I830(dev) ((dev)->pci_device == 0x3577)
#define IS_845G(dev) ((dev)->pci_device == 0x2562)
-@@ -1119,7 +634,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
+@@ -1119,7 +639,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
@@ -4493,7 +4781,7 @@
#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
(dev)->pci_device == 0x2E12 || \
-@@ -1133,9 +648,9 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
+@@ -1133,9 +653,9 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev))
#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
@@ -4507,10 +4795,10 @@
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
new file mode 100644
-index 0000000..a31ee32
+index 0000000..9ac73dd
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_gem.c
-@@ -0,0 +1,2517 @@
+@@ -0,0 +1,2558 @@
+/*
+ * Copyright © 2008 Intel Corporation
+ *
@@ -4563,6 +4851,9 @@
+static void i915_gem_object_free_page_list(struct drm_gem_object *obj);
+static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
+
++static void
++i915_gem_cleanup_ringbuffer(struct drm_device *dev);
++
+int
+i915_gem_init_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file_priv)
@@ -5095,7 +5386,7 @@
+ was_empty = list_empty(&dev_priv->mm.request_list);
+ list_add_tail(&request->list, &dev_priv->mm.request_list);
+
-+ if (was_empty)
++ if (was_empty && !dev_priv->mm.suspended)
+ schedule_delayed_work(&dev_priv->mm.retire_work, HZ);
+ return seqno;
+}
@@ -5244,7 +5535,8 @@
+
+ mutex_lock(&dev->struct_mutex);
+ i915_gem_retire_requests(dev);
-+ if (!list_empty(&dev_priv->mm.request_list))
++ if (!dev_priv->mm.suspended &&
++ !list_empty(&dev_priv->mm.request_list))
+ schedule_delayed_work(&dev_priv->mm.retire_work, HZ);
+ mutex_unlock(&dev->struct_mutex);
+}
@@ -5672,7 +5964,8 @@
+ obj_priv->agp_mem = drm_agp_bind_pages(dev,
+ obj_priv->page_list,
+ page_count,
-+ obj_priv->gtt_offset);
++ obj_priv->gtt_offset,
++ obj_priv->agp_type);
+ if (obj_priv->agp_mem == NULL) {
+ i915_gem_object_free_page_list(obj);
+ drm_mm_put_block(obj_priv->gtt_space);
@@ -6655,6 +6948,8 @@
+ obj->write_domain = I915_GEM_DOMAIN_CPU;
+ obj->read_domains = I915_GEM_DOMAIN_CPU;
+
++ obj_priv->agp_type = AGP_USER_MEMORY;
++
+ obj->driver_private = obj_priv;
+ obj_priv->obj = obj;
+ INIT_LIST_HEAD(&obj_priv->list);
@@ -6737,14 +7032,24 @@
+ uint32_t seqno, cur_seqno, last_seqno;
+ int stuck, ret;
+
-+ if (dev_priv->mm.suspended)
++ mutex_lock(&dev->struct_mutex);
++
++ if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
++ mutex_unlock(&dev->struct_mutex);
+ return 0;
++ }
+
+ /* Hack! Don't let anybody do execbuf while we don't control the chip.
+ * We need to replace this with a semaphore, or something.
+ */
+ dev_priv->mm.suspended = 1;
+
++ /* Cancel the retire work handler, wait for it to finish if running
++ */
++ mutex_unlock(&dev->struct_mutex);
++ cancel_delayed_work_sync(&dev_priv->mm.retire_work);
++ mutex_lock(&dev->struct_mutex);
++
+ i915_kernel_lost_context(dev);
+
+ /* Flush the GPU along with all non-CPU write domains
@@ -6794,13 +7099,19 @@
+
+ /* Move all buffers out of the GTT. */
+ ret = i915_gem_evict_from_list(dev, &dev_priv->mm.inactive_list);
-+ if (ret)
++ if (ret) {
++ mutex_unlock(&dev->struct_mutex);
+ return ret;
++ }
+
+ BUG_ON(!list_empty(&dev_priv->mm.active_list));
+ BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
+ BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
+ BUG_ON(!list_empty(&dev_priv->mm.request_list));
++
++ i915_gem_cleanup_ringbuffer(dev);
++ mutex_unlock(&dev->struct_mutex);
++
+ return 0;
+}
+
@@ -6824,6 +7135,7 @@
+ return -ENOMEM;
+ }
+ obj_priv = obj->driver_private;
++ obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
+
+ ret = i915_gem_object_pin(obj, 4096);
+ if (ret != 0) {
@@ -6832,25 +7144,18 @@
+ }
+
+ dev_priv->status_gfx_addr = obj_priv->gtt_offset;
-+ dev_priv->hws_map.offset = dev->agp->base + obj_priv->gtt_offset;
-+ dev_priv->hws_map.size = 4096;
-+ dev_priv->hws_map.type = 0;
-+ dev_priv->hws_map.flags = 0;
-+ dev_priv->hws_map.mtrr = 0;
+
-+ /* Ioremapping here is the wrong thing to do. We want cached access.
-+ */
-+ drm_core_ioremap_wc(&dev_priv->hws_map, dev);
-+ if (dev_priv->hws_map.handle == NULL) {
++ dev_priv->hw_status_page = kmap(obj_priv->page_list[0]);
++ if (dev_priv->hw_status_page == NULL) {
+ DRM_ERROR("Failed to map status page.\n");
+ memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
+ drm_gem_object_unreference(obj);
+ return -EINVAL;
+ }
+ dev_priv->hws_obj = obj;
-+ dev_priv->hw_status_page = dev_priv->hws_map.handle;
+ memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
+ I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
++ I915_READ(HWS_PGA); /* posting read */
+ DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
+
+ return 0;
@@ -6863,6 +7168,7 @@
+ struct drm_gem_object *obj;
+ struct drm_i915_gem_object *obj_priv;
+ int ret;
++ u32 head;
+
+ ret = i915_gem_init_hws(dev);
+ if (ret != 0)
@@ -6903,17 +7209,49 @@
+
+ /* Stop the ring if it's running. */
+ I915_WRITE(PRB0_CTL, 0);
-+ I915_WRITE(PRB0_HEAD, 0);
+ I915_WRITE(PRB0_TAIL, 0);
-+ I915_WRITE(PRB0_START, 0);
++ I915_WRITE(PRB0_HEAD, 0);
+
+ /* Initialize the ring. */
+ I915_WRITE(PRB0_START, obj_priv->gtt_offset);
++ head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
++
++ /* G45 ring initialization fails to reset head to zero */
++ if (head != 0) {
++ DRM_ERROR("Ring head not reset to zero "
++ "ctl %08x head %08x tail %08x start %08x\n",
++ I915_READ(PRB0_CTL),
++ I915_READ(PRB0_HEAD),
++ I915_READ(PRB0_TAIL),
++ I915_READ(PRB0_START));
++ I915_WRITE(PRB0_HEAD, 0);
++
++ DRM_ERROR("Ring head forced to zero "
++ "ctl %08x head %08x tail %08x start %08x\n",
++ I915_READ(PRB0_CTL),
++ I915_READ(PRB0_HEAD),
++ I915_READ(PRB0_TAIL),
++ I915_READ(PRB0_START));
++ }
++
+ I915_WRITE(PRB0_CTL,
+ ((obj->size - 4096) & RING_NR_PAGES) |
+ RING_NO_REPORT |
+ RING_VALID);
+
++ head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
++
++ /* If the head is still not zero, the ring is dead */
++ if (head != 0) {
++ DRM_ERROR("Ring initialization failed "
++ "ctl %08x head %08x tail %08x start %08x\n",
++ I915_READ(PRB0_CTL),
++ I915_READ(PRB0_HEAD),
++ I915_READ(PRB0_TAIL),
++ I915_READ(PRB0_START));
++ return -EIO;
++ }
++
+ /* Update our cache of the ring state */
+ i915_kernel_lost_context(dev);
+
@@ -6936,10 +7274,15 @@
+ memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
+
+ if (dev_priv->hws_obj != NULL) {
-+ i915_gem_object_unpin(dev_priv->hws_obj);
-+ drm_gem_object_unreference(dev_priv->hws_obj);
++ struct drm_gem_object *obj = dev_priv->hws_obj;
++ struct drm_i915_gem_object *obj_priv = obj->driver_private;
++
++ kunmap(obj_priv->page_list[0]);
++ i915_gem_object_unpin(obj);
++ drm_gem_object_unreference(obj);
+ dev_priv->hws_obj = NULL;
+ memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
++ dev_priv->hw_status_page = NULL;
+
+ /* Write high address into HWS_PGA when disabling. */
+ I915_WRITE(HWS_PGA, 0x1ffff000);
@@ -6981,34 +7324,20 @@
+{
+ int ret;
+
-+ mutex_lock(&dev->struct_mutex);
+ ret = i915_gem_idle(dev);
-+ if (ret == 0)
-+ i915_gem_cleanup_ringbuffer(dev);
-+ mutex_unlock(&dev->struct_mutex);
-+
+ drm_irq_uninstall(dev);
+
-+ return 0;
++ return ret;
+}
+
+void
+i915_gem_lastclose(struct drm_device *dev)
+{
+ int ret;
-+ drm_i915_private_t *dev_priv = dev->dev_private;
+
-+ mutex_lock(&dev->struct_mutex);
-+
-+ if (dev_priv->ring.ring_obj != NULL) {
-+ ret = i915_gem_idle(dev);
-+ if (ret)
-+ DRM_ERROR("failed to idle hardware: %d\n", ret);
-+
-+ i915_gem_cleanup_ringbuffer(dev);
-+ }
-+
-+ mutex_unlock(&dev->struct_mutex);
++ ret = i915_gem_idle(dev);
++ if (ret)
++ DRM_ERROR("failed to idle hardware: %d\n", ret);
+}
+
+void
@@ -7237,10 +7566,10 @@
+#endif
diff --git a/drivers/gpu/drm/i915/i915_gem_proc.c b/drivers/gpu/drm/i915/i915_gem_proc.c
new file mode 100644
-index 0000000..15d4160
+index 0000000..93de15b
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_gem_proc.c
-@@ -0,0 +1,292 @@
+@@ -0,0 +1,301 @@
+/*
+ * Copyright © 2008 Intel Corporation
+ *
@@ -7435,7 +7764,12 @@
+
+ *start = &buf[offset];
+ *eof = 0;
-+ DRM_PROC_PRINT("Current sequence: %d\n", i915_get_gem_seqno(dev));
++ if (dev_priv->hw_status_page != NULL) {
++ DRM_PROC_PRINT("Current sequence: %d\n",
++ i915_get_gem_seqno(dev));
++ } else {
++ DRM_PROC_PRINT("Current sequence: hws uninitialized\n");
++ }
+ DRM_PROC_PRINT("Waiter sequence: %d\n",
+ dev_priv->mm.waiting_gem_seqno);
+ DRM_PROC_PRINT("IRQ sequence: %d\n", dev_priv->mm.irq_gem_seqno);
@@ -7473,8 +7807,12 @@
+ I915_READ(PIPEBSTAT));
+ DRM_PROC_PRINT("Interrupts received: %d\n",
+ atomic_read(&dev_priv->irq_received));
-+ DRM_PROC_PRINT("Current sequence: %d\n",
-+ i915_get_gem_seqno(dev));
++ if (dev_priv->hw_status_page != NULL) {
++ DRM_PROC_PRINT("Current sequence: %d\n",
++ i915_get_gem_seqno(dev));
++ } else {
++ DRM_PROC_PRINT("Current sequence: hws uninitialized\n");
++ }
+ DRM_PROC_PRINT("Waiter sequence: %d\n",
+ dev_priv->mm.waiting_gem_seqno);
+ DRM_PROC_PRINT("IRQ sequence: %d\n",
@@ -7535,10 +7873,10 @@
+}
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
new file mode 100644
-index 0000000..6b3f1e4
+index 0000000..e8b85ac
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
-@@ -0,0 +1,256 @@
+@@ -0,0 +1,257 @@
+/*
+ * Copyright © 2008 Intel Corporation
+ *
@@ -7637,7 +7975,8 @@
+ */
+ swizzle_x = I915_BIT_6_SWIZZLE_NONE;
+ swizzle_y = I915_BIT_6_SWIZZLE_NONE;
-+ } else if ((!IS_I965G(dev) && !IS_G33(dev)) || IS_I965GM(dev)) {
++ } else if ((!IS_I965G(dev) && !IS_G33(dev)) || IS_I965GM(dev) ||
++ IS_GM45(dev)) {
+ uint32_t dcc;
+
+ /* On 915-945 and GM965, channel interleave by the CPU is
@@ -7659,7 +7998,7 @@
+ dcc & DCC_CHANNEL_XOR_DISABLE) {
+ swizzle_x = I915_BIT_6_SWIZZLE_9_10;
+ swizzle_y = I915_BIT_6_SWIZZLE_9;
-+ } else if (IS_I965GM(dev)) {
++ } else if (IS_I965GM(dev) || IS_GM45(dev)) {
+ /* GM965 only does bit 11-based channel
+ * randomization
+ */
@@ -7796,7 +8135,7 @@
+ return 0;
+}
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
-index df03611..ef03a59 100644
+index df03611..ca55c40 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -31,12 +31,92 @@
@@ -7954,7 +8293,7 @@
for (num_rects = drw->num_rects; num_rects--; rect++) {
int y1 = max(rect->y1, top);
-@@ -229,61 +313,137 @@ static void i915_vblank_tasklet(struct drm_device *dev)
+@@ -229,61 +313,139 @@ static void i915_vblank_tasklet(struct drm_device *dev)
}
}
@@ -8020,11 +8359,14 @@
- pipea_stats = I915_READ(I915REG_PIPEASTAT);
- pipeb_stats = I915_READ(I915REG_PIPEBSTAT);
++ atomic_inc(&dev_priv->irq_received);
+
+- temp = I915_READ16(I915REG_INT_IDENTITY_R);
+ if (dev->pdev->msi_enabled)
+ I915_WRITE(IMR, ~0);
+ iir = I915_READ(IIR);
-- temp = I915_READ16(I915REG_INT_IDENTITY_R);
+- temp &= (USER_INT_FLAG | VSYNC_PIPEA_FLAG | VSYNC_PIPEB_FLAG);
+ if (iir == 0) {
+ if (dev->pdev->msi_enabled) {
+ I915_WRITE(IMR, dev_priv->irq_mask_reg);
@@ -8033,7 +8375,7 @@
+ return IRQ_NONE;
+ }
-- temp &= (USER_INT_FLAG | VSYNC_PIPEA_FLAG | VSYNC_PIPEB_FLAG);
+- DRM_DEBUG("%s flag=%08x\n", __FUNCTION__, temp);
+ /*
+ * Clear the PIPE(A|B)STAT regs before the IIR otherwise
+ * we may get extra interrupts.
@@ -8049,7 +8391,8 @@
+ drm_handle_vblank(dev, i915_get_plane(dev, 0));
+ }
-- DRM_DEBUG("%s flag=%08x\n", __FUNCTION__, temp);
+- if (temp == 0)
+- return IRQ_NONE;
+ I915_WRITE(PIPEASTAT, pipea_stats);
+ }
+ if (iir & I915_DISPLAY_PIPE_B_EVENT_INTERRUPT) {
@@ -8067,9 +8410,7 @@
+ vblank++;
+ drm_handle_vblank(dev, i915_get_plane(dev, 1));
+ }
-
-- if (temp == 0)
-- return IRQ_NONE;
++
+ if (pipeb_stats & I915_LEGACY_BLC_EVENT_STATUS)
+ opregion_asle_intr(dev);
+ I915_WRITE(PIPEBSTAT, pipeb_stats);
@@ -8093,6 +8434,9 @@
+ dev_priv->mm.irq_gem_seqno = i915_get_gem_seqno(dev);
DRM_WAKEUP(&dev_priv->irq_queue);
+ }
++
++ if (iir & I915_ASLE_INTERRUPT)
++ opregion_asle_intr(dev);
- if (temp & (VSYNC_PIPEA_FLAG | VSYNC_PIPEB_FLAG)) {
- int vblank_pipe = dev_priv->vblank_pipe;
@@ -8114,9 +8458,6 @@
- drm_vbl_send_signals(dev);
-
- if (dev_priv->swaps_pending > 0)
-+ if (iir & I915_ASLE_INTERRUPT)
-+ opregion_asle_intr(dev);
-+
+ if (vblank && dev_priv->swaps_pending > 0) {
+ if (dev_priv->ring.ring_obj == NULL)
drm_locked_tasklet(dev, i915_vblank_tasklet);
@@ -8131,7 +8472,7 @@
}
return IRQ_HANDLED;
-@@ -298,23 +458,45 @@ static int i915_emit_irq(struct drm_device * dev)
+@@ -298,23 +460,47 @@ static int i915_emit_irq(struct drm_device * dev)
DRM_DEBUG("\n");
@@ -8162,28 +8503,30 @@
+void i915_user_irq_get(struct drm_device *dev)
+{
+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
++ unsigned long irqflags;
+
-+ spin_lock(&dev_priv->user_irq_lock);
++ spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
+ if (dev->irq_enabled && (++dev_priv->user_irq_refcount == 1))
+ i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
-+ spin_unlock(&dev_priv->user_irq_lock);
++ spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
+}
+
+void i915_user_irq_put(struct drm_device *dev)
+{
+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
++ unsigned long irqflags;
+
-+ spin_lock(&dev_priv->user_irq_lock);
++ spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
+ BUG_ON(dev->irq_enabled && dev_priv->user_irq_refcount <= 0);
+ if (dev->irq_enabled && (--dev_priv->user_irq_refcount == 0))
+ i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
-+ spin_unlock(&dev_priv->user_irq_lock);
++ spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
+}
+
static int i915_wait_irq(struct drm_device * dev, int irq_nr)
{
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
-@@ -323,55 +505,34 @@ static int i915_wait_irq(struct drm_device * dev, int irq_nr)
+@@ -323,55 +509,34 @@ static int i915_wait_irq(struct drm_device * dev, int irq_nr)
DRM_DEBUG("irq_nr=%d breadcrumb=%d\n", irq_nr,
READ_BREADCRUMB(dev_priv));
@@ -8252,7 +8595,7 @@
/* Needs the lock as it touches the ring.
*/
int i915_irq_emit(struct drm_device *dev, void *data,
-@@ -381,14 +542,15 @@ int i915_irq_emit(struct drm_device *dev, void *data,
+@@ -381,14 +546,15 @@ int i915_irq_emit(struct drm_device *dev, void *data,
drm_i915_irq_emit_t *emit = data;
int result;
@@ -8270,7 +8613,7 @@
if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
DRM_ERROR("copy_to_user\n");
-@@ -414,18 +576,74 @@ int i915_irq_wait(struct drm_device *dev, void *data,
+@@ -414,18 +580,91 @@ int i915_irq_wait(struct drm_device *dev, void *data,
return i915_wait_irq(dev, irqwait->irq_seq);
}
@@ -8282,78 +8625,95 @@
+ int pipe = i915_get_pipe(dev, plane);
+ u32 pipestat_reg = 0;
+ u32 pipestat;
-+
++ u32 interrupt = 0;
++ unsigned long irqflags;
+
+- flag = 0;
+- if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_A)
+- flag |= VSYNC_PIPEA_FLAG;
+- if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_B)
+- flag |= VSYNC_PIPEB_FLAG;
+ switch (pipe) {
+ case 0:
+ pipestat_reg = PIPEASTAT;
-+ i915_enable_irq(dev_priv, I915_DISPLAY_PIPE_A_EVENT_INTERRUPT);
++ interrupt = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
+ break;
+ case 1:
+ pipestat_reg = PIPEBSTAT;
-+ i915_enable_irq(dev_priv, I915_DISPLAY_PIPE_B_EVENT_INTERRUPT);
++ interrupt = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
+ break;
+ default:
+ DRM_ERROR("tried to enable vblank on non-existent pipe %d\n",
+ pipe);
-+ break;
-+ }
-+
-+ if (pipestat_reg) {
-+ pipestat = I915_READ(pipestat_reg);
-+ if (IS_I965G(dev))
-+ pipestat |= PIPE_START_VBLANK_INTERRUPT_ENABLE;
-+ else
-+ pipestat |= PIPE_VBLANK_INTERRUPT_ENABLE;
-+ /* Clear any stale interrupt status */
-+ pipestat |= (PIPE_START_VBLANK_INTERRUPT_STATUS |
-+ PIPE_VBLANK_INTERRUPT_STATUS);
-+ I915_WRITE(pipestat_reg, pipestat);
++ return 0;
+ }
+
+- I915_WRITE16(I915REG_INT_ENABLE_R, USER_INT_FLAG | flag);
++ spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
++ /* Enabling vblank events in IMR comes before PIPESTAT write, or
++ * there's a race where the PIPESTAT vblank bit gets set to 1, so
++ * the OR of enabled PIPESTAT bits goes to 1, so the PIPExEVENT in
++ * ISR flashes to 1, but the IIR bit doesn't get set to 1 because
++ * IMR masks it. It doesn't ever get set after we clear the masking
++ * in IMR because the ISR bit is edge, not level-triggered, on the
++ * OR of PIPESTAT bits.
++ */
++ i915_enable_irq(dev_priv, interrupt);
++ pipestat = I915_READ(pipestat_reg);
++ if (IS_I965G(dev))
++ pipestat |= PIPE_START_VBLANK_INTERRUPT_ENABLE;
++ else
++ pipestat |= PIPE_VBLANK_INTERRUPT_ENABLE;
++ /* Clear any stale interrupt status */
++ pipestat |= (PIPE_START_VBLANK_INTERRUPT_STATUS |
++ PIPE_VBLANK_INTERRUPT_STATUS);
++ I915_WRITE(pipestat_reg, pipestat);
++ (void) I915_READ(pipestat_reg); /* Posting read */
++ spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
+
+ return 0;
+}
-
-- flag = 0;
-- if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_A)
-- flag |= VSYNC_PIPEA_FLAG;
-- if (dev_priv->vblank_pipe & DRM_I915_VBLANK_PIPE_B)
-- flag |= VSYNC_PIPEB_FLAG;
++
+void i915_disable_vblank(struct drm_device *dev, int plane)
+{
+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+ int pipe = i915_get_pipe(dev, plane);
+ u32 pipestat_reg = 0;
+ u32 pipestat;
++ u32 interrupt = 0;
++ unsigned long irqflags;
+
+ switch (pipe) {
+ case 0:
+ pipestat_reg = PIPEASTAT;
-+ i915_disable_irq(dev_priv, I915_DISPLAY_PIPE_A_EVENT_INTERRUPT);
++ interrupt = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
+ break;
+ case 1:
+ pipestat_reg = PIPEBSTAT;
-+ i915_disable_irq(dev_priv, I915_DISPLAY_PIPE_B_EVENT_INTERRUPT);
++ interrupt = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
+ break;
+ default:
+ DRM_ERROR("tried to disable vblank on non-existent pipe %d\n",
+ pipe);
++ return;
+ break;
+ }
-
-- I915_WRITE16(I915REG_INT_ENABLE_R, USER_INT_FLAG | flag);
-+ if (pipestat_reg) {
-+ pipestat = I915_READ(pipestat_reg);
-+ pipestat &= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE |
-+ PIPE_VBLANK_INTERRUPT_ENABLE);
-+ /* Clear any stale interrupt status */
-+ pipestat |= (PIPE_START_VBLANK_INTERRUPT_STATUS |
-+ PIPE_VBLANK_INTERRUPT_STATUS);
-+ I915_WRITE(pipestat_reg, pipestat);
-+ }
++
++ spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
++ i915_disable_irq(dev_priv, interrupt);
++ pipestat = I915_READ(pipestat_reg);
++ pipestat &= ~(PIPE_START_VBLANK_INTERRUPT_ENABLE |
++ PIPE_VBLANK_INTERRUPT_ENABLE);
++ /* Clear any stale interrupt status */
++ pipestat |= (PIPE_START_VBLANK_INTERRUPT_STATUS |
++ PIPE_VBLANK_INTERRUPT_STATUS);
++ I915_WRITE(pipestat_reg, pipestat);
++ (void) I915_READ(pipestat_reg); /* Posting read */
++ spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
}
/* Set the vblank monitor pipe
-@@ -434,22 +652,12 @@ int i915_vblank_pipe_set(struct drm_device *dev, void *data,
+@@ -434,22 +673,12 @@ int i915_vblank_pipe_set(struct drm_device *dev, void *data,
struct drm_file *file_priv)
{
drm_i915_private_t *dev_priv = dev->dev_private;
@@ -8376,7 +8736,7 @@
return 0;
}
-@@ -458,19 +666,13 @@ int i915_vblank_pipe_get(struct drm_device *dev, void *data,
+@@ -458,19 +687,13 @@ int i915_vblank_pipe_get(struct drm_device *dev, void *data,
{
drm_i915_private_t *dev_priv = dev->dev_private;
drm_i915_vblank_pipe_t *pipe = data;
@@ -8397,7 +8757,7 @@
return 0;
}
-@@ -484,11 +686,12 @@ int i915_vblank_swap(struct drm_device *dev, void *data,
+@@ -484,11 +707,12 @@ int i915_vblank_swap(struct drm_device *dev, void *data,
drm_i915_private_t *dev_priv = dev->dev_private;
drm_i915_vblank_swap_t *swap = data;
drm_i915_vbl_swap_t *vbl_swap;
@@ -8412,7 +8772,7 @@
DRM_ERROR("%s called with no initialization\n", __func__);
return -EINVAL;
}
-@@ -504,7 +707,8 @@ int i915_vblank_swap(struct drm_device *dev, void *data,
+@@ -504,7 +728,8 @@ int i915_vblank_swap(struct drm_device *dev, void *data,
return -EINVAL;
}
@@ -8422,7 +8782,7 @@
seqtype = swap->seqtype & (_DRM_VBLANK_RELATIVE | _DRM_VBLANK_ABSOLUTE);
-@@ -523,7 +727,14 @@ int i915_vblank_swap(struct drm_device *dev, void *data,
+@@ -523,7 +748,14 @@ int i915_vblank_swap(struct drm_device *dev, void *data,
spin_unlock_irqrestore(&dev->drw_lock, irqflags);
@@ -8438,7 +8798,7 @@
if (seqtype == _DRM_VBLANK_RELATIVE)
swap->sequence += curseq;
-@@ -533,6 +744,7 @@ int i915_vblank_swap(struct drm_device *dev, void *data,
+@@ -533,6 +765,7 @@ int i915_vblank_swap(struct drm_device *dev, void *data,
swap->sequence = curseq + 1;
} else {
DRM_DEBUG("Missed target sequence\n");
@@ -8446,7 +8806,7 @@
return -EINVAL;
}
}
-@@ -543,7 +755,7 @@ int i915_vblank_swap(struct drm_device *dev, void *data,
+@@ -543,9 +776,10 @@ int i915_vblank_swap(struct drm_device *dev, void *data,
vbl_swap = list_entry(list, drm_i915_vbl_swap_t, head);
if (vbl_swap->drw_id == swap->drawable &&
@@ -8454,8 +8814,11 @@
+ vbl_swap->plane == plane &&
vbl_swap->sequence == swap->sequence) {
spin_unlock_irqrestore(&dev_priv->swaps_lock, irqflags);
++ drm_vblank_put(dev, pipe);
DRM_DEBUG("Already scheduled\n");
-@@ -555,6 +767,7 @@ int i915_vblank_swap(struct drm_device *dev, void *data,
+ return 0;
+ }
+@@ -555,6 +789,7 @@ int i915_vblank_swap(struct drm_device *dev, void *data,
if (dev_priv->swaps_pending >= 100) {
DRM_DEBUG("Too many swaps queued\n");
@@ -8463,7 +8826,7 @@
return -EBUSY;
}
-@@ -562,13 +775,14 @@ int i915_vblank_swap(struct drm_device *dev, void *data,
+@@ -562,13 +797,14 @@ int i915_vblank_swap(struct drm_device *dev, void *data,
if (!vbl_swap) {
DRM_ERROR("Failed to allocate memory to queue swap\n");
@@ -8479,7 +8842,7 @@
vbl_swap->sequence = swap->sequence;
spin_lock_irqsave(&dev_priv->swaps_lock, irqflags);
-@@ -587,37 +801,63 @@ void i915_driver_irq_preinstall(struct drm_device * dev)
+@@ -587,37 +823,63 @@ void i915_driver_irq_preinstall(struct drm_device * dev)
{
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
@@ -11302,10 +11665,99 @@
default:
return -EINVAL;
diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c
-index 248ab4a..6157cd4 100644
+index 248ab4a..59a2132 100644
--- a/drivers/gpu/drm/radeon/radeon_cp.c
+++ b/drivers/gpu/drm/radeon/radeon_cp.c
-@@ -626,8 +626,6 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
+@@ -71,7 +71,8 @@ static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
+
+ static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
+ {
+- if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
++ if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
++ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
+ return RS690_READ_MCIND(dev_priv, addr);
+ else
+ return RS480_READ_MCIND(dev_priv, addr);
+@@ -82,7 +83,8 @@ u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
+
+ if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
+ return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
+- else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
++ else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
++ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
+ return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
+ else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
+ return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
+@@ -94,7 +96,8 @@ static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
+ {
+ if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
+ R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
+- else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
++ else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
++ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
+ RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
+ else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
+ R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
+@@ -106,7 +109,8 @@ static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_lo
+ {
+ if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
+ R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
+- else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
++ else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
++ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
+ RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
+ else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
+ R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
+@@ -122,15 +126,17 @@ static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
+ if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
+ R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
+ R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
+- } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
++ } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
++ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
+ RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
+ RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
+ } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
+ R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
+ R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
+- } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480) {
++ } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
++ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
+ RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
+- RADEON_WRITE(RS480_AGP_BASE_2, 0);
++ RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
+ } else {
+ RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
+ if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
+@@ -347,6 +353,7 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
+ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
+ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
+ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
++ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
+ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
+ DRM_INFO("Loading R300 Microcode\n");
+ for (i = 0; i < 256; i++) {
+@@ -356,6 +363,7 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
+ R300_cp_microcode[i][0]);
+ }
+ } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
++ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) ||
+ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
+ DRM_INFO("Loading R400 Microcode\n");
+ for (i = 0; i < 256; i++) {
+@@ -364,8 +372,9 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
+ RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
+ R420_cp_microcode[i][0]);
+ }
+- } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
+- DRM_INFO("Loading RS690 Microcode\n");
++ } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
++ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
++ DRM_INFO("Loading RS690/RS740 Microcode\n");
+ for (i = 0; i < 256; i++) {
+ RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
+ RS690_cp_microcode[i][1]);
+@@ -626,8 +635,6 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
dev_priv->ring.size_l2qw);
#endif
@@ -11314,7 +11766,28 @@
/* Initialize the scratch register pointer. This will cause
* the scratch register values to be written out to memory
-@@ -674,6 +672,9 @@ static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
+@@ -646,8 +653,18 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
+ RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
+
+ /* Turn on bus mastering */
+- tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
+- RADEON_WRITE(RADEON_BUS_CNTL, tmp);
++ if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
++ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
++ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
++ /* rs400, rs690/rs740 */
++ tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS400_BUS_MASTER_DIS;
++ RADEON_WRITE(RADEON_BUS_CNTL, tmp);
++ } else if (!(((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
++ ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R423))) {
++ /* r1xx, r2xx, r300, r(v)350, r420/r481, rs480 */
++ tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
++ RADEON_WRITE(RADEON_BUS_CNTL, tmp);
++ } /* PCIE cards appears to not need this */
+
+ dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
+ RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
+@@ -674,6 +691,9 @@ static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
{
u32 tmp;
@@ -11324,7 +11797,25 @@
/* Writeback doesn't seem to work everywhere, test it here and possibly
* enable it if it appears to work
*/
-@@ -1286,7 +1287,7 @@ static int radeon_do_resume_cp(struct drm_device * dev)
+@@ -719,7 +739,8 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
+ dev_priv->gart_size);
+
+ temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
+- if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
++ if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
++ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
+ IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
+ RS690_BLOCK_GFX_D3_EN));
+ else
+@@ -812,6 +833,7 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
+ u32 tmp;
+
+ if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
++ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
+ (dev_priv->flags & RADEON_IS_IGPGART)) {
+ radeon_set_igpgart(dev_priv, on);
+ return;
+@@ -1286,7 +1308,7 @@ static int radeon_do_resume_cp(struct drm_device * dev)
radeon_cp_init_ring_buffer(dev, dev_priv);
radeon_do_engine_reset(dev);
@@ -11333,6 +11824,14 @@
DRM_DEBUG("radeon_do_resume_cp() complete\n");
+@@ -1708,6 +1730,7 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
+ case CHIP_R300:
+ case CHIP_R350:
+ case CHIP_R420:
++ case CHIP_R423:
+ case CHIP_RV410:
+ case CHIP_RV515:
+ case CHIP_R520:
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index 637bd7f..71af746 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
@@ -11391,10 +11890,23 @@
.irq_preinstall = radeon_driver_irq_preinstall,
.irq_postinstall = radeon_driver_irq_postinstall,
diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
-index 0993816..d7e9c6c 100644
+index 0993816..4dbb813 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.h
+++ b/drivers/gpu/drm/radeon/radeon_drv.h
-@@ -378,17 +378,17 @@ extern void radeon_mem_release(struct drm_file *file_priv,
+@@ -122,9 +122,12 @@ enum radeon_family {
+ CHIP_RV350,
+ CHIP_RV380,
+ CHIP_R420,
++ CHIP_R423,
+ CHIP_RV410,
++ CHIP_RS400,
+ CHIP_RS480,
+ CHIP_RS690,
++ CHIP_RS740,
+ CHIP_RV515,
+ CHIP_R520,
+ CHIP_RV530,
+@@ -378,17 +381,17 @@ extern void radeon_mem_release(struct drm_file *file_priv,
struct mem_block *heap);
/* radeon_irq.c */
@@ -11417,7 +11929,7 @@
extern void radeon_driver_irq_uninstall(struct drm_device * dev);
extern void radeon_enable_interrupt(struct drm_device *dev);
extern int radeon_vblank_crtc_get(struct drm_device *dev);
-@@ -397,19 +397,22 @@ extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
+@@ -397,19 +400,22 @@ extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
extern int radeon_driver_unload(struct drm_device *dev);
extern int radeon_driver_firstopen(struct drm_device *dev);
@@ -11445,7 +11957,39 @@
/* Flags for stats.boxes
*/
-@@ -623,6 +626,7 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
+@@ -434,8 +440,31 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
+ # define RADEON_SCISSOR_1_ENABLE (1 << 29)
+ # define RADEON_SCISSOR_2_ENABLE (1 << 30)
+
++/*
++ * PCIE radeons (rv370/rv380, rv410, r423/r430/r480, r5xx)
++ * don't have an explicit bus mastering disable bit. It's handled
++ * by the PCI D-states. PMI_BM_DIS disables D-state bus master
++ * handling, not bus mastering itself.
++ */
+ #define RADEON_BUS_CNTL 0x0030
++/* r1xx, r2xx, r300, r(v)350, r420/r481, rs480 */
+ # define RADEON_BUS_MASTER_DIS (1 << 6)
++/* rs400, rs690/rs740 */
++# define RS400_BUS_MASTER_DIS (1 << 14)
++# define RS400_MSI_REARM (1 << 20)
++/* see RS480_MSI_REARM in AIC_CNTL for rs480 */
++
++#define RADEON_BUS_CNTL1 0x0034
++# define RADEON_PMI_BM_DIS (1 << 2)
++# define RADEON_PMI_INT_DIS (1 << 3)
++
++#define RV370_BUS_CNTL 0x004c
++# define RV370_PMI_BM_DIS (1 << 5)
++# define RV370_PMI_INT_DIS (1 << 6)
++
++#define RADEON_MSI_REARM_EN 0x0160
++/* rv370/rv380, rv410, r423/r430/r480, r5xx */
++# define RV370_MSI_REARM_EN (1 << 0)
+
+ #define RADEON_CLOCK_CNTL_DATA 0x000c
+ # define RADEON_PLL_WR_EN (1 << 7)
+@@ -623,6 +652,7 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
# define RADEON_SW_INT_TEST (1 << 25)
# define RADEON_SW_INT_TEST_ACK (1 << 25)
# define RADEON_SW_INT_FIRE (1 << 26)
@@ -11453,7 +11997,15 @@
#define RADEON_HOST_PATH_CNTL 0x0130
# define RADEON_HDP_SOFT_RESET (1 << 26)
-@@ -1116,6 +1120,9 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
+@@ -907,6 +937,7 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
+
+ #define RADEON_AIC_CNTL 0x01d0
+ # define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
++# define RS480_MSI_REARM (1 << 3)
+ #define RADEON_AIC_STAT 0x01d4
+ #define RADEON_AIC_PT_BASE 0x01d8
+ #define RADEON_AIC_LO_ADDR 0x01dc
+@@ -1116,6 +1147,9 @@ extern int r300_do_cp_cmdbuf(struct drm_device * dev,
#define R200_VAP_PVS_CNTL_1 0x22D0
@@ -11463,6 +12015,16 @@
#define R500_D1CRTC_STATUS 0x609c
#define R500_D2CRTC_STATUS 0x689c
#define R500_CRTC_V_BLANK (1<<0)
+@@ -1200,7 +1234,8 @@ do { \
+
+ #define IGP_WRITE_MCIND(addr, val) \
+ do { \
+- if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) \
++ if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) || \
++ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) \
+ RS690_WRITE_MCIND(addr, val); \
+ else \
+ RS480_WRITE_MCIND(addr, val); \
diff --git a/drivers/gpu/drm/radeon/radeon_irq.c b/drivers/gpu/drm/radeon/radeon_irq.c
index ee40d19..5079f70 100644
--- a/drivers/gpu/drm/radeon/radeon_irq.c
@@ -12325,7 +12887,7 @@
#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique)
#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth)
diff --git a/include/drm/drmP.h b/include/drm/drmP.h
-index 1c1b13e..90a9e02 100644
+index 1c1b13e..59c796b 100644
--- a/include/drm/drmP.h
+++ b/include/drm/drmP.h
@@ -104,6 +104,7 @@ struct drm_device;
@@ -12570,18 +13132,19 @@
static __inline__ int drm_core_check_feature(struct drm_device *dev,
int feature)
{
-@@ -867,6 +1013,10 @@ extern void *drm_realloc(void *oldpt, size_t oldsize, size_t size, int area);
+@@ -867,6 +1013,11 @@ extern void *drm_realloc(void *oldpt, size_t oldsize, size_t size, int area);
extern DRM_AGP_MEM *drm_alloc_agp(struct drm_device *dev, int pages, u32 type);
extern int drm_free_agp(DRM_AGP_MEM * handle, int pages);
extern int drm_bind_agp(DRM_AGP_MEM * handle, unsigned int start);
+extern DRM_AGP_MEM *drm_agp_bind_pages(struct drm_device *dev,
+ struct page **pages,
+ unsigned long num_pages,
-+ uint32_t gtt_offset);
++ uint32_t gtt_offset,
++ uint32_t type);
extern int drm_unbind_agp(DRM_AGP_MEM * handle);
/* Misc. IOCTL support (drm_ioctl.h) */
-@@ -929,6 +1079,9 @@ extern int drm_getmagic(struct drm_device *dev, void *data,
+@@ -929,6 +1080,9 @@ extern int drm_getmagic(struct drm_device *dev, void *data,
extern int drm_authmagic(struct drm_device *dev, void *data,
struct drm_file *file_priv);
@@ -12591,7 +13154,7 @@
/* Locking IOCTL support (drm_lock.h) */
extern int drm_lock(struct drm_device *dev, void *data,
struct drm_file *file_priv);
-@@ -985,15 +1138,25 @@ extern void drm_core_reclaim_buffers(struct drm_device *dev,
+@@ -985,15 +1139,25 @@ extern void drm_core_reclaim_buffers(struct drm_device *dev,
extern int drm_control(struct drm_device *dev, void *data,
struct drm_file *file_priv);
extern irqreturn_t drm_irq_handler(DRM_IRQ_ARGS);
@@ -12619,7 +13182,7 @@
extern void drm_locked_tasklet(struct drm_device *dev, void(*func)(struct drm_device*));
/* AGP/GART support (drm_agpsupport.h) */
-@@ -1026,6 +1189,7 @@ extern DRM_AGP_MEM *drm_agp_allocate_memory(struct agp_bridge_data *bridge, size
+@@ -1026,6 +1190,7 @@ extern DRM_AGP_MEM *drm_agp_allocate_memory(struct agp_bridge_data *bridge, size
extern int drm_agp_free_memory(DRM_AGP_MEM * handle);
extern int drm_agp_bind_memory(DRM_AGP_MEM * handle, off_t start);
extern int drm_agp_unbind_memory(DRM_AGP_MEM * handle);
@@ -12627,7 +13190,7 @@
/* Stub support (drm_stub.h) */
extern int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent,
-@@ -1088,6 +1252,66 @@ extern unsigned long drm_mm_tail_space(struct drm_mm *mm);
+@@ -1088,6 +1253,66 @@ extern unsigned long drm_mm_tail_space(struct drm_mm *mm);
extern int drm_mm_remove_space_from_tail(struct drm_mm *mm, unsigned long size);
extern int drm_mm_add_space_to_tail(struct drm_mm *mm, unsigned long size);
@@ -12694,6 +13257,92 @@
extern void drm_core_ioremap(struct drm_map *map, struct drm_device *dev);
extern void drm_core_ioremap_wc(struct drm_map *map, struct drm_device *dev);
extern void drm_core_ioremapfree(struct drm_map *map, struct drm_device *dev);
+diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h
+index 135bd19..da04109 100644
+--- a/include/drm/drm_pciids.h
++++ b/include/drm/drm_pciids.h
+@@ -84,18 +84,18 @@
+ {0x1002, 0x5462, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \
+ {0x1002, 0x5464, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \
+ {0x1002, 0x5657, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
+- {0x1002, 0x5548, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+- {0x1002, 0x5549, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+- {0x1002, 0x554A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+- {0x1002, 0x554B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+- {0x1002, 0x554C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+- {0x1002, 0x554D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+- {0x1002, 0x554E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+- {0x1002, 0x554F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+- {0x1002, 0x5550, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+- {0x1002, 0x5551, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+- {0x1002, 0x5552, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+- {0x1002, 0x5554, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x5548, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x5549, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x554A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x554B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x554C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x554D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x554E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x554F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x5550, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x5551, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x5552, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x5554, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x564A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x564B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x564F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+@@ -113,8 +113,10 @@
+ {0x1002, 0x5964, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
+ {0x1002, 0x5965, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
+ {0x1002, 0x5969, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
+- {0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
+- {0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
++ {0x1002, 0x5a41, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_IGPGART}, \
++ {0x1002, 0x5a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
++ {0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_IGPGART}, \
++ {0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
+ {0x1002, 0x5b60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x5b62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x5b63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
+@@ -122,16 +124,16 @@
+ {0x1002, 0x5b65, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x5c61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280|RADEON_IS_MOBILITY}, \
+ {0x1002, 0x5c63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280|RADEON_IS_MOBILITY}, \
+- {0x1002, 0x5d48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+- {0x1002, 0x5d49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+- {0x1002, 0x5d4a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+- {0x1002, 0x5d4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+- {0x1002, 0x5d4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+- {0x1002, 0x5d4e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+- {0x1002, 0x5d4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+- {0x1002, 0x5d50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+- {0x1002, 0x5d52, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+- {0x1002, 0x5d57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x5d48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x5d49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x5d4a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x5d4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x5d4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x5d4e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x5d4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x5d50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x5d52, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
++ {0x1002, 0x5d57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x5e48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x5e4a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x5e4b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
+@@ -237,6 +239,10 @@
+ {0x1002, 0x7835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+ {0x1002, 0x791e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
+ {0x1002, 0x791f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
++ {0x1002, 0x796c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
++ {0x1002, 0x796d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
++ {0x1002, 0x796e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
++ {0x1002, 0x796f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
+ {0, 0, 0}
+
+ #define r128_PCI_IDS \
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index 05c66cf..eb4b350 100644
--- a/include/drm/i915_drm.h
Index: kernel.spec
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/devel/kernel.spec,v
retrieving revision 1.1069
retrieving revision 1.1070
diff -u -r1.1069 -r1.1070
--- kernel.spec 20 Oct 2008 21:47:08 -0000 1.1069
+++ kernel.spec 21 Oct 2008 04:43:00 -0000 1.1070
@@ -645,7 +645,6 @@
Patch1811: drm-modesetting-radeon.patch
Patch1812: drm-modesetting-i915.patch
Patch1813: drm-nouveau.patch
-Patch1814: linux-2.6.27-drm-i915-fix-ioctl-security.patch
# kludge to make ich9 e1000 work
Patch2000: linux-2.6-e1000-ich9.patch
@@ -1243,9 +1242,8 @@
ApplyPatch linux-2.6-agp-intel-cantiga-fix.patch
ApplyPatch drm-next.patch
ApplyPatch drm-modesetting-radeon.patch
-ApplyPatch drm-modesetting-i915.patch
+#ApplyPatch drm-modesetting-i915.patch
ApplyPatch drm-nouveau.patch
-ApplyPatch linux-2.6.27-drm-i915-fix-ioctl-security.patch
# linux1394 git patches
ApplyPatch linux-2.6-firewire-git-update.patch
@@ -1844,6 +1842,10 @@
%kernel_variant_files -k vmlinux %{with_kdump} kdump
%changelog
+* Tue Oct 21 2008 Dave Airlie <airlied at redhat.com>
+- rebase to drm-next from upstream for GEM fixes.
+- drop intel modesetting for now - broken by rebase
+
* Mon Oct 20 2008 Chuck Ebbert <cebbert at redhat.com> 2.6.27.3-33.rc1
- Update applesmc hwmon driver to what is upstream for 2.6.28.
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