rpms/kernel/devel drm-modesetting-radeon.patch, 1.41, 1.42 kernel.spec, 1.1092, 1.1093
Dave Airlie
airlied at fedoraproject.org
Mon Oct 27 20:13:26 UTC 2008
Author: airlied
Update of /cvs/pkgs/rpms/kernel/devel
In directory cvs1.fedora.phx.redhat.com:/tmp/cvs-serv9236
Modified Files:
drm-modesetting-radeon.patch kernel.spec
Log Message:
- fix rs4xx bus mastering.
drm-modesetting-radeon.patch:
Index: drm-modesetting-radeon.patch
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/devel/drm-modesetting-radeon.patch,v
retrieving revision 1.41
retrieving revision 1.42
diff -u -r1.41 -r1.42
--- drm-modesetting-radeon.patch 27 Oct 2008 06:52:24 -0000 1.41
+++ drm-modesetting-radeon.patch 27 Oct 2008 20:13:25 -0000 1.42
@@ -1,3 +1,15 @@
+commit c5ac6f0d9dedfaa78987d00ed2dfa7296ba55668
+Author: Dave Airlie <airlied at redhat.com>
+Date: Tue Oct 28 06:05:58 2008 +1000
+
+ radeon: rs480 fixes for bus mastering
+
+commit dcdddb966eee207a3a24b8e0c2fcd7caf30f512d
+Author: Dave Airlie <airlied at redhat.com>
+Date: Mon Oct 27 18:30:15 2008 +1000
+
+ radeon: remove unused gem indirect ioctl
+
commit 3d3d149bb684e40fd0f64e6bd24435cca67f3782
Author: Dave Airlie <airlied at redhat.com>
Date: Mon Oct 27 16:41:09 2008 +1000
@@ -23158,7 +23170,7 @@
+ return NULL;
+}
diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c
-index 59a2132..fa7f9f6 100644
+index 59a2132..0d62c65 100644
--- a/drivers/gpu/drm/radeon/radeon_cp.c
+++ b/drivers/gpu/drm/radeon/radeon_cp.c
@@ -31,6 +31,7 @@
@@ -23270,7 +23282,7 @@
R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
else
RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
-@@ -144,20 +200,115 @@ static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
+@@ -144,20 +200,116 @@ static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
}
}
@@ -23280,15 +23292,16 @@
- drm_radeon_private_t *dev_priv = dev->dev_private;
+ u32 tmp;
+ /* Turn on bus mastering */
-+ if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
-+ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
++ if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
+ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
-+ /* rs400, rs690/rs740 */
-+ tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS400_BUS_MASTER_DIS;
++ /* rs600/rs690/rs740 */
++ tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
+ RADEON_WRITE(RADEON_BUS_CNTL, tmp);
-+ } else if (!(((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
-+ ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R423))) {
-+ /* r1xx, r2xx, r300, r(v)350, r420/r481, rs480 */
++ } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
++ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
++ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
++ ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
++ /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
+ tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
+ RADEON_WRITE(RADEON_BUS_CNTL, tmp);
+ } /* PCIE cards appears to not need this */
@@ -23310,9 +23323,7 @@
+ */
+ if (dev_priv->pll_errata & CHIP_ERRATA_PLL_DELAY)
+ udelay(5000);
-
-- RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
-- return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
++
+ /* This function is required to workaround a hardware bug in some (all?)
+ * revisions of the R300. This workaround should be called after every
+ * CLOCK_CNTL_INDEX register access. If not, register reads afterward
@@ -23332,23 +23343,25 @@
+u32 RADEON_READ_PLL(struct drm_radeon_private *dev_priv, int addr)
+{
+ uint32_t data;
-+
+
+- RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
+- return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
+ RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x3f);
+ radeon_pll_errata_after_index(dev_priv);
+ data = RADEON_READ(RADEON_CLOCK_CNTL_DATA);
+ radeon_pll_errata_after_data(dev_priv);
+ return data;
- }
-
--static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
++}
++
+void RADEON_WRITE_PLL(struct drm_radeon_private *dev_priv, int addr, uint32_t data)
+{
+ RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, ((addr & 0x3f) | RADEON_PLL_WR_EN));
+ radeon_pll_errata_after_index(dev_priv);
+ RADEON_WRITE(RADEON_CLOCK_CNTL_DATA, data);
+ radeon_pll_errata_after_data(dev_priv);
-+}
-+
+ }
+
+-static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
+u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
{
RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
@@ -23391,7 +23404,7 @@
#if RADEON_FIFO_DEBUG
static void radeon_status(drm_radeon_private_t * dev_priv)
{
-@@ -240,7 +391,7 @@ static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
+@@ -240,7 +392,7 @@ static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
return -EBUSY;
}
@@ -23400,7 +23413,7 @@
{
int i, ret;
-@@ -300,7 +451,7 @@ static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
+@@ -300,7 +452,7 @@ static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
}
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
@@ -23409,7 +23422,7 @@
RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
}
RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
-@@ -406,7 +557,6 @@ static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
+@@ -406,7 +558,6 @@ static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
DRM_DEBUG("\n");
#if 0
u32 tmp;
@@ -23417,7 +23430,7 @@
tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
#endif
-@@ -501,15 +651,15 @@ static int radeon_do_engine_reset(struct drm_device * dev)
+@@ -501,15 +652,15 @@ static int radeon_do_engine_reset(struct drm_device * dev)
if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
/* may need something similar for newer chips */
clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
@@ -23442,7 +23455,7 @@
}
rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
-@@ -534,7 +684,7 @@ static int radeon_do_engine_reset(struct drm_device * dev)
+@@ -534,7 +685,7 @@ static int radeon_do_engine_reset(struct drm_device * dev)
RADEON_READ(RADEON_RBBM_SOFT_RESET);
if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
@@ -23451,7 +23464,7 @@
RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
}
-@@ -550,7 +700,8 @@ static int radeon_do_engine_reset(struct drm_device * dev)
+@@ -550,7 +701,8 @@ static int radeon_do_engine_reset(struct drm_device * dev)
dev_priv->cp_running = 0;
/* Reset any pending vertex, indirect buffers */
@@ -23461,7 +23474,7 @@
return 0;
}
-@@ -559,7 +710,6 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
+@@ -559,7 +711,6 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
drm_radeon_private_t * dev_priv)
{
u32 ring_start, cur_read_ptr;
@@ -23469,7 +23482,7 @@
/* Initialize the memory controller. With new memory map, the fb location
* is not changed, it should have been properly initialized already. Part
-@@ -568,9 +718,13 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
+@@ -568,9 +719,13 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
*/
if (!dev_priv->new_memmap)
radeon_write_fb_location(dev_priv,
@@ -23486,7 +23499,7 @@
#if __OS_HAS_AGP
if (dev_priv->flags & RADEON_IS_AGP) {
radeon_write_agp_base(dev_priv, dev->agp->base);
-@@ -578,7 +732,7 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
+@@ -578,7 +733,7 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
radeon_write_agp_location(dev_priv,
(((dev_priv->gart_vm_start - 1 +
dev_priv->gart_size) & 0xffff0000) |
@@ -23495,7 +23508,7 @@
ring_start = (dev_priv->cp_ring->offset
- dev->agp->base
-@@ -600,6 +754,12 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
+@@ -600,6 +755,12 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
SET_RING_HEAD(dev_priv, cur_read_ptr);
dev_priv->ring.tail = cur_read_ptr;
@@ -23508,7 +23521,7 @@
#if __OS_HAS_AGP
if (dev_priv->flags & RADEON_IS_AGP) {
RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
-@@ -646,62 +806,79 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
+@@ -646,62 +807,79 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
+ RADEON_SCRATCH_REG_OFFSET);
@@ -23616,7 +23629,7 @@
0xdeadbeef)
break;
DRM_UDELAY(1);
-@@ -719,10 +896,12 @@ static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
+@@ -719,10 +897,12 @@ static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
DRM_INFO("writeback forced off\n");
}
@@ -23632,7 +23645,7 @@
RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
}
}
-@@ -734,9 +913,9 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
+@@ -734,9 +914,9 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
if (on) {
DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
@@ -23645,7 +23658,7 @@
temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
-@@ -763,13 +942,20 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
+@@ -763,13 +943,20 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
RS480_REQ_TYPE_SNOOP_DIS));
@@ -23670,7 +23683,7 @@
temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
-@@ -780,7 +966,7 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
+@@ -780,7 +967,7 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
break;
DRM_UDELAY(1);
@@ -23679,7 +23692,7 @@
IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
RS480_GART_CACHE_INVALIDATE);
-@@ -790,7 +976,7 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
+@@ -790,7 +977,7 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
break;
DRM_UDELAY(1);
@@ -23688,7 +23701,7 @@
IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
} else {
-@@ -817,7 +1003,7 @@ static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
+@@ -817,7 +1004,7 @@ static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
dev_priv->gart_vm_start +
dev_priv->gart_size - 1);
@@ -23697,7 +23710,7 @@
RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
RADEON_PCIE_TX_GART_EN);
-@@ -828,7 +1014,7 @@ static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
+@@ -828,7 +1015,7 @@ static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
}
/* Enable or disable PCI GART on the chip */
@@ -23706,7 +23719,7 @@
{
u32 tmp;
-@@ -862,7 +1048,7 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
+@@ -862,7 +1049,7 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
/* Turn off AGP aperture -- is this required for PCI GART?
*/
@@ -23715,7 +23728,7 @@
RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
} else {
RADEON_WRITE(RADEON_AIC_CNTL,
-@@ -870,9 +1056,11 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
+@@ -870,9 +1057,11 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
}
}
@@ -23728,7 +23741,7 @@
DRM_DEBUG("\n");
-@@ -910,17 +1098,6 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
+@@ -910,17 +1099,6 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
*/
dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
@@ -23746,7 +23759,7 @@
dev_priv->do_boxes = 0;
dev_priv->cp_mode = init->cp_mode;
-@@ -968,9 +1145,8 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
+@@ -968,9 +1146,8 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
*/
dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
(dev_priv->color_fmt << 10) |
@@ -23758,7 +23771,7 @@
dev_priv->depth_clear.rb3d_zstencilcntl =
(dev_priv->depth_fmt |
RADEON_Z_TEST_ALWAYS |
-@@ -997,8 +1173,8 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
+@@ -997,8 +1174,8 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
dev_priv->buffers_offset = init->buffers_offset;
dev_priv->gart_textures_offset = init->gart_textures_offset;
@@ -23769,7 +23782,7 @@
DRM_ERROR("could not find sarea!\n");
radeon_do_cleanup_cp(dev);
return -EINVAL;
-@@ -1034,10 +1210,6 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
+@@ -1034,10 +1211,6 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
}
}
@@ -23780,7 +23793,7 @@
#if __OS_HAS_AGP
if (dev_priv->flags & RADEON_IS_AGP) {
drm_core_ioremap(dev_priv->cp_ring, dev);
-@@ -1167,28 +1339,41 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
+@@ -1167,28 +1340,41 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
/* if we have an offset set from userspace */
if (dev_priv->pcigart_offset_set) {
@@ -23842,7 +23855,7 @@
if (dev_priv->flags & RADEON_IS_IGPGART)
dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
else
-@@ -1197,12 +1382,7 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
+@@ -1197,12 +1383,7 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
DRM_ATI_GART_MAIN;
dev_priv->gart_info.addr = NULL;
dev_priv->gart_info.bus_addr = 0;
@@ -23856,7 +23869,7 @@
}
if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
-@@ -1215,6 +1395,9 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
+@@ -1215,6 +1396,9 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
radeon_set_pcigart(dev_priv, 1);
}
@@ -23866,7 +23879,7 @@
radeon_cp_load_microcode(dev_priv);
radeon_cp_init_ring_buffer(dev, dev_priv);
-@@ -1259,14 +1442,16 @@ static int radeon_do_cleanup_cp(struct drm_device * dev)
+@@ -1259,14 +1443,16 @@ static int radeon_do_cleanup_cp(struct drm_device * dev)
if (dev_priv->gart_info.bus_addr) {
/* Turn off PCI GART */
radeon_set_pcigart(dev_priv, 0);
@@ -23887,7 +23900,7 @@
}
}
/* only clear to the start of flags */
-@@ -1318,6 +1503,10 @@ static int radeon_do_resume_cp(struct drm_device * dev)
+@@ -1318,6 +1504,10 @@ static int radeon_do_resume_cp(struct drm_device * dev)
int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
drm_radeon_init_t *init = data;
@@ -23898,7 +23911,7 @@
LOCK_TEST_WITH_RETURN(dev, file_priv);
-@@ -1328,7 +1517,7 @@ int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_pri
+@@ -1328,7 +1518,7 @@ int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_pri
case RADEON_INIT_CP:
case RADEON_INIT_R200_CP:
case RADEON_INIT_R300_CP:
@@ -23907,7 +23920,7 @@
case RADEON_CLEANUP_CP:
return radeon_do_cleanup_cp(dev);
}
-@@ -1341,6 +1530,9 @@ int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_pr
+@@ -1341,6 +1531,9 @@ int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_pr
drm_radeon_private_t *dev_priv = dev->dev_private;
DRM_DEBUG("\n");
@@ -23917,7 +23930,7 @@
LOCK_TEST_WITH_RETURN(dev, file_priv);
if (dev_priv->cp_running) {
-@@ -1368,6 +1560,9 @@ int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_pri
+@@ -1368,6 +1561,9 @@ int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_pri
int ret;
DRM_DEBUG("\n");
@@ -23927,7 +23940,7 @@
LOCK_TEST_WITH_RETURN(dev, file_priv);
if (!dev_priv->cp_running)
-@@ -1406,6 +1601,9 @@ void radeon_do_release(struct drm_device * dev)
+@@ -1406,6 +1602,9 @@ void radeon_do_release(struct drm_device * dev)
drm_radeon_private_t *dev_priv = dev->dev_private;
int i, ret;
@@ -23937,7 +23950,7 @@
if (dev_priv) {
if (dev_priv->cp_running) {
/* Stop the cp */
-@@ -1439,6 +1637,9 @@ void radeon_do_release(struct drm_device * dev)
+@@ -1439,6 +1638,9 @@ void radeon_do_release(struct drm_device * dev)
radeon_mem_takedown(&(dev_priv->gart_heap));
radeon_mem_takedown(&(dev_priv->fb_heap));
@@ -23947,7 +23960,7 @@
/* deallocate kernel resources */
radeon_do_cleanup_cp(dev);
}
-@@ -1451,6 +1652,9 @@ int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_pr
+@@ -1451,6 +1653,9 @@ int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_pr
drm_radeon_private_t *dev_priv = dev->dev_private;
DRM_DEBUG("\n");
@@ -23957,7 +23970,7 @@
LOCK_TEST_WITH_RETURN(dev, file_priv);
if (!dev_priv) {
-@@ -1471,7 +1675,9 @@ int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_pri
+@@ -1471,7 +1676,9 @@ int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_pri
drm_radeon_private_t *dev_priv = dev->dev_private;
DRM_DEBUG("\n");
@@ -23968,7 +23981,7 @@
return radeon_do_cp_idle(dev_priv);
}
-@@ -1481,6 +1687,9 @@ int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_pri
+@@ -1481,6 +1688,9 @@ int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_pri
int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
@@ -23978,7 +23991,7 @@
return radeon_do_resume_cp(dev);
}
-@@ -1488,6 +1697,9 @@ int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *fil
+@@ -1488,6 +1698,9 @@ int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *fil
{
DRM_DEBUG("\n");
@@ -23988,7 +24001,7 @@
LOCK_TEST_WITH_RETURN(dev, file_priv);
return radeon_do_engine_reset(dev);
-@@ -1710,6 +1922,709 @@ int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_
+@@ -1710,6 +1923,709 @@ int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_
return ret;
}
@@ -24698,7 +24711,7 @@
int radeon_driver_load(struct drm_device *dev, unsigned long flags)
{
drm_radeon_private_t *dev_priv;
-@@ -1723,6 +2638,8 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
+@@ -1723,6 +2639,8 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
dev->dev_private = (void *)dev_priv;
dev_priv->flags = flags;
@@ -24707,7 +24720,7 @@
switch (flags & RADEON_FAMILY_MASK) {
case CHIP_R100:
case CHIP_RV200:
-@@ -1743,6 +2660,14 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
+@@ -1743,6 +2661,14 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
break;
}
@@ -24722,7 +24735,7 @@
if (drm_device_is_agp(dev))
dev_priv->flags |= RADEON_IS_AGP;
else if (drm_device_is_pcie(dev))
-@@ -1752,7 +2677,112 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
+@@ -1752,33 +2678,123 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
DRM_DEBUG("%s card detected\n",
((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
@@ -24782,13 +24795,13 @@
+ }
+
+
- return ret;
++ return ret;
+modeset_fail:
+ dev->driver->driver_features &= ~DRIVER_MODESET;
+ drm_put_minor(&dev->control);
-+ return ret;
-+}
-+
+ return ret;
+ }
+
+int radeon_master_create(struct drm_device *dev, struct drm_master *master)
+{
+ struct drm_radeon_master_private *master_priv;
@@ -24832,10 +24845,10 @@
+ drm_free(master_priv, sizeof(*master_priv), DRM_MEM_DRIVER);
+
+ master->driver_priv = NULL;
- }
-
++}
++
/* Create mappings for registers and framebuffer so userland doesn't necessarily
-@@ -1760,25 +2790,10 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
+ * have to find them.
*/
int radeon_driver_firstopen(struct drm_device *dev)
{
@@ -24861,7 +24874,7 @@
return 0;
}
-@@ -1786,9 +2801,44 @@ int radeon_driver_unload(struct drm_device *dev)
+@@ -1786,9 +2802,44 @@ int radeon_driver_unload(struct drm_device *dev)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -26612,7 +26625,7 @@
}
diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
-index 4dbb813..cf7761c 100644
+index 4dbb813..aff4f29 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.h
+++ b/drivers/gpu/drm/radeon/radeon_drv.h
@@ -34,6 +34,8 @@
@@ -26778,7 +26791,7 @@
+ int (*relocate)(struct drm_radeon_cs_parser *parser,
+ uint32_t *reloc, uint32_t *offset);
+};
-+
+
+
+
+struct radeon_pm_regs {
@@ -26788,7 +26801,7 @@
+
+typedef struct drm_radeon_private {
+ drm_radeon_ring_buffer_t ring;
-
++
+ bool new_memmap;
+ bool user_mm_enable; /* userspace enabled the memory manager */
int gart_size;
@@ -26950,6 +26963,24 @@
#define RADEON_AGP_COMMAND 0x0f60
#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
# define RADEON_AGP_ENABLE (1<<8)
+@@ -447,12 +597,12 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+ * handling, not bus mastering itself.
+ */
+ #define RADEON_BUS_CNTL 0x0030
+-/* r1xx, r2xx, r300, r(v)350, r420/r481, rs480 */
++/* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
+ # define RADEON_BUS_MASTER_DIS (1 << 6)
+-/* rs400, rs690/rs740 */
+-# define RS400_BUS_MASTER_DIS (1 << 14)
+-# define RS400_MSI_REARM (1 << 20)
+-/* see RS480_MSI_REARM in AIC_CNTL for rs480 */
++/* rs600/rs690/rs740 */
++# define RS600_BUS_MASTER_DIS (1 << 14)
++# define RS600_MSI_REARM (1 << 20)
++/* see RS400_MSI_REARM in AIC_CNTL for rs480 */
+
+ #define RADEON_BUS_CNTL1 0x0034
+ # define RADEON_PMI_BM_DIS (1 << 2)
@@ -554,16 +704,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define R520_MC_IND_WR_EN (1 << 24)
#define R520_MC_IND_DATA 0x74
@@ -27066,6 +27097,15 @@
#define RADEON_RBBM_SOFT_RESET 0x00f0
# define RADEON_SOFT_RESET_CP (1 << 0)
# define RADEON_SOFT_RESET_HI (1 << 1)
+@@ -937,7 +1087,7 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+
+ #define RADEON_AIC_CNTL 0x01d0
+ # define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
+-# define RS480_MSI_REARM (1 << 3)
++# define RS400_MSI_REARM (1 << 3)
+ #define RADEON_AIC_STAT 0x01d4
+ #define RADEON_AIC_PT_BASE 0x01d8
+ #define RADEON_AIC_LO_ADDR 0x01dc
@@ -1009,27 +1159,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define RADEON_NUM_VERTICES_SHIFT 16
@@ -27206,7 +27246,7 @@
if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
int __ret = radeon_do_cp_idle( dev_priv ); \
if ( __ret ) return __ret; \
-@@ -1443,4 +1618,144 @@ do { \
+@@ -1443,4 +1618,142 @@ do { \
write &= mask; \
} while (0)
@@ -27319,8 +27359,6 @@
+int radeon_gem_object_pin(struct drm_gem_object *obj,
+ uint32_t alignment, uint32_t pin_domain);
+int radeon_gem_object_unpin(struct drm_gem_object *obj);
-+int radeon_gem_indirect_ioctl(struct drm_device *dev, void *data,
-+ struct drm_file *file_priv);
+int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
+ struct drm_file *file_priv);
+struct drm_gem_object *radeon_gem_object_alloc(struct drm_device *dev, int size, int alignment,
@@ -29499,10 +29537,10 @@
+
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
new file mode 100644
-index 0000000..6c62620
+index 0000000..ce33979
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
-@@ -0,0 +1,1646 @@
+@@ -0,0 +1,1571 @@
+/*
+ * Copyright 2008 Red Hat Inc.
+ *
@@ -29929,81 +29967,6 @@
+
+}
+
-+int radeon_gem_indirect_ioctl(struct drm_device *dev, void *data,
-+ struct drm_file *file_priv)
-+{
-+ struct drm_radeon_gem_indirect *args = data;
-+ struct drm_radeon_private *dev_priv = dev->dev_private;
-+ struct drm_gem_object *obj;
-+ struct drm_radeon_gem_object *obj_priv;
-+ uint32_t start, end;
-+ int ret;
-+ RING_LOCALS;
-+
-+ obj = drm_gem_object_lookup(dev, file_priv, args->handle);
-+ if (obj == NULL)
-+ return -EINVAL;
-+
-+ obj_priv = obj->driver_private;
-+
-+ DRM_DEBUG("got here %p %d\n", obj, args->used);
-+ //RING_SPACE_TEST_WITH_RETURN(dev_priv);
-+ //VB_AGE_TEST_WITH_RETURN(dev_priv);
-+
-+ ret = drm_bo_do_validate(obj_priv->bo, 0, DRM_BO_FLAG_NO_EVICT,
-+ 0 , 0);
-+ if (ret)
-+ return ret;
-+
-+ /* Wait for the 3D stream to idle before the indirect buffer
-+ * containing 2D acceleration commands is processed.
-+ */
-+ BEGIN_RING(2);
-+
-+ RADEON_WAIT_UNTIL_3D_IDLE();
-+
-+ ADVANCE_RING();
-+
-+ start = 0;
-+ end = args->used;
-+
-+ if (start != end) {
-+ int offset = (dev_priv->gart_vm_start +
-+ + obj_priv->bo->offset + start);
-+ int dwords = (end - start + 3) / sizeof(u32);
-+
-+ /* Fire off the indirect buffer */
-+ BEGIN_RING(3);
-+
-+ OUT_RING(CP_PACKET0(RADEON_CP_IB_BASE, 1));
-+ OUT_RING(offset);
-+ OUT_RING(dwords);
-+
-+ ADVANCE_RING();
-+ }
-+
-+ COMMIT_RING();
-+
-+ /* we need to fence the buffer */
-+ ret = drm_fence_buffer_objects(dev, NULL, 0, NULL, &obj_priv->fence);
-+ if (ret) {
-+
-+ drm_putback_buffer_objects(dev);
-+ ret = 0;
-+ goto fail;
-+ }
-+
-+ /* dereference he fence object */
-+ drm_fence_usage_deref_unlocked(&obj_priv->fence);
-+
-+ mutex_lock(&dev->struct_mutex);
-+ drm_gem_object_unreference(obj);
-+ mutex_unlock(&dev->struct_mutex);
-+ ret = 0;
-+ fail:
-+ return ret;
-+}
-+
+/*
+ * Depending on card genertation, chipset bugs, etc... the amount of vram
+ * accessible to the CPU can vary. This function is our best shot at figuring
@@ -39840,7 +39803,7 @@
+
+#endif
diff --git a/drivers/gpu/drm/radeon/radeon_state.c b/drivers/gpu/drm/radeon/radeon_state.c
-index 5d7153f..5dbff1c 100644
+index 5d7153f..3200f01 100644
--- a/drivers/gpu/drm/radeon/radeon_state.c
+++ b/drivers/gpu/drm/radeon/radeon_state.c
@@ -305,8 +305,9 @@ static __inline__ int radeon_check_and_fixup_packet3(drm_radeon_private_t *
@@ -40513,7 +40476,7 @@
radeon_do_release(dev);
}
-@@ -3197,7 +3232,20 @@ struct drm_ioctl_desc radeon_ioctls[] = {
+@@ -3197,7 +3232,19 @@ struct drm_ioctl_desc radeon_ioctls[] = {
DRM_IOCTL_DEF(DRM_RADEON_IRQ_WAIT, radeon_irq_wait, DRM_AUTH),
DRM_IOCTL_DEF(DRM_RADEON_SETPARAM, radeon_cp_setparam, DRM_AUTH),
DRM_IOCTL_DEF(DRM_RADEON_SURF_ALLOC, radeon_surface_alloc, DRM_AUTH),
@@ -40529,7 +40492,6 @@
+ DRM_IOCTL_DEF(DRM_RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH),
+ DRM_IOCTL_DEF(DRM_RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH),
+ DRM_IOCTL_DEF(DRM_RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH),
-+ DRM_IOCTL_DEF(DRM_RADEON_GEM_INDIRECT, radeon_gem_indirect_ioctl, DRM_AUTH),
+ DRM_IOCTL_DEF(DRM_RADEON_CS, radeon_cs_ioctl, DRM_AUTH),
+ DRM_IOCTL_DEF(DRM_RADEON_CS2, radeon_cs2_ioctl, DRM_AUTH),
};
@@ -43330,7 +43292,7 @@
int used; /* nr bytes in use */
int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
diff --git a/include/drm/radeon_drm.h b/include/drm/radeon_drm.h
-index 73ff51f..d63d20c 100644
+index 73ff51f..a2c6b79 100644
--- a/include/drm/radeon_drm.h
+++ b/include/drm/radeon_drm.h
@@ -453,6 +453,15 @@ typedef struct {
@@ -43349,7 +43311,7 @@
} drm_radeon_sarea_t;
/* WARNING: If you change any of these defines, make sure to change the
-@@ -493,6 +502,19 @@ typedef struct {
+@@ -493,6 +502,18 @@ typedef struct {
#define DRM_RADEON_SURF_ALLOC 0x1a
#define DRM_RADEON_SURF_FREE 0x1b
@@ -43361,7 +43323,6 @@
+#define DRM_RADEON_GEM_PREAD 0x21
+#define DRM_RADEON_GEM_PWRITE 0x22
+#define DRM_RADEON_GEM_SET_DOMAIN 0x23
-+#define DRM_RADEON_GEM_INDIRECT 0x24 // temporary for X server
+
+#define DRM_RADEON_CS 0x25
+#define DRM_RADEON_CS2 0x26
@@ -43369,7 +43330,7 @@
#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_INIT, drm_radeon_init_t)
#define DRM_IOCTL_RADEON_CP_START DRM_IO( DRM_COMMAND_BASE + DRM_RADEON_CP_START)
#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_CP_STOP, drm_radeon_cp_stop_t)
-@@ -521,6 +543,20 @@ typedef struct {
+@@ -521,6 +542,19 @@ typedef struct {
#define DRM_IOCTL_RADEON_SURF_ALLOC DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_ALLOC, drm_radeon_surface_alloc_t)
#define DRM_IOCTL_RADEON_SURF_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_RADEON_SURF_FREE, drm_radeon_surface_free_t)
@@ -43381,7 +43342,6 @@
+#define DRM_IOCTL_RADEON_GEM_PREAD DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PREAD, struct drm_radeon_gem_pread)
+#define DRM_IOCTL_RADEON_GEM_PWRITE DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_PWRITE, struct drm_radeon_gem_pwrite)
+#define DRM_IOCTL_RADEON_GEM_SET_DOMAIN DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_SET_DOMAIN, struct drm_radeon_gem_set_domain)
-+#define DRM_IOCTL_RADEON_GEM_INDIRECT DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_GEM_INDIRECT, struct drm_radeon_gem_indirect)
+
+#define DRM_IOCTL_RADEON_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS, struct drm_radeon_cs)
+#define DRM_IOCTL_RADEON_CS2 DRM_IOWR(DRM_COMMAND_BASE + DRM_RADEON_CS2, struct drm_radeon_cs2)
@@ -43390,7 +43350,7 @@
typedef struct drm_radeon_init {
enum {
RADEON_INIT_CP = 0x01,
-@@ -677,6 +713,7 @@ typedef struct drm_radeon_indirect {
+@@ -677,6 +711,7 @@ typedef struct drm_radeon_indirect {
#define RADEON_PARAM_VBLANK_CRTC 13 /* VBLANK CRTC */
#define RADEON_PARAM_FB_LOCATION 14 /* FB location */
#define RADEON_PARAM_NUM_GB_PIPES 15 /* num GB pipes */
@@ -43398,7 +43358,7 @@
typedef struct drm_radeon_getparam {
int param;
-@@ -731,6 +768,7 @@ typedef struct drm_radeon_setparam {
+@@ -731,6 +766,7 @@ typedef struct drm_radeon_setparam {
#define RADEON_SETPARAM_NEW_MEMMAP 4 /* Use new memory map */
#define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 /* PCI GART Table Size */
#define RADEON_SETPARAM_VBLANK_CRTC 6 /* VBLANK CRTC */
@@ -43406,7 +43366,7 @@
/* 1.14: Clients can allocate/free a surface
*/
typedef struct drm_radeon_surface_alloc {
-@@ -746,4 +784,117 @@ typedef struct drm_radeon_surface_free {
+@@ -746,4 +782,113 @@ typedef struct drm_radeon_surface_free {
#define DRM_RADEON_VBLANK_CRTC1 1
#define DRM_RADEON_VBLANK_CRTC2 2
@@ -43490,10 +43450,6 @@
+ uint64_t data_ptr; /* void *, but pointers are not 32/64 compatible */
+};
+
-+struct drm_radeon_gem_indirect {
-+ uint32_t handle;
-+ uint32_t used;
-+};
+
+/* New interface which obsolete all previous interface.
+ */
Index: kernel.spec
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/devel/kernel.spec,v
retrieving revision 1.1092
retrieving revision 1.1093
diff -u -r1.1092 -r1.1093
--- kernel.spec 27 Oct 2008 17:12:32 -0000 1.1092
+++ kernel.spec 27 Oct 2008 20:13:25 -0000 1.1093
@@ -1875,6 +1875,9 @@
%kernel_variant_files -k vmlinux %{with_kdump} kdump
%changelog
+* Tue Oct 28 2008 Dave Airlie <airlied at redhat.com>
+- fix rs4xx bus mastering.
+
* Mon Oct 27 2008 Jeremy Katz <katzj at redhat.com>
- Make olpc-battery built in so that its usable (#467759)
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