rpms/kernel/devel drm-modesetting-radeon.patch, 1.43, 1.44 kernel.spec, 1.1096, 1.1097
Dave Airlie
airlied at fedoraproject.org
Tue Oct 28 10:45:52 UTC 2008
Author: airlied
Update of /cvs/pkgs/rpms/kernel/devel
In directory cvs1.fedora.phx.redhat.com:/tmp/cvs-serv27070
Modified Files:
drm-modesetting-radeon.patch kernel.spec
Log Message:
- modesetting add some debugging in /proc and pad ring writes
drm-modesetting-radeon.patch:
Index: drm-modesetting-radeon.patch
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/devel/drm-modesetting-radeon.patch,v
retrieving revision 1.43
retrieving revision 1.44
diff -u -r1.43 -r1.44
--- drm-modesetting-radeon.patch 27 Oct 2008 20:40:04 -0000 1.43
+++ drm-modesetting-radeon.patch 28 Oct 2008 10:45:51 -0000 1.44
@@ -1,3 +1,41 @@
+commit df78b729e04e0bde33d88526f594ac70f8fe1649
+Author: Dave Airlie <airlied at redhat.com>
+Date: Tue Oct 28 20:33:13 2008 +1000
+
+ radeon: setup isync cntl properly
+
+commit 9aea2a12e6a98a889dfa3031a5f7199e35bdb42d
+Author: Dave Airlie <airlied at redhat.com>
+Date: Tue Oct 28 20:31:27 2008 +1000
+
+ radeon: add more debugging
+
+commit 2be1531419a8fb4abe33ce0e2202aed52ba59700
+Author: Dave Airlie <airlied at redhat.com>
+Date: Tue Oct 28 20:26:04 2008 +1000
+
+ radeon: overhaul ring interactions
+
+ emit in 16-dword blocks, emit irqs at same time as everything else
+
+commit b7f75f50040569ad8187cc5b3c97a7ef806ec513
+Author: Dave Airlie <airlied at redhat.com>
+Date: Tue Oct 28 16:49:09 2008 +1000
+
+ radeon: fix race in sysfs
+
+commit 1a26da2f878bc6bf52676e35676bc5034cd9a9fe
+Author: Dave Airlie <airlied at redhat.com>
+Date: Tue Oct 28 16:46:47 2008 +1000
+
+ radeon: add proc debugging for interrupts/ring
+
+commit a50011a833c6bc3c1437376cb5d106d45250aeb5
+Author: Dave Airlie <airlied at redhat.com>
+Date: Tue Oct 28 16:44:54 2008 +1000
+
+ radeon: only enable dynclks if asked for
+
commit 927236acfb2a745d42c2f70c9099bdf664b2e26b
Author: Dave Airlie <airlied at redhat.com>
Date: Tue Oct 28 06:35:10 2008 +1000
@@ -12674,7 +12712,7 @@
unsigned shift, nr;
unsigned start;
diff --git a/drivers/gpu/drm/radeon/Makefile b/drivers/gpu/drm/radeon/Makefile
-index feb521e..f611328 100644
+index feb521e..5d6bc6c 100644
--- a/drivers/gpu/drm/radeon/Makefile
+++ b/drivers/gpu/drm/radeon/Makefile
@@ -3,7 +3,11 @@
@@ -12686,7 +12724,7 @@
+ radeon_gem.o radeon_buffer.o radeon_fence.o radeon_cs.o \
+ radeon_i2c.o radeon_fb.o radeon_encoders.o radeon_connectors.o radeon_display.o \
+ atombios_crtc.o atom.o radeon_atombios.o radeon_combios.o radeon_legacy_crtc.o \
-+ radeon_legacy_encoders.o radeon_cursor.o radeon_pm.o
++ radeon_legacy_encoders.o radeon_cursor.o radeon_pm.o radeon_gem_proc.o
radeon-$(CONFIG_COMPAT) += radeon_ioc32.o
@@ -20938,10 +20976,10 @@
+}
diff --git a/drivers/gpu/drm/radeon/radeon_buffer.c b/drivers/gpu/drm/radeon/radeon_buffer.c
new file mode 100644
-index 0000000..e88378a
+index 0000000..571a0b9
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_buffer.c
-@@ -0,0 +1,446 @@
+@@ -0,0 +1,452 @@
+/**************************************************************************
+ *
+ * Copyright 2007 Dave Airlie
@@ -21114,10 +21152,12 @@
+ ADVANCE_RING();
+ }
+
-+ BEGIN_RING(4);
++ BEGIN_RING(6);
+ OUT_RING(CP_PACKET0(RADEON_RB2D_DSTCACHE_CTLSTAT, 0));
+ OUT_RING(RADEON_RB2D_DC_FLUSH_ALL);
+ RADEON_WAIT_UNTIL_2D_IDLE();
++ OUT_RING(CP_PACKET2());
++ OUT_RING(CP_PACKET2());
+ ADVANCE_RING();
+
+ COMMIT_RING();
@@ -21209,10 +21249,14 @@
+ ADVANCE_RING();
+ }
+
-+ BEGIN_RING(4);
++ BEGIN_RING(8);
+ OUT_RING(CP_PACKET0(RADEON_RB2D_DSTCACHE_CTLSTAT, 0));
+ OUT_RING(RADEON_RB2D_DC_FLUSH_ALL);
+ RADEON_WAIT_UNTIL_2D_IDLE();
++ OUT_RING(CP_PACKET2());
++ OUT_RING(CP_PACKET2());
++ OUT_RING(CP_PACKET2());
++ OUT_RING(CP_PACKET2());
+ ADVANCE_RING();
+
+ COMMIT_RING();
@@ -23176,7 +23220,7 @@
+ return NULL;
+}
diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c
-index 59a2132..0d62c65 100644
+index 59a2132..2be65a5 100644
--- a/drivers/gpu/drm/radeon/radeon_cp.c
+++ b/drivers/gpu/drm/radeon/radeon_cp.c
@@ -31,6 +31,7 @@
@@ -23436,7 +23480,25 @@
tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
#endif
-@@ -501,15 +652,15 @@ static int radeon_do_engine_reset(struct drm_device * dev)
+@@ -447,10 +598,15 @@ static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
+ BEGIN_RING(8);
+ /* isync can only be written through cp on r5xx write it here */
+ OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
++ if (dev_priv->chip_family > CHIP_RV280)
++ OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
++ RADEON_ISYNC_ANY3D_IDLE2D |
++ RADEON_ISYNC_WAIT_IDLEGUI |
++ dev_priv->mm_enabled ? 0 : RADEON_ISYNC_CPSCRATCH_IDLEGUI);
++ else
+ OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
+ RADEON_ISYNC_ANY3D_IDLE2D |
+- RADEON_ISYNC_WAIT_IDLEGUI |
+- RADEON_ISYNC_CPSCRATCH_IDLEGUI);
++ RADEON_ISYNC_WAIT_IDLEGUI);
+ RADEON_PURGE_CACHE();
+ RADEON_PURGE_ZCACHE();
+ RADEON_WAIT_UNTIL_IDLE();
+@@ -501,15 +657,15 @@ static int radeon_do_engine_reset(struct drm_device * dev)
if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
/* may need something similar for newer chips */
clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
@@ -23461,7 +23523,7 @@
}
rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
-@@ -534,7 +685,7 @@ static int radeon_do_engine_reset(struct drm_device * dev)
+@@ -534,7 +690,7 @@ static int radeon_do_engine_reset(struct drm_device * dev)
RADEON_READ(RADEON_RBBM_SOFT_RESET);
if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
@@ -23470,7 +23532,7 @@
RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
}
-@@ -550,7 +701,8 @@ static int radeon_do_engine_reset(struct drm_device * dev)
+@@ -550,7 +706,8 @@ static int radeon_do_engine_reset(struct drm_device * dev)
dev_priv->cp_running = 0;
/* Reset any pending vertex, indirect buffers */
@@ -23480,7 +23542,7 @@
return 0;
}
-@@ -559,7 +711,6 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
+@@ -559,7 +716,6 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
drm_radeon_private_t * dev_priv)
{
u32 ring_start, cur_read_ptr;
@@ -23488,7 +23550,7 @@
/* Initialize the memory controller. With new memory map, the fb location
* is not changed, it should have been properly initialized already. Part
-@@ -568,9 +719,13 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
+@@ -568,9 +724,13 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
*/
if (!dev_priv->new_memmap)
radeon_write_fb_location(dev_priv,
@@ -23505,7 +23567,7 @@
#if __OS_HAS_AGP
if (dev_priv->flags & RADEON_IS_AGP) {
radeon_write_agp_base(dev_priv, dev->agp->base);
-@@ -578,7 +733,7 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
+@@ -578,7 +738,7 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
radeon_write_agp_location(dev_priv,
(((dev_priv->gart_vm_start - 1 +
dev_priv->gart_size) & 0xffff0000) |
@@ -23514,7 +23576,7 @@
ring_start = (dev_priv->cp_ring->offset
- dev->agp->base
-@@ -600,6 +755,12 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
+@@ -600,6 +760,12 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
SET_RING_HEAD(dev_priv, cur_read_ptr);
dev_priv->ring.tail = cur_read_ptr;
@@ -23527,7 +23589,7 @@
#if __OS_HAS_AGP
if (dev_priv->flags & RADEON_IS_AGP) {
RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
-@@ -646,62 +807,79 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
+@@ -646,62 +812,79 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
+ RADEON_SCRATCH_REG_OFFSET);
@@ -23566,26 +23628,26 @@
+
+ dev_priv->scratch[0] = 0;
+ RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
++
++ dev_priv->scratch[1] = 0;
++ RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
++
++ dev_priv->scratch[2] = 0;
++ RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
- dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
- RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
-+ dev_priv->scratch[1] = 0;
-+ RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
++ dev_priv->scratch[3] = 0;
++ RADEON_WRITE(RADEON_LAST_SWI_REG, 0);
- dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
- RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
- dev_priv->sarea_priv->last_dispatch);
-+ dev_priv->scratch[2] = 0;
-+ RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
++ dev_priv->scratch[4] = 0;
++ RADEON_WRITE(RADEON_SCRATCH_REG4, 0);
- dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
- RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
-+ dev_priv->scratch[3] = 0;
-+ RADEON_WRITE(RADEON_LAST_SWI_REG, 0);
-+
-+ dev_priv->scratch[4] = 0;
-+ RADEON_WRITE(RADEON_SCRATCH_REG4, 0);
-+
+ dev_priv->scratch[6] = 0;
+ RADEON_WRITE(RADEON_SCRATCH_REG6, 0);
@@ -23635,7 +23697,7 @@
0xdeadbeef)
break;
DRM_UDELAY(1);
-@@ -719,10 +897,12 @@ static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
+@@ -719,10 +902,12 @@ static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
DRM_INFO("writeback forced off\n");
}
@@ -23651,7 +23713,7 @@
RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
}
}
-@@ -734,9 +914,9 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
+@@ -734,9 +919,9 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
if (on) {
DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
@@ -23664,7 +23726,7 @@
temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
-@@ -763,13 +943,20 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
+@@ -763,13 +948,20 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
RS480_REQ_TYPE_SNOOP_DIS));
@@ -23689,7 +23751,7 @@
temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
-@@ -780,7 +967,7 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
+@@ -780,7 +972,7 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
break;
DRM_UDELAY(1);
@@ -23698,7 +23760,7 @@
IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
RS480_GART_CACHE_INVALIDATE);
-@@ -790,7 +977,7 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
+@@ -790,7 +982,7 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
break;
DRM_UDELAY(1);
@@ -23707,7 +23769,7 @@
IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
} else {
-@@ -817,7 +1004,7 @@ static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
+@@ -817,7 +1009,7 @@ static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
dev_priv->gart_vm_start +
dev_priv->gart_size - 1);
@@ -23716,7 +23778,7 @@
RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
RADEON_PCIE_TX_GART_EN);
-@@ -828,7 +1015,7 @@ static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
+@@ -828,7 +1020,7 @@ static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
}
/* Enable or disable PCI GART on the chip */
@@ -23725,7 +23787,7 @@
{
u32 tmp;
-@@ -862,7 +1049,7 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
+@@ -862,7 +1054,7 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
/* Turn off AGP aperture -- is this required for PCI GART?
*/
@@ -23734,7 +23796,7 @@
RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
} else {
RADEON_WRITE(RADEON_AIC_CNTL,
-@@ -870,9 +1057,11 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
+@@ -870,9 +1062,11 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
}
}
@@ -23747,7 +23809,7 @@
DRM_DEBUG("\n");
-@@ -910,17 +1099,6 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
+@@ -910,17 +1104,6 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
*/
dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
@@ -23765,7 +23827,7 @@
dev_priv->do_boxes = 0;
dev_priv->cp_mode = init->cp_mode;
-@@ -968,9 +1146,8 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
+@@ -968,9 +1151,8 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
*/
dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
(dev_priv->color_fmt << 10) |
@@ -23777,7 +23839,7 @@
dev_priv->depth_clear.rb3d_zstencilcntl =
(dev_priv->depth_fmt |
RADEON_Z_TEST_ALWAYS |
-@@ -997,8 +1174,8 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
+@@ -997,8 +1179,8 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
dev_priv->buffers_offset = init->buffers_offset;
dev_priv->gart_textures_offset = init->gart_textures_offset;
@@ -23788,7 +23850,7 @@
DRM_ERROR("could not find sarea!\n");
radeon_do_cleanup_cp(dev);
return -EINVAL;
-@@ -1034,10 +1211,6 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
+@@ -1034,10 +1216,6 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
}
}
@@ -23799,7 +23861,7 @@
#if __OS_HAS_AGP
if (dev_priv->flags & RADEON_IS_AGP) {
drm_core_ioremap(dev_priv->cp_ring, dev);
-@@ -1167,28 +1340,41 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
+@@ -1167,28 +1345,41 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
/* if we have an offset set from userspace */
if (dev_priv->pcigart_offset_set) {
@@ -23861,7 +23923,7 @@
if (dev_priv->flags & RADEON_IS_IGPGART)
dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
else
-@@ -1197,12 +1383,7 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
+@@ -1197,12 +1388,7 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
DRM_ATI_GART_MAIN;
dev_priv->gart_info.addr = NULL;
dev_priv->gart_info.bus_addr = 0;
@@ -23875,7 +23937,7 @@
}
if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
-@@ -1215,6 +1396,9 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
+@@ -1215,6 +1401,9 @@ static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
radeon_set_pcigart(dev_priv, 1);
}
@@ -23885,7 +23947,7 @@
radeon_cp_load_microcode(dev_priv);
radeon_cp_init_ring_buffer(dev, dev_priv);
-@@ -1259,14 +1443,16 @@ static int radeon_do_cleanup_cp(struct drm_device * dev)
+@@ -1259,14 +1448,16 @@ static int radeon_do_cleanup_cp(struct drm_device * dev)
if (dev_priv->gart_info.bus_addr) {
/* Turn off PCI GART */
radeon_set_pcigart(dev_priv, 0);
@@ -23906,7 +23968,7 @@
}
}
/* only clear to the start of flags */
-@@ -1318,6 +1504,10 @@ static int radeon_do_resume_cp(struct drm_device * dev)
+@@ -1318,6 +1509,10 @@ static int radeon_do_resume_cp(struct drm_device * dev)
int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
drm_radeon_init_t *init = data;
@@ -23917,7 +23979,7 @@
LOCK_TEST_WITH_RETURN(dev, file_priv);
-@@ -1328,7 +1518,7 @@ int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_pri
+@@ -1328,7 +1523,7 @@ int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_pri
case RADEON_INIT_CP:
case RADEON_INIT_R200_CP:
case RADEON_INIT_R300_CP:
@@ -23926,7 +23988,7 @@
case RADEON_CLEANUP_CP:
return radeon_do_cleanup_cp(dev);
}
-@@ -1341,6 +1531,9 @@ int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_pr
+@@ -1341,6 +1536,9 @@ int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_pr
drm_radeon_private_t *dev_priv = dev->dev_private;
DRM_DEBUG("\n");
@@ -23936,7 +23998,7 @@
LOCK_TEST_WITH_RETURN(dev, file_priv);
if (dev_priv->cp_running) {
-@@ -1368,6 +1561,9 @@ int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_pri
+@@ -1368,6 +1566,9 @@ int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_pri
int ret;
DRM_DEBUG("\n");
@@ -23946,7 +24008,7 @@
LOCK_TEST_WITH_RETURN(dev, file_priv);
if (!dev_priv->cp_running)
-@@ -1406,6 +1602,9 @@ void radeon_do_release(struct drm_device * dev)
+@@ -1406,6 +1607,9 @@ void radeon_do_release(struct drm_device * dev)
drm_radeon_private_t *dev_priv = dev->dev_private;
int i, ret;
@@ -23956,7 +24018,7 @@
if (dev_priv) {
if (dev_priv->cp_running) {
/* Stop the cp */
-@@ -1439,6 +1638,9 @@ void radeon_do_release(struct drm_device * dev)
+@@ -1439,6 +1643,9 @@ void radeon_do_release(struct drm_device * dev)
radeon_mem_takedown(&(dev_priv->gart_heap));
radeon_mem_takedown(&(dev_priv->fb_heap));
@@ -23966,7 +24028,7 @@
/* deallocate kernel resources */
radeon_do_cleanup_cp(dev);
}
-@@ -1451,6 +1653,9 @@ int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_pr
+@@ -1451,6 +1658,9 @@ int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_pr
drm_radeon_private_t *dev_priv = dev->dev_private;
DRM_DEBUG("\n");
@@ -23976,7 +24038,7 @@
LOCK_TEST_WITH_RETURN(dev, file_priv);
if (!dev_priv) {
-@@ -1471,7 +1676,9 @@ int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_pri
+@@ -1471,7 +1681,9 @@ int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_pri
drm_radeon_private_t *dev_priv = dev->dev_private;
DRM_DEBUG("\n");
@@ -23987,7 +24049,7 @@
return radeon_do_cp_idle(dev_priv);
}
-@@ -1481,6 +1688,9 @@ int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_pri
+@@ -1481,6 +1693,9 @@ int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_pri
int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
{
@@ -23997,7 +24059,7 @@
return radeon_do_resume_cp(dev);
}
-@@ -1488,6 +1698,9 @@ int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *fil
+@@ -1488,6 +1703,9 @@ int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *fil
{
DRM_DEBUG("\n");
@@ -24007,7 +24069,7 @@
LOCK_TEST_WITH_RETURN(dev, file_priv);
return radeon_do_engine_reset(dev);
-@@ -1710,6 +1923,709 @@ int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_
+@@ -1710,6 +1928,713 @@ int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_
return ret;
}
@@ -24698,26 +24760,30 @@
+{
+ drm_radeon_private_t *dev_priv = dev->dev_private;
+
-+ if (dev_priv->chip_family == CHIP_RS400 ||
-+ dev_priv->chip_family == CHIP_RS480)
-+ radeon_dynclks = 0;
-+
-+ if ((dev_priv->flags & RADEON_IS_MOBILITY) && !radeon_is_avivo(dev_priv)) {
-+ radeon_set_dynamic_clock(dev, radeon_dynclks);
-+ } else if (radeon_is_avivo(dev_priv)) {
-+ if (radeon_dynclks) {
-+ radeon_atom_static_pwrmgt_setup(dev, 1);
-+ radeon_atom_dyn_clk_setup(dev, 1);
++ if (radeon_dynclks != -1) {
++
++ if (dev_priv->chip_family == CHIP_RS400 ||
++ dev_priv->chip_family == CHIP_RS480)
++ radeon_dynclks = 0;
++
++ if ((dev_priv->flags & RADEON_IS_MOBILITY) && !radeon_is_avivo(dev_priv)) {
++ radeon_set_dynamic_clock(dev, radeon_dynclks);
++ } else if (radeon_is_avivo(dev_priv)) {
++ if (radeon_dynclks) {
++ radeon_atom_static_pwrmgt_setup(dev, 1);
++ radeon_atom_dyn_clk_setup(dev, 1);
++ }
+ }
+ }
-+ radeon_force_some_clocks(dev);
++ if (radeon_is_r300(dev_priv) || radeon_is_rv100(dev_priv))
++ radeon_force_some_clocks(dev);
+ return 0;
+}
+
int radeon_driver_load(struct drm_device *dev, unsigned long flags)
{
drm_radeon_private_t *dev_priv;
-@@ -1723,6 +2639,8 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
+@@ -1723,6 +2648,8 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
dev->dev_private = (void *)dev_priv;
dev_priv->flags = flags;
@@ -24726,7 +24792,7 @@
switch (flags & RADEON_FAMILY_MASK) {
case CHIP_R100:
case CHIP_RV200:
-@@ -1743,6 +2661,14 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
+@@ -1743,6 +2670,14 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
break;
}
@@ -24741,7 +24807,7 @@
if (drm_device_is_agp(dev))
dev_priv->flags |= RADEON_IS_AGP;
else if (drm_device_is_pcie(dev))
-@@ -1752,33 +2678,123 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
+@@ -1752,33 +2687,123 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
DRM_DEBUG("%s card detected\n",
((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
@@ -24880,7 +24946,7 @@
return 0;
}
-@@ -1786,9 +2802,44 @@ int radeon_driver_unload(struct drm_device *dev)
+@@ -1786,9 +2811,44 @@ int radeon_driver_unload(struct drm_device *dev)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -24927,10 +24993,10 @@
+}
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
new file mode 100644
-index 0000000..6ad499b
+index 0000000..302dd93
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
-@@ -0,0 +1,589 @@
+@@ -0,0 +1,609 @@
+/*
+ * Copyright 2008 Jerome Glisse.
+ * All Rights Reserved.
@@ -24971,10 +25037,8 @@
+ struct drm_radeon_cs_chunk __user **chunk_ptr = NULL;
+ uint64_t *chunk_array;
+ uint64_t *chunk_array_ptr;
-+ uint32_t card_offset;
+ long size;
+ int r, i;
-+ RING_LOCALS;
+
+ /* set command stream id to 0 which is fake id */
+ cs_id = 0;
@@ -25077,7 +25141,7 @@
+ }
+
+ /* get ib */
-+ r = dev_priv->cs.ib_get(&parser, &card_offset);
++ r = dev_priv->cs.ib_get(&parser);
+ if (r) {
+ DRM_ERROR("ib_get failed\n");
+ goto out;
@@ -25089,16 +25153,8 @@
+ goto out;
+ }
+
-+ BEGIN_RING(4);
-+ OUT_RING(CP_PACKET0(RADEON_CP_IB_BASE, 1));
-+ OUT_RING(card_offset);
-+ OUT_RING(parser.chunks[parser.ib_index].length_dw);
-+ OUT_RING(CP_PACKET2());
-+ ADVANCE_RING();
-+
+ /* emit cs id sequence */
-+ dev_priv->cs.id_emit(dev, &cs_id);
-+ COMMIT_RING();
++ dev_priv->cs.id_emit(&parser, &cs_id);
+
+ cs->cs_id = cs_id;
+
@@ -25127,7 +25183,6 @@
+ long size;
+ int r;
+ struct drm_radeon_kernel_chunk chunk_fake[1];
-+ RING_LOCALS;
+
+ /* set command stream id to 0 which is fake id */
+ cs_id = 0;
@@ -25171,7 +25226,7 @@
+ parser.reloc_index = -1;
+
+ /* get ib */
-+ r = dev_priv->cs.ib_get(&parser, &card_offset);
++ r = dev_priv->cs.ib_get(&parser);
+ if (r) {
+ DRM_ERROR("ib_get failed\n");
+ goto out;
@@ -25183,15 +25238,8 @@
+ goto out;
+ }
+
-+ BEGIN_RING(4);
-+ OUT_RING(CP_PACKET0(RADEON_CP_IB_BASE, 1));
-+ OUT_RING(card_offset);
-+ OUT_RING(cs->dwords);
-+ OUT_RING(CP_PACKET2());
-+ ADVANCE_RING();
-+
+ /* emit cs id sequence */
-+ dev_priv->cs.id_emit(dev, &cs_id);
++ dev_priv->cs.id_emit(&parser, &cs_id);
+ COMMIT_RING();
+
+ cs->cs_id = cs_id;
@@ -25456,37 +25504,75 @@
+ return (radeon->cs.id_scnt | radeon->cs.id_wcnt);
+}
+
-+void r100_cs_id_emit(struct drm_device *dev, uint32_t *id)
++void r100_cs_id_emit(struct drm_radeon_cs_parser *parser, uint32_t *id)
+{
-+ drm_radeon_private_t *dev_priv = dev->dev_private;
++ drm_radeon_private_t *dev_priv = parser->dev->dev_private;
+ RING_LOCALS;
+
++ dev_priv->irq_emitted = radeon_update_breadcrumb(parser->dev);
+ /* ISYNC_CNTL should have CPSCRACTH bit set */
+ *id = radeon_cs_id_get(dev_priv);
+ /* emit id in SCRATCH4 (not used yet in old drm) */
-+ BEGIN_RING(2);
++ BEGIN_RING(10);
++ OUT_RING(CP_PACKET0(RADEON_CP_IB_BASE, 1));
++ OUT_RING(parser->card_offset);
++ OUT_RING(parser->chunks[parser->ib_index].length_dw);
++ OUT_RING(CP_PACKET2());
+ OUT_RING(CP_PACKET0(RADEON_SCRATCH_REG4, 0));
+ OUT_RING(*id);
++ OUT_RING_REG(RADEON_LAST_SWI_REG, dev_priv->irq_emitted);
++ OUT_RING_REG(RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE);
+ ADVANCE_RING();
++ COMMIT_RING();
++
+}
+
-+void r300_cs_id_emit(struct drm_device *dev, uint32_t *id)
++void r300_cs_id_emit(struct drm_radeon_cs_parser *parser, uint32_t *id)
+{
-+ drm_radeon_private_t *dev_priv = dev->dev_private;
++ drm_radeon_private_t *dev_priv = parser->dev->dev_private;
++ int i;
+ RING_LOCALS;
+
++ dev_priv->irq_emitted = radeon_update_breadcrumb(parser->dev);
++
+ /* ISYNC_CNTL should not have CPSCRACTH bit set */
+ *id = radeon_cs_id_get(dev_priv);
++
+ /* emit id in SCRATCH6 */
-+ BEGIN_RING(8);
-+ OUT_RING(CP_PACKET0(R300_CP_RESYNC_ADDR, 0));
++ BEGIN_RING(16);
++ OUT_RING(CP_PACKET0(RADEON_CP_IB_BASE, 1));
++ OUT_RING(parser->card_offset);
++ OUT_RING(parser->chunks[parser->ib_index].length_dw);
++ OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
++ OUT_RING(0);
++ for (i = 0; i < 11; i++) /* emit fillers like fglrx */
++ OUT_RING(CP_PACKET2());
++ ADVANCE_RING();
++ COMMIT_RING();
++
++ BEGIN_RING(16);
++ OUT_RING_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DC_FLUSH);
++ OUT_RING(CP_PACKET0(R300_CP_RESYNC_ADDR, 1));
+ OUT_RING(6);
-+ OUT_RING(CP_PACKET0(R300_CP_RESYNC_DATA, 0));
+ OUT_RING(*id);
-+ OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
-+ OUT_RING(R300_RB3D_DC_FINISH);
++ OUT_RING_REG(R300_RB3D_DSTCACHE_CTLSTAT, R300_RB3D_DC_FINISH|R300_RB3D_DC_FLUSH);
++ /* emit inline breadcrumb for TTM fencing */
++#if 1
+ RADEON_WAIT_UNTIL_3D_IDLE();
++ OUT_RING_REG(RADEON_LAST_SWI_REG, dev_priv->irq_emitted);
++#else
++ OUT_RING(CP_PACKET0(R300_CP_RESYNC_ADDR, 1));
++ OUT_RING(3); /* breadcrumb register */
++ OUT_RING(dev_priv->irq_emitted);
++ OUT_RING(CP_PACKET2());
++#endif
++ OUT_RING_REG(RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE);
++ OUT_RING(CP_PACKET2());
++ OUT_RING(CP_PACKET2());
++ OUT_RING(CP_PACKET2());
+ ADVANCE_RING();
++ COMMIT_RING();
++
+}
+
+uint32_t r100_cs_id_last_get(struct drm_device *dev)
@@ -26493,17 +26579,17 @@
+ drm_mode_config_cleanup(dev);
+}
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
-index 71af746..e201792 100644
+index 71af746..50e2234 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
-@@ -35,12 +35,28 @@
+@@ -35,53 +35,72 @@
#include "radeon_drv.h"
#include "drm_pciids.h"
+#include <linux/console.h>
int radeon_no_wb;
-+int radeon_dynclks = 1;
++int radeon_dynclks = -1;
+int radeon_r4xx_atom = 0;
+int radeon_agpmode = 0;
@@ -26525,7 +26611,16 @@
static int dri_library_name(struct drm_device *dev, char *buf)
{
drm_radeon_private_t *dev_priv = dev->dev_private;
-@@ -52,36 +68,35 @@ static int dri_library_name(struct drm_device *dev, char *buf)
+- int family = dev_priv->flags & RADEON_FAMILY_MASK;
++ int family;
++
++ if (!dev_priv)
++ return 0;
+
++ family = dev_priv->flags & RADEON_FAMILY_MASK;
+ return snprintf(buf, PAGE_SIZE, "%s\n",
+ (family < CHIP_R200) ? "radeon" :
+ ((family < CHIP_R300) ? "r200" :
"r300"));
}
@@ -26584,7 +26679,7 @@
.dev_priv_size = sizeof(drm_radeon_buf_priv_t),
.load = radeon_driver_load,
.firstopen = radeon_driver_firstopen,
-@@ -104,7 +119,11 @@ static struct drm_driver driver = {
+@@ -104,7 +123,13 @@ static struct drm_driver driver = {
.get_map_ofs = drm_core_get_map_ofs,
.get_reg_ofs = drm_core_get_reg_ofs,
.ioctls = radeon_ioctls,
@@ -26593,10 +26688,12 @@
.dma_ioctl = radeon_cp_buffers,
+ .master_create = radeon_master_create,
+ .master_destroy = radeon_master_destroy,
++ .proc_init = radeon_gem_proc_init,
++ .proc_cleanup = radeon_gem_proc_cleanup,
.fops = {
.owner = THIS_MODULE,
.open = drm_open,
-@@ -123,6 +142,9 @@ static struct drm_driver driver = {
+@@ -123,6 +148,9 @@ static struct drm_driver driver = {
.id_table = pciidlist,
},
@@ -26606,7 +26703,7 @@
.name = DRIVER_NAME,
.desc = DRIVER_DESC,
.date = DRIVER_DATE,
-@@ -134,6 +156,23 @@ static struct drm_driver driver = {
+@@ -134,6 +162,23 @@ static struct drm_driver driver = {
static int __init radeon_init(void)
{
driver.num_ioctls = radeon_max_ioctl;
@@ -26631,7 +26728,7 @@
}
diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
-index 4dbb813..b430917 100644
+index 4dbb813..f924a84 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.h
+++ b/drivers/gpu/drm/radeon/radeon_drv.h
@@ -34,6 +34,8 @@
@@ -26721,7 +26818,7 @@
typedef struct drm_radeon_freelist {
unsigned int age;
-@@ -226,14 +265,86 @@ struct radeon_virt_surface {
+@@ -226,14 +265,87 @@ struct radeon_virt_surface {
#define RADEON_FLUSH_EMITED (1 < 0)
#define RADEON_PURGE_EMITED (1 < 1)
@@ -26774,6 +26871,7 @@
+ struct drm_radeon_kernel_chunk *chunks;
+ int ib_index;
+ int reloc_index;
++ uint32_t card_offset;
+ void *ib;
+};
+
@@ -26785,12 +26883,12 @@
+ uint32_t id_last_scnt;
+
+ int (*parse)(struct drm_radeon_cs_parser *parser);
-+ void (*id_emit)(struct drm_device *dev, uint32_t *id);
++ void (*id_emit)(struct drm_radeon_cs_parser *parser, uint32_t *id);
+ uint32_t (*id_last_get)(struct drm_device *dev);
+ /* this ib handling callback are for hidding memory manager drm
+ * from memory manager less drm, free have to emit ib discard
+ * sequence into the ring */
-+ int (*ib_get)(struct drm_radeon_cs_parser *parser, uint32_t *card_offset);
++ int (*ib_get)(struct drm_radeon_cs_parser *parser);
+ uint32_t (*ib_get_ptr)(struct drm_device *dev, void *ib);
+ void (*ib_free)(struct drm_radeon_cs_parser *parser);
+ /* do a relocation either MM or non-MM */
@@ -26813,7 +26911,7 @@
int gart_size;
u32 gart_vm_start;
unsigned long gart_buffers_offset;
-@@ -249,8 +360,6 @@ typedef struct drm_radeon_private {
+@@ -249,8 +361,6 @@ typedef struct drm_radeon_private {
int usec_timeout;
@@ -26822,7 +26920,7 @@
struct {
u32 boxes;
int freelist_timeouts;
-@@ -286,8 +395,6 @@ typedef struct drm_radeon_private {
+@@ -286,8 +396,6 @@ typedef struct drm_radeon_private {
unsigned long buffers_offset;
unsigned long gart_textures_offset;
@@ -26831,7 +26929,7 @@
drm_local_map_t *cp_ring;
drm_local_map_t *ring_rptr;
drm_local_map_t *gart_textures;
-@@ -296,8 +403,8 @@ typedef struct drm_radeon_private {
+@@ -296,8 +404,8 @@ typedef struct drm_radeon_private {
struct mem_block *fb_heap;
/* SW interrupt */
@@ -26841,7 +26939,7 @@
int vblank_crtc;
uint32_t irq_enable_reg;
int irq_enabled;
-@@ -306,9 +413,6 @@ typedef struct drm_radeon_private {
+@@ -306,9 +414,6 @@ typedef struct drm_radeon_private {
struct radeon_surface surfaces[RADEON_MAX_SURFACES];
struct radeon_virt_surface virt_surfaces[2 * RADEON_MAX_SURFACES];
@@ -26851,7 +26949,7 @@
u32 scratch_ages[5];
-@@ -318,6 +422,39 @@ typedef struct drm_radeon_private {
+@@ -318,6 +423,41 @@ typedef struct drm_radeon_private {
int num_gb_pipes;
int track_flush;
@@ -26888,10 +26986,12 @@
+ struct drm_radeon_cs_priv cs;
+
+ struct radeon_pm_regs pmregs;
++ int irq_emitted;
++ atomic_t irq_received;
} drm_radeon_private_t;
typedef struct drm_radeon_buf_priv {
-@@ -332,8 +469,12 @@ typedef struct drm_radeon_kcmd_buffer {
+@@ -332,8 +472,12 @@ typedef struct drm_radeon_kcmd_buffer {
} drm_radeon_kcmd_buffer_t;
extern int radeon_no_wb;
@@ -26904,7 +27004,7 @@
/* Check whether the given hardware address is inside the framebuffer or the
* GART area.
-@@ -367,12 +508,9 @@ extern struct drm_buf *radeon_freelist_get(struct drm_device * dev);
+@@ -367,12 +511,9 @@ extern struct drm_buf *radeon_freelist_get(struct drm_device * dev);
extern int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n);
@@ -26918,7 +27018,7 @@
extern int radeon_mem_alloc(struct drm_device *dev, void *data, struct drm_file *file_priv);
extern int radeon_mem_free(struct drm_device *dev, void *data, struct drm_file *file_priv);
extern int radeon_mem_init_heap(struct drm_device *dev, void *data, struct drm_file *file_priv);
-@@ -400,16 +538,19 @@ extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
+@@ -400,16 +541,19 @@ extern int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value);
extern int radeon_driver_load(struct drm_device *dev, unsigned long flags);
extern int radeon_driver_unload(struct drm_device *dev);
extern int radeon_driver_firstopen(struct drm_device *dev);
@@ -26942,7 +27042,7 @@
/* r300_cmdbuf.c */
extern void r300_init_reg_flags(struct drm_device *dev);
-@@ -417,6 +558,11 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -417,6 +561,11 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
struct drm_file *file_priv,
drm_radeon_kcmd_buffer_t *cmdbuf);
@@ -26954,7 +27054,7 @@
/* Flags for stats.boxes
*/
#define RADEON_BOX_DMA_IDLE 0x1
-@@ -425,10 +571,14 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -425,10 +574,14 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define RADEON_BOX_WAIT_IDLE 0x8
#define RADEON_BOX_TEXTURE_LOAD 0x10
@@ -26969,7 +27069,7 @@
#define RADEON_AGP_COMMAND 0x0f60
#define RADEON_AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config */
# define RADEON_AGP_ENABLE (1<<8)
-@@ -447,12 +597,12 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -447,12 +600,12 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
* handling, not bus mastering itself.
*/
#define RADEON_BUS_CNTL 0x0030
@@ -26987,7 +27087,7 @@
#define RADEON_BUS_CNTL1 0x0034
# define RADEON_PMI_BM_DIS (1 << 2)
-@@ -554,16 +704,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -554,16 +707,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define R520_MC_IND_WR_EN (1 << 24)
#define R520_MC_IND_DATA 0x74
@@ -27004,7 +27104,7 @@
#define RADEON_MPP_TB_CONFIG 0x01c0
#define RADEON_MEM_CNTL 0x0140
#define RADEON_MEM_SDRAM_MODE_REG 0x0158
-@@ -628,14 +768,23 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -628,14 +771,23 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define RADEON_SCRATCH_REG3 0x15ec
#define RADEON_SCRATCH_REG4 0x15f0
#define RADEON_SCRATCH_REG5 0x15f4
@@ -27031,7 +27131,7 @@
#define RADEON_GEN_INT_CNTL 0x0040
# define RADEON_CRTC_VBLANK_MASK (1 << 0)
-@@ -654,10 +803,11 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -654,10 +806,11 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
# define RADEON_SW_INT_FIRE (1 << 26)
# define R500_DISPLAY_INT_STATUS (1 << 0)
@@ -27047,7 +27147,7 @@
#define RADEON_ISYNC_CNTL 0x1724
# define RADEON_ISYNC_ANY2D_IDLE3D (1 << 0)
-@@ -696,12 +846,17 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -696,12 +849,17 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define RADEON_PP_TXFILTER_1 0x1c6c
#define RADEON_PP_TXFILTER_2 0x1c84
@@ -27071,7 +27171,7 @@
#define RADEON_RB3D_CNTL 0x1c3c
# define RADEON_ALPHA_BLEND_ENABLE (1 << 0)
# define RADEON_PLANE_MASK_ENABLE (1 << 1)
-@@ -728,11 +883,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -728,11 +886,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
# define R300_ZC_FLUSH (1 << 0)
# define R300_ZC_FREE (1 << 1)
# define R300_ZC_BUSY (1 << 31)
@@ -27083,7 +27183,7 @@
#define R300_RB3D_DSTCACHE_CTLSTAT 0x4e4c
# define R300_RB3D_DC_FLUSH (2 << 0)
# define R300_RB3D_DC_FREE (2 << 2)
-@@ -740,15 +890,15 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -740,15 +893,15 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define RADEON_RB3D_ZSTENCILCNTL 0x1c2c
# define RADEON_Z_TEST_MASK (7 << 4)
# define RADEON_Z_TEST_ALWAYS (7 << 4)
@@ -27103,7 +27203,7 @@
#define RADEON_RBBM_SOFT_RESET 0x00f0
# define RADEON_SOFT_RESET_CP (1 << 0)
# define RADEON_SOFT_RESET_HI (1 << 1)
-@@ -937,7 +1087,7 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -937,7 +1090,7 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define RADEON_AIC_CNTL 0x01d0
# define RADEON_PCIGART_TRANSLATE_EN (1 << 0)
@@ -27112,7 +27212,7 @@
#define RADEON_AIC_STAT 0x01d4
#define RADEON_AIC_PT_BASE 0x01d8
#define RADEON_AIC_LO_ADDR 0x01dc
-@@ -1009,27 +1159,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -1009,27 +1162,6 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define RADEON_NUM_VERTICES_SHIFT 16
#define RADEON_COLOR_FORMAT_CI8 2
@@ -27140,7 +27240,7 @@
#define R200_PP_TXCBLEND_0 0x2f00
#define R200_PP_TXCBLEND_1 0x2f10
-@@ -1140,16 +1269,44 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -1140,16 +1272,44 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
@@ -27187,7 +27287,7 @@
#define R500_D1CRTC_STATUS 0x609c
#define R500_D2CRTC_STATUS 0x689c
#define R500_CRTC_V_BLANK (1<<0)
-@@ -1190,19 +1347,36 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
+@@ -1190,19 +1350,36 @@ extern int r300_do_cp_cmdbuf(struct drm_device *dev,
#define RADEON_RING_HIGH_MARK 128
#define RADEON_PCIGART_TABLE_SIZE (32*1024)
@@ -27231,7 +27331,7 @@
#define RADEON_WRITE_PCIE(addr, val) \
do { \
RADEON_WRITE8(RADEON_PCIE_INDEX, \
-@@ -1259,7 +1433,7 @@ do { \
+@@ -1259,7 +1436,7 @@ do { \
#define RADEON_WAIT_UNTIL_2D_IDLE() do { \
OUT_RING( CP_PACKET0( RADEON_WAIT_UNTIL, 0 ) ); \
OUT_RING( (RADEON_WAIT_2D_IDLECLEAN | \
@@ -27240,7 +27340,7 @@
} while (0)
#define RADEON_WAIT_UNTIL_3D_IDLE() do { \
-@@ -1336,8 +1510,9 @@ do { \
+@@ -1336,8 +1513,9 @@ do { \
} while (0)
#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
@@ -27252,7 +27352,7 @@
if ( sarea_priv->last_dispatch >= RADEON_MAX_VB_AGE ) { \
int __ret = radeon_do_cp_idle( dev_priv ); \
if ( __ret ) return __ret; \
-@@ -1443,4 +1618,144 @@ do { \
+@@ -1443,4 +1621,146 @@ do { \
write &= mask; \
} while (0)
@@ -27390,6 +27490,8 @@
+void radeon_init_memory_map(struct drm_device *dev);
+void radeon_enable_bm(struct drm_radeon_private *dev_priv);
+
++extern int radeon_gem_proc_init(struct drm_minor *minor);
++extern void radeon_gem_proc_cleanup(struct drm_minor *minor);
+#define MARK_SAFE 1
+#define MARK_CHECK_OFFSET 2
+#define MARK_CHECK_SCISSOR 3
@@ -29440,10 +29542,10 @@
+MODULE_LICENSE("GPL");
diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c
new file mode 100644
-index 0000000..591ad53
+index 0000000..b662da2
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_fence.c
-@@ -0,0 +1,99 @@
+@@ -0,0 +1,98 @@
+/**************************************************************************
+ *
+ * Copyright 2006 Tungsten Graphics, Inc., Bismarck, ND., USA
@@ -29485,7 +29587,6 @@
+ uint32_t *native_type)
+{
+ struct drm_radeon_private *dev_priv = (struct drm_radeon_private *) dev->dev_private;
-+ RING_LOCALS;
+
+ if (!dev_priv)
+ return -EINVAL;
@@ -29545,10 +29646,10 @@
+
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
new file mode 100644
-index 0000000..f5d6b94
+index 0000000..a785041
--- /dev/null
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
-@@ -0,0 +1,1590 @@
+@@ -0,0 +1,1591 @@
+/*
+ * Copyright 2008 Red Hat Inc.
+ *
@@ -30637,7 +30738,7 @@
+
+#define RADEON_NUM_IB (RADEON_IB_MEMORY / RADEON_IB_SIZE)
+
-+int radeon_gem_ib_get(struct drm_radeon_cs_parser *parser, uint32_t *card_offset)
++int radeon_gem_ib_get(struct drm_radeon_cs_parser *parser)
+{
+ int i, index = -1;
+ int ret;
@@ -30683,8 +30784,8 @@
+ return -EINVAL;
+ }
+
-+ *card_offset = dev_priv->gart_vm_start + dev_priv->ib_objs[index]->bo->offset;
+ parser->ib = dev_priv->ib_objs[index]->kmap.virtual;
++ parser->card_offset = dev_priv->gart_vm_start + dev_priv->ib_objs[index]->bo->offset;
+ dev_priv->ib_alloc_bitmap |= (1 << i);
+ return 0;
+}
@@ -30701,6 +30802,7 @@
+ if (dev_priv->ib_objs[i]->kmap.virtual == parser->ib) {
+ /* emit a fence object */
+ ret = drm_fence_buffer_objects(dev, NULL, 0, NULL, &fence);
++ dev_priv->irq_emitted = 0;
+ if (ret) {
+ drm_putback_buffer_objects(dev);
+ }
@@ -31139,6 +31241,158 @@
+}
+
+
+diff --git a/drivers/gpu/drm/radeon/radeon_gem_proc.c b/drivers/gpu/drm/radeon/radeon_gem_proc.c
+new file mode 100644
+index 0000000..04f5a5f
+--- /dev/null
++++ b/drivers/gpu/drm/radeon/radeon_gem_proc.c
+@@ -0,0 +1,146 @@
++/*
++ * Copyright © 2008 Intel Corporation
++ *
++ * Permission is hereby granted, free of charge, to any person obtaining a
++ * copy of this software and associated documentation files (the "Software"),
++ * to deal in the Software without restriction, including without limitation
++ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
++ * and/or sell copies of the Software, and to permit persons to whom the
++ * Software is furnished to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice (including the next
++ * paragraph) shall be included in all copies or substantial portions of the
++ * Software.
++ *
++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
++ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
++ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
++ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
++ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
++ * IN THE SOFTWARE.
++ *
++ * Authors:
++ * Eric Anholt <eric at anholt.net>
++ * Keith Packard <keithp at keithp.com>
++ *
++ */
++
++#include "drmP.h"
++#include "drm.h"
++#include "radeon_drm.h"
++#include "radeon_drv.h"
++
++
++static int radeon_ring_info(char *buf, char **start, off_t offset,
++ int request, int *eof, void *data)
++{
++ struct drm_minor *minor = (struct drm_minor *) data;
++ struct drm_device *dev = minor->dev;
++ drm_radeon_private_t *dev_priv = dev->dev_private;
++ int len = 0;
++
++ if (offset > DRM_PROC_LIMIT) {
++ *eof = 1;
++ return 0;
++ }
++
++ *start = &buf[offset];
++ *eof = 0;
++ DRM_PROC_PRINT("RADEON_CP_RB_WPTR %08x\n",
++ RADEON_READ(RADEON_CP_RB_WPTR));
++
++ DRM_PROC_PRINT("RADEON_CP_RB_RPTR %08x\n",
++ RADEON_READ(RADEON_CP_RB_RPTR));
++
++
++ if (len > request + offset)
++ return request;
++ *eof = 1;
++ return len - offset;
++}
++
++static int radeon_interrupt_info(char *buf, char **start, off_t offset,
++ int request, int *eof, void *data)
++{
++ struct drm_minor *minor = (struct drm_minor *) data;
++ struct drm_device *dev = minor->dev;
++ drm_radeon_private_t *dev_priv = dev->dev_private;
++ int len = 0;
++
++ if (offset > DRM_PROC_LIMIT) {
++ *eof = 1;
++ return 0;
++ }
++
++ *start = &buf[offset];
++ *eof = 0;
++ DRM_PROC_PRINT("Interrupt enable: %08x\n",
++ RADEON_READ(RADEON_GEN_INT_CNTL));
++
++ if (dev_priv->chip_family >= CHIP_RS690) {
++ DRM_PROC_PRINT("DxMODE_INT_MASK: %08x\n",
++ RADEON_READ(R500_DxMODE_INT_MASK));
++ }
++ DRM_PROC_PRINT("Interrupts received: %d\n",
++ atomic_read(&dev_priv->irq_received));
++ DRM_PROC_PRINT("Current sequence: %d %d\n",
++ READ_BREADCRUMB(dev_priv), RADEON_READ(RADEON_SCRATCH_REG3));
++ DRM_PROC_PRINT("Counter sequence: %d\n",
++ dev_priv->counter);
++ if (dev_priv->chip_family >= CHIP_R300)
++ DRM_PROC_PRINT("CS: %d\n",
++ GET_SCRATCH(6));
++
++
++ if (len > request + offset)
++ return request;
++ *eof = 1;
++ return len - offset;
++}
++
++static struct drm_proc_list {
++ /** file name */
++ const char *name;
++ /** proc callback*/
++ int (*f) (char *, char **, off_t, int, int *, void *);
++} radeon_gem_proc_list[] = {
++ {"radeon_gem_interrupt", radeon_interrupt_info},
++ {"radeon_gem_ring", radeon_ring_info},
++};
++
++
++#define RADEON_GEM_PROC_ENTRIES ARRAY_SIZE(radeon_gem_proc_list)
++
++int radeon_gem_proc_init(struct drm_minor *minor)
++{
++ struct proc_dir_entry *ent;
++ int i, j;
++
++ for (i = 0; i < RADEON_GEM_PROC_ENTRIES; i++) {
++ ent = create_proc_entry(radeon_gem_proc_list[i].name,
++ S_IFREG | S_IRUGO, minor->dev_root);
++ if (!ent) {
++ DRM_ERROR("Cannot create /proc/dri/.../%s\n",
++ radeon_gem_proc_list[i].name);
++ for (j = 0; j < i; j++)
++ remove_proc_entry(radeon_gem_proc_list[i].name,
++ minor->dev_root);
++ return -1;
++ }
++ ent->read_proc = radeon_gem_proc_list[i].f;
++ ent->data = minor;
++ }
++ return 0;
++}
++
++void radeon_gem_proc_cleanup(struct drm_minor *minor)
++{
++ int i;
++
++ if (!minor->dev_root)
++ return;
++
++ for (i = 0; i < RADEON_GEM_PROC_ENTRIES; i++)
++ remove_proc_entry(radeon_gem_proc_list[i].name, minor->dev_root);
++}
diff --git a/drivers/gpu/drm/radeon/radeon_i2c.c b/drivers/gpu/drm/radeon/radeon_i2c.c
new file mode 100644
index 0000000..94a485b
@@ -31342,10 +31596,14 @@
+}
+
diff --git a/drivers/gpu/drm/radeon/radeon_irq.c b/drivers/gpu/drm/radeon/radeon_irq.c
-index 5079f70..34e62ed 100644
+index 5079f70..b4f5d50 100644
--- a/drivers/gpu/drm/radeon/radeon_irq.c
+++ b/drivers/gpu/drm/radeon/radeon_irq.c
-@@ -196,8 +196,10 @@ irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS)
+@@ -193,11 +193,14 @@ irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS)
+ if (!stat)
+ return IRQ_NONE;
+
++ atomic_inc(&dev_priv->irq_received);
stat &= dev_priv->irq_enable_reg;
/* SW interrupt */
@@ -31357,7 +31615,7 @@
/* VBLANK interrupt */
if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS690) {
-@@ -214,14 +216,13 @@ irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS)
+@@ -214,20 +217,23 @@ irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS)
return IRQ_HANDLED;
}
@@ -31366,15 +31624,30 @@
{
drm_radeon_private_t *dev_priv = dev->dev_private;
unsigned int ret;
++ int i;
RING_LOCALS;
- atomic_inc(&dev_priv->swi_emitted);
- ret = atomic_read(&dev_priv->swi_emitted);
-+ ret = radeon_update_breadcrumb(dev);
++ if (!dev_priv->irq_emitted) {
++ ret = radeon_update_breadcrumb(dev);
- BEGIN_RING(4);
- OUT_RING_REG(RADEON_LAST_SWI_REG, ret);
-@@ -238,13 +239,13 @@ static int radeon_wait_irq(struct drm_device * dev, int swi_nr)
+- BEGIN_RING(4);
+- OUT_RING_REG(RADEON_LAST_SWI_REG, ret);
+- OUT_RING_REG(RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE);
+- ADVANCE_RING();
+- COMMIT_RING();
++ BEGIN_RING(4);
++ OUT_RING_REG(RADEON_LAST_SWI_REG, ret);
++ OUT_RING_REG(RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE);
++ ADVANCE_RING();
++ COMMIT_RING();
++ } else
++ ret = dev_priv->irq_emitted;
+
+ return ret;
+ }
+@@ -238,13 +244,13 @@ static int radeon_wait_irq(struct drm_device * dev, int swi_nr)
(drm_radeon_private_t *) dev->dev_private;
int ret = 0;
@@ -31390,7 +31663,7 @@
return ret;
}
-@@ -339,7 +340,6 @@ int radeon_driver_irq_postinstall(struct drm_device *dev)
+@@ -339,7 +345,6 @@ int radeon_driver_irq_postinstall(struct drm_device *dev)
(drm_radeon_private_t *) dev->dev_private;
int ret;
Index: kernel.spec
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/devel/kernel.spec,v
retrieving revision 1.1096
retrieving revision 1.1097
diff -u -r1.1096 -r1.1097
--- kernel.spec 28 Oct 2008 02:12:22 -0000 1.1096
+++ kernel.spec 28 Oct 2008 10:45:51 -0000 1.1097
@@ -1883,6 +1883,9 @@
%kernel_variant_files -k vmlinux %{with_kdump} kdump
%changelog
+* Tue Oct 28 2008 Dave Airlie <airlied at redhat.com>
+- modesetting add some debugging in /proc and pad ring writes
+
* Tue Oct 28 2008 Jeremy Katz <katzj at redhat.com>
- add fix for speaker output on OLPC (#466038)
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