rpms/mesa/devel mesa.spec, 1.238, 1.239 radeon-rewrite.patch, 1.16, 1.17 radeon-fix-r100.patch, 1.1, NONE
Dave Airlie
airlied at fedoraproject.org
Mon Apr 6 10:46:18 UTC 2009
Author: airlied
Update of /cvs/pkgs/rpms/mesa/devel
In directory cvs1.fedora.phx.redhat.com:/tmp/cvs-serv1216
Modified Files:
mesa.spec radeon-rewrite.patch
Removed Files:
radeon-fix-r100.patch
Log Message:
* Mon Apr 06 2009 Dave Airlie <airlied at redhat.com> 7.5-0.7
- rebase to latest radeon-rewrite
Index: mesa.spec
===================================================================
RCS file: /cvs/pkgs/rpms/mesa/devel/mesa.spec,v
retrieving revision 1.238
retrieving revision 1.239
diff -u -r1.238 -r1.239
--- mesa.spec 1 Apr 2009 12:23:39 -0000 1.238
+++ mesa.spec 6 Apr 2009 10:45:46 -0000 1.239
@@ -20,7 +20,7 @@
Summary: Mesa graphics libraries
Name: mesa
Version: 7.5
-Release: 0.6%{?dist}
+Release: 0.7%{?dist}
License: MIT
Group: System Environment/Libraries
URL: http://www.mesa3d.org
@@ -46,7 +46,6 @@
Patch9: intel-revert-vbl.patch
Patch12: mesa-7.1-disable-intel-classic-warn.patch
-Patch13: radeon-fix-r100.patch
BuildRequires: pkgconfig autoconf automake
%if %{with_dri}
@@ -174,7 +173,6 @@
%patch7 -p1 -b .dricore
%patch9 -p1 -b .intel-vbl
%patch12 -p1 -b .intel-nowarn
-%patch13 -p1 -b .r100
# Hack the demos to use installed data files
sed -i 's,../images,%{_libdir}/mesa-demos-data,' progs/demos/*.c
@@ -431,6 +429,9 @@
%{_libdir}/mesa-demos-data
%changelog
+* Mon Apr 06 2009 Dave Airlie <airlied at redhat.com> 7.5-0.7
+- rebase to latest radeon-rewrite
+
* Wed Apr 01 2009 Dave Airlie <airlied at redhat.com> 7.5-0.6
- Build fbo files for r100
radeon-rewrite.patch:
View full diff with command:
/usr/bin/cvs -f diff -kk -u -N -r 1.16 -r 1.17 radeon-rewrite.patch
Index: radeon-rewrite.patch
===================================================================
RCS file: /cvs/pkgs/rpms/mesa/devel/radeon-rewrite.patch,v
retrieving revision 1.16
retrieving revision 1.17
diff -u -r1.16 -r1.17
--- radeon-rewrite.patch 31 Mar 2009 06:07:01 -0000 1.16
+++ radeon-rewrite.patch 6 Apr 2009 10:45:46 -0000 1.17
@@ -125,7 +125,7 @@
##### TARGETS #####
diff --git a/src/mesa/drivers/dri/r200/r200_cmdbuf.c b/src/mesa/drivers/dri/r200/r200_cmdbuf.c
-index e163377..83375c8 100644
+index e163377..3a11a44 100644
--- a/src/mesa/drivers/dri/r200/r200_cmdbuf.c
+++ b/src/mesa/drivers/dri/r200/r200_cmdbuf.c
@@ -38,6 +38,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
@@ -387,18 +387,18 @@
+ if (!rmesa->radeon.radeonScreen->kernel_mm) {
+ OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER, 2);
+ OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810);
-+ OUT_BATCH_RELOC(rmesa->tcl.elt_dma_offset,
-+ rmesa->tcl.elt_dma_bo,
-+ rmesa->tcl.elt_dma_offset,
++ OUT_BATCH_RELOC(rmesa->radeon.tcl.elt_dma_offset,
++ rmesa->radeon.tcl.elt_dma_bo,
++ rmesa->radeon.tcl.elt_dma_offset,
+ RADEON_GEM_DOMAIN_GTT, 0, 0);
+ OUT_BATCH(vertex_count/2);
+ } else {
+ OUT_BATCH_PACKET3(R200_CP_CMD_INDX_BUFFER, 2);
+ OUT_BATCH((0x80 << 24) | (0 << 16) | 0x810);
-+ OUT_BATCH(rmesa->tcl.elt_dma_offset);
++ OUT_BATCH(rmesa->radeon.tcl.elt_dma_offset);
+ OUT_BATCH(vertex_count/2);
+ radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
-+ rmesa->tcl.elt_dma_bo,
++ rmesa->radeon.tcl.elt_dma_bo,
+ RADEON_GEM_DOMAIN_GTT, 0, 0);
+ }
+ END_BATCH();
@@ -431,14 +431,14 @@
- */
- rmesa->store.cmd_used = (rmesa->store.cmd_used + 2) & ~2;
- dwords = (rmesa->store.cmd_used - rmesa->store.elts_start) / 4;
-+ radeon_bo_unmap(rmesa->tcl.elt_dma_bo);
++ radeon_bo_unmap(rmesa->radeon.tcl.elt_dma_bo);
- cmd[1] |= (dwords - 3) << 16;
- cmd[2] |= nr << R200_VF_VERTEX_NUMBER_SHIFT;
+ r200FireEB(rmesa, nr, rmesa->tcl.hw_primitive);
+
-+ radeon_bo_unref(rmesa->tcl.elt_dma_bo);
-+ rmesa->tcl.elt_dma_bo = NULL;
++ radeon_bo_unref(rmesa->radeon.tcl.elt_dma_bo);
++ rmesa->radeon.tcl.elt_dma_bo = NULL;
if (R200_DEBUG & DEBUG_SYNC) {
fprintf(stderr, "%s: Syncing\n", __FUNCTION__);
@@ -471,14 +471,14 @@
- R200_VF_COLOR_ORDER_RGBA);
+ radeonEmitState(&rmesa->radeon);
+
-+ rmesa->tcl.elt_dma_bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom,
++ rmesa->radeon.tcl.elt_dma_bo = radeon_bo_open(rmesa->radeon.radeonScreen->bom,
+ 0, R200_ELT_BUF_SZ, 4,
+ RADEON_GEM_DOMAIN_GTT, 0);
-+ rmesa->tcl.elt_dma_offset = 0;
++ rmesa->radeon.tcl.elt_dma_offset = 0;
+ rmesa->tcl.elt_used = min_nr * 2;
-+ radeon_bo_map(rmesa->tcl.elt_dma_bo, 1);
-+ retval = rmesa->tcl.elt_dma_bo->ptr + rmesa->tcl.elt_dma_offset;
++ radeon_bo_map(rmesa->radeon.tcl.elt_dma_bo, 1);
++ retval = rmesa->radeon.tcl.elt_dma_bo->ptr + rmesa->radeon.tcl.elt_dma_offset;
- retval = (GLushort *)(cmd+3);
@@ -578,22 +578,22 @@
+
+ if (!rmesa->radeon.radeonScreen->kernel_mm) {
+ for (i = 0; i + 1 < nr; i += 2) {
-+ OUT_BATCH((rmesa->tcl.aos[i].components << 0) |
-+ (rmesa->tcl.aos[i].stride << 8) |
-+ (rmesa->tcl.aos[i + 1].components << 16) |
-+ (rmesa->tcl.aos[i + 1].stride << 24));
++ OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) |
++ (rmesa->radeon.tcl.aos[i].stride << 8) |
++ (rmesa->radeon.tcl.aos[i + 1].components << 16) |
++ (rmesa->radeon.tcl.aos[i + 1].stride << 24));
+
-+ voffset = rmesa->tcl.aos[i + 0].offset +
-+ offset * 4 * rmesa->tcl.aos[i + 0].stride;
++ voffset = rmesa->radeon.tcl.aos[i + 0].offset +
++ offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
+ OUT_BATCH_RELOC(voffset,
-+ rmesa->tcl.aos[i].bo,
++ rmesa->radeon.tcl.aos[i].bo,
+ voffset,
+ RADEON_GEM_DOMAIN_GTT,
+ 0, 0);
-+ voffset = rmesa->tcl.aos[i + 1].offset +
-+ offset * 4 * rmesa->tcl.aos[i + 1].stride;
++ voffset = rmesa->radeon.tcl.aos[i + 1].offset +
++ offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
+ OUT_BATCH_RELOC(voffset,
-+ rmesa->tcl.aos[i+1].bo,
++ rmesa->radeon.tcl.aos[i+1].bo,
+ voffset,
+ RADEON_GEM_DOMAIN_GTT,
+ 0, 0);
@@ -605,57 +605,57 @@
- offset * component[i]->aos_stride * 4);
+
+ if (nr & 1) {
-+ OUT_BATCH((rmesa->tcl.aos[nr - 1].components << 0) |
-+ (rmesa->tcl.aos[nr - 1].stride << 8));
-+ voffset = rmesa->tcl.aos[nr - 1].offset +
-+ offset * 4 * rmesa->tcl.aos[nr - 1].stride;
++ OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) |
++ (rmesa->radeon.tcl.aos[nr - 1].stride << 8));
++ voffset = rmesa->radeon.tcl.aos[nr - 1].offset +
++ offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
+ OUT_BATCH_RELOC(voffset,
-+ rmesa->tcl.aos[nr - 1].bo,
++ rmesa->radeon.tcl.aos[nr - 1].bo,
+ voffset,
+ RADEON_GEM_DOMAIN_GTT,
+ 0, 0);
+ }
+ } else {
+ for (i = 0; i + 1 < nr; i += 2) {
-+ OUT_BATCH((rmesa->tcl.aos[i].components << 0) |
-+ (rmesa->tcl.aos[i].stride << 8) |
-+ (rmesa->tcl.aos[i + 1].components << 16) |
-+ (rmesa->tcl.aos[i + 1].stride << 24));
++ OUT_BATCH((rmesa->radeon.tcl.aos[i].components << 0) |
++ (rmesa->radeon.tcl.aos[i].stride << 8) |
++ (rmesa->radeon.tcl.aos[i + 1].components << 16) |
++ (rmesa->radeon.tcl.aos[i + 1].stride << 24));
+
-+ voffset = rmesa->tcl.aos[i + 0].offset +
-+ offset * 4 * rmesa->tcl.aos[i + 0].stride;
++ voffset = rmesa->radeon.tcl.aos[i + 0].offset +
++ offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
+ OUT_BATCH(voffset);
-+ voffset = rmesa->tcl.aos[i + 1].offset +
-+ offset * 4 * rmesa->tcl.aos[i + 1].stride;
++ voffset = rmesa->radeon.tcl.aos[i + 1].offset +
++ offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
+ OUT_BATCH(voffset);
+ }
+
+ if (nr & 1) {
-+ OUT_BATCH((rmesa->tcl.aos[nr - 1].components << 0) |
-+ (rmesa->tcl.aos[nr - 1].stride << 8));
-+ voffset = rmesa->tcl.aos[nr - 1].offset +
-+ offset * 4 * rmesa->tcl.aos[nr - 1].stride;
++ OUT_BATCH((rmesa->radeon.tcl.aos[nr - 1].components << 0) |
++ (rmesa->radeon.tcl.aos[nr - 1].stride << 8));
++ voffset = rmesa->radeon.tcl.aos[nr - 1].offset +
++ offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
+ OUT_BATCH(voffset);
+ }
+ for (i = 0; i + 1 < nr; i += 2) {
-+ voffset = rmesa->tcl.aos[i + 0].offset +
-+ offset * 4 * rmesa->tcl.aos[i + 0].stride;
++ voffset = rmesa->radeon.tcl.aos[i + 0].offset +
++ offset * 4 * rmesa->radeon.tcl.aos[i + 0].stride;
+ radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
-+ rmesa->tcl.aos[i+0].bo,
++ rmesa->radeon.tcl.aos[i+0].bo,
+ RADEON_GEM_DOMAIN_GTT,
+ 0, 0);
-+ voffset = rmesa->tcl.aos[i + 1].offset +
-+ offset * 4 * rmesa->tcl.aos[i + 1].stride;
++ voffset = rmesa->radeon.tcl.aos[i + 1].offset +
++ offset * 4 * rmesa->radeon.tcl.aos[i + 1].stride;
+ radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
-+ rmesa->tcl.aos[i+1].bo,
++ rmesa->radeon.tcl.aos[i+1].bo,
+ RADEON_GEM_DOMAIN_GTT,
+ 0, 0);
+ }
+ if (nr & 1) {
-+ voffset = rmesa->tcl.aos[nr - 1].offset +
-+ offset * 4 * rmesa->tcl.aos[nr - 1].stride;
++ voffset = rmesa->radeon.tcl.aos[nr - 1].offset +
++ offset * 4 * rmesa->radeon.tcl.aos[nr - 1].stride;
+ radeon_cs_write_reloc(rmesa->radeon.cmdbuf.cs,
-+ rmesa->tcl.aos[nr-1].bo,
++ rmesa->radeon.tcl.aos[nr-1].bo,
+ RADEON_GEM_DOMAIN_GTT,
+ 0, 0);
}
@@ -732,7 +732,7 @@
+ END_BATCH();
}
diff --git a/src/mesa/drivers/dri/r200/r200_context.c b/src/mesa/drivers/dri/r200/r200_context.c
-index c067515..564e168 100644
[...4610 lines suppressed...]
@@ -42,6 +42,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
@@ -33533,13 +33766,13 @@
- radeonEnsureCmdBufSpace(rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) +
- rmesa->hw.max_state_size + ELTS_BUFSZ(nr));
+ rcommonEnsureCmdBufSpace(&rmesa->radeon, rmesa->radeon.hw.max_state_size + ELTS_BUFSZ(nr) +
-+ AOS_BUFSZ(rmesa->tcl.nr_aos_components), __FUNCTION__);
++ AOS_BUFSZ(rmesa->radeon.tcl.aos_count), __FUNCTION__);
- radeonEmitAOS( rmesa,
- rmesa->tcl.aos_components,
- rmesa->tcl.nr_aos_components, 0 );
+ radeonEmitAOS( rmesa,
-+ rmesa->tcl.nr_aos_components, 0 );
++ rmesa->radeon.tcl.aos_count, 0 );
- return radeonAllocEltsOpenEnded( rmesa,
- rmesa->tcl.vertex_format,
@@ -33553,7 +33786,7 @@
-@@ -174,14 +173,14 @@ static void radeonEmitPrim( GLcontext *ctx,
+@@ -174,15 +173,15 @@ static void radeonEmitPrim( GLcontext *ctx,
GLuint start,
GLuint count)
{
@@ -33564,14 +33797,16 @@
- radeonEnsureCmdBufSpace( rmesa, AOS_BUFSZ(rmesa->tcl.nr_aos_components) +
- rmesa->hw.max_state_size + VBUF_BUFSZ );
+ rcommonEnsureCmdBufSpace( &rmesa->radeon,
-+ AOS_BUFSZ(rmesa->tcl.nr_aos_components) +
++ AOS_BUFSZ(rmesa->radeon.tcl.aos_count) +
+ rmesa->radeon.hw.max_state_size + VBUF_BUFSZ, __FUNCTION__ );
radeonEmitAOS( rmesa,
- rmesa->tcl.aos_components,
- rmesa->tcl.nr_aos_components,
+- rmesa->tcl.nr_aos_components,
++ rmesa->radeon.tcl.aos_count,
start );
+ /* Why couldn't this packet have taken an offset param?
@@ -254,7 +253,7 @@ void radeonTclPrimitive( GLcontext *ctx,
GLenum prim,
int hw_prim )
@@ -33664,7 +33899,7 @@
if (RADEON_DEBUG & DEBUG_FALLBACKS)
fprintf(stderr, "Radeon end tcl fallback %s\n",
diff --git a/src/mesa/drivers/dri/radeon/radeon_tex.c b/src/mesa/drivers/dri/radeon/radeon_tex.c
-index b0aec21..2dfb504 100644
+index b0aec21..21509c6 100644
--- a/src/mesa/drivers/dri/radeon/radeon_tex.c
+++ b/src/mesa/drivers/dri/radeon/radeon_tex.c
@@ -44,6 +44,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
@@ -34232,7 +34467,7 @@
GLuint unit = ctx->Texture.CurrentUnit;
rmesa->recheck_texgen[unit] = GL_TRUE;
}
-@@ -846,17 +424,27 @@ static void radeonTexGen( GLcontext *ctx,
+@@ -846,29 +424,40 @@ static void radeonTexGen( GLcontext *ctx,
static struct gl_texture_object *
radeonNewTextureObject( GLcontext *ctx, GLuint name, GLenum target )
{
@@ -34267,8 +34502,9 @@
+
void radeonInitTextureFuncs( struct dd_function_table *functions )
{
- functions->ChooseTextureFormat = radeonChooseTextureFormat;
-@@ -864,11 +452,12 @@ void radeonInitTextureFuncs( struct dd_function_table *functions )
+- functions->ChooseTextureFormat = radeonChooseTextureFormat;
++ functions->ChooseTextureFormat = radeonChooseTextureFormat_mesa;
+ functions->TexImage1D = radeonTexImage1D;
functions->TexImage2D = radeonTexImage2D;
functions->TexSubImage1D = radeonTexSubImage1D;
functions->TexSubImage2D = radeonTexSubImage2D;
@@ -34730,7 +34966,7 @@
- return 0;
-}
diff --git a/src/mesa/drivers/dri/radeon/radeon_texstate.c b/src/mesa/drivers/dri/radeon/radeon_texstate.c
-index b165205..dab0df0 100644
+index b165205..e4df337 100644
--- a/src/mesa/drivers/dri/radeon/radeon_texstate.c
+++ b/src/mesa/drivers/dri/radeon/radeon_texstate.c
@@ -39,10 +39,12 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
@@ -35129,7 +35365,7 @@
+ texImage->RowStride = rb->pitch / rb->cpp;
+ texImage->TexFormat = radeonChooseTextureFormat(radeon->glCtx,
+ internalFormat,
-+ type, format);
++ type, format, 0);
+ rImage->bo = rb->bo;
+ radeon_bo_ref(rImage->bo);
+ t->bo = rb->bo;
@@ -35706,10 +35942,10 @@
}
diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c b/src/mesa/drivers/dri/radeon/radeon_texture.c
new file mode 100644
-index 0000000..21529f6
+index 0000000..35ed542
--- /dev/null
+++ b/src/mesa/drivers/dri/radeon/radeon_texture.c
-@@ -0,0 +1,987 @@
+@@ -0,0 +1,996 @@
+/*
+ * Copyright (C) 2008 Nicolai Haehnle.
+ * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
@@ -35969,13 +36205,13 @@
+/* try to find a format which will only need a memcopy */
+static const struct gl_texture_format *radeonChoose8888TexFormat(radeonContextPtr rmesa,
+ GLenum srcFormat,
-+ GLenum srcType)
++ GLenum srcType, GLboolean fbo)
+{
+ const GLuint ui = 1;
+ const GLubyte littleEndian = *((const GLubyte *)&ui);
+
+ /* r100 can only do this */
-+ if (IS_R100_CLASS(rmesa->radeonScreen))
++ if (IS_R100_CLASS(rmesa->radeonScreen) || fbo)
+ return _dri_texformat_argb8888;
+
+ if ((srcFormat == GL_RGBA && srcType == GL_UNSIGNED_INT_8_8_8_8) ||
@@ -36000,11 +36236,20 @@
+ return _dri_texformat_argb8888;
+}
+
-+const struct gl_texture_format *radeonChooseTextureFormat(GLcontext * ctx,
++const struct gl_texture_format *radeonChooseTextureFormat_mesa(GLcontext * ctx,
+ GLint internalFormat,
+ GLenum format,
+ GLenum type)
+{
++ return radeonChooseTextureFormat(ctx, internalFormat, format,
++ type, 0);
++}
++
++const struct gl_texture_format *radeonChooseTextureFormat(GLcontext * ctx,
++ GLint internalFormat,
++ GLenum format,
++ GLenum type, GLboolean fbo)
++{
+ radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
+ const GLboolean do32bpt =
+ (rmesa->texture_depth == DRI_CONF_TEXTURE_DEPTH_32);
@@ -36035,7 +36280,7 @@
+ case GL_UNSIGNED_SHORT_1_5_5_5_REV:
+ return _dri_texformat_argb1555;
+ default:
-+ return do32bpt ? radeonChoose8888TexFormat(rmesa, format, type) :
++ return do32bpt ? radeonChoose8888TexFormat(rmesa, format, type, fbo) :
+ _dri_texformat_argb4444;
+ }
+
@@ -36062,7 +36307,7 @@
+ case GL_RGBA12:
+ case GL_RGBA16:
+ return !force16bpt ?
-+ radeonChoose8888TexFormat(rmesa, format,type) :
++ radeonChoose8888TexFormat(rmesa, format, type, fbo) :
+ _dri_texformat_argb4444;
+
+ case GL_RGBA4:
@@ -36222,7 +36467,7 @@
+ }
+
+ /* Choose and fill in the texture format for this image */
-+ texImage->TexFormat = radeonChooseTextureFormat(ctx, internalFormat, format, type);
++ texImage->TexFormat = radeonChooseTextureFormat(ctx, internalFormat, format, type, 0);
+ _mesa_set_fetch_functions(texImage, dims);
+
+ if (texImage->TexFormat->TexelBytes == 0) {
@@ -36699,10 +36944,10 @@
+}
diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.h b/src/mesa/drivers/dri/radeon/radeon_texture.h
new file mode 100644
-index 0000000..d90fda7
+index 0000000..888a55b
--- /dev/null
+++ b/src/mesa/drivers/dri/radeon/radeon_texture.h
-@@ -0,0 +1,118 @@
+@@ -0,0 +1,122 @@
+/*
+ * Copyright (C) 2008 Nicolai Haehnle.
+ * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
@@ -36745,10 +36990,14 @@
+void radeonGenerateMipmap(GLcontext* ctx, GLenum target, struct gl_texture_object *texObj);
+int radeon_validate_texture_miptree(GLcontext * ctx, struct gl_texture_object *texObj);
+GLuint radeon_face_for_target(GLenum target);
-+const struct gl_texture_format *radeonChooseTextureFormat(GLcontext * ctx,
++const struct gl_texture_format *radeonChooseTextureFormat_mesa(GLcontext * ctx,
+ GLint internalFormat,
+ GLenum format,
+ GLenum type);
++const struct gl_texture_format *radeonChooseTextureFormat(GLcontext * ctx,
++ GLint internalFormat,
++ GLenum format,
++ GLenum type, GLboolean fbo);
+
+void radeonTexImage1D(GLcontext * ctx, GLenum target, GLint level,
+ GLint internalFormat,
--- radeon-fix-r100.patch DELETED ---
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