rpms/kernel/devel drm-nouveau.patch, 1.7, 1.8 kernel.spec, 1.1285, 1.1286
Ben Skeggs
bskeggs at fedoraproject.org
Wed Feb 11 04:35:14 UTC 2009
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Author: bskeggs
Update of /cvs/pkgs/rpms/kernel/devel
In directory cvs1.fedora.phx.redhat.com:/tmp/cvs-serv7414
Modified Files:
drm-nouveau.patch kernel.spec
Log Message:
nouveau update
drm-nouveau.patch:
View full diff with command:
/usr/bin/cvs -f diff -kk -u -N -r 1.7 -r 1.8 drm-nouveau.patch
Index: drm-nouveau.patch
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/devel/drm-nouveau.patch,v
retrieving revision 1.7
retrieving revision 1.8
diff -u -r1.7 -r1.8
--- drm-nouveau.patch 6 Feb 2009 23:46:10 -0000 1.7
+++ drm-nouveau.patch 11 Feb 2009 04:35:13 -0000 1.8
@@ -45,9 +45,27 @@
static int drm_map_handle(struct drm_device *dev, struct drm_hash_item *hash,
unsigned long user_token, int hashed_handle)
+diff --git a/drivers/gpu/drm/drm_drv.c b/drivers/gpu/drm/drm_drv.c
+index c6ade45..969b372 100644
+--- a/drivers/gpu/drm/drm_drv.c
++++ b/drivers/gpu/drm/drm_drv.c
+@@ -327,11 +327,10 @@ static void drm_cleanup(struct drm_device * dev)
+ dev->agp = NULL;
+ }
+
+- drm_ht_remove(&dev->map_hash);
+- drm_ctxbitmap_cleanup(dev);
+-
+ list_for_each_entry_safe(r_list, list_temp, &dev->maplist, head)
+ drm_rmmap(dev, r_list->map);
++ drm_ht_remove(&dev->map_hash);
++ drm_ctxbitmap_cleanup(dev);
+
+ if (drm_core_check_feature(dev, DRIVER_MODESET))
+ drm_put_minor(&dev->control);
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
new file mode 100644
-index 0000000..384c3b5
+index 0000000..d8a32e0
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -0,0 +1,24 @@
@@ -70,14 +88,14 @@
+ nv04_instmem.o nv50_instmem.o \
+ nv50_crtc.o nv50_dac.o nv50_sor.o nv50_connector.o \
+ nv50_lut.o nv50_cursor.o nv50_i2c.o nv50_display.o \
-+ nv50_fbcon.o
++ nv50_fbcon.o nv50_fbcon_accel.o
+
+nouveau-$(CONFIG_COMPAT) += nouveau_ioc32.o
+
+obj-$(CONFIG_DRM_NOUVEAU)+= nouveau.o
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c
new file mode 100644
-index 0000000..faa2b2b
+index 0000000..bcbedb7
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.c
@@ -0,0 +1,854 @@
@@ -152,20 +170,20 @@
+ int i;
+
+ /* enable access to rom */
-+ NV_WRITE(NV04_PBUS_PCI_NV_20, NV04_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED);
++ nv_wr32(NV04_PBUS_PCI_NV_20, NV04_PBUS_PCI_NV_20_ROM_SHADOW_DISABLED);
+
+ /* This is also valid for pre-NV50, it just happened to be the only define already present. */
+ for (i=0; i < NV50_PROM__ESIZE; i++) {
+ /* Appearantly needed for a 6600GT/6800LE bug. */
-+ data[i] = DRM_READ8(dev_priv->mmio, NV50_PROM + i);
-+ data[i] = DRM_READ8(dev_priv->mmio, NV50_PROM + i);
-+ data[i] = DRM_READ8(dev_priv->mmio, NV50_PROM + i);
-+ data[i] = DRM_READ8(dev_priv->mmio, NV50_PROM + i);
-+ data[i] = DRM_READ8(dev_priv->mmio, NV50_PROM + i);
++ data[i] = nv_rd08(NV50_PROM + i);
++ data[i] = nv_rd08(NV50_PROM + i);
++ data[i] = nv_rd08(NV50_PROM + i);
++ data[i] = nv_rd08(NV50_PROM + i);
++ data[i] = nv_rd08(NV50_PROM + i);
+ }
+
+ /* disable access to rom */
-+ NV_WRITE(NV04_PBUS_PCI_NV_20, NV04_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
++ nv_wr32(NV04_PBUS_PCI_NV_20, NV04_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
+}
+
+static void nv_shadow_bios_ramin(struct drm_device *dev, uint8_t *data)
@@ -176,20 +194,20 @@
+
+ /* Move the bios copy to the start of ramin? */
+ if (dev_priv->card_type >= NV_50) {
-+ uint32_t vbios_vram = (NV_READ(0x619f04) & ~0xff) << 8;
++ uint32_t vbios_vram = (nv_rd32(0x619f04) & ~0xff) << 8;
+
+ if (!vbios_vram)
-+ vbios_vram = (NV_READ(0x1700) << 16) + 0xf0000;
++ vbios_vram = (nv_rd32(0x1700) << 16) + 0xf0000;
+
-+ old_bar0_pramin = NV_READ(0x1700);
-+ NV_WRITE(0x1700, vbios_vram >> 16);
++ old_bar0_pramin = nv_rd32(0x1700);
++ nv_wr32(0x1700, vbios_vram >> 16);
+ }
+
+ for (i=0; i < NV50_PROM__ESIZE; i++)
-+ data[i] = DRM_READ8(dev_priv->mmio, NV04_PRAMIN + i);
++ data[i] = nv_rd08(NV04_PRAMIN + i);
+
+ if (dev_priv->card_type >= NV_50)
-+ NV_WRITE(0x1700, old_bar0_pramin);
++ nv_wr32(0x1700, old_bar0_pramin);
+}
+
+static bool nv_shadow_bios(struct drm_device *dev, uint8_t *data)
@@ -723,7 +741,7 @@
+ if (bios->chip_version > 0x10 && bios->chip_version != 0x15 &&
+ bios->chip_version != 0x1a && bios->chip_version != 0x20)
+ crystal_strap_mask |= 1 << 22;
-+ crystal_straps = NV_READ(NV50_PEXTDEV + 0x0) & crystal_strap_mask;
++ crystal_straps = nv_rd32(NV50_PEXTDEV + 0x0) & crystal_strap_mask;
+
+ switch (pll_lim_ver) {
+ /* we use version 0 to indicate a pre limit table bios (single stage pll)
@@ -1488,7 +1506,7 @@
+};
diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.c b/drivers/gpu/drm/nouveau/nouveau_dma.c
new file mode 100644
-index 0000000..e8afda8
+index 0000000..276575a
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_dma.c
@@ -0,0 +1,202 @@
@@ -1640,8 +1658,8 @@
+ return 0;
+}
+
-+#define READ_GET() ((NV_READ(chan->get) - chan->pushbuf_base) >> 2)
-+#define WRITE_PUT(val) NV_WRITE(chan->put, ((val) << 2) + chan->pushbuf_base)
++#define READ_GET() ((nv_rd32(chan->get) - chan->pushbuf_base) >> 2)
++#define WRITE_PUT(val) nv_wr32(chan->put, ((val) << 2) + chan->pushbuf_base)
+
+int
+nouveau_dma_wait(struct nouveau_channel *chan, int size)
@@ -1696,10 +1714,10 @@
+}
diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.h b/drivers/gpu/drm/nouveau/nouveau_dma.h
new file mode 100644
-index 0000000..424716d
+index 0000000..076baf6
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_dma.h
-@@ -0,0 +1,103 @@
+@@ -0,0 +1,105 @@
+/*
+ * Copyright (C) 2007 Ben Skeggs.
+ * All Rights Reserved.
@@ -1731,13 +1749,15 @@
+
+typedef enum {
+ NvSubM2MF = 0,
++ NvSub2D = 1
+} nouveau_subchannel_id_t;
+
+typedef enum {
+ NvM2MF = 0x80000001,
+ NvDmaFB = 0x80000002,
+ NvDmaTT = 0x80000003,
-+ NvNotify0 = 0x80000004
++ NvNotify0 = 0x80000004,
++ Nv2D = 0x80000005,
+} nouveau_object_handle_t;
+
+#define NV_MEMORY_TO_MEMORY_FORMAT 0x00000039
@@ -1794,12 +1814,12 @@
+
+ DRM_MEMORYBARRIER();
+ chan->dma.put = chan->dma.cur;
-+ NV_WRITE(chan->put, (chan->dma.put << 2) + chan->pushbuf_base);
++ nv_wr32(chan->put, (chan->dma.put << 2) + chan->pushbuf_base);
+}
+
+/* This should allow easy switching to a real fifo in the future. */
+#define OUT_MODE(mthd, val) do { \
-+ nv50_display_command(dev_priv, mthd, val); \
++ nv50_display_command(dev, mthd, val); \
+} while(0)
+
+#endif
@@ -1938,10 +1958,10 @@
+MODULE_LICENSE("GPL and additional rights");
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
new file mode 100644
-index 0000000..f209614
+index 0000000..dc212cc
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
-@@ -0,0 +1,704 @@
+@@ -0,0 +1,712 @@
+/*
+ * Copyright 2005 Stephane Marchesin.
+ * All Rights Reserved.
@@ -2626,29 +2646,37 @@
+ struct drm_file *);
+
+#if defined(__powerpc__)
[...7933 lines suppressed...]
+ if (val & 1)
+ *clock_high = 1;
@@ -31573,10 +35065,10 @@
+#endif /* __NV50_I2C_H__ */
diff --git a/drivers/gpu/drm/nouveau/nv50_instmem.c b/drivers/gpu/drm/nouveau/nv50_instmem.c
new file mode 100644
-index 0000000..b7a51f0
+index 0000000..e89df2e
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nv50_instmem.c
-@@ -0,0 +1,324 @@
+@@ -0,0 +1,331 @@
+/*
+ * Copyright (C) 2007 Ben Skeggs.
+ *
@@ -31630,7 +35122,7 @@
+ offset += (g)->im_pramin->start; \
+ } \
+ offset += (o); \
-+ NV_WRITE(NV_RAMIN + (offset & 0xfffff), (v)); \
++ nv_wr32(NV_RAMIN + (offset & 0xfffff), (v)); \
+} while(0)
+
+int
@@ -31650,7 +35142,7 @@
+
+ /* Save state, will restore at takedown. */
+ for (i = 0x1700; i <= 0x1710; i+=4)
-+ priv->save1700[(i-0x1700)/4] = NV_READ(i);
++ priv->save1700[(i-0x1700)/4] = nv_rd32(i);
+
+ /* Reserve the last MiB of VRAM, we should probably try to avoid
+ * setting up the below tables over the top of the VBIOS image at
@@ -31665,12 +35157,12 @@
+ pt_size = NV50_INSTMEM_PT_SIZE(dev_priv->ramin->size);
+
+ DRM_DEBUG(" Rsvd VRAM base: 0x%08x\n", c_offset);
-+ DRM_DEBUG(" VBIOS image: 0x%08x\n", (NV_READ(0x619f04)&~0xff)<<8);
++ DRM_DEBUG(" VBIOS image: 0x%08x\n", (nv_rd32(0x619f04)&~0xff)<<8);
+ DRM_DEBUG(" Aperture size: %d MiB\n",
+ (uint32_t)dev_priv->ramin->size >> 20);
+ DRM_DEBUG(" PT size: %d KiB\n", pt_size >> 10);
+
-+ NV_WRITE(NV50_PUNK_BAR0_PRAMIN, (c_offset >> 16));
++ nv_wr32(NV50_PUNK_BAR0_PRAMIN, (c_offset >> 16));
+
+ /* Create a fake channel, and use it as our "dummy" channels 0/127.
+ * The main reason for creating a channel is so we can use the gpuobj
@@ -31745,18 +35237,18 @@
+ BAR0_WI32(priv->pramin_bar->gpuobj, 0x14, 0x00000000);
+
+ /* Poke the relevant regs, and pray it works :) */
-+ NV_WRITE(NV50_PUNK_BAR_CFG_BASE, (chan->ramin->instance >> 12));
-+ NV_WRITE(NV50_PUNK_UNK1710, 0);
-+ NV_WRITE(NV50_PUNK_BAR_CFG_BASE, (chan->ramin->instance >> 12) |
++ nv_wr32(NV50_PUNK_BAR_CFG_BASE, (chan->ramin->instance >> 12));
++ nv_wr32(NV50_PUNK_UNK1710, 0);
++ nv_wr32(NV50_PUNK_BAR_CFG_BASE, (chan->ramin->instance >> 12) |
+ NV50_PUNK_BAR_CFG_BASE_VALID);
-+ NV_WRITE(NV50_PUNK_BAR1_CTXDMA, 0);
-+ NV_WRITE(NV50_PUNK_BAR3_CTXDMA, (priv->pramin_bar->instance >> 4) |
++ nv_wr32(NV50_PUNK_BAR1_CTXDMA, 0);
++ nv_wr32(NV50_PUNK_BAR3_CTXDMA, (priv->pramin_bar->instance >> 4) |
+ NV50_PUNK_BAR3_CTXDMA_VALID);
+
+ /* Assume that praying isn't enough, check that we can re-read the
+ * entire fake channel back from the PRAMIN BAR */
+ for (i = 0; i < c_size; i+=4) {
-+ if (NV_READ(NV_RAMIN + i) != NV_RI32(i)) {
++ if (nv_rd32(NV_RAMIN + i) != nv_ri32(i)) {
+ DRM_ERROR("Error reading back PRAMIN at 0x%08x\n", i);
+ return -EINVAL;
+ }
@@ -31791,7 +35283,7 @@
+
+ /* Restore state from before init */
+ for (i = 0x1700; i <= 0x1710; i+=4)
-+ NV_WRITE(i, priv->save1700[(i-0x1700)/4]);
++ nv_wr32(i, priv->save1700[(i-0x1700)/4]);
+
+ nouveau_gpuobj_ref_del(dev, &priv->pramin_bar);
+ nouveau_gpuobj_ref_del(dev, &priv->pramin_pt);
@@ -31876,6 +35368,13 @@
+ vram += NV50_INSTMEM_PAGE_SIZE;
+ }
+
++ nv_wr32(0x070000, 0x00000001);
++ while(nv_rd32(0x070000) & 1);
++ nv_wr32(0x100c80, 0x00040001);
++ while(nv_rd32(0x100c80) & 1);
++ nv_wr32(0x100c80, 0x00060001);
++ while(nv_rd32(0x100c80) & 1);
++
+ gpuobj->im_bound = 1;
+ return 0;
+}
@@ -31903,10 +35402,10 @@
+}
diff --git a/drivers/gpu/drm/nouveau/nv50_lut.c b/drivers/gpu/drm/nouveau/nv50_lut.c
new file mode 100644
-index 0000000..f2b8150
+index 0000000..a3ed2f8
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nv50_lut.c
-@@ -0,0 +1,182 @@
+@@ -0,0 +1,178 @@
+/*
+ * Copyright (C) 2008 Maarten Maathuis.
+ * All Rights Reserved.
@@ -31986,10 +35485,6 @@
+
+ DRM_DEBUG("\n");
+
-+ DRM_INFO("%p %p %p %p %p %p\n", crtc->lut, crtc->lut->bo,
-+ crtc->lut->kmap.virtual, red, green, blue);
-+ return 0;
-+
+ if (!crtc->lut || !crtc->lut->bo) {
+ DRM_ERROR("Something wrong with the LUT\n");
+ return -EINVAL;
@@ -32143,7 +35638,7 @@
+#endif /* __NV50_LUT_H__ */
diff --git a/drivers/gpu/drm/nouveau/nv50_mc.c b/drivers/gpu/drm/nouveau/nv50_mc.c
new file mode 100644
-index 0000000..b111826
+index 0000000..0843473
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nv50_mc.c
@@ -0,0 +1,43 @@
@@ -32182,7 +35677,7 @@
+{
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+
-+ NV_WRITE(NV03_PMC_ENABLE, 0xFFFFFFFF);
++ nv_wr32(NV03_PMC_ENABLE, 0xFFFFFFFF);
+
+ return 0;
+}
@@ -32250,7 +35745,7 @@
+#endif /* __NV50_OUTPUT_H__ */
diff --git a/drivers/gpu/drm/nouveau/nv50_sor.c b/drivers/gpu/drm/nouveau/nv50_sor.c
new file mode 100644
-index 0000000..544af86
+index 0000000..f4b6499
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nv50_sor.c
@@ -0,0 +1,217 @@
@@ -32304,7 +35799,7 @@
+static int nv50_sor_execute_mode(struct nv50_output *output, bool disconnect)
+{
+ struct drm_encoder *drm_encoder = &output->base;
-+ struct drm_nouveau_private *dev_priv = drm_encoder->dev->dev_private;
++ struct drm_device *dev = drm_encoder->dev;
+ struct nv50_crtc *crtc = to_nv50_crtc(drm_encoder->crtc);
+ struct drm_display_mode *desired_mode = NULL;
+ uint32_t offset = output->or * 0x40;
@@ -32365,7 +35860,7 @@
+
+ /* 0x70000 was a late addition to nv, mentioned as fixing tmds initialisation on certain gpu's. */
+ /* I presume it's some kind of clock setting, but what precisely i do not know. */
-+ NV_WRITE(NV50_PDISPLAY_SOR_CLK_CLK_CTRL2(output->or), 0x70000 | ((mode->clock > limit) ? 0x101 : 0));
++ nv_wr32(NV50_PDISPLAY_SOR_CLK_CLK_CTRL2(output->or), 0x70000 | ((mode->clock > limit) ? 0x101 : 0));
+
+ return 0;
+}
@@ -32379,16 +35874,16 @@
+ DRM_DEBUG("or %d\n", output->or);
+
+ /* wait for it to be done */
-+ while (NV_READ(NV50_PDISPLAY_SOR_REGS_DPMS_CTRL(or)) & NV50_PDISPLAY_SOR_REGS_DPMS_CTRL_PENDING);
++ while (nv_rd32(NV50_PDISPLAY_SOR_REGS_DPMS_CTRL(or)) & NV50_PDISPLAY_SOR_REGS_DPMS_CTRL_PENDING);
+
-+ val = NV_READ(NV50_PDISPLAY_SOR_REGS_DPMS_CTRL(or));
++ val = nv_rd32(NV50_PDISPLAY_SOR_REGS_DPMS_CTRL(or));
+
+ if (mode == DRM_MODE_DPMS_ON)
+ val |= NV50_PDISPLAY_SOR_REGS_DPMS_CTRL_ON;
+ else
+ val &= ~NV50_PDISPLAY_SOR_REGS_DPMS_CTRL_ON;
+
-+ NV_WRITE(NV50_PDISPLAY_SOR_REGS_DPMS_CTRL(or), val | NV50_PDISPLAY_SOR_REGS_DPMS_CTRL_PENDING);
++ nv_wr32(NV50_PDISPLAY_SOR_REGS_DPMS_CTRL(or), val | NV50_PDISPLAY_SOR_REGS_DPMS_CTRL_PENDING);
+
+ return 0;
+}
@@ -32463,10 +35958,10 @@
+ if (output->base.encoder_type == DRM_MODE_ENCODER_TMDS) {
+ int or = output->or;
+
-+ NV_WRITE(NV50_PDISPLAY_SOR_REGS_UNK_00C(or), 0x03010700);
-+ NV_WRITE(NV50_PDISPLAY_SOR_REGS_UNK_010(or), 0x0000152f);
-+ NV_WRITE(NV50_PDISPLAY_SOR_REGS_UNK_014(or), 0x00000000);
-+ NV_WRITE(NV50_PDISPLAY_SOR_REGS_UNK_018(or), 0x00245af8);
++ nv_wr32(NV50_PDISPLAY_SOR_REGS_UNK_00C(or), 0x03010700);
++ nv_wr32(NV50_PDISPLAY_SOR_REGS_UNK_010(or), 0x0000152f);
++ nv_wr32(NV50_PDISPLAY_SOR_REGS_UNK_014(or), 0x00000000);
++ nv_wr32(NV50_PDISPLAY_SOR_REGS_UNK_018(or), 0x00245af8);
+ }
+
+ return 0;
Index: kernel.spec
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/devel/kernel.spec,v
retrieving revision 1.1285
retrieving revision 1.1286
diff -u -r1.1285 -r1.1286
--- kernel.spec 10 Feb 2009 18:28:18 -0000 1.1285
+++ kernel.spec 11 Feb 2009 04:35:13 -0000 1.1286
@@ -1749,6 +1749,9 @@
%kernel_variant_files -k vmlinux %{with_kdump} kdump
%changelog
+* Wed Feb 11 2009 Ben Skeggs <bskeggs at redhat.com>
+- nouveau update: GeForce 9 support, kms fixes improvements
+
* Tue Feb 10 2009 Jarod Wilson <jarod at redhat.com> 2.6.29-0.105.rc4.git1
- Enhance kernel's bumpspecfile.py to add VR to changelog when it can
- Previous message: rpms/gparted/devel .cvsignore, 1.18, 1.19 gparted.spec, 1.45, 1.46 sources, 1.18, 1.19
- Next message: rpms/kernel/F-10 drm-nouveau.patch, 1.8, 1.9 kernel.spec, 1.1254, 1.1255
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