rpms/kernel/F-12 patch-2.6.32.9-rc1.bz2.sign, NONE, 1.1 .cvsignore, 1.1147, 1.1148 kernel.spec, 1.2019, 1.2020 linux-2.6-upstream-reverts.patch, 1.8, 1.9 sources, 1.1105, 1.1106 upstream, 1.1019, 1.1020 fix-conntrack-bug-with-namespaces.patch, 1.1, NONE fix-crash-with-sys_move_pages.patch, 1.2, NONE fix-race-in-tty_fasync-properly.patch, 1.1, NONE futex-handle-futex-value-corruption-gracefully.patch, 1.1, NONE futex-handle-user-space-corruption-gracefully.patch, 1.1, NONE futex_lock_pi-key-refcnt-fix.patch, 1.1, NONE prevent-runtime-conntrack-changes.patch, 1.1, NONE wmi-check-wmi-get-event-data-return-value.patch, 1.1, NONE wmi-free-the-allocated-acpi-objects.patch, 1.1, NONE
Chuck Ebbert
cebbert at fedoraproject.org
Mon Feb 22 07:36:06 UTC 2010
Author: cebbert
Update of /cvs/pkgs/rpms/kernel/F-12
In directory cvs1.fedora.phx.redhat.com:/tmp/cvs-serv12275
Modified Files:
.cvsignore kernel.spec linux-2.6-upstream-reverts.patch
sources upstream
Added Files:
patch-2.6.32.9-rc1.bz2.sign
Removed Files:
fix-conntrack-bug-with-namespaces.patch
fix-crash-with-sys_move_pages.patch
fix-race-in-tty_fasync-properly.patch
futex-handle-futex-value-corruption-gracefully.patch
futex-handle-user-space-corruption-gracefully.patch
futex_lock_pi-key-refcnt-fix.patch
prevent-runtime-conntrack-changes.patch
wmi-check-wmi-get-event-data-return-value.patch
wmi-free-the-allocated-acpi-objects.patch
Log Message:
Linux 2.6.32.9-rc1
Revert the 14 DRM patches from 2.6.32.9: we already have them
Drop other patches merged upstream:
wmi-check-wmi-get-event-data-return-value.patch
wmi-free-the-allocated-acpi-objects.patch
fix-conntrack-bug-with-namespaces.patch
prevent-runtime-conntrack-changes.patch
fix-crash-with-sys_move_pages.patch
futex-handle-futex-value-corruption-gracefully.patch
futex-handle-user-space-corruption-gracefully.patch
futex_lock_pi-key-refcnt-fix.patch
fix-race-in-tty_fasync-properly.patch
--- NEW FILE patch-2.6.32.9-rc1.bz2.sign ---
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.9 (GNU/Linux)
Comment: See http://www.kernel.org/signature.html for info
iD8DBQBLfryLyGugalF9Dw4RArKfAJ41ECCl2c0cvWMgAG0nChmn6IurrQCfYf2t
jxpCHzxhv1iTYC2EaeNZ04E=
=TOW2
-----END PGP SIGNATURE-----
Index: .cvsignore
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/F-12/.cvsignore,v
retrieving revision 1.1147
retrieving revision 1.1148
diff -u -p -r1.1147 -r1.1148
--- .cvsignore 9 Feb 2010 13:46:06 -0000 1.1147
+++ .cvsignore 22 Feb 2010 07:36:03 -0000 1.1148
@@ -6,3 +6,4 @@ temp-*
kernel-2.6.32
linux-2.6.32.tar.bz2
patch-2.6.32.8.bz2
+patch-2.6.32.9-rc1.bz2
Index: kernel.spec
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/F-12/kernel.spec,v
retrieving revision 1.2019
retrieving revision 1.2020
diff -u -p -r1.2019 -r1.2020
--- kernel.spec 18 Feb 2010 20:13:23 -0000 1.2019
+++ kernel.spec 22 Feb 2010 07:36:05 -0000 1.2020
@@ -40,9 +40,9 @@ Summary: The Linux kernel
%if 0%{?released_kernel}
# Do we have a -stable update to apply?
-%define stable_update 8
+%define stable_update 9
# Is it a -stable RC?
-%define stable_rc 0
+%define stable_rc 1
# Set rpm version accordingly
%if 0%{?stable_update}
%define stablerev .%{stable_update}
@@ -746,31 +746,18 @@ Patch12011: linux-2.6-block-silently-err
Patch12013: linux-2.6-rfkill-all.patch
Patch12020: linux-2.6-cantiga-iommu-gfx.patch
-# Patches for -stable
-Patch12101: wmi-free-the-allocated-acpi-objects.patch
-Patch12102: wmi-check-wmi-get-event-data-return-value.patch
-
Patch12200: add-appleir-usb-driver.patch
-Patch12301: fix-conntrack-bug-with-namespaces.patch
-Patch12302: prevent-runtime-conntrack-changes.patch
+# Patches for -stable
-Patch12310: fix-crash-with-sys_move_pages.patch
Patch12311: fix-ima-null-ptr-deref.patch
-# cve-2010-0622, cve-2010-0623
-Patch12312: futex-handle-user-space-corruption-gracefully.patch
-Patch12313: futex-handle-futex-value-corruption-gracefully.patch
-Patch12314: futex_lock_pi-key-refcnt-fix.patch
-
Patch12318: fix-abrtd.patch
Patch12319: vgaarb-fix-userspace-ptr-deref.patch
-# cve-2009-4537
+# cve-2009-4537 [not upstream]
Patch12320: linux-2.6-net-r8169-improved-rx-length-check-errors.patch
-Patch12330: fix-race-in-tty_fasync-properly.patch
-
# rhbz#/566565
Patch12340: ice1712-fix-revo71-mixer-names.patch
@@ -1398,28 +1385,15 @@ ApplyPatch linux-2.6-rfkill-all.patch
ApplyPatch add-appleir-usb-driver.patch
# Patches for -stable
-ApplyPatch wmi-free-the-allocated-acpi-objects.patch
-ApplyPatch wmi-check-wmi-get-event-data-return-value.patch
-
-ApplyPatch fix-conntrack-bug-with-namespaces.patch
-ApplyPatch prevent-runtime-conntrack-changes.patch
-ApplyPatch fix-crash-with-sys_move_pages.patch
ApplyPatch fix-ima-null-ptr-deref.patch
-# cve-2010-0622, cve-2010-0623
-ApplyPatch futex-handle-user-space-corruption-gracefully.patch
-ApplyPatch futex-handle-futex-value-corruption-gracefully.patch
-ApplyPatch futex_lock_pi-key-refcnt-fix.patch
-
ApplyPatch fix-abrtd.patch
ApplyPatch vgaarb-fix-userspace-ptr-deref.patch
# cve-2009-4537
ApplyPatch linux-2.6-net-r8169-improved-rx-length-check-errors.patch
-ApplyPatch fix-race-in-tty_fasync-properly.patch
-
# rhbz#566565
ApplyPatch ice1712-fix-revo71-mixer-names.patch
@@ -2078,6 +2052,20 @@ fi
# and build.
%changelog
+* Mon Feb 22 2010 Chuck Ebbert <cebbert at redhat.com> 2.6.32.9-60.rc1
+- Linux 2.6.32.9-rc1
+- Revert the 14 DRM patches from 2.6.32.9: we already have them
+- Drop other patches merged upstream:
+ wmi-check-wmi-get-event-data-return-value.patch
+ wmi-free-the-allocated-acpi-objects.patch
+ fix-conntrack-bug-with-namespaces.patch
+ prevent-runtime-conntrack-changes.patch
+ fix-crash-with-sys_move_pages.patch
+ futex-handle-futex-value-corruption-gracefully.patch
+ futex-handle-user-space-corruption-gracefully.patch
+ futex_lock_pi-key-refcnt-fix.patch
+ fix-race-in-tty_fasync-properly.patch
+
* Thu Feb 18 2010 Kyle McMartin <kyle at redhat.com> 2.6.32.8-59
- ice1712-fix-revo71-mixer-names.patch: fix mixer names for
monty. (rhbz#566565)
linux-2.6-upstream-reverts.patch:
drivers/gpu/drm/i915/i915_debugfs.c | 30 --------
drivers/gpu/drm/i915/i915_drv.h | 13 +++
drivers/gpu/drm/i915/i915_gem.c | 123 +++++++++++++++++++++++++++++++----
drivers/gpu/drm/i915/i915_reg.h | 15 ++++
drivers/gpu/drm/i915/i915_suspend.c | 5 +
drivers/gpu/drm/i915/intel_crt.c | 3
drivers/gpu/drm/i915/intel_display.c | 48 ++++++++++++-
drivers/gpu/drm/i915/intel_drv.h | 2
drivers/gpu/drm/i915/intel_fb.c | 2
drivers/gpu/drm/i915/intel_i2c.c | 19 +++++
drivers/gpu/drm/i915/intel_lvds.c | 23 ++++++
drivers/gpu/drm/radeon/atom.c | 2
include/drm/drm_os_linux.h | 2
13 files changed, 233 insertions(+), 54 deletions(-)
Index: linux-2.6-upstream-reverts.patch
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/F-12/linux-2.6-upstream-reverts.patch,v
retrieving revision 1.8
retrieving revision 1.9
diff -u -p -r1.8 -r1.9
--- linux-2.6-upstream-reverts.patch 17 Feb 2010 04:27:41 -0000 1.8
+++ linux-2.6-upstream-reverts.patch 22 Feb 2010 07:36:05 -0000 1.9
@@ -1 +1,995 @@
+From 01d4503968f471f876fb44335800d2cf8dc5a2ce Mon Sep 17 00:00:00 2001
+From: Dave Airlie <airlied at redhat.com>
+Date: Sun, 31 Jan 2010 07:07:14 +1000
+Subject: drm/radeon/kms: use udelay for short delays
+From: Dave Airlie <airlied at redhat.com>
+
+commit 01d4503968f471f876fb44335800d2cf8dc5a2ce upstream.
+
+For usec delays use udelay instead of scheduling, this should
+allow reclocking to happen faster. This also was the cause
+of reported 33s delays at bootup on certain systems.
+
+fixes: freedesktop.org bug 25506
+
+Signed-off-by: Dave Airlie <airlied at redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh at suse.de>
+
+---
+ drivers/gpu/drm/radeon/atom.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/radeon/atom.c
++++ b/drivers/gpu/drm/radeon/atom.c
+@@ -607,7 +607,7 @@ static void atom_op_delay(atom_exec_cont
+ uint8_t count = U8((*ptr)++);
+ SDEBUG(" count: %d\n", count);
+ if (arg == ATOM_UNIT_MICROSEC)
+- schedule_timeout_uninterruptible(usecs_to_jiffies(count));
++ udelay(count);
+ else
+ schedule_timeout_uninterruptible(msecs_to_jiffies(count));
+ }
+From b9241ea31fae4887104e5d1b3b18f4009c25a0c4 Mon Sep 17 00:00:00 2001
+From: Zhenyu Wang <zhenyuw at linux.intel.com>
+Date: Wed, 25 Nov 2009 13:09:39 +0800
+Subject: drm/i915: Don't wait interruptible for possible plane buffer flush
+
+From: Zhenyu Wang <zhenyuw at linux.intel.com>
+
+commit b9241ea31fae4887104e5d1b3b18f4009c25a0c4 upstream.
+
+When we setup buffer for display plane, we'll check any pending
+required GPU flush and possible make interruptible wait for flush
+complete. But that wait would be most possibly to fail in case of
+signals received for X process, which will then fail modeset process
+and put display engine in unconsistent state. The result could be
+blank screen or CPU hang, and DDX driver would always turn on outputs
+DPMS after whatever modeset fails or not.
+
+So this one creates new helper for setup display plane buffer, and
+when needing flush using uninterruptible wait for that.
+
+This one should fix bug like https://bugs.freedesktop.org/show_bug.cgi?id=24009.
+Also fixing mode switch stress test on Ironlake.
+
+Signed-off-by: Zhenyu Wang <zhenyuw at linux.intel.com>
+Signed-off-by: Eric Anholt <eric at anholt.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh at suse.de>
+
+---
+ drivers/gpu/drm/i915/i915_drv.h | 1
+ drivers/gpu/drm/i915/i915_gem.c | 51 +++++++++++++++++++++++++++++++++++
+ drivers/gpu/drm/i915/intel_display.c | 2 -
+ 3 files changed, 53 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/i915/i915_drv.h
++++ b/drivers/gpu/drm/i915/i915_drv.h
+@@ -829,6 +829,7 @@ int i915_lp_ring_sync(struct drm_device
+ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
+ int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
+ int write);
++int i915_gem_object_set_to_display_plane(struct drm_gem_object *obj);
+ int i915_gem_attach_phys_object(struct drm_device *dev,
+ struct drm_gem_object *obj, int id);
+ void i915_gem_detach_phys_object(struct drm_device *dev,
+--- a/drivers/gpu/drm/i915/i915_gem.c
++++ b/drivers/gpu/drm/i915/i915_gem.c
+@@ -2825,6 +2825,57 @@ i915_gem_object_set_to_gtt_domain(struct
+ return 0;
+ }
+
++/*
++ * Prepare buffer for display plane. Use uninterruptible for possible flush
++ * wait, as in modesetting process we're not supposed to be interrupted.
++ */
++int
++i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
++{
++ struct drm_device *dev = obj->dev;
++ struct drm_i915_gem_object *obj_priv = obj->driver_private;
++ uint32_t old_write_domain, old_read_domains;
++ int ret;
++
++ /* Not valid to be called on unbound objects. */
++ if (obj_priv->gtt_space == NULL)
++ return -EINVAL;
++
++ i915_gem_object_flush_gpu_write_domain(obj);
++
++ /* Wait on any GPU rendering and flushing to occur. */
++ if (obj_priv->active) {
++#if WATCH_BUF
++ DRM_INFO("%s: object %p wait for seqno %08x\n",
++ __func__, obj, obj_priv->last_rendering_seqno);
++#endif
++ ret = i915_do_wait_request(dev, obj_priv->last_rendering_seqno, 0);
++ if (ret != 0)
++ return ret;
++ }
++
++ old_write_domain = obj->write_domain;
++ old_read_domains = obj->read_domains;
++
++ obj->read_domains &= I915_GEM_DOMAIN_GTT;
++
++ i915_gem_object_flush_cpu_write_domain(obj);
++
++ /* It should now be out of any other write domains, and we can update
++ * the domain values for our changes.
++ */
++ BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
++ obj->read_domains |= I915_GEM_DOMAIN_GTT;
++ obj->write_domain = I915_GEM_DOMAIN_GTT;
++ obj_priv->dirty = 1;
++
++ trace_i915_gem_object_change_domain(obj,
++ old_read_domains,
++ old_write_domain);
++
++ return 0;
++}
++
+ /**
+ * Moves a single object to the CPU read, and possibly write domain.
+ *
+--- a/drivers/gpu/drm/i915/intel_display.c
++++ b/drivers/gpu/drm/i915/intel_display.c
+@@ -1253,7 +1253,7 @@ intel_pipe_set_base(struct drm_crtc *crt
+ return ret;
+ }
+
+- ret = i915_gem_object_set_to_gtt_domain(obj, 1);
++ ret = i915_gem_object_set_to_display_plane(obj);
+ if (ret != 0) {
+ i915_gem_object_unpin(obj);
+ mutex_unlock(&dev->struct_mutex);
+From 48764bf43f746113fc77877d7e80f2df23ca4cbb Mon Sep 17 00:00:00 2001
+From: Daniel Vetter <daniel.vetter at ffwll.ch>
+Date: Tue, 15 Sep 2009 22:57:32 +0200
+Subject: drm/i915: add i915_lp_ring_sync helper
+
+From: Daniel Vetter <daniel.vetter at ffwll.ch>
+
+commit 48764bf43f746113fc77877d7e80f2df23ca4cbb upstream.
+
+This just waits until the hw passed the current ring position with
+cmd execution. This slightly changes the existing i915_wait_request
+function to make uninterruptible waiting possible - no point in
+returning to userspace while mucking around with the overlay, that
+piece of hw is just too fragile.
+
+Also replace a magic 0 with the symbolic constant (and kill the then
+superflous comment) while I was looking at the code.
+
+Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
+Signed-off-by: Eric Anholt <eric at anholt.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh at suse.de>
+
+---
+ drivers/gpu/drm/i915/i915_drv.h | 1
+ drivers/gpu/drm/i915/i915_gem.c | 49 +++++++++++++++++++++++++++++++---------
+ include/drm/drm_os_linux.h | 2 -
+ 3 files changed, 41 insertions(+), 11 deletions(-)
+
+--- a/drivers/gpu/drm/i915/i915_drv.h
++++ b/drivers/gpu/drm/i915/i915_drv.h
+@@ -825,6 +825,7 @@ void i915_gem_cleanup_ringbuffer(struct
+ int i915_gem_do_init(struct drm_device *dev, unsigned long start,
+ unsigned long end);
+ int i915_gem_idle(struct drm_device *dev);
++int i915_lp_ring_sync(struct drm_device *dev);
+ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
+ int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
+ int write);
+--- a/drivers/gpu/drm/i915/i915_gem.c
++++ b/drivers/gpu/drm/i915/i915_gem.c
+@@ -1809,12 +1809,8 @@ i915_gem_retire_work_handler(struct work
+ mutex_unlock(&dev->struct_mutex);
+ }
+
+-/**
+- * Waits for a sequence number to be signaled, and cleans up the
+- * request and object lists appropriately for that event.
+- */
+ static int
+-i915_wait_request(struct drm_device *dev, uint32_t seqno)
++i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible)
+ {
+ drm_i915_private_t *dev_priv = dev->dev_private;
+ u32 ier;
+@@ -1841,10 +1837,15 @@ i915_wait_request(struct drm_device *dev
+
+ dev_priv->mm.waiting_gem_seqno = seqno;
+ i915_user_irq_get(dev);
+- ret = wait_event_interruptible(dev_priv->irq_queue,
+- i915_seqno_passed(i915_get_gem_seqno(dev),
+- seqno) ||
+- atomic_read(&dev_priv->mm.wedged));
++ if (interruptible)
++ ret = wait_event_interruptible(dev_priv->irq_queue,
++ i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
++ atomic_read(&dev_priv->mm.wedged));
++ else
++ wait_event(dev_priv->irq_queue,
++ i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
++ atomic_read(&dev_priv->mm.wedged));
++
+ i915_user_irq_put(dev);
+ dev_priv->mm.waiting_gem_seqno = 0;
+
+@@ -1868,6 +1869,34 @@ i915_wait_request(struct drm_device *dev
+ return ret;
+ }
+
++/**
++ * Waits for a sequence number to be signaled, and cleans up the
++ * request and object lists appropriately for that event.
++ */
++static int
++i915_wait_request(struct drm_device *dev, uint32_t seqno)
++{
++ return i915_do_wait_request(dev, seqno, 1);
++}
++
++/**
++ * Waits for the ring to finish up to the latest request. Usefull for waiting
++ * for flip events, e.g for the overlay support. */
++int i915_lp_ring_sync(struct drm_device *dev)
++{
++ uint32_t seqno;
++ int ret;
++
++ seqno = i915_add_request(dev, NULL, 0);
++
++ if (seqno == 0)
++ return -ENOMEM;
++
++ ret = i915_do_wait_request(dev, seqno, 0);
++ BUG_ON(ret == -ERESTARTSYS);
++ return ret;
++}
++
+ static void
+ i915_gem_flush(struct drm_device *dev,
+ uint32_t invalidate_domains,
+@@ -1936,7 +1965,7 @@ i915_gem_flush(struct drm_device *dev,
+ #endif
+ BEGIN_LP_RING(2);
+ OUT_RING(cmd);
+- OUT_RING(0); /* noop */
++ OUT_RING(MI_NOOP);
+ ADVANCE_LP_RING();
+ }
+ }
+--- a/include/drm/drm_os_linux.h
++++ b/include/drm/drm_os_linux.h
+@@ -123,5 +123,5 @@ do { \
+ remove_wait_queue(&(queue), &entry); \
+ } while (0)
+
+-#define DRM_WAKEUP( queue ) wake_up_interruptible( queue )
++#define DRM_WAKEUP( queue ) wake_up( queue )
+ #define DRM_INIT_WAITQUEUE( queue ) init_waitqueue_head( queue )
+From 823f68fd646da6a39a9c0d3eb4c60d69dab5aa13 Mon Sep 17 00:00:00 2001
+From: Zhenyu Wang <zhenyuw at linux.intel.com>
+Date: Mon, 28 Dec 2009 13:23:36 +0800
+Subject: drm/i915: remove full registers dump debug
+
+From: Zhenyu Wang <zhenyuw at linux.intel.com>
+
+commit 823f68fd646da6a39a9c0d3eb4c60d69dab5aa13 upstream.
+
+This one reverts 9e3a6d155ed0a7636b926a798dd7221ea107b274.
+As reported by http://bugzilla.kernel.org/show_bug.cgi?id=14485,
+this dump will cause hang problem on some machine. If something
+really needs this kind of full registers dump, that could be done
+within intel-gpu-tools.
+
+Cc: Ben Gamari <bgamari.foss at gmail.com>
+Signed-off-by: Zhenyu Wang <zhenyuw at linux.intel.com>
+Signed-off-by: Eric Anholt <eric at anholt.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh at suse.de>
+
+
+---
+ drivers/gpu/drm/i915/i915_debugfs.c | 30 ------------------------------
+ 1 file changed, 30 deletions(-)
+
+--- a/drivers/gpu/drm/i915/i915_debugfs.c
++++ b/drivers/gpu/drm/i915/i915_debugfs.c
+@@ -384,37 +384,7 @@ out:
+ return 0;
+ }
+
+-static int i915_registers_info(struct seq_file *m, void *data) {
+- struct drm_info_node *node = (struct drm_info_node *) m->private;
+- struct drm_device *dev = node->minor->dev;
+- drm_i915_private_t *dev_priv = dev->dev_private;
+- uint32_t reg;
+-
+-#define DUMP_RANGE(start, end) \
+- for (reg=start; reg < end; reg += 4) \
+- seq_printf(m, "%08x\t%08x\n", reg, I915_READ(reg));
+-
+- DUMP_RANGE(0x00000, 0x00fff); /* VGA registers */
+- DUMP_RANGE(0x02000, 0x02fff); /* instruction, memory, interrupt control registers */
+- DUMP_RANGE(0x03000, 0x031ff); /* FENCE and PPGTT control registers */
+- DUMP_RANGE(0x03200, 0x03fff); /* frame buffer compression registers */
+- DUMP_RANGE(0x05000, 0x05fff); /* I/O control registers */
+- DUMP_RANGE(0x06000, 0x06fff); /* clock control registers */
+- DUMP_RANGE(0x07000, 0x07fff); /* 3D internal debug registers */
+- DUMP_RANGE(0x07400, 0x088ff); /* GPE debug registers */
+- DUMP_RANGE(0x0a000, 0x0afff); /* display palette registers */
+- DUMP_RANGE(0x10000, 0x13fff); /* MMIO MCHBAR */
+- DUMP_RANGE(0x30000, 0x3ffff); /* overlay registers */
+- DUMP_RANGE(0x60000, 0x6ffff); /* display engine pipeline registers */
+- DUMP_RANGE(0x70000, 0x72fff); /* display and cursor registers */
+- DUMP_RANGE(0x73000, 0x73fff); /* performance counters */
+-
+- return 0;
+-}
+-
+-
+ static struct drm_info_list i915_debugfs_list[] = {
+- {"i915_regs", i915_registers_info, 0},
+ {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
+ {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST},
+ {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
+From 99fcb766a3a50466fe31d743260a3400c1aee855 Mon Sep 17 00:00:00 2001
+From: Daniel Vetter <daniel.vetter at ffwll.ch>
+Date: Sun, 7 Feb 2010 16:20:18 +0100
+Subject: drm/i915: Update write_domains on active list after flush.
+
+From: Daniel Vetter <daniel.vetter at ffwll.ch>
+
+commit 99fcb766a3a50466fe31d743260a3400c1aee855 upstream.
+
+Before changing the status of a buffer with a pending write we will await
+upon a new flush for that buffer. So we can take advantage of any flushes
+posted whilst the buffer is active and pending processing by the GPU, by
+clearing its write_domain and updating its last_rendering_seqno -- thus
+saving a potential flush in deep queues and improves flushing behaviour
+upon eviction for both GTT space and fences.
+
+In order to reduce the time spent searching the active list for matching
+write_domains, we move those to a separate list whose elements are
+the buffers belong to the active/flushing list with pending writes.
+
+Orignal patch by Chris Wilson <chris at chris-wilson.co.uk>, forward-ported
+by me.
+
+In addition to better performance, this also fixes a real bug. Before
+this changes, i915_gem_evict_everything didn't work as advertised. When
+the gpu was actually busy and processing request, the flush and subsequent
+wait would not move active and dirty buffers to the inactive list, but
+just to the flushing list. Which triggered the BUG_ON at the end of this
+function. With the more tight dirty buffer tracking, all currently busy and
+dirty buffers get moved to the inactive list by one i915_gem_flush operation.
+
+I've left the BUG_ON I've used to prove this in there.
+
+References:
+ Bug 25911 - 2.10.0 causes kernel oops and system hangs
+ http://bugs.freedesktop.org/show_bug.cgi?id=25911
+
+ Bug 26101 - [i915] xf86-video-intel 2.10.0 (and git) triggers kernel oops
+ within seconds after login
+ http://bugs.freedesktop.org/show_bug.cgi?id=26101
+
+Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
+Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
+Tested-by: Adam Lantos <hege at playma.org>
+Signed-off-by: Eric Anholt <eric at anholt.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh at suse.de>
+
+---
+ drivers/gpu/drm/i915/i915_drv.h | 11 +++++++++++
+ drivers/gpu/drm/i915/i915_gem.c | 23 +++++++++++++++++++----
+ 2 files changed, 30 insertions(+), 4 deletions(-)
+
+--- a/drivers/gpu/drm/i915/i915_drv.h
++++ b/drivers/gpu/drm/i915/i915_drv.h
+@@ -467,6 +467,15 @@ typedef struct drm_i915_private {
+ struct list_head flushing_list;
+
+ /**
++ * List of objects currently pending a GPU write flush.
++ *
++ * All elements on this list will belong to either the
++ * active_list or flushing_list, last_rendering_seqno can
++ * be used to differentiate between the two elements.
++ */
++ struct list_head gpu_write_list;
++
++ /**
+ * LRU list of objects which are not in the ringbuffer and
+ * are ready to unbind, but are still in the GTT.
+ *
+@@ -558,6 +567,8 @@ struct drm_i915_gem_object {
+
+ /** This object's place on the active/flushing/inactive lists */
+ struct list_head list;
++ /** This object's place on GPU write list */
++ struct list_head gpu_write_list;
+
+ /** This object's place on the fenced object LRU */
+ struct list_head fence_list;
+--- a/drivers/gpu/drm/i915/i915_gem.c
++++ b/drivers/gpu/drm/i915/i915_gem.c
+@@ -1552,6 +1552,8 @@ i915_gem_object_move_to_inactive(struct
+ else
+ list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
+
++ BUG_ON(!list_empty(&obj_priv->gpu_write_list));
++
+ obj_priv->last_rendering_seqno = 0;
+ if (obj_priv->active) {
+ obj_priv->active = 0;
+@@ -1622,7 +1624,8 @@ i915_add_request(struct drm_device *dev,
+ struct drm_i915_gem_object *obj_priv, *next;
+
+ list_for_each_entry_safe(obj_priv, next,
+- &dev_priv->mm.flushing_list, list) {
++ &dev_priv->mm.gpu_write_list,
++ gpu_write_list) {
+ struct drm_gem_object *obj = obj_priv->obj;
+
+ if ((obj->write_domain & flush_domains) ==
+@@ -1630,6 +1633,7 @@ i915_add_request(struct drm_device *dev,
+ uint32_t old_write_domain = obj->write_domain;
+
+ obj->write_domain = 0;
++ list_del_init(&obj_priv->gpu_write_list);
+ i915_gem_object_move_to_active(obj, seqno);
+
+ trace_i915_gem_object_change_domain(obj,
+@@ -2073,8 +2077,8 @@ static int
+ i915_gem_evict_everything(struct drm_device *dev)
+ {
+ drm_i915_private_t *dev_priv = dev->dev_private;
+- uint32_t seqno;
+ int ret;
++ uint32_t seqno;
+ bool lists_empty;
+
+ spin_lock(&dev_priv->mm.active_list_lock);
+@@ -2096,6 +2100,8 @@ i915_gem_evict_everything(struct drm_dev
+ if (ret)
+ return ret;
+
++ BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
++
+ ret = i915_gem_evict_from_inactive_list(dev);
+ if (ret)
+ return ret;
+@@ -2690,7 +2696,7 @@ i915_gem_object_flush_gpu_write_domain(s
+ old_write_domain = obj->write_domain;
+ i915_gem_flush(dev, 0, obj->write_domain);
+ seqno = i915_add_request(dev, NULL, obj->write_domain);
+- obj->write_domain = 0;
++ BUG_ON(obj->write_domain);
+ i915_gem_object_move_to_active(obj, seqno);
+
+ trace_i915_gem_object_change_domain(obj,
+@@ -3710,16 +3716,23 @@ i915_gem_execbuffer(struct drm_device *d
+ i915_gem_flush(dev,
+ dev->invalidate_domains,
+ dev->flush_domains);
+- if (dev->flush_domains)
++ if (dev->flush_domains & I915_GEM_GPU_DOMAINS)
+ (void)i915_add_request(dev, file_priv,
+ dev->flush_domains);
+ }
+
+ for (i = 0; i < args->buffer_count; i++) {
+ struct drm_gem_object *obj = object_list[i];
++ struct drm_i915_gem_object *obj_priv = obj->driver_private;
+ uint32_t old_write_domain = obj->write_domain;
+
+ obj->write_domain = obj->pending_write_domain;
++ if (obj->write_domain)
++ list_move_tail(&obj_priv->gpu_write_list,
++ &dev_priv->mm.gpu_write_list);
++ else
++ list_del_init(&obj_priv->gpu_write_list);
++
+ trace_i915_gem_object_change_domain(obj,
+ obj->read_domains,
+ old_write_domain);
+@@ -4112,6 +4125,7 @@ int i915_gem_init_object(struct drm_gem_
+ obj_priv->obj = obj;
+ obj_priv->fence_reg = I915_FENCE_REG_NONE;
+ INIT_LIST_HEAD(&obj_priv->list);
++ INIT_LIST_HEAD(&obj_priv->gpu_write_list);
+ INIT_LIST_HEAD(&obj_priv->fence_list);
+ obj_priv->madv = I915_MADV_WILLNEED;
+
+@@ -4563,6 +4577,7 @@ i915_gem_load(struct drm_device *dev)
+ spin_lock_init(&dev_priv->mm.active_list_lock);
+ INIT_LIST_HEAD(&dev_priv->mm.active_list);
+ INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
++ INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
+ INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
+ INIT_LIST_HEAD(&dev_priv->mm.request_list);
+ INIT_LIST_HEAD(&dev_priv->mm.fence_list);
+From fd2e8ea597222b8f38ae8948776a61ea7958232e Mon Sep 17 00:00:00 2001
+From: Chris Wilson <chris at chris-wilson.co.uk>
+Date: Tue, 9 Feb 2010 14:14:36 +0000
+Subject: drm/i915: Increase fb alignment to 64k
+
+From: Chris Wilson <chris at chris-wilson.co.uk>
+
+commit fd2e8ea597222b8f38ae8948776a61ea7958232e upstream.
+
+An untiled framebuffer must be aligned to 64k. This is normally handled
+by intel_pin_and_fence_fb_obj(), but the intelfb_create() likes to be
+different and do the pinning itself. However, it aligns the buffer
+object incorrectly for pre-i965 chipsets causing a PGTBL_ERR when it is
+installed onto the output.
+
+Fixes:
+ KMS error message while initializing modesetting -
+ render error detected: EIR: 0x10 [i915]
+ http://bugs.freedesktop.org/show_bug.cgi?id=22936
+
+Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
+Signed-off-by: Eric Anholt <eric at anholt.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh at suse.de>
+
+---
+ drivers/gpu/drm/i915/intel_fb.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/i915/intel_fb.c
++++ b/drivers/gpu/drm/i915/intel_fb.c
+@@ -148,7 +148,7 @@ static int intelfb_create(struct drm_dev
+
+ mutex_lock(&dev->struct_mutex);
+
+- ret = i915_gem_object_pin(fbo, PAGE_SIZE);
++ ret = i915_gem_object_pin(fbo, 64*1024);
+ if (ret) {
+ DRM_ERROR("failed to pin fb: %d\n", ret);
+ goto out_unref;
+From ee25df2bc379728c45d81e04cf87984db1425edf Mon Sep 17 00:00:00 2001
+From: Jesse Barnes <jbarnes at virtuousgeek.org>
+Date: Sat, 6 Feb 2010 10:41:53 -0800
+Subject: drm/i915: handle FBC and self-refresh better
+
+From: Jesse Barnes <jbarnes at virtuousgeek.org>
+
+commit ee25df2bc379728c45d81e04cf87984db1425edf upstream.
+
+On 945, we need to avoid entering self-refresh if the compressor is
+busy, or we may cause display FIFO underruns leading to ugly flicker.
+
+Fixes fdo bug #24314, kernel bug #15043.
+
+Tested-by: Alexander Lam <lambchop468 at gmail.com>
+Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
+Tested-by: Julien Cristau <jcristau at debian.org> (fd.o #25371)
+Signed-off-by: Eric Anholt <eric at anholt.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh at suse.de>
+
+---
+ drivers/gpu/drm/i915/i915_reg.h | 1 +
+ drivers/gpu/drm/i915/intel_display.c | 2 ++
+ 2 files changed, 3 insertions(+)
+
+--- a/drivers/gpu/drm/i915/i915_reg.h
++++ b/drivers/gpu/drm/i915/i915_reg.h
+@@ -329,6 +329,7 @@
+ #define FBC_CTL_PERIODIC (1<<30)
+ #define FBC_CTL_INTERVAL_SHIFT (16)
+ #define FBC_CTL_UNCOMPRESSIBLE (1<<14)
++#define FBC_C3_IDLE (1<<13)
+ #define FBC_CTL_STRIDE_SHIFT (5)
+ #define FBC_CTL_FENCENO (1<<0)
+ #define FBC_COMMAND 0x0320c
+--- a/drivers/gpu/drm/i915/intel_display.c
++++ b/drivers/gpu/drm/i915/intel_display.c
+@@ -988,6 +988,8 @@ static void i8xx_enable_fbc(struct drm_c
+
+ /* enable it... */
+ fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
++ if (IS_I945GM(dev))
++ fbc_ctl |= FBC_C3_IDLE; /* 945 needs special SR handling */
+ fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
+ fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
+ if (obj_priv->tiling_mode != I915_TILING_NONE)
+From a3cb5195f6db58dbebd8a31b877ddce082c9b63d Mon Sep 17 00:00:00 2001
+From: Zhao Yakui <yakui.zhao at intel.com>
+Date: Fri, 11 Dec 2009 09:26:10 +0800
+Subject: drm/i915: Add MALATA PC-81005 to ACPI LID quirk list
+
+From: Zhao Yakui <yakui.zhao at intel.com>
+
+commit a3cb5195f6db58dbebd8a31b877ddce082c9b63d upstream.
+
+The MALATA PC-81005 laptop always reports that the LID status is closed and we
+can't use it reliabily for LVDS detection. So add this box into the quirk list.
+
+https://bugs.freedesktop.org/show_bug.cgi?id=25523
+
+Signed-off-by: Zhao Yakui <yakui.zhao at intel.com>
+Review-by: Jesse Barnes <jbarnes at virtuousgeek.org>
+Tested-by: Hector <hector1987 at gmail.com>
+Signed-off-by: Eric Anholt <eric at anholt.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh at suse.de>
+
+---
+ drivers/gpu/drm/i915/intel_lvds.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/drivers/gpu/drm/i915/intel_lvds.c
++++ b/drivers/gpu/drm/i915/intel_lvds.c
+@@ -622,6 +622,13 @@ static const struct dmi_system_id bad_li
+ DMI_MATCH(DMI_PRODUCT_NAME, "Aspire one"),
+ },
+ },
++ {
++ .ident = "PC-81005",
++ .matches = {
++ DMI_MATCH(DMI_SYS_VENDOR, "MALATA"),
++ DMI_MATCH(DMI_PRODUCT_NAME, "PC-81005"),
++ },
++ },
+ { }
+ };
+
+From f034b12dbb5749b11e9390e15e93ffa87ece8038 Mon Sep 17 00:00:00 2001
+From: Zhao Yakui <yakui.zhao at intel.com>
+Date: Thu, 21 Jan 2010 15:20:18 +0800
+Subject: drm/i915: Fix the incorrect DMI string for Samsung SX20S laptop
+
+From: Zhao Yakui <yakui.zhao at intel.com>
+
+commit f034b12dbb5749b11e9390e15e93ffa87ece8038 upstream.
+
+Signed-off-by: Zhao Yakui <yakui.zhao at intel.com>
+Reported-by: Philipp Kohlbecher <xt28 at gmx.de>
+Signed-off-by: Eric Anholt <eric at anholt.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh at suse.de>
+
+---
+ drivers/gpu/drm/i915/intel_lvds.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/i915/intel_lvds.c
++++ b/drivers/gpu/drm/i915/intel_lvds.c
+@@ -611,7 +611,7 @@ static const struct dmi_system_id bad_li
+ {
+ .ident = "Samsung SX20S",
+ .matches = {
+- DMI_MATCH(DMI_SYS_VENDOR, "Phoenix Technologies LTD"),
++ DMI_MATCH(DMI_SYS_VENDOR, "Samsung Electronics"),
+ DMI_MATCH(DMI_BOARD_NAME, "SX20S"),
+ },
+ },
+From 40f33a92100f4d9b6e85ad642100cfe42d7ff57d Mon Sep 17 00:00:00 2001
+From: Zhao Yakui <yakui.zhao at intel.com>
+Date: Wed, 6 Jan 2010 13:30:36 +0800
+Subject: drm/i915: Add HP nx9020/SamsungSX20S to ACPI LID quirk list
+
+From: Zhao Yakui <yakui.zhao at intel.com>
+
+commit 40f33a92100f4d9b6e85ad642100cfe42d7ff57d upstream.
+
+The HP comaq nx9020/Samsung SX20S laptop always report that the LID status is
+closed and we can't use it reliabily for LVDS detection. So add the two boxes
+into the quirk list.
+
+http://bugzilla.kernel.org/show_bug.cgi?id=14957
+http://bugzilla.kernel.org/show_bug.cgi?id=14554
+
+Signed-off-by: Zhao Yakui <yakui.zhao at intel.com>
+Signed-off-by: Eric Anholt <eric at anholt.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh at suse.de>
+
+---
+ drivers/gpu/drm/i915/intel_lvds.c | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+--- a/drivers/gpu/drm/i915/intel_lvds.c
++++ b/drivers/gpu/drm/i915/intel_lvds.c
+@@ -602,6 +602,20 @@ static void intel_lvds_mode_set(struct d
+ /* Some lid devices report incorrect lid status, assume they're connected */
+ static const struct dmi_system_id bad_lid_status[] = {
+ {
++ .ident = "Compaq nx9020",
++ .matches = {
++ DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
++ DMI_MATCH(DMI_BOARD_NAME, "3084"),
++ },
++ },
++ {
++ .ident = "Samsung SX20S",
++ .matches = {
++ DMI_MATCH(DMI_SYS_VENDOR, "Phoenix Technologies LTD"),
++ DMI_MATCH(DMI_BOARD_NAME, "SX20S"),
++ },
++ },
++ {
+ .ident = "Aspire One",
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
+From f0217c42c9ab3d772e543f635ce628b9478f70b6 Mon Sep 17 00:00:00 2001
+From: Eric Anholt <eric at anholt.net>
+Date: Tue, 1 Dec 2009 11:56:30 -0800
+Subject: drm/i915: Fix DDC on some systems by clearing BIOS GMBUS setup.
+
+From: Eric Anholt <eric at anholt.net>
+
+commit f0217c42c9ab3d772e543f635ce628b9478f70b6 upstream.
+
+This is a sync of a fix I made in the old UMS code. If the BIOS uses
+the GMBUS and doesn't clear that setup, then our bit-banging I2C can
+fail, leading to monitors not being detected.
+
+Signed-off-by: Eric Anholt <eric at anholt.net>
+Cc: maximilian attems <max at stro.at>
+Signed-off-by: Greg Kroah-Hartman <gregkh at suse.de>
+
+---
+ drivers/gpu/drm/i915/i915_reg.h | 14 ++++++++++++++
+ drivers/gpu/drm/i915/i915_suspend.c | 5 ++++-
+ drivers/gpu/drm/i915/intel_drv.h | 2 ++
+ drivers/gpu/drm/i915/intel_i2c.c | 19 +++++++++++++++++++
+ 4 files changed, 39 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/i915/i915_reg.h
++++ b/drivers/gpu/drm/i915/i915_reg.h
+@@ -405,6 +405,13 @@
+ # define GPIO_DATA_VAL_IN (1 << 12)
+ # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
+
++#define GMBUS0 0x5100
++#define GMBUS1 0x5104
++#define GMBUS2 0x5108
++#define GMBUS3 0x510c
++#define GMBUS4 0x5110
++#define GMBUS5 0x5120
++
+ /*
+ * Clock control & power management
+ */
+@@ -2153,6 +2160,13 @@
+ #define PCH_GPIOE 0xc5020
+ #define PCH_GPIOF 0xc5024
+
++#define PCH_GMBUS0 0xc5100
++#define PCH_GMBUS1 0xc5104
++#define PCH_GMBUS2 0xc5108
++#define PCH_GMBUS3 0xc510c
++#define PCH_GMBUS4 0xc5110
++#define PCH_GMBUS5 0xc5120
++
+ #define PCH_DPLL_A 0xc6014
+ #define PCH_DPLL_B 0xc6018
+
+--- a/drivers/gpu/drm/i915/i915_suspend.c
++++ b/drivers/gpu/drm/i915/i915_suspend.c
+@@ -27,7 +27,7 @@
+ #include "drmP.h"
+ #include "drm.h"
+ #include "i915_drm.h"
+-#include "i915_drv.h"
++#include "intel_drv.h"
+
+ static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
+ {
+@@ -846,6 +846,9 @@ int i915_restore_state(struct drm_device
+ for (i = 0; i < 3; i++)
+ I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);
+
++ /* I2C state */
++ intel_i2c_reset_gmbus(dev);
++
+ return 0;
+ }
+
+--- a/drivers/gpu/drm/i915/intel_drv.h
++++ b/drivers/gpu/drm/i915/intel_drv.h
+@@ -134,6 +134,8 @@ void intel_i2c_destroy(struct i2c_adapte
+ int intel_ddc_get_modes(struct intel_output *intel_output);
+ extern bool intel_ddc_probe(struct intel_output *intel_output);
+ void intel_i2c_quirk_set(struct drm_device *dev, bool enable);
++void intel_i2c_reset_gmbus(struct drm_device *dev);
++
+ extern void intel_crt_init(struct drm_device *dev);
+ extern void intel_hdmi_init(struct drm_device *dev, int sdvox_reg);
+ extern bool intel_sdvo_init(struct drm_device *dev, int output_device);
+--- a/drivers/gpu/drm/i915/intel_i2c.c
++++ b/drivers/gpu/drm/i915/intel_i2c.c
+@@ -118,6 +118,23 @@ static void set_data(void *data, int sta
+ udelay(I2C_RISEFALL_TIME); /* wait for the line to change state */
+ }
+
++/* Clears the GMBUS setup. Our driver doesn't make use of the GMBUS I2C
++ * engine, but if the BIOS leaves it enabled, then that can break our use
++ * of the bit-banging I2C interfaces. This is notably the case with the
++ * Mac Mini in EFI mode.
++ */
++void
++intel_i2c_reset_gmbus(struct drm_device *dev)
++{
++ struct drm_i915_private *dev_priv = dev->dev_private;
++
++ if (IS_IGDNG(dev)) {
++ I915_WRITE(PCH_GMBUS0, 0);
++ } else {
++ I915_WRITE(GMBUS0, 0);
++ }
++}
++
+ /**
+ * intel_i2c_create - instantiate an Intel i2c bus using the specified GPIO reg
+ * @dev: DRM device
+@@ -168,6 +185,8 @@ struct i2c_adapter *intel_i2c_create(str
+ if(i2c_bit_add_bus(&chan->adapter))
+ goto out_free;
+
++ intel_i2c_reset_gmbus(dev);
++
+ /* JJJ: raise SCL and SDA? */
+ intel_i2c_quirk_set(dev, true);
+ set_data(chan, 1);
+From 33c5fd121eabbccc9103daf6cda36941eb3c349f Mon Sep 17 00:00:00 2001
+From: David John <davidjon at xenontk.org>
+Date: Wed, 27 Jan 2010 15:19:08 +0530
+Subject: drm/i915: Disable SR when more than one pipe is enabled
+
+From: David John <davidjon at xenontk.org>
+
+commit 33c5fd121eabbccc9103daf6cda36941eb3c349f upstream.
+
+Self Refresh should be disabled on dual plane configs. Otherwise, as
+the SR watermark is not calculated for such configs, switching to non
+VGA mode causes FIFO underrun and display flicker.
+
+This fixes Korg Bug #14897.
+
+Signed-off-by: David John <davidjon at xenontk.org>
+Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
+Signed-off-by: Eric Anholt <eric at anholt.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh at suse.de>
+
+---
+ drivers/gpu/drm/i915/intel_display.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+--- a/drivers/gpu/drm/i915/intel_display.c
++++ b/drivers/gpu/drm/i915/intel_display.c
+@@ -2538,6 +2538,10 @@ static void g4x_update_wm(struct drm_dev
+ sr_entries = roundup(sr_entries / cacheline_size, 1);
+ DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
+ I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
++ } else {
++ /* Turn off self refresh if both pipes are enabled */
++ I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
++ & ~FW_BLC_SELF_EN);
+ }
+
+ DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
+@@ -2581,6 +2585,10 @@ static void i965_update_wm(struct drm_de
+ srwm = 1;
+ srwm &= 0x3f;
+ I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
++ } else {
++ /* Turn off self refresh if both pipes are enabled */
++ I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
++ & ~FW_BLC_SELF_EN);
+ }
+
+ DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
+@@ -2649,6 +2657,10 @@ static void i9xx_update_wm(struct drm_de
+ if (srwm < 0)
+ srwm = 1;
+ I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
++ } else {
++ /* Turn off self refresh if both pipes are enabled */
++ I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
++ & ~FW_BLC_SELF_EN);
+ }
+
+ DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
+From 1dc7546d1a73664e5d117715b214bea9cae5951c Mon Sep 17 00:00:00 2001
+From: Jesse Barnes <jbarnes at jbarnes-x200.(none)>
+Date: Mon, 19 Oct 2009 10:08:17 +0900
+Subject: drm/i915: enable self-refresh on 965
+
+From: Jesse Barnes <jbarnes at jbarnes-x200.(none)>
+
+commit 1dc7546d1a73664e5d117715b214bea9cae5951c upstream.
+
+Need to calculate the SR watermark and enable it.
+
+Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
+Signed-off-by: Eric Anholt <eric at anholt.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh at suse.de>
+
+---
+ drivers/gpu/drm/i915/intel_display.c | 32 ++++++++++++++++++++++++++++----
+ 1 file changed, 28 insertions(+), 4 deletions(-)
+
+--- a/drivers/gpu/drm/i915/intel_display.c
++++ b/drivers/gpu/drm/i915/intel_display.c
+@@ -2556,15 +2556,39 @@ static void g4x_update_wm(struct drm_dev
+ (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
+ }
+
+-static void i965_update_wm(struct drm_device *dev, int unused, int unused2,
+- int unused3, int unused4)
++static void i965_update_wm(struct drm_device *dev, int planea_clock,
++ int planeb_clock, int sr_hdisplay, int pixel_size)
+ {
+ struct drm_i915_private *dev_priv = dev->dev_private;
++ unsigned long line_time_us;
++ int sr_clock, sr_entries, srwm = 1;
+
+- DRM_DEBUG("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 8\n");
++ /* Calc sr entries for one plane configs */
++ if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
++ /* self-refresh has much higher latency */
++ const static int sr_latency_ns = 12000;
++
++ sr_clock = planea_clock ? planea_clock : planeb_clock;
++ line_time_us = ((sr_hdisplay * 1000) / sr_clock);
++
++ /* Use ns/us then divide to preserve precision */
++ sr_entries = (((sr_latency_ns / line_time_us) + 1) *
++ pixel_size * sr_hdisplay) / 1000;
++ sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
++ DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
++ srwm = I945_FIFO_SIZE - sr_entries;
++ if (srwm < 0)
++ srwm = 1;
++ srwm &= 0x3f;
++ I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
++ }
++
++ DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
++ srwm);
+
+ /* 965 has limitations... */
+- I915_WRITE(DSPFW1, (8 << 16) | (8 << 8) | (8 << 0));
++ I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
++ (8 << 0));
+ I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
+ }
+
+From eceb784cec4dc0fcc2993d9ee4a7c0d111ada80a Mon Sep 17 00:00:00 2001
+From: Zhenyu Wang <zhenyuw at linux.intel.com>
+Date: Mon, 25 Jan 2010 10:35:16 +0800
+Subject: drm/i915: disable hotplug detect before Ironlake CRT detect
+
+From: Zhenyu Wang <zhenyuw at linux.intel.com>
+
+commit eceb784cec4dc0fcc2993d9ee4a7c0d111ada80a upstream.
+
+This tries to fix CRT detect loop hang seen on some Ironlake form
+factor, to clear up hotplug detect state before taking CRT detect
+to make sure next hotplug detect cycle is consistent.
+
+Signed-off-by: Zhenyu Wang <zhenyuw at linux.intel.com>
+Signed-off-by: Eric Anholt <eric at anholt.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh at suse.de>
+
+---
+ drivers/gpu/drm/i915/intel_crt.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/gpu/drm/i915/intel_crt.c
++++ b/drivers/gpu/drm/i915/intel_crt.c
+@@ -185,6 +185,9 @@ static bool intel_igdng_crt_detect_hotpl
+ adpa = I915_READ(PCH_ADPA);
+
+ adpa &= ~ADPA_CRT_HOTPLUG_MASK;
++ /* disable HPD first */
++ I915_WRITE(PCH_ADPA, adpa);
++ (void)I915_READ(PCH_ADPA);
+
+ adpa |= (ADPA_CRT_HOTPLUG_PERIOD_128 |
+ ADPA_CRT_HOTPLUG_WARMUP_10MS |
Index: sources
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/F-12/sources,v
retrieving revision 1.1105
retrieving revision 1.1106
diff -u -p -r1.1105 -r1.1106
--- sources 9 Feb 2010 13:46:07 -0000 1.1105
+++ sources 22 Feb 2010 07:36:06 -0000 1.1106
@@ -1,2 +1,3 @@
260551284ac224c3a43c4adac7df4879 linux-2.6.32.tar.bz2
eabf01da4c72f7ea5b4e4bf8e8535e5f patch-2.6.32.8.bz2
+9daac0fa72347239e2e286a841e143c6 patch-2.6.32.9-rc1.bz2
Index: upstream
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/F-12/upstream,v
retrieving revision 1.1019
retrieving revision 1.1020
diff -u -p -r1.1019 -r1.1020
--- upstream 9 Feb 2010 13:46:07 -0000 1.1019
+++ upstream 22 Feb 2010 07:36:06 -0000 1.1020
@@ -1,2 +1,3 @@
linux-2.6.32.tar.bz2
patch-2.6.32.8.bz2
+patch-2.6.32.9-rc1.bz2
--- fix-conntrack-bug-with-namespaces.patch DELETED ---
--- fix-crash-with-sys_move_pages.patch DELETED ---
--- fix-race-in-tty_fasync-properly.patch DELETED ---
--- futex-handle-futex-value-corruption-gracefully.patch DELETED ---
--- futex-handle-user-space-corruption-gracefully.patch DELETED ---
--- futex_lock_pi-key-refcnt-fix.patch DELETED ---
--- prevent-runtime-conntrack-changes.patch DELETED ---
--- wmi-check-wmi-get-event-data-return-value.patch DELETED ---
--- wmi-free-the-allocated-acpi-objects.patch DELETED ---
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