rpms/kernel/F-11 drm-2.6.30.patch, NONE, 1.1 kernel.spec, 1.1819, 1.1820 linux-2.6-upstream-reverts.patch, 1.11, 1.12
Kyle McMartin
kyle at fedoraproject.org
Mon Feb 22 23:17:15 UTC 2010
Author: kyle
Update of /cvs/pkgs/rpms/kernel/F-11
In directory cvs1.fedora.phx.redhat.com:/tmp/cvs-serv11732
Modified Files:
kernel.spec linux-2.6-upstream-reverts.patch
Added Files:
drm-2.6.30.patch
Log Message:
* Mon Feb 22 2010 Kyle McMartin <kyle at redhat.com>
- Forward port F-11-2.6.30 DRM to 2.6.32... remove VGA arbiter
since it didn't exist in release F-11. Clean up a bunch, fix up
a bunch of rejects, and build failures.
- It probably still won't work right, here's hoping.
drm-2.6.30.patch:
b/arch/alpha/include/asm/agp.h | 4
b/arch/ia64/include/asm/agp.h | 3
b/arch/powerpc/include/asm/agp.h | 3
b/arch/sparc/include/asm/agp.h | 4
b/arch/x86/include/asm/agp.h | 3
b/arch/x86/mm/pat.c | 1
b/drivers/char/agp/agp.h | 25
b/drivers/char/agp/ali-agp.c | 28
b/drivers/char/agp/alpha-agp.c | 2
b/drivers/char/agp/amd-k7-agp.c | 10
b/drivers/char/agp/amd64-agp.c | 7
b/drivers/char/agp/ati-agp.c | 28
b/drivers/char/agp/backend.c | 40
b/drivers/char/agp/efficeon-agp.c | 7
b/drivers/char/agp/generic.c | 93
b/drivers/char/agp/hp-agp.c | 27
b/drivers/char/agp/i460-agp.c | 38
b/drivers/char/agp/intel-agp.c | 279
b/drivers/char/agp/nvidia-agp.c | 2
b/drivers/char/agp/parisc-agp.c | 12
b/drivers/char/agp/sgi-agp.c | 11
b/drivers/char/agp/sworks-agp.c | 10
b/drivers/char/agp/uninorth-agp.c | 85
b/drivers/gpu/Makefile | 2
b/drivers/gpu/drm/Kconfig | 52
b/drivers/gpu/drm/Makefile | 12
b/drivers/gpu/drm/ati_pcigart.c | 277
b/drivers/gpu/drm/drm_agpsupport.c | 185
b/drivers/gpu/drm/drm_auth.c | 4
b/drivers/gpu/drm/drm_bo.c | 2161 ++
b/drivers/gpu/drm/drm_bo_move.c | 709
b/drivers/gpu/drm/drm_bufs.c | 191
b/drivers/gpu/drm/drm_cache.c | 46
b/drivers/gpu/drm/drm_context.c | 4
b/drivers/gpu/drm/drm_crtc.c | 118
b/drivers/gpu/drm/drm_crtc_helper.c | 348
b/drivers/gpu/drm/drm_debugfs.c | 26
b/drivers/gpu/drm/drm_dma.c | 33
b/drivers/gpu/drm/drm_drawable.c | 25
b/drivers/gpu/drm/drm_drv.c | 53
b/drivers/gpu/drm/drm_edid.c | 657
b/drivers/gpu/drm/drm_fence.c | 540
b/drivers/gpu/drm/drm_fops.c | 13
b/drivers/gpu/drm/drm_gem.c | 93
b/drivers/gpu/drm/drm_hashtab.c | 10
b/drivers/gpu/drm/drm_info.c | 8
b/drivers/gpu/drm/drm_ioctl.c | 14
b/drivers/gpu/drm/drm_irq.c | 105
b/drivers/gpu/drm/drm_memory.c | 140
b/drivers/gpu/drm/drm_mm.c | 181
b/drivers/gpu/drm/drm_modes.c | 444
b/drivers/gpu/drm/drm_page_alloc.c | 172
b/drivers/gpu/drm/drm_page_alloc.h | 33
b/drivers/gpu/drm/drm_pci.c | 61
b/drivers/gpu/drm/drm_proc.c | 25
b/drivers/gpu/drm/drm_scatter.c | 33
b/drivers/gpu/drm/drm_sman.c | 29
b/drivers/gpu/drm/drm_stub.c | 59
b/drivers/gpu/drm/drm_sysfs.c | 86
b/drivers/gpu/drm/drm_ttm.c | 469
b/drivers/gpu/drm/drm_vm.c | 228
b/drivers/gpu/drm/i810/i810_dma.c | 6
b/drivers/gpu/drm/i830/i830_dma.c | 6
b/drivers/gpu/drm/i915/Makefile | 5
b/drivers/gpu/drm/i915/dvo.h | 4
b/drivers/gpu/drm/i915/dvo_ch7017.c | 20
b/drivers/gpu/drm/i915/dvo_ch7xxx.c | 25
b/drivers/gpu/drm/i915/dvo_ivch.c | 21
b/drivers/gpu/drm/i915/dvo_sil164.c | 25
b/drivers/gpu/drm/i915/dvo_tfp410.c | 25
b/drivers/gpu/drm/i915/i915_dma.c | 471
b/drivers/gpu/drm/i915/i915_drv.c | 152
b/drivers/gpu/drm/i915/i915_drv.h | 291
b/drivers/gpu/drm/i915/i915_gem.c | 1264 -
b/drivers/gpu/drm/i915/i915_gem_debug.c | 6
b/drivers/gpu/drm/i915/i915_gem_debugfs.c | 356
b/drivers/gpu/drm/i915/i915_gem_tiling.c | 148
b/drivers/gpu/drm/i915/i915_irq.c | 581
b/drivers/gpu/drm/i915/i915_mem.c | 24
b/drivers/gpu/drm/i915/i915_opregion.c | 22
b/drivers/gpu/drm/i915/i915_reg.h | 956
b/drivers/gpu/drm/i915/i915_suspend.c | 616
b/drivers/gpu/drm/i915/intel_bios.c | 186
b/drivers/gpu/drm/i915/intel_bios.h | 146
b/drivers/gpu/drm/i915/intel_crt.c | 148
b/drivers/gpu/drm/i915/intel_display.c | 2847 --
b/drivers/gpu/drm/i915/intel_drv.h | 56
b/drivers/gpu/drm/i915/intel_dvo.c | 22
b/drivers/gpu/drm/i915/intel_fb.c | 750
b/drivers/gpu/drm/i915/intel_hdmi.c | 117
b/drivers/gpu/drm/i915/intel_i2c.c | 24
b/drivers/gpu/drm/i915/intel_lvds.c | 643
b/drivers/gpu/drm/i915/intel_modes.c | 14
b/drivers/gpu/drm/i915/intel_sdvo.c | 1494 -
b/drivers/gpu/drm/i915/intel_sdvo_regs.h | 1
b/drivers/gpu/drm/i915/intel_tv.c | 132
b/drivers/gpu/drm/mga/mga_dma.c | 18
b/drivers/gpu/drm/mga/mga_drv.h | 1
b/drivers/gpu/drm/mga/mga_state.c | 4
b/drivers/gpu/drm/mga/mga_ucode.h |11645 ++++++++++
b/drivers/gpu/drm/mga/mga_warp.c | 180
b/drivers/gpu/drm/nouveau/Makefile | 24
b/drivers/gpu/drm/nouveau/nouveau_backlight.c | 152
b/drivers/gpu/drm/nouveau/nouveau_bios.c | 4852 ++++
b/drivers/gpu/drm/nouveau/nouveau_bios.h | 223
b/drivers/gpu/drm/nouveau/nouveau_bo.c | 415
b/drivers/gpu/drm/nouveau/nouveau_calc.c | 622
b/drivers/gpu/drm/nouveau/nouveau_connector.h | 51
b/drivers/gpu/drm/nouveau/nouveau_crtc.h | 74
b/drivers/gpu/drm/nouveau/nouveau_display.c | 114
b/drivers/gpu/drm/nouveau/nouveau_dma.c | 209
b/drivers/gpu/drm/nouveau/nouveau_dma.h | 107
b/drivers/gpu/drm/nouveau/nouveau_drv.c | 194
b/drivers/gpu/drm/nouveau/nouveau_drv.h | 836
b/drivers/gpu/drm/nouveau/nouveau_encoder.h | 46
b/drivers/gpu/drm/nouveau/nouveau_fb.h | 44
b/drivers/gpu/drm/nouveau/nouveau_fbcon.c | 946
b/drivers/gpu/drm/nouveau/nouveau_fbcon.h | 48
b/drivers/gpu/drm/nouveau/nouveau_fence.c | 126
b/drivers/gpu/drm/nouveau/nouveau_fifo.c | 692
b/drivers/gpu/drm/nouveau/nouveau_gem.c | 729
b/drivers/gpu/drm/nouveau/nouveau_hw.c | 1019
b/drivers/gpu/drm/nouveau/nouveau_hw.h | 530
b/drivers/gpu/drm/nouveau/nouveau_i2c.c | 222
b/drivers/gpu/drm/nouveau/nouveau_i2c.h | 46
b/drivers/gpu/drm/nouveau/nouveau_ioc32.c | 72
b/drivers/gpu/drm/nouveau/nouveau_irq.c | 592
b/drivers/gpu/drm/nouveau/nouveau_mem.c | 1073 +
b/drivers/gpu/drm/nouveau/nouveau_notifier.c | 176
b/drivers/gpu/drm/nouveau/nouveau_object.c | 1236 +
b/drivers/gpu/drm/nouveau/nouveau_reg.h | 854
b/drivers/gpu/drm/nouveau/nouveau_sgdma.c | 340
b/drivers/gpu/drm/nouveau/nouveau_state.c | 1043
b/drivers/gpu/drm/nouveau/nouveau_swmthd.c | 190
b/drivers/gpu/drm/nouveau/nouveau_swmthd.h | 33
b/drivers/gpu/drm/nouveau/nv04_fb.c | 21
b/drivers/gpu/drm/nouveau/nv04_fifo.c | 144
b/drivers/gpu/drm/nouveau/nv04_graph.c | 521
b/drivers/gpu/drm/nouveau/nv04_instmem.c | 190
b/drivers/gpu/drm/nouveau/nv04_mc.c | 20
b/drivers/gpu/drm/nouveau/nv04_timer.c | 50
b/drivers/gpu/drm/nouveau/nv10_fb.c | 24
b/drivers/gpu/drm/nouveau/nv10_fifo.c | 175
b/drivers/gpu/drm/nouveau/nv10_graph.c | 912
b/drivers/gpu/drm/nouveau/nv20_graph.c | 907
b/drivers/gpu/drm/nouveau/nv40_fb.c | 62
b/drivers/gpu/drm/nouveau/nv40_fifo.c | 216
b/drivers/gpu/drm/nouveau/nv40_graph.c | 2179 ++
b/drivers/gpu/drm/nouveau/nv40_mc.c | 38
b/drivers/gpu/drm/nouveau/nv50_connector.c | 491
b/drivers/gpu/drm/nouveau/nv50_crtc.c | 810
b/drivers/gpu/drm/nouveau/nv50_cursor.c | 144
b/drivers/gpu/drm/nouveau/nv50_dac.c | 288
b/drivers/gpu/drm/nouveau/nv50_display.c | 637
b/drivers/gpu/drm/nouveau/nv50_display.h | 44
b/drivers/gpu/drm/nouveau/nv50_display_commands.h | 195
b/drivers/gpu/drm/nouveau/nv50_fbcon.c | 222
b/drivers/gpu/drm/nouveau/nv50_fifo.c | 343
b/drivers/gpu/drm/nouveau/nv50_graph.c | 336
b/drivers/gpu/drm/nouveau/nv50_grctx.h |20935 +++++++++++++++++++
b/drivers/gpu/drm/nouveau/nv50_instmem.c | 382
b/drivers/gpu/drm/nouveau/nv50_mc.c | 40
b/drivers/gpu/drm/nouveau/nv50_sor.c | 303
b/drivers/gpu/drm/nouveau/nvreg.h | 495
b/drivers/gpu/drm/r128/r128_cce.c | 110
b/drivers/gpu/drm/r128/r128_state.c | 84
b/drivers/gpu/drm/radeon/Makefile | 52
b/drivers/gpu/drm/radeon/ObjectID.h | 678
b/drivers/gpu/drm/radeon/atom-bits.h | 18
b/drivers/gpu/drm/radeon/atom-names.h | 8
b/drivers/gpu/drm/radeon/atom.c | 1811 -
b/drivers/gpu/drm/radeon/atom.h | 15
b/drivers/gpu/drm/radeon/atombios.h | 6289 +++--
b/drivers/gpu/drm/radeon/atombios_crtc.c | 800
b/drivers/gpu/drm/radeon/r300_cmdbuf.c | 153
b/drivers/gpu/drm/radeon/r300_reg.h | 72
b/drivers/gpu/drm/radeon/r600_cp.c | 557
b/drivers/gpu/drm/radeon/r600_microcode.h |23297 ++++++++++++++++++++++
b/drivers/gpu/drm/radeon/radeon_atombios.c | 1079 -
b/drivers/gpu/drm/radeon/radeon_buffer.c | 473
b/drivers/gpu/drm/radeon/radeon_combios.c | 1709 -
b/drivers/gpu/drm/radeon/radeon_connectors.c | 725
b/drivers/gpu/drm/radeon/radeon_cp.c | 1708 +
b/drivers/gpu/drm/radeon/radeon_cs.c | 856
b/drivers/gpu/drm/radeon/radeon_cursor.c | 195
b/drivers/gpu/drm/radeon/radeon_display.c | 692
b/drivers/gpu/drm/radeon/radeon_drv.c | 289
b/drivers/gpu/drm/radeon/radeon_drv.h | 714
b/drivers/gpu/drm/radeon/radeon_encoders.c | 789
b/drivers/gpu/drm/radeon/radeon_fb.c | 940
b/drivers/gpu/drm/radeon/radeon_fence.c | 435
b/drivers/gpu/drm/radeon/radeon_fixed.h | 21
b/drivers/gpu/drm/radeon/radeon_gem.c | 1698 +
b/drivers/gpu/drm/radeon/radeon_gem_debugfs.c | 179
b/drivers/gpu/drm/radeon/radeon_i2c.c | 124
b/drivers/gpu/drm/radeon/radeon_ioc32.c | 15
b/drivers/gpu/drm/radeon/radeon_irq.c | 82
b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c | 1731 +
b/drivers/gpu/drm/radeon/radeon_legacy_encoders.c | 997
b/drivers/gpu/drm/radeon/radeon_mem.c | 26
b/drivers/gpu/drm/radeon/radeon_microcode.h | 1844 +
b/drivers/gpu/drm/radeon/radeon_mode.h | 207
b/drivers/gpu/drm/radeon/radeon_pm.c | 257
b/drivers/gpu/drm/radeon/radeon_reg.h | 2111 +
b/drivers/gpu/drm/radeon/radeon_state.c | 109
b/drivers/gpu/drm/savage/savage_bci.c | 21
b/drivers/gpu/drm/savage/savage_state.c | 17
b/drivers/gpu/drm/sis/sis_drv.c | 6
b/drivers/gpu/drm/via/via_dmablit.c | 6
b/drivers/gpu/drm/via/via_irq.c | 6
b/drivers/gpu/drm/via/via_map.c | 8
b/drivers/staging/Kconfig | 2
b/drivers/video/Kconfig | 2
b/include/drm/Kbuild | 1
b/include/drm/drm.h | 1
b/include/drm/drmP.h | 314
b/include/drm/drm_crtc.h | 28
b/include/drm/drm_crtc_helper.h | 12
b/include/drm/drm_edid.h | 92
b/include/drm/drm_hashtab.h | 2
b/include/drm/drm_memory.h | 2
b/include/drm/drm_memory_debug.h | 309
b/include/drm/drm_mode.h | 11
b/include/drm/drm_objects.h | 913
b/include/drm/drm_pciids.h | 31
b/include/drm/i915_drm.h | 19
b/include/drm/nouveau_drm.h | 299
b/include/drm/radeon_drm.h | 37
b/include/linux/agp_backend.h | 9
drivers/gpu/drm/drm_encoder_slave.c | 116
drivers/gpu/drm/drm_fb_helper.c | 1030
drivers/gpu/drm/i915/i915_debugfs.c | 447
drivers/gpu/drm/i915/i915_trace.h | 316
drivers/gpu/drm/i915/i915_trace_points.c | 11
drivers/gpu/drm/i915/intel_dp.c | 1336 -
drivers/gpu/drm/i915/intel_dp.h | 144
drivers/gpu/drm/i915/intel_dp_i2c.c | 273
drivers/gpu/drm/radeon/.gitignore | 3
drivers/gpu/drm/radeon/Kconfig | 33
drivers/gpu/drm/radeon/avivod.h | 60
drivers/gpu/drm/radeon/mkregtable.c | 720
drivers/gpu/drm/radeon/r100.c | 3291 ---
drivers/gpu/drm/radeon/r100_track.h | 183
drivers/gpu/drm/radeon/r100d.h | 714
drivers/gpu/drm/radeon/r200.c | 454
drivers/gpu/drm/radeon/r300.c | 1359 -
drivers/gpu/drm/radeon/r300d.h | 306
drivers/gpu/drm/radeon/r420.c | 401
drivers/gpu/drm/radeon/r420d.h | 249
drivers/gpu/drm/radeon/r500_reg.h | 771
drivers/gpu/drm/radeon/r520.c | 302
drivers/gpu/drm/radeon/r520d.h | 187
drivers/gpu/drm/radeon/r600.c | 1857 -
drivers/gpu/drm/radeon/r600_blit.c | 858
drivers/gpu/drm/radeon/r600_blit_kms.c | 805
drivers/gpu/drm/radeon/r600_blit_shaders.c | 1072 -
drivers/gpu/drm/radeon/r600_blit_shaders.h | 14
drivers/gpu/drm/radeon/r600_cs.c | 801
drivers/gpu/drm/radeon/r600_reg.h | 114
drivers/gpu/drm/radeon/r600d.h | 677
drivers/gpu/drm/radeon/radeon.h | 1110 -
drivers/gpu/drm/radeon/radeon_agp.c | 261
drivers/gpu/drm/radeon/radeon_asic.h | 528
drivers/gpu/drm/radeon/radeon_benchmark.c | 133
drivers/gpu/drm/radeon/radeon_bios.c | 432
drivers/gpu/drm/radeon/radeon_clocks.c | 835
drivers/gpu/drm/radeon/radeon_device.c | 760
drivers/gpu/drm/radeon/radeon_family.h | 97
drivers/gpu/drm/radeon/radeon_gart.c | 240
drivers/gpu/drm/radeon/radeon_irq_kms.c | 116
drivers/gpu/drm/radeon/radeon_kms.c | 294
drivers/gpu/drm/radeon/radeon_legacy_tv.c | 904
drivers/gpu/drm/radeon/radeon_object.c | 627
drivers/gpu/drm/radeon/radeon_object.h | 46
drivers/gpu/drm/radeon/radeon_ring.c | 379
drivers/gpu/drm/radeon/radeon_test.c | 209
drivers/gpu/drm/radeon/radeon_ttm.c | 740
drivers/gpu/drm/radeon/reg_srcs/r100 | 105
drivers/gpu/drm/radeon/reg_srcs/r200 | 184
drivers/gpu/drm/radeon/reg_srcs/r300 | 729
drivers/gpu/drm/radeon/reg_srcs/rn50 | 30
drivers/gpu/drm/radeon/reg_srcs/rs600 | 729
drivers/gpu/drm/radeon/reg_srcs/rv515 | 486
drivers/gpu/drm/radeon/rs100d.h | 40
drivers/gpu/drm/radeon/rs400.c | 534
drivers/gpu/drm/radeon/rs400d.h | 160
drivers/gpu/drm/radeon/rs600.c | 538
drivers/gpu/drm/radeon/rs600d.h | 470
drivers/gpu/drm/radeon/rs690.c | 748
drivers/gpu/drm/radeon/rs690d.h | 307
drivers/gpu/drm/radeon/rv200d.h | 36
drivers/gpu/drm/radeon/rv250d.h | 123
drivers/gpu/drm/radeon/rv350d.h | 52
drivers/gpu/drm/radeon/rv515.c | 1178 -
drivers/gpu/drm/radeon/rv515d.h | 603
drivers/gpu/drm/radeon/rv770.c | 1067 -
drivers/gpu/drm/radeon/rv770d.h | 346
drivers/gpu/drm/ttm/Makefile | 8
drivers/gpu/drm/ttm/ttm_agp_backend.c | 149
drivers/gpu/drm/ttm/ttm_bo.c | 1830 -
drivers/gpu/drm/ttm/ttm_bo_util.c | 603
drivers/gpu/drm/ttm/ttm_bo_vm.c | 456
drivers/gpu/drm/ttm/ttm_global.c | 112
drivers/gpu/drm/ttm/ttm_memory.c | 590
drivers/gpu/drm/ttm/ttm_module.c | 106
drivers/gpu/drm/ttm/ttm_tt.c | 585
drivers/gpu/vga/Kconfig | 10
drivers/gpu/vga/Makefile | 1
drivers/gpu/vga/vgaarb.c | 1205 -
include/drm/drm_cache.h | 38
include/drm/drm_encoder_slave.h | 162
include/drm/drm_fb_helper.h | 111
include/drm/drm_mm.h | 106
include/drm/drm_sysfs.h | 12
include/drm/ttm/ttm_bo_api.h | 619
include/drm/ttm/ttm_bo_driver.h | 927
include/drm/ttm/ttm_memory.h | 159
include/drm/ttm/ttm_module.h | 60
include/drm/ttm/ttm_placement.h | 92
319 files changed, 112852 insertions(+), 67140 deletions(-)
--- NEW FILE drm-2.6.30.patch ---
diff --git a/arch/alpha/include/asm/agp.h b/arch/alpha/include/asm/agp.h
index a94d48b..ff87914 100644
--- a/arch/alpha/include/asm/agp.h
+++ b/arch/alpha/include/asm/agp.h
@@ -5,6 +5,10 @@
/* dummy for now */
+#define phys_to_gart(x) (x)
+#define gart_to_phys(x) (x)
+
+
#define map_page_into_agp(page)
#define unmap_page_from_agp(page)
#define flush_agp_cache() mb()
diff --git a/arch/ia64/include/asm/agp.h b/arch/ia64/include/asm/agp.h
index 01d09c4..2820ed0 100644
--- a/arch/ia64/include/asm/agp.h
+++ b/arch/ia64/include/asm/agp.h
@@ -8,6 +8,9 @@
* David Mosberger-Tang <davidm at hpl.hp.com>
*/
+#define phys_to_gart(x) (x)
+#define gart_to_phys(x) (x)
+
/*
* To avoid memory-attribute aliasing issues, we require that the AGPGART engine operate
* in coherent mode, which lets us map the AGP memory as normal (write-back) memory
diff --git a/arch/powerpc/include/asm/agp.h b/arch/powerpc/include/asm/agp.h
index 416e12c..b8885b8 100644
--- a/arch/powerpc/include/asm/agp.h
+++ b/arch/powerpc/include/asm/agp.h
@@ -8,6 +8,9 @@
#define unmap_page_from_agp(page)
#define flush_agp_cache() mb()
+#define phys_to_gart(x) (x)
+#define gart_to_phys(x) (x)
+
/* GATT allocation. Returns/accepts GATT kernel virtual address. */
#define alloc_gatt_pages(order) \
((char *)__get_free_pages(GFP_KERNEL, (order)))
diff --git a/arch/sparc/include/asm/agp.h b/arch/sparc/include/asm/agp.h
index 70f52c1..1f35044 100644
--- a/arch/sparc/include/asm/agp.h
+++ b/arch/sparc/include/asm/agp.h
@@ -3,6 +3,10 @@
/* dummy for now */
+#define phys_to_gart(x) (x)
+#define gart_to_phys(x) (x)
+
+
#define map_page_into_agp(page)
#define unmap_page_from_agp(page)
#define flush_agp_cache() mb()
diff --git a/arch/x86/include/asm/agp.h b/arch/x86/include/asm/agp.h
index eec2a70..e909694 100644
--- a/arch/x86/include/asm/agp.h
+++ b/arch/x86/include/asm/agp.h
@@ -4,6 +4,9 @@
#include <asm/pgtable.h>
#include <asm/cacheflush.h>
+#define phys_to_gart(x) (x)
+#define gart_to_phys(x) (x)
+
/*
* Functions to keep the agpgart mappings coherent with the MMU. The
* GART gives the CPU a physical alias of pages in memory. The alias
diff --git a/arch/x86/mm/pat.c b/arch/x86/mm/pat.c
index e78cd0e..3ff04a2 100644
--- a/arch/x86/mm/pat.c
+++ b/arch/x86/mm/pat.c
@@ -31,6 +31,7 @@
#ifdef CONFIG_X86_PAT
int __read_mostly pat_enabled = 1;
+EXPORT_SYMBOL(pat_enabled);
static inline void pat_disable(const char *reason)
{
diff --git a/drivers/char/agp/agp.h b/drivers/char/agp/agp.h
index 870f12c..46f5075 100644
--- a/drivers/char/agp/agp.h
+++ b/drivers/char/agp/agp.h
@@ -107,7 +107,7 @@ struct agp_bridge_driver {
void (*agp_enable)(struct agp_bridge_data *, u32);
void (*cleanup)(void);
void (*tlb_flush)(struct agp_memory *);
- unsigned long (*mask_memory)(struct agp_bridge_data *, dma_addr_t, int);
+ unsigned long (*mask_memory)(struct agp_bridge_data *, unsigned long, int);
void (*cache_flush)(void);
int (*create_gatt_table)(struct agp_bridge_data *);
int (*free_gatt_table)(struct agp_bridge_data *);
@@ -115,23 +115,18 @@ struct agp_bridge_driver {
int (*remove_memory)(struct agp_memory *, off_t, int);
struct agp_memory *(*alloc_by_type) (size_t, int);
void (*free_by_type)(struct agp_memory *);
- struct page *(*agp_alloc_page)(struct agp_bridge_data *);
+ void *(*agp_alloc_page)(struct agp_bridge_data *);
int (*agp_alloc_pages)(struct agp_bridge_data *, struct agp_memory *, size_t);
- void (*agp_destroy_page)(struct page *, int flags);
+ void (*agp_destroy_page)(void *, int flags);
void (*agp_destroy_pages)(struct agp_memory *);
int (*agp_type_to_mask_type) (struct agp_bridge_data *, int);
void (*chipset_flush)(struct agp_bridge_data *);
-
- int (*agp_map_page)(struct page *page, dma_addr_t *ret);
- void (*agp_unmap_page)(struct page *page, dma_addr_t dma);
- int (*agp_map_memory)(struct agp_memory *mem);
- void (*agp_unmap_memory)(struct agp_memory *mem);
};
struct agp_bridge_data {
const struct agp_version *version;
const struct agp_bridge_driver *driver;
- const struct vm_operations_struct *vm_ops;
+ struct vm_operations_struct *vm_ops;
void *previous_size;
void *current_size;
void *dev_private_data;
@@ -139,8 +134,7 @@ struct agp_bridge_data {
u32 __iomem *gatt_table;
u32 *gatt_table_real;
unsigned long scratch_page;
- struct page *scratch_page_page;
- dma_addr_t scratch_page_dma;
+ unsigned long scratch_page_real;
unsigned long gart_bus_addr;
unsigned long gatt_bus_addr;
u32 mode;
@@ -284,10 +278,10 @@ int agp_generic_insert_memory(struct agp_memory *mem, off_t pg_start, int type);
int agp_generic_remove_memory(struct agp_memory *mem, off_t pg_start, int type);
struct agp_memory *agp_generic_alloc_by_type(size_t page_count, int type);
void agp_generic_free_by_type(struct agp_memory *curr);
-struct page *agp_generic_alloc_page(struct agp_bridge_data *bridge);
+void *agp_generic_alloc_page(struct agp_bridge_data *bridge);
int agp_generic_alloc_pages(struct agp_bridge_data *agp_bridge,
struct agp_memory *memory, size_t page_count);
-void agp_generic_destroy_page(struct page *page, int flags);
+void agp_generic_destroy_page(void *addr, int flags);
void agp_generic_destroy_pages(struct agp_memory *memory);
void agp_free_key(int key);
int agp_num_entries(void);
@@ -297,7 +291,7 @@ int agp_3_5_enable(struct agp_bridge_data *bridge);
void global_cache_flush(void);
void get_agp_version(struct agp_bridge_data *bridge);
unsigned long agp_generic_mask_memory(struct agp_bridge_data *bridge,
- dma_addr_t phys, int type);
+ unsigned long addr, int type);
int agp_generic_type_to_mask_type(struct agp_bridge_data *bridge,
int type);
struct agp_bridge_data *agp_generic_find_bridge(struct pci_dev *pdev);
@@ -318,6 +312,9 @@ void agp3_generic_cleanup(void);
#define AGP_GENERIC_SIZES_ENTRIES 11
extern const struct aper_size_info_16 agp3_generic_sizes[];
+#define virt_to_gart(x) (phys_to_gart(virt_to_phys(x)))
+#define gart_to_virt(x) (phys_to_virt(gart_to_phys(x)))
+
extern int agp_off;
extern int agp_try_unsupported_boot;
diff --git a/drivers/char/agp/ali-agp.c b/drivers/char/agp/ali-agp.c
index d2ce68f..dc8d1a9 100644
--- a/drivers/char/agp/ali-agp.c
+++ b/drivers/char/agp/ali-agp.c
@@ -141,37 +141,37 @@ static void m1541_cache_flush(void)
}
}
-static struct page *m1541_alloc_page(struct agp_bridge_data *bridge)
+static void *m1541_alloc_page(struct agp_bridge_data *bridge)
{
- struct page *page = agp_generic_alloc_page(agp_bridge);
+ void *addr = agp_generic_alloc_page(agp_bridge);
u32 temp;
- if (!page)
+ if (!addr)
return NULL;
pci_read_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL, &temp);
pci_write_config_dword(agp_bridge->dev, ALI_CACHE_FLUSH_CTRL,
(((temp & ALI_CACHE_FLUSH_ADDR_MASK) |
- page_to_phys(page)) | ALI_CACHE_FLUSH_EN ));
- return page;
+ virt_to_gart(addr)) | ALI_CACHE_FLUSH_EN ));
+ return addr;
}
-static void ali_destroy_page(struct page *page, int flags)
+static void ali_destroy_page(void * addr, int flags)
{
- if (page) {
+ if (addr) {
[...198700 lines suppressed...]
diff --git a/include/drm/ttm/ttm_module.h b/include/drm/ttm/ttm_module.h
deleted file mode 100644
index cf416ae..0000000
--- a/include/drm/ttm/ttm_module.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/**************************************************************************
- *
- * Copyright 2008-2009 VMware, Inc., Palo Alto, CA., USA
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- **************************************************************************/
-/*
- * Authors: Thomas Hellstrom <thellstrom-at-vmware-dot-com>
- */
-
-#ifndef _TTM_MODULE_H_
-#define _TTM_MODULE_H_
-
-#include <linux/kernel.h>
-struct kobject;
-
-#define TTM_PFX "[TTM] "
-
-enum ttm_global_types {
- TTM_GLOBAL_TTM_MEM = 0,
- TTM_GLOBAL_TTM_BO,
- TTM_GLOBAL_TTM_OBJECT,
- TTM_GLOBAL_NUM
-};
-
-struct ttm_global_reference {
- enum ttm_global_types global_type;
- size_t size;
- void *object;
- int (*init) (struct ttm_global_reference *);
- void (*release) (struct ttm_global_reference *);
-};
-
-extern void ttm_global_init(void);
-extern void ttm_global_release(void);
-extern int ttm_global_item_ref(struct ttm_global_reference *ref);
-extern void ttm_global_item_unref(struct ttm_global_reference *ref);
-extern struct kobject *ttm_get_kobj(void);
-
-#endif /* _TTM_MODULE_H_ */
diff --git a/include/drm/ttm/ttm_placement.h b/include/drm/ttm/ttm_placement.h
deleted file mode 100644
index c84ff15..0000000
--- a/include/drm/ttm/ttm_placement.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/**************************************************************************
- *
- * Copyright (c) 2006-2009 VMware, Inc., Palo Alto, CA., USA
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- **************************************************************************/
-/*
- * Authors: Thomas Hellstrom <thellstrom-at-vmware-dot-com>
- */
-
-#ifndef _TTM_PLACEMENT_H_
-#define _TTM_PLACEMENT_H_
-/*
- * Memory regions for data placement.
- */
-
-#define TTM_PL_SYSTEM 0
-#define TTM_PL_TT 1
-#define TTM_PL_VRAM 2
-#define TTM_PL_PRIV0 3
-#define TTM_PL_PRIV1 4
-#define TTM_PL_PRIV2 5
-#define TTM_PL_PRIV3 6
-#define TTM_PL_PRIV4 7
-#define TTM_PL_PRIV5 8
-#define TTM_PL_SWAPPED 15
-
-#define TTM_PL_FLAG_SYSTEM (1 << TTM_PL_SYSTEM)
-#define TTM_PL_FLAG_TT (1 << TTM_PL_TT)
-#define TTM_PL_FLAG_VRAM (1 << TTM_PL_VRAM)
-#define TTM_PL_FLAG_PRIV0 (1 << TTM_PL_PRIV0)
-#define TTM_PL_FLAG_PRIV1 (1 << TTM_PL_PRIV1)
-#define TTM_PL_FLAG_PRIV2 (1 << TTM_PL_PRIV2)
-#define TTM_PL_FLAG_PRIV3 (1 << TTM_PL_PRIV3)
-#define TTM_PL_FLAG_PRIV4 (1 << TTM_PL_PRIV4)
-#define TTM_PL_FLAG_PRIV5 (1 << TTM_PL_PRIV5)
-#define TTM_PL_FLAG_SWAPPED (1 << TTM_PL_SWAPPED)
-#define TTM_PL_MASK_MEM 0x0000FFFF
-
-/*
- * Other flags that affects data placement.
- * TTM_PL_FLAG_CACHED indicates cache-coherent mappings
- * if available.
- * TTM_PL_FLAG_SHARED means that another application may
- * reference the buffer.
- * TTM_PL_FLAG_NO_EVICT means that the buffer may never
- * be evicted to make room for other buffers.
- */
-
-#define TTM_PL_FLAG_CACHED (1 << 16)
-#define TTM_PL_FLAG_UNCACHED (1 << 17)
-#define TTM_PL_FLAG_WC (1 << 18)
-#define TTM_PL_FLAG_SHARED (1 << 20)
-#define TTM_PL_FLAG_NO_EVICT (1 << 21)
-
-#define TTM_PL_MASK_CACHING (TTM_PL_FLAG_CACHED | \
- TTM_PL_FLAG_UNCACHED | \
- TTM_PL_FLAG_WC)
-
-#define TTM_PL_MASK_MEMTYPE (TTM_PL_MASK_MEM | TTM_PL_MASK_CACHING)
-
-/*
- * Access flags to be used for CPU- and GPU- mappings.
- * The idea is that the TTM synchronization mechanism will
- * allow concurrent READ access and exclusive write access.
- * Currently GPU- and CPU accesses are exclusive.
- */
-
-#define TTM_ACCESS_READ (1 << 0)
-#define TTM_ACCESS_WRITE (1 << 1)
-
-#endif
diff --git a/include/linux/agp_backend.h b/include/linux/agp_backend.h
index 9101ed6..2b8df8b 100644
--- a/include/linux/agp_backend.h
+++ b/include/linux/agp_backend.h
@@ -53,7 +53,7 @@ struct agp_kern_info {
int current_memory;
bool cant_use_aperture;
unsigned long page_mask;
- const struct vm_operations_struct *vm_ops;
+ struct vm_operations_struct *vm_ops;
};
/*
@@ -70,7 +70,7 @@ struct agp_memory {
struct agp_memory *next;
struct agp_memory *prev;
struct agp_bridge_data *bridge;
- struct page **pages;
+ unsigned long *memory;
size_t page_count;
int key;
int num_scratch_pages;
@@ -79,12 +79,9 @@ struct agp_memory {
u32 physical;
bool is_bound;
bool is_flushed;
- bool vmalloc_flag;
+ bool vmalloc_flag;
/* list of agp_memory mapped to the aperture */
struct list_head mapped_list;
- /* DMA-mapped addresses */
- struct scatterlist *sg_list;
- int num_sg;
};
#define AGP_NORMAL_MEMORY 0
Index: kernel.spec
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/F-11/kernel.spec,v
retrieving revision 1.1819
retrieving revision 1.1820
diff -u -p -r1.1819 -r1.1820
--- kernel.spec 22 Feb 2010 11:54:23 -0000 1.1819
+++ kernel.spec 22 Feb 2010 23:17:13 -0000 1.1820
@@ -702,6 +702,7 @@ Patch1517: hdpvr-ir-enable.patch
# virt + ksm patches
Patch1551: linux-2.6-ksm-kvm.patch
+Patch1800: drm-2.6.30.patch
# nouveau + drm fixes
Patch1811: drm-radeon-fixes.patch
Patch1812: drm-radeon-dp-support.patch
@@ -1339,16 +1340,17 @@ ApplyPatch hdpvr-ir-enable.patch
ApplyPatch linux-2.6-e1000-ich9.patch
+ApplyPatch drm-2.6.30.patch
# Nouveau DRM + drm fixes
-ApplyPatch drm-radeon-fixes.patch
-ApplyPatch drm-radeon-dp-support.patch
-ApplyPatch drm-nouveau.patch
+#ApplyPatch drm-radeon-fixes.patch
+#ApplyPatch drm-radeon-dp-support.patch
+#ApplyPatch drm-nouveau.patch
# pm broken on my thinkpad t60p - airlied
#ApplyPatch drm-radeon-pm.patch
#ApplyPatch drm-i915-resume-force-mode.patch
-ApplyPatch drm-intel-big-hammer.patch
+#ApplyPatch drm-intel-big-hammer.patch
#ApplyPatch drm-page-flip.patch
-ApplyOptionalPatch drm-intel-next.patch
+#ApplyOptionalPatch drm-intel-next.patch
#this appears to be upstream - mjg59?
#ApplyPatch drm-intel-pm.patch
@@ -1372,7 +1374,8 @@ ApplyPatch linux-2.6-cantiga-iommu-gfx.p
# Patches for -stable
ApplyPatch fix-ima-null-ptr-deref.patch
-ApplyPatch vgaarb-fix-userspace-ptr-deref.patch
+#not backported. not a feature. not a concern.
+#ApplyPatch vgaarb-fix-userspace-ptr-deref.patch
# END OF PATCH APPLICATIONS ====================================================
@@ -2028,6 +2031,12 @@ fi
# and build.
%changelog
+* Mon Feb 22 2010 Kyle McMartin <kyle at redhat.com>
+- Forward port F-11-2.6.30 DRM to 2.6.32... remove VGA arbiter
+ since it didn't exist in release F-11. Clean up a bunch, fix up
+ a bunch of rejects, and build failures.
+ - It probably still won't work right, here's hoping.
+
* Mon Feb 22 2010 Chuck Ebbert <cebbert at redhat.com> 2.6.32.9-34.rc1
- Drop the PCI device table in the viafb driver -- it was added in
2.6.32 and we don't want the driver to autoload.
linux-2.6-upstream-reverts.patch:
drivers/gpu/drm/i915/i915_debugfs.c | 30 --------
drivers/gpu/drm/i915/i915_drv.h | 13 +++
drivers/gpu/drm/i915/i915_gem.c | 123 +++++++++++++++++++++++++++++++----
drivers/gpu/drm/i915/i915_reg.h | 15 ++++
drivers/gpu/drm/i915/i915_suspend.c | 5 +
drivers/gpu/drm/i915/intel_crt.c | 3
drivers/gpu/drm/i915/intel_display.c | 48 ++++++++++++-
drivers/gpu/drm/i915/intel_drv.h | 2
drivers/gpu/drm/i915/intel_fb.c | 2
drivers/gpu/drm/i915/intel_i2c.c | 19 +++++
drivers/gpu/drm/i915/intel_lvds.c | 23 ++++++
drivers/gpu/drm/radeon/atom.c | 2
include/drm/drm_os_linux.h | 2
13 files changed, 233 insertions(+), 54 deletions(-)
Index: linux-2.6-upstream-reverts.patch
===================================================================
RCS file: /cvs/pkgs/rpms/kernel/F-11/linux-2.6-upstream-reverts.patch,v
retrieving revision 1.11
retrieving revision 1.12
diff -u -p -r1.11 -r1.12
--- linux-2.6-upstream-reverts.patch 4 Jan 2010 15:25:49 -0000 1.11
+++ linux-2.6-upstream-reverts.patch 22 Feb 2010 23:17:14 -0000 1.12
@@ -1 +1,995 @@
-nil
+From 01d4503968f471f876fb44335800d2cf8dc5a2ce Mon Sep 17 00:00:00 2001
+From: Dave Airlie <airlied at redhat.com>
+Date: Sun, 31 Jan 2010 07:07:14 +1000
+Subject: drm/radeon/kms: use udelay for short delays
+
+From: Dave Airlie <airlied at redhat.com>
+
+commit 01d4503968f471f876fb44335800d2cf8dc5a2ce upstream.
+
+For usec delays use udelay instead of scheduling, this should
+allow reclocking to happen faster. This also was the cause
+of reported 33s delays at bootup on certain systems.
+
+fixes: freedesktop.org bug 25506
+
+Signed-off-by: Dave Airlie <airlied at redhat.com>
+Signed-off-by: Greg Kroah-Hartman <gregkh at suse.de>
+
+---
+ drivers/gpu/drm/radeon/atom.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/radeon/atom.c
++++ b/drivers/gpu/drm/radeon/atom.c
+@@ -607,7 +607,7 @@ static void atom_op_delay(atom_exec_cont
+ uint8_t count = U8((*ptr)++);
+ SDEBUG(" count: %d\n", count);
+ if (arg == ATOM_UNIT_MICROSEC)
+- schedule_timeout_uninterruptible(usecs_to_jiffies(count));
++ udelay(count);
+ else
+ schedule_timeout_uninterruptible(msecs_to_jiffies(count));
+ }
+From b9241ea31fae4887104e5d1b3b18f4009c25a0c4 Mon Sep 17 00:00:00 2001
+From: Zhenyu Wang <zhenyuw at linux.intel.com>
+Date: Wed, 25 Nov 2009 13:09:39 +0800
+Subject: drm/i915: Don't wait interruptible for possible plane buffer flush
+
+From: Zhenyu Wang <zhenyuw at linux.intel.com>
+
+commit b9241ea31fae4887104e5d1b3b18f4009c25a0c4 upstream.
+
+When we setup buffer for display plane, we'll check any pending
+required GPU flush and possible make interruptible wait for flush
+complete. But that wait would be most possibly to fail in case of
+signals received for X process, which will then fail modeset process
+and put display engine in unconsistent state. The result could be
+blank screen or CPU hang, and DDX driver would always turn on outputs
+DPMS after whatever modeset fails or not.
+
+So this one creates new helper for setup display plane buffer, and
+when needing flush using uninterruptible wait for that.
+
+This one should fix bug like https://bugs.freedesktop.org/show_bug.cgi?id=24009.
+Also fixing mode switch stress test on Ironlake.
+
+Signed-off-by: Zhenyu Wang <zhenyuw at linux.intel.com>
+Signed-off-by: Eric Anholt <eric at anholt.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh at suse.de>
+
+---
+ drivers/gpu/drm/i915/i915_drv.h | 1
+ drivers/gpu/drm/i915/i915_gem.c | 51 +++++++++++++++++++++++++++++++++++
+ drivers/gpu/drm/i915/intel_display.c | 2 -
+ 3 files changed, 53 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/i915/i915_drv.h
++++ b/drivers/gpu/drm/i915/i915_drv.h
+@@ -829,6 +829,7 @@ int i915_lp_ring_sync(struct drm_device
+ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
+ int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
+ int write);
++int i915_gem_object_set_to_display_plane(struct drm_gem_object *obj);
+ int i915_gem_attach_phys_object(struct drm_device *dev,
+ struct drm_gem_object *obj, int id);
+ void i915_gem_detach_phys_object(struct drm_device *dev,
+--- a/drivers/gpu/drm/i915/i915_gem.c
++++ b/drivers/gpu/drm/i915/i915_gem.c
+@@ -2825,6 +2825,57 @@ i915_gem_object_set_to_gtt_domain(struct
+ return 0;
+ }
+
++/*
++ * Prepare buffer for display plane. Use uninterruptible for possible flush
++ * wait, as in modesetting process we're not supposed to be interrupted.
++ */
++int
++i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
++{
++ struct drm_device *dev = obj->dev;
++ struct drm_i915_gem_object *obj_priv = obj->driver_private;
++ uint32_t old_write_domain, old_read_domains;
++ int ret;
++
++ /* Not valid to be called on unbound objects. */
++ if (obj_priv->gtt_space == NULL)
++ return -EINVAL;
++
++ i915_gem_object_flush_gpu_write_domain(obj);
++
++ /* Wait on any GPU rendering and flushing to occur. */
++ if (obj_priv->active) {
++#if WATCH_BUF
++ DRM_INFO("%s: object %p wait for seqno %08x\n",
++ __func__, obj, obj_priv->last_rendering_seqno);
++#endif
++ ret = i915_do_wait_request(dev, obj_priv->last_rendering_seqno, 0);
++ if (ret != 0)
++ return ret;
++ }
++
++ old_write_domain = obj->write_domain;
++ old_read_domains = obj->read_domains;
++
++ obj->read_domains &= I915_GEM_DOMAIN_GTT;
++
++ i915_gem_object_flush_cpu_write_domain(obj);
++
++ /* It should now be out of any other write domains, and we can update
++ * the domain values for our changes.
++ */
++ BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
++ obj->read_domains |= I915_GEM_DOMAIN_GTT;
++ obj->write_domain = I915_GEM_DOMAIN_GTT;
++ obj_priv->dirty = 1;
++
++ trace_i915_gem_object_change_domain(obj,
++ old_read_domains,
++ old_write_domain);
++
++ return 0;
++}
++
+ /**
+ * Moves a single object to the CPU read, and possibly write domain.
+ *
+--- a/drivers/gpu/drm/i915/intel_display.c
++++ b/drivers/gpu/drm/i915/intel_display.c
+@@ -1253,7 +1253,7 @@ intel_pipe_set_base(struct drm_crtc *crt
+ return ret;
+ }
+
+- ret = i915_gem_object_set_to_gtt_domain(obj, 1);
++ ret = i915_gem_object_set_to_display_plane(obj);
+ if (ret != 0) {
+ i915_gem_object_unpin(obj);
+ mutex_unlock(&dev->struct_mutex);
+From 48764bf43f746113fc77877d7e80f2df23ca4cbb Mon Sep 17 00:00:00 2001
+From: Daniel Vetter <daniel.vetter at ffwll.ch>
+Date: Tue, 15 Sep 2009 22:57:32 +0200
+Subject: drm/i915: add i915_lp_ring_sync helper
+
+From: Daniel Vetter <daniel.vetter at ffwll.ch>
+
+commit 48764bf43f746113fc77877d7e80f2df23ca4cbb upstream.
+
+This just waits until the hw passed the current ring position with
+cmd execution. This slightly changes the existing i915_wait_request
+function to make uninterruptible waiting possible - no point in
+returning to userspace while mucking around with the overlay, that
+piece of hw is just too fragile.
+
+Also replace a magic 0 with the symbolic constant (and kill the then
+superflous comment) while I was looking at the code.
+
+Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
+Signed-off-by: Eric Anholt <eric at anholt.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh at suse.de>
+
+---
+ drivers/gpu/drm/i915/i915_drv.h | 1
+ drivers/gpu/drm/i915/i915_gem.c | 49 +++++++++++++++++++++++++++++++---------
+ include/drm/drm_os_linux.h | 2 -
+ 3 files changed, 41 insertions(+), 11 deletions(-)
+
+--- a/drivers/gpu/drm/i915/i915_drv.h
++++ b/drivers/gpu/drm/i915/i915_drv.h
+@@ -825,6 +825,7 @@ void i915_gem_cleanup_ringbuffer(struct
+ int i915_gem_do_init(struct drm_device *dev, unsigned long start,
+ unsigned long end);
+ int i915_gem_idle(struct drm_device *dev);
++int i915_lp_ring_sync(struct drm_device *dev);
+ int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
+ int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
+ int write);
+--- a/drivers/gpu/drm/i915/i915_gem.c
++++ b/drivers/gpu/drm/i915/i915_gem.c
+@@ -1809,12 +1809,8 @@ i915_gem_retire_work_handler(struct work
+ mutex_unlock(&dev->struct_mutex);
+ }
+
+-/**
+- * Waits for a sequence number to be signaled, and cleans up the
+- * request and object lists appropriately for that event.
+- */
+ static int
+-i915_wait_request(struct drm_device *dev, uint32_t seqno)
++i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible)
+ {
+ drm_i915_private_t *dev_priv = dev->dev_private;
+ u32 ier;
+@@ -1841,10 +1837,15 @@ i915_wait_request(struct drm_device *dev
+
+ dev_priv->mm.waiting_gem_seqno = seqno;
+ i915_user_irq_get(dev);
+- ret = wait_event_interruptible(dev_priv->irq_queue,
+- i915_seqno_passed(i915_get_gem_seqno(dev),
+- seqno) ||
+- atomic_read(&dev_priv->mm.wedged));
++ if (interruptible)
++ ret = wait_event_interruptible(dev_priv->irq_queue,
++ i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
++ atomic_read(&dev_priv->mm.wedged));
++ else
++ wait_event(dev_priv->irq_queue,
++ i915_seqno_passed(i915_get_gem_seqno(dev), seqno) ||
++ atomic_read(&dev_priv->mm.wedged));
++
+ i915_user_irq_put(dev);
+ dev_priv->mm.waiting_gem_seqno = 0;
+
+@@ -1868,6 +1869,34 @@ i915_wait_request(struct drm_device *dev
+ return ret;
+ }
+
++/**
++ * Waits for a sequence number to be signaled, and cleans up the
++ * request and object lists appropriately for that event.
++ */
++static int
++i915_wait_request(struct drm_device *dev, uint32_t seqno)
++{
++ return i915_do_wait_request(dev, seqno, 1);
++}
++
++/**
++ * Waits for the ring to finish up to the latest request. Usefull for waiting
++ * for flip events, e.g for the overlay support. */
++int i915_lp_ring_sync(struct drm_device *dev)
++{
++ uint32_t seqno;
++ int ret;
++
++ seqno = i915_add_request(dev, NULL, 0);
++
++ if (seqno == 0)
++ return -ENOMEM;
++
++ ret = i915_do_wait_request(dev, seqno, 0);
++ BUG_ON(ret == -ERESTARTSYS);
++ return ret;
++}
++
+ static void
+ i915_gem_flush(struct drm_device *dev,
+ uint32_t invalidate_domains,
+@@ -1936,7 +1965,7 @@ i915_gem_flush(struct drm_device *dev,
+ #endif
+ BEGIN_LP_RING(2);
+ OUT_RING(cmd);
+- OUT_RING(0); /* noop */
++ OUT_RING(MI_NOOP);
+ ADVANCE_LP_RING();
+ }
+ }
+--- a/include/drm/drm_os_linux.h
++++ b/include/drm/drm_os_linux.h
+@@ -123,5 +123,5 @@ do { \
+ remove_wait_queue(&(queue), &entry); \
+ } while (0)
+
+-#define DRM_WAKEUP( queue ) wake_up_interruptible( queue )
++#define DRM_WAKEUP( queue ) wake_up( queue )
+ #define DRM_INIT_WAITQUEUE( queue ) init_waitqueue_head( queue )
+From 823f68fd646da6a39a9c0d3eb4c60d69dab5aa13 Mon Sep 17 00:00:00 2001
+From: Zhenyu Wang <zhenyuw at linux.intel.com>
+Date: Mon, 28 Dec 2009 13:23:36 +0800
+Subject: drm/i915: remove full registers dump debug
+
+From: Zhenyu Wang <zhenyuw at linux.intel.com>
+
+commit 823f68fd646da6a39a9c0d3eb4c60d69dab5aa13 upstream.
+
+This one reverts 9e3a6d155ed0a7636b926a798dd7221ea107b274.
+As reported by http://bugzilla.kernel.org/show_bug.cgi?id=14485,
+this dump will cause hang problem on some machine. If something
+really needs this kind of full registers dump, that could be done
+within intel-gpu-tools.
+
+Cc: Ben Gamari <bgamari.foss at gmail.com>
+Signed-off-by: Zhenyu Wang <zhenyuw at linux.intel.com>
+Signed-off-by: Eric Anholt <eric at anholt.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh at suse.de>
+
+
+---
+ drivers/gpu/drm/i915/i915_debugfs.c | 30 ------------------------------
+ 1 file changed, 30 deletions(-)
+
+--- a/drivers/gpu/drm/i915/i915_debugfs.c
++++ b/drivers/gpu/drm/i915/i915_debugfs.c
+@@ -384,37 +384,7 @@ out:
+ return 0;
+ }
+
+-static int i915_registers_info(struct seq_file *m, void *data) {
+- struct drm_info_node *node = (struct drm_info_node *) m->private;
+- struct drm_device *dev = node->minor->dev;
+- drm_i915_private_t *dev_priv = dev->dev_private;
+- uint32_t reg;
+-
+-#define DUMP_RANGE(start, end) \
+- for (reg=start; reg < end; reg += 4) \
+- seq_printf(m, "%08x\t%08x\n", reg, I915_READ(reg));
+-
+- DUMP_RANGE(0x00000, 0x00fff); /* VGA registers */
+- DUMP_RANGE(0x02000, 0x02fff); /* instruction, memory, interrupt control registers */
+- DUMP_RANGE(0x03000, 0x031ff); /* FENCE and PPGTT control registers */
+- DUMP_RANGE(0x03200, 0x03fff); /* frame buffer compression registers */
+- DUMP_RANGE(0x05000, 0x05fff); /* I/O control registers */
+- DUMP_RANGE(0x06000, 0x06fff); /* clock control registers */
+- DUMP_RANGE(0x07000, 0x07fff); /* 3D internal debug registers */
+- DUMP_RANGE(0x07400, 0x088ff); /* GPE debug registers */
+- DUMP_RANGE(0x0a000, 0x0afff); /* display palette registers */
+- DUMP_RANGE(0x10000, 0x13fff); /* MMIO MCHBAR */
+- DUMP_RANGE(0x30000, 0x3ffff); /* overlay registers */
+- DUMP_RANGE(0x60000, 0x6ffff); /* display engine pipeline registers */
+- DUMP_RANGE(0x70000, 0x72fff); /* display and cursor registers */
+- DUMP_RANGE(0x73000, 0x73fff); /* performance counters */
+-
+- return 0;
+-}
+-
+-
+ static struct drm_info_list i915_debugfs_list[] = {
+- {"i915_regs", i915_registers_info, 0},
+ {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
+ {"i915_gem_flushing", i915_gem_object_list_info, 0, (void *) FLUSHING_LIST},
+ {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
+From 99fcb766a3a50466fe31d743260a3400c1aee855 Mon Sep 17 00:00:00 2001
+From: Daniel Vetter <daniel.vetter at ffwll.ch>
+Date: Sun, 7 Feb 2010 16:20:18 +0100
+Subject: drm/i915: Update write_domains on active list after flush.
+
+From: Daniel Vetter <daniel.vetter at ffwll.ch>
+
+commit 99fcb766a3a50466fe31d743260a3400c1aee855 upstream.
+
+Before changing the status of a buffer with a pending write we will await
+upon a new flush for that buffer. So we can take advantage of any flushes
+posted whilst the buffer is active and pending processing by the GPU, by
+clearing its write_domain and updating its last_rendering_seqno -- thus
+saving a potential flush in deep queues and improves flushing behaviour
+upon eviction for both GTT space and fences.
+
+In order to reduce the time spent searching the active list for matching
+write_domains, we move those to a separate list whose elements are
+the buffers belong to the active/flushing list with pending writes.
+
+Orignal patch by Chris Wilson <chris at chris-wilson.co.uk>, forward-ported
+by me.
+
+In addition to better performance, this also fixes a real bug. Before
+this changes, i915_gem_evict_everything didn't work as advertised. When
+the gpu was actually busy and processing request, the flush and subsequent
+wait would not move active and dirty buffers to the inactive list, but
+just to the flushing list. Which triggered the BUG_ON at the end of this
+function. With the more tight dirty buffer tracking, all currently busy and
+dirty buffers get moved to the inactive list by one i915_gem_flush operation.
+
+I've left the BUG_ON I've used to prove this in there.
+
+References:
+ Bug 25911 - 2.10.0 causes kernel oops and system hangs
+ http://bugs.freedesktop.org/show_bug.cgi?id=25911
+
+ Bug 26101 - [i915] xf86-video-intel 2.10.0 (and git) triggers kernel oops
+ within seconds after login
+ http://bugs.freedesktop.org/show_bug.cgi?id=26101
+
+Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
+Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
+Tested-by: Adam Lantos <hege at playma.org>
+Signed-off-by: Eric Anholt <eric at anholt.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh at suse.de>
+
+---
+ drivers/gpu/drm/i915/i915_drv.h | 11 +++++++++++
+ drivers/gpu/drm/i915/i915_gem.c | 23 +++++++++++++++++++----
+ 2 files changed, 30 insertions(+), 4 deletions(-)
+
+--- a/drivers/gpu/drm/i915/i915_drv.h
++++ b/drivers/gpu/drm/i915/i915_drv.h
+@@ -467,6 +467,15 @@ typedef struct drm_i915_private {
+ struct list_head flushing_list;
+
+ /**
++ * List of objects currently pending a GPU write flush.
++ *
++ * All elements on this list will belong to either the
++ * active_list or flushing_list, last_rendering_seqno can
++ * be used to differentiate between the two elements.
++ */
++ struct list_head gpu_write_list;
++
++ /**
+ * LRU list of objects which are not in the ringbuffer and
+ * are ready to unbind, but are still in the GTT.
+ *
+@@ -558,6 +567,8 @@ struct drm_i915_gem_object {
+
+ /** This object's place on the active/flushing/inactive lists */
+ struct list_head list;
++ /** This object's place on GPU write list */
++ struct list_head gpu_write_list;
+
+ /** This object's place on the fenced object LRU */
+ struct list_head fence_list;
+--- a/drivers/gpu/drm/i915/i915_gem.c
++++ b/drivers/gpu/drm/i915/i915_gem.c
+@@ -1552,6 +1552,8 @@ i915_gem_object_move_to_inactive(struct
+ else
+ list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
+
++ BUG_ON(!list_empty(&obj_priv->gpu_write_list));
++
+ obj_priv->last_rendering_seqno = 0;
+ if (obj_priv->active) {
+ obj_priv->active = 0;
+@@ -1622,7 +1624,8 @@ i915_add_request(struct drm_device *dev,
+ struct drm_i915_gem_object *obj_priv, *next;
+
+ list_for_each_entry_safe(obj_priv, next,
+- &dev_priv->mm.flushing_list, list) {
++ &dev_priv->mm.gpu_write_list,
++ gpu_write_list) {
+ struct drm_gem_object *obj = obj_priv->obj;
+
+ if ((obj->write_domain & flush_domains) ==
+@@ -1630,6 +1633,7 @@ i915_add_request(struct drm_device *dev,
+ uint32_t old_write_domain = obj->write_domain;
+
+ obj->write_domain = 0;
++ list_del_init(&obj_priv->gpu_write_list);
+ i915_gem_object_move_to_active(obj, seqno);
+
+ trace_i915_gem_object_change_domain(obj,
+@@ -2073,8 +2077,8 @@ static int
+ i915_gem_evict_everything(struct drm_device *dev)
+ {
+ drm_i915_private_t *dev_priv = dev->dev_private;
+- uint32_t seqno;
+ int ret;
++ uint32_t seqno;
+ bool lists_empty;
+
+ spin_lock(&dev_priv->mm.active_list_lock);
+@@ -2096,6 +2100,8 @@ i915_gem_evict_everything(struct drm_dev
+ if (ret)
+ return ret;
+
++ BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
++
+ ret = i915_gem_evict_from_inactive_list(dev);
+ if (ret)
+ return ret;
+@@ -2690,7 +2696,7 @@ i915_gem_object_flush_gpu_write_domain(s
+ old_write_domain = obj->write_domain;
+ i915_gem_flush(dev, 0, obj->write_domain);
+ seqno = i915_add_request(dev, NULL, obj->write_domain);
+- obj->write_domain = 0;
++ BUG_ON(obj->write_domain);
+ i915_gem_object_move_to_active(obj, seqno);
+
+ trace_i915_gem_object_change_domain(obj,
+@@ -3710,16 +3716,23 @@ i915_gem_execbuffer(struct drm_device *d
+ i915_gem_flush(dev,
+ dev->invalidate_domains,
+ dev->flush_domains);
+- if (dev->flush_domains)
++ if (dev->flush_domains & I915_GEM_GPU_DOMAINS)
+ (void)i915_add_request(dev, file_priv,
+ dev->flush_domains);
+ }
+
+ for (i = 0; i < args->buffer_count; i++) {
+ struct drm_gem_object *obj = object_list[i];
++ struct drm_i915_gem_object *obj_priv = obj->driver_private;
+ uint32_t old_write_domain = obj->write_domain;
+
+ obj->write_domain = obj->pending_write_domain;
++ if (obj->write_domain)
++ list_move_tail(&obj_priv->gpu_write_list,
++ &dev_priv->mm.gpu_write_list);
++ else
++ list_del_init(&obj_priv->gpu_write_list);
++
+ trace_i915_gem_object_change_domain(obj,
+ obj->read_domains,
+ old_write_domain);
+@@ -4112,6 +4125,7 @@ int i915_gem_init_object(struct drm_gem_
+ obj_priv->obj = obj;
+ obj_priv->fence_reg = I915_FENCE_REG_NONE;
+ INIT_LIST_HEAD(&obj_priv->list);
++ INIT_LIST_HEAD(&obj_priv->gpu_write_list);
+ INIT_LIST_HEAD(&obj_priv->fence_list);
+ obj_priv->madv = I915_MADV_WILLNEED;
+
+@@ -4563,6 +4577,7 @@ i915_gem_load(struct drm_device *dev)
+ spin_lock_init(&dev_priv->mm.active_list_lock);
+ INIT_LIST_HEAD(&dev_priv->mm.active_list);
+ INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
++ INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
+ INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
+ INIT_LIST_HEAD(&dev_priv->mm.request_list);
+ INIT_LIST_HEAD(&dev_priv->mm.fence_list);
+From fd2e8ea597222b8f38ae8948776a61ea7958232e Mon Sep 17 00:00:00 2001
+From: Chris Wilson <chris at chris-wilson.co.uk>
+Date: Tue, 9 Feb 2010 14:14:36 +0000
+Subject: drm/i915: Increase fb alignment to 64k
+
+From: Chris Wilson <chris at chris-wilson.co.uk>
+
+commit fd2e8ea597222b8f38ae8948776a61ea7958232e upstream.
+
+An untiled framebuffer must be aligned to 64k. This is normally handled
+by intel_pin_and_fence_fb_obj(), but the intelfb_create() likes to be
+different and do the pinning itself. However, it aligns the buffer
+object incorrectly for pre-i965 chipsets causing a PGTBL_ERR when it is
+installed onto the output.
+
+Fixes:
+ KMS error message while initializing modesetting -
+ render error detected: EIR: 0x10 [i915]
+ http://bugs.freedesktop.org/show_bug.cgi?id=22936
+
+Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
+Signed-off-by: Eric Anholt <eric at anholt.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh at suse.de>
+
+---
+ drivers/gpu/drm/i915/intel_fb.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/i915/intel_fb.c
++++ b/drivers/gpu/drm/i915/intel_fb.c
+@@ -148,7 +148,7 @@ static int intelfb_create(struct drm_dev
+
+ mutex_lock(&dev->struct_mutex);
+
+- ret = i915_gem_object_pin(fbo, PAGE_SIZE);
++ ret = i915_gem_object_pin(fbo, 64*1024);
+ if (ret) {
+ DRM_ERROR("failed to pin fb: %d\n", ret);
+ goto out_unref;
+From ee25df2bc379728c45d81e04cf87984db1425edf Mon Sep 17 00:00:00 2001
+From: Jesse Barnes <jbarnes at virtuousgeek.org>
+Date: Sat, 6 Feb 2010 10:41:53 -0800
+Subject: drm/i915: handle FBC and self-refresh better
+
+From: Jesse Barnes <jbarnes at virtuousgeek.org>
+
+commit ee25df2bc379728c45d81e04cf87984db1425edf upstream.
+
+On 945, we need to avoid entering self-refresh if the compressor is
+busy, or we may cause display FIFO underruns leading to ugly flicker.
+
+Fixes fdo bug #24314, kernel bug #15043.
+
+Tested-by: Alexander Lam <lambchop468 at gmail.com>
+Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
+Tested-by: Julien Cristau <jcristau at debian.org> (fd.o #25371)
+Signed-off-by: Eric Anholt <eric at anholt.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh at suse.de>
+
+---
+ drivers/gpu/drm/i915/i915_reg.h | 1 +
+ drivers/gpu/drm/i915/intel_display.c | 2 ++
+ 2 files changed, 3 insertions(+)
+
+--- a/drivers/gpu/drm/i915/i915_reg.h
++++ b/drivers/gpu/drm/i915/i915_reg.h
+@@ -329,6 +329,7 @@
+ #define FBC_CTL_PERIODIC (1<<30)
+ #define FBC_CTL_INTERVAL_SHIFT (16)
+ #define FBC_CTL_UNCOMPRESSIBLE (1<<14)
++#define FBC_C3_IDLE (1<<13)
+ #define FBC_CTL_STRIDE_SHIFT (5)
+ #define FBC_CTL_FENCENO (1<<0)
+ #define FBC_COMMAND 0x0320c
+--- a/drivers/gpu/drm/i915/intel_display.c
++++ b/drivers/gpu/drm/i915/intel_display.c
+@@ -988,6 +988,8 @@ static void i8xx_enable_fbc(struct drm_c
+
+ /* enable it... */
+ fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
++ if (IS_I945GM(dev))
++ fbc_ctl |= FBC_C3_IDLE; /* 945 needs special SR handling */
+ fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
+ fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
+ if (obj_priv->tiling_mode != I915_TILING_NONE)
+From a3cb5195f6db58dbebd8a31b877ddce082c9b63d Mon Sep 17 00:00:00 2001
+From: Zhao Yakui <yakui.zhao at intel.com>
+Date: Fri, 11 Dec 2009 09:26:10 +0800
+Subject: drm/i915: Add MALATA PC-81005 to ACPI LID quirk list
+
+From: Zhao Yakui <yakui.zhao at intel.com>
+
+commit a3cb5195f6db58dbebd8a31b877ddce082c9b63d upstream.
+
+The MALATA PC-81005 laptop always reports that the LID status is closed and we
+can't use it reliabily for LVDS detection. So add this box into the quirk list.
+
+https://bugs.freedesktop.org/show_bug.cgi?id=25523
+
+Signed-off-by: Zhao Yakui <yakui.zhao at intel.com>
+Review-by: Jesse Barnes <jbarnes at virtuousgeek.org>
+Tested-by: Hector <hector1987 at gmail.com>
+Signed-off-by: Eric Anholt <eric at anholt.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh at suse.de>
+
+---
+ drivers/gpu/drm/i915/intel_lvds.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/drivers/gpu/drm/i915/intel_lvds.c
++++ b/drivers/gpu/drm/i915/intel_lvds.c
+@@ -622,6 +622,13 @@ static const struct dmi_system_id bad_li
+ DMI_MATCH(DMI_PRODUCT_NAME, "Aspire one"),
+ },
+ },
++ {
++ .ident = "PC-81005",
++ .matches = {
++ DMI_MATCH(DMI_SYS_VENDOR, "MALATA"),
++ DMI_MATCH(DMI_PRODUCT_NAME, "PC-81005"),
++ },
++ },
+ { }
+ };
+
+From f034b12dbb5749b11e9390e15e93ffa87ece8038 Mon Sep 17 00:00:00 2001
+From: Zhao Yakui <yakui.zhao at intel.com>
+Date: Thu, 21 Jan 2010 15:20:18 +0800
+Subject: drm/i915: Fix the incorrect DMI string for Samsung SX20S laptop
+
+From: Zhao Yakui <yakui.zhao at intel.com>
+
+commit f034b12dbb5749b11e9390e15e93ffa87ece8038 upstream.
+
+Signed-off-by: Zhao Yakui <yakui.zhao at intel.com>
+Reported-by: Philipp Kohlbecher <xt28 at gmx.de>
+Signed-off-by: Eric Anholt <eric at anholt.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh at suse.de>
+
+---
+ drivers/gpu/drm/i915/intel_lvds.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/i915/intel_lvds.c
++++ b/drivers/gpu/drm/i915/intel_lvds.c
+@@ -611,7 +611,7 @@ static const struct dmi_system_id bad_li
+ {
+ .ident = "Samsung SX20S",
+ .matches = {
+- DMI_MATCH(DMI_SYS_VENDOR, "Phoenix Technologies LTD"),
++ DMI_MATCH(DMI_SYS_VENDOR, "Samsung Electronics"),
+ DMI_MATCH(DMI_BOARD_NAME, "SX20S"),
+ },
+ },
+From 40f33a92100f4d9b6e85ad642100cfe42d7ff57d Mon Sep 17 00:00:00 2001
+From: Zhao Yakui <yakui.zhao at intel.com>
+Date: Wed, 6 Jan 2010 13:30:36 +0800
+Subject: drm/i915: Add HP nx9020/SamsungSX20S to ACPI LID quirk list
+
+From: Zhao Yakui <yakui.zhao at intel.com>
+
+commit 40f33a92100f4d9b6e85ad642100cfe42d7ff57d upstream.
+
+The HP comaq nx9020/Samsung SX20S laptop always report that the LID status is
+closed and we can't use it reliabily for LVDS detection. So add the two boxes
+into the quirk list.
+
+http://bugzilla.kernel.org/show_bug.cgi?id=14957
+http://bugzilla.kernel.org/show_bug.cgi?id=14554
+
+Signed-off-by: Zhao Yakui <yakui.zhao at intel.com>
+Signed-off-by: Eric Anholt <eric at anholt.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh at suse.de>
+
+---
+ drivers/gpu/drm/i915/intel_lvds.c | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+--- a/drivers/gpu/drm/i915/intel_lvds.c
++++ b/drivers/gpu/drm/i915/intel_lvds.c
+@@ -602,6 +602,20 @@ static void intel_lvds_mode_set(struct d
+ /* Some lid devices report incorrect lid status, assume they're connected */
+ static const struct dmi_system_id bad_lid_status[] = {
+ {
++ .ident = "Compaq nx9020",
++ .matches = {
++ DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
++ DMI_MATCH(DMI_BOARD_NAME, "3084"),
++ },
++ },
++ {
++ .ident = "Samsung SX20S",
++ .matches = {
++ DMI_MATCH(DMI_SYS_VENDOR, "Phoenix Technologies LTD"),
++ DMI_MATCH(DMI_BOARD_NAME, "SX20S"),
++ },
++ },
++ {
+ .ident = "Aspire One",
+ .matches = {
+ DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
+From f0217c42c9ab3d772e543f635ce628b9478f70b6 Mon Sep 17 00:00:00 2001
+From: Eric Anholt <eric at anholt.net>
+Date: Tue, 1 Dec 2009 11:56:30 -0800
+Subject: drm/i915: Fix DDC on some systems by clearing BIOS GMBUS setup.
+
+From: Eric Anholt <eric at anholt.net>
+
+commit f0217c42c9ab3d772e543f635ce628b9478f70b6 upstream.
+
+This is a sync of a fix I made in the old UMS code. If the BIOS uses
+the GMBUS and doesn't clear that setup, then our bit-banging I2C can
+fail, leading to monitors not being detected.
+
+Signed-off-by: Eric Anholt <eric at anholt.net>
+Cc: maximilian attems <max at stro.at>
+Signed-off-by: Greg Kroah-Hartman <gregkh at suse.de>
+
+---
+ drivers/gpu/drm/i915/i915_reg.h | 14 ++++++++++++++
+ drivers/gpu/drm/i915/i915_suspend.c | 5 ++++-
+ drivers/gpu/drm/i915/intel_drv.h | 2 ++
+ drivers/gpu/drm/i915/intel_i2c.c | 19 +++++++++++++++++++
+ 4 files changed, 39 insertions(+), 1 deletion(-)
+
+--- a/drivers/gpu/drm/i915/i915_reg.h
++++ b/drivers/gpu/drm/i915/i915_reg.h
+@@ -405,6 +405,13 @@
+ # define GPIO_DATA_VAL_IN (1 << 12)
+ # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
+
++#define GMBUS0 0x5100
++#define GMBUS1 0x5104
++#define GMBUS2 0x5108
++#define GMBUS3 0x510c
++#define GMBUS4 0x5110
++#define GMBUS5 0x5120
++
+ /*
+ * Clock control & power management
+ */
+@@ -2153,6 +2160,13 @@
+ #define PCH_GPIOE 0xc5020
+ #define PCH_GPIOF 0xc5024
+
++#define PCH_GMBUS0 0xc5100
++#define PCH_GMBUS1 0xc5104
++#define PCH_GMBUS2 0xc5108
++#define PCH_GMBUS3 0xc510c
++#define PCH_GMBUS4 0xc5110
++#define PCH_GMBUS5 0xc5120
++
+ #define PCH_DPLL_A 0xc6014
+ #define PCH_DPLL_B 0xc6018
+
+--- a/drivers/gpu/drm/i915/i915_suspend.c
++++ b/drivers/gpu/drm/i915/i915_suspend.c
+@@ -27,7 +27,7 @@
+ #include "drmP.h"
+ #include "drm.h"
+ #include "i915_drm.h"
+-#include "i915_drv.h"
++#include "intel_drv.h"
+
+ static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
+ {
+@@ -846,6 +846,9 @@ int i915_restore_state(struct drm_device
+ for (i = 0; i < 3; i++)
+ I915_WRITE(SWF30 + (i << 2), dev_priv->saveSWF2[i]);
+
++ /* I2C state */
++ intel_i2c_reset_gmbus(dev);
++
+ return 0;
+ }
+
+--- a/drivers/gpu/drm/i915/intel_drv.h
++++ b/drivers/gpu/drm/i915/intel_drv.h
+@@ -134,6 +134,8 @@ void intel_i2c_destroy(struct i2c_adapte
+ int intel_ddc_get_modes(struct intel_output *intel_output);
+ extern bool intel_ddc_probe(struct intel_output *intel_output);
+ void intel_i2c_quirk_set(struct drm_device *dev, bool enable);
++void intel_i2c_reset_gmbus(struct drm_device *dev);
++
+ extern void intel_crt_init(struct drm_device *dev);
+ extern void intel_hdmi_init(struct drm_device *dev, int sdvox_reg);
+ extern bool intel_sdvo_init(struct drm_device *dev, int output_device);
+--- a/drivers/gpu/drm/i915/intel_i2c.c
++++ b/drivers/gpu/drm/i915/intel_i2c.c
+@@ -118,6 +118,23 @@ static void set_data(void *data, int sta
+ udelay(I2C_RISEFALL_TIME); /* wait for the line to change state */
+ }
+
++/* Clears the GMBUS setup. Our driver doesn't make use of the GMBUS I2C
++ * engine, but if the BIOS leaves it enabled, then that can break our use
++ * of the bit-banging I2C interfaces. This is notably the case with the
++ * Mac Mini in EFI mode.
++ */
++void
++intel_i2c_reset_gmbus(struct drm_device *dev)
++{
++ struct drm_i915_private *dev_priv = dev->dev_private;
++
++ if (IS_IGDNG(dev)) {
++ I915_WRITE(PCH_GMBUS0, 0);
++ } else {
++ I915_WRITE(GMBUS0, 0);
++ }
++}
++
+ /**
+ * intel_i2c_create - instantiate an Intel i2c bus using the specified GPIO reg
+ * @dev: DRM device
+@@ -168,6 +185,8 @@ struct i2c_adapter *intel_i2c_create(str
+ if(i2c_bit_add_bus(&chan->adapter))
+ goto out_free;
+
++ intel_i2c_reset_gmbus(dev);
++
+ /* JJJ: raise SCL and SDA? */
+ intel_i2c_quirk_set(dev, true);
+ set_data(chan, 1);
+From 33c5fd121eabbccc9103daf6cda36941eb3c349f Mon Sep 17 00:00:00 2001
+From: David John <davidjon at xenontk.org>
+Date: Wed, 27 Jan 2010 15:19:08 +0530
+Subject: drm/i915: Disable SR when more than one pipe is enabled
+
+From: David John <davidjon at xenontk.org>
+
+commit 33c5fd121eabbccc9103daf6cda36941eb3c349f upstream.
+
+Self Refresh should be disabled on dual plane configs. Otherwise, as
+the SR watermark is not calculated for such configs, switching to non
+VGA mode causes FIFO underrun and display flicker.
+
+This fixes Korg Bug #14897.
+
+Signed-off-by: David John <davidjon at xenontk.org>
+Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
+Signed-off-by: Eric Anholt <eric at anholt.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh at suse.de>
+
+---
+ drivers/gpu/drm/i915/intel_display.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+--- a/drivers/gpu/drm/i915/intel_display.c
++++ b/drivers/gpu/drm/i915/intel_display.c
+@@ -2538,6 +2538,10 @@ static void g4x_update_wm(struct drm_dev
+ sr_entries = roundup(sr_entries / cacheline_size, 1);
+ DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
+ I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
++ } else {
++ /* Turn off self refresh if both pipes are enabled */
++ I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
++ & ~FW_BLC_SELF_EN);
+ }
+
+ DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
+@@ -2581,6 +2585,10 @@ static void i965_update_wm(struct drm_de
+ srwm = 1;
+ srwm &= 0x3f;
+ I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
++ } else {
++ /* Turn off self refresh if both pipes are enabled */
++ I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
++ & ~FW_BLC_SELF_EN);
+ }
+
+ DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
+@@ -2649,6 +2657,10 @@ static void i9xx_update_wm(struct drm_de
+ if (srwm < 0)
+ srwm = 1;
+ I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
++ } else {
++ /* Turn off self refresh if both pipes are enabled */
++ I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
++ & ~FW_BLC_SELF_EN);
+ }
+
+ DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
+From 1dc7546d1a73664e5d117715b214bea9cae5951c Mon Sep 17 00:00:00 2001
+From: Jesse Barnes <jbarnes at jbarnes-x200.(none)>
+Date: Mon, 19 Oct 2009 10:08:17 +0900
+Subject: drm/i915: enable self-refresh on 965
+
+From: Jesse Barnes <jbarnes at jbarnes-x200.(none)>
+
+commit 1dc7546d1a73664e5d117715b214bea9cae5951c upstream.
+
+Need to calculate the SR watermark and enable it.
+
+Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
+Signed-off-by: Eric Anholt <eric at anholt.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh at suse.de>
+
+---
+ drivers/gpu/drm/i915/intel_display.c | 32 ++++++++++++++++++++++++++++----
+ 1 file changed, 28 insertions(+), 4 deletions(-)
+
+--- a/drivers/gpu/drm/i915/intel_display.c
++++ b/drivers/gpu/drm/i915/intel_display.c
+@@ -2556,15 +2556,39 @@ static void g4x_update_wm(struct drm_dev
+ (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
+ }
+
+-static void i965_update_wm(struct drm_device *dev, int unused, int unused2,
+- int unused3, int unused4)
++static void i965_update_wm(struct drm_device *dev, int planea_clock,
++ int planeb_clock, int sr_hdisplay, int pixel_size)
+ {
+ struct drm_i915_private *dev_priv = dev->dev_private;
++ unsigned long line_time_us;
++ int sr_clock, sr_entries, srwm = 1;
+
+- DRM_DEBUG("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 8\n");
++ /* Calc sr entries for one plane configs */
++ if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
++ /* self-refresh has much higher latency */
++ const static int sr_latency_ns = 12000;
++
++ sr_clock = planea_clock ? planea_clock : planeb_clock;
++ line_time_us = ((sr_hdisplay * 1000) / sr_clock);
++
++ /* Use ns/us then divide to preserve precision */
++ sr_entries = (((sr_latency_ns / line_time_us) + 1) *
++ pixel_size * sr_hdisplay) / 1000;
++ sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
++ DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
++ srwm = I945_FIFO_SIZE - sr_entries;
++ if (srwm < 0)
++ srwm = 1;
++ srwm &= 0x3f;
++ I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
++ }
++
++ DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
++ srwm);
+
+ /* 965 has limitations... */
+- I915_WRITE(DSPFW1, (8 << 16) | (8 << 8) | (8 << 0));
++ I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
++ (8 << 0));
+ I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
+ }
+
+From eceb784cec4dc0fcc2993d9ee4a7c0d111ada80a Mon Sep 17 00:00:00 2001
+From: Zhenyu Wang <zhenyuw at linux.intel.com>
+Date: Mon, 25 Jan 2010 10:35:16 +0800
+Subject: drm/i915: disable hotplug detect before Ironlake CRT detect
+
+From: Zhenyu Wang <zhenyuw at linux.intel.com>
+
+commit eceb784cec4dc0fcc2993d9ee4a7c0d111ada80a upstream.
+
+This tries to fix CRT detect loop hang seen on some Ironlake form
+factor, to clear up hotplug detect state before taking CRT detect
+to make sure next hotplug detect cycle is consistent.
+
+Signed-off-by: Zhenyu Wang <zhenyuw at linux.intel.com>
+Signed-off-by: Eric Anholt <eric at anholt.net>
+Signed-off-by: Greg Kroah-Hartman <gregkh at suse.de>
+
+---
+ drivers/gpu/drm/i915/intel_crt.c | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/drivers/gpu/drm/i915/intel_crt.c
++++ b/drivers/gpu/drm/i915/intel_crt.c
+@@ -185,6 +185,9 @@ static bool intel_igdng_crt_detect_hotpl
+ adpa = I915_READ(PCH_ADPA);
+
+ adpa &= ~ADPA_CRT_HOTPLUG_MASK;
++ /* disable HPD first */
++ I915_WRITE(PCH_ADPA, adpa);
++ (void)I915_READ(PCH_ADPA);
+
+ adpa |= (ADPA_CRT_HOTPLUG_PERIOD_128 |
+ ADPA_CRT_HOTPLUG_WARMUP_10MS |
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