[kernel/f15] drm-radeon-update2.patch: more radeon updates + cayman accel support
Dave Airlie
airlied at fedoraproject.org
Thu May 26 02:48:37 UTC 2011
commit f6fc553f93ef953a159f59e9e0c176b8ecbd4860
Author: Dave Airlie <airlied at redhat.com>
Date: Wed May 25 22:48:20 2011 -0400
drm-radeon-update2.patch: more radeon updates + cayman accel support
drm-radeon-update2.patch | 1708 ++++++++++++++++++++++++++++++++++++++++++++++
kernel.spec | 5 +
2 files changed, 1713 insertions(+), 0 deletions(-)
---
diff --git a/drm-radeon-update2.patch b/drm-radeon-update2.patch
new file mode 100644
index 0000000..1224c0f
--- /dev/null
+++ b/drm-radeon-update2.patch
@@ -0,0 +1,1708 @@
+commit 05d1ee2878c955f7cf4254ed7f94bd65758f9208
+Author: Alex Deucher <alexdeucher at gmail.com>
+Date: Wed May 25 01:00:45 2011 -0400
+
+ drm/radeon/kms/blit: workaround some hw issues on evergreen+
+
+ Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit e520c516656b3c361ebf8add4e00428b7c37afd6
+Author: Alex Deucher <alexdeucher at gmail.com>
+Date: Wed May 25 16:39:00 2011 -0400
+
+ drm/radeon/kms: add blit support for cayman (v2)
+
+ Allows us to use the 3D engine for memory management
+ and allows us to use vram beyond the BAR aperture.
+
+ v2: fix copy paste typo
+ Reported-by: Nils Wallménius <nils.wallmenius at gmail.com>
+
+ Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit e1b12b63f9df3a5480972c21f504163b36ceaa88
+Author: Alex Deucher <alexdeucher at gmail.com>
+Date: Wed May 25 18:45:37 2011 -0400
+
+ drm/radeon/kms: fix thermal sensor reading on juniper
+
+ Uses a different method than other evergreen asics.
+
+ Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit 46f21922e84d074158781368eee24727a60f9d32
+Author: Alex Deucher <alexdeucher at gmail.com>
+Date: Wed May 25 17:49:54 2011 -0400
+
+ drm/radeon/kms: add missing case for cayman thermal sensor
+
+ The rest of the code is already in place.
+
+ Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit 8cc42a1f51ada532c76009fd8b3261d5e7e8f02b
+Author: Alex Deucher <alexdeucher at gmail.com>
+Date: Fri May 20 12:35:23 2011 -0400
+
+ drm/radeon/kms: bump kms version number
+
+ - proper bank size for fusion for 2D tiling.
+
+ Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit e0014e347d1d15e12c5beffd6af9d22a8d495969
+Author: Alex Deucher <alexdeucher at gmail.com>
+Date: Fri May 20 12:35:22 2011 -0400
+
+ drm/radeon/kms: properly set num banks for fusion asics
+
+ Needed by userspace for 2D tiled buffer alignment
+
+ Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit 48c7304eb2af97b6e50a93e22b656c9f3ead5f90
+Author: Alex Deucher <alexdeucher at gmail.com>
+Date: Mon May 23 14:22:26 2011 -0400
+
+ drm/radeon/kms/cayman: fix typo in register mask
+
+ Noticed by Droste on IRC.
+
+ Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit 13e5c224cdd62fc3d454f1ef6d8157181ade07d9
+Author: Dave Airlie <airlied at redhat.com>
+Date: Thu May 19 14:14:41 2011 +1000
+
+ drm/radeon/kms: fix tile_config value reported to userspace on cayman.
+
+ cayman is reporting the wrong tile config value to userspace, this
+ causes piglit mipmap generation tests to fail.
+
+ Reviewed-by: Alex Deucher <alexdeucher at gmail.com>
+ cc: stable at kernel.org
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit a9b83345a9c37d3bdea30be5a7d0cd34a0f28a68
+Author: Dave Airlie <airlied at redhat.com>
+Date: Thu May 19 14:14:40 2011 +1000
+
+ drm/radeon/kms: fix incorrect comparison in cayman setup code.
+
+ This was leading to a bogus value being programmed to the backend
+ routing register.
+
+ Reviewed-by: Alex Deucher <alexdeucher at gmail.com>
+ cc: stable at kernel.org
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit 4f71384abcb866214a927510d7e315ad00692faa
+Author: Dave Airlie <airlied at redhat.com>
+Date: Thu May 19 14:14:43 2011 +1000
+
+ drm/radeon/kms: add wait idle ioctl for eg->cayman
+
+ None of the latest GPUs had this hooked up, this is necessary for
+ correct operation in a lot of cases, however we should test this on a few
+ GPUs in these families as we've had problems in this area before.
+
+ Reviewed-by: Alex Deucher <alexdeucher at gmail.com>
+ cc: stable at kernel.org
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit 0676d9dc1e66566af98e1192a041c9e983a69eaf
+Author: Dave Airlie <airlied at redhat.com>
+Date: Thu May 19 14:14:42 2011 +1000
+
+ drm/radeon/cayman: setup hdp to invalidate and flush when asked
+
+ On cayman we need to set the bit to cause HDP flushes to invalidate the
+ HDP cache also.
+
+ Reviewed-by: Alex Deucher <alexdeucher at gmail.com>
+ cc: stable at kernel.org
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit 5e9df070bdc59db0b8718b8e2e6a387e49acda7c
+Author: Alex Deucher <alexdeucher at gmail.com>
+Date: Thu May 19 11:07:57 2011 -0400
+
+ drm/radeon/evergreen/btc/fusion: setup hdp to invalidate and flush when asked
+
+ This needs to be explicitly set on btc. It's set by default
+ on evergreen/fusion, so it fine to just unconditionally enable it for
+ all chips.
+
+ Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
+ cc: stable at kernel.org
+ Signed-off-by: Dave Airlie <airlied at gmail.com>
+
+commit 97bce584876b2293c0ceeeb1abc33ec568d320ea
+Author: Alex Deucher <alexdeucher at gmail.com>
+Date: Thu May 12 21:15:15 2011 -0400
+
+ drm/radeon/kms: add some evergreen/ni safe regs
+
+ need to programmed from the userspace drivers.
+
+ Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit d3be86b8137152ebf1be2ee2ccf90fea7f9a07a9
+Author: Alex Deucher <alexdeucher at gmail.com>
+Date: Wed May 11 03:15:24 2011 -0400
+
+ drm/radeon/kms: fix tiling reg on fusion
+
+ The location of MC_ARB_RAMCFG changed on fusion.
+ I've diffed all the other regs in evergreend.h and this
+ is the only other reg that changed.
+
+ Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit 740da77e0792cd804510d018924df8f149f58fe4
+Author: Alex Deucher <alexdeucher at gmail.com>
+Date: Tue May 10 02:14:52 2011 +0000
+
+ drm/radeon/kms: fix cayman acceleration
+
+ The TCC disable setup was incorrect. This
+ prevents the GPU from hanging when draw commands
+ are issued.
+
+ Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit 02b1b583d1c9b2559288ea5f46f04b0c8385f1ef
+Author: Dave Airlie <airlied at redhat.com>
+Date: Mon May 9 14:54:33 2011 +1000
+
+ drm/radeon: fix cayman struct accessors.
+
+ We are accessing totally the wrong struct in this case, and putting
+ uninitialised values into the GPU, which it doesn't like unsurprisingly.
+
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit 202ea65cf5d6451baf74feb4becdad19ab53eadc
+Author: Ilija Hadzic <ihadzic at research.bell-labs.com>
+Date: Wed May 4 20:15:03 2011 -0400
+
+ drm/radeon: fix order of doing things in radeon_crtc_cursor_set
+
+ if object pin or object lookup in radeon_cursor_set fail, the function
+ could leave inconsistent mouse width and hight values in radeon_crtc
+ fixed by moving cursor width and height assignments after all
+ checks have passed
+
+ Signed-off-by: Ilija Hadzic <ihadzic at research.bell-labs.com>
+ Reviewed-by: Alex Deucher <alexdeucher at gmail.com>
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit a796f1fc096d0032972480657d6d9c4fc5836496
+Author: Alex Deucher <alexdeucher at gmail.com>
+Date: Fri May 6 01:42:49 2011 -0400
+
+ drm/radeon/kms: ATPX switcheroo fixes
+
+ When we switch the display mux, also switch
+ the i2c mux. Also use the start and finish
+ methods to let the sbios know that the switch
+ is happening.
+
+ Should fix:
+ https://bugs.freedesktop.org/show_bug.cgi?id=35398
+
+ Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+
+commit 134627db513fffd8ecc90b96d477c18ae76d2d61
+Author: Alex Deucher <alexdeucher at gmail.com>
+Date: Tue May 3 12:44:54 2011 -0400
+
+ drm/radeon/kms: add support for thermal chips on combios asics
+
+ Signed-off-by: Alex Deucher <alexdeucher at gmail.com>
+ Signed-off-by: Dave Airlie <airlied at redhat.com>
+diff --git a/drivers/gpu/drm/radeon/cayman_blit_shaders.c b/drivers/gpu/drm/radeon/cayman_blit_shaders.c
+index e148ab0..7b4eeb7 100644
+--- a/drivers/gpu/drm/radeon/cayman_blit_shaders.c
++++ b/drivers/gpu/drm/radeon/cayman_blit_shaders.c
+@@ -39,17 +39,335 @@
+
+ const u32 cayman_default_state[] =
+ {
+- /* XXX fill in additional blit state */
++ 0xc0066900,
++ 0x00000000,
++ 0x00000060, /* DB_RENDER_CONTROL */
++ 0x00000000, /* DB_COUNT_CONTROL */
++ 0x00000000, /* DB_DEPTH_VIEW */
++ 0x0000002a, /* DB_RENDER_OVERRIDE */
++ 0x00000000, /* DB_RENDER_OVERRIDE2 */
++ 0x00000000, /* DB_HTILE_DATA_BASE */
+
+ 0xc0026900,
+- 0x00000316,
+- 0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */
+- 0x00000010, /* */
++ 0x0000000a,
++ 0x00000000, /* DB_STENCIL_CLEAR */
++ 0x00000000, /* DB_DEPTH_CLEAR */
++
++ 0xc0036900,
++ 0x0000000f,
++ 0x00000000, /* DB_DEPTH_INFO */
++ 0x00000000, /* DB_Z_INFO */
++ 0x00000000, /* DB_STENCIL_INFO */
++
++ 0xc0016900,
++ 0x00000080,
++ 0x00000000, /* PA_SC_WINDOW_OFFSET */
++
++ 0xc00d6900,
++ 0x00000083,
++ 0x0000ffff, /* PA_SC_CLIPRECT_RULE */
++ 0x00000000, /* PA_SC_CLIPRECT_0_TL */
++ 0x20002000, /* PA_SC_CLIPRECT_0_BR */
++ 0x00000000,
++ 0x20002000,
++ 0x00000000,
++ 0x20002000,
++ 0x00000000,
++ 0x20002000,
++ 0xaaaaaaaa, /* PA_SC_EDGERULE */
++ 0x00000000, /* PA_SU_HARDWARE_SCREEN_OFFSET */
++ 0x0000000f, /* CB_TARGET_MASK */
++ 0x0000000f, /* CB_SHADER_MASK */
++
++ 0xc0226900,
++ 0x00000094,
++ 0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
++ 0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
++ 0x80000000,
++ 0x20002000,
++ 0x80000000,
++ 0x20002000,
++ 0x80000000,
++ 0x20002000,
++ 0x80000000,
++ 0x20002000,
++ 0x80000000,
++ 0x20002000,
++ 0x80000000,
++ 0x20002000,
++ 0x80000000,
++ 0x20002000,
++ 0x80000000,
++ 0x20002000,
++ 0x80000000,
++ 0x20002000,
++ 0x80000000,
++ 0x20002000,
++ 0x80000000,
++ 0x20002000,
++ 0x80000000,
++ 0x20002000,
++ 0x80000000,
++ 0x20002000,
++ 0x80000000,
++ 0x20002000,
++ 0x80000000,
++ 0x20002000,
++ 0x00000000, /* PA_SC_VPORT_ZMIN_0 */
++ 0x3f800000, /* PA_SC_VPORT_ZMAX_0 */
++
++ 0xc0016900,
++ 0x000000d4,
++ 0x00000000, /* SX_MISC */
+
+ 0xc0026900,
+ 0x000000d9,
+ 0x00000000, /* CP_RINGID */
+ 0x00000000, /* CP_VMID */
++
++ 0xc0096900,
++ 0x00000100,
++ 0x00ffffff, /* VGT_MAX_VTX_INDX */
++ 0x00000000, /* VGT_MIN_VTX_INDX */
++ 0x00000000, /* VGT_INDX_OFFSET */
++ 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
++ 0x00000000, /* SX_ALPHA_TEST_CONTROL */
++ 0x00000000, /* CB_BLEND_RED */
++ 0x00000000, /* CB_BLEND_GREEN */
++ 0x00000000, /* CB_BLEND_BLUE */
++ 0x00000000, /* CB_BLEND_ALPHA */
++
++ 0xc0016900,
++ 0x00000187,
++ 0x00000100, /* SPI_VS_OUT_ID_0 */
++
++ 0xc0026900,
++ 0x00000191,
++ 0x00000100, /* SPI_PS_INPUT_CNTL_0 */
++ 0x00000101, /* SPI_PS_INPUT_CNTL_1 */
++
++ 0xc0016900,
++ 0x000001b1,
++ 0x00000000, /* SPI_VS_OUT_CONFIG */
++
++ 0xc0106900,
++ 0x000001b3,
++ 0x20000001, /* SPI_PS_IN_CONTROL_0 */
++ 0x00000000, /* SPI_PS_IN_CONTROL_1 */
++ 0x00000000, /* SPI_INTERP_CONTROL_0 */
++ 0x00000000, /* SPI_INPUT_Z */
++ 0x00000000, /* SPI_FOG_CNTL */
++ 0x00100000, /* SPI_BARYC_CNTL */
++ 0x00000000, /* SPI_PS_IN_CONTROL_2 */
++ 0x00000000, /* SPI_COMPUTE_INPUT_CNTL */
++ 0x00000000, /* SPI_COMPUTE_NUM_THREAD_X */
++ 0x00000000, /* SPI_COMPUTE_NUM_THREAD_Y */
++ 0x00000000, /* SPI_COMPUTE_NUM_THREAD_Z */
++ 0x00000000, /* SPI_GPR_MGMT */
++ 0x00000000, /* SPI_LDS_MGMT */
++ 0x00000000, /* SPI_STACK_MGMT */
++ 0x00000000, /* SPI_WAVE_MGMT_1 */
++ 0x00000000, /* SPI_WAVE_MGMT_2 */
++
++ 0xc0016900,
++ 0x000001e0,
++ 0x00000000, /* CB_BLEND0_CONTROL */
++
++ 0xc00e6900,
++ 0x00000200,
++ 0x00000000, /* DB_DEPTH_CONTROL */
++ 0x00000000, /* DB_EQAA */
++ 0x00cc0010, /* CB_COLOR_CONTROL */
++ 0x00000210, /* DB_SHADER_CONTROL */
++ 0x00010000, /* PA_CL_CLIP_CNTL */
++ 0x00000004, /* PA_SU_SC_MODE_CNTL */
++ 0x00000100, /* PA_CL_VTE_CNTL */
++ 0x00000000, /* PA_CL_VS_OUT_CNTL */
++ 0x00000000, /* PA_CL_NANINF_CNTL */
++ 0x00000000, /* PA_SU_LINE_STIPPLE_CNTL */
++ 0x00000000, /* PA_SU_LINE_STIPPLE_SCALE */
++ 0x00000000, /* PA_SU_PRIM_FILTER_CNTL */
++ 0x00000000, /* */
++ 0x00000000, /* */
++
++ 0xc0026900,
++ 0x00000229,
++ 0x00000000, /* SQ_PGM_START_FS */
++ 0x00000000,
++
++ 0xc0016900,
++ 0x0000023b,
++ 0x00000000, /* SQ_LDS_ALLOC_PS */
++
++ 0xc0066900,
++ 0x00000240,
++ 0x00000000, /* SQ_ESGS_RING_ITEMSIZE */
++ 0x00000000,
++ 0x00000000,
++ 0x00000000,
++ 0x00000000,
++ 0x00000000,
++
++ 0xc0046900,
++ 0x00000247,
++ 0x00000000, /* SQ_GS_VERT_ITEMSIZE */
++ 0x00000000,
++ 0x00000000,
++ 0x00000000,
++
++ 0xc0116900,
++ 0x00000280,
++ 0x00000000, /* PA_SU_POINT_SIZE */
++ 0x00000000, /* PA_SU_POINT_MINMAX */
++ 0x00000008, /* PA_SU_LINE_CNTL */
++ 0x00000000, /* PA_SC_LINE_STIPPLE */
++ 0x00000000, /* VGT_OUTPUT_PATH_CNTL */
++ 0x00000000, /* VGT_HOS_CNTL */
++ 0x00000000,
++ 0x00000000,
++ 0x00000000,
++ 0x00000000,
++ 0x00000000,
++ 0x00000000,
++ 0x00000000,
++ 0x00000000,
++ 0x00000000,
++ 0x00000000,
++ 0x00000000, /* VGT_GS_MODE */
++
++ 0xc0026900,
++ 0x00000292,
++ 0x00000000, /* PA_SC_MODE_CNTL_0 */
++ 0x00000000, /* PA_SC_MODE_CNTL_1 */
++
++ 0xc0016900,
++ 0x000002a1,
++ 0x00000000, /* VGT_PRIMITIVEID_EN */
++
++ 0xc0016900,
++ 0x000002a5,
++ 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_EN */
++
++ 0xc0026900,
++ 0x000002a8,
++ 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
++ 0x00000000,
++
++ 0xc0026900,
++ 0x000002ad,
++ 0x00000000, /* VGT_REUSE_OFF */
++ 0x00000000,
++
++ 0xc0016900,
++ 0x000002d5,
++ 0x00000000, /* VGT_SHADER_STAGES_EN */
++
++ 0xc0016900,
++ 0x000002dc,
++ 0x0000aa00, /* DB_ALPHA_TO_MASK */
++
++ 0xc0066900,
++ 0x000002de,
++ 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
++ 0x00000000,
++ 0x00000000,
++ 0x00000000,
++ 0x00000000,
++ 0x00000000,
++
++ 0xc0026900,
++ 0x000002e5,
++ 0x00000000, /* VGT_STRMOUT_CONFIG */
++ 0x00000000,
++
++ 0xc01b6900,
++ 0x000002f5,
++ 0x76543210, /* PA_SC_CENTROID_PRIORITY_0 */
++ 0xfedcba98, /* PA_SC_CENTROID_PRIORITY_1 */
++ 0x00000000, /* PA_SC_LINE_CNTL */
++ 0x00000000, /* PA_SC_AA_CONFIG */
++ 0x00000005, /* PA_SU_VTX_CNTL */
++ 0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
++ 0x3f800000, /* PA_CL_GB_VERT_DISC_ADJ */
++ 0x3f800000, /* PA_CL_GB_HORZ_CLIP_ADJ */
++ 0x3f800000, /* PA_CL_GB_HORZ_DISC_ADJ */
++ 0x00000000, /* PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 */
++ 0x00000000,
++ 0x00000000,
++ 0x00000000,
++ 0x00000000,
++ 0x00000000,
++ 0x00000000,
++ 0x00000000,
++ 0x00000000,
++ 0x00000000,
++ 0x00000000,
++ 0x00000000,
++ 0x00000000,
++ 0x00000000,
++ 0x00000000,
++ 0x00000000,
++ 0xffffffff, /* PA_SC_AA_MASK_X0Y0_X1Y0 */
++ 0xffffffff,
++
++ 0xc0026900,
++ 0x00000316,
++ 0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */
++ 0x00000010, /* */
++};
++
++const u32 cayman_vs[] =
++{
++ 0x00000004,
++ 0x80400400,
++ 0x0000a03c,
++ 0x95000688,
++ 0x00004000,
++ 0x15000688,
++ 0x00000000,
++ 0x88000000,
++ 0x04000000,
++ 0x67961001,
++#ifdef __BIG_ENDIAN
++ 0x00020000,
++#else
++ 0x00000000,
++#endif
++ 0x00000000,
++ 0x04000000,
++ 0x67961000,
++#ifdef __BIG_ENDIAN
++ 0x00020008,
++#else
++ 0x00000008,
++#endif
++ 0x00000000,
++};
++
++const u32 cayman_ps[] =
++{
++ 0x00000004,
++ 0xa00c0000,
++ 0x00000008,
++ 0x80400000,
++ 0x00000000,
++ 0x95000688,
++ 0x00000000,
++ 0x88000000,
++ 0x00380400,
++ 0x00146b10,
++ 0x00380000,
++ 0x20146b10,
++ 0x00380400,
++ 0x40146b00,
++ 0x80380000,
++ 0x60146b00,
++ 0x00000010,
++ 0x000d1000,
++ 0xb0800000,
++ 0x00000000,
+ };
+
++const u32 cayman_ps_size = ARRAY_SIZE(cayman_ps);
++const u32 cayman_vs_size = ARRAY_SIZE(cayman_vs);
+ const u32 cayman_default_size = ARRAY_SIZE(cayman_default_state);
+diff --git a/drivers/gpu/drm/radeon/cayman_blit_shaders.h b/drivers/gpu/drm/radeon/cayman_blit_shaders.h
+index 33b75e5..f5d0e9a 100644
+--- a/drivers/gpu/drm/radeon/cayman_blit_shaders.h
++++ b/drivers/gpu/drm/radeon/cayman_blit_shaders.h
+@@ -25,8 +25,11 @@
+ #ifndef CAYMAN_BLIT_SHADERS_H
+ #define CAYMAN_BLIT_SHADERS_H
+
++extern const u32 cayman_ps[];
++extern const u32 cayman_vs[];
+ extern const u32 cayman_default_state[];
+
++extern const u32 cayman_ps_size, cayman_vs_size;
+ extern const u32 cayman_default_size;
+
+ #endif
+diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
+index f7e0376..1b583f8 100644
+--- a/drivers/gpu/drm/radeon/evergreen.c
++++ b/drivers/gpu/drm/radeon/evergreen.c
+@@ -88,21 +88,39 @@ u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
+ /* get temperature in millidegrees */
+ int evergreen_get_temp(struct radeon_device *rdev)
+ {
+- u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
+- ASIC_T_SHIFT;
+- u32 actual_temp = 0;
+-
+- if (temp & 0x400)
+- actual_temp = -256;
+- else if (temp & 0x200)
+- actual_temp = 255;
+- else if (temp & 0x100) {
+- actual_temp = temp & 0x1ff;
+- actual_temp |= ~0x1ff;
+- } else
+- actual_temp = temp & 0xff;
++ u32 temp, toffset, actual_temp = 0;
++
++ if (rdev->family == CHIP_JUNIPER) {
++ toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
++ TOFFSET_SHIFT;
++ temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >>
++ TS0_ADC_DOUT_SHIFT;
++
++ if (toffset & 0x100)
++ actual_temp = temp / 2 - (0x200 - toffset);
++ else
++ actual_temp = temp / 2 + toffset;
++
++ actual_temp = actual_temp * 1000;
++
++ } else {
++ temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
++ ASIC_T_SHIFT;
++
++ if (temp & 0x400)
++ actual_temp = -256;
++ else if (temp & 0x200)
++ actual_temp = 255;
++ else if (temp & 0x100) {
++ actual_temp = temp & 0x1ff;
++ actual_temp |= ~0x1ff;
++ } else
++ actual_temp = temp & 0xff;
+
+- return (actual_temp * 1000) / 2;
++ actual_temp = (actual_temp * 1000) / 2;
++ }
++
++ return actual_temp;
+ }
+
+ int sumo_get_temp(struct radeon_device *rdev)
+@@ -1578,7 +1596,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
+ u32 sq_stack_resource_mgmt_2;
+ u32 sq_stack_resource_mgmt_3;
+ u32 vgt_cache_invalidation;
+- u32 hdp_host_path_cntl;
++ u32 hdp_host_path_cntl, tmp;
+ int i, j, num_shader_engines, ps_thread_count;
+
+ switch (rdev->family) {
+@@ -1780,7 +1798,10 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
+
+
+ mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
+- mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
++ if (rdev->flags & RADEON_IS_IGP)
++ mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG);
++ else
++ mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
+
+ switch (rdev->config.evergreen.max_tile_pipes) {
+ case 1:
+@@ -1933,8 +1954,12 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
+ rdev->config.evergreen.tile_config |= (3 << 0);
+ break;
+ }
+- rdev->config.evergreen.tile_config |=
+- ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
++ /* num banks is 8 on all fusion asics */
++ if (rdev->flags & RADEON_IS_IGP)
++ rdev->config.evergreen.tile_config |= 8 << 4;
++ else
++ rdev->config.evergreen.tile_config |=
++ ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
+ rdev->config.evergreen.tile_config |=
+ ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8;
+ rdev->config.evergreen.tile_config |=
+@@ -2138,6 +2163,10 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
+ for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
+ WREG32(i, 0);
+
++ tmp = RREG32(HDP_MISC_CNTL);
++ tmp |= HDP_FLUSH_INVALIDATE_CACHE;
++ WREG32(HDP_MISC_CNTL, tmp);
++
+ hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
+ WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
+
+diff --git a/drivers/gpu/drm/radeon/evergreen_blit_kms.c b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
+index 2be698e..9c91468 100644
+--- a/drivers/gpu/drm/radeon/evergreen_blit_kms.c
++++ b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
+@@ -31,6 +31,7 @@
+
+ #include "evergreend.h"
+ #include "evergreen_blit_shaders.h"
++#include "cayman_blit_shaders.h"
+
+ #define DI_PT_RECTLIST 0x11
+ #define DI_INDEX_SIZE_16_BIT 0x0
+@@ -199,6 +200,16 @@ static void
+ set_scissors(struct radeon_device *rdev, int x1, int y1,
+ int x2, int y2)
+ {
++ /* workaround some hw bugs */
++ if (x2 == 0)
++ x1 = 1;
++ if (y2 == 0)
++ y1 = 1;
++ if (rdev->family == CHIP_CAYMAN) {
++ if ((x2 == 1) && (y2 == 1))
++ x2 = 2;
++ }
++
+ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
+ radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
+ radeon_ring_write(rdev, (x1 << 0) | (y1 << 16));
+@@ -255,238 +266,240 @@ set_default_state(struct radeon_device *rdev)
+ u64 gpu_addr;
+ int dwords;
+
+- switch (rdev->family) {
+- case CHIP_CEDAR:
+- default:
+- num_ps_gprs = 93;
+- num_vs_gprs = 46;
+- num_temp_gprs = 4;
+- num_gs_gprs = 31;
+- num_es_gprs = 31;
+- num_hs_gprs = 23;
+- num_ls_gprs = 23;
+- num_ps_threads = 96;
+- num_vs_threads = 16;
+- num_gs_threads = 16;
+- num_es_threads = 16;
+- num_hs_threads = 16;
+- num_ls_threads = 16;
+- num_ps_stack_entries = 42;
+- num_vs_stack_entries = 42;
+- num_gs_stack_entries = 42;
+- num_es_stack_entries = 42;
+- num_hs_stack_entries = 42;
+- num_ls_stack_entries = 42;
+- break;
+- case CHIP_REDWOOD:
+- num_ps_gprs = 93;
+- num_vs_gprs = 46;
+- num_temp_gprs = 4;
+- num_gs_gprs = 31;
+- num_es_gprs = 31;
+- num_hs_gprs = 23;
+- num_ls_gprs = 23;
+- num_ps_threads = 128;
+- num_vs_threads = 20;
+- num_gs_threads = 20;
+- num_es_threads = 20;
+- num_hs_threads = 20;
+- num_ls_threads = 20;
+- num_ps_stack_entries = 42;
+- num_vs_stack_entries = 42;
+- num_gs_stack_entries = 42;
+- num_es_stack_entries = 42;
+- num_hs_stack_entries = 42;
+- num_ls_stack_entries = 42;
+- break;
+- case CHIP_JUNIPER:
+- num_ps_gprs = 93;
+- num_vs_gprs = 46;
+- num_temp_gprs = 4;
+- num_gs_gprs = 31;
+- num_es_gprs = 31;
+- num_hs_gprs = 23;
+- num_ls_gprs = 23;
+- num_ps_threads = 128;
+- num_vs_threads = 20;
+- num_gs_threads = 20;
+- num_es_threads = 20;
+- num_hs_threads = 20;
+- num_ls_threads = 20;
+- num_ps_stack_entries = 85;
+- num_vs_stack_entries = 85;
+- num_gs_stack_entries = 85;
+- num_es_stack_entries = 85;
+- num_hs_stack_entries = 85;
+- num_ls_stack_entries = 85;
+- break;
+- case CHIP_CYPRESS:
+- case CHIP_HEMLOCK:
+- num_ps_gprs = 93;
+- num_vs_gprs = 46;
+- num_temp_gprs = 4;
+- num_gs_gprs = 31;
+- num_es_gprs = 31;
+- num_hs_gprs = 23;
+- num_ls_gprs = 23;
+- num_ps_threads = 128;
+- num_vs_threads = 20;
+- num_gs_threads = 20;
+- num_es_threads = 20;
+- num_hs_threads = 20;
+- num_ls_threads = 20;
+- num_ps_stack_entries = 85;
+- num_vs_stack_entries = 85;
+- num_gs_stack_entries = 85;
+- num_es_stack_entries = 85;
+- num_hs_stack_entries = 85;
+- num_ls_stack_entries = 85;
+- break;
+- case CHIP_PALM:
+- num_ps_gprs = 93;
+- num_vs_gprs = 46;
+- num_temp_gprs = 4;
+- num_gs_gprs = 31;
+- num_es_gprs = 31;
+- num_hs_gprs = 23;
+- num_ls_gprs = 23;
+- num_ps_threads = 96;
+- num_vs_threads = 16;
+- num_gs_threads = 16;
+- num_es_threads = 16;
+- num_hs_threads = 16;
+- num_ls_threads = 16;
+- num_ps_stack_entries = 42;
+- num_vs_stack_entries = 42;
+- num_gs_stack_entries = 42;
+- num_es_stack_entries = 42;
+- num_hs_stack_entries = 42;
+- num_ls_stack_entries = 42;
+- break;
+- case CHIP_BARTS:
+- num_ps_gprs = 93;
+- num_vs_gprs = 46;
+- num_temp_gprs = 4;
+- num_gs_gprs = 31;
+- num_es_gprs = 31;
+- num_hs_gprs = 23;
+- num_ls_gprs = 23;
+- num_ps_threads = 128;
+- num_vs_threads = 20;
+- num_gs_threads = 20;
+- num_es_threads = 20;
+- num_hs_threads = 20;
+- num_ls_threads = 20;
+- num_ps_stack_entries = 85;
+- num_vs_stack_entries = 85;
+- num_gs_stack_entries = 85;
+- num_es_stack_entries = 85;
+- num_hs_stack_entries = 85;
+- num_ls_stack_entries = 85;
+- break;
+- case CHIP_TURKS:
+- num_ps_gprs = 93;
+- num_vs_gprs = 46;
+- num_temp_gprs = 4;
+- num_gs_gprs = 31;
+- num_es_gprs = 31;
+- num_hs_gprs = 23;
+- num_ls_gprs = 23;
+- num_ps_threads = 128;
+- num_vs_threads = 20;
+- num_gs_threads = 20;
+- num_es_threads = 20;
+- num_hs_threads = 20;
+- num_ls_threads = 20;
+- num_ps_stack_entries = 42;
+- num_vs_stack_entries = 42;
+- num_gs_stack_entries = 42;
+- num_es_stack_entries = 42;
+- num_hs_stack_entries = 42;
+- num_ls_stack_entries = 42;
+- break;
+- case CHIP_CAICOS:
+- num_ps_gprs = 93;
+- num_vs_gprs = 46;
+- num_temp_gprs = 4;
+- num_gs_gprs = 31;
+- num_es_gprs = 31;
+- num_hs_gprs = 23;
+- num_ls_gprs = 23;
+- num_ps_threads = 128;
+- num_vs_threads = 10;
+- num_gs_threads = 10;
+- num_es_threads = 10;
+- num_hs_threads = 10;
+- num_ls_threads = 10;
+- num_ps_stack_entries = 42;
+- num_vs_stack_entries = 42;
+- num_gs_stack_entries = 42;
+- num_es_stack_entries = 42;
+- num_hs_stack_entries = 42;
+- num_ls_stack_entries = 42;
+- break;
+- }
+-
+- if ((rdev->family == CHIP_CEDAR) ||
+- (rdev->family == CHIP_PALM) ||
+- (rdev->family == CHIP_CAICOS))
+- sq_config = 0;
+- else
+- sq_config = VC_ENABLE;
+-
+- sq_config |= (EXPORT_SRC_C |
+- CS_PRIO(0) |
+- LS_PRIO(0) |
+- HS_PRIO(0) |
+- PS_PRIO(0) |
+- VS_PRIO(1) |
+- GS_PRIO(2) |
+- ES_PRIO(3));
+-
+- sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
+- NUM_VS_GPRS(num_vs_gprs) |
+- NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
+- sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) |
+- NUM_ES_GPRS(num_es_gprs));
+- sq_gpr_resource_mgmt_3 = (NUM_HS_GPRS(num_hs_gprs) |
+- NUM_LS_GPRS(num_ls_gprs));
+- sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) |
+- NUM_VS_THREADS(num_vs_threads) |
+- NUM_GS_THREADS(num_gs_threads) |
+- NUM_ES_THREADS(num_es_threads));
+- sq_thread_resource_mgmt_2 = (NUM_HS_THREADS(num_hs_threads) |
+- NUM_LS_THREADS(num_ls_threads));
+- sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
+- NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
+- sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
+- NUM_ES_STACK_ENTRIES(num_es_stack_entries));
+- sq_stack_resource_mgmt_3 = (NUM_HS_STACK_ENTRIES(num_hs_stack_entries) |
+- NUM_LS_STACK_ENTRIES(num_ls_stack_entries));
+-
+ /* set clear context state */
+ radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
+ radeon_ring_write(rdev, 0);
+
+- /* disable dyn gprs */
+- radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
+- radeon_ring_write(rdev, (SQ_DYN_GPR_CNTL_PS_FLUSH_REQ - PACKET3_SET_CONFIG_REG_START) >> 2);
+- radeon_ring_write(rdev, 0);
++ if (rdev->family < CHIP_CAYMAN) {
++ switch (rdev->family) {
++ case CHIP_CEDAR:
++ default:
++ num_ps_gprs = 93;
++ num_vs_gprs = 46;
++ num_temp_gprs = 4;
++ num_gs_gprs = 31;
++ num_es_gprs = 31;
++ num_hs_gprs = 23;
++ num_ls_gprs = 23;
++ num_ps_threads = 96;
++ num_vs_threads = 16;
++ num_gs_threads = 16;
++ num_es_threads = 16;
++ num_hs_threads = 16;
++ num_ls_threads = 16;
++ num_ps_stack_entries = 42;
++ num_vs_stack_entries = 42;
++ num_gs_stack_entries = 42;
++ num_es_stack_entries = 42;
++ num_hs_stack_entries = 42;
++ num_ls_stack_entries = 42;
++ break;
++ case CHIP_REDWOOD:
++ num_ps_gprs = 93;
++ num_vs_gprs = 46;
++ num_temp_gprs = 4;
++ num_gs_gprs = 31;
++ num_es_gprs = 31;
++ num_hs_gprs = 23;
++ num_ls_gprs = 23;
++ num_ps_threads = 128;
++ num_vs_threads = 20;
++ num_gs_threads = 20;
++ num_es_threads = 20;
++ num_hs_threads = 20;
++ num_ls_threads = 20;
++ num_ps_stack_entries = 42;
++ num_vs_stack_entries = 42;
++ num_gs_stack_entries = 42;
++ num_es_stack_entries = 42;
++ num_hs_stack_entries = 42;
++ num_ls_stack_entries = 42;
++ break;
++ case CHIP_JUNIPER:
++ num_ps_gprs = 93;
++ num_vs_gprs = 46;
++ num_temp_gprs = 4;
++ num_gs_gprs = 31;
++ num_es_gprs = 31;
++ num_hs_gprs = 23;
++ num_ls_gprs = 23;
++ num_ps_threads = 128;
++ num_vs_threads = 20;
++ num_gs_threads = 20;
++ num_es_threads = 20;
++ num_hs_threads = 20;
++ num_ls_threads = 20;
++ num_ps_stack_entries = 85;
++ num_vs_stack_entries = 85;
++ num_gs_stack_entries = 85;
++ num_es_stack_entries = 85;
++ num_hs_stack_entries = 85;
++ num_ls_stack_entries = 85;
++ break;
++ case CHIP_CYPRESS:
++ case CHIP_HEMLOCK:
++ num_ps_gprs = 93;
++ num_vs_gprs = 46;
++ num_temp_gprs = 4;
++ num_gs_gprs = 31;
++ num_es_gprs = 31;
++ num_hs_gprs = 23;
++ num_ls_gprs = 23;
++ num_ps_threads = 128;
++ num_vs_threads = 20;
++ num_gs_threads = 20;
++ num_es_threads = 20;
++ num_hs_threads = 20;
++ num_ls_threads = 20;
++ num_ps_stack_entries = 85;
++ num_vs_stack_entries = 85;
++ num_gs_stack_entries = 85;
++ num_es_stack_entries = 85;
++ num_hs_stack_entries = 85;
++ num_ls_stack_entries = 85;
++ break;
++ case CHIP_PALM:
++ num_ps_gprs = 93;
++ num_vs_gprs = 46;
++ num_temp_gprs = 4;
++ num_gs_gprs = 31;
++ num_es_gprs = 31;
++ num_hs_gprs = 23;
++ num_ls_gprs = 23;
++ num_ps_threads = 96;
++ num_vs_threads = 16;
++ num_gs_threads = 16;
++ num_es_threads = 16;
++ num_hs_threads = 16;
++ num_ls_threads = 16;
++ num_ps_stack_entries = 42;
++ num_vs_stack_entries = 42;
++ num_gs_stack_entries = 42;
++ num_es_stack_entries = 42;
++ num_hs_stack_entries = 42;
++ num_ls_stack_entries = 42;
++ break;
++ case CHIP_BARTS:
++ num_ps_gprs = 93;
++ num_vs_gprs = 46;
++ num_temp_gprs = 4;
++ num_gs_gprs = 31;
++ num_es_gprs = 31;
++ num_hs_gprs = 23;
++ num_ls_gprs = 23;
++ num_ps_threads = 128;
++ num_vs_threads = 20;
++ num_gs_threads = 20;
++ num_es_threads = 20;
++ num_hs_threads = 20;
++ num_ls_threads = 20;
++ num_ps_stack_entries = 85;
++ num_vs_stack_entries = 85;
++ num_gs_stack_entries = 85;
++ num_es_stack_entries = 85;
++ num_hs_stack_entries = 85;
++ num_ls_stack_entries = 85;
++ break;
++ case CHIP_TURKS:
++ num_ps_gprs = 93;
++ num_vs_gprs = 46;
++ num_temp_gprs = 4;
++ num_gs_gprs = 31;
++ num_es_gprs = 31;
++ num_hs_gprs = 23;
++ num_ls_gprs = 23;
++ num_ps_threads = 128;
++ num_vs_threads = 20;
++ num_gs_threads = 20;
++ num_es_threads = 20;
++ num_hs_threads = 20;
++ num_ls_threads = 20;
++ num_ps_stack_entries = 42;
++ num_vs_stack_entries = 42;
++ num_gs_stack_entries = 42;
++ num_es_stack_entries = 42;
++ num_hs_stack_entries = 42;
++ num_ls_stack_entries = 42;
++ break;
++ case CHIP_CAICOS:
++ num_ps_gprs = 93;
++ num_vs_gprs = 46;
++ num_temp_gprs = 4;
++ num_gs_gprs = 31;
++ num_es_gprs = 31;
++ num_hs_gprs = 23;
++ num_ls_gprs = 23;
++ num_ps_threads = 128;
++ num_vs_threads = 10;
++ num_gs_threads = 10;
++ num_es_threads = 10;
++ num_hs_threads = 10;
++ num_ls_threads = 10;
++ num_ps_stack_entries = 42;
++ num_vs_stack_entries = 42;
++ num_gs_stack_entries = 42;
++ num_es_stack_entries = 42;
++ num_hs_stack_entries = 42;
++ num_ls_stack_entries = 42;
++ break;
++ }
+
+- /* SQ config */
+- radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 11));
+- radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_START) >> 2);
+- radeon_ring_write(rdev, sq_config);
+- radeon_ring_write(rdev, sq_gpr_resource_mgmt_1);
+- radeon_ring_write(rdev, sq_gpr_resource_mgmt_2);
+- radeon_ring_write(rdev, sq_gpr_resource_mgmt_3);
+- radeon_ring_write(rdev, 0);
+- radeon_ring_write(rdev, 0);
+- radeon_ring_write(rdev, sq_thread_resource_mgmt);
+- radeon_ring_write(rdev, sq_thread_resource_mgmt_2);
+- radeon_ring_write(rdev, sq_stack_resource_mgmt_1);
+- radeon_ring_write(rdev, sq_stack_resource_mgmt_2);
+- radeon_ring_write(rdev, sq_stack_resource_mgmt_3);
++ if ((rdev->family == CHIP_CEDAR) ||
++ (rdev->family == CHIP_PALM) ||
++ (rdev->family == CHIP_CAICOS))
++ sq_config = 0;
++ else
++ sq_config = VC_ENABLE;
++
++ sq_config |= (EXPORT_SRC_C |
++ CS_PRIO(0) |
++ LS_PRIO(0) |
++ HS_PRIO(0) |
++ PS_PRIO(0) |
++ VS_PRIO(1) |
++ GS_PRIO(2) |
++ ES_PRIO(3));
++
++ sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) |
++ NUM_VS_GPRS(num_vs_gprs) |
++ NUM_CLAUSE_TEMP_GPRS(num_temp_gprs));
++ sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) |
++ NUM_ES_GPRS(num_es_gprs));
++ sq_gpr_resource_mgmt_3 = (NUM_HS_GPRS(num_hs_gprs) |
++ NUM_LS_GPRS(num_ls_gprs));
++ sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) |
++ NUM_VS_THREADS(num_vs_threads) |
++ NUM_GS_THREADS(num_gs_threads) |
++ NUM_ES_THREADS(num_es_threads));
++ sq_thread_resource_mgmt_2 = (NUM_HS_THREADS(num_hs_threads) |
++ NUM_LS_THREADS(num_ls_threads));
++ sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) |
++ NUM_VS_STACK_ENTRIES(num_vs_stack_entries));
++ sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) |
++ NUM_ES_STACK_ENTRIES(num_es_stack_entries));
++ sq_stack_resource_mgmt_3 = (NUM_HS_STACK_ENTRIES(num_hs_stack_entries) |
++ NUM_LS_STACK_ENTRIES(num_ls_stack_entries));
++
++ /* disable dyn gprs */
++ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
++ radeon_ring_write(rdev, (SQ_DYN_GPR_CNTL_PS_FLUSH_REQ - PACKET3_SET_CONFIG_REG_START) >> 2);
++ radeon_ring_write(rdev, 0);
++
++ /* SQ config */
++ radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 11));
++ radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_START) >> 2);
++ radeon_ring_write(rdev, sq_config);
++ radeon_ring_write(rdev, sq_gpr_resource_mgmt_1);
++ radeon_ring_write(rdev, sq_gpr_resource_mgmt_2);
++ radeon_ring_write(rdev, sq_gpr_resource_mgmt_3);
++ radeon_ring_write(rdev, 0);
++ radeon_ring_write(rdev, 0);
++ radeon_ring_write(rdev, sq_thread_resource_mgmt);
++ radeon_ring_write(rdev, sq_thread_resource_mgmt_2);
++ radeon_ring_write(rdev, sq_stack_resource_mgmt_1);
++ radeon_ring_write(rdev, sq_stack_resource_mgmt_2);
++ radeon_ring_write(rdev, sq_stack_resource_mgmt_3);
++ }
+
+ /* CONTEXT_CONTROL */
+ radeon_ring_write(rdev, 0xc0012800);
+@@ -560,7 +573,10 @@ int evergreen_blit_init(struct radeon_device *rdev)
+ mutex_init(&rdev->r600_blit.mutex);
+ rdev->r600_blit.state_offset = 0;
+
+- rdev->r600_blit.state_len = evergreen_default_size;
++ if (rdev->family < CHIP_CAYMAN)
++ rdev->r600_blit.state_len = evergreen_default_size;
++ else
++ rdev->r600_blit.state_len = cayman_default_size;
+
+ dwords = rdev->r600_blit.state_len;
+ while (dwords & 0xf) {
+@@ -572,11 +588,17 @@ int evergreen_blit_init(struct radeon_device *rdev)
+ obj_size = ALIGN(obj_size, 256);
+
+ rdev->r600_blit.vs_offset = obj_size;
+- obj_size += evergreen_vs_size * 4;
++ if (rdev->family < CHIP_CAYMAN)
++ obj_size += evergreen_vs_size * 4;
++ else
++ obj_size += cayman_vs_size * 4;
+ obj_size = ALIGN(obj_size, 256);
+
+ rdev->r600_blit.ps_offset = obj_size;
+- obj_size += evergreen_ps_size * 4;
++ if (rdev->family < CHIP_CAYMAN)
++ obj_size += evergreen_ps_size * 4;
++ else
++ obj_size += cayman_ps_size * 4;
+ obj_size = ALIGN(obj_size, 256);
+
+ r = radeon_bo_create(rdev, NULL, obj_size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
+@@ -599,16 +621,29 @@ int evergreen_blit_init(struct radeon_device *rdev)
+ return r;
+ }
+
+- memcpy_toio(ptr + rdev->r600_blit.state_offset,
+- evergreen_default_state, rdev->r600_blit.state_len * 4);
+-
+- if (num_packet2s)
+- memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
+- packet2s, num_packet2s * 4);
+- for (i = 0; i < evergreen_vs_size; i++)
+- *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(evergreen_vs[i]);
+- for (i = 0; i < evergreen_ps_size; i++)
+- *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(evergreen_ps[i]);
++ if (rdev->family < CHIP_CAYMAN) {
++ memcpy_toio(ptr + rdev->r600_blit.state_offset,
++ evergreen_default_state, rdev->r600_blit.state_len * 4);
++
++ if (num_packet2s)
++ memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
++ packet2s, num_packet2s * 4);
++ for (i = 0; i < evergreen_vs_size; i++)
++ *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(evergreen_vs[i]);
++ for (i = 0; i < evergreen_ps_size; i++)
++ *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(evergreen_ps[i]);
++ } else {
++ memcpy_toio(ptr + rdev->r600_blit.state_offset,
++ cayman_default_state, rdev->r600_blit.state_len * 4);
++
++ if (num_packet2s)
++ memcpy_toio(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4),
++ packet2s, num_packet2s * 4);
++ for (i = 0; i < cayman_vs_size; i++)
++ *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(cayman_vs[i]);
++ for (i = 0; i < cayman_ps_size; i++)
++ *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(cayman_ps[i]);
++ }
+ radeon_bo_kunmap(rdev->r600_blit.shader_obj);
+ radeon_bo_unreserve(rdev->r600_blit.shader_obj);
+
+diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
+index 9453384..1636e34 100644
+--- a/drivers/gpu/drm/radeon/evergreend.h
++++ b/drivers/gpu/drm/radeon/evergreend.h
+@@ -64,6 +64,8 @@
+ #define GB_BACKEND_MAP 0x98FC
+ #define DMIF_ADDR_CONFIG 0xBD4
+ #define HDP_ADDR_CONFIG 0x2F48
++#define HDP_MISC_CNTL 0x2F4C
++#define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
+
+ #define CC_SYS_RB_BACKEND_DISABLE 0x3F88
+ #define GC_USER_RB_BACKEND_DISABLE 0x9B7C
+@@ -166,10 +168,16 @@
+ #define SE_DB_BUSY (1 << 30)
+ #define SE_CB_BUSY (1 << 31)
+ /* evergreen */
++#define CG_THERMAL_CTRL 0x72c
++#define TOFFSET_MASK 0x00003FE0
++#define TOFFSET_SHIFT 5
+ #define CG_MULT_THERMAL_STATUS 0x740
+ #define ASIC_T(x) ((x) << 16)
+-#define ASIC_T_MASK 0x7FF0000
++#define ASIC_T_MASK 0x07FF0000
+ #define ASIC_T_SHIFT 16
++#define CG_TS0_STATUS 0x760
++#define TS0_ADC_DOUT_MASK 0x000003FF
++#define TS0_ADC_DOUT_SHIFT 0
+ /* APU */
+ #define CG_THERMAL_STATUS 0x678
+
+@@ -200,6 +208,7 @@
+ #define BURSTLENGTH_SHIFT 9
+ #define BURSTLENGTH_MASK 0x00000200
+ #define CHANSIZE_OVERRIDE (1 << 11)
++#define FUS_MC_ARB_RAMCFG 0x2768
+ #define MC_VM_AGP_TOP 0x2028
+ #define MC_VM_AGP_BOT 0x202C
+ #define MC_VM_AGP_BASE 0x2030
+diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
+index 8c199c4..b226cca 100644
+--- a/drivers/gpu/drm/radeon/ni.c
++++ b/drivers/gpu/drm/radeon/ni.c
+@@ -417,7 +417,7 @@ static u32 cayman_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
+ num_shader_engines = 1;
+ if (num_shader_engines > rdev->config.cayman.max_shader_engines)
+ num_shader_engines = rdev->config.cayman.max_shader_engines;
+- if (num_backends_per_asic > num_shader_engines)
++ if (num_backends_per_asic < num_shader_engines)
+ num_backends_per_asic = num_shader_engines;
+ if (num_backends_per_asic > (rdev->config.cayman.max_backends_per_se * num_shader_engines))
+ num_backends_per_asic = rdev->config.cayman.max_backends_per_se * num_shader_engines;
+@@ -674,7 +674,7 @@ static void cayman_gpu_init(struct radeon_device *rdev)
+
+ cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE);
+ cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG);
+- cgts_tcc_disable = RREG32(CGTS_TCC_DISABLE);
++ cgts_tcc_disable = 0xff000000;
+ gc_user_rb_backend_disable = RREG32(GC_USER_RB_BACKEND_DISABLE);
+ gc_user_shader_pipe_config = RREG32(GC_USER_SHADER_PIPE_CONFIG);
+ cgts_user_tcc_disable = RREG32(CGTS_USER_TCC_DISABLE);
+@@ -829,7 +829,7 @@ static void cayman_gpu_init(struct radeon_device *rdev)
+ rdev->config.cayman.tile_config |=
+ ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
+ rdev->config.cayman.tile_config |=
+- (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
++ ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
+ rdev->config.cayman.tile_config |=
+ ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
+
+@@ -871,7 +871,7 @@ static void cayman_gpu_init(struct radeon_device *rdev)
+
+ smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
+ smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
+- smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
++ smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.cayman.sx_num_of_sets);
+ WREG32(SMX_DC_CTL0, smx_dc_ctl0);
+
+ WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4) | CRC_SIMD_ID_WADDR_DISABLE);
+@@ -887,20 +887,20 @@ static void cayman_gpu_init(struct radeon_device *rdev)
+
+ WREG32(TA_CNTL_AUX, DISABLE_CUBE_ANISO);
+
+- WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
+- POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
+- SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
++ WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.cayman.sx_max_export_size / 4) - 1) |
++ POSITION_BUFFER_SIZE((rdev->config.cayman.sx_max_export_pos_size / 4) - 1) |
++ SMX_BUFFER_SIZE((rdev->config.cayman.sx_max_export_smx_size / 4) - 1)));
+
+- WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
+- SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
+- SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
++ WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.cayman.sc_prim_fifo_size) |
++ SC_HIZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_hiz_tile_fifo_size) |
++ SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cayman.sc_earlyz_tile_fifo_size)));
+
+
+ WREG32(VGT_NUM_INSTANCES, 1);
+
+ WREG32(CP_PERFMON_CNTL, 0);
+
+- WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
++ WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.cayman.sq_num_cf_insts) |
+ FETCH_FIFO_HIWATER(0x4) |
+ DONE_FIFO_HIWATER(0xe0) |
+ ALU_UPDATE_FIFO_HIWATER(0x8)));
+@@ -931,6 +931,10 @@ static void cayman_gpu_init(struct radeon_device *rdev)
+ WREG32(CB_PERF_CTR3_SEL_0, 0);
+ WREG32(CB_PERF_CTR3_SEL_1, 0);
+
++ tmp = RREG32(HDP_MISC_CNTL);
++ tmp |= HDP_FLUSH_INVALIDATE_CACHE;
++ WREG32(HDP_MISC_CNTL, tmp);
++
+ hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
+ WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
+
+@@ -1383,14 +1387,12 @@ static int cayman_startup(struct radeon_device *rdev)
+ return r;
+ cayman_gpu_init(rdev);
+
+-#if 0
+- r = cayman_blit_init(rdev);
++ r = evergreen_blit_init(rdev);
+ if (r) {
+- cayman_blit_fini(rdev);
++ evergreen_blit_fini(rdev);
+ rdev->asic->copy = NULL;
+ dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
+ }
+-#endif
+
+ /* allocate wb buffer */
+ r = radeon_wb_init(rdev);
+@@ -1448,7 +1450,7 @@ int cayman_resume(struct radeon_device *rdev)
+
+ int cayman_suspend(struct radeon_device *rdev)
+ {
+- /* int r; */
++ int r;
+
+ /* FIXME: we should wait for ring to be empty */
+ cayman_cp_enable(rdev, false);
+@@ -1457,14 +1459,13 @@ int cayman_suspend(struct radeon_device *rdev)
+ radeon_wb_disable(rdev);
+ cayman_pcie_gart_disable(rdev);
+
+-#if 0
+ /* unpin shaders bo */
+ r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
+ if (likely(r == 0)) {
+ radeon_bo_unpin(rdev->r600_blit.shader_obj);
+ radeon_bo_unreserve(rdev->r600_blit.shader_obj);
+ }
+-#endif
++
+ return 0;
+ }
+
+@@ -1576,7 +1577,7 @@ int cayman_init(struct radeon_device *rdev)
+
+ void cayman_fini(struct radeon_device *rdev)
+ {
+- /* cayman_blit_fini(rdev); */
++ evergreen_blit_fini(rdev);
+ cayman_cp_fini(rdev);
+ r600_irq_fini(rdev);
+ radeon_wb_fini(rdev);
+diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
+index 0f9a08b..9736746 100644
+--- a/drivers/gpu/drm/radeon/nid.h
++++ b/drivers/gpu/drm/radeon/nid.h
+@@ -136,6 +136,8 @@
+ #define HDP_NONSURFACE_INFO 0x2C08
+ #define HDP_NONSURFACE_SIZE 0x2C0C
+ #define HDP_ADDR_CONFIG 0x2F48
++#define HDP_MISC_CNTL 0x2F4C
++#define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
+
+ #define CC_SYS_RB_BACKEND_DISABLE 0x3F88
+ #define GC_USER_SYS_RB_BACKEND_DISABLE 0x3F8C
+@@ -351,7 +353,7 @@
+ #define MULTI_GPU_TILE_SIZE_MASK 0x03000000
+ #define MULTI_GPU_TILE_SIZE_SHIFT 24
+ #define ROW_SIZE(x) ((x) << 28)
+-#define ROW_SIZE_MASK 0x30000007
++#define ROW_SIZE_MASK 0x30000000
+ #define ROW_SIZE_SHIFT 28
+ #define NUM_LOWER_PIPES(x) ((x) << 30)
+ #define NUM_LOWER_PIPES_MASK 0x40000000
+diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
+index ca57619..b9b3c2a 100644
+--- a/drivers/gpu/drm/radeon/radeon_asic.c
++++ b/drivers/gpu/drm/radeon/radeon_asic.c
+@@ -782,6 +782,7 @@ static struct radeon_asic evergreen_asic = {
+ .hpd_fini = &evergreen_hpd_fini,
+ .hpd_sense = &evergreen_hpd_sense,
+ .hpd_set_polarity = &evergreen_hpd_set_polarity,
++ .ioctl_wait_idle = r600_ioctl_wait_idle,
+ .gui_idle = &r600_gui_idle,
+ .pm_misc = &evergreen_pm_misc,
+ .pm_prepare = &evergreen_pm_prepare,
+@@ -828,6 +829,7 @@ static struct radeon_asic sumo_asic = {
+ .hpd_fini = &evergreen_hpd_fini,
+ .hpd_sense = &evergreen_hpd_sense,
+ .hpd_set_polarity = &evergreen_hpd_set_polarity,
++ .ioctl_wait_idle = r600_ioctl_wait_idle,
+ .gui_idle = &r600_gui_idle,
+ .pm_misc = &evergreen_pm_misc,
+ .pm_prepare = &evergreen_pm_prepare,
+@@ -874,6 +876,7 @@ static struct radeon_asic btc_asic = {
+ .hpd_fini = &evergreen_hpd_fini,
+ .hpd_sense = &evergreen_hpd_sense,
+ .hpd_set_polarity = &evergreen_hpd_set_polarity,
++ .ioctl_wait_idle = r600_ioctl_wait_idle,
+ .gui_idle = &r600_gui_idle,
+ .pm_misc = &evergreen_pm_misc,
+ .pm_prepare = &evergreen_pm_prepare,
+@@ -903,9 +906,9 @@ static struct radeon_asic cayman_asic = {
+ .get_vblank_counter = &evergreen_get_vblank_counter,
+ .fence_ring_emit = &r600_fence_ring_emit,
+ .cs_parse = &evergreen_cs_parse,
+- .copy_blit = NULL,
+- .copy_dma = NULL,
+- .copy = NULL,
++ .copy_blit = &evergreen_copy_blit,
++ .copy_dma = &evergreen_copy_blit,
++ .copy = &evergreen_copy_blit,
+ .get_engine_clock = &radeon_atom_get_engine_clock,
+ .set_engine_clock = &radeon_atom_set_engine_clock,
+ .get_memory_clock = &radeon_atom_get_memory_clock,
+@@ -920,6 +923,7 @@ static struct radeon_asic cayman_asic = {
+ .hpd_fini = &evergreen_hpd_fini,
+ .hpd_sense = &evergreen_hpd_sense,
+ .hpd_set_polarity = &evergreen_hpd_set_polarity,
++ .ioctl_wait_idle = r600_ioctl_wait_idle,
+ .gui_idle = &r600_gui_idle,
+ .pm_misc = &evergreen_pm_misc,
+ .pm_prepare = &evergreen_pm_prepare,
+diff --git a/drivers/gpu/drm/radeon/radeon_atpx_handler.c b/drivers/gpu/drm/radeon/radeon_atpx_handler.c
+index ed5dfe5..9d95792 100644
+--- a/drivers/gpu/drm/radeon/radeon_atpx_handler.c
++++ b/drivers/gpu/drm/radeon/radeon_atpx_handler.c
+@@ -15,6 +15,9 @@
+ #define ATPX_VERSION 0
+ #define ATPX_GPU_PWR 2
+ #define ATPX_MUX_SELECT 3
++#define ATPX_I2C_MUX_SELECT 4
++#define ATPX_SWITCH_START 5
++#define ATPX_SWITCH_END 6
+
+ #define ATPX_INTEGRATED 0
+ #define ATPX_DISCRETE 1
+@@ -149,13 +152,35 @@ static int radeon_atpx_switch_mux(acpi_handle handle, int mux_id)
+ return radeon_atpx_execute(handle, ATPX_MUX_SELECT, mux_id);
+ }
+
++static int radeon_atpx_switch_i2c_mux(acpi_handle handle, int mux_id)
++{
++ return radeon_atpx_execute(handle, ATPX_I2C_MUX_SELECT, mux_id);
++}
++
++static int radeon_atpx_switch_start(acpi_handle handle, int gpu_id)
++{
++ return radeon_atpx_execute(handle, ATPX_SWITCH_START, gpu_id);
++}
++
++static int radeon_atpx_switch_end(acpi_handle handle, int gpu_id)
++{
++ return radeon_atpx_execute(handle, ATPX_SWITCH_END, gpu_id);
++}
+
+ static int radeon_atpx_switchto(enum vga_switcheroo_client_id id)
+ {
++ int gpu_id;
++
+ if (id == VGA_SWITCHEROO_IGD)
+- radeon_atpx_switch_mux(radeon_atpx_priv.atpx_handle, 0);
++ gpu_id = ATPX_INTEGRATED;
+ else
+- radeon_atpx_switch_mux(radeon_atpx_priv.atpx_handle, 1);
++ gpu_id = ATPX_DISCRETE;
++
++ radeon_atpx_switch_start(radeon_atpx_priv.atpx_handle, gpu_id);
++ radeon_atpx_switch_mux(radeon_atpx_priv.atpx_handle, gpu_id);
++ radeon_atpx_switch_i2c_mux(radeon_atpx_priv.atpx_handle, gpu_id);
++ radeon_atpx_switch_end(radeon_atpx_priv.atpx_handle, gpu_id);
++
+ return 0;
+ }
+
+diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
+index 8caf546..089ab92 100644
+--- a/drivers/gpu/drm/radeon/radeon_combios.c
++++ b/drivers/gpu/drm/radeon/radeon_combios.c
+@@ -2504,6 +2504,12 @@ bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev)
+ return true;
+ }
+
++static const char *thermal_controller_names[] = {
++ "NONE",
++ "lm63",
++ "adm1032",
++};
++
+ void radeon_combios_get_power_modes(struct radeon_device *rdev)
+ {
+ struct drm_device *dev = rdev->ddev;
+@@ -2524,6 +2530,54 @@ void radeon_combios_get_power_modes(struct radeon_device *rdev)
+ return;
+ }
+
++ /* check for a thermal chip */
++ offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE);
++ if (offset) {
++ u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0;
++ struct radeon_i2c_bus_rec i2c_bus;
++
++ rev = RBIOS8(offset);
++
++ if (rev == 0) {
++ thermal_controller = RBIOS8(offset + 3);
++ gpio = RBIOS8(offset + 4) & 0x3f;
++ i2c_addr = RBIOS8(offset + 5);
++ } else if (rev == 1) {
++ thermal_controller = RBIOS8(offset + 4);
++ gpio = RBIOS8(offset + 5) & 0x3f;
++ i2c_addr = RBIOS8(offset + 6);
++ } else if (rev == 2) {
++ thermal_controller = RBIOS8(offset + 4);
++ gpio = RBIOS8(offset + 5) & 0x3f;
++ i2c_addr = RBIOS8(offset + 6);
++ clk_bit = RBIOS8(offset + 0xa);
++ data_bit = RBIOS8(offset + 0xb);
++ }
++ if ((thermal_controller > 0) && (thermal_controller < 3)) {
++ DRM_INFO("Possible %s thermal controller at 0x%02x\n",
++ thermal_controller_names[thermal_controller],
++ i2c_addr >> 1);
++ if (gpio == DDC_LCD) {
++ /* MM i2c */
++ i2c_bus.valid = true;
++ i2c_bus.hw_capable = true;
++ i2c_bus.mm_i2c = true;
++ i2c_bus.i2c_id = 0xa0;
++ } else if (gpio == DDC_GPIO)
++ i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit);
++ else
++ i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
++ rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
++ if (rdev->pm.i2c_bus) {
++ struct i2c_board_info info = { };
++ const char *name = thermal_controller_names[thermal_controller];
++ info.addr = i2c_addr >> 1;
++ strlcpy(info.type, name, sizeof(info.type));
++ i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
++ }
++ }
++ }
++
+ if (rdev->flags & RADEON_IS_MOBILITY) {
+ offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
+ if (offset) {
+diff --git a/drivers/gpu/drm/radeon/radeon_cursor.c b/drivers/gpu/drm/radeon/radeon_cursor.c
+index 017ac54..5df2acd 100644
+--- a/drivers/gpu/drm/radeon/radeon_cursor.c
++++ b/drivers/gpu/drm/radeon/radeon_cursor.c
+@@ -167,9 +167,6 @@ int radeon_crtc_cursor_set(struct drm_crtc *crtc,
+ return -EINVAL;
+ }
+
+- radeon_crtc->cursor_width = width;
+- radeon_crtc->cursor_height = height;
+-
+ obj = drm_gem_object_lookup(crtc->dev, file_priv, handle);
+ if (!obj) {
+ DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, radeon_crtc->crtc_id);
+@@ -180,6 +177,9 @@ int radeon_crtc_cursor_set(struct drm_crtc *crtc,
+ if (ret)
+ goto fail;
+
++ radeon_crtc->cursor_width = width;
++ radeon_crtc->cursor_height = height;
++
+ radeon_lock_cursor(crtc, true);
+ /* XXX only 27 bit offset for legacy cursor */
+ radeon_set_cursor(crtc, obj, gpu_addr);
+diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
+index 0444911..fc44376 100644
+--- a/drivers/gpu/drm/radeon/radeon_drv.c
++++ b/drivers/gpu/drm/radeon/radeon_drv.c
+@@ -50,9 +50,10 @@
+ * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
+ * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
+ * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
++ * 2.10.0 - fusion 2D tiling
+ */
+ #define KMS_DRIVER_MAJOR 2
+-#define KMS_DRIVER_MINOR 9
++#define KMS_DRIVER_MINOR 10
+ #define KMS_DRIVER_PATCHLEVEL 0
+ int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
+ int radeon_driver_unload_kms(struct drm_device *dev);
+diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
+index 320ddc3..4fec348 100644
+--- a/drivers/gpu/drm/radeon/radeon_pm.c
++++ b/drivers/gpu/drm/radeon/radeon_pm.c
+@@ -485,6 +485,7 @@ static int radeon_hwmon_init(struct radeon_device *rdev)
+ case THERMAL_TYPE_RV6XX:
+ case THERMAL_TYPE_RV770:
+ case THERMAL_TYPE_EVERGREEN:
++ case THERMAL_TYPE_NI:
+ case THERMAL_TYPE_SUMO:
+ rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
+ if (IS_ERR(rdev->pm.int_hwmon_dev)) {
+diff --git a/drivers/gpu/drm/radeon/reg_srcs/cayman b/drivers/gpu/drm/radeon/reg_srcs/cayman
+index 6334f8a..0aa8e85 100644
+--- a/drivers/gpu/drm/radeon/reg_srcs/cayman
++++ b/drivers/gpu/drm/radeon/reg_srcs/cayman
+@@ -33,6 +33,7 @@ cayman 0x9400
+ 0x00008E48 SQ_EX_ALLOC_TABLE_SLOTS
+ 0x00009100 SPI_CONFIG_CNTL
+ 0x0000913C SPI_CONFIG_CNTL_1
++0x00009508 TA_CNTL_AUX
+ 0x00009830 DB_DEBUG
+ 0x00009834 DB_DEBUG2
+ 0x00009838 DB_DEBUG3
+diff --git a/drivers/gpu/drm/radeon/reg_srcs/evergreen b/drivers/gpu/drm/radeon/reg_srcs/evergreen
+index 7e16371..0e28cae 100644
+--- a/drivers/gpu/drm/radeon/reg_srcs/evergreen
++++ b/drivers/gpu/drm/radeon/reg_srcs/evergreen
+@@ -46,6 +46,7 @@ evergreen 0x9400
+ 0x00008E48 SQ_EX_ALLOC_TABLE_SLOTS
+ 0x00009100 SPI_CONFIG_CNTL
+ 0x0000913C SPI_CONFIG_CNTL_1
++0x00009508 TA_CNTL_AUX
+ 0x00009700 VC_CNTL
+ 0x00009714 VC_ENHANCE
+ 0x00009830 DB_DEBUG
diff --git a/kernel.spec b/kernel.spec
index 15b2bc1..587ce74 100644
--- a/kernel.spec
+++ b/kernel.spec
@@ -687,6 +687,7 @@ Patch1829: drm-intel-restore-mode.patch
# radeon - new hw + fixes for fusion and t500 regression
Patch1839: drm-radeon-fix-regression-on-atom-cards-with-hardcoded-EDID-record.patch
Patch1840: drm-radeon-update.patch
+Patch1841: drm-radeon-update2.patch
Patch1900: linux-2.6-intel-iommu-igfx.patch
@@ -1344,6 +1345,7 @@ ApplyPatch drm-intel-restore-mode.patch
# radeon DRM (add cayman support)
ApplyPatch drm-radeon-fix-regression-on-atom-cards-with-hardcoded-EDID-record.patch -R
ApplyPatch drm-radeon-update.patch
+ApplyPatch drm-radeon-update2.patch
# linux1394 git patches
#ApplyPatch linux-2.6-firewire-git-update.patch
@@ -2015,6 +2017,9 @@ fi
# and build.
%changelog
+* Wed May 25 2011 Dave Airlie <airlied at redhat.com>
+- drm-radeon-update2.patch: more radeon updates + cayman accel support
+
* Tue May 24 2011 Kyle McMartin <kmcmartin at redhat.com>
- hid-multitouch: add support for elo touchsystems panels (requested
by hadess, backported from hid-next)
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