[llvm] Add patch to fix building OCAML on ARM

Peter Robinson pbrobinson at fedoraproject.org
Fri Jul 13 07:33:27 UTC 2012


commit 23fedafb32d10739a6fd23a759c08c2da5e75d3f
Author: Peter Robinson <pbrobinson at gmail.com>
Date:   Fri Jul 13 08:33:20 2012 +0100

    Add patch to fix building OCAML on ARM

 llvm-fix-ocaml.patch |  128 ++++++++++++++++++++++++++++++++++++++++++++++++++
 llvm.spec            |   10 ++++-
 2 files changed, 137 insertions(+), 1 deletions(-)
---
diff --git a/llvm-fix-ocaml.patch b/llvm-fix-ocaml.patch
new file mode 100644
index 0000000..b737df0
--- /dev/null
+++ b/llvm-fix-ocaml.patch
@@ -0,0 +1,128 @@
+Index: lib/Target/ARM/ARMFrameLowering.cpp
+===================================================================
+--- lib/Target/ARM/ARMFrameLowering.cpp	(revision 159085)
++++ lib/Target/ARM/ARMFrameLowering.cpp	(working copy)
+@@ -15,6 +15,8 @@
+ #include "ARMBaseInstrInfo.h"
+ #include "ARMBaseRegisterInfo.h"
+ #include "ARMMachineFunctionInfo.h"
++#include "llvm/CallingConv.h"
++#include "llvm/Function.h"
+ #include "MCTargetDesc/ARMAddressingModes.h"
+ #include "llvm/Function.h"
+ #include "llvm/CodeGen/MachineFrameInfo.h"
+@@ -151,6 +153,10 @@
+   int FramePtrSpillFI = 0;
+   int D8SpillFI = 0;
+ 
++  // All calls are tail calls in GHC calling conv, and functions have no prologue/epilogue.
++  if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
++    return;
++
+   // Allocate the vararg register save area. This is not counted in NumBytes.
+   if (VARegSaveSize)
+     emitSPUpdate(isARM, MBB, MBBI, dl, TII, -VARegSaveSize,
+@@ -354,6 +360,10 @@
+   int NumBytes = (int)MFI->getStackSize();
+   unsigned FramePtr = RegInfo->getFrameRegister(MF);
+ 
++  // All calls are tail calls in GHC calling conv, and functions have no prologue/epilogue.
++  if (MF.getFunction()->getCallingConv() == CallingConv::GHC)
++    return;
++
+   if (!AFI->hasStackFrame()) {
+     if (NumBytes != 0)
+       emitSPUpdate(isARM, MBB, MBBI, dl, TII, NumBytes);
+Index: lib/Target/ARM/ARMISelLowering.cpp
+===================================================================
+--- lib/Target/ARM/ARMISelLowering.cpp	(revision 159085)
++++ lib/Target/ARM/ARMISelLowering.cpp	(working copy)
+@@ -1171,6 +1171,8 @@
+     return (Return ? RetCC_ARM_AAPCS : CC_ARM_AAPCS);
+   case CallingConv::ARM_APCS:
+     return (Return ? RetCC_ARM_APCS : CC_ARM_APCS);
++  case CallingConv::GHC:
++    return (Return ? RetCC_ARM_APCS : CC_ARM_APCS_GHC);
+   }
+ }
+ 
+Index: lib/Target/ARM/ARMCallingConv.td
+===================================================================
+--- lib/Target/ARM/ARMCallingConv.td	(revision 159085)
++++ lib/Target/ARM/ARMCallingConv.td	(working copy)
+@@ -79,7 +79,26 @@
+   CCDelegateTo<RetCC_ARM_APCS>
+ ]>;
+ 
++//===----------------------------------------------------------------------===//
++// ARM APCS Calling Convention for GHC
++//===----------------------------------------------------------------------===//
+ 
++def CC_ARM_APCS_GHC : CallingConv<[
++  // Handle all vector types as either f64 or v2f64.
++  CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
++  CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
++
++  CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>,
++  CCIfType<[f64], CCAssignToReg<[D8, D9, D10, D11]>>,
++  CCIfType<[f32], CCAssignToReg<[S16, S17, S18, S19, S20, S21, S22, S23]>>,
++
++  // Promote i8/i16 arguments to i32.
++  CCIfType<[i8, i16], CCPromoteToType<i32>>,
++
++  // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, SpLim
++  CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>>
++]>;
++
+ //===----------------------------------------------------------------------===//
+ // ARM AAPCS (EABI) Calling Convention, common parts
+ //===----------------------------------------------------------------------===//
+@@ -171,3 +190,9 @@
+ // iOS ABI deviates from ARM standard ABI. R9 is not a callee-saved register.
+ // Also save R7-R4 first to match the stack frame fixed spill areas.
+ def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>;
++
++// GHC set of callee saved regs is empty as all those regs are
++// used for passing STG regs around
++// sub/add LR is a workaround for not being able to compile empty list:
++// def CSR_GHC : CalleeSavedRegs<()>;
++def CSR_GHC : CalleeSavedRegs<(sub (add LR), LR)>;
+Index: lib/Target/ARM/ARMFastISel.cpp
+===================================================================
+--- lib/Target/ARM/ARMFastISel.cpp	(revision 159085)
++++ lib/Target/ARM/ARMFastISel.cpp	(working copy)
+@@ -1835,6 +1835,11 @@
+     return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS);
+   case CallingConv::ARM_APCS:
+     return (Return ? RetCC_ARM_APCS: CC_ARM_APCS);
++  case CallingConv::GHC:
++    if (Return)
++      llvm_unreachable("Can't return in GHC call convention");
++    else
++      return CC_ARM_APCS_GHC;
+   }
+ }
+ 
+--- lib/Target/ARM/ARMBaseRegisterInfo.cpp.orig	2012-07-12 09:59:58.181723592 +0100
++++ lib/Target/ARM/ARMBaseRegisterInfo.cpp	2012-07-12 10:01:15.301344412 +0100
+@@ -62,7 +62,19 @@
+ 
+ const uint16_t*
+ ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
+-  return (STI.isTargetIOS()) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList;
++  bool ghcCall = false;
++
++  if (MF) {
++    const Function *F = MF->getFunction();
++    ghcCall = (F ? F->getCallingConv() == CallingConv::GHC : false);
++  }
++
++  if (ghcCall) {
++      return CSR_GHC_SaveList;
++  }
++  else {
++      return (STI.isTargetIOS()) ? CSR_iOS_SaveList : CSR_AAPCS_SaveList;
++  }
+ }
+ 
+ const uint32_t*
diff --git a/llvm.spec b/llvm.spec
index ee36aa7..258c121 100644
--- a/llvm.spec
+++ b/llvm.spec
@@ -36,7 +36,7 @@ ExcludeArch: s390 s390x ppc ppc64
 
 Name:           llvm
 Version:        3.1
-Release:        5%{?dist}
+Release:        6%{?dist}
 Summary:        The Low Level Virtual Machine
 
 Group:          Development/Languages
@@ -60,6 +60,9 @@ Patch610: 0001-Add-r600-TargetInfo.patch
 Patch611: 0002-r600-Add-some-target-builtins.patch
 Patch612: 0003-r600-Add-read_global_size-and-read_local_size-builti.patch
 
+# ocaml
+Patch700: llvm-fix-ocaml.patch
+
 BuildRequires:  bison
 BuildRequires:  chrpath
 BuildRequires:  flex
@@ -266,6 +269,8 @@ pushd tools/clang
 %patch612 -p1 -b .r612
 popd
 
+%patch700 -p0 -b .ocaml
+
 # fix ld search path
 sed -i 's|/lib /usr/lib $lt_ld_extra|%{_libdir} $lt_ld_extra|' \
     ./configure
@@ -549,6 +554,9 @@ exit 0
 %endif
 
 %changelog
+* Thu Jul 12 2012 Peter Robinson <pbrobinson at fedoraproject.org> - 3.1-6
+- Add patch to fix building OCAML on ARM
+
 * Wed Jul  4 2012 Michel Salim <salimma at fedoraproject.org> - 3.1-5
 - Actually set runtime dependency on libstdc++ 4.7.1
 


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