[ghdl] disable cloog

[sailer]

commit a67c00057ed65f791925bff9054dc72ae2f493cf
Author: Thomas Sailer <t.sailer at alumni.ethz.ch>
Date:   Fri Feb 1 18:22:31 2013 +0100

    disable cloog

 ghdl.spec |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)
---
diff --git a/ghdl.spec b/ghdl.spec
index 6461d41..033e7d7 100644
--- a/ghdl.spec
+++ b/ghdl.spec
@@ -3,11 +3,11 @@
 %global gccinstver 4.7.3
 %global ghdlver 0.29
 %global ghdlsvnver 150
-%if 0%{?rhel} >= 7
+#if 0%{?rhel} >= 7
 %global build_cloog 0
-%else
-%global build_cloog 1
-%endif
+#else
+#global build_cloog 1
+#endif
 
 Summary: A VHDL simulator, using the GCC technology
 Name: ghdl