[arm-none-eabi-binutils-cs/f18] make it build with new texinfo
Michal Hlavinka
mhlavink at fedoraproject.org
Wed Feb 20 15:15:21 UTC 2013
commit 904abd0799ceba8bc678bbbb9d00715b5de96337
Author: Michal Hlavinka <mhlavink at redhat.com>
Date: Wed Feb 20 16:15:09 2013 +0100
make it build with new texinfo
arm-none-eabi-binutils-cs-2012.09.63-fixtex.patch | 494 +++++++++++++++++++++
arm-none-eabi-binutils-cs.spec | 9 +-
2 files changed, 501 insertions(+), 2 deletions(-)
---
diff --git a/arm-none-eabi-binutils-cs-2012.09.63-fixtex.patch b/arm-none-eabi-binutils-cs-2012.09.63-fixtex.patch
new file mode 100644
index 0000000..f30c37f
--- /dev/null
+++ b/arm-none-eabi-binutils-cs-2012.09.63-fixtex.patch
@@ -0,0 +1,494 @@
+diff -up binutils-2012.09/bfd/doc/bfd.texinfo.fixtex binutils-2012.09/bfd/doc/bfd.texinfo
+--- binutils-2012.09/bfd/doc/bfd.texinfo.fixtex 2012-10-30 18:24:00.000000000 +0100
++++ binutils-2012.09/bfd/doc/bfd.texinfo 2013-02-20 14:37:36.405844568 +0100
+@@ -1,7 +1,7 @@
+ \input texinfo.tex
+ @setfilename bfd.info
+ @c Copyright 1988, 1989, 1990, 1991, 1992, 1993, 1994, 1997, 2000,
+- at c 2001, 2002, 2003, 2006, 2007, 2008, 2009
++ at c 2001, 2002, 2003, 2006, 2007, 2008, 2009, 2013
+ @c Free Software Foundation, Inc.
+ @c
+ @synindex fn cp
+@@ -16,7 +16,8 @@
+ @copying
+ This file documents the BFD library.
+
+-Copyright @copyright{} 1991, 2000, 2001, 2003, 2006, 2007, 2008 Free Software Foundation, Inc.
++Copyright @copyright{} 1991, 2000, 2001, 2003, 2006, 2007, 2008, 2013
++Free Software Foundation, Inc.
+
+ Permission is granted to copy, distribute and/or modify this document
+ under the terms of the GNU Free Documentation License, Version 1.3 or
+@@ -64,7 +65,8 @@ included in the section entitled ``GNU F
+ @end tex
+
+ @vskip 0pt plus 1filll
+-Copyright @copyright{} 1991, 2001, 2003, 2006, 2008 Free Software Foundation, Inc.
++Copyright @copyright{} 1991, 2001, 2003, 2006, 2008, 2013
++Free Software Foundation, Inc.
+
+ Permission is granted to copy, distribute and/or modify this document
+ under the terms of the GNU Free Documentation License, Version 1.3
+@@ -322,7 +324,7 @@ All of BFD lives in one directory.
+ @printindex cp
+
+ @tex
+-% I think something like @colophon should be in texinfo. In the
++% I think something like @@colophon should be in texinfo. In the
+ % meantime:
+ \long\def\colophon{\hbox to0pt{}\vfill
+ \centerline{The body of this manual is set in}
+@@ -333,7 +335,7 @@ All of BFD lives in one directory.
+ \centerline{{\sl\fontname\tensl\/}}
+ \centerline{are used for emphasis.}\vfill}
+ \page\colophon
+-% Blame: doc at cygnus.com, 28mar91.
++% Blame: doc@@cygnus.com, 28mar91.
+ @end tex
+
+ @bye
+diff -up binutils-2012.09/binutils/doc/binutils.texi.fixtex binutils-2012.09/binutils/doc/binutils.texi
+--- binutils-2012.09/binutils/doc/binutils.texi.fixtex 2012-10-30 18:23:59.000000000 +0100
++++ binutils-2012.09/binutils/doc/binutils.texi 2013-02-20 14:37:36.406844576 +0100
+@@ -4375,7 +4375,7 @@ equivalent. At least one of the @option{
+
+ @table @env
+
+- at itemx --input-mach=@var{machine}
++ at item --input-mach=@var{machine}
+ Set the matching input ELF machine type to @var{machine}. If
+ @option{--input-mach} isn't specified, it will match any ELF
+ machine types.
+@@ -4383,21 +4383,21 @@ machine types.
+ The supported ELF machine types are, @var{L1OM}, @var{K1OM} and
+ @var{x86-64}.
+
+- at itemx --output-mach=@var{machine}
++ at item --output-mach=@var{machine}
+ Change the ELF machine type in the ELF header to @var{machine}. The
+ supported ELF machine types are the same as @option{--input-mach}.
+
+- at itemx --input-type=@var{type}
++ at item --input-type=@var{type}
+ Set the matching input ELF file type to @var{type}. If
+ @option{--input-type} isn't specified, it will match any ELF file types.
+
+ The supported ELF file types are, @var{rel}, @var{exec} and @var{dyn}.
+
+- at itemx --output-type=@var{type}
++ at item --output-type=@var{type}
+ Change the ELF file type in the ELF header to @var{type}. The
+ supported ELF types are the same as @option{--input-type}.
+
+- at itemx --input-osabi=@var{osabi}
++ at item --input-osabi=@var{osabi}
+ Set the matching input ELF file OSABI to @var{osabi}. If
+ @option{--input-osabi} isn't specified, it will match any ELF OSABIs.
+
+@@ -4407,7 +4407,7 @@ The supported ELF OSABIs are, @var{none}
+ @var{FreeBSD}, @var{TRU64}, @var{Modesto}, @var{OpenBSD}, @var{OpenVMS},
+ @var{NSK}, @var{AROS} and @var{FenixOS}.
+
+- at itemx --output-osabi=@var{osabi}
++ at item --output-osabi=@var{osabi}
+ Change the ELF OSABI in the ELF header to @var{osabi}. The
+ supported ELF OSABI are the same as @option{--input-osabi}.
+
+diff -up binutils-2012.09/gas/doc/c-arc.texi.fixtex binutils-2012.09/gas/doc/c-arc.texi
+--- binutils-2012.09/gas/doc/c-arc.texi.fixtex 2012-10-30 18:23:49.000000000 +0100
++++ binutils-2012.09/gas/doc/c-arc.texi 2013-02-20 14:37:36.406844576 +0100
+@@ -220,7 +220,7 @@ The extension instructions are not macro
+ encodings for use of these instructions according to the specification
+ by the user. The parameters are:
+
+- at table @bullet
++ at table @code
+ @item @var{name}
+ Name of the extension instruction
+
+diff -up binutils-2012.09/gas/doc/c-arm.texi.fixtex binutils-2012.09/gas/doc/c-arm.texi
+--- binutils-2012.09/gas/doc/c-arm.texi.fixtex 2012-10-30 18:23:49.000000000 +0100
++++ binutils-2012.09/gas/doc/c-arm.texi 2013-02-20 15:55:48.682995079 +0100
+@@ -20,6 +20,7 @@
+ * ARM Options:: Options
+ * ARM Syntax:: Syntax
+ * ARM Floating Point:: Floating Point
++* ARM Relocations:: ARM relocation generation
+ * ARM Directives:: ARM Machine Directives
+ * ARM Opcodes:: Opcodes
+ * ARM Mapping Symbols:: Mapping Symbols
+@@ -38,7 +39,7 @@
+ This option specifies the target processor. The assembler will issue an
+ error message if an attempt is made to assemble an instruction which
+ will not execute on the target processor. The following processor names are
+-recognized:
++recognized:
+ @code{arm1},
+ @code{arm2},
+ @code{arm250},
+@@ -131,25 +132,25 @@ recognized:
+ @code{i80200} (Intel XScale processor)
+ @code{iwmmxt} (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
+ and
+- at code{xscale}.
++ at code{xscale}.
+ The special name @code{all} may be used to allow the
+ assembler to accept instructions valid for any ARM processor.
+
+-In addition to the basic instruction set, the assembler can be told to
+-accept various extension mnemonics that extend the processor using the
++In addition to the basic instruction set, the assembler can be told to
++accept various extension mnemonics that extend the processor using the
+ co-processor instruction space. For example, @code{-mcpu=arm920+maverick}
+-is equivalent to specifying @code{-mcpu=ep9312}.
++is equivalent to specifying @code{-mcpu=ep9312}.
+
+-Multiple extensions may be specified, separated by a @code{+}. The
++Multiple extensions may be specified, separated by a @code{+}. The
+ extensions should be specified in ascending alphabetical order.
+
+-Some extensions may be restricted to particular architectures; this is
++Some extensions may be restricted to particular architectures; this is
+ documented in the list of extensions below.
+
+-Extension mnemonics may also be removed from those the assembler accepts.
+-This is done be prepending @code{no} to the option that adds the extension.
+-Extensions that are removed should be listed after all extensions which have
+-been added, again in ascending alphabetical order. For example,
++Extension mnemonics may also be removed from those the assembler accepts.
++This is done be prepending @code{no} to the option that adds the extension.
++Extensions that are removed should be listed after all extensions which have
++been added, again in ascending alphabetical order. For example,
+ @code{-mcpu=ep9312+nomaverick} is equivalent to specifying @code{-mcpu=arm920}.
+
+
+@@ -164,7 +165,7 @@ The following extensions are currently s
+ @code{os} (Operating System for v6M architecture),
+ @code{sec} (Security Extensions for v6K and v7-A architectures),
+ @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
+- at code{virt} (Virtualization Extensions for v7-A architecture, implies
++ at code{virt} (Virtualization Extensions for v7-A architecture, implies
+ @code{idiv}),
+ and
+ @code{xscale}.
+@@ -173,8 +174,8 @@ and
+ @item -march=@var{architecture}[+ at var{extension}@dots{}]
+ This option specifies the target architecture. The assembler will issue
+ an error message if an attempt is made to assemble an instruction which
+-will not execute on the target architecture. The following architecture
+-names are recognized:
++will not execute on the target architecture. The following architecture
++names are recognized:
+ @code{armv1},
+ @code{armv2},
+ @code{armv2a},
+@@ -218,7 +219,7 @@ extension options as the @code{-mcpu} op
+
+ This option specifies the floating point format to assemble for. The
+ assembler will issue an error message if an attempt is made to assemble
+-an instruction which will not execute on the target floating point unit.
++an instruction which will not execute on the target floating point unit.
+ The following format options are recognized:
+ @code{softfpa},
+ @code{fpe},
+@@ -260,14 +261,14 @@ In addition to determining which instruc
+ also affects the way in which the @code{.double} assembler directive behaves
+ when assembling little-endian code.
+
+-The default is dependent on the processor selected. For Architecture 5 or
+-later, the default is to assembler for VFP instructions; for earlier
++The default is dependent on the processor selected. For Architecture 5 or
++later, the default is to assembler for VFP instructions; for earlier
+ architectures the default is to assemble for FPA instructions.
+
+ @cindex @code{-mthumb} command line option, ARM
+ @item -mthumb
+ This option specifies that the assembler should start assembling Thumb
+-instructions; that is, it should behave as though the file starts with a
++instructions; that is, it should behave as though the file starts with a
+ @code{.code 16} directive.
+
+ @cindex @code{-mthumb-interwork} command line option, ARM
+@@ -303,7 +304,7 @@ Calling Standard.
+
+ @cindex @code{-matpcs} command line option, ARM
+ @item -matpcs
+-This option specifies that the output generated by the assembler should
++This option specifies that the output generated by the assembler should
+ be marked as supporting the Arm/Thumb Procedure Calling Standard. If
+ enabled this option will cause the assembler to create an empty
+ debugging section in the object file called .arm.atpcs. Debuggers can
+@@ -376,7 +377,6 @@ features. The default is to warn.
+ * ARM-Instruction-Set:: Instruction Set
+ * ARM-Chars:: Special Characters
+ * ARM-Regs:: Register Names
+-* ARM-Relocations:: Relocations
+ * ARM-Neon-Alignment:: NEON Alignment Specifiers
+ @end menu
+
+@@ -388,7 +388,7 @@ ARM and THUMB instructions had their own
+ @code{unified} syntax, which can be selected via the @code{.syntax}
+ directive, and has the following main features:
+
+- at table @bullet
++ at table @code
+ @item
+ Immediate operands do not require a @code{#} prefix.
+
+@@ -471,8 +471,8 @@ so @samp{: @var{align}} is used instead.
+ @cindex ARM floating point (@sc{ieee})
+ The ARM family uses @sc{ieee} floating-point numbers.
+
+- at node ARM-Relocations
+- at subsection ARM relocation generation
++ at node ARM Relocations
++ at section ARM relocation generation
+
+ @cindex data relocations, ARM
+ @cindex ARM data relocations
+@@ -546,13 +546,13 @@ boundary). This is for compatibility wi
+ Select the target architecture. Valid values for @var{name} are the same as
+ for the @option{-march} commandline option.
+
+-Specifying @code{.arch} clears any previously selected architecture
++Specifying @code{.arch} clears any previously selected architecture
+ extensions.
+
+ @cindex @code{.arch_extension} directive, ARM
+ @item .arch_extension @var{name}
+-Add or remove an architecture extension to the target architecture. Valid
+-values for @var{name} are the same as those accepted as architectural
++Add or remove an architecture extension to the target architecture. Valid
++values for @var{name} are the same as those accepted as architectural
+ extensions by the @option{-mcpu} commandline option.
+
+ @code{.arch_extension} may be used multiple times to add or remove extensions
+@@ -592,7 +592,7 @@ selects Thumb, with the value 32 selecti
+ Select the target processor. Valid values for @var{name} are the same as
+ for the @option{-mcpu} commandline option.
+
+-Specifying @code{.cpu} clears any previously selected architecture
++Specifying @code{.cpu} clears any previously selected architecture
+ extensions.
+
+ @c DDDDDDDDDDDDDDDDDDDDDDDDDD
+@@ -658,7 +658,7 @@ The @var{value} is either a @code{number
+ @code{number, "string"} depending on the tag.
+
+ Note - the following legacy values are also accepted by @var{tag}:
+- at code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
++ at code{Tag_VFP_arch}, @code{Tag_ABI_align8_needed},
+ @code{Tag_ABI_align8_preserved}, @code{Tag_VFP_HP_extension},
+
+ @cindex @code{.even} directive, ARM
+@@ -950,7 +950,7 @@ used in favour of @code{.save} for savin
+ @cindex opcodes for ARM
+ @code{@value{AS}} implements all the standard ARM opcodes. It also
+ implements several pseudo opcodes, including several synthetic load
+-instructions.
++instructions.
+
+ @table @code
+
+@@ -964,7 +964,7 @@ This pseudo op will always evaluate to a
+ nothing. Currently it will evaluate to MOV r0, r0.
+
+ @cindex @code{LDR reg,=<label>} pseudo op, ARM
+- at item LDR
++ at item LDR
+ @smallexample
+ ldr <register> , = <expression>
+ @end smallexample
+@@ -989,7 +989,7 @@ the ADR instruction, then an error will
+ will not make use of the literal pool.
+
+ @cindex @code{ADRL reg,<label>} pseudo op, ARM
+- at item ADRL
++ at item ADRL
+ @smallexample
+ adrl <register> <label>
+ @end smallexample
+@@ -1065,12 +1065,12 @@ that G++ generates for the following C++
+ @verbatim
+ void callee (int *);
+
+-int
+-caller ()
++int
++caller ()
+ {
+ int i;
+ callee (&i);
+- return i;
++ return i;
+ }
+ @end verbatim
+
+@@ -1127,7 +1127,7 @@ The @code{.fnstart} (@pxref{arm_fnstart,
+ op appears immediately before the first instruction of the function
+ while the @code{.fnend} (@pxref{arm_fnend,,.fnend pseudo op}) pseudo
+ op appears immediately after the last instruction of the function.
+-These pseudo ops specify the range of the function.
++These pseudo ops specify the range of the function.
+
+ Only the order of the other pseudos ops (e.g., @code{.setfp} or
+ @code{.pad}) matters; their exact locations are irrelevant. In the
+diff -up binutils-2012.09/gas/doc/c-mips.texi.fixtex binutils-2012.09/gas/doc/c-mips.texi
+--- binutils-2012.09/gas/doc/c-mips.texi.fixtex 2012-10-30 18:23:49.000000000 +0100
++++ binutils-2012.09/gas/doc/c-mips.texi 2013-02-20 14:37:36.407844584 +0100
+@@ -1,5 +1,5 @@
+ @c Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1999, 2000, 2001,
+- at c 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011
++ at c 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011, 2013
+ @c Free Software Foundation, Inc.
+ @c This is part of the GAS manual.
+ @c For copying conditions, see the file as.texinfo.
+@@ -245,7 +245,7 @@ the @samp{mad} and @samp{madu} instructi
+ instructions around accesses to the @samp{HI} and @samp{LO} registers.
+ @samp{-no-m4650} turns off this option.
+
+- at itemx -m3900
++ at item -m3900
+ @itemx -no-m3900
+ @itemx -m4100
+ @itemx -no-m4100
+diff -up binutils-2012.09/gas/doc/c-score.texi.fixtex binutils-2012.09/gas/doc/c-score.texi
+--- binutils-2012.09/gas/doc/c-score.texi.fixtex 2012-10-30 18:23:49.000000000 +0100
++++ binutils-2012.09/gas/doc/c-score.texi 2013-02-20 14:37:36.407844584 +0100
+@@ -1,4 +1,4 @@
+- at c Copyright 2009, 2011
++ at c Copyright 2009, 2011, 2013
+ @c Free Software Foundation, Inc.
+ @c This is part of the GAS manual.
+ @c For copying conditions, see the file as.texinfo.
+@@ -37,7 +37,7 @@ implicitly with the @code{gp} register.
+ @item -EB
+ Assemble code for a big-endian cpu
+
+- at itemx -EL
++ at item -EL
+ Assemble code for a little-endian cpu
+
+ @item -FIXDD
+@@ -49,13 +49,13 @@ Assemble code for no warning message for
+ @item -SCORE5
+ Assemble code for target is SCORE5
+
+- at itemx -SCORE5U
++ at item -SCORE5U
+ Assemble code for target is SCORE5U
+
+- at itemx -SCORE7
++ at item -SCORE7
+ Assemble code for target is SCORE7, this is default setting
+
+- at itemx -SCORE3
++ at item -SCORE3
+ Assemble code for target is SCORE3
+
+ @item -march=score7
+diff -up binutils-2012.09/gas/doc/c-tic54x.texi.fixtex binutils-2012.09/gas/doc/c-tic54x.texi
+--- binutils-2012.09/gas/doc/c-tic54x.texi.fixtex 2012-10-30 18:23:49.000000000 +0100
++++ binutils-2012.09/gas/doc/c-tic54x.texi 2013-02-20 14:37:36.407844584 +0100
+@@ -109,7 +109,7 @@ In this example, x is replaced with SYM2
+ is replaced with x. At this point, x has already been encountered
+ and the substitution stops.
+
+- at smallexample @code
++ at smallexample @code{*}
+ .asg "x",SYM1
+ .asg "SYM1",SYM2
+ .asg "SYM2",x
+@@ -126,14 +126,14 @@ Substitution may be forced in situations
+ ambiguous by placing colons on either side of the subsym. The following
+ code:
+
+- at smallexample @code
++ at smallexample @code{*}
+ .eval "10",x
+ LAB:X: add #x, a
+ @end smallexample
+
+ When assembled becomes:
+
+- at smallexample @code
++ at smallexample @code{*}
+ LAB10 add #10, a
+ @end smallexample
+
+@@ -309,7 +309,7 @@ The @code{LDX} pseudo-op is provided for
+ of a label or address. For example, if an address @code{_label} resides
+ in extended program memory, the value of @code{_label} may be loaded as
+ follows:
+- at smallexample @code
++ at smallexample @code{*}
+ ldx #_label,16,a ; loads extended bits of _label
+ or #_label,a ; loads lower 16 bits of _label
+ bacc a ; full address is in accumulator A
+@@ -345,7 +345,7 @@ Assign @var{name} the string @var{string
+ performed on @var{string} before assignment.
+
+ @cindex @code{eval} directive, TIC54X
+- at itemx .eval @var{string}, @var{name}
++ at item .eval @var{string}, @var{name}
+ Evaluate the contents of string @var{string} and assign the result as a
+ string to the subsym @var{name}. String replacement is performed on
+ @var{string} before assignment.
+diff -up binutils-2012.09/ld/ld.texinfo.fixtex binutils-2012.09/ld/ld.texinfo
+--- binutils-2012.09/ld/ld.texinfo.fixtex 2012-10-30 18:23:49.000000000 +0100
++++ binutils-2012.09/ld/ld.texinfo 2013-02-20 14:37:36.409844601 +0100
+@@ -143,12 +143,12 @@ in the section entitled ``GNU Free Docum
+ @ifset ARM
+ * ARM:: ld and the ARM family
+ @end ifset
+- at ifset HPPA
+-* HPPA ELF32:: ld and HPPA 32-bit ELF
+- at end ifset
+ @ifset M68HC11
+ * M68HC11/68HC12:: ld and the Motorola 68HC11 and 68HC12 families
+ @end ifset
++ at ifset HPPA
++* HPPA ELF32:: ld and HPPA 32-bit ELF
++ at end ifset
+ @ifset M68K
+ * M68K:: ld and Motorola 68K family
+ @end ifset
+@@ -6046,6 +6046,9 @@ functionality are not listed.
+ @ifset I960
+ * i960:: @command{ld} and the Intel 960 family
+ @end ifset
++ at ifset M68HC11
++* M68HC11/68HC12:: @code{ld} and the Motorola 68HC11 and 68HC12 families
++ at end ifset
+ @ifset ARM
+ * ARM:: @command{ld} and the ARM family
+ @end ifset
+@@ -6064,9 +6067,6 @@ functionality are not listed.
+ @ifset MSP430
+ * MSP430:: @command{ld} and MSP430
+ @end ifset
+- at ifset M68HC11
+-* M68HC11/68HC12:: @code{ld} and the Motorola 68HC11 and 68HC12 families
+- at end ifset
+ @ifset POWERPC
+ * PowerPC ELF32:: @command{ld} and PowerPC 32-bit ELF Support
+ @end ifset
+@@ -7944,7 +7944,7 @@ If you have more than one @code{SECT} st
+ @printindex cp
+
+ @tex
+-% I think something like @colophon should be in texinfo. In the
++% I think something like @@colophon should be in texinfo. In the
+ % meantime:
+ \long\def\colophon{\hbox to0pt{}\vfill
+ \centerline{The body of this manual is set in}
+@@ -7955,7 +7955,7 @@ If you have more than one @code{SECT} st
+ \centerline{{\sl\fontname\tensl\/}}
+ \centerline{are used for emphasis.}\vfill}
+ \page\colophon
+-% Blame: doc at cygnus.com, 28mar91.
++% Blame: doc@@cygnus.com, 28mar91.
+ @end tex
+
+ @bye
diff --git a/arm-none-eabi-binutils-cs.spec b/arm-none-eabi-binutils-cs.spec
index 2352568..5a7bd9e 100644
--- a/arm-none-eabi-binutils-cs.spec
+++ b/arm-none-eabi-binutils-cs.spec
@@ -9,7 +9,7 @@
Name: %{target}-binutils-cs
Version: %{cs_date}.%{cs_rel}
-Release: 1%{?dist}
+Release: 2%{?dist}
Summary: GNU Binutils for cross-compilation for %{target} target
Group: Development/Tools
# Most of the sources are licensed under GPLv3+ with these exceptions:
@@ -27,8 +27,9 @@ Source0: binutils-%{cs_date}-%{cs_rel}.tar.bz2
#tar jxvf %{processor_arch}-%{cs_date}-%{cs_rel}-%{target}.src.tar.bz2
Source1: README.fedora
+Patch1: arm-none-eabi-binutils-cs-2012.09.63-fixtex.patch
BuildRequires: flex bison ppl-devel cloog-ppl-devel
-BuildRequires: texinfo texinfo-tex
+BuildRequires: texinfo texinfo-tex perl-podlators
%description
This is a cross-compilation version of GNU Binutils, which can be used to
@@ -43,6 +44,7 @@ of FSF.
%prep
%setup -q -n binutils-%{cs_date}
+%patch1 -p1 -b .fixtex
cp -p %{SOURCE1} .
%build
@@ -86,5 +88,8 @@ rmdir %{buildroot}%{_libdir}
%changelog
+* Wed Feb 20 2013 Michal Hlavinka <mhlavink at redhat.com> - 2012.09.63-2
+- make it build with new texinfo
+
* Mon Dec 03 2012 Michal Hlavinka <mhlavink at redhat.com> - 2012.09.63-1
- new spec for arm-none-eabi using CodeSourcery release
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