[valgrind] 3.9.0-20.svn20140718r14176
Mark Wielaard
mjw at fedoraproject.org
Sat Jul 19 15:10:35 UTC 2014
commit 6f7ad20fd4125c82e297a5f557892884022c13ba
Author: Mark Wielaard <mjw at redhat.com>
Date: Sat Jul 19 15:07:43 2014 +0200
3.9.0-20.svn20140718r14176
- Update to upstream svn r14176
Remove valgrind-3.9.0-arm64-user_regs.patch
- Add ppc64le support
valgrind-3.9.0-ppc64le-initial.patch
valgrind-3.9.0-ppc64le-functional.patch
valgrind-3.9.0-ppc64le-test.patch
valgrind-3.9.0-ppc64le-extra.patch
.gitignore | 1 +
sources | 2 +-
valgrind-3.9.0-arm64-user_regs.patch | 22 -
valgrind-3.9.0-ppc64le-extra.patch | 13 +
valgrind-3.9.0-ppc64le-functional.patch | 6723 ++++++++
valgrind-3.9.0-ppc64le-initial.patch | 3456 +++++
valgrind-3.9.0-ppc64le-test.patch |25843 +++++++++++++++++++++++++++++++
valgrind.spec | 57 +-
8 files changed, 36085 insertions(+), 32 deletions(-)
---
diff --git a/.gitignore b/.gitignore
index 11423a0..f8fae52 100644
--- a/.gitignore
+++ b/.gitignore
@@ -9,3 +9,4 @@
/valgrind-3.9.0-svn20140319r13879.tar.bz2
/valgrind-3.9.0-svn20140513r13961.tar.bz2
/valgrind-3.9.0-svn20140715r14165.tar.bz2
+/valgrind-3.9.0-svn20140718r14176.tar.bz2
diff --git a/sources b/sources
index 405783d..6fa7f2e 100644
--- a/sources
+++ b/sources
@@ -1 +1 @@
-292e552468663f50eab5e5c43adfc8b5 valgrind-3.9.0-svn20140715r14165.tar.bz2
+55a277f9c428152ccfa8339ac5f0c9ec valgrind-3.9.0-svn20140718r14176.tar.bz2
diff --git a/valgrind-3.9.0-ppc64le-extra.patch b/valgrind-3.9.0-ppc64le-extra.patch
new file mode 100644
index 0000000..e4eca34
--- /dev/null
+++ b/valgrind-3.9.0-ppc64le-extra.patch
@@ -0,0 +1,13 @@
+diff --git a/coregrind/vg_preloaded.c b/coregrind/vg_preloaded.c
+index fe8b50a..e36d90d 100644
+--- a/coregrind/vg_preloaded.c
++++ b/coregrind/vg_preloaded.c
+@@ -83,7 +83,7 @@ void * VG_NOTIFY_ON_LOAD(ifunc_wrapper) (void)
+ VALGRIND_GET_ORIG_FN(fn);
+ CALL_FN_W_v(result, fn);
+
+-#if defined(VGP_ppc64_linux)
++#if defined(VGP_ppc64be_linux)
+ /* ppc64 uses function descriptors, so get the actual function entry
+ address for the client request, but return the function descriptor
+ from this function.
diff --git a/valgrind-3.9.0-ppc64le-functional.patch b/valgrind-3.9.0-ppc64le-functional.patch
new file mode 100644
index 0000000..cb3d39f
--- /dev/null
+++ b/valgrind-3.9.0-ppc64le-functional.patch
@@ -0,0 +1,6723 @@
+From cb1fa6b1a906fdb06fbeeb1ce813e8cdcd5a604a Mon Sep 17 00:00:00 2001
+From: Carl Love <carll at us.ibm.com>
+Date: Fri, 20 Jun 2014 12:33:52 -0500
+Subject: [PATCH 2/3] POWER PC, add the functional Little Endian support
+
+The IBM POWER processor now supports both Big Endian and Little Endian.
+The ABI for Little Endian also changes. Specifically, the function
+descriptor is not used, the stack size changed, accessing the TOC
+changed. Functions now have a local and a global entry point. Register
+r2 contains the TOC for local calls and register r12 contains the TOC
+for global calls. This patch makes the functional changes to the
+Valgrind tool. The patch makes the changes needed for the
+none/tests/ppc32 and none/tests/ppc64 Makefile.am. A number of the
+ppc specific tests have Endian dependencies that are not fixed in
+this patch. They are fixed in the next patch.
+
+Signed-off-by: Carl Love <carll at us.ibm.com>
+---
+ VEX/priv/guest_amd64_defs.h | 1 +
+ VEX/priv/guest_amd64_toIR.c | 1 +
+ VEX/priv/guest_arm64_defs.h | 1 +
+ VEX/priv/guest_arm64_toIR.c | 1 +
+ VEX/priv/guest_arm_defs.h | 1 +
+ VEX/priv/guest_arm_toIR.c | 1 +
+ VEX/priv/guest_generic_bb_to_IR.c | 15 +
+ VEX/priv/guest_generic_bb_to_IR.h | 3 +
+ VEX/priv/guest_mips_defs.h | 1 +
+ VEX/priv/guest_mips_toIR.c | 1 +
+ VEX/priv/guest_ppc_defs.h | 4 +-
+ VEX/priv/guest_ppc_helpers.c | 20 +-
+ VEX/priv/guest_ppc_toIR.c | 1288 ++++++++++++++++-----------
+ VEX/priv/guest_s390_defs.h | 1 +
+ VEX/priv/guest_s390_toIR.c | 1 +
+ VEX/priv/guest_x86_defs.h | 1 +
+ VEX/priv/guest_x86_toIR.c | 1 +
+ VEX/priv/host_ppc_defs.c | 22 +-
+ VEX/priv/host_ppc_isel.c | 171 ++--
+ VEX/priv/main_main.c | 8 +
+ coregrind/launcher-darwin.c | 1 +
+ coregrind/launcher-linux.c | 5 +
+ coregrind/m_coredump/coredump-elf.c | 21 +
+ coregrind/m_debuginfo/debuginfo.c | 3 +
+ coregrind/m_debuginfo/priv_storage.h | 5 +-
+ coregrind/m_debuginfo/readelf.c | 80 +-
+ coregrind/m_debuginfo/readmacho.c | 2 +
+ coregrind/m_dispatch/dispatch-ppc64-linux.S | 115 ++-
+ coregrind/m_initimg/initimg-linux.c | 5 +-
+ coregrind/m_libcsetjmp.c | 108 ++-
+ coregrind/m_main.c | 49 +
+ coregrind/m_redir.c | 45 +-
+ coregrind/m_sigframe/sigframe-ppc64-linux.c | 12 +-
+ coregrind/m_signals.c | 17 +
+ coregrind/m_syscall.c | 39 +
+ coregrind/m_syswrap/syscall-ppc64-linux.S | 23 +-
+ coregrind/m_syswrap/syswrap-main.c | 19 +
+ coregrind/m_syswrap/syswrap-ppc64-linux.c | 125 ++-
+ coregrind/m_trampoline.S | 41 +-
+ coregrind/m_translate.c | 73 +-
+ coregrind/m_ume/elf.c | 16 +
+ coregrind/m_ume/macho.c | 2 +
+ coregrind/pub_core_machine.h | 5 +
+ coregrind/vgdb-invoker-ptrace.c | 10 +
+ helgrind/hg_main.c | 1 +
+ include/pub_tool_debuginfo.h | 1 +
+ include/pub_tool_redir.h | 1 +
+ include/valgrind.h | 637 +++++++++++++
+ include/vki/vki-ppc64-linux.h | 6 +-
+ memcheck/mc_machine.c | 10 +-
+ memcheck/tests/atomic_incs.c | 51 ++
+ tests/arch_test.c | 4 +
+ 52 files changed, 2449 insertions(+), 626 deletions(-)
+
+diff --git a/VEX/priv/guest_amd64_defs.h b/VEX/priv/guest_amd64_defs.h
+index 42a6a37..0f565c1 100644
+--- a/VEX/priv/guest_amd64_defs.h
++++ b/VEX/priv/guest_amd64_defs.h
+@@ -61,6 +61,7 @@ DisResult disInstr_AMD64 ( IRSB* irbb,
+ VexArchInfo* archinfo,
+ VexAbiInfo* abiinfo,
+ Bool host_bigendian,
++ Bool guest_bigendian,
+ Bool sigill_diag );
+
+ /* Used by the optimiser to specialise calls to helpers. */
+diff --git a/VEX/priv/guest_amd64_toIR.c b/VEX/priv/guest_amd64_toIR.c
+index 563e957..0bd6221 100644
+--- a/VEX/priv/guest_amd64_toIR.c
++++ b/VEX/priv/guest_amd64_toIR.c
+@@ -31746,6 +31746,7 @@ DisResult disInstr_AMD64 ( IRSB* irsb_IN,
+ VexArchInfo* archinfo,
+ VexAbiInfo* abiinfo,
+ Bool host_bigendian_IN,
++ Bool guest_bigendian_IN,
+ Bool sigill_diag_IN )
+ {
+ Int i, x1, x2;
+diff --git a/VEX/priv/guest_arm64_defs.h b/VEX/priv/guest_arm64_defs.h
+index 342312e..707a411 100644
+--- a/VEX/priv/guest_arm64_defs.h
++++ b/VEX/priv/guest_arm64_defs.h
+@@ -51,6 +51,7 @@ DisResult disInstr_ARM64 ( IRSB* irbb,
+ VexArchInfo* archinfo,
+ VexAbiInfo* abiinfo,
+ Bool host_bigendian,
++ Bool guest_bigendian,
+ Bool sigill_diag );
+
+ /* Used by the optimiser to specialise calls to helpers. */
+diff --git a/VEX/priv/guest_arm64_toIR.c b/VEX/priv/guest_arm64_toIR.c
+index 07d19c9..9faec24 100644
+--- a/VEX/priv/guest_arm64_toIR.c
++++ b/VEX/priv/guest_arm64_toIR.c
+@@ -8496,6 +8496,7 @@ DisResult disInstr_ARM64 ( IRSB* irsb_IN,
+ VexArchInfo* archinfo,
+ VexAbiInfo* abiinfo,
+ Bool host_bigendian_IN,
++ Bool guest_bigendian_IN,
+ Bool sigill_diag_IN )
+ {
+ DisResult dres;
+diff --git a/VEX/priv/guest_arm_defs.h b/VEX/priv/guest_arm_defs.h
+index 776abb7..c3c38f7 100644
+--- a/VEX/priv/guest_arm_defs.h
++++ b/VEX/priv/guest_arm_defs.h
+@@ -53,6 +53,7 @@ DisResult disInstr_ARM ( IRSB* irbb,
+ VexArchInfo* archinfo,
+ VexAbiInfo* abiinfo,
+ Bool host_bigendian,
++ Bool guest_bigendian,
+ Bool sigill_diag );
+
+ /* Used by the optimiser to specialise calls to helpers. */
+diff --git a/VEX/priv/guest_arm_toIR.c b/VEX/priv/guest_arm_toIR.c
+index 7ab367c..2c42bf7 100644
+--- a/VEX/priv/guest_arm_toIR.c
++++ b/VEX/priv/guest_arm_toIR.c
+@@ -21975,6 +21975,7 @@ DisResult disInstr_ARM ( IRSB* irsb_IN,
+ VexArchInfo* archinfo,
+ VexAbiInfo* abiinfo,
+ Bool host_bigendian_IN,
++ Bool guest_bigendian_IN,
+ Bool sigill_diag_IN )
+ {
+ DisResult dres;
+diff --git a/VEX/priv/guest_generic_bb_to_IR.c b/VEX/priv/guest_generic_bb_to_IR.c
+index 8bba8de..225b745 100644
+--- a/VEX/priv/guest_generic_bb_to_IR.c
++++ b/VEX/priv/guest_generic_bb_to_IR.c
+@@ -203,6 +203,7 @@ IRSB* bb_to_IR (
+ Long delta;
+ Int i, n_instrs, first_stmt_idx;
+ Bool resteerOK, debug_print;
++ Bool guest_bigendian;
+ DisResult dres;
+ IRStmt* imark;
+ IRStmt* nop;
+@@ -216,6 +217,19 @@ IRSB* bb_to_IR (
+
+ Bool (*resteerOKfn)(void*,Addr64) = NULL;
+
++ /* WORK IN PROGRESS: Need to know the endianess of the guest code.
++ * The goal is to remove the #defines in the VEX code for the
++ * guest code endianess on the supported archietectures and
++ * instead pass in the guest and host endiannesses via the
++ * VexTranslateArgs structure to LibVEX_Translate(). The function
++ * will then pass the Endianess args to this function. June 27, 2014
++ *
++ * For now, just assume the host and guest have the same Endianess.
++ *
++ * Currently PPC64 uses the guest_bigendian parameter to dis_instr_fn().
++ */
++ guest_bigendian = host_bigendian;
++
+ debug_print = toBool(vex_traceflags & VEX_TRACE_FE);
+
+ /* check sanity .. */
+@@ -363,6 +377,7 @@ IRSB* bb_to_IR (
+ archinfo_guest,
+ abiinfo_both,
+ host_bigendian,
++ guest_bigendian,
+ sigill_diag );
+
+ /* stay sane ... */
+diff --git a/VEX/priv/guest_generic_bb_to_IR.h b/VEX/priv/guest_generic_bb_to_IR.h
+index 30e216d..0763032 100644
+--- a/VEX/priv/guest_generic_bb_to_IR.h
++++ b/VEX/priv/guest_generic_bb_to_IR.h
+@@ -155,6 +155,9 @@ typedef
+ /* Is the host bigendian? */
+ /*IN*/ Bool host_bigendian,
+
++ /* Is the guest bigendian? */
++ /*IN*/ Bool guest_bigendian,
++
+ /* Should diagnostics be printed for illegal instructions? */
+ /*IN*/ Bool sigill_diag
+
+diff --git a/VEX/priv/guest_mips_defs.h b/VEX/priv/guest_mips_defs.h
+index da112c5..27e467a 100644
+--- a/VEX/priv/guest_mips_defs.h
++++ b/VEX/priv/guest_mips_defs.h
+@@ -52,6 +52,7 @@ extern DisResult disInstr_MIPS ( IRSB* irbb,
+ VexArchInfo* archinfo,
+ VexAbiInfo* abiinfo,
+ Bool host_bigendian,
++ Bool guest_bigendian,
+ Bool sigill_diag );
+
+ /* Used by the optimiser to specialise calls to helpers. */
+diff --git a/VEX/priv/guest_mips_toIR.c b/VEX/priv/guest_mips_toIR.c
+index 0e9f160..1589263 100644
+--- a/VEX/priv/guest_mips_toIR.c
++++ b/VEX/priv/guest_mips_toIR.c
+@@ -17203,6 +17203,7 @@ DisResult disInstr_MIPS( IRSB* irsb_IN,
+ VexArchInfo* archinfo,
+ VexAbiInfo* abiinfo,
+ Bool host_bigendian_IN,
++ Bool guest_bigendian_IN,
+ Bool sigill_diag_IN )
+ {
+ DisResult dres;
+diff --git a/VEX/priv/guest_ppc_defs.h b/VEX/priv/guest_ppc_defs.h
+index a27c96f..342b043 100644
+--- a/VEX/priv/guest_ppc_defs.h
++++ b/VEX/priv/guest_ppc_defs.h
+@@ -62,6 +62,7 @@ DisResult disInstr_PPC ( IRSB* irbb,
+ VexArchInfo* archinfo,
+ VexAbiInfo* abiinfo,
+ Bool host_bigendian,
++ Bool guest_bigendian,
+ Bool sigill_diag );
+
+ /* Used by the optimiser to specialise calls to helpers. */
+@@ -161,7 +162,8 @@ extern void ppc32g_dirtyhelper_LVS ( VexGuestPPC32State* gst,
+
+ extern void ppc64g_dirtyhelper_LVS ( VexGuestPPC64State* gst,
+ UInt vD_idx, UInt sh,
+- UInt shift_right );
++ UInt shift_right,
++ Bool guest_is_BE );
+
+ #endif /* ndef __VEX_GUEST_PPC_DEFS_H */
+
+diff --git a/VEX/priv/guest_ppc_helpers.c b/VEX/priv/guest_ppc_helpers.c
+index 2db109b..21c699c 100644
+--- a/VEX/priv/guest_ppc_helpers.c
++++ b/VEX/priv/guest_ppc_helpers.c
+@@ -153,10 +153,12 @@ void ppc32g_dirtyhelper_LVS ( VexGuestPPC32State* gst,
+ /* CALLED FROM GENERATED CODE */
+ /* DIRTY HELPER (reads guest state, writes guest mem) */
+ void ppc64g_dirtyhelper_LVS ( VexGuestPPC64State* gst,
+- UInt vD_off, UInt sh, UInt shift_right )
++ UInt vD_off, UInt sh, UInt shift_right,
++ Bool guest_is_BE )
+ {
+ UChar ref[32];
+ ULong i;
++ Int k;
+ /* ref[] used to be a static const array, but this doesn't work on
+ ppc64 because VEX doesn't load the TOC pointer for the call here,
+ and so we wind up picking up some totally random other data.
+@@ -179,10 +181,18 @@ void ppc64g_dirtyhelper_LVS ( VexGuestPPC64State* gst,
+ pU128_src = (U128*)&ref[sh];
+ pU128_dst = (U128*)( ((UChar*)gst) + vD_off );
+
+- (*pU128_dst)[0] = (*pU128_src)[0];
+- (*pU128_dst)[1] = (*pU128_src)[1];
+- (*pU128_dst)[2] = (*pU128_src)[2];
+- (*pU128_dst)[3] = (*pU128_src)[3];
++ if (!guest_is_BE) {
++ unsigned char *srcp, *dstp;
++ srcp = (unsigned char *)pU128_src;
++ dstp = (unsigned char *)pU128_dst;
++ for (k = 15; k >= 0; k--, srcp++)
++ dstp[k] = *srcp;
++ } else {
++ (*pU128_dst)[0] = (*pU128_src)[0];
++ (*pU128_dst)[1] = (*pU128_src)[1];
++ (*pU128_dst)[2] = (*pU128_src)[2];
++ (*pU128_dst)[3] = (*pU128_src)[3];
++ }
+ }
+
+
+diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
+index 81c2ccf..080773a 100644
+--- a/VEX/priv/guest_ppc_toIR.c
++++ b/VEX/priv/guest_ppc_toIR.c
+@@ -97,7 +97,8 @@
+
+ 7C210B78 (or 1,1,1) %R3 = client_request ( %R4 )
+ 7C421378 (or 2,2,2) %R3 = guest_NRADDR
+- 7C631B78 (or 3,3,3) branch-and-link-to-noredir %R11
++ 7C631B78 (or 3,3,3) branch-and-link-to-noredir %R11 Big endian
++ 7C631B78 (or 3,3,3) branch-and-link-to-noredir %R12 Little endian
+ 7C842378 (or 4,4,4) %R3 = guest_NRADDR_GPR2
+ 7CA52B78 (or 5,5,5) IR injection
+
+@@ -107,7 +108,55 @@
+ fragments designed for Valgrind to catch.
+ */
+
+-
++/* Little Endian notes */
++/*
++ * Vector operations in little Endian mode behave in non-obvious ways at times.
++ * Below is an attempt at explaining this.
++ *
++ * LE/BE vector example
++ * With a vector of unsigned ints declared as follows:
++ * vector unsigned int vec_inA =
++ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 };
++ * The '0x11111111' word is word zero in both LE and BE format. But the
++ * loaded vector register will have word zero on the far left in BE mode and
++ * on the far right in LE mode. The lvx and stvx instructions work naturally
++ * for whatever endianness is in effect. For example, in LE mode, the stvx
++ * stores word zero (far right word) of the vector at the lowest memory
++ * address of the EA; in BE mode, stvx still stores word zero at the lowest
++ * memory address, but with word zero interpreted as the one at the far left
++ * of the register.
++ *
++ * The lxvd2x and stxvd2x instructions are not so well suited for LE mode.
++ * When the compiler generates an lxvd2x instruction to load the
++ * above-declared vector of unsigned integers, it loads the vector as two
++ * double words, but they are in BE word-wise format. To put the vector in
++ * the right order for LE, the compiler also generates an xxswapd after the
++ * load, which puts it in proper LE format. Similarly, the stxvd2x
++ * instruction has a BE bias, storing the vector in BE word-wise format. But
++ * the compiler also generates an xxswapd prior to the store, thus ensuring
++ * the vector is stored in memory in the correct LE order.
++ *
++ * Vector-flavored Iops, such Iop_V128Hito64, reference the hi and lo parts
++ * of a double words and words within a vector. Because of the reverse order
++ * of numbering for LE as described above, the high part refers to word 1 in
++ * LE format. When input data is saved to a guest state vector register
++ * (e.g., via Iop_64HLtoV128), it is first saved to memory and then the
++ * register is loaded via PPCInstr_AvLdSt, which does an lvx instruction.
++ * The saving of the data to memory must be done in proper LE order. For the
++ * inverse operation of extracting data from a vector register (e.g.,
++ * Iop_V128Hito64), the register is first saved (by PPCInstr_AvLdSt resulting
++ * in stvx), and then integer registers are loaded from the memory location
++ * from where the vector register was saved. Again, this must be done in
++ * proper LE order. So for these various vector Iops, we have LE-specific
++ * code in host_ppc_isel.c
++ *
++ * Another unique behavior of vectors in LE mode is with the vector scalar
++ * (VSX) operations that operate on "double word 0" of the source register,
++ * storing the result in "double word 0" of the output vector register. For
++ * these operations, "double word 0" is interpreted as "high half of the
++ * register" (i.e, the part on the left side).
++ *
++ */
+ /* Translates PPC32/64 code to IR. */
+
+ /* References
+@@ -143,8 +192,6 @@
+ #include "guest_generic_bb_to_IR.h"
+ #include "guest_ppc_defs.h"
+
+-
+-#define IENDIANESS Iend_BE
+ /*------------------------------------------------------------*/
+ /*--- Globals ---*/
+ /*------------------------------------------------------------*/
+@@ -506,13 +553,20 @@ static ULong extend_s_32to64 ( UInt x )
+
+ /* Do a proper-endian load of a 32-bit word, regardless of the endianness
+ of the underlying host. */
+-static UInt getUIntPPCendianly ( UChar* p )
++static UInt getUIntPPCendianly ( UChar* p, Bool guest_is_BE )
+ {
+ UInt w = 0;
+- w = (w << 8) | p[0];
+- w = (w << 8) | p[1];
+- w = (w << 8) | p[2];
+- w = (w << 8) | p[3];
++ if (guest_is_BE) {
++ w = (w << 8) | p[0];
++ w = (w << 8) | p[1];
++ w = (w << 8) | p[2];
++ w = (w << 8) | p[3];
++ } else {
++ w = (w << 8) | p[3];
++ w = (w << 8) | p[2];
++ w = (w << 8) | p[1];
++ w = (w << 8) | p[0];
++ }
+ return w;
+ }
+
+@@ -527,11 +581,13 @@ static void assign ( IRTemp dst, IRExpr* e )
+ }
+
+ /* This generates a normal (non store-conditional) store. */
+-static void store ( IRExpr* addr, IRExpr* data )
++static void store ( IRExpr* addr, IRExpr* data, Bool guest_is_BE )
+ {
+ IRType tyA = typeOfIRExpr(irsb->tyenv, addr);
++ IREndness endian = guest_is_BE ? Iend_BE: Iend_LE;
++
+ vassert(tyA == Ity_I32 || tyA == Ity_I64);
+- stmt( IRStmt_Store(IENDIANESS, addr, data) );
++ stmt( IRStmt_Store(endian, addr, data) );
+ }
+
+ static IRExpr* unop ( IROp op, IRExpr* a )
+@@ -587,9 +643,19 @@ static IRExpr* mkV128 ( UShort i )
+ }
+
+ /* This generates a normal (non load-linked) load. */
+-static IRExpr* load ( IRType ty, IRExpr* addr )
++static IRExpr* load ( IRType ty, IRExpr* addr, Bool guest_is_BE )
++{
++ IREndness endian = guest_is_BE ? Iend_BE: Iend_LE;
++
++ return IRExpr_Load(endian, ty, addr);
++}
++
++static IRStmt* stmt_load ( Bool guest_is_BE, IRTemp result,
++ IRExpr* addr, IRExpr* storedata )
+ {
+- return IRExpr_Load(IENDIANESS, ty, addr);
++ IREndness endian = guest_is_BE ? Iend_BE: Iend_LE;
++
++ return IRStmt_LLSC(endian, result, addr, storedata);
+ }
+
+ static IRExpr* mkOR1 ( IRExpr* arg1, IRExpr* arg2 )
+@@ -1040,7 +1106,6 @@ static Int integerGuestRegOffset ( UInt archreg )
+ // jrs: probably not necessary; only matters if we reference sub-parts
+ // of the ppc registers, but that isn't the case
+ // later: this might affect Altivec though?
+- vassert(host_is_bigendian);
+
+ switch (archreg) {
+ case 0: return offsetofPPCGuestState(guest_GPR0);
+@@ -1098,100 +1163,138 @@ static void putIReg ( UInt archreg, IRExpr* e )
+
+
+ /* Floating point egisters are mapped to VSX registers[0..31]. */
+-static Int floatGuestRegOffset ( UInt archreg )
++static Int floatGuestRegOffset ( UInt archreg, Bool guest_is_BE )
+ {
+ vassert(archreg < 32);
+
+- switch (archreg) {
+- case 0: return offsetofPPCGuestState(guest_VSR0);
+- case 1: return offsetofPPCGuestState(guest_VSR1);
+- case 2: return offsetofPPCGuestState(guest_VSR2);
+- case 3: return offsetofPPCGuestState(guest_VSR3);
+- case 4: return offsetofPPCGuestState(guest_VSR4);
+- case 5: return offsetofPPCGuestState(guest_VSR5);
+- case 6: return offsetofPPCGuestState(guest_VSR6);
+- case 7: return offsetofPPCGuestState(guest_VSR7);
+- case 8: return offsetofPPCGuestState(guest_VSR8);
+- case 9: return offsetofPPCGuestState(guest_VSR9);
+- case 10: return offsetofPPCGuestState(guest_VSR10);
+- case 11: return offsetofPPCGuestState(guest_VSR11);
+- case 12: return offsetofPPCGuestState(guest_VSR12);
+- case 13: return offsetofPPCGuestState(guest_VSR13);
+- case 14: return offsetofPPCGuestState(guest_VSR14);
+- case 15: return offsetofPPCGuestState(guest_VSR15);
+- case 16: return offsetofPPCGuestState(guest_VSR16);
+- case 17: return offsetofPPCGuestState(guest_VSR17);
+- case 18: return offsetofPPCGuestState(guest_VSR18);
+- case 19: return offsetofPPCGuestState(guest_VSR19);
+- case 20: return offsetofPPCGuestState(guest_VSR20);
+- case 21: return offsetofPPCGuestState(guest_VSR21);
+- case 22: return offsetofPPCGuestState(guest_VSR22);
+- case 23: return offsetofPPCGuestState(guest_VSR23);
+- case 24: return offsetofPPCGuestState(guest_VSR24);
+- case 25: return offsetofPPCGuestState(guest_VSR25);
+- case 26: return offsetofPPCGuestState(guest_VSR26);
+- case 27: return offsetofPPCGuestState(guest_VSR27);
+- case 28: return offsetofPPCGuestState(guest_VSR28);
+- case 29: return offsetofPPCGuestState(guest_VSR29);
+- case 30: return offsetofPPCGuestState(guest_VSR30);
+- case 31: return offsetofPPCGuestState(guest_VSR31);
+- default: break;
++ if (!guest_is_BE) {
++ switch (archreg) {
++ case 0: return offsetofPPCGuestState(guest_VSR0 + 8);
++ case 1: return offsetofPPCGuestState(guest_VSR1 + 8);
++ case 2: return offsetofPPCGuestState(guest_VSR2 + 8);
++ case 3: return offsetofPPCGuestState(guest_VSR3 + 8);
++ case 4: return offsetofPPCGuestState(guest_VSR4 + 8);
++ case 5: return offsetofPPCGuestState(guest_VSR5 + 8);
++ case 6: return offsetofPPCGuestState(guest_VSR6 + 8);
++ case 7: return offsetofPPCGuestState(guest_VSR7 + 8);
++ case 8: return offsetofPPCGuestState(guest_VSR8 + 8);
++ case 9: return offsetofPPCGuestState(guest_VSR9 + 8);
++ case 10: return offsetofPPCGuestState(guest_VSR10 + 8);
++ case 11: return offsetofPPCGuestState(guest_VSR11 + 8);
++ case 12: return offsetofPPCGuestState(guest_VSR12 + 8);
++ case 13: return offsetofPPCGuestState(guest_VSR13 + 8);
++ case 14: return offsetofPPCGuestState(guest_VSR14 + 8);
++ case 15: return offsetofPPCGuestState(guest_VSR15 + 8);
++ case 16: return offsetofPPCGuestState(guest_VSR16 + 8);
++ case 17: return offsetofPPCGuestState(guest_VSR17 + 8);
++ case 18: return offsetofPPCGuestState(guest_VSR18 + 8);
++ case 19: return offsetofPPCGuestState(guest_VSR19 + 8);
++ case 20: return offsetofPPCGuestState(guest_VSR20 + 8);
++ case 21: return offsetofPPCGuestState(guest_VSR21 + 8);
++ case 22: return offsetofPPCGuestState(guest_VSR22 + 8);
++ case 23: return offsetofPPCGuestState(guest_VSR23 + 8);
++ case 24: return offsetofPPCGuestState(guest_VSR24 + 8);
++ case 25: return offsetofPPCGuestState(guest_VSR25 + 8);
++ case 26: return offsetofPPCGuestState(guest_VSR26 + 8);
++ case 27: return offsetofPPCGuestState(guest_VSR27 + 8);
++ case 28: return offsetofPPCGuestState(guest_VSR28 + 8);
++ case 29: return offsetofPPCGuestState(guest_VSR29 + 8);
++ case 30: return offsetofPPCGuestState(guest_VSR30 + 8);
++ case 31: return offsetofPPCGuestState(guest_VSR31 + 8);
++ default: break;
++ }
++ } else {
++ switch (archreg) {
++ case 0: return offsetofPPCGuestState(guest_VSR0);
++ case 1: return offsetofPPCGuestState(guest_VSR1);
++ case 2: return offsetofPPCGuestState(guest_VSR2);
++ case 3: return offsetofPPCGuestState(guest_VSR3);
++ case 4: return offsetofPPCGuestState(guest_VSR4);
++ case 5: return offsetofPPCGuestState(guest_VSR5);
++ case 6: return offsetofPPCGuestState(guest_VSR6);
++ case 7: return offsetofPPCGuestState(guest_VSR7);
++ case 8: return offsetofPPCGuestState(guest_VSR8);
++ case 9: return offsetofPPCGuestState(guest_VSR9);
++ case 10: return offsetofPPCGuestState(guest_VSR10);
++ case 11: return offsetofPPCGuestState(guest_VSR11);
++ case 12: return offsetofPPCGuestState(guest_VSR12);
++ case 13: return offsetofPPCGuestState(guest_VSR13);
++ case 14: return offsetofPPCGuestState(guest_VSR14);
++ case 15: return offsetofPPCGuestState(guest_VSR15);
++ case 16: return offsetofPPCGuestState(guest_VSR16);
++ case 17: return offsetofPPCGuestState(guest_VSR17);
++ case 18: return offsetofPPCGuestState(guest_VSR18);
++ case 19: return offsetofPPCGuestState(guest_VSR19);
++ case 20: return offsetofPPCGuestState(guest_VSR20);
++ case 21: return offsetofPPCGuestState(guest_VSR21);
++ case 22: return offsetofPPCGuestState(guest_VSR22);
++ case 23: return offsetofPPCGuestState(guest_VSR23);
++ case 24: return offsetofPPCGuestState(guest_VSR24);
++ case 25: return offsetofPPCGuestState(guest_VSR25);
++ case 26: return offsetofPPCGuestState(guest_VSR26);
++ case 27: return offsetofPPCGuestState(guest_VSR27);
++ case 28: return offsetofPPCGuestState(guest_VSR28);
++ case 29: return offsetofPPCGuestState(guest_VSR29);
++ case 30: return offsetofPPCGuestState(guest_VSR30);
++ case 31: return offsetofPPCGuestState(guest_VSR31);
++ default: break;
++ }
+ }
+ vpanic("floatGuestRegOffset(ppc)"); /*notreached*/
+ }
+
+-static IRExpr* getFReg ( UInt archreg )
++static IRExpr* getFReg ( UInt archreg, Bool guest_is_BE )
+ {
+ vassert(archreg < 32);
+- return IRExpr_Get( floatGuestRegOffset(archreg), Ity_F64 );
++ return IRExpr_Get( floatGuestRegOffset(archreg, guest_is_BE), Ity_F64 );
+ }
+
+ /* Ditto, but write to a reg instead. */
+-static void putFReg ( UInt archreg, IRExpr* e )
++static void putFReg ( UInt archreg, IRExpr* e, Bool guest_is_BE )
+ {
+ vassert(archreg < 32);
+ vassert(typeOfIRExpr(irsb->tyenv, e) == Ity_F64);
+- stmt( IRStmt_Put(floatGuestRegOffset(archreg), e) );
++ stmt( IRStmt_Put(floatGuestRegOffset(archreg, guest_is_BE), e) );
+ }
+
+ /* get Decimal float value. Note, they share floating point register file. */
+-static IRExpr* getDReg(UInt archreg) {
++static IRExpr* getDReg(UInt archreg, Bool guest_is_BE) {
+ IRExpr *e;
+ vassert( archreg < 32 );
+- e = IRExpr_Get( floatGuestRegOffset( archreg ), Ity_D64 );
++ e = IRExpr_Get( floatGuestRegOffset( archreg, guest_is_BE ), Ity_D64 );
+ return e;
+ }
+-static IRExpr* getDReg32(UInt archreg) {
++static IRExpr* getDReg32(UInt archreg, Bool guest_is_BE) {
+ IRExpr *e;
+ vassert( archreg < 32 );
+- e = IRExpr_Get( floatGuestRegOffset( archreg ), Ity_D32 );
++ e = IRExpr_Get( floatGuestRegOffset( archreg, guest_is_BE ), Ity_D32 );
+ return e;
+ }
+
+ /* Read a floating point register pair and combine their contents into a
+ 128-bit value */
+-static IRExpr *getDReg_pair(UInt archreg) {
+- IRExpr *high = getDReg( archreg );
+- IRExpr *low = getDReg( archreg + 1 );
++static IRExpr *getDReg_pair(UInt archreg, Bool guest_is_BE ) {
++ IRExpr *high = getDReg( archreg, guest_is_BE );
++ IRExpr *low = getDReg( archreg + 1, guest_is_BE );
+
+ return binop( Iop_D64HLtoD128, high, low );
+ }
+
+ /* Ditto, but write to a reg instead. */
+-static void putDReg32(UInt archreg, IRExpr* e) {
++static void putDReg32(UInt archreg, IRExpr* e, Bool guest_is_BE) {
+ vassert( archreg < 32 );
+ vassert( typeOfIRExpr(irsb->tyenv, e) == Ity_D32 );
+- stmt( IRStmt_Put( floatGuestRegOffset( archreg ), e ) );
++ stmt( IRStmt_Put( floatGuestRegOffset( archreg, guest_is_BE ), e ) );
+ }
+
+-static void putDReg(UInt archreg, IRExpr* e) {
++static void putDReg(UInt archreg, IRExpr* e, Bool guest_is_BE) {
+ vassert( archreg < 32 );
+ vassert( typeOfIRExpr(irsb->tyenv, e) == Ity_D64 );
+- stmt( IRStmt_Put( floatGuestRegOffset( archreg ), e ) );
++ stmt( IRStmt_Put( floatGuestRegOffset( archreg, guest_is_BE), e ) );
+ }
+
+ /* Write a 128-bit floating point value into a register pair. */
+-static void putDReg_pair(UInt archreg, IRExpr *e) {
++static void putDReg_pair(UInt archreg, IRExpr *e, Bool guest_is_BE) {
+ IRTemp low = newTemp( Ity_D64 );
+ IRTemp high = newTemp( Ity_D64 );
+
+@@ -1201,8 +1304,10 @@ static void putDReg_pair(UInt archreg, IRExpr *e) {
+ assign( low, unop( Iop_D128LOtoD64, e ) );
+ assign( high, unop( Iop_D128HItoD64, e ) );
+
+- stmt( IRStmt_Put( floatGuestRegOffset( archreg ), mkexpr( high ) ) );
+- stmt( IRStmt_Put( floatGuestRegOffset( archreg + 1 ), mkexpr( low ) ) );
++ stmt( IRStmt_Put( floatGuestRegOffset( archreg, guest_is_BE ),
++ mkexpr( high ) ) );
++ stmt( IRStmt_Put( floatGuestRegOffset( archreg + 1, guest_is_BE ),
++ mkexpr( low ) ) );
+ }
+
+ static Int vsxGuestRegOffset ( UInt archreg )
+@@ -3963,7 +4068,7 @@ static Bool dis_int_cmp ( UInt theInstr )
+ /*
+ Integer Logical Instructions
+ */
+-static Bool dis_int_logic ( UInt theInstr )
++static Bool dis_int_logic ( UInt theInstr, Bool guest_is_BE )
+ {
+ /* D-Form, X-Form */
+ UChar opc1 = ifieldOPC(theInstr);
+@@ -4194,7 +4299,7 @@ static Bool dis_int_logic ( UInt theInstr )
+ IRTemp frB = newTemp(Ity_F64);
+ DIP("mftgpr r%u,fr%u\n", rS_addr, rB_addr);
+
+- assign( frB, getFReg(rB_addr)); // always F64
++ assign( frB, getFReg(rB_addr, guest_is_BE )); // always F64
+ if (mode64)
+ assign( rA, unop( Iop_ReinterpF64asI64, mkexpr(frB)) );
+ else
+@@ -4213,7 +4318,7 @@ static Bool dis_int_logic ( UInt theInstr )
+ else
+ assign( frA, unop( Iop_ReinterpI64asF64, unop( Iop_32Uto64, mkexpr(rB))) );
+
+- putFReg( rS_addr, mkexpr(frA));
++ putFReg( rS_addr, mkexpr(frA), guest_is_BE );
+ return True;
+ }
+ case 0x1FA: // popcntd (population count doubleword
+@@ -4720,7 +4825,7 @@ static Bool dis_int_rot ( UInt theInstr )
+ /*
+ Integer Load Instructions
+ */
+-static Bool dis_int_load ( UInt theInstr )
++static Bool dis_int_load ( UInt theInstr, Bool guest_is_BE )
+ {
+ /* D-Form, X-Form, DS-Form */
+ UChar opc1 = ifieldOPC(theInstr);
+@@ -4759,7 +4864,7 @@ static Bool dis_int_load ( UInt theInstr )
+ switch (opc1) {
+ case 0x22: // lbz (Load B & Zero, PPC32 p433)
+ DIP("lbz r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr);
+- val = load(Ity_I8, mkexpr(EA));
++ val = load(Ity_I8, mkexpr(EA), guest_is_BE );
+ putIReg( rD_addr, mkWidenFrom8(ty, val, False) );
+ break;
+
+@@ -4769,14 +4874,14 @@ static Bool dis_int_load ( UInt theInstr )
+ return False;
+ }
+ DIP("lbzu r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr);
+- val = load(Ity_I8, mkexpr(EA));
++ val = load(Ity_I8, mkexpr(EA), guest_is_BE );
+ putIReg( rD_addr, mkWidenFrom8(ty, val, False) );
+ putIReg( rA_addr, mkexpr(EA) );
+ break;
+
+ case 0x2A: // lha (Load HW Alg, PPC32 p445)
+ DIP("lha r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr);
+- val = load(Ity_I16, mkexpr(EA));
++ val = load(Ity_I16, mkexpr(EA), guest_is_BE );
+ putIReg( rD_addr, mkWidenFrom16(ty, val, True) );
+ break;
+
+@@ -4786,14 +4891,14 @@ static Bool dis_int_load ( UInt theInstr )
+ return False;
+ }
+ DIP("lhau r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr);
+- val = load(Ity_I16, mkexpr(EA));
++ val = load(Ity_I16, mkexpr(EA), guest_is_BE );
+ putIReg( rD_addr, mkWidenFrom16(ty, val, True) );
+ putIReg( rA_addr, mkexpr(EA) );
+ break;
+
+ case 0x28: // lhz (Load HW & Zero, PPC32 p450)
+ DIP("lhz r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr);
+- val = load(Ity_I16, mkexpr(EA));
++ val = load(Ity_I16, mkexpr(EA), guest_is_BE );
+ putIReg( rD_addr, mkWidenFrom16(ty, val, False) );
+ break;
+
+@@ -4803,14 +4908,14 @@ static Bool dis_int_load ( UInt theInstr )
+ return False;
+ }
+ DIP("lhzu r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr);
+- val = load(Ity_I16, mkexpr(EA));
++ val = load(Ity_I16, mkexpr(EA), guest_is_BE );
+ putIReg( rD_addr, mkWidenFrom16(ty, val, False) );
+ putIReg( rA_addr, mkexpr(EA) );
+ break;
+
+ case 0x20: // lwz (Load W & Zero, PPC32 p460)
+ DIP("lwz r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr);
+- val = load(Ity_I32, mkexpr(EA));
++ val = load(Ity_I32, mkexpr(EA), guest_is_BE );
+ putIReg( rD_addr, mkWidenFrom32(ty, val, False) );
+ break;
+
+@@ -4820,7 +4925,7 @@ static Bool dis_int_load ( UInt theInstr )
+ return False;
+ }
+ DIP("lwzu r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr);
+- val = load(Ity_I32, mkexpr(EA));
++ val = load(Ity_I32, mkexpr(EA), guest_is_BE );
+ putIReg( rD_addr, mkWidenFrom32(ty, val, False) );
+ putIReg( rA_addr, mkexpr(EA) );
+ break;
+@@ -4839,14 +4944,14 @@ static Bool dis_int_load ( UInt theInstr )
+ vex_printf("dis_int_load(ppc)(lwzux,rA_addr|rD_addr)\n");
+ return False;
+ }
+- val = load(Ity_I8, mkexpr(EA));
++ val = load(Ity_I8, mkexpr(EA), guest_is_BE );
+ putIReg( rD_addr, mkWidenFrom8(ty, val, False) );
+ putIReg( rA_addr, mkexpr(EA) );
+ break;
+
+ case 0x057: // lbzx (Load B & Zero, Indexed, PPC32 p436)
+ DIP("lbzx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
+- val = load(Ity_I8, mkexpr(EA));
++ val = load(Ity_I8, mkexpr(EA), guest_is_BE );
+ putIReg( rD_addr, mkWidenFrom8(ty, val, False) );
+ break;
+
+@@ -4856,14 +4961,14 @@ static Bool dis_int_load ( UInt theInstr )
+ return False;
+ }
+ DIP("lhaux r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
+- val = load(Ity_I16, mkexpr(EA));
++ val = load(Ity_I16, mkexpr(EA), guest_is_BE );
+ putIReg( rD_addr, mkWidenFrom16(ty, val, True) );
+ putIReg( rA_addr, mkexpr(EA) );
+ break;
+
+ case 0x157: // lhax (Load HW Alg, Indexed, PPC32 p448)
+ DIP("lhax r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
+- val = load(Ity_I16, mkexpr(EA));
++ val = load(Ity_I16, mkexpr(EA), guest_is_BE );
+ putIReg( rD_addr, mkWidenFrom16(ty, val, True) );
+ break;
+
+@@ -4873,14 +4978,14 @@ static Bool dis_int_load ( UInt theInstr )
+ return False;
+ }
+ DIP("lhzux r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
+- val = load(Ity_I16, mkexpr(EA));
++ val = load(Ity_I16, mkexpr(EA), guest_is_BE );
+ putIReg( rD_addr, mkWidenFrom16(ty, val, False) );
+ putIReg( rA_addr, mkexpr(EA) );
+ break;
+
+ case 0x117: // lhzx (Load HW & Zero, Indexed, PPC32 p453)
+ DIP("lhzx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
+- val = load(Ity_I16, mkexpr(EA));
++ val = load(Ity_I16, mkexpr(EA), guest_is_BE );
+ putIReg( rD_addr, mkWidenFrom16(ty, val, False) );
+ break;
+
+@@ -4890,14 +4995,14 @@ static Bool dis_int_load ( UInt theInstr )
+ return False;
+ }
+ DIP("lwzux r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
+- val = load(Ity_I32, mkexpr(EA));
++ val = load(Ity_I32, mkexpr(EA), guest_is_BE );
+ putIReg( rD_addr, mkWidenFrom32(ty, val, False) );
+ putIReg( rA_addr, mkexpr(EA) );
+ break;
+
+ case 0x017: // lwzx (Load W & Zero, Indexed, PPC32 p463)
+ DIP("lwzx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
+- val = load(Ity_I32, mkexpr(EA));
++ val = load(Ity_I32, mkexpr(EA), guest_is_BE );
+ putIReg( rD_addr, mkWidenFrom32(ty, val, False) );
+ break;
+
+@@ -4909,13 +5014,13 @@ static Bool dis_int_load ( UInt theInstr )
+ return False;
+ }
+ DIP("ldux r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
+- putIReg( rD_addr, load(Ity_I64, mkexpr(EA)) );
++ putIReg( rD_addr, load(Ity_I64, mkexpr(EA), guest_is_BE ) );
+ putIReg( rA_addr, mkexpr(EA) );
+ break;
+
+ case 0x015: // ldx (Load DWord, Indexed, PPC64 p476)
+ DIP("ldx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
+- putIReg( rD_addr, load(Ity_I64, mkexpr(EA)) );
++ putIReg( rD_addr, load(Ity_I64, mkexpr(EA), guest_is_BE ) );
+ break;
+
+ case 0x175: // lwaux (Load W Alg, Update Indexed, PPC64 p501)
+@@ -4925,14 +5030,14 @@ static Bool dis_int_load ( UInt theInstr )
+ }
+ DIP("lwaux r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
+ putIReg( rD_addr,
+- unop(Iop_32Sto64, load(Ity_I32, mkexpr(EA))) );
++ unop(Iop_32Sto64, load(Ity_I32, mkexpr(EA), guest_is_BE )) );
+ putIReg( rA_addr, mkexpr(EA) );
+ break;
+
+ case 0x155: // lwax (Load W Alg, Indexed, PPC64 p502)
+ DIP("lwax r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
+ putIReg( rD_addr,
+- unop(Iop_32Sto64, load(Ity_I32, mkexpr(EA))) );
++ unop(Iop_32Sto64, load(Ity_I32, mkexpr(EA), guest_is_BE )) );
+ break;
+
+ default:
+@@ -4947,7 +5052,7 @@ static Bool dis_int_load ( UInt theInstr )
+ switch ((b1<<1) | b0) {
+ case 0x0: // ld (Load DWord, PPC64 p472)
+ DIP("ld r%u,%d(r%u)\n", rD_addr, simm16, rA_addr);
+- putIReg( rD_addr, load(Ity_I64, mkexpr(EA)) );
++ putIReg( rD_addr, load(Ity_I64, mkexpr(EA), guest_is_BE ) );
+ break;
+
+ case 0x1: // ldu (Load DWord, Update, PPC64 p474)
+@@ -4956,14 +5061,14 @@ static Bool dis_int_load ( UInt theInstr )
+ return False;
+ }
+ DIP("ldu r%u,%d(r%u)\n", rD_addr, simm16, rA_addr);
+- putIReg( rD_addr, load(Ity_I64, mkexpr(EA)) );
++ putIReg( rD_addr, load(Ity_I64, mkexpr(EA), guest_is_BE ) );
+ putIReg( rA_addr, mkexpr(EA) );
+ break;
+
+ case 0x2: // lwa (Load Word Alg, PPC64 p499)
+ DIP("lwa r%u,%d(r%u)\n", rD_addr, simm16, rA_addr);
+ putIReg( rD_addr,
+- unop(Iop_32Sto64, load(Ity_I32, mkexpr(EA))) );
++ unop(Iop_32Sto64, load(Ity_I32, mkexpr(EA), guest_is_BE )) );
+ break;
+
+ default:
+@@ -4982,17 +5087,19 @@ static Bool dis_int_load ( UInt theInstr )
+ */
+ // trap if EA misaligned on 16 byte address
+ if (mode64) {
+- assign(high, load(ty, mkexpr( EA ) ) );
++ assign(high, load(ty, mkexpr( EA ), guest_is_BE ) );
+ assign(low, load(ty, binop( Iop_Add64,
+ mkexpr( EA ),
+- mkU64( 8 ) ) ) );
++ mkU64( 8 ) ), guest_is_BE ));
+ } else {
+ assign(high, load(ty, binop( Iop_Add32,
+ mkexpr( EA ),
+- mkU32( 4 ) ) ) );
++ mkU32( 4 ) ),
++ guest_is_BE ) );
+ assign(low, load(ty, binop( Iop_Add32,
+ mkexpr( EA ),
+- mkU32( 12 ) ) ) );
++ mkU32( 12 ) ),
++ guest_is_BE ) );
+ }
+ gen_SIGBUS_if_misaligned( EA, 16 );
+ putIReg( rD_addr, mkexpr( high) );
+@@ -5011,7 +5118,7 @@ static Bool dis_int_load ( UInt theInstr )
+ /*
+ Integer Store Instructions
+ */
+-static Bool dis_int_store ( UInt theInstr, VexAbiInfo* vbi )
++static Bool dis_int_store ( UInt theInstr, VexAbiInfo* vbi, Bool guest_is_BE )
+ {
+ /* D-Form, X-Form, DS-Form */
+ UChar opc1 = ifieldOPC(theInstr);
+@@ -5047,7 +5154,7 @@ static Bool dis_int_store ( UInt theInstr, VexAbiInfo* vbi )
+ switch (opc1) {
+ case 0x26: // stb (Store B, PPC32 p509)
+ DIP("stb r%u,%d(r%u)\n", rS_addr, simm16, rA_addr);
+- store( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)) );
++ store( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)), guest_is_BE );
+ break;
+
+ case 0x27: // stbu (Store B, Update, PPC32 p510)
+@@ -5057,12 +5164,12 @@ static Bool dis_int_store ( UInt theInstr, VexAbiInfo* vbi )
+ }
+ DIP("stbu r%u,%d(r%u)\n", rS_addr, simm16, rA_addr);
+ putIReg( rA_addr, mkexpr(EA) );
+- store( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)) );
++ store( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)), guest_is_BE );
+ break;
+
+ case 0x2C: // sth (Store HW, PPC32 p522)
+ DIP("sth r%u,%d(r%u)\n", rS_addr, simm16, rA_addr);
+- store( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)) );
++ store( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)), guest_is_BE );
+ break;
+
+ case 0x2D: // sthu (Store HW, Update, PPC32 p524)
+@@ -5072,12 +5179,12 @@ static Bool dis_int_store ( UInt theInstr, VexAbiInfo* vbi )
+ }
+ DIP("sthu r%u,%d(r%u)\n", rS_addr, simm16, rA_addr);
+ putIReg( rA_addr, mkexpr(EA) );
+- store( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)) );
++ store( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)), guest_is_BE );
+ break;
+
+ case 0x24: // stw (Store W, PPC32 p530)
+ DIP("stw r%u,%d(r%u)\n", rS_addr, simm16, rA_addr);
+- store( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)) );
++ store( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)), guest_is_BE );
+ break;
+
+ case 0x25: // stwu (Store W, Update, PPC32 p534)
+@@ -5087,7 +5194,7 @@ static Bool dis_int_store ( UInt theInstr, VexAbiInfo* vbi )
+ }
+ DIP("stwu r%u,%d(r%u)\n", rS_addr, simm16, rA_addr);
+ putIReg( rA_addr, mkexpr(EA) );
+- store( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)) );
++ store( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)), guest_is_BE );
+ break;
+
+ /* X Form : all these use EA_indexed */
+@@ -5105,12 +5212,12 @@ static Bool dis_int_store ( UInt theInstr, VexAbiInfo* vbi )
+ }
+ DIP("stbux r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);
+ putIReg( rA_addr, mkexpr(EA) );
+- store( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)) );
++ store( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)), guest_is_BE );
+ break;
+
+ case 0x0D7: // stbx (Store B Indexed, PPC32 p512)
+ DIP("stbx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);
+- store( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)) );
++ store( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)), guest_is_BE );
+ break;
+
+ case 0x1B7: // sthux (Store HW, Update Indexed, PPC32 p525)
+@@ -5120,12 +5227,12 @@ static Bool dis_int_store ( UInt theInstr, VexAbiInfo* vbi )
+ }
+ DIP("sthux r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);
+ putIReg( rA_addr, mkexpr(EA) );
+- store( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)) );
++ store( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)), guest_is_BE );
+ break;
+
+ case 0x197: // sthx (Store HW Indexed, PPC32 p526)
+ DIP("sthx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);
+- store( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)) );
++ store( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)), guest_is_BE );
+ break;
+
+ case 0x0B7: // stwux (Store W, Update Indexed, PPC32 p535)
+@@ -5135,12 +5242,12 @@ static Bool dis_int_store ( UInt theInstr, VexAbiInfo* vbi )
+ }
+ DIP("stwux r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);
+ putIReg( rA_addr, mkexpr(EA) );
+- store( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)) );
++ store( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)), guest_is_BE );
+ break;
+
+ case 0x097: // stwx (Store W Indexed, PPC32 p536)
+ DIP("stwx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);
+- store( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)) );
++ store( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)), guest_is_BE );
+ break;
+
+
+@@ -5152,12 +5259,12 @@ static Bool dis_int_store ( UInt theInstr, VexAbiInfo* vbi )
+ }
+ DIP("stdux r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);
+ putIReg( rA_addr, mkexpr(EA) );
+- store( mkexpr(EA), mkexpr(rS) );
++ store( mkexpr(EA), mkexpr(rS), guest_is_BE );
+ break;
+
+ case 0x095: // stdx (Store DWord Indexed, PPC64 p585)
+ DIP("stdx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);
+- store( mkexpr(EA), mkexpr(rS) );
++ store( mkexpr(EA), mkexpr(rS), guest_is_BE );
+ break;
+
+ default:
+@@ -5175,7 +5282,7 @@ static Bool dis_int_store ( UInt theInstr, VexAbiInfo* vbi )
+ return False;
+
+ DIP("std r%u,%d(r%u)\n", rS_addr, simm16, rA_addr);
+- store( mkexpr(EA), mkexpr(rS) );
++ store( mkexpr(EA), mkexpr(rS), guest_is_BE );
+ break;
+
+ case 0x1: // stdu (Store DWord, Update, PPC64 p583)
+@@ -5184,7 +5291,7 @@ static Bool dis_int_store ( UInt theInstr, VexAbiInfo* vbi )
+
+ DIP("stdu r%u,%d(r%u)\n", rS_addr, simm16, rA_addr);
+ putIReg( rA_addr, mkexpr(EA) );
+- store( mkexpr(EA), mkexpr(rS) );
++ store( mkexpr(EA), mkexpr(rS), guest_is_BE );
+ break;
+
+ case 0x2: { // stq (Store QuadWord, Update, PPC64 p583)
+@@ -5206,9 +5313,9 @@ static Bool dis_int_store ( UInt theInstr, VexAbiInfo* vbi )
+ assign( EA_lo, ea_rAor0_simm( rA_addr, simm16+12 ) );
+ }
+ putIReg( rA_addr, mkexpr(EA_hi) );
+- store( mkexpr(EA_hi), mkexpr(rS) );
++ store( mkexpr(EA_hi), mkexpr(rS), guest_is_BE );
+ putIReg( rA_addr, mkexpr( EA_lo) );
+- store( mkexpr(EA_lo), getIReg( rS_addr+1 ) );
++ store( mkexpr(EA_lo), getIReg( rS_addr+1 ), guest_is_BE );
+ break;
+ }
+ default:
+@@ -5229,7 +5336,7 @@ static Bool dis_int_store ( UInt theInstr, VexAbiInfo* vbi )
+ /*
+ Integer Load/Store Multiple Instructions
+ */
+-static Bool dis_int_ldst_mult ( UInt theInstr )
++static Bool dis_int_ldst_mult ( UInt theInstr, Bool guest_is_BE )
+ {
+ /* D-Form */
+ UChar opc1 = ifieldOPC(theInstr);
+@@ -5257,7 +5364,7 @@ static Bool dis_int_ldst_mult ( UInt theInstr )
+ DIP("lmw r%u,%d(r%u)\n", rD_addr, simm16, rA_addr);
+ for (r = rD_addr; r <= 31; r++) {
+ irx_addr = binop(mkAdd, mkexpr(EA), mode64 ? mkU64(ea_off) : mkU32(ea_off));
+- putIReg( r, mkWidenFrom32(ty, load(Ity_I32, irx_addr ),
++ putIReg( r, mkWidenFrom32(ty, load(Ity_I32, irx_addr, guest_is_BE ),
+ False) );
+ ea_off += 4;
+ }
+@@ -5267,7 +5374,7 @@ static Bool dis_int_ldst_mult ( UInt theInstr )
+ DIP("stmw r%u,%d(r%u)\n", rS_addr, simm16, rA_addr);
+ for (r = rS_addr; r <= 31; r++) {
+ irx_addr = binop(mkAdd, mkexpr(EA), mode64 ? mkU64(ea_off) : mkU32(ea_off));
+- store( irx_addr, mkNarrowTo32(ty, getIReg(r)) );
++ store( irx_addr, mkNarrowTo32(ty, getIReg(r)), guest_is_BE );
+ ea_off += 4;
+ }
+ break;
+@@ -5288,7 +5395,8 @@ static
+ void generate_lsw_sequence ( IRTemp tNBytes, // # bytes, :: Ity_I32
+ IRTemp EA, // EA
+ Int rD, // first dst register
+- Int maxBytes ) // 32 or 128
++ Int maxBytes,
++ Bool guest_is_BE ) // 32 or 128
+ {
+ Int i, shift = 24;
+ IRExpr* e_nbytes = mkexpr(tNBytes);
+@@ -5324,7 +5432,8 @@ void generate_lsw_sequence ( IRTemp tNBytes, // # bytes, :: Ity_I32
+ Iop_8Uto32,
+ load( Ity_I8,
+ binop( mkSzOp(ty,Iop_Add8),
+- e_EA, mkSzImm(ty,i)))
++ e_EA, mkSzImm(ty,i)),
++ guest_is_BE )
+ ),
+ mkU8(toUChar(shift))
+ )
+@@ -5340,7 +5449,8 @@ static
+ void generate_stsw_sequence ( IRTemp tNBytes, // # bytes, :: Ity_I32
+ IRTemp EA, // EA
+ Int rS, // first src register
+- Int maxBytes ) // 32 or 128
++ Int maxBytes, // 32 or 128
++ Bool guest_is_BE)
+ {
+ Int i, shift = 24;
+ IRExpr* e_nbytes = mkexpr(tNBytes);
+@@ -5367,13 +5477,14 @@ void generate_stsw_sequence ( IRTemp tNBytes, // # bytes, :: Ity_I32
+ unop( Iop_32to8,
+ binop( Iop_Shr32,
+ mkNarrowTo32( ty, getIReg(rS) ),
+- mkU8( toUChar(shift) )))
+- );
++ mkU8( toUChar(shift) ))),
++ guest_is_BE);
+ shift -= 8;
+ }
+ }
+
+-static Bool dis_int_ldst_str ( UInt theInstr, /*OUT*/Bool* stopHere )
++static Bool dis_int_ldst_str ( UInt theInstr, /*OUT*/Bool* stopHere,
++ Bool guest_is_BE )
+ {
+ /* X-Form */
+ UChar opc1 = ifieldOPC(theInstr);
+@@ -5406,14 +5517,15 @@ static Bool dis_int_ldst_str ( UInt theInstr, /*OUT*/Bool* stopHere )
+ /* Special case hack */
+ /* rD = Mem[EA]; (rD+1)%32 = Mem[EA+4] */
+ putIReg( rD_addr,
+- load(Ity_I32, mkexpr(t_EA)) );
++ load(Ity_I32, mkexpr(t_EA), guest_is_BE ) );
+ putIReg( (rD_addr+1) % 32,
+ load(Ity_I32,
+- binop(Iop_Add32, mkexpr(t_EA), mkU32(4))) );
++ binop(Iop_Add32, mkexpr(t_EA), mkU32(4)),
++ guest_is_BE ));
+ } else {
+ t_nbytes = newTemp(Ity_I32);
+ assign( t_nbytes, mkU32(NumBytes==0 ? 32 : NumBytes) );
+- generate_lsw_sequence( t_nbytes, t_EA, rD_addr, 32 );
++ generate_lsw_sequence( t_nbytes, t_EA, rD_addr, 32, guest_is_BE );
+ *stopHere = True;
+ }
+ return True;
+@@ -5431,7 +5543,7 @@ static Bool dis_int_ldst_str ( UInt theInstr, /*OUT*/Bool* stopHere )
+ t_nbytes = newTemp(Ity_I32);
+ assign( t_EA, ea_rAor0_idxd(rA_addr,rB_addr) );
+ assign( t_nbytes, unop( Iop_8Uto32, getXER_BC() ) );
+- generate_lsw_sequence( t_nbytes, t_EA, rD_addr, 128 );
++ generate_lsw_sequence( t_nbytes, t_EA, rD_addr, 128, guest_is_BE );
+ *stopHere = True;
+ return True;
+
+@@ -5441,14 +5553,13 @@ static Bool dis_int_ldst_str ( UInt theInstr, /*OUT*/Bool* stopHere )
+ if (NumBytes == 8 && !mode64) {
+ /* Special case hack */
+ /* Mem[EA] = rD; Mem[EA+4] = (rD+1)%32 */
+- store( mkexpr(t_EA),
+- getIReg(rD_addr) );
++ store( mkexpr(t_EA), getIReg(rD_addr), guest_is_BE );
+ store( binop(Iop_Add32, mkexpr(t_EA), mkU32(4)),
+- getIReg((rD_addr+1) % 32) );
++ getIReg((rD_addr+1) % 32), guest_is_BE );
+ } else {
+ t_nbytes = newTemp(Ity_I32);
+ assign( t_nbytes, mkU32(NumBytes==0 ? 32 : NumBytes) );
+- generate_stsw_sequence( t_nbytes, t_EA, rD_addr, 32 );
++ generate_stsw_sequence( t_nbytes, t_EA, rD_addr, 32, guest_is_BE );
+ *stopHere = True;
+ }
+ return True;
+@@ -5458,7 +5569,7 @@ static Bool dis_int_ldst_str ( UInt theInstr, /*OUT*/Bool* stopHere )
+ t_nbytes = newTemp(Ity_I32);
+ assign( t_EA, ea_rAor0_idxd(rA_addr,rB_addr) );
+ assign( t_nbytes, unop( Iop_8Uto32, getXER_BC() ) );
+- generate_stsw_sequence( t_nbytes, t_EA, rS_addr, 128 );
++ generate_stsw_sequence( t_nbytes, t_EA, rS_addr, 128, guest_is_BE );
+ *stopHere = True;
+ return True;
+
+@@ -6087,7 +6198,7 @@ static Bool dis_syslink ( UInt theInstr,
+ check any stores it does. Instead, the reservation is cancelled when
+ the scheduler switches to another thread (run_thread_for_a_while()).
+ */
+-static Bool dis_memsync ( UInt theInstr )
++static Bool dis_memsync ( UInt theInstr, Bool guest_is_BE )
+ {
+ /* X-Form, XL-Form */
+ UChar opc1 = ifieldOPC(theInstr);
+@@ -6147,7 +6258,7 @@ static Bool dis_memsync ( UInt theInstr )
+
+ // and actually do the load
+ res = newTemp(Ity_I32);
+- stmt( IRStmt_LLSC(IENDIANESS, res, mkexpr(EA), NULL/*this is a load*/) );
++ stmt( stmt_load(guest_is_BE, res, mkexpr(EA), NULL/*this is a load*/) );
+
+ putIReg( rD_addr, mkWidenFrom32(ty, mkexpr(res), False) );
+ break;
+@@ -6173,7 +6284,7 @@ static Bool dis_memsync ( UInt theInstr )
+
+ // Do the store, and get success/failure bit into resSC
+ resSC = newTemp(Ity_I1);
+- stmt( IRStmt_LLSC(IENDIANESS, resSC, mkexpr(EA), mkexpr(rS)) );
++ stmt( stmt_load(guest_is_BE, resSC, mkexpr(EA), mkexpr(rS)) );
+
+ // Set CR0[LT GT EQ S0] = 0b000 || XER[SO] on failure
+ // Set CR0[LT GT EQ S0] = 0b001 || XER[SO] on success
+@@ -6240,7 +6351,7 @@ static Bool dis_memsync ( UInt theInstr )
+
+ // and actually do the load
+ res = newTemp(Ity_I64);
+- stmt( IRStmt_LLSC(IENDIANESS, res, mkexpr(EA), NULL/*this is a load*/) );
++ stmt( stmt_load(guest_is_BE, res, mkexpr(EA), NULL/*this is a load*/) );
+
+ putIReg( rD_addr, mkexpr(res) );
+ break;
+@@ -6266,7 +6377,7 @@ static Bool dis_memsync ( UInt theInstr )
+
+ // Do the store, and get success/failure bit into resSC
+ resSC = newTemp(Ity_I1);
+- stmt( IRStmt_LLSC(IENDIANESS, resSC, mkexpr(EA), mkexpr(rS)) );
++ stmt( stmt_load(guest_is_BE, resSC, mkexpr(EA), mkexpr(rS)) );
+
+ // Set CR0[LT GT EQ S0] = 0b000 || XER[SO] on failure
+ // Set CR0[LT GT EQ S0] = 0b001 || XER[SO] on success
+@@ -6296,18 +6407,18 @@ static Bool dis_memsync ( UInt theInstr )
+
+ // and actually do the load
+ if (mode64) {
+- stmt( IRStmt_LLSC( IENDIANESS, res_hi,
+- mkexpr(EA), NULL/*this is a load*/) );
+- stmt( IRStmt_LLSC( IENDIANESS, res_lo,
+- binop(Iop_Add64, mkexpr(EA), mkU64(8) ),
+- NULL/*this is a load*/) );
++ stmt( stmt_load( guest_is_BE, res_hi,
++ mkexpr(EA), NULL/*this is a load*/) );
++ stmt( stmt_load( guest_is_BE, res_lo,
++ binop(Iop_Add64, mkexpr(EA), mkU64(8) ),
++ NULL/*this is a load*/) );
+ } else {
+- stmt( IRStmt_LLSC( IENDIANESS, res_hi,
+- binop( Iop_Add32, mkexpr(EA), mkU32(4) ),
+- NULL/*this is a load*/) );
+- stmt( IRStmt_LLSC( IENDIANESS, res_lo,
+- binop( Iop_Add32, mkexpr(EA), mkU32(12) ),
+- NULL/*this is a load*/) );
++ stmt( stmt_load( guest_is_BE, res_hi,
++ binop( Iop_Add32, mkexpr(EA), mkU32(4) ),
++ NULL/*this is a load*/) );
++ stmt( stmt_load( guest_is_BE, res_lo,
++ binop( Iop_Add32, mkexpr(EA), mkU32(12) ),
++ NULL/*this is a load*/) );
+ }
+ putIReg( rD_addr, mkexpr(res_hi) );
+ putIReg( rD_addr+1, mkexpr(res_lo) );
+@@ -6336,14 +6447,16 @@ static Bool dis_memsync ( UInt theInstr )
+ resSC = newTemp(Ity_I1);
+
+ if (mode64) {
+- stmt( IRStmt_LLSC( IENDIANESS, resSC, mkexpr(EA), mkexpr(rS_hi) ) );
+- store( binop( Iop_Add64, mkexpr(EA), mkU64(8) ), mkexpr(rS_lo) );
++ stmt( stmt_load( guest_is_BE, resSC, mkexpr(EA), mkexpr(rS_hi) ) );
++ store( binop( Iop_Add64, mkexpr(EA), mkU64(8) ), mkexpr(rS_lo),
++ guest_is_BE );
+ } else {
+- stmt( IRStmt_LLSC( IENDIANESS, resSC, binop( Iop_Add32,
+- mkexpr(EA),
+- mkU32(4) ),
+- mkexpr(rS_hi) ) );
+- store( binop(Iop_Add32, mkexpr(EA), mkU32(12) ), mkexpr(rS_lo) );
++ stmt( stmt_load( guest_is_BE, resSC, binop( Iop_Add32,
++ mkexpr(EA),
++ mkU32(4) ),
++ mkexpr(rS_hi) ) );
++ store( binop(Iop_Add32, mkexpr(EA), mkU32(12) ), mkexpr(rS_lo),
++ guest_is_BE );
+ }
+
+ // Set CR0[LT GT EQ S0] = 0b000 || XER[SO] on failure
+@@ -6639,7 +6752,7 @@ static IRExpr* /* :: Ity_I32 */ gen_byterev16 ( IRTemp t )
+ );
+ }
+
+-static Bool dis_int_ldst_rev ( UInt theInstr )
++static Bool dis_int_ldst_rev ( UInt theInstr, Bool guest_is_BE )
+ {
+ /* X-Form */
+ UChar opc1 = ifieldOPC(theInstr);
+@@ -6666,7 +6779,8 @@ static Bool dis_int_ldst_rev ( UInt theInstr )
+
+ case 0x316: // lhbrx (Load Halfword Byte-Reverse Indexed, PPC32 p449)
+ DIP("lhbrx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
+- assign( w1, unop(Iop_16Uto32, load(Ity_I16, mkexpr(EA))) );
++ assign( w1, unop(Iop_16Uto32, load(Ity_I16, mkexpr(EA),
++ guest_is_BE )) );
+ assign( w2, gen_byterev16(w1) );
+ putIReg( rD_addr, mkWidenFrom32(ty, mkexpr(w2),
+ /* Signed */False) );
+@@ -6674,7 +6788,7 @@ static Bool dis_int_ldst_rev ( UInt theInstr )
+
+ case 0x216: // lwbrx (Load Word Byte-Reverse Indexed, PPC32 p459)
+ DIP("lwbrx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
+- assign( w1, load(Ity_I32, mkexpr(EA)) );
++ assign( w1, load(Ity_I32, mkexpr(EA), guest_is_BE ));
+ assign( w2, gen_byterev32(w1) );
+ putIReg( rD_addr, mkWidenFrom32(ty, mkexpr(w2),
+ /* Signed */False) );
+@@ -6686,26 +6800,30 @@ static Bool dis_int_ldst_rev ( UInt theInstr )
+ IRTemp w3 = newTemp( Ity_I32 );
+ IRTemp w4 = newTemp( Ity_I32 );
+ DIP("ldbrx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
+- assign( w1, load( Ity_I32, mkexpr( EA ) ) );
++ assign( w1, load( Ity_I32, mkexpr( EA ), guest_is_BE ) );
+ assign( w2, gen_byterev32( w1 ) );
+ nextAddr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( 4 ) : mkU32( 4 ) );
+- assign( w3, load( Ity_I32, nextAddr ) );
++ assign( w3, load( Ity_I32, nextAddr, guest_is_BE ));
+ assign( w4, gen_byterev32( w3 ) );
+- putIReg( rD_addr, binop( Iop_32HLto64, mkexpr( w4 ), mkexpr( w2 ) ) );
++ if (!guest_is_BE)
++ putIReg( rD_addr, binop( Iop_32HLto64, mkexpr( w2 ), mkexpr( w4 ) ) );
++ else
++ putIReg( rD_addr, binop( Iop_32HLto64, mkexpr( w4 ), mkexpr( w2 ) ) );
+ break;
+ }
+
+ case 0x396: // sthbrx (Store Half Word Byte-Reverse Indexed, PPC32 p523)
+ DIP("sthbrx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);
+ assign( w1, mkNarrowTo32(ty, getIReg(rS_addr)) );
+- store( mkexpr(EA), unop(Iop_32to16, gen_byterev16(w1)) );
++ store( mkexpr(EA), unop(Iop_32to16, gen_byterev16(w1)),
++ guest_is_BE );
+ break;
+
+ case 0x296: // stwbrx (Store Word Byte-Reverse Indxd, PPC32 p531)
+ DIP("stwbrx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);
+ assign( w1, mkNarrowTo32(ty, getIReg(rS_addr)) );
+- store( mkexpr(EA), gen_byterev32(w1) );
++ store( mkexpr(EA), gen_byterev32(w1), guest_is_BE );
+ break;
+
+ case 0x294: // stdbrx (Store Doubleword Byte-Reverse Indexed)
+@@ -6719,7 +6837,8 @@ static Bool dis_int_ldst_rev ( UInt theInstr )
+ assign(hi, unop(Iop_64to32, mkexpr(rS)));
+ store( mkexpr( EA ),
+ binop( Iop_32HLto64, gen_byterev32( hi ),
+- gen_byterev32( lo ) ) );
++ gen_byterev32( lo ) ),
++ guest_is_BE );
+ break;
+ }
+
+@@ -7138,7 +7257,8 @@ static Bool dis_proc_ctl ( VexAbiInfo* vbi, UInt theInstr )
+ */
+ static Bool dis_cache_manage ( UInt theInstr,
+ DisResult* dres,
+- VexArchInfo* guest_archinfo )
++ VexArchInfo* guest_archinfo,
++ Bool guest_is_BE)
+ {
+ /* X-Form */
+ UChar opc1 = ifieldOPC(theInstr);
+@@ -7237,7 +7357,7 @@ static Bool dis_cache_manage ( UInt theInstr,
+
+ for (i = 0; i < clearszB / 8; i++) {
+ irx_addr = binop( Iop_Add64, mkexpr(addr), mkU64(i*8) );
+- store( irx_addr, mkU64(0) );
++ store( irx_addr, mkU64(0), guest_is_BE );
+ }
+ } else {
+ /* Round EA down to the start of the containing block. */
+@@ -7247,7 +7367,7 @@ static Bool dis_cache_manage ( UInt theInstr,
+
+ for (i = 0; i < clearszB / 4; i++) {
+ irx_addr = binop( Iop_Add32, mkexpr(addr), mkU32(i*4) );
+- store( irx_addr, mkU32(0) );
++ store( irx_addr, mkU32(0), guest_is_BE );
+ }
+ }
+ break;
+@@ -7436,7 +7556,7 @@ static IRExpr * Complement_non_NaN( IRExpr * value, IRExpr * nan_mask )
+ /*
+ Floating Point Load Instructions
+ */
+-static Bool dis_fp_load ( UInt theInstr )
++static Bool dis_fp_load ( UInt theInstr, Bool guest_is_BE )
+ {
+ /* X-Form, D-Form */
+ UChar opc1 = ifieldOPC(theInstr);
+@@ -7467,7 +7587,8 @@ static Bool dis_fp_load ( UInt theInstr )
+ DIP("lfs fr%u,%d(r%u)\n", frD_addr, simm16, rA_addr);
+ assign( EA, ea_rAor0_simm(rA_addr, simm16) );
+ putFReg( frD_addr,
+- unop(Iop_F32toF64, load(Ity_F32, mkexpr(EA))) );
++ unop(Iop_F32toF64, load(Ity_F32, mkexpr(EA), guest_is_BE)),
++ guest_is_BE);
+ break;
+
+ case 0x31: // lfsu (Load Float Single, Update, PPC32 p442)
+@@ -7476,14 +7597,16 @@ static Bool dis_fp_load ( UInt theInstr )
+ DIP("lfsu fr%u,%d(r%u)\n", frD_addr, simm16, rA_addr);
+ assign( EA, ea_rA_simm(rA_addr, simm16) );
+ putFReg( frD_addr,
+- unop(Iop_F32toF64, load(Ity_F32, mkexpr(EA))) );
++ unop(Iop_F32toF64, load(Ity_F32, mkexpr(EA), guest_is_BE)),
++ guest_is_BE );
+ putIReg( rA_addr, mkexpr(EA) );
+ break;
+
+ case 0x32: // lfd (Load Float Double, PPC32 p437)
+ DIP("lfd fr%u,%d(r%u)\n", frD_addr, simm16, rA_addr);
+ assign( EA, ea_rAor0_simm(rA_addr, simm16) );
+- putFReg( frD_addr, load(Ity_F64, mkexpr(EA)) );
++ putFReg( frD_addr, load(Ity_F64, mkexpr(EA), guest_is_BE ),
++ guest_is_BE );
+ break;
+
+ case 0x33: // lfdu (Load Float Double, Update, PPC32 p438)
+@@ -7491,7 +7614,8 @@ static Bool dis_fp_load ( UInt theInstr )
+ return False;
+ DIP("lfdu fr%u,%d(r%u)\n", frD_addr, simm16, rA_addr);
+ assign( EA, ea_rA_simm(rA_addr, simm16) );
+- putFReg( frD_addr, load(Ity_F64, mkexpr(EA)) );
++ putFReg( frD_addr, load(Ity_F64, mkexpr(EA), guest_is_BE),
++ guest_is_BE );
+ putIReg( rA_addr, mkexpr(EA) );
+ break;
+
+@@ -7506,7 +7630,8 @@ static Bool dis_fp_load ( UInt theInstr )
+ DIP("lfsx fr%u,r%u,r%u\n", frD_addr, rA_addr, rB_addr);
+ assign( EA, ea_rAor0_idxd(rA_addr, rB_addr) );
+ putFReg( frD_addr, unop( Iop_F32toF64,
+- load(Ity_F32, mkexpr(EA))) );
++ load(Ity_F32, mkexpr(EA), guest_is_BE)),
++ guest_is_BE );
+ break;
+
+ case 0x237: // lfsux (Load Float Single, Update Indxd, PPC32 p443)
+@@ -7515,14 +7640,16 @@ static Bool dis_fp_load ( UInt theInstr )
+ DIP("lfsux fr%u,r%u,r%u\n", frD_addr, rA_addr, rB_addr);
+ assign( EA, ea_rA_idxd(rA_addr, rB_addr) );
+ putFReg( frD_addr,
+- unop(Iop_F32toF64, load(Ity_F32, mkexpr(EA))) );
++ unop(Iop_F32toF64, load(Ity_F32, mkexpr(EA), guest_is_BE)),
++ guest_is_BE );
+ putIReg( rA_addr, mkexpr(EA) );
+ break;
+
+ case 0x257: // lfdx (Load Float Double Indexed, PPC32 p440)
+ DIP("lfdx fr%u,r%u,r%u\n", frD_addr, rA_addr, rB_addr);
+ assign( EA, ea_rAor0_idxd(rA_addr, rB_addr) );
+- putFReg( frD_addr, load(Ity_F64, mkexpr(EA)) );
++ putFReg( frD_addr, load(Ity_F64, mkexpr(EA), guest_is_BE),
++ guest_is_BE );
+ break;
+
+ case 0x277: // lfdux (Load Float Double, Update Indxd, PPC32 p439)
+@@ -7530,19 +7657,22 @@ static Bool dis_fp_load ( UInt theInstr )
+ return False;
+ DIP("lfdux fr%u,r%u,r%u\n", frD_addr, rA_addr, rB_addr);
+ assign( EA, ea_rA_idxd(rA_addr, rB_addr) );
+- putFReg( frD_addr, load(Ity_F64, mkexpr(EA)) );
++ putFReg( frD_addr, load(Ity_F64, mkexpr(EA), guest_is_BE),
++ guest_is_BE );
+ putIReg( rA_addr, mkexpr(EA) );
+ break;
+
+ case 0x357: // lfiwax (Load Float As Integer, Indxd, ISA 2.05 p120)
+ DIP("lfiwax fr%u,r%u,r%u\n", frD_addr, rA_addr, rB_addr);
+ assign( EA, ea_rAor0_idxd( rA_addr, rB_addr ) );
+- assign( iLo, load(Ity_I32, mkexpr(EA)) );
++ assign( iLo, load(Ity_I32, mkexpr(EA), guest_is_BE) );
+ assign( iHi, binop(Iop_Sub32,
+ mkU32(0),
+ binop(Iop_Shr32, mkexpr(iLo), mkU8(31))) );
+- putFReg( frD_addr, unop(Iop_ReinterpI64asF64,
+- binop(Iop_32HLto64, mkexpr(iHi), mkexpr(iLo))) );
++ putFReg( frD_addr,
++ unop(Iop_ReinterpI64asF64,
++ binop(Iop_32HLto64, mkexpr(iHi), mkexpr(iLo))),
++ guest_is_BE );
+ break;
+
+ case 0x377: // lfiwzx (Load floating-point as integer word, zero indexed
+@@ -7550,9 +7680,10 @@ static Bool dis_fp_load ( UInt theInstr )
+ IRTemp dw = newTemp( Ity_I64 );
+ DIP("lfiwzx fr%u,r%u,r%u\n", frD_addr, rA_addr, rB_addr);
+ assign( EA, ea_rAor0_idxd( rA_addr, rB_addr ) );
+- assign( iLo, load(Ity_I32, mkexpr(EA)) );
++ assign( iLo, load(Ity_I32, mkexpr(EA), guest_is_BE) );
+ assign( dw, binop( Iop_32HLto64, mkU32( 0 ), mkexpr( iLo ) ) );
+- putFReg( frD_addr, unop( Iop_ReinterpI64asF64, mkexpr( dw ) ) );
++ putFReg( frD_addr, unop( Iop_ReinterpI64asF64, mkexpr( dw ) ),
++ guest_is_BE);
+ break;
+ }
+
+@@ -7574,7 +7705,7 @@ static Bool dis_fp_load ( UInt theInstr )
+ /*
+ Floating Point Store Instructions
+ */
+-static Bool dis_fp_store ( UInt theInstr )
++static Bool dis_fp_store ( UInt theInstr, Bool guest_is_BE )
+ {
+ /* X-Form, D-Form */
+ UChar opc1 = ifieldOPC(theInstr);
+@@ -7592,7 +7723,7 @@ static Bool dis_fp_store ( UInt theInstr )
+ IRTemp rA = newTemp(ty);
+ IRTemp rB = newTemp(ty);
+
+- assign( frS, getFReg(frS_addr) );
++ assign( frS, getFReg(frS_addr, guest_is_BE) );
+ assign( rA, getIReg(rA_addr) );
+ assign( rB, getIReg(rB_addr) );
+
+@@ -7609,7 +7740,7 @@ static Bool dis_fp_store ( UInt theInstr )
+ /* Use Iop_TruncF64asF32 to truncate and possible denormalise
+ the value to be stored in the correct way, without any
+ rounding. */
+- store( mkexpr(EA), unop(Iop_TruncF64asF32, mkexpr(frS)) );
++ store( mkexpr(EA), unop(Iop_TruncF64asF32, mkexpr(frS)), guest_is_BE );
+ break;
+
+ case 0x35: // stfsu (Store Float Single, Update, PPC32 p519)
+@@ -7618,14 +7749,14 @@ static Bool dis_fp_store ( UInt theInstr )
+ DIP("stfsu fr%u,%d(r%u)\n", frS_addr, simm16, rA_addr);
+ assign( EA, ea_rA_simm(rA_addr, simm16) );
+ /* See comment for stfs */
+- store( mkexpr(EA), unop(Iop_TruncF64asF32, mkexpr(frS)) );
++ store( mkexpr(EA), unop(Iop_TruncF64asF32, mkexpr(frS)), guest_is_BE );
+ putIReg( rA_addr, mkexpr(EA) );
+ break;
+
+ case 0x36: // stfd (Store Float Double, PPC32 p513)
+ DIP("stfd fr%u,%d(r%u)\n", frS_addr, simm16, rA_addr);
+ assign( EA, ea_rAor0_simm(rA_addr, simm16) );
+- store( mkexpr(EA), mkexpr(frS) );
++ store( mkexpr(EA), mkexpr(frS), guest_is_BE );
+ break;
+
+ case 0x37: // stfdu (Store Float Double, Update, PPC32 p514)
+@@ -7633,7 +7764,7 @@ static Bool dis_fp_store ( UInt theInstr )
+ return False;
+ DIP("stfdu fr%u,%d(r%u)\n", frS_addr, simm16, rA_addr);
+ assign( EA, ea_rA_simm(rA_addr, simm16) );
+- store( mkexpr(EA), mkexpr(frS) );
++ store( mkexpr(EA), mkexpr(frS), guest_is_BE );
+ putIReg( rA_addr, mkexpr(EA) );
+ break;
+
+@@ -7648,7 +7779,8 @@ static Bool dis_fp_store ( UInt theInstr )
+ assign( EA, ea_rAor0_idxd(rA_addr, rB_addr) );
+ /* See note for stfs */
+ store( mkexpr(EA),
+- unop(Iop_TruncF64asF32, mkexpr(frS)) );
++ unop(Iop_TruncF64asF32, mkexpr(frS)),
++ guest_is_BE );
+ break;
+
+ case 0x2B7: // stfsux (Store Float Sgl, Update Indxd, PPC32 p520)
+@@ -7657,14 +7789,15 @@ static Bool dis_fp_store ( UInt theInstr )
+ DIP("stfsux fr%u,r%u,r%u\n", frS_addr, rA_addr, rB_addr);
+ assign( EA, ea_rA_idxd(rA_addr, rB_addr) );
+ /* See note for stfs */
+- store( mkexpr(EA), unop(Iop_TruncF64asF32, mkexpr(frS)) );
++ store( mkexpr(EA), unop(Iop_TruncF64asF32, mkexpr(frS)),
++ guest_is_BE );
+ putIReg( rA_addr, mkexpr(EA) );
+ break;
+
+ case 0x2D7: // stfdx (Store Float Double Indexed, PPC32 p516)
+ DIP("stfdx fr%u,r%u,r%u\n", frS_addr, rA_addr, rB_addr);
+ assign( EA, ea_rAor0_idxd(rA_addr, rB_addr) );
+- store( mkexpr(EA), mkexpr(frS) );
++ store( mkexpr(EA), mkexpr(frS), guest_is_BE );
+ break;
+
+ case 0x2F7: // stfdux (Store Float Dbl, Update Indxd, PPC32 p515)
+@@ -7672,7 +7805,7 @@ static Bool dis_fp_store ( UInt theInstr )
+ return False;
+ DIP("stfdux fr%u,r%u,r%u\n", frS_addr, rA_addr, rB_addr);
+ assign( EA, ea_rA_idxd(rA_addr, rB_addr) );
+- store( mkexpr(EA), mkexpr(frS) );
++ store( mkexpr(EA), mkexpr(frS), guest_is_BE );
+ putIReg( rA_addr, mkexpr(EA) );
+ break;
+
+@@ -7681,7 +7814,8 @@ static Bool dis_fp_store ( UInt theInstr )
+ DIP("stfiwx fr%u,r%u,r%u\n", frS_addr, rA_addr, rB_addr);
+ assign( EA, ea_rAor0_idxd(rA_addr, rB_addr) );
+ store( mkexpr(EA),
+- unop(Iop_64to32, unop(Iop_ReinterpF64asI64, mkexpr(frS))) );
++ unop(Iop_64to32, unop(Iop_ReinterpF64asI64, mkexpr(frS))),
++ guest_is_BE );
+ break;
+
+ default:
+@@ -7702,7 +7836,7 @@ static Bool dis_fp_store ( UInt theInstr )
+ /*
+ Floating Point Arith Instructions
+ */
+-static Bool dis_fp_arith ( UInt theInstr )
++static Bool dis_fp_arith ( UInt theInstr, Bool guest_is_BE )
+ {
+ /* A-Form */
+ UChar opc1 = ifieldOPC(theInstr);
+@@ -7730,9 +7864,9 @@ static Bool dis_fp_arith ( UInt theInstr )
+ zero. Hence cr1 should be cleared if this is a . form insn. */
+ Bool clear_CR1 = True;
+
+- assign( frA, getFReg(frA_addr));
+- assign( frB, getFReg(frB_addr));
+- assign( frC, getFReg(frC_addr));
++ assign( frA, getFReg(frA_addr, guest_is_BE));
++ assign( frB, getFReg(frB_addr, guest_is_BE));
++ assign( frC, getFReg(frC_addr, guest_is_BE));
+
+ switch (opc1) {
+ case 0x3B:
+@@ -7920,7 +8054,7 @@ static Bool dis_fp_arith ( UInt theInstr )
+ return False;
+ }
+
+- putFReg( frD_addr, mkexpr(frD) );
++ putFReg( frD_addr, mkexpr(frD), guest_is_BE );
+
+ if (set_FPRF) {
+ // XXX XXX XXX FIXME
+@@ -7940,7 +8074,7 @@ static Bool dis_fp_arith ( UInt theInstr )
+ /*
+ Floating Point Mult-Add Instructions
+ */
+-static Bool dis_fp_multadd ( UInt theInstr )
++static Bool dis_fp_multadd ( UInt theInstr, Bool guest_is_BE )
+ {
+ /* A-Form */
+ UChar opc1 = ifieldOPC(theInstr);
+@@ -7978,9 +8112,9 @@ static Bool dis_fp_multadd ( UInt theInstr )
+ assign( rmt, get_IR_roundingmode() );
+ rm = mkexpr(rmt);
+
+- assign( frA, getFReg(frA_addr));
+- assign( frB, getFReg(frB_addr));
+- assign( frC, getFReg(frC_addr));
++ assign( frA, getFReg(frA_addr, guest_is_BE));
++ assign( frB, getFReg(frB_addr, guest_is_BE));
++ assign( frC, getFReg(frC_addr, guest_is_BE));
+
+ /* The rounding in this is all a bit dodgy. The idea is to only do
+ one rounding. That clearly isn't achieveable without dedicated
+@@ -8084,7 +8218,7 @@ static Bool dis_fp_multadd ( UInt theInstr )
+ return False;
+ }
+
+- putFReg( frD_addr, mkexpr(frD) );
++ putFReg( frD_addr, mkexpr(frD), guest_is_BE );
+
+ if (set_FPRF) {
+ // XXX XXX XXX FIXME
+@@ -8420,7 +8554,7 @@ static IRExpr * do_fp_tdiv(IRTemp frA_int, IRTemp frB_int)
+ binop( Iop_Shl32, mkexpr(fe_flag), mkU8( 1 ) ) );
+ }
+
+-static Bool dis_fp_tests ( UInt theInstr )
++static Bool dis_fp_tests ( UInt theInstr, Bool guest_is_BE )
+ {
+ UChar opc1 = ifieldOPC(theInstr);
+ UChar crfD = toUChar( IFIELD( theInstr, 23, 3 ) );
+@@ -8433,7 +8567,8 @@ static Bool dis_fp_tests ( UInt theInstr )
+ vex_printf("dis_fp_tests(ppc)(ftdiv)\n");
+ return False;
+ }
+- assign( frB_I64, unop( Iop_ReinterpF64asI64, getFReg( frB_addr ) ) );
++ assign( frB_I64, unop( Iop_ReinterpF64asI64, getFReg( frB_addr,
++ guest_is_BE ) ) );
+
+ switch (opc2) {
+ case 0x080: // ftdiv
+@@ -8446,7 +8581,8 @@ static Bool dis_fp_tests ( UInt theInstr )
+ return False;
+ }
+
+- assign( frA_I64, unop( Iop_ReinterpF64asI64, getFReg( frA_addr ) ) );
++ assign( frA_I64, unop( Iop_ReinterpF64asI64,
++ getFReg( frA_addr, guest_is_BE ) ) );
+ putGST_field( PPC_GST_CR, do_fp_tdiv(frA_I64, frB_I64), crfD );
+
+ DIP("ftdiv crf%d,fr%u,fr%u\n", crfD, frA_addr, frB_addr);
+@@ -8487,7 +8623,7 @@ static Bool dis_fp_tests ( UInt theInstr )
+ /*
+ Floating Point Compare Instructions
+ */
+-static Bool dis_fp_cmp ( UInt theInstr )
++static Bool dis_fp_cmp ( UInt theInstr, Bool guest_is_BE )
+ {
+ /* X-Form */
+ UChar opc1 = ifieldOPC(theInstr);
+@@ -8509,8 +8645,8 @@ static Bool dis_fp_cmp ( UInt theInstr )
+ return False;
+ }
+
+- assign( frA, getFReg(frA_addr));
+- assign( frB, getFReg(frB_addr));
++ assign( frA, getFReg(frA_addr, guest_is_BE));
++ assign( frB, getFReg(frB_addr, guest_is_BE));
+
+ assign( ccIR, binop(Iop_CmpF64, mkexpr(frA), mkexpr(frB)) );
+
+@@ -8586,7 +8722,7 @@ static Bool dis_fp_cmp ( UInt theInstr )
+ /*
+ Floating Point Rounding/Conversion Instructions
+ */
+-static Bool dis_fp_round ( UInt theInstr )
++static Bool dis_fp_round ( UInt theInstr, Bool guest_is_BE )
+ {
+ /* X-Form */
+ UChar opc1 = ifieldOPC(theInstr);
+@@ -8617,7 +8753,7 @@ static Bool dis_fp_round ( UInt theInstr )
+ return False;
+ }
+
+- assign( frB, getFReg(frB_addr));
++ assign( frB, getFReg(frB_addr, guest_is_BE));
+ if (opc1 == 0x3B) {
+ /* The fcfid[u]s instructions (from ISA 2.06) are a bit odd because
+ * they're very similar to the other instructions handled here, but have
+@@ -8781,7 +8917,7 @@ static Bool dis_fp_round ( UInt theInstr )
+ return False;
+ }
+ putFR:
+- putFReg( frD_addr, mkexpr(frD) );
++ putFReg( frD_addr, mkexpr(frD), guest_is_BE );
+
+ if (set_FPRF) {
+ // XXX XXX XXX FIXME
+@@ -8799,7 +8935,7 @@ putFR:
+ /*
+ Floating Point Pair Instructions
+ */
+-static Bool dis_fp_pair ( UInt theInstr )
++static Bool dis_fp_pair ( UInt theInstr, Bool guest_is_BE )
+ {
+ /* X-Form/DS-Form */
+ UChar opc1 = ifieldOPC(theInstr);
+@@ -8863,15 +8999,17 @@ static Bool dis_fp_pair ( UInt theInstr )
+ else
+ assign( EA_lo, binop(Iop_Add32, mkexpr(EA_hi), mkU32(8)) );
+
+- assign( frT_hi, getFReg(frT_hi_addr) );
+- assign( frT_lo, getFReg(frT_lo_addr) );
++ assign( frT_hi, getFReg(frT_hi_addr, guest_is_BE) );
++ assign( frT_lo, getFReg(frT_lo_addr, guest_is_BE) );
+
+ if (is_load) {
+- putFReg( frT_hi_addr, load(Ity_F64, mkexpr(EA_hi)) );
+- putFReg( frT_lo_addr, load(Ity_F64, mkexpr(EA_lo)) );
++ putFReg( frT_hi_addr, load(Ity_F64, mkexpr(EA_hi), guest_is_BE),
++ guest_is_BE );
++ putFReg( frT_lo_addr, load(Ity_F64, mkexpr(EA_lo), guest_is_BE),
++ guest_is_BE );
+ } else {
+- store( mkexpr(EA_hi), mkexpr(frT_hi) );
+- store( mkexpr(EA_lo), mkexpr(frT_lo) );
++ store( mkexpr(EA_hi), mkexpr(frT_hi), guest_is_BE );
++ store( mkexpr(EA_lo), mkexpr(frT_lo), guest_is_BE );
+ }
+
+ return True;
+@@ -8881,7 +9019,7 @@ static Bool dis_fp_pair ( UInt theInstr )
+ /*
+ Floating Point Merge Instructions
+ */
+-static Bool dis_fp_merge ( UInt theInstr )
++static Bool dis_fp_merge ( UInt theInstr, Bool guest_is_BE )
+ {
+ /* X-Form */
+ UInt opc2 = ifieldOPClo10(theInstr);
+@@ -8893,8 +9031,8 @@ static Bool dis_fp_merge ( UInt theInstr )
+ IRTemp frA = newTemp(Ity_F64);
+ IRTemp frB = newTemp(Ity_F64);
+
+- assign( frA, getFReg(frA_addr));
+- assign( frB, getFReg(frB_addr));
++ assign( frA, getFReg(frA_addr, guest_is_BE));
++ assign( frB, getFReg(frB_addr, guest_is_BE));
+
+ switch (opc2) {
+ case 0x3c6: // fmrgew floating merge even word
+@@ -8928,14 +9066,14 @@ static Bool dis_fp_merge ( UInt theInstr )
+ return False;
+ }
+
+- putFReg( frD_addr, mkexpr(frD) );
++ putFReg( frD_addr, mkexpr(frD), guest_is_BE );
+ return True;
+ }
+
+ /*
+ Floating Point Move Instructions
+ */
+-static Bool dis_fp_move ( UInt theInstr )
++static Bool dis_fp_move ( UInt theInstr, Bool guest_is_BE )
+ {
+ /* X-Form */
+ UChar opc1 = ifieldOPC(theInstr);
+@@ -8957,7 +9095,7 @@ static Bool dis_fp_move ( UInt theInstr )
+ return False;
+ }
+
+- assign( frB, getFReg(frB_addr));
++ assign( frB, getFReg(frB_addr, guest_is_BE));
+
+ switch (opc2) {
+ case 0x008: // fcpsgn (Floating Copy Sign, ISA_V2.05 p126)
+@@ -8967,7 +9105,7 @@ static Bool dis_fp_move ( UInt theInstr )
+ hiD = newTemp(Ity_I32);
+ itmpB = newTemp(Ity_I64);
+ frA = newTemp(Ity_F64);
+- assign( frA, getFReg(frA_addr) );
++ assign( frA, getFReg(frA_addr, guest_is_BE) );
+
+ /* get A's sign bit */
+ assign(signA, binop(Iop_And32,
+@@ -9018,7 +9156,7 @@ static Bool dis_fp_move ( UInt theInstr )
+ return False;
+ }
+
+- putFReg( frD_addr, mkexpr(frD) );
++ putFReg( frD_addr, mkexpr(frD), guest_is_BE );
+
+ /* None of these change FPRF. cr1 is set in the usual way though,
+ if flag_rC is set. */
+@@ -9036,7 +9174,7 @@ static Bool dis_fp_move ( UInt theInstr )
+ /*
+ Floating Point Status/Control Register Instructions
+ */
+-static Bool dis_fp_scr ( UInt theInstr, Bool GX_level )
++static Bool dis_fp_scr ( UInt theInstr, Bool GX_level, Bool guest_is_BE )
+ {
+ /* Many forms - see each switch case */
+ UChar opc1 = ifieldOPC(theInstr);
+@@ -9138,8 +9276,9 @@ static Bool dis_fp_scr ( UInt theInstr, Bool GX_level )
+ }
+ DIP("mffs%s fr%u\n", flag_rC ? ".":"", frD_addr);
+ putFReg( frD_addr,
+- unop( Iop_ReinterpI64asF64,
+- binop( Iop_32HLto64, fpscr_upper, fpscr_lower ) ) );
++ unop( Iop_ReinterpI64asF64,
++ binop( Iop_32HLto64, fpscr_upper, fpscr_lower ) ),
++ guest_is_BE );
+ break;
+ }
+
+@@ -9195,7 +9334,7 @@ static Bool dis_fp_scr ( UInt theInstr, Bool GX_level )
+ }
+ }
+ }
+- assign( frB, getFReg(frB_addr));
++ assign( frB, getFReg(frB_addr, guest_is_BE));
+ assign( rB_64, unop( Iop_ReinterpF64asI64, mkexpr( frB ) ) );
+ putGST_masked( PPC_GST_FPSCR, mkexpr( rB_64 ), mask );
+ break;
+@@ -9855,7 +9994,7 @@ static IRExpr * Check_unordered(IRExpr * val)
+ /*------------------------------------------------------------*/
+
+ /* DFP Arithmetic instructions */
+-static Bool dis_dfp_arith(UInt theInstr)
++static Bool dis_dfp_arith(UInt theInstr, Bool guest_is_BE)
+ {
+ UInt opc2 = ifieldOPClo10( theInstr );
+ UChar frS_addr = ifieldRegDS( theInstr );
+@@ -9876,8 +10015,8 @@ static Bool dis_dfp_arith(UInt theInstr)
+ */
+ Bool clear_CR1 = True;
+
+- assign( frA, getDReg( frA_addr ) );
+- assign( frB, getDReg( frB_addr ) );
++ assign( frA, getDReg( frA_addr, guest_is_BE ) );
++ assign( frB, getDReg( frB_addr, guest_is_BE ) );
+
+ switch (opc2) {
+ case 0x2: // dadd
+@@ -9902,7 +10041,7 @@ static Bool dis_dfp_arith(UInt theInstr)
+ break;
+ }
+
+- putDReg( frS_addr, mkexpr( frS ) );
++ putDReg( frS_addr, mkexpr( frS), guest_is_BE );
+
+ if (flag_rC && clear_CR1) {
+ putCR321( 1, mkU8( 0 ) );
+@@ -9913,7 +10052,7 @@ static Bool dis_dfp_arith(UInt theInstr)
+ }
+
+ /* Quad DFP Arithmetic instructions */
+-static Bool dis_dfp_arithq(UInt theInstr)
++static Bool dis_dfp_arithq(UInt theInstr, Bool guest_is_BE)
+ {
+ UInt opc2 = ifieldOPClo10( theInstr );
+ UChar frS_addr = ifieldRegDS( theInstr );
+@@ -9934,8 +10073,8 @@ static Bool dis_dfp_arithq(UInt theInstr)
+ */
+ Bool clear_CR1 = True;
+
+- assign( frA, getDReg_pair( frA_addr ) );
+- assign( frB, getDReg_pair( frB_addr ) );
++ assign( frA, getDReg_pair( frA_addr, guest_is_BE ) );
++ assign( frB, getDReg_pair( frB_addr, guest_is_BE ) );
+
+ switch (opc2) {
+ case 0x2: // daddq
+@@ -9960,7 +10099,7 @@ static Bool dis_dfp_arithq(UInt theInstr)
+ break;
+ }
+
+- putDReg_pair( frS_addr, mkexpr( frS ) );
++ putDReg_pair( frS_addr, mkexpr( frS ), guest_is_BE );
+
+ if (flag_rC && clear_CR1) {
+ putCR321( 1, mkU8( 0 ) );
+@@ -9971,7 +10110,7 @@ static Bool dis_dfp_arithq(UInt theInstr)
+ }
+
+ /* DFP 64-bit logical shift instructions */
+-static Bool dis_dfp_shift(UInt theInstr) {
++static Bool dis_dfp_shift(UInt theInstr, Bool guest_is_BE) {
+ UInt opc2 = ifieldOPClo9( theInstr );
+ UChar frS_addr = ifieldRegDS( theInstr );
+ UChar frA_addr = ifieldRegA( theInstr );
+@@ -9982,7 +10121,7 @@ static Bool dis_dfp_shift(UInt theInstr) {
+ IRTemp frS = newTemp( Ity_D64 );
+ Bool clear_CR1 = True;
+
+- assign( frA, getDReg( frA_addr ) );
++ assign( frA, getDReg( frA_addr, guest_is_BE ) );
+
+ switch (opc2) {
+ case 0x42: // dscli
+@@ -9997,7 +10136,7 @@ static Bool dis_dfp_shift(UInt theInstr) {
+ break;
+ }
+
+- putDReg( frS_addr, mkexpr( frS ) );
++ putDReg( frS_addr, mkexpr( frS ), guest_is_BE );
+
+ if (flag_rC && clear_CR1) {
+ putCR321( 1, mkU8( 0 ) );
+@@ -10008,7 +10147,7 @@ static Bool dis_dfp_shift(UInt theInstr) {
+ }
+
+ /* Quad DFP logical shift instructions */
+-static Bool dis_dfp_shiftq(UInt theInstr) {
++static Bool dis_dfp_shiftq(UInt theInstr, Bool guest_is_BE) {
+ UInt opc2 = ifieldOPClo9( theInstr );
+ UChar frS_addr = ifieldRegDS( theInstr );
+ UChar frA_addr = ifieldRegA( theInstr );
+@@ -10019,7 +10158,7 @@ static Bool dis_dfp_shiftq(UInt theInstr) {
+ IRTemp frS = newTemp( Ity_D128 );
+ Bool clear_CR1 = True;
+
+- assign( frA, getDReg_pair( frA_addr ) );
++ assign( frA, getDReg_pair( frA_addr, guest_is_BE ) );
+
+ switch (opc2) {
+ case 0x42: // dscliq
+@@ -10034,7 +10173,7 @@ static Bool dis_dfp_shiftq(UInt theInstr) {
+ break;
+ }
+
+- putDReg_pair( frS_addr, mkexpr( frS ) );
++ putDReg_pair( frS_addr, mkexpr( frS ), guest_is_BE );
+
+ if (flag_rC && clear_CR1) {
+ putCR321( 1, mkU8( 0 ) );
+@@ -10045,7 +10184,7 @@ static Bool dis_dfp_shiftq(UInt theInstr) {
+ }
+
+ /* DFP 64-bit format conversion instructions */
+-static Bool dis_dfp_fmt_conv(UInt theInstr) {
++static Bool dis_dfp_fmt_conv(UInt theInstr, Bool guest_is_BE) {
+ UInt opc2 = ifieldOPClo10( theInstr );
+ UChar frS_addr = ifieldRegDS( theInstr );
+ UChar frB_addr = ifieldRegB( theInstr );
+@@ -10062,18 +10201,18 @@ static Bool dis_dfp_fmt_conv(UInt theInstr) {
+
+ frB = newTemp( Ity_D32 );
+ frS = newTemp( Ity_D64 );
+- assign( frB, getDReg32( frB_addr ) );
++ assign( frB, getDReg32( frB_addr, guest_is_BE ) );
+ assign( frS, unop( Iop_D32toD64, mkexpr( frB ) ) );
+- putDReg( frS_addr, mkexpr( frS ) );
++ putDReg( frS_addr, mkexpr( frS), guest_is_BE );
+ break;
+ case 0x302: // drsp
+ DIP( "drsp%s fr%u,fr%u\n",
+ flag_rC ? ".":"", frS_addr, frB_addr );
+ frB = newTemp( Ity_D64 );
+ frS = newTemp( Ity_D32 );
+- assign( frB, getDReg( frB_addr ) );
++ assign( frB, getDReg( frB_addr, guest_is_BE ) );
+ assign( frS, binop( Iop_D64toD32, round, mkexpr( frB ) ) );
+- putDReg32( frS_addr, mkexpr( frS ) );
++ putDReg32( frS_addr, mkexpr( frS ), guest_is_BE );
+ break;
+ case 0x122: // dctfix
+ {
+@@ -10083,10 +10222,10 @@ static Bool dis_dfp_fmt_conv(UInt theInstr) {
+ flag_rC ? ".":"", frS_addr, frB_addr );
+ frB = newTemp( Ity_D64 );
+ frS = newTemp( Ity_D64 );
+- assign( frB, getDReg( frB_addr ) );
++ assign( frB, getDReg( frB_addr, guest_is_BE ) );
+ assign( tmp, binop( Iop_D64toI64S, round, mkexpr( frB ) ) );
+ assign( frS, unop( Iop_ReinterpI64asD64, mkexpr( tmp ) ) );
+- putDReg( frS_addr, mkexpr( frS ) );
++ putDReg( frS_addr, mkexpr( frS ), guest_is_BE );
+ }
+ break;
+ case 0x322: // dcffix
+@@ -10094,11 +10233,11 @@ static Bool dis_dfp_fmt_conv(UInt theInstr) {
+ flag_rC ? ".":"", frS_addr, frB_addr );
+ frB = newTemp( Ity_D64 );
+ frS = newTemp( Ity_D64 );
+- assign( frB, getDReg( frB_addr ) );
++ assign( frB, getDReg( frB_addr, guest_is_BE ) );
+ assign( frS, binop( Iop_I64StoD64,
+ round,
+ unop( Iop_ReinterpD64asI64, mkexpr( frB ) ) ) );
+- putDReg( frS_addr, mkexpr( frS ) );
++ putDReg( frS_addr, mkexpr( frS ), guest_is_BE );
+ break;
+ }
+
+@@ -10111,7 +10250,7 @@ static Bool dis_dfp_fmt_conv(UInt theInstr) {
+ }
+
+ /* Quad DFP format conversion instructions */
+-static Bool dis_dfp_fmt_convq(UInt theInstr) {
++static Bool dis_dfp_fmt_convq(UInt theInstr, Bool guest_is_BE) {
+ UInt opc2 = ifieldOPClo10( theInstr );
+ UChar frS_addr = ifieldRegDS( theInstr );
+ UChar frB_addr = ifieldRegB( theInstr );
+@@ -10127,9 +10266,9 @@ static Bool dis_dfp_fmt_convq(UInt theInstr) {
+ case 0x102: // dctqpq
+ DIP( "dctqpq%s fr%u,fr%u\n",
+ flag_rC ? ".":"", frS_addr, frB_addr );
+- assign( frB64, getDReg( frB_addr ) );
++ assign( frB64, getDReg( frB_addr, guest_is_BE ) );
+ assign( frS128, unop( Iop_D64toD128, mkexpr( frB64 ) ) );
+- putDReg_pair( frS_addr, mkexpr( frS128 ) );
++ putDReg_pair( frS_addr, mkexpr( frS128 ), guest_is_BE );
+ break;
+ case 0x122: // dctfixq
+ {
+@@ -10137,18 +10276,18 @@ static Bool dis_dfp_fmt_convq(UInt theInstr) {
+
+ DIP( "dctfixq%s fr%u,fr%u\n",
+ flag_rC ? ".":"", frS_addr, frB_addr );
+- assign( frB128, getDReg_pair( frB_addr ) );
++ assign( frB128, getDReg_pair( frB_addr, guest_is_BE ) );
+ assign( tmp, binop( Iop_D128toI64S, round, mkexpr( frB128 ) ) );
+ assign( frS64, unop( Iop_ReinterpI64asD64, mkexpr( tmp ) ) );
+- putDReg( frS_addr, mkexpr( frS64 ) );
++ putDReg( frS_addr, mkexpr( frS64 ), guest_is_BE );
+ }
+ break;
+ case 0x302: //drdpq
+ DIP( "drdpq%s fr%u,fr%u\n",
+ flag_rC ? ".":"", frS_addr, frB_addr );
+- assign( frB128, getDReg_pair( frB_addr ) );
++ assign( frB128, getDReg_pair( frB_addr, guest_is_BE ) );
+ assign( frS64, binop( Iop_D128toD64, round, mkexpr( frB128 ) ) );
+- putDReg( frS_addr, mkexpr( frS64 ) );
++ putDReg( frS_addr, mkexpr( frS64 ), guest_is_BE );
+ break;
+ case 0x322: // dcffixq
+ {
+@@ -10158,11 +10297,11 @@ static Bool dis_dfp_fmt_convq(UInt theInstr) {
+ */
+ DIP( "dcffixq%s fr%u,fr%u\n",
+ flag_rC ? ".":"", frS_addr, frB_addr );
+- assign( frB64, getDReg( frB_addr ) );
++ assign( frB64, getDReg( frB_addr, guest_is_BE ) );
+ assign( frS128, unop( Iop_I64StoD128,
+ unop( Iop_ReinterpD64asI64,
+ mkexpr( frB64 ) ) ) );
+- putDReg_pair( frS_addr, mkexpr( frS128 ) );
++ putDReg_pair( frS_addr, mkexpr( frS128 ), guest_is_BE );
+ break;
+ }
+ }
+@@ -10175,7 +10314,7 @@ static Bool dis_dfp_fmt_convq(UInt theInstr) {
+ return True;
+ }
+
+-static Bool dis_dfp_round( UInt theInstr ) {
++static Bool dis_dfp_round( UInt theInstr, Bool guest_is_BE ) {
+ UChar frS_addr = ifieldRegDS(theInstr);
+ UChar R = IFIELD(theInstr, 16, 1);
+ UChar RMC = IFIELD(theInstr, 9, 2);
+@@ -10201,11 +10340,11 @@ static Bool dis_dfp_round( UInt theInstr ) {
+ * is zero. The result is a floating point number.
+ */
+ /* pass the value of R and RMC in the same field */
+- assign( frB, getDReg( frB_addr ) );
++ assign( frB, getDReg( frB_addr, guest_is_BE ) );
+ assign( frS, binop( Iop_RoundD64toInt,
+ mkU32( ( R << 3 ) | RMC ),
+ mkexpr( frB ) ) );
+- putDReg( frS_addr, mkexpr( frS ) );
++ putDReg( frS_addr, mkexpr( frS ), guest_is_BE );
+ break;
+ default:
+ vex_printf("dis_dfp_round(ppc)(opc2)\n");
+@@ -10220,7 +10359,7 @@ static Bool dis_dfp_round( UInt theInstr ) {
+ return True;
+ }
+
+-static Bool dis_dfp_roundq(UInt theInstr) {
++static Bool dis_dfp_roundq(UInt theInstr, Bool guest_is_BE) {
+ UChar frS_addr = ifieldRegDS( theInstr );
+ UChar frB_addr = ifieldRegB( theInstr );
+ UChar R = IFIELD(theInstr, 16, 1);
+@@ -10242,11 +10381,11 @@ static Bool dis_dfp_roundq(UInt theInstr) {
+ flag_rC ? ".":"", frS_addr, frB_addr );
+
+ /* pass the value of R and RMC in the same field */
+- assign( frB, getDReg_pair( frB_addr ) );
++ assign( frB, getDReg_pair( frB_addr, guest_is_BE ) );
+ assign( frS, binop( Iop_RoundD128toInt,
+ mkU32( ( R << 3 ) | RMC ),
+ mkexpr( frB ) ) );
+- putDReg_pair( frS_addr, mkexpr( frS ) );
++ putDReg_pair( frS_addr, mkexpr( frS ), guest_is_BE );
+ break;
+ default:
+ vex_printf("dis_dfp_roundq(ppc)(opc2)\n");
+@@ -10261,7 +10400,7 @@ static Bool dis_dfp_roundq(UInt theInstr) {
+ return True;
+ }
+
+-static Bool dis_dfp_quantize_sig_rrnd(UInt theInstr) {
++static Bool dis_dfp_quantize_sig_rrnd(UInt theInstr, Bool guest_is_BE) {
+ UInt opc2 = ifieldOPClo8( theInstr );
+ UChar frS_addr = ifieldRegDS( theInstr );
+ UChar frA_addr = ifieldRegA( theInstr );
+@@ -10275,7 +10414,7 @@ static Bool dis_dfp_quantize_sig_rrnd(UInt theInstr) {
+ IRTemp frS = newTemp( Ity_D64 );
+ Bool clear_CR1 = True;
+
+- assign( frB, getDReg( frB_addr ) );
++ assign( frB, getDReg( frB_addr, guest_is_BE ) );
+
+ switch (opc2) {
+ case 0x43: // dquai
+@@ -10317,7 +10456,7 @@ static Bool dis_dfp_quantize_sig_rrnd(UInt theInstr) {
+ case 0x3: // dqua
+ DIP( "dqua%s fr%u,fr%u,fr%u\n",
+ flag_rC ? ".":"", frS_addr, frA_addr, frB_addr );
+- assign( frA, getDReg( frA_addr ) );
++ assign( frA, getDReg( frA_addr, guest_is_BE ) );
+ assign( frS, triop( Iop_QuantizeD64,
+ mkU32( RMC ),
+ mkexpr( frA ),
+@@ -10329,7 +10468,7 @@ static Bool dis_dfp_quantize_sig_rrnd(UInt theInstr) {
+
+ DIP( "drrnd%s fr%u,fr%u,fr%u\n",
+ flag_rC ? ".":"", frS_addr, frA_addr, frB_addr );
+- assign( frA, getDReg( frA_addr ) );
++ assign( frA, getDReg( frA_addr, guest_is_BE ) );
+ /* Iop_64to8 not supported in 32 bit mode, do it in two steps. */
+ assign( tmp, unop( Iop_32to8,
+ unop( Iop_64to32,
+@@ -10345,7 +10484,7 @@ static Bool dis_dfp_quantize_sig_rrnd(UInt theInstr) {
+ vex_printf("dis_dfp_quantize_sig_rrnd(ppc)(opc2)\n");
+ return False;
+ }
+- putDReg( frS_addr, mkexpr( frS ) );
++ putDReg( frS_addr, mkexpr( frS ), guest_is_BE );
+
+ if (flag_rC && clear_CR1) {
+ putCR321( 1, mkU8( 0 ) );
+@@ -10355,7 +10494,7 @@ static Bool dis_dfp_quantize_sig_rrnd(UInt theInstr) {
+ return True;
+ }
+
+-static Bool dis_dfp_quantize_sig_rrndq(UInt theInstr) {
++static Bool dis_dfp_quantize_sig_rrndq(UInt theInstr, Bool guest_is_BE) {
+ UInt opc2 = ifieldOPClo8( theInstr );
+ UChar frS_addr = ifieldRegDS( theInstr );
+ UChar frA_addr = ifieldRegA( theInstr );
+@@ -10369,7 +10508,7 @@ static Bool dis_dfp_quantize_sig_rrndq(UInt theInstr) {
+ IRTemp frS = newTemp( Ity_D128 );
+ Bool clear_CR1 = True;
+
+- assign( frB, getDReg_pair( frB_addr ) );
++ assign( frB, getDReg_pair( frB_addr, guest_is_BE ) );
+
+ switch (opc2) {
+ case 0x43: // dquaiq
+@@ -10412,7 +10551,7 @@ static Bool dis_dfp_quantize_sig_rrndq(UInt theInstr) {
+ case 0x3: // dquaq
+ DIP( "dquaiq%s fr%u,fr%u,fr%u\n",
+ flag_rC ? ".":"", frS_addr, frA_addr, frB_addr );
+- assign( frA, getDReg_pair( frA_addr ) );
++ assign( frA, getDReg_pair( frA_addr, guest_is_BE ) );
+ assign( frS, triop( Iop_QuantizeD128,
+ mkU32( RMC ),
+ mkexpr( frA ),
+@@ -10424,7 +10563,7 @@ static Bool dis_dfp_quantize_sig_rrndq(UInt theInstr) {
+
+ DIP( "drrndq%s fr%u,fr%u,fr%u\n",
+ flag_rC ? ".":"", frS_addr, frA_addr, frB_addr );
+- assign( frA, getDReg_pair( frA_addr ) );
++ assign( frA, getDReg_pair( frA_addr, guest_is_BE ) );
+ assign( tmp, unop( Iop_32to8,
+ unop( Iop_64to32,
+ unop( Iop_ReinterpD64asI64,
+@@ -10440,7 +10579,7 @@ static Bool dis_dfp_quantize_sig_rrndq(UInt theInstr) {
+ vex_printf("dis_dfp_quantize_sig_rrndq(ppc)(opc2)\n");
+ return False;
+ }
+- putDReg_pair( frS_addr, mkexpr( frS ) );
++ putDReg_pair( frS_addr, mkexpr( frS ), guest_is_BE );
+
+ if (flag_rC && clear_CR1) {
+ putCR321( 1, mkU8( 0 ) );
+@@ -10450,7 +10589,7 @@ static Bool dis_dfp_quantize_sig_rrndq(UInt theInstr) {
+ return True;
+ }
+
+-static Bool dis_dfp_extract_insert(UInt theInstr) {
++static Bool dis_dfp_extract_insert(UInt theInstr, Bool guest_is_BE) {
+ UInt opc2 = ifieldOPClo10( theInstr );
+ UChar frS_addr = ifieldRegDS( theInstr );
+ UChar frA_addr = ifieldRegA( theInstr );
+@@ -10463,8 +10602,8 @@ static Bool dis_dfp_extract_insert(UInt theInstr) {
+ IRTemp frS = newTemp( Ity_D64 );
+ IRTemp tmp = newTemp( Ity_I64 );
+
+- assign( frA, getDReg( frA_addr ) );
+- assign( frB, getDReg( frB_addr ) );
++ assign( frA, getDReg( frA_addr, guest_is_BE ) );
++ assign( frB, getDReg( frB_addr, guest_is_BE ) );
+
+ switch (opc2) {
+ case 0x162: // dxex
+@@ -10486,7 +10625,7 @@ static Bool dis_dfp_extract_insert(UInt theInstr) {
+ return False;
+ }
+
+- putDReg( frS_addr, mkexpr( frS ) );
++ putDReg( frS_addr, mkexpr( frS ), guest_is_BE );
+
+ if (flag_rC && clear_CR1) {
+ putCR321( 1, mkU8( 0 ) );
+@@ -10496,7 +10635,7 @@ static Bool dis_dfp_extract_insert(UInt theInstr) {
+ return True;
+ }
+
+-static Bool dis_dfp_extract_insertq(UInt theInstr) {
++static Bool dis_dfp_extract_insertq(UInt theInstr, Bool guest_is_BE) {
+ UInt opc2 = ifieldOPClo10( theInstr );
+ UChar frS_addr = ifieldRegDS( theInstr );
+ UChar frA_addr = ifieldRegA( theInstr );
+@@ -10510,7 +10649,7 @@ static Bool dis_dfp_extract_insertq(UInt theInstr) {
+ IRTemp tmp = newTemp( Ity_I64 );
+ Bool clear_CR1 = True;
+
+- assign( frB, getDReg_pair( frB_addr ) );
++ assign( frB, getDReg_pair( frB_addr, guest_is_BE ) );
+
+ switch (opc2) {
+ case 0x162: // dxexq
+@@ -10522,16 +10661,16 @@ static Bool dis_dfp_extract_insertq(UInt theInstr) {
+ */
+ assign( tmp, unop( Iop_ExtractExpD128, mkexpr( frB ) ) );
+ assign( frS64, unop( Iop_ReinterpI64asD64, mkexpr( tmp ) ) );
+- putDReg( frS_addr, mkexpr( frS64 ) );
++ putDReg( frS_addr, mkexpr( frS64), guest_is_BE );
+ break;
+ case 0x362: // diexq
+ DIP( "diexq%s fr%u,fr%u,fr%u\n",
+ flag_rC ? ".":"", frS_addr, frA_addr, frB_addr );
+- assign( frA, getDReg( frA_addr ) );
++ assign( frA, getDReg( frA_addr, guest_is_BE ) );
+ assign( frS, binop( Iop_InsertExpD128,
+ unop( Iop_ReinterpD64asI64, mkexpr( frA ) ),
+ mkexpr( frB ) ) );
+- putDReg_pair( frS_addr, mkexpr( frS ) );
++ putDReg_pair( frS_addr, mkexpr( frS ), guest_is_BE );
+ break;
+ default:
+ vex_printf("dis_dfp_extract_insertq(ppc)(opc2)\n");
+@@ -10547,7 +10686,7 @@ static Bool dis_dfp_extract_insertq(UInt theInstr) {
+ }
+
+ /* DFP 64-bit comparison instructions */
+-static Bool dis_dfp_compare(UInt theInstr) {
++static Bool dis_dfp_compare(UInt theInstr, Bool guest_is_BE) {
+ /* X-Form */
+ UChar crfD = toUChar( IFIELD( theInstr, 23, 3 ) ); // AKA BF
+ UChar frA_addr = ifieldRegA( theInstr );
+@@ -10568,8 +10707,8 @@ static Bool dis_dfp_compare(UInt theInstr) {
+ frA = newTemp( Ity_D64 );
+ frB = newTemp( Ity_D64 );
+
+- assign( frA, getDReg( frA_addr ) );
+- assign( frB, getDReg( frB_addr ) );
++ assign( frA, getDReg( frA_addr, guest_is_BE ) );
++ assign( frB, getDReg( frB_addr, guest_is_BE ) );
+
+ assign( ccIR, binop( Iop_CmpD64, mkexpr( frA ), mkexpr( frB ) ) );
+ break;
+@@ -10578,8 +10717,8 @@ static Bool dis_dfp_compare(UInt theInstr) {
+ frA = newTemp( Ity_D128 );
+ frB = newTemp( Ity_D128 );
+
+- assign( frA, getDReg_pair( frA_addr ) );
+- assign( frB, getDReg_pair( frB_addr ) );
++ assign( frA, getDReg_pair( frA_addr, guest_is_BE ) );
++ assign( frB, getDReg_pair( frB_addr, guest_is_BE ) );
+ assign( ccIR, binop( Iop_CmpD128, mkexpr( frA ), mkexpr( frB ) ) );
+ break;
+ default:
+@@ -10621,7 +10760,7 @@ static Bool dis_dfp_compare(UInt theInstr) {
+ }
+
+ /* Test class/group/exponent/significance instructions. */
+-static Bool dis_dfp_exponent_test ( UInt theInstr )
++static Bool dis_dfp_exponent_test ( UInt theInstr, Bool guest_is_BE )
+ {
+ UChar frA_addr = ifieldRegA( theInstr );
+ UChar frB_addr = ifieldRegB( theInstr );
+@@ -10655,8 +10794,8 @@ static Bool dis_dfp_exponent_test ( UInt theInstr )
+ switch (opc1) {
+ case 0x3b: // dtstex Extended instruction setup
+ DIP("dtstex %u,r%u,r%d\n", crfD, frA_addr, frB_addr);
+- assign( frA, getDReg( frA_addr ) );
+- assign( frB, getDReg( frB_addr ) );
++ assign( frA, getDReg( frA_addr , guest_is_BE) );
++ assign( frB, getDReg( frB_addr , guest_is_BE) );
+ assign( gfield_mask, mkU32( DFP_G_FIELD_LONG_MASK ) );
+ assign(exponent_A, unop( Iop_64to32,
+ unop( Iop_ExtractExpD64,
+@@ -10668,8 +10807,8 @@ static Bool dis_dfp_exponent_test ( UInt theInstr )
+
+ case 0x3F: // dtstexq Quad instruction setup
+ DIP("dtstexq %u,r%u,r%d\n", crfD, frA_addr, frB_addr);
+- assign( frA128, getDReg_pair( frA_addr ) );
+- assign( frB128, getDReg_pair( frB_addr ) );
++ assign( frA128, getDReg_pair( frA_addr, guest_is_BE ) );
++ assign( frB128, getDReg_pair( frB_addr, guest_is_BE ) );
+ assign( frA, unop( Iop_D128HItoD64, mkexpr( frA128 ) ) );
+ assign( frB, unop( Iop_D128HItoD64, mkexpr( frB128 ) ) );
+ assign( gfield_mask, mkU32( DFP_G_FIELD_EXTND_MASK ) );
+@@ -10813,7 +10952,7 @@ static Bool dis_dfp_exponent_test ( UInt theInstr )
+ }
+
+ /* Test class/group/exponent/significance instructions. */
+-static Bool dis_dfp_class_test ( UInt theInstr )
++static Bool dis_dfp_class_test ( UInt theInstr, Bool guest_is_BE )
+ {
+ UChar frA_addr = ifieldRegA( theInstr );
+ IRTemp frA = newTemp( Ity_D64 );
+@@ -10875,7 +11014,7 @@ static Bool dis_dfp_class_test ( UInt theInstr )
+ * LT | 0x01
+ */
+
+- assign( frA, getDReg( frA_addr ) );
++ assign( frA, getDReg( frA_addr, guest_is_BE ) );
+ assign( frAI64_hi, unop( Iop_ReinterpD64asI64, mkexpr( frA ) ) );
+
+ assign( abs_frA, unop( Iop_ReinterpI64asD64,
+@@ -10928,14 +11067,14 @@ static Bool dis_dfp_class_test ( UInt theInstr )
+ * two instructions
+ */
+ assign( frAI64_lo, unop( Iop_ReinterpD64asI64,
+- getDReg( frA_addr+1 ) ) );
++ getDReg( frA_addr+1, guest_is_BE ) ) );
+
+ assign( gfield_mask, mkU32( DFP_G_FIELD_EXTND_MASK ) );
+ max_exp = DFP_EXTND_EXP_MAX;
+ min_exp = DFP_EXTND_EXP_MIN;
+ assign( exponent, unop( Iop_64to32,
+ unop( Iop_ExtractExpD128,
+- getDReg_pair( frA_addr) ) ) );
++ getDReg_pair( frA_addr, guest_is_BE ) ) ) );
+
+ /* create quand exponent for minimum normal number */
+ assign( exp_min_normal, mkU64( 6176 - 6143 ) );
+@@ -10957,13 +11096,13 @@ static Bool dis_dfp_class_test ( UInt theInstr )
+ unop( Iop_ReinterpD64asI64,
+ mkexpr( frA ) ),
+ mkU64( 0x7FFFFFFFFFFFFFFFULL ) ) ),
+- getDReg( frA_addr+1 ) ),
++ getDReg( frA_addr+1, guest_is_BE ) ),
+ mkexpr( min_subnormalD128 ) ) );
+ assign( ccIR_zero,
+ binop( Iop_CmpD128,
+ binop( Iop_D64HLtoD128,
+ mkexpr( abs_frA ),
+- getDReg( frA_addr+1 ) ),
++ getDReg( frA_addr+1, guest_is_BE ) ),
+ unop( Iop_D64toD128,
+ unop( Iop_ReinterpI64asD64,
+ mkU64( 0x0ULL ) ) ) ) );
+@@ -11256,7 +11395,7 @@ static Bool dis_dfp_class_test ( UInt theInstr )
+ return True;
+ }
+
+-static Bool dis_dfp_bcd(UInt theInstr) {
++static Bool dis_dfp_bcd(UInt theInstr, Bool guest_is_BE) {
+ UInt opc2 = ifieldOPClo10( theInstr );
+ ULong sp = IFIELD(theInstr, 19, 2);
+ ULong s = IFIELD(theInstr, 20, 1);
+@@ -11273,7 +11412,7 @@ static Bool dis_dfp_bcd(UInt theInstr) {
+ IRTemp dbcd_l = newTemp( Ity_I32 );
+ IRTemp lmd = newTemp( Ity_I32 );
+
+- assign( frB, getDReg( frB_addr ) );
++ assign( frB, getDReg( frB_addr, guest_is_BE ) );
+ assign( frBI64, unop( Iop_ReinterpD64asI64, mkexpr( frB ) ) );
+
+ switch ( opc2 ) {
+@@ -11352,7 +11491,8 @@ static Bool dis_dfp_bcd(UInt theInstr) {
+ mkU8( 4 ) ) ) ) );
+ }
+
+- putDReg( frT_addr, unop( Iop_ReinterpI64asD64, mkexpr( result ) ) );
++ putDReg( frT_addr, unop( Iop_ReinterpI64asD64, mkexpr( result ) ),
++ guest_is_BE );
+ break;
+
+ case 0x342: // denbcd DFP Encode BCD to DPD
+@@ -11506,7 +11646,7 @@ static Bool dis_dfp_bcd(UInt theInstr) {
+ binop( Iop_And32,
+ mkU32( 0x0 ),
+ mkexpr( invalid_mask ) ) ) ) ) );
+- putDReg( frT_addr, mkexpr( resultD64 ) );
++ putDReg( frT_addr, mkexpr( resultD64 ), guest_is_BE );
+ }
+ break;
+ default:
+@@ -11516,7 +11656,7 @@ static Bool dis_dfp_bcd(UInt theInstr) {
+ return True;
+ }
+
+-static Bool dis_dfp_bcdq( UInt theInstr )
++static Bool dis_dfp_bcdq( UInt theInstr, Bool guest_is_BE )
+ {
+ UInt opc2 = ifieldOPClo10( theInstr );
+ ULong sp = IFIELD(theInstr, 19, 2);
+@@ -11532,8 +11672,8 @@ static Bool dis_dfp_bcdq( UInt theInstr )
+ IRTemp result_hi = newTemp( Ity_I64 );
+ IRTemp result_lo = newTemp( Ity_I64 );
+
+- assign( frB_hi, getDReg( frB_addr ) );
+- assign( frB_lo, getDReg( frB_addr + 1 ) );
++ assign( frB_hi, getDReg( frB_addr, guest_is_BE ) );
++ assign( frB_lo, getDReg( frB_addr + 1, guest_is_BE ) );
+ assign( frBI64_hi, unop( Iop_ReinterpD64asI64, mkexpr( frB_hi ) ) );
+ assign( frBI64_lo, unop( Iop_ReinterpD64asI64, mkexpr( frB_lo ) ) );
+
+@@ -11647,9 +11787,11 @@ static Bool dis_dfp_bcdq( UInt theInstr )
+ mkexpr( sign ) ) ) );
+ }
+
+- putDReg( frT_addr, unop( Iop_ReinterpI64asD64, mkexpr( result_hi ) ) );
++ putDReg( frT_addr, unop( Iop_ReinterpI64asD64, mkexpr( result_hi ) ),
++ guest_is_BE);
+ putDReg( frT_addr + 1,
+- unop( Iop_ReinterpI64asD64, mkexpr( result_lo ) ) );
++ unop( Iop_ReinterpI64asD64, mkexpr( result_lo ) ),
++ guest_is_BE);
+ }
+ break;
+ case 0x342: // denbcdq DFP Encode BCD to DPD
+@@ -11912,9 +12054,11 @@ static Bool dis_dfp_bcdq( UInt theInstr )
+ mkU32( 0x0 ),
+ mkexpr( invalid_mask ) ) ) ) );
+
+- putDReg( frT_addr, unop( Iop_ReinterpI64asD64, mkexpr( result_hi ) ) );
++ putDReg( frT_addr, unop( Iop_ReinterpI64asD64, mkexpr( result_hi ) ),
++ guest_is_BE);
+ putDReg( frT_addr + 1,
+- unop( Iop_ReinterpI64asD64, mkexpr( result_lo ) ) );
++ unop( Iop_ReinterpI64asD64, mkexpr( result_lo ) ),
++ guest_is_BE );
+
+ }
+ break;
+@@ -11925,7 +12069,7 @@ static Bool dis_dfp_bcdq( UInt theInstr )
+ return True;
+ }
+
+-static Bool dis_dfp_significant_digits( UInt theInstr )
++static Bool dis_dfp_significant_digits( UInt theInstr, Bool guest_is_BE )
+ {
+ UChar frA_addr = ifieldRegA( theInstr );
+ UChar frB_addr = ifieldRegB( theInstr );
+@@ -11944,7 +12088,7 @@ static Bool dis_dfp_significant_digits( UInt theInstr )
+ IRTemp KisZero_false_mask = newTemp( Ity_I32 );
+
+ /* Get the reference singificance stored in frA */
+- assign( frA, getDReg( frA_addr ) );
++ assign( frA, getDReg( frA_addr, guest_is_BE ) );
+
+ /* Convert from 64 bit to 8 bits in two steps. The Iop_64to8 is not
+ * supported in 32-bit mode.
+@@ -11967,7 +12111,7 @@ static Bool dis_dfp_significant_digits( UInt theInstr )
+
+ DIP( "dtstsf %u,r%u,r%u\n", crfD, frA_addr, frB_addr );
+
+- assign( frB, getDReg( frB_addr ) );
++ assign( frB, getDReg( frB_addr, guest_is_BE ) );
+ assign( frBI64, unop( Iop_ReinterpD64asI64, mkexpr( frB ) ) );
+
+ /* Get the BCD string for the value stored in a series of I32 values.
+@@ -12007,8 +12151,8 @@ static Bool dis_dfp_significant_digits( UInt theInstr )
+
+ DIP( "dtstsfq %u,r%u,r%u\n", crfD, frA_addr, frB_addr );
+
+- assign( frB_hi, getDReg( frB_addr ) );
+- assign( frB_lo, getDReg( frB_addr + 1 ) );
++ assign( frB_hi, getDReg( frB_addr, guest_is_BE ) );
++ assign( frB_lo, getDReg( frB_addr + 1, guest_is_BE ) );
+
+ assign( frBI64_hi, unop( Iop_ReinterpD64asI64, mkexpr( frB_hi ) ) );
+ assign( frBI64_lo, unop( Iop_ReinterpD64asI64, mkexpr( frB_lo ) ) );
+@@ -14767,8 +14911,9 @@ dis_vvec_cmp( UInt theInstr, UInt opc2 )
+ * Miscellaneous VSX Scalar Instructions
+ */
+ static Bool
+-dis_vxs_misc( UInt theInstr, UInt opc2 )
++dis_vxs_misc( UInt theInstr, UInt opc2, Bool guest_is_BE )
+ {
++#define VG_PPC_SIGN_MASK 0x7fffffffffffffffULL
+ /* XX3-Form and XX2-Form */
+ UChar opc1 = ifieldOPC( theInstr );
+ UChar XT = ifieldRegXT ( theInstr );
+@@ -14795,7 +14940,20 @@ dis_vxs_misc( UInt theInstr, UInt opc2 )
+ {
+ /* Move abs val of dw 0 of VSX[XB] to dw 0 of VSX[XT]. */
+ IRTemp absVal = newTemp(Ity_V128);
+- assign(absVal, binop(Iop_ShrV128, binop(Iop_ShlV128, mkexpr(vB), mkU8(1)), mkU8(1)));
++ if (!guest_is_BE) {
++ IRTemp hi64 = newTemp(Ity_I64);
++ IRTemp lo64 = newTemp(Ity_I64);
++ assign( hi64, unop( Iop_V128HIto64, mkexpr(vB) ) );
++ assign( lo64, unop( Iop_V128to64, mkexpr(vB) ) );
++ assign( absVal, binop( Iop_64HLtoV128,
++ binop( Iop_And64, mkexpr(hi64),
++ mkU64(VG_PPC_SIGN_MASK) ),
++ mkexpr(lo64) ) );
++ } else {
++ assign(absVal, binop(Iop_ShrV128,
++ binop(Iop_ShlV128, mkexpr(vB),
++ mkU8(1)), mkU8(1)));
++ }
+ DIP("xsabsdp v%d,v%d\n", (UInt)XT, (UInt)XB);
+ putVSReg(XT, mkexpr(absVal));
+ break;
+@@ -14803,51 +14961,73 @@ dis_vxs_misc( UInt theInstr, UInt opc2 )
+ case 0x2C0: // xscpsgndp
+ {
+ /* Scalar copy sign double-precision */
+- IRTemp vecA_signbit = newTemp(Ity_V128);
+- IRTemp vecB_no_signbit = newTemp(Ity_V128);
++ IRTemp vecA_signed = newTemp(Ity_I64);
++ IRTemp vecB_unsigned = newTemp(Ity_I64);
+ IRTemp vec_result = newTemp(Ity_V128);
+ DIP("xscpsgndp v%d,v%d v%d\n", (UInt)XT, (UInt)XA, (UInt)XB);
+- assign( vecB_no_signbit, binop( Iop_ShrV128, binop( Iop_ShlV128,
+- mkexpr( vB ),
+- mkU8( 1 ) ),
+- mkU8( 1 ) ) );
+- assign( vecA_signbit, binop( Iop_ShlV128, binop( Iop_ShrV128,
+- mkexpr( vA ),
+- mkU8( 127 ) ),
+- mkU8( 127 ) ) );
+- assign( vec_result, binop( Iop_OrV128, mkexpr(vecA_signbit), mkexpr( vecB_no_signbit ) ) );
++ assign( vecA_signed, binop( Iop_And64,
++ unop( Iop_V128HIto64,
++ mkexpr(vA)),
++ mkU64(~VG_PPC_SIGN_MASK) ) );
++ assign( vecB_unsigned, binop( Iop_And64,
++ unop( Iop_V128HIto64,
++ mkexpr(vB) ),
++ mkU64(VG_PPC_SIGN_MASK) ) );
++ assign( vec_result, binop( Iop_64HLtoV128,
++ binop( Iop_Or64,
++ mkexpr(vecA_signed),
++ mkexpr(vecB_unsigned) ),
++ mkU64(0x0ULL)));
+ putVSReg(XT, mkexpr(vec_result));
+ break;
+ }
+ case 0x2D2: // xsnabsdp
+ {
+ /* Scalar negative absolute value double-precision */
+- IRTemp vec_neg_signbit = newTemp(Ity_V128);
++ IRTemp BHi_signed = newTemp(Ity_I64);
+ DIP("xsnabsdp v%d,v%d\n", (UInt)XT, (UInt)XB);
+- assign( vec_neg_signbit, unop( Iop_NotV128, binop( Iop_ShrV128,
+- mkV128( 0xffff ),
+- mkU8( 1 ) ) ) );
+- putVSReg(XT, binop(Iop_OrV128, mkexpr(vec_neg_signbit), mkexpr(vB)));
++ assign( BHi_signed, binop( Iop_Or64,
++ unop( Iop_V128HIto64,
++ mkexpr(vB) ),
++ mkU64(~VG_PPC_SIGN_MASK) ) );
++ putVSReg(XT, binop( Iop_64HLtoV128,
++ mkexpr(BHi_signed), mkU64(0x0ULL) ) );
+ break;
+ }
+ case 0x2F2: // xsnegdp
+ {
+ /* Scalar negate double-precision */
+- IRTemp vecB_no_signbit = newTemp(Ity_V128);
+- IRTemp vecB_signbit_comp = newTemp(Ity_V128);
++ IRTemp BHi_signed = newTemp(Ity_I64);
++ IRTemp BHi_unsigned = newTemp(Ity_I64);
++ IRTemp BHi_negated = newTemp(Ity_I64);
++ IRTemp BHi_negated_signbit = newTemp(Ity_I1);
++ IRTemp vec_result = newTemp(Ity_V128);
+ DIP("xsnabsdp v%d,v%d\n", (UInt)XT, (UInt)XB);
+- assign( vecB_no_signbit, binop( Iop_ShrV128, binop( Iop_ShlV128,
+- mkexpr( vB ),
+- mkU8( 1 ) ),
+- mkU8( 1 ) ) );
+- assign( vecB_signbit_comp, binop( Iop_ShlV128,
+- unop( Iop_NotV128,
+- binop( Iop_ShrV128,
+- mkexpr( vB ),
+- mkU8( 127 ) ) ),
+- mkU8( 127 ) ) );
+- putVSReg( XT, binop( Iop_OrV128, mkexpr( vecB_no_signbit ),
+- mkexpr( vecB_signbit_comp ) ) );
++ assign( BHi_signed, unop( Iop_V128HIto64, mkexpr(vB) ) );
++ assign( BHi_unsigned, binop( Iop_And64, mkexpr(BHi_signed),
++ mkU64(VG_PPC_SIGN_MASK) ) );
++ assign( BHi_negated_signbit,
++ unop( Iop_Not1,
++ unop( Iop_32to1,
++ binop( Iop_Shr32,
++ unop( Iop_64HIto32,
++ binop( Iop_And64,
++ mkexpr(BHi_signed),
++ mkU64(~VG_PPC_SIGN_MASK) )
++ ),
++ mkU8(31) ) ) ) );
++ assign( BHi_negated,
++ binop( Iop_Or64,
++ binop( Iop_32HLto64,
++ binop( Iop_Shl32,
++ unop( Iop_1Uto32,
++ mkexpr(BHi_negated_signbit) ),
++ mkU8(31) ),
++ mkU32(0) ),
++ mkexpr(BHi_unsigned) ) );
++ assign( vec_result, binop( Iop_64HLtoV128, mkexpr(BHi_negated),
++ mkU64(0x0ULL)));
++ putVSReg( XT, mkexpr(vec_result));
+ break;
+ }
+ case 0x280: // xsmaxdp (VSX Scalar Maximum Double-Precision)
+@@ -15048,7 +15228,7 @@ dis_vx_logic ( UInt theInstr, UInt opc2 )
+ * NOTE: VSX supports word-aligned storage access.
+ */
+ static Bool
+-dis_vx_load ( UInt theInstr )
++dis_vx_load ( UInt theInstr, Bool guest_is_BE )
+ {
+ /* XX1-Form */
+ UChar opc1 = ifieldOPC( theInstr );
+@@ -15072,7 +15252,7 @@ dis_vx_load ( UInt theInstr )
+ {
+ IRExpr * exp;
+ DIP("lxsiwzx %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr);
+- exp = unop( Iop_64HIto32, load( Ity_I64, mkexpr( EA ) ) );
++ exp = unop( Iop_64HIto32, load( Ity_I64, mkexpr( EA ), guest_is_BE ) );
+ putVSReg( XT, binop( Iop_64HLtoV128,
+ unop( Iop_32Uto64, exp),
+ mkU64(0) ) );
+@@ -15082,7 +15262,7 @@ dis_vx_load ( UInt theInstr )
+ {
+ IRExpr * exp;
+ DIP("lxsiwax %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr);
+- exp = unop( Iop_64HIto32, load( Ity_I64, mkexpr( EA ) ) );
++ exp = unop( Iop_64HIto32, load( Ity_I64, mkexpr( EA ), guest_is_BE ) );
+ putVSReg( XT, binop( Iop_64HLtoV128,
+ unop( Iop_32Sto64, exp),
+ mkU64(0) ) );
+@@ -15099,7 +15279,7 @@ dis_vx_load ( UInt theInstr )
+ exp = unop( Iop_ReinterpF64asI64,
+ unop( Iop_F32toF64,
+ unop( Iop_ReinterpI32asF32,
+- load( Ity_I32, mkexpr( EA ) ) ) ) );
++ load( Ity_I32, mkexpr( EA ), guest_is_BE ) ) ) );
+
+ putVSReg( XT, binop( Iop_64HLtoV128, exp, mkU64( 0 ) ) );
+ break;
+@@ -15108,7 +15288,7 @@ dis_vx_load ( UInt theInstr )
+ {
+ IRExpr * exp;
+ DIP("lxsdx %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr);
+- exp = load( Ity_I64, mkexpr( EA ) );
++ exp = load( Ity_I64, mkexpr( EA ), guest_is_BE );
+ // We need to pass an expression of type Ity_V128 with putVSReg, but the load
+ // we just performed is only a DW. But since the contents of VSR[XT] element 1
+ // are undefined after this operation, we can just do a splat op.
+@@ -15122,10 +15302,10 @@ dis_vx_load ( UInt theInstr )
+ ULong ea_off = 8;
+ IRExpr* high_addr;
+ DIP("lxvd2x %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr);
+- high = load( Ity_I64, mkexpr( EA ) );
++ high = load( Ity_I64, mkexpr( EA ), guest_is_BE );
+ high_addr = binop( addOp, mkexpr( EA ), ty == Ity_I64 ? mkU64( ea_off )
+ : mkU32( ea_off ) );
+- low = load( Ity_I64, high_addr );
++ low = load( Ity_I64, high_addr, guest_is_BE );
+ putVSReg( XT, binop( Iop_64HLtoV128, high, low ) );
+ break;
+ }
+@@ -15133,7 +15313,7 @@ dis_vx_load ( UInt theInstr )
+ {
+ IRTemp data = newTemp(Ity_I64);
+ DIP("lxvdsx %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr);
+- assign( data, load( Ity_I64, mkexpr( EA ) ) );
++ assign( data, load( Ity_I64, mkexpr( EA ), guest_is_BE ) );
+ putVSReg( XT, binop( Iop_64HLtoV128, mkexpr( data ), mkexpr( data ) ) );
+ break;
+ }
+@@ -15144,19 +15324,19 @@ dis_vx_load ( UInt theInstr )
+ IRExpr* irx_addr;
+
+ DIP("lxvw4x %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr);
+- t3 = load( Ity_I32, mkexpr( EA ) );
++ t3 = load( Ity_I32, mkexpr( EA ), guest_is_BE );
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+- t2 = load( Ity_I32, irx_addr );
++ t2 = load( Ity_I32, irx_addr, guest_is_BE );
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+- t1 = load( Ity_I32, irx_addr );
++ t1 = load( Ity_I32, irx_addr, guest_is_BE );
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+- t0 = load( Ity_I32, irx_addr );
++ t0 = load( Ity_I32, irx_addr, guest_is_BE );
+ putVSReg( XT, binop( Iop_64HLtoV128, binop( Iop_32HLto64, t3, t2 ),
+ binop( Iop_32HLto64, t1, t0 ) ) );
+ break;
+@@ -15173,7 +15353,7 @@ dis_vx_load ( UInt theInstr )
+ * NOTE: VSX supports word-aligned storage access.
+ */
+ static Bool
+-dis_vx_store ( UInt theInstr )
++dis_vx_store ( UInt theInstr, Bool guest_is_BE )
+ {
+ /* XX1-Form */
+ UChar opc1 = ifieldOPC( theInstr );
+@@ -15204,7 +15384,7 @@ dis_vx_store ( UInt theInstr )
+ DIP("stxsiwx %d,r%u,r%u\n", (UInt)XS, rA_addr, rB_addr);
+ high64 = unop( Iop_V128HIto64, mkexpr( vS ) );
+ low32 = unop( Iop_64to32, high64 );
+- store( mkexpr( EA ), low32 );
++ store( mkexpr( EA ), low32, guest_is_BE );
+ break;
+ }
+ case 0x28C:
+@@ -15217,7 +15397,7 @@ dis_vx_store ( UInt theInstr )
+ assign(val32, unop( Iop_ReinterpF32asI32,
+ unop( Iop_TruncF64asF32,
+ mkexpr(high64) ) ) );
+- store( mkexpr( EA ), mkexpr( val32 ) );
++ store( mkexpr( EA ), mkexpr( val32 ), guest_is_BE );
+ break;
+ }
+ case 0x2CC:
+@@ -15225,7 +15405,7 @@ dis_vx_store ( UInt theInstr )
+ IRExpr * high64;
+ DIP("stxsdx %d,r%u,r%u\n", (UInt)XS, rA_addr, rB_addr);
+ high64 = unop( Iop_V128HIto64, mkexpr( vS ) );
+- store( mkexpr( EA ), high64 );
++ store( mkexpr( EA ), high64, guest_is_BE );
+ break;
+ }
+ case 0x3CC:
+@@ -15234,9 +15414,10 @@ dis_vx_store ( UInt theInstr )
+ DIP("stxvd2x %d,r%u,r%u\n", (UInt)XS, rA_addr, rB_addr);
+ high64 = unop( Iop_V128HIto64, mkexpr( vS ) );
+ low64 = unop( Iop_V128to64, mkexpr( vS ) );
+- store( mkexpr( EA ), high64 );
++ store( mkexpr( EA ), high64, guest_is_BE );
+ store( binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+- ty == Ity_I64 ? mkU64( 8 ) : mkU32( 8 ) ), low64 );
++ ty == Ity_I64 ? mkU64( 8 ) : mkU32( 8 ) ), low64,
++ guest_is_BE );
+ break;
+ }
+ case 0x38C:
+@@ -15252,19 +15433,20 @@ dis_vx_store ( UInt theInstr )
+ // quad-word aligned. Therefore, do 4 individual word-size stores.
+ assign( hi64, unop( Iop_V128HIto64, mkexpr( vS ) ) );
+ assign( lo64, unop( Iop_V128to64, mkexpr( vS ) ) );
+- store( mkexpr( EA ), unop( Iop_64HIto32, mkexpr( hi64 ) ) );
++ store( mkexpr( EA ), unop( Iop_64HIto32, mkexpr( hi64 ) ),
++ guest_is_BE );
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+- store( irx_addr, unop( Iop_64to32, mkexpr( hi64 ) ) );
++ store( irx_addr, unop( Iop_64to32, mkexpr( hi64 ) ), guest_is_BE );
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+- store( irx_addr, unop( Iop_64HIto32, mkexpr( lo64 ) ) );
++ store( irx_addr, unop( Iop_64HIto32, mkexpr( lo64 ) ), guest_is_BE );
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+- store( irx_addr, unop( Iop_64to32, mkexpr( lo64 ) ) );
++ store( irx_addr, unop( Iop_64to32, mkexpr( lo64 ) ), guest_is_BE );
+
+ break;
+ }
+@@ -15399,7 +15581,7 @@ dis_vx_permute_misc( UInt theInstr, UInt opc2 )
+ /*
+ AltiVec Load Instructions
+ */
+-static Bool dis_av_load ( VexAbiInfo* vbi, UInt theInstr )
++static Bool dis_av_load ( VexAbiInfo* vbi, UInt theInstr, Bool guest_is_BE )
+ {
+ /* X-Form */
+ UChar opc1 = ifieldOPC(theInstr);
+@@ -15426,24 +15608,39 @@ static Bool dis_av_load ( VexAbiInfo* vbi, UInt theInstr )
+ case 0x006: { // lvsl (Load Vector for Shift Left, AV p123)
+ IRDirty* d;
+ UInt vD_off = vectorGuestRegOffset(vD_addr);
+- IRExpr** args = mkIRExprVec_4(
++ IRExpr** args_be = mkIRExprVec_5(
++ IRExpr_BBPTR(),
++ mkU32(vD_off),
++ binop(Iop_And32, mkNarrowTo32(ty, mkexpr(EA)),
++ mkU32(0xF)),
++ mkU32(0)/*left*/,
++ mkU32(1)/*Big Endian*/);
++ IRExpr** args_le = mkIRExprVec_5(
+ IRExpr_BBPTR(),
+- mkU32(vD_off),
++ mkU32(vD_off),
+ binop(Iop_And32, mkNarrowTo32(ty, mkexpr(EA)),
+ mkU32(0xF)),
+- mkU32(0)/*left*/ );
++ mkU32(0)/*left*/,
++ mkU32(0)/*Little Endian*/);
+ if (!mode64) {
+ d = unsafeIRDirty_0_N (
+ 0/*regparms*/,
+ "ppc32g_dirtyhelper_LVS",
+ fnptr_to_fnentry(vbi, &ppc32g_dirtyhelper_LVS),
+- args );
++ args_be );
+ } else {
+- d = unsafeIRDirty_0_N (
+- 0/*regparms*/,
+- "ppc64g_dirtyhelper_LVS",
+- fnptr_to_fnentry(vbi, &ppc64g_dirtyhelper_LVS),
+- args );
++ if (guest_is_BE)
++ d = unsafeIRDirty_0_N (
++ 0/*regparms*/,
++ "ppc64g_dirtyhelper_LVS",
++ fnptr_to_fnentry(vbi, &ppc64g_dirtyhelper_LVS),
++ args_be );
++ else
++ d = unsafeIRDirty_0_N (
++ 0/*regparms*/,
++ "ppc64g_dirtyhelper_LVS",
++ &ppc64g_dirtyhelper_LVS,
++ args_le );
+ }
+ DIP("lvsl v%d,r%u,r%u\n", vD_addr, rA_addr, rB_addr);
+ /* declare guest state effects */
+@@ -15460,24 +15657,40 @@ static Bool dis_av_load ( VexAbiInfo* vbi, UInt theInstr )
+ case 0x026: { // lvsr (Load Vector for Shift Right, AV p125)
+ IRDirty* d;
+ UInt vD_off = vectorGuestRegOffset(vD_addr);
+- IRExpr** args = mkIRExprVec_4(
+- IRExpr_BBPTR(),
+- mkU32(vD_off),
+- binop(Iop_And32, mkNarrowTo32(ty, mkexpr(EA)),
+- mkU32(0xF)),
+- mkU32(1)/*right*/ );
++ IRExpr** args_be = mkIRExprVec_5(
++ IRExpr_BBPTR(),
++ mkU32(vD_off),
++ binop(Iop_And32, mkNarrowTo32(ty, mkexpr(EA)),
++ mkU32(0xF)),
++ mkU32(1)/*right*/,
++ mkU32(1)/*Big Endian*/);
++ IRExpr** args_le = mkIRExprVec_5(
++ IRExpr_BBPTR(),
++ mkU32(vD_off),
++ binop(Iop_And32, mkNarrowTo32(ty, mkexpr(EA)),
++ mkU32(0xF)),
++ mkU32(1)/*right*/,
++ mkU32(0)/*Little Endian*/);
++
+ if (!mode64) {
+ d = unsafeIRDirty_0_N (
+- 0/*regparms*/,
++ 0/*regparms*/,
+ "ppc32g_dirtyhelper_LVS",
+ fnptr_to_fnentry(vbi, &ppc32g_dirtyhelper_LVS),
+- args );
++ args_be );
+ } else {
+- d = unsafeIRDirty_0_N (
+- 0/*regparms*/,
+- "ppc64g_dirtyhelper_LVS",
+- fnptr_to_fnentry(vbi, &ppc64g_dirtyhelper_LVS),
+- args );
++ if (guest_is_BE)
++ d = unsafeIRDirty_0_N (
++ 0/*regparms*/,
++ "ppc64g_dirtyhelper_LVS",
++ fnptr_to_fnentry(vbi, &ppc64g_dirtyhelper_LVS),
++ args_be );
++ else
++ d = unsafeIRDirty_0_N (
++ 0/*regparms*/,
++ "ppc64g_dirtyhelper_LVS",
++ &ppc64g_dirtyhelper_LVS,
++ args_le );
+ }
+ DIP("lvsr v%d,r%u,r%u\n", vD_addr, rA_addr, rB_addr);
+ /* declare guest state effects */
+@@ -15496,29 +15709,29 @@ static Bool dis_av_load ( VexAbiInfo* vbi, UInt theInstr )
+ /* loads addressed byte into vector[EA[0:3]
+ since all other destination bytes are undefined,
+ can simply load entire vector from 16-aligned EA */
+- putVReg( vD_addr, load(Ity_V128, mkexpr(EA_align16)) );
++ putVReg( vD_addr, load(Ity_V128, mkexpr(EA_align16), guest_is_BE) );
+ break;
+
+ case 0x027: // lvehx (Load Vector Element Half Word Indexed, AV p121)
+ DIP("lvehx v%d,r%u,r%u\n", vD_addr, rA_addr, rB_addr);
+ /* see note for lvebx */
+- putVReg( vD_addr, load(Ity_V128, mkexpr(EA_align16)) );
++ putVReg( vD_addr, load(Ity_V128, mkexpr(EA_align16), guest_is_BE) );
+ break;
+
+ case 0x047: // lvewx (Load Vector Element Word Indexed, AV p122)
+ DIP("lvewx v%d,r%u,r%u\n", vD_addr, rA_addr, rB_addr);
+ /* see note for lvebx */
+- putVReg( vD_addr, load(Ity_V128, mkexpr(EA_align16)) );
++ putVReg( vD_addr, load(Ity_V128, mkexpr(EA_align16), guest_is_BE) );
+ break;
+
+ case 0x067: // lvx (Load Vector Indexed, AV p127)
+ DIP("lvx v%d,r%u,r%u\n", vD_addr, rA_addr, rB_addr);
+- putVReg( vD_addr, load(Ity_V128, mkexpr(EA_align16)) );
++ putVReg( vD_addr, load(Ity_V128, mkexpr(EA_align16), guest_is_BE) );
+ break;
+
+ case 0x167: // lvxl (Load Vector Indexed LRU, AV p128)
+ DIP("lvxl v%d,r%u,r%u\n", vD_addr, rA_addr, rB_addr);
+- putVReg( vD_addr, load(Ity_V128, mkexpr(EA_align16)) );
++ putVReg( vD_addr, load(Ity_V128, mkexpr(EA_align16), guest_is_BE) );
+ break;
+
+ default:
+@@ -15531,7 +15744,7 @@ static Bool dis_av_load ( VexAbiInfo* vbi, UInt theInstr )
+ /*
+ AltiVec Store Instructions
+ */
+-static Bool dis_av_store ( UInt theInstr )
++static Bool dis_av_store ( UInt theInstr, Bool guest_is_BE )
+ {
+ /* X-Form */
+ UChar opc1 = ifieldOPC(theInstr);
+@@ -15562,12 +15775,17 @@ static Bool dis_av_store ( UInt theInstr )
+ assign( eb, binop(Iop_And8, mkU8(0xF),
+ unop(Iop_32to8,
+ mkNarrowTo32(ty, mkexpr(EA)) )) );
+- assign( idx, binop(Iop_Shl8,
+- binop(Iop_Sub8, mkU8(15), mkexpr(eb)),
+- mkU8(3)) );
++ if (!guest_is_BE) {
++ assign( idx, binop(Iop_Shl8, mkexpr(eb), mkU8(3)) );
++ } else {
++ assign( idx, binop(Iop_Shl8,
++ binop(Iop_Sub8, mkU8(15), mkexpr(eb)),
++ mkU8(3)) );
++ }
+ store( mkexpr(EA),
+ unop( Iop_32to8, unop(Iop_V128to32,
+- binop(Iop_ShrV128, mkexpr(vS), mkexpr(idx)))) );
++ binop(Iop_ShrV128, mkexpr(vS), mkexpr(idx)))),
++ guest_is_BE );
+ break;
+ }
+ case 0x0A7: { // stvehx (Store Vector Half Word Indexed, AV p132)
+@@ -15575,12 +15793,17 @@ static Bool dis_av_store ( UInt theInstr )
+ assign( addr_aligned, addr_align(mkexpr(EA), 2) );
+ assign( eb, binop(Iop_And8, mkU8(0xF),
+ mkNarrowTo8(ty, mkexpr(addr_aligned) )) );
+- assign( idx, binop(Iop_Shl8,
+- binop(Iop_Sub8, mkU8(14), mkexpr(eb)),
+- mkU8(3)) );
++ if (!guest_is_BE) {
++ assign( idx, binop(Iop_Shl8, mkexpr(eb), mkU8(3)) );
++ } else {
++ assign( idx, binop(Iop_Shl8,
++ binop(Iop_Sub8, mkU8(14), mkexpr(eb)),
++ mkU8(3)) );
++ }
+ store( mkexpr(addr_aligned),
+ unop( Iop_32to16, unop(Iop_V128to32,
+- binop(Iop_ShrV128, mkexpr(vS), mkexpr(idx)))) );
++ binop(Iop_ShrV128, mkexpr(vS), mkexpr(idx)))),
++ guest_is_BE );
+ break;
+ }
+ case 0x0C7: { // stvewx (Store Vector Word Indexed, AV p133)
+@@ -15588,23 +15811,28 @@ static Bool dis_av_store ( UInt theInstr )
+ assign( addr_aligned, addr_align(mkexpr(EA), 4) );
+ assign( eb, binop(Iop_And8, mkU8(0xF),
+ mkNarrowTo8(ty, mkexpr(addr_aligned) )) );
+- assign( idx, binop(Iop_Shl8,
+- binop(Iop_Sub8, mkU8(12), mkexpr(eb)),
+- mkU8(3)) );
++ if (!guest_is_BE) {
++ assign( idx, binop(Iop_Shl8, mkexpr(eb), mkU8(3)) );
++ } else {
++ assign( idx, binop(Iop_Shl8,
++ binop(Iop_Sub8, mkU8(12), mkexpr(eb)),
++ mkU8(3)) );
++ }
+ store( mkexpr( addr_aligned),
+ unop( Iop_V128to32,
+- binop(Iop_ShrV128, mkexpr(vS), mkexpr(idx))) );
++ binop(Iop_ShrV128, mkexpr(vS), mkexpr(idx))),
++ guest_is_BE );
+ break;
+ }
+
+ case 0x0E7: // stvx (Store Vector Indexed, AV p134)
+ DIP("stvx v%d,r%u,r%u\n", vS_addr, rA_addr, rB_addr);
+- store( addr_align( mkexpr(EA), 16 ), mkexpr(vS) );
++ store( addr_align( mkexpr(EA), 16 ), mkexpr(vS), guest_is_BE );
+ break;
+
+ case 0x1E7: // stvxl (Store Vector Indexed LRU, AV p135)
+ DIP("stvxl v%d,r%u,r%u\n", vS_addr, rA_addr, rB_addr);
+- store( addr_align( mkexpr(EA), 16 ), mkexpr(vS) );
++ store( addr_align( mkexpr(EA), 16 ), mkexpr(vS), guest_is_BE );
+ break;
+
+ default:
+@@ -18484,7 +18712,8 @@ DisResult disInstr_PPC_WRK (
+ Long delta64,
+ VexArchInfo* archinfo,
+ VexAbiInfo* abiinfo,
+- Bool sigill_diag
++ Bool sigill_diag,
++ Bool guest_is_BE
+ )
+ {
+ UChar opc1;
+@@ -18533,7 +18762,8 @@ DisResult disInstr_PPC_WRK (
+ /* At least this is simple on PPC32: insns are all 4 bytes long, and
+ 4-aligned. So just fish the whole thing out of memory right now
+ and have done. */
+- theInstr = getUIntPPCendianly( (UChar*)(&guest_code[delta]) );
++ theInstr = getUIntPPCendianly( (UChar*)(&guest_code[delta]),
++ guest_is_BE);
+
+ if (0) vex_printf("insn: 0x%x\n", theInstr);
+
+@@ -18558,12 +18788,12 @@ DisResult disInstr_PPC_WRK (
+ UInt word2 = mode64 ? 0x78006800 : 0x5400683E;
+ UInt word3 = mode64 ? 0x7800E802 : 0x5400E83E;
+ UInt word4 = mode64 ? 0x78009802 : 0x5400983E;
+- if (getUIntPPCendianly(code+ 0) == word1 &&
+- getUIntPPCendianly(code+ 4) == word2 &&
+- getUIntPPCendianly(code+ 8) == word3 &&
+- getUIntPPCendianly(code+12) == word4) {
++ if (getUIntPPCendianly(code+ 0, guest_is_BE) == word1 &&
++ getUIntPPCendianly(code+ 4, guest_is_BE) == word2 &&
++ getUIntPPCendianly(code+ 8, guest_is_BE) == word3 &&
++ getUIntPPCendianly(code+12,guest_is_BE) == word4) {
+ /* Got a "Special" instruction preamble. Which one is it? */
+- if (getUIntPPCendianly(code+16) == 0x7C210B78 /* or 1,1,1 */) {
++ if (getUIntPPCendianly(code+16, guest_is_BE) == 0x7C210B78 /* or 1,1,1 */) {
+ /* %R3 = client_request ( %R4 ) */
+ DIP("r3 = client_request ( %%r4 )\n");
+ delta += 20;
+@@ -18573,7 +18803,7 @@ DisResult disInstr_PPC_WRK (
+ goto decode_success;
+ }
+ else
+- if (getUIntPPCendianly(code+16) == 0x7C421378 /* or 2,2,2 */) {
++ if (getUIntPPCendianly(code+16, guest_is_BE) == 0x7C421378 /* or 2,2,2 */) {
+ /* %R3 = guest_NRADDR */
+ DIP("r3 = guest_NRADDR\n");
+ delta += 20;
+@@ -18582,18 +18812,27 @@ DisResult disInstr_PPC_WRK (
+ goto decode_success;
+ }
+ else
+- if (getUIntPPCendianly(code+16) == 0x7C631B78 /* or 3,3,3 */) {
+- /* branch-and-link-to-noredir %R11 */
+- DIP("branch-and-link-to-noredir r11\n");
++ if (getUIntPPCendianly(code+16, guest_is_BE) == 0x7C631B78 /* or 3,3,3 */) {
+ delta += 20;
+- putGST( PPC_GST_LR, mkSzImm(ty, guest_CIA_bbstart + (Long)delta) );
+- putGST( PPC_GST_CIA, getIReg(11));
++ if( !guest_is_BE) {
++ /* branch-and-link-to-noredir %R12 */
++ DIP("branch-and-link-to-noredir r12\n");
++ putGST( PPC_GST_LR,
++ mkSzImm(ty, guest_CIA_bbstart + (Long)delta) );
++ putGST( PPC_GST_CIA, getIReg(12));
++ } else {
++ /* branch-and-link-to-noredir %R11 */
++ DIP("branch-and-link-to-noredir r11\n");
++ putGST( PPC_GST_LR,
++ mkSzImm(ty, guest_CIA_bbstart + (Long)delta) );
++ putGST( PPC_GST_CIA, getIReg(11));
++ }
+ dres.jk_StopHere = Ijk_NoRedir;
+ dres.whatNext = Dis_StopHere;
+ goto decode_success;
+ }
+ else
+- if (getUIntPPCendianly(code+16) == 0x7C842378 /* or 4,4,4 */) {
++ if (getUIntPPCendianly(code+16, guest_is_BE) == 0x7C842378 /* or 4,4,4 */) {
+ /* %R3 = guest_NRADDR_GPR2 */
+ DIP("r3 = guest_NRADDR_GPR2\n");
+ delta += 20;
+@@ -18602,10 +18841,11 @@ DisResult disInstr_PPC_WRK (
+ goto decode_success;
+ }
+ else
+- if (getUIntPPCendianly(code+16) == 0x7CA52B78 /* or 5,5,5 */) {
++ if (getUIntPPCendianly(code+16, guest_is_BE) == 0x7CA52B78 /* or 5,5,5 */) {
+ DIP("IR injection\n");
++ IREndness endian = guest_is_BE ? Iend_BE: Iend_LE;
+
+- vex_inject_ir(irsb, IENDIANESS);
++ vex_inject_ir(irsb, endian);
+
+ delta += 20;
+ dres.len = 20;
+@@ -18625,7 +18865,7 @@ DisResult disInstr_PPC_WRK (
+ }
+ /* We don't know what it is. Set opc1/opc2 so decode_failure
+ can print the insn following the Special-insn preamble. */
+- theInstr = getUIntPPCendianly(code+16);
++ theInstr = getUIntPPCendianly(code+16, guest_is_BE);
+ opc1 = ifieldOPC(theInstr);
+ opc2 = ifieldOPClo10(theInstr);
+ goto decode_failure;
+@@ -18653,7 +18893,7 @@ DisResult disInstr_PPC_WRK (
+ /* Integer Logical Instructions */
+ case 0x1C: case 0x1D: case 0x18: // andi., andis., ori
+ case 0x19: case 0x1A: case 0x1B: // oris, xori, xoris
+- if (dis_int_logic( theInstr )) goto decode_success;
++ if (dis_int_logic( theInstr, guest_is_BE )) goto decode_success;
+ goto decode_failure;
+
+ /* Integer Rotate Instructions */
+@@ -18671,18 +18911,18 @@ DisResult disInstr_PPC_WRK (
+ case 0x22: case 0x23: case 0x2A: // lbz, lbzu, lha
+ case 0x2B: case 0x28: case 0x29: // lhau, lhz, lhzu
+ case 0x20: case 0x21: // lwz, lwzu
+- if (dis_int_load( theInstr )) goto decode_success;
++ if (dis_int_load( theInstr, guest_is_BE )) goto decode_success;
+ goto decode_failure;
+
+ /* Integer Store Instructions */
+ case 0x26: case 0x27: case 0x2C: // stb, stbu, sth
+ case 0x2D: case 0x24: case 0x25: // sthu, stw, stwu
+- if (dis_int_store( theInstr, abiinfo )) goto decode_success;
++ if (dis_int_store( theInstr, abiinfo, guest_is_BE )) goto decode_success;
+ goto decode_failure;
+
+ /* Integer Load and Store Multiple Instructions */
+ case 0x2E: case 0x2F: // lmw, stmw
+- if (dis_int_ldst_mult( theInstr )) goto decode_success;
++ if (dis_int_ldst_mult( theInstr, guest_is_BE )) goto decode_success;
+ goto decode_failure;
+
+ /* Branch Instructions */
+@@ -18711,31 +18951,31 @@ DisResult disInstr_PPC_WRK (
+ case 0x30: case 0x31: case 0x32: // lfs, lfsu, lfd
+ case 0x33: // lfdu
+ if (!allow_F) goto decode_noF;
+- if (dis_fp_load( theInstr )) goto decode_success;
++ if (dis_fp_load( theInstr, guest_is_BE )) goto decode_success;
+ goto decode_failure;
+
+ /* Floating Point Store Instructions */
+ case 0x34: case 0x35: case 0x36: // stfsx, stfsux, stfdx
+ case 0x37: // stfdux
+ if (!allow_F) goto decode_noF;
+- if (dis_fp_store( theInstr )) goto decode_success;
++ if (dis_fp_store( theInstr, guest_is_BE )) goto decode_success;
+ goto decode_failure;
+
+ /* Floating Point Load Double Pair Instructions */
+ case 0x39: case 0x3D:
+ if (!allow_F) goto decode_noF;
+- if (dis_fp_pair( theInstr )) goto decode_success;
++ if (dis_fp_pair( theInstr, guest_is_BE )) goto decode_success;
+ goto decode_failure;
+
+ /* 128-bit Integer Load */
+ case 0x38: // lq
+- if (dis_int_load( theInstr )) goto decode_success;
++ if (dis_int_load( theInstr, guest_is_BE )) goto decode_success;
+ goto decode_failure;
+
+ /* 64bit Integer Loads */
+ case 0x3A: // ld, ldu, lwa
+ if (!mode64) goto decode_failure;
+- if (dis_int_load( theInstr )) goto decode_success;
++ if (dis_int_load( theInstr, guest_is_BE )) goto decode_success;
+ goto decode_failure;
+
+ case 0x3B:
+@@ -18748,13 +18988,13 @@ DisResult disInstr_PPC_WRK (
+ case 0x22: // dmul - DFP Mult
+ case 0x222: // ddiv - DFP Divide
+ if (!allow_DFP) goto decode_noDFP;
+- if (dis_dfp_arith( theInstr ))
++ if (dis_dfp_arith( theInstr, guest_is_BE ))
+ goto decode_success;
+ case 0x82: // dcmpo, DFP comparison ordered instruction
+ case 0x282: // dcmpu, DFP comparison unordered instruction
+ if (!allow_DFP)
+ goto decode_failure;
+- if (dis_dfp_compare( theInstr ) )
++ if (dis_dfp_compare( theInstr, guest_is_BE ) )
+ goto decode_success;
+ goto decode_failure;
+ case 0x102: // dctdp - DFP convert to DFP long
+@@ -18762,43 +19002,43 @@ DisResult disInstr_PPC_WRK (
+ case 0x122: // dctfix - DFP convert to fixed
+ if (!allow_DFP)
+ goto decode_failure;
+- if (dis_dfp_fmt_conv( theInstr ))
++ if (dis_dfp_fmt_conv( theInstr, guest_is_BE ))
+ goto decode_success;
+ goto decode_failure;
+ case 0x322: // POWER 7 inst, dcffix - DFP convert from fixed
+ if (!allow_VX)
+ goto decode_failure;
+- if (dis_dfp_fmt_conv( theInstr ))
++ if (dis_dfp_fmt_conv( theInstr, guest_is_BE ))
+ goto decode_success;
+ goto decode_failure;
+ case 0x2A2: // dtstsf - DFP number of significant digits
+ if (!allow_DFP)
+ goto decode_failure;
+- if (dis_dfp_significant_digits(theInstr))
++ if (dis_dfp_significant_digits(theInstr, guest_is_BE))
+ goto decode_success;
+ goto decode_failure;
+ case 0x142: // ddedpd DFP Decode DPD to BCD
+ case 0x342: // denbcd DFP Encode BCD to DPD
+ if (!allow_DFP)
+ goto decode_failure;
+- if (dis_dfp_bcd(theInstr))
++ if (dis_dfp_bcd(theInstr, guest_is_BE))
+ goto decode_success;
+ goto decode_failure;
+ case 0x162: // dxex - Extract exponent
+ case 0x362: // diex - Insert exponent
+ if (!allow_DFP)
+ goto decode_failure;
+- if (dis_dfp_extract_insert( theInstr ) )
++ if (dis_dfp_extract_insert( theInstr, guest_is_BE ) )
+ goto decode_success;
+ goto decode_failure;
+ case 0x3CE: // fcfidus (implemented as native insn)
+ if (!allow_VX)
+ goto decode_noVX;
+- if (dis_fp_round( theInstr ))
++ if (dis_fp_round( theInstr, guest_is_BE ))
+ goto decode_success;
+ goto decode_failure;
+ case 0x34E: // fcfids
+- if (dis_fp_round( theInstr ))
++ if (dis_fp_round( theInstr, guest_is_BE ))
+ goto decode_success;
+ goto decode_failure;
+ }
+@@ -18809,14 +19049,14 @@ DisResult disInstr_PPC_WRK (
+ case 0x62: // dscri, DFP shift right
+ if (!allow_DFP)
+ goto decode_failure;
+- if (dis_dfp_shift( theInstr ))
++ if (dis_dfp_shift( theInstr, guest_is_BE ))
+ goto decode_success;
+ goto decode_failure;
+ case 0xc2: // dtstdc, DFP test data class
+ case 0xe2: // dtstdg, DFP test data group
+ if (!allow_DFP)
+ goto decode_failure;
+- if (dis_dfp_class_test( theInstr ))
++ if (dis_dfp_class_test( theInstr, guest_is_BE ))
+ goto decode_success;
+ goto decode_failure;
+ }
+@@ -18828,20 +19068,20 @@ DisResult disInstr_PPC_WRK (
+ case 0x43: // dquai - DFP Quantize immediate
+ if (!allow_DFP)
+ goto decode_failure;
+- if (dis_dfp_quantize_sig_rrnd( theInstr ) )
++ if (dis_dfp_quantize_sig_rrnd( theInstr, guest_is_BE ) )
+ goto decode_success;
+ goto decode_failure;
+ case 0xA2: // dtstex - DFP Test exponent
+ if (!allow_DFP)
+ goto decode_failure;
+- if (dis_dfp_exponent_test( theInstr ) )
++ if (dis_dfp_exponent_test( theInstr, guest_is_BE ) )
+ goto decode_success;
+ goto decode_failure;
+ case 0x63: // drintx - Round to an integer value
+ case 0xE3: // drintn - Round to an integer value
+ if (!allow_DFP)
+ goto decode_failure;
+- if (dis_dfp_round( theInstr ) ) {
++ if (dis_dfp_round( theInstr, guest_is_BE ) ) {
+ goto decode_success;
+ }
+ goto decode_failure;
+@@ -18854,26 +19094,26 @@ DisResult disInstr_PPC_WRK (
+ /* Floating Point Arith Instructions */
+ case 0x12: case 0x14: case 0x15: // fdivs, fsubs, fadds
+ case 0x19: // fmuls
+- if (dis_fp_arith(theInstr)) goto decode_success;
++ if (dis_fp_arith(theInstr, guest_is_BE)) goto decode_success;
+ goto decode_failure;
+ case 0x16: // fsqrts
+ if (!allow_FX) goto decode_noFX;
+- if (dis_fp_arith(theInstr)) goto decode_success;
++ if (dis_fp_arith(theInstr, guest_is_BE)) goto decode_success;
+ goto decode_failure;
+ case 0x18: // fres
+ if (!allow_GX) goto decode_noGX;
+- if (dis_fp_arith(theInstr)) goto decode_success;
++ if (dis_fp_arith(theInstr, guest_is_BE)) goto decode_success;
+ goto decode_failure;
+
+ /* Floating Point Mult-Add Instructions */
+ case 0x1C: case 0x1D: case 0x1E: // fmsubs, fmadds, fnmsubs
+ case 0x1F: // fnmadds
+- if (dis_fp_multadd(theInstr)) goto decode_success;
++ if (dis_fp_multadd(theInstr, guest_is_BE)) goto decode_success;
+ goto decode_failure;
+
+ case 0x1A: // frsqrtes
+ if (!allow_GX) goto decode_noGX;
+- if (dis_fp_arith(theInstr)) goto decode_success;
++ if (dis_fp_arith(theInstr, guest_is_BE)) goto decode_success;
+ goto decode_failure;
+
+ default:
+@@ -18913,7 +19153,7 @@ DisResult disInstr_PPC_WRK (
+ case 0x0B4: case 0x094: // xsredp, xsrsqrtedp
+ case 0x0D6: case 0x0B2: // xsrdpic, xsrdpiz
+ case 0x092: case 0x232: // xsrdpi, xsrsp
+- if (dis_vxs_misc(theInstr, vsxOpc2)) goto decode_success;
++ if (dis_vxs_misc(theInstr, vsxOpc2, guest_is_BE)) goto decode_success;
+ goto decode_failure;
+ case 0x08C: case 0x0AC: // xscmpudp, xscmpodp
+ if (dis_vx_cmp(theInstr, vsxOpc2)) goto decode_success;
+@@ -19022,7 +19262,7 @@ DisResult disInstr_PPC_WRK (
+
+ /* 64bit Integer Stores */
+ case 0x3E: // std, stdu, stq
+- if (dis_int_store( theInstr, abiinfo )) goto decode_success;
++ if (dis_int_store( theInstr, abiinfo, guest_is_BE )) goto decode_success;
+ goto decode_failure;
+
+ case 0x3F:
+@@ -19035,26 +19275,26 @@ DisResult disInstr_PPC_WRK (
+ /* Floating Point Arith Instructions */
+ case 0x12: case 0x14: case 0x15: // fdiv, fsub, fadd
+ case 0x19: // fmul
+- if (dis_fp_arith(theInstr)) goto decode_success;
++ if (dis_fp_arith(theInstr, guest_is_BE)) goto decode_success;
+ goto decode_failure;
+ case 0x16: // fsqrt
+ if (!allow_FX) goto decode_noFX;
+- if (dis_fp_arith(theInstr)) goto decode_success;
++ if (dis_fp_arith(theInstr, guest_is_BE)) goto decode_success;
+ goto decode_failure;
+ case 0x17: case 0x1A: // fsel, frsqrte
+ if (!allow_GX) goto decode_noGX;
+- if (dis_fp_arith(theInstr)) goto decode_success;
++ if (dis_fp_arith(theInstr, guest_is_BE)) goto decode_success;
+ goto decode_failure;
+
+ /* Floating Point Mult-Add Instructions */
+ case 0x1C: case 0x1D: case 0x1E: // fmsub, fmadd, fnmsub
+ case 0x1F: // fnmadd
+- if (dis_fp_multadd(theInstr)) goto decode_success;
++ if (dis_fp_multadd(theInstr, guest_is_BE)) goto decode_success;
+ goto decode_failure;
+
+ case 0x18: // fre
+ if (!allow_GX) goto decode_noGX;
+- if (dis_fp_arith(theInstr)) goto decode_success;
++ if (dis_fp_arith(theInstr, guest_is_BE)) goto decode_success;
+ goto decode_failure;
+
+ default:
+@@ -19069,14 +19309,14 @@ DisResult disInstr_PPC_WRK (
+ case 0x22: // dmulq - DFP Mult
+ case 0x222: // ddivq - DFP Divide
+ if (!allow_DFP) goto decode_noDFP;
+- if (dis_dfp_arithq( theInstr ))
++ if (dis_dfp_arithq( theInstr, guest_is_BE ))
+ goto decode_success;
+ goto decode_failure;
+ case 0x162: // dxexq - DFP Extract exponent
+ case 0x362: // diexq - DFP Insert exponent
+ if (!allow_DFP)
+ goto decode_failure;
+- if (dis_dfp_extract_insertq( theInstr ))
++ if (dis_dfp_extract_insertq( theInstr, guest_is_BE ))
+ goto decode_success;
+ goto decode_failure;
+
+@@ -19084,7 +19324,7 @@ DisResult disInstr_PPC_WRK (
+ case 0x282: // dcmpuq, DFP comparison unordered instruction
+ if (!allow_DFP)
+ goto decode_failure;
+- if (dis_dfp_compare( theInstr ) )
++ if (dis_dfp_compare( theInstr, guest_is_BE ) )
+ goto decode_success;
+ goto decode_failure;
+
+@@ -19094,14 +19334,14 @@ DisResult disInstr_PPC_WRK (
+ case 0x322: // dcffixq - DFP convert from fixed quad
+ if (!allow_DFP)
+ goto decode_failure;
+- if (dis_dfp_fmt_convq( theInstr ))
++ if (dis_dfp_fmt_convq( theInstr, guest_is_BE ))
+ goto decode_success;
+ goto decode_failure;
+
+ case 0x2A2: // dtstsfq - DFP number of significant digits
+ if (!allow_DFP)
+ goto decode_failure;
+- if (dis_dfp_significant_digits(theInstr))
++ if (dis_dfp_significant_digits(theInstr, guest_is_BE))
+ goto decode_success;
+ goto decode_failure;
+
+@@ -19109,19 +19349,19 @@ DisResult disInstr_PPC_WRK (
+ case 0x342: // denbcdq DFP Encode BCD to DPD
+ if (!allow_DFP)
+ goto decode_failure;
+- if (dis_dfp_bcdq(theInstr))
++ if (dis_dfp_bcdq(theInstr, guest_is_BE))
+ goto decode_success;
+ goto decode_failure;
+
+ /* Floating Point Compare Instructions */
+ case 0x000: // fcmpu
+ case 0x020: // fcmpo
+- if (dis_fp_cmp(theInstr)) goto decode_success;
++ if (dis_fp_cmp(theInstr, guest_is_BE)) goto decode_success;
+ goto decode_failure;
+
+ case 0x080: // ftdiv
+ case 0x0A0: // ftsqrt
+- if (dis_fp_tests(theInstr)) goto decode_success;
++ if (dis_fp_tests(theInstr, guest_is_BE)) goto decode_success;
+ goto decode_failure;
+
+ /* Floating Point Rounding/Conversion Instructions */
+@@ -19131,12 +19371,12 @@ DisResult disInstr_PPC_WRK (
+ case 0x32E: // fctid
+ case 0x32F: // fctidz
+ case 0x34E: // fcfid
+- if (dis_fp_round(theInstr)) goto decode_success;
++ if (dis_fp_round(theInstr, guest_is_BE)) goto decode_success;
+ goto decode_failure;
+ case 0x3CE: case 0x3AE: case 0x3AF: // fcfidu, fctidu[z] (implemented as native insns)
+ case 0x08F: case 0x08E: // fctiwu[z] (implemented as native insns)
+ if (!allow_VX) goto decode_noVX;
+- if (dis_fp_round(theInstr)) goto decode_success;
++ if (dis_fp_round(theInstr, guest_is_BE)) goto decode_success;
+ goto decode_failure;
+
+ /* Power6 rounding stuff */
+@@ -19146,7 +19386,7 @@ DisResult disInstr_PPC_WRK (
+ case 0x1A8: // friz
+ /* A hack to check for P6 capability . . . */
+ if ((allow_F && allow_V && allow_FX && allow_GX) &&
+- (dis_fp_round(theInstr)))
++ (dis_fp_round(theInstr, guest_is_BE)))
+ goto decode_success;
+ goto decode_failure;
+
+@@ -19156,11 +19396,11 @@ DisResult disInstr_PPC_WRK (
+ case 0x048: // fmr
+ case 0x088: // fnabs
+ case 0x108: // fabs
+- if (dis_fp_move( theInstr )) goto decode_success;
++ if (dis_fp_move( theInstr, guest_is_BE )) goto decode_success;
+ goto decode_failure;
+
+ case 0x3c6: case 0x346: // fmrgew, fmrgow
+- if (dis_fp_merge( theInstr )) goto decode_success;
++ if (dis_fp_merge( theInstr, guest_is_BE )) goto decode_success;
+ goto decode_failure;
+
+ /* Floating Point Status/Control Register Instructions */
+@@ -19172,7 +19412,7 @@ DisResult disInstr_PPC_WRK (
+ case 0x2C7: // mtfsf
+ // Some of the above instructions need to know more about the
+ // ISA level supported by the host.
+- if (dis_fp_scr( theInstr, allow_GX )) goto decode_success;
++ if (dis_fp_scr( theInstr, allow_GX, guest_is_BE )) goto decode_success;
+ goto decode_failure;
+
+ default:
+@@ -19185,14 +19425,14 @@ DisResult disInstr_PPC_WRK (
+ case 0x62: // dscri, DFP shift right
+ if (!allow_DFP)
+ goto decode_failure;
+- if (dis_dfp_shiftq( theInstr ))
++ if (dis_dfp_shiftq( theInstr, guest_is_BE ))
+ goto decode_success;
+ goto decode_failure;
+ case 0xc2: // dtstdc, DFP test data class
+ case 0xe2: // dtstdg, DFP test data group
+ if (!allow_DFP)
+ goto decode_failure;
+- if (dis_dfp_class_test( theInstr ))
++ if (dis_dfp_class_test( theInstr, guest_is_BE ))
+ goto decode_success;
+ goto decode_failure;
+ default:
+@@ -19206,18 +19446,18 @@ DisResult disInstr_PPC_WRK (
+ case 0x43: // dquaiq - DFP Quantize immediate Quad
+ if (!allow_DFP)
+ goto decode_failure;
+- if (dis_dfp_quantize_sig_rrndq( theInstr ))
++ if (dis_dfp_quantize_sig_rrndq( theInstr, guest_is_BE ))
+ goto decode_success;
+ goto decode_failure;
+ case 0xA2: // dtstexq - DFP Test exponent Quad
+- if (dis_dfp_exponent_test( theInstr ) )
++ if (dis_dfp_exponent_test( theInstr, guest_is_BE ) )
+ goto decode_success;
+ goto decode_failure;
+ case 0x63: // drintxq - DFP Round to an integer value
+ case 0xE3: // drintnq - DFP Round to an integer value
+ if (!allow_DFP)
+ goto decode_failure;
+- if (dis_dfp_roundq( theInstr ))
++ if (dis_dfp_roundq( theInstr, guest_is_BE ))
+ goto decode_success;
+ goto decode_failure;
+
+@@ -19245,7 +19485,7 @@ DisResult disInstr_PPC_WRK (
+
+ /* Memory Synchronization Instructions */
+ case 0x096: // isync
+- if (dis_memsync( theInstr )) goto decode_success;
++ if (dis_memsync( theInstr, guest_is_BE )) goto decode_success;
+ goto decode_failure;
+
+ default:
+@@ -19291,7 +19531,7 @@ DisResult disInstr_PPC_WRK (
+ goto decode_failure;
+
+ case 0x1FC: // cmpb
+- if (dis_int_logic( theInstr )) goto decode_success;
++ if (dis_int_logic( theInstr, guest_is_BE )) goto decode_success;
+ goto decode_failure;
+
+ default:
+@@ -19313,7 +19553,7 @@ DisResult disInstr_PPC_WRK (
+ case 0x1DC: case 0x07C: case 0x1BC: // nand, nor, or
+ case 0x19C: case 0x13C: // orc, xor
+ case 0x2DF: case 0x25F: // mftgpr, mffgpr
+- if (dis_int_logic( theInstr )) goto decode_success;
++ if (dis_int_logic( theInstr, guest_is_BE )) goto decode_success;
+ goto decode_failure;
+
+ case 0x28E: case 0x2AE: // tbegin., tend.
+@@ -19321,7 +19561,8 @@ DisResult disInstr_PPC_WRK (
+ case 0x32E: case 0x34E: case 0x36E: // tabortdc., tabortwci., tabortdci.
+ case 0x38E: case 0x3AE: case 0x3EE: // tabort., treclaim., trechkpt.
+ if (dis_transactional_memory( theInstr,
+- getUIntPPCendianly( (UChar*)(&guest_code[delta + 4])),
++ getUIntPPCendianly( (UChar*)(&guest_code[delta + 4]),
++ guest_is_BE),
+ abiinfo, &dres,
+ resteerOkFn, callback_opaque))
+ goto decode_success;
+@@ -19330,7 +19571,7 @@ DisResult disInstr_PPC_WRK (
+ /* 64bit Integer Logical Instructions */
+ case 0x3DA: case 0x03A: // extsw, cntlzd
+ if (!mode64) goto decode_failure;
+- if (dis_int_logic( theInstr )) goto decode_success;
++ if (dis_int_logic( theInstr, guest_is_BE )) goto decode_success;
+ goto decode_failure;
+
+ /* 64bit Integer Parity Instructions */
+@@ -19361,44 +19602,44 @@ DisResult disInstr_PPC_WRK (
+ case 0x057: case 0x077: case 0x157: // lbzx, lbzux, lhax
+ case 0x177: case 0x117: case 0x137: // lhaux, lhzx, lhzux
+ case 0x017: case 0x037: // lwzx, lwzux
+- if (dis_int_load( theInstr )) goto decode_success;
++ if (dis_int_load( theInstr, guest_is_BE )) goto decode_success;
+ goto decode_failure;
+
+ /* 64bit Integer Load Instructions */
+ case 0x035: case 0x015: // ldux, ldx
+ case 0x175: case 0x155: // lwaux, lwax
+ if (!mode64) goto decode_failure;
+- if (dis_int_load( theInstr )) goto decode_success;
++ if (dis_int_load( theInstr, guest_is_BE )) goto decode_success;
+ goto decode_failure;
+
+ /* Integer Store Instructions */
+ case 0x0F7: case 0x0D7: case 0x1B7: // stbux, stbx, sthux
+ case 0x197: case 0x0B7: case 0x097: // sthx, stwux, stwx
+- if (dis_int_store( theInstr, abiinfo )) goto decode_success;
++ if (dis_int_store( theInstr, abiinfo, guest_is_BE )) goto decode_success;
+ goto decode_failure;
+
+ /* 64bit Integer Store Instructions */
+ case 0x0B5: case 0x095: // stdux, stdx
+ if (!mode64) goto decode_failure;
+- if (dis_int_store( theInstr, abiinfo )) goto decode_success;
++ if (dis_int_store( theInstr, abiinfo, guest_is_BE )) goto decode_success;
+ goto decode_failure;
+
+ /* Integer Load and Store with Byte Reverse Instructions */
+ case 0x214: case 0x294: // ldbrx, stdbrx
+ if (!mode64) goto decode_failure;
+- if (dis_int_ldst_rev( theInstr )) goto decode_success;
++ if (dis_int_ldst_rev( theInstr, guest_is_BE )) goto decode_success;
+ goto decode_failure;
+
+ case 0x216: case 0x316: case 0x296: // lwbrx, lhbrx, stwbrx
+ case 0x396: // sthbrx
+- if (dis_int_ldst_rev( theInstr )) goto decode_success;
++ if (dis_int_ldst_rev( theInstr, guest_is_BE )) goto decode_success;
+ goto decode_failure;
+
+ /* Integer Load and Store String Instructions */
+ case 0x255: case 0x215: case 0x2D5: // lswi, lswx, stswi
+ case 0x295: { // stswx
+ Bool stopHere = False;
+- Bool ok = dis_int_ldst_str( theInstr, &stopHere );
++ Bool ok = dis_int_ldst_str( theInstr, &stopHere, guest_is_BE );
+ if (!ok) goto decode_failure;
+ if (stopHere) {
+ putGST( PPC_GST_CIA, mkSzImm(ty, nextInsnAddr()) );
+@@ -19411,17 +19652,17 @@ DisResult disInstr_PPC_WRK (
+ /* Memory Synchronization Instructions */
+ case 0x356: case 0x014: case 0x096: // eieio, lwarx, stwcx.
+ case 0x256: // sync
+- if (dis_memsync( theInstr )) goto decode_success;
++ if (dis_memsync( theInstr, guest_is_BE )) goto decode_success;
+ goto decode_failure;
+
+ /* 64bit Memory Synchronization Instructions */
+ case 0x054: case 0x0D6: // ldarx, stdcx.
+ if (!mode64) goto decode_failure;
+- if (dis_memsync( theInstr )) goto decode_success;
++ if (dis_memsync( theInstr, guest_is_BE )) goto decode_success;
+ goto decode_failure;
+
+ case 0x114: case 0x0B6: // lqarx, stqcx.
+- if (dis_memsync( theInstr )) goto decode_success;
++ if (dis_memsync( theInstr, guest_is_BE )) goto decode_success;
+ goto decode_failure;
+
+ /* Processor Control Instructions */
+@@ -19437,7 +19678,7 @@ DisResult disInstr_PPC_WRK (
+ case 0x2F6: case 0x056: case 0x036: // dcba, dcbf, dcbst
+ case 0x116: case 0x0F6: case 0x3F6: // dcbt, dcbtst, dcbz
+ case 0x3D6: // icbi
+- if (dis_cache_manage( theInstr, &dres, archinfo ))
++ if (dis_cache_manage( theInstr, &dres, archinfo, guest_is_BE ))
+ goto decode_success;
+ goto decode_failure;
+
+@@ -19460,36 +19701,36 @@ DisResult disInstr_PPC_WRK (
+ case 0x217: case 0x237: case 0x257: // lfsx, lfsux, lfdx
+ case 0x277: // lfdux
+ if (!allow_F) goto decode_noF;
+- if (dis_fp_load( theInstr )) goto decode_success;
++ if (dis_fp_load( theInstr, guest_is_BE )) goto decode_success;
+ goto decode_failure;
+
+ /* Floating Point Store Instructions */
+ case 0x297: case 0x2B7: case 0x2D7: // stfs, stfsu, stfd
+ case 0x2F7: // stfdu, stfiwx
+ if (!allow_F) goto decode_noF;
+- if (dis_fp_store( theInstr )) goto decode_success;
++ if (dis_fp_store( theInstr, guest_is_BE )) goto decode_success;
+ goto decode_failure;
+ case 0x3D7: // stfiwx
+ if (!allow_F) goto decode_noF;
+ if (!allow_GX) goto decode_noGX;
+- if (dis_fp_store( theInstr )) goto decode_success;
++ if (dis_fp_store( theInstr, guest_is_BE )) goto decode_success;
+ goto decode_failure;
+
+ /* Floating Point Double Pair Indexed Instructions */
+ case 0x317: // lfdpx (Power6)
+ case 0x397: // stfdpx (Power6)
+ if (!allow_F) goto decode_noF;
+- if (dis_fp_pair(theInstr)) goto decode_success;
++ if (dis_fp_pair(theInstr, guest_is_BE)) goto decode_success;
+ goto decode_failure;
+
+ case 0x357: // lfiwax
+ if (!allow_F) goto decode_noF;
+- if (dis_fp_load( theInstr )) goto decode_success;
++ if (dis_fp_load( theInstr, guest_is_BE )) goto decode_success;
+ goto decode_failure;
+
+ case 0x377: // lfiwzx
+ if (!allow_F) goto decode_noF;
+- if (dis_fp_load( theInstr )) goto decode_success;
++ if (dis_fp_load( theInstr, guest_is_BE )) goto decode_success;
+ goto decode_failure;
+
+ /* AltiVec instructions */
+@@ -19505,14 +19746,14 @@ DisResult disInstr_PPC_WRK (
+ case 0x007: case 0x027: case 0x047: // lvebx, lvehx, lvewx
+ case 0x067: case 0x167: // lvx, lvxl
+ if (!allow_V) goto decode_noV;
+- if (dis_av_load( abiinfo, theInstr )) goto decode_success;
++ if (dis_av_load( abiinfo, theInstr, guest_is_BE )) goto decode_success;
+ goto decode_failure;
+
+ /* AV Store */
+ case 0x087: case 0x0A7: case 0x0C7: // stvebx, stvehx, stvewx
+ case 0x0E7: case 0x1E7: // stvx, stvxl
+ if (!allow_V) goto decode_noV;
+- if (dis_av_store( theInstr )) goto decode_success;
++ if (dis_av_store( theInstr, guest_is_BE )) goto decode_success;
+ goto decode_failure;
+
+ /* VSX Load */
+@@ -19527,7 +19768,7 @@ DisResult disInstr_PPC_WRK (
+ // if allow_V is not set, we'll skip trying to decode.
+ if (!allow_V) goto decode_noV;
+
+- if (dis_vx_load( theInstr )) goto decode_success;
++ if (dis_vx_load( theInstr, guest_is_BE )) goto decode_success;
+ goto decode_failure;
+
+ /* VSX Store */
+@@ -19540,19 +19781,19 @@ DisResult disInstr_PPC_WRK (
+ // if allow_V is not set, we'll skip trying to decode.
+ if (!allow_V) goto decode_noV;
+
+- if (dis_vx_store( theInstr )) goto decode_success;
++ if (dis_vx_store( theInstr, guest_is_BE )) goto decode_success;
+ goto decode_failure;
+
+ /* Miscellaneous ISA 2.06 instructions */
+ case 0x1FA: // popcntd
+ case 0x17A: // popcntw
+ case 0x7A: // popcntb
+- if (dis_int_logic( theInstr )) goto decode_success;
++ if (dis_int_logic( theInstr, guest_is_BE )) goto decode_success;
+ goto decode_failure;
+
+ case 0x0FC: // bpermd
+ if (!mode64) goto decode_failure;
+- if (dis_int_logic( theInstr )) goto decode_success;
++ if (dis_int_logic( theInstr, guest_is_BE )) goto decode_success;
+ goto decode_failure;
+
+ default:
+@@ -19942,6 +20183,7 @@ DisResult disInstr_PPC ( IRSB* irsb_IN,
+ VexArchInfo* archinfo,
+ VexAbiInfo* abiinfo,
+ Bool host_bigendian_IN,
++ Bool guest_bigendian_IN,
+ Bool sigill_diag_IN )
+ {
+ IRType ty;
+@@ -19954,6 +20196,13 @@ DisResult disInstr_PPC ( IRSB* irsb_IN,
+ /* global -- ick */
+ mode64 = guest_arch == VexArchPPC64;
+ ty = mode64 ? Ity_I64 : Ity_I32;
++ if (!mode64 && !guest_bigendian_IN) {
++ vex_printf("disInstr(ppc): Little Endian 32-bit mode is not supported\n");
++ dres.whatNext = Dis_StopHere;
++ dres.jk_StopHere = Ijk_NoDecode;
++ dres.len = 0;
++ return dres;
++ }
+
+ /* do some sanity checks */
+ mask32 = VEX_HWCAPS_PPC32_F | VEX_HWCAPS_PPC32_V
+@@ -19979,7 +20228,8 @@ DisResult disInstr_PPC ( IRSB* irsb_IN,
+ guest_CIA_bbstart = mkSzAddr(ty, guest_IP - delta);
+
+ dres = disInstr_PPC_WRK ( resteerOkFn, resteerCisOk, callback_opaque,
+- delta, archinfo, abiinfo, sigill_diag_IN );
++ delta, archinfo, abiinfo, sigill_diag_IN,
++ guest_bigendian_IN);
+
+ return dres;
+ }
+diff --git a/VEX/priv/guest_s390_defs.h b/VEX/priv/guest_s390_defs.h
+index 63dd1af..b11dcc6 100644
+--- a/VEX/priv/guest_s390_defs.h
++++ b/VEX/priv/guest_s390_defs.h
+@@ -51,6 +51,7 @@ DisResult disInstr_S390 ( IRSB* irbb,
+ VexArchInfo* archinfo,
+ VexAbiInfo* abiinfo,
+ Bool host_bigendian,
++ Bool guest_bigendian,
+ Bool sigill_diag );
+
+ /* Used by the optimiser to specialise calls to helpers. */
+diff --git a/VEX/priv/guest_s390_toIR.c b/VEX/priv/guest_s390_toIR.c
+index b6fc165..06b6ca0 100644
+--- a/VEX/priv/guest_s390_toIR.c
++++ b/VEX/priv/guest_s390_toIR.c
+@@ -16566,6 +16566,7 @@ disInstr_S390(IRSB *irsb_IN,
+ VexArchInfo *archinfo,
+ VexAbiInfo *abiinfo,
+ Bool host_bigendian,
++ Bool guest_bigendian,
+ Bool sigill_diag_IN)
+ {
+ vassert(guest_arch == VexArchS390X);
+diff --git a/VEX/priv/guest_x86_defs.h b/VEX/priv/guest_x86_defs.h
+index 1c64912..c87e23c 100644
+--- a/VEX/priv/guest_x86_defs.h
++++ b/VEX/priv/guest_x86_defs.h
+@@ -61,6 +61,7 @@ DisResult disInstr_X86 ( IRSB* irbb,
+ VexArchInfo* archinfo,
+ VexAbiInfo* abiinfo,
+ Bool host_bigendian,
++ Bool guest_bigendian_IN,
+ Bool sigill_diag );
+
+ /* Used by the optimiser to specialise calls to helpers. */
+diff --git a/VEX/priv/guest_x86_toIR.c b/VEX/priv/guest_x86_toIR.c
+index 37afd97..8da303c 100644
+--- a/VEX/priv/guest_x86_toIR.c
++++ b/VEX/priv/guest_x86_toIR.c
+@@ -15422,6 +15422,7 @@ DisResult disInstr_X86 ( IRSB* irsb_IN,
+ VexArchInfo* archinfo,
+ VexAbiInfo* abiinfo,
+ Bool host_bigendian_IN,
++ Bool guest_bigendian_IN,
+ Bool sigill_diag_IN )
+ {
+ Int i, x1, x2;
+diff --git a/VEX/priv/host_ppc_defs.c b/VEX/priv/host_ppc_defs.c
+index 7c98aeb..95e64f8 100644
+--- a/VEX/priv/host_ppc_defs.c
++++ b/VEX/priv/host_ppc_defs.c
+@@ -3115,24 +3115,42 @@ static UInt vregNo ( HReg v )
+ return n;
+ }
+
+-/* Emit an instruction big-endianly */
++/* Emit an instruction ppc-endianly */
+ static UChar* emit32 ( UChar* p, UInt w32 )
+ {
++#if defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux)
+ *p++ = toUChar((w32 >> 24) & 0x000000FF);
+ *p++ = toUChar((w32 >> 16) & 0x000000FF);
+ *p++ = toUChar((w32 >> 8) & 0x000000FF);
+ *p++ = toUChar((w32) & 0x000000FF);
++#elif defined(VGP_ppc64le_linux)
++ *p++ = toUChar((w32) & 0x000000FF);
++ *p++ = toUChar((w32 >> 8) & 0x000000FF);
++ *p++ = toUChar((w32 >> 16) & 0x000000FF);
++ *p++ = toUChar((w32 >> 24) & 0x000000FF);
++#else
++ //error Unknown variant of PowerPC
++#endif
+ return p;
+ }
+
+-/* Fetch an instruction big-endianly */
++/* Fetch an instruction ppc-endianly */
+ static UInt fetch32 ( UChar* p )
+ {
+ UInt w32 = 0;
++#if defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux)
+ w32 |= ((0xFF & (UInt)p[0]) << 24);
+ w32 |= ((0xFF & (UInt)p[1]) << 16);
+ w32 |= ((0xFF & (UInt)p[2]) << 8);
+ w32 |= ((0xFF & (UInt)p[3]) << 0);
++#elif defined(VGP_ppc64le_linux)
++ w32 |= ((0xFF & (UInt)p[3]) << 24);
++ w32 |= ((0xFF & (UInt)p[2]) << 16);
++ w32 |= ((0xFF & (UInt)p[1]) << 8);
++ w32 |= ((0xFF & (UInt)p[0]) << 0);
++#else
++ //error Unknown variant of PowerPC
++#endif
+ return w32;
+ }
+
+diff --git a/VEX/priv/host_ppc_isel.c b/VEX/priv/host_ppc_isel.c
+index d35ea6d..eb58ba3 100644
+--- a/VEX/priv/host_ppc_isel.c
++++ b/VEX/priv/host_ppc_isel.c
+@@ -47,6 +47,11 @@
+ /* GPR register class for ppc32/64 */
+ #define HRcGPR(__mode64) (__mode64 ? HRcInt64 : HRcInt32)
+
++#if defined(VGP_ppc64le_linux)
++#define IENDIANESS Iend_LE
++#else
++#define IENDIANESS Iend_BE
++#endif
+
+ /*---------------------------------------------------------*/
+ /*--- Register Usage Conventions ---*/
+@@ -1275,29 +1280,28 @@ static HReg mk_AvDuplicateRI( ISelEnv* env, IRExpr* e )
+ r_src = ri->Pri.Reg;
+ }
+
+- /* default case: store r_src in lowest lane of 16-aligned mem,
+- load vector, splat lowest lane to dst */
+ {
+- /* CAB: Maybe faster to store r_src multiple times (sz dependent),
+- and simply load the vector? */
++ /* Store r_src multiple times (sz dependent); then load the dest vector. */
+ HReg r_aligned16;
+- HReg v_src = newVRegV(env);
+- PPCAMode *am_off12;
++ PPCAMode *am_offset, *am_offset_zero;
+
+ sub_from_sp( env, 32 ); // Move SP down
+ /* Get a 16-aligned address within our stack space */
+ r_aligned16 = get_sp_aligned16( env );
+- am_off12 = PPCAMode_IR( 12, r_aligned16 );
+
+- /* Store r_src in low word of 16-aligned mem */
+- addInstr(env, PPCInstr_Store( 4, am_off12, r_src, env->mode64 ));
++ Int i;
++ Int stride = (sz == 8) ? 1 : (sz == 16) ? 2 : 4;
++ UChar num_bytes_to_store = stride;
++ am_offset_zero = PPCAMode_IR( 0, r_aligned16 );
++ am_offset = am_offset_zero;
++ for (i = 0; i < 16; i+=stride, am_offset = PPCAMode_IR( i, r_aligned16)) {
++ addInstr(env, PPCInstr_Store( num_bytes_to_store, am_offset, r_src, env->mode64 ));
++ }
+
+- /* Load src to vector[low lane] */
+- addInstr(env, PPCInstr_AvLdSt( True/*ld*/, 4, v_src, am_off12 ) );
++ /* Effectively splat the r_src value to dst */
++ addInstr(env, PPCInstr_AvLdSt( True/*ld*/, 4, dst, am_offset_zero ) );
+ add_to_sp( env, 32 ); // Reset SP
+
+- /* Finally, splat v_src[low_lane] to dst */
+- addInstr(env, PPCInstr_AvSplat(sz, dst, PPCVI5s_Reg(v_src)));
+ return dst;
+ }
+ }
+@@ -1382,7 +1386,7 @@ static HReg iselWordExpr_R_wrk ( ISelEnv* env, IRExpr* e )
+ case Iex_Load: {
+ HReg r_dst;
+ PPCAMode* am_addr;
+- if (e->Iex.Load.end != Iend_BE)
++ if (e->Iex.Load.end != IENDIANESS)
+ goto irreducible;
+ r_dst = newVRegI(env);
+ am_addr = iselWordExpr_AMode( env, e->Iex.Load.addr, ty/*of xfer*/ );
+@@ -1828,7 +1832,7 @@ static HReg iselWordExpr_R_wrk ( ISelEnv* env, IRExpr* e )
+ DECLARE_PATTERN(p_LDbe16_then_16Uto32);
+ DEFINE_PATTERN(p_LDbe16_then_16Uto32,
+ unop(Iop_16Uto32,
+- IRExpr_Load(Iend_BE,Ity_I16,bind(0))) );
++ IRExpr_Load(IENDIANESS,Ity_I16,bind(0))) );
+ if (matchIRExpr(&mi,p_LDbe16_then_16Uto32,e)) {
+ HReg r_dst = newVRegI(env);
+ PPCAMode* amode
+@@ -2058,19 +2062,30 @@ static HReg iselWordExpr_R_wrk ( ISelEnv* env, IRExpr* e )
+ HReg r_aligned16;
+ HReg dst = newVRegI(env);
+ HReg vec = iselVecExpr(env, e->Iex.Unop.arg);
+- PPCAMode *am_off0, *am_off12;
++ PPCAMode *am_off0, *am_off_word0;
+ sub_from_sp( env, 32 ); // Move SP down 32 bytes
+
+ // get a quadword aligned address within our stack space
+ r_aligned16 = get_sp_aligned16( env );
+ am_off0 = PPCAMode_IR( 0, r_aligned16 );
+- am_off12 = PPCAMode_IR( 12,r_aligned16 );
++
++ /* Note that the store below (done via PPCInstr_AvLdSt) uses
++ * stvx, which stores the vector in proper LE format,
++ * with byte zero (far right byte of the register in LE format)
++ * stored at the lowest memory address. Therefore, to obtain
++ * integer word zero, we need to use that lowest memory address
++ * as the base for the load.
++ */
++ if (IENDIANESS == Iend_LE)
++ am_off_word0 = am_off0;
++ else
++ am_off_word0 = PPCAMode_IR( 12,r_aligned16 );
+
+ // store vec, load low word to dst
+ addInstr(env,
+ PPCInstr_AvLdSt( False/*store*/, 16, vec, am_off0 ));
+ addInstr(env,
+- PPCInstr_Load( 4, dst, am_off12, mode64 ));
++ PPCInstr_Load( 4, dst, am_off_word0, mode64 ));
+
+ add_to_sp( env, 32 ); // Reset SP
+ return dst;
+@@ -2082,7 +2097,7 @@ static HReg iselWordExpr_R_wrk ( ISelEnv* env, IRExpr* e )
+ HReg r_aligned16;
+ HReg dst = newVRegI(env);
+ HReg vec = iselVecExpr(env, e->Iex.Unop.arg);
+- PPCAMode *am_off0, *am_off8;
++ PPCAMode *am_off0, *am_off8, *am_off_arg;
+ sub_from_sp( env, 32 ); // Move SP down 32 bytes
+
+ // get a quadword aligned address within our stack space
+@@ -2090,13 +2105,24 @@ static HReg iselWordExpr_R_wrk ( ISelEnv* env, IRExpr* e )
+ am_off0 = PPCAMode_IR( 0, r_aligned16 );
+ am_off8 = PPCAMode_IR( 8 ,r_aligned16 );
+
+- // store vec, load low word (+8) or high (+0) to dst
++ // store vec, load low word or high to dst
+ addInstr(env,
+ PPCInstr_AvLdSt( False/*store*/, 16, vec, am_off0 ));
++ if (IENDIANESS == Iend_LE) {
++ if (op_unop == Iop_V128HIto64)
++ am_off_arg = am_off8;
++ else
++ am_off_arg = am_off0;
++ } else {
++ if (op_unop == Iop_V128HIto64)
++ am_off_arg = am_off0;
++ else
++ am_off_arg = am_off8;
++ }
+ addInstr(env,
+ PPCInstr_Load(
+ 8, dst,
+- op_unop == Iop_V128HIto64 ? am_off0 : am_off8,
++ am_off_arg,
+ mode64 ));
+
+ add_to_sp( env, 32 ); // Reset SP
+@@ -2185,7 +2211,6 @@ static HReg iselWordExpr_R_wrk ( ISelEnv* env, IRExpr* e )
+ HReg argregs[1];
+ HReg r_dst = newVRegI(env);
+ Int argreg;
+- HWord* fdescr;
+
+ argiregs = 0;
+ argreg = 0;
+@@ -2196,11 +2221,18 @@ static HReg iselWordExpr_R_wrk ( ISelEnv* env, IRExpr* e )
+ iselWordExpr_R(env, e->Iex.Unop.arg) ) );
+
+ cc = mk_PPCCondCode( Pct_ALWAYS, Pcf_NONE );
+-
+- fdescr = (HWord*)h_calc_BCDtoDPB;
+- addInstr(env, PPCInstr_Call( cc, (Addr64)(fdescr[0]),
++#if defined(VGP_ppc64le_linux)
++ addInstr(env, PPCInstr_Call( cc, (Addr64) h_calc_BCDtoDPB,
+ argiregs, mk_RetLoc_simple(RLPri_Int)) );
+-
++#else
++ {
++ HWord* fdescr;
++ fdescr = (HWord*)h_calc_BCDtoDPB;
++ addInstr(env, PPCInstr_Call( cc, (Addr64)(fdescr[0]),
++ argiregs,
++ mk_RetLoc_simple(RLPri_Int)) );
++ }
++#endif
+ addInstr(env, mk_iMOVds_RR(r_dst, argregs[0]));
+ return r_dst;
+ }
+@@ -2214,7 +2246,6 @@ static HReg iselWordExpr_R_wrk ( ISelEnv* env, IRExpr* e )
+ HReg argregs[1];
+ HReg r_dst = newVRegI(env);
+ Int argreg;
+- HWord* fdescr;
+
+ argiregs = 0;
+ argreg = 0;
+@@ -2225,11 +2256,18 @@ static HReg iselWordExpr_R_wrk ( ISelEnv* env, IRExpr* e )
+ iselWordExpr_R(env, e->Iex.Unop.arg) ) );
+
+ cc = mk_PPCCondCode( Pct_ALWAYS, Pcf_NONE );
+-
+- fdescr = (HWord*)h_calc_DPBtoBCD;
+- addInstr(env, PPCInstr_Call( cc, (Addr64)(fdescr[0]),
++#if defined(VGP_ppc64le_linux)
++ addInstr(env, PPCInstr_Call( cc, (Addr64)(h_calc_DPBtoBCD),
+ argiregs, mk_RetLoc_simple(RLPri_Int) ) );
+-
++#else
++ {
++ HWord* fdescr;
++ fdescr = (HWord*)h_calc_DPBtoBCD;
++ addInstr(env, PPCInstr_Call( cc, (Addr64)(fdescr[0]),
++ argiregs,
++ mk_RetLoc_simple(RLPri_Int) ) );
++ }
++#endif
+ addInstr(env, mk_iMOVds_RR(r_dst, argregs[0]));
+ return r_dst;
+ }
+@@ -3075,7 +3113,7 @@ static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo,
+ vassert(typeOfIRExpr(env->type_env,e) == Ity_I64);
+
+ /* 64-bit load */
+- if (e->tag == Iex_Load && e->Iex.Load.end == Iend_BE) {
++ if (e->tag == Iex_Load && e->Iex.Load.end == IENDIANESS) {
+ HReg tLo = newVRegI(env);
+ HReg tHi = newVRegI(env);
+ HReg r_addr = iselWordExpr_R(env, e->Iex.Load.addr);
+@@ -3552,7 +3590,6 @@ static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo,
+ HReg tHi = newVRegI(env);
+ HReg tmpHi;
+ HReg tmpLo;
+- ULong target;
+ Bool mode64 = env->mode64;
+
+ argregs[0] = hregPPC_GPR3(mode64);
+@@ -3570,11 +3607,19 @@ static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo,
+ addInstr( env, mk_iMOVds_RR( argregs[argreg], tmpLo ) );
+
+ cc = mk_PPCCondCode( Pct_ALWAYS, Pcf_NONE );
+- target = toUInt( Ptr_to_ULong(h_calc_BCDtoDPB ) );
+-
+- addInstr( env, PPCInstr_Call( cc, (Addr64)target,
++#if defined(VGP_ppc64le_linux)
++ addInstr( env, PPCInstr_Call( cc, (Addr64)h_calc_BCDtoDPB,
+ argiregs,
+ mk_RetLoc_simple(RLPri_2Int) ) );
++#else
++ {
++ ULong target;
++ target = toUInt( Ptr_to_ULong(h_calc_BCDtoDPB ) );
++ addInstr( env, PPCInstr_Call( cc, (Addr64)target,
++ argiregs,
++ mk_RetLoc_simple(RLPri_2Int) ) );
++ }
++#endif
+ addInstr( env, mk_iMOVds_RR( tHi, argregs[argreg-1] ) );
+ addInstr( env, mk_iMOVds_RR( tLo, argregs[argreg] ) );
+
+@@ -3592,7 +3637,6 @@ static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo,
+ HReg tHi = newVRegI(env);
+ HReg tmpHi;
+ HReg tmpLo;
+- ULong target;
+ Bool mode64 = env->mode64;
+
+ argregs[0] = hregPPC_GPR3(mode64);
+@@ -3611,10 +3655,18 @@ static void iselInt64Expr_wrk ( HReg* rHi, HReg* rLo,
+
+ cc = mk_PPCCondCode( Pct_ALWAYS, Pcf_NONE );
+
+- target = toUInt( Ptr_to_ULong( h_calc_DPBtoBCD ) );
+-
+- addInstr(env, PPCInstr_Call( cc, (Addr64)target, argiregs,
++#if defined(VGP_ppc64le_linux)
++ addInstr(env, PPCInstr_Call( cc, (Addr64)h_calc_DPBtoBCD, argiregs,
+ mk_RetLoc_simple(RLPri_2Int) ) );
++#else
++ {
++ ULong target;
++ target = toUInt( Ptr_to_ULong( h_calc_DPBtoBCD ) );
++ addInstr(env, PPCInstr_Call( cc, (Addr64)target, argiregs,
++ mk_RetLoc_simple(RLPri_2Int) ) );
++ }
++#endif
++
+ addInstr(env, mk_iMOVds_RR(tHi, argregs[argreg-1]));
+ addInstr(env, mk_iMOVds_RR(tLo, argregs[argreg]));
+
+@@ -3664,7 +3716,7 @@ static HReg iselFltExpr_wrk ( ISelEnv* env, IRExpr* e )
+ return lookupIRTemp(env, e->Iex.RdTmp.tmp);
+ }
+
+- if (e->tag == Iex_Load && e->Iex.Load.end == Iend_BE) {
++ if (e->tag == Iex_Load && e->Iex.Load.end == IENDIANESS) {
+ PPCAMode* am_addr;
+ HReg r_dst = newVRegF(env);
+ vassert(e->Iex.Load.ty == Ity_F32);
+@@ -3866,7 +3918,7 @@ static HReg iselDblExpr_wrk ( ISelEnv* env, IRExpr* e )
+ }
+
+ /* --------- LOAD --------- */
+- if (e->tag == Iex_Load && e->Iex.Load.end == Iend_BE) {
++ if (e->tag == Iex_Load && e->Iex.Load.end == IENDIANESS) {
+ HReg r_dst = newVRegF(env);
+ PPCAMode* am_addr;
+ vassert(e->Iex.Load.ty == Ity_F64);
+@@ -4127,7 +4179,7 @@ static HReg iselDfp32Expr_wrk(ISelEnv* env, IRExpr* e)
+ }
+
+ /* --------- LOAD --------- */
+- if (e->tag == Iex_Load && e->Iex.Load.end == Iend_BE) {
++ if (e->tag == Iex_Load && e->Iex.Load.end == IENDIANESS) {
+ PPCAMode* am_addr;
+ HReg r_dst = newVRegF(env);
+ vassert(e->Iex.Load.ty == Ity_D32);
+@@ -4182,7 +4234,7 @@ static HReg iselDfp64Expr_wrk(ISelEnv* env, IRExpr* e)
+ return r_dst;
+ }
+
+- if (e->tag == Iex_Load && e->Iex.Load.end == Iend_BE) {
++ if (e->tag == Iex_Load && e->Iex.Load.end == IENDIANESS) {
+ PPCAMode* am_addr;
+ HReg r_dst = newVRegF(env);
+ vassert(e->Iex.Load.ty == Ity_D64);
+@@ -4732,7 +4784,7 @@ static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e )
+ return dst;
+ }
+
+- if (e->tag == Iex_Load && e->Iex.Load.end == Iend_BE) {
++ if (e->tag == Iex_Load && e->Iex.Load.end == IENDIANESS) {
+ PPCAMode* am_addr;
+ HReg v_dst = newVRegV(env);
+ vassert(e->Iex.Load.ty == Ity_V128);
+@@ -4826,15 +4878,24 @@ static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e )
+ /* Store zeros */
+ r_zeros = newVRegI(env);
+ addInstr(env, PPCInstr_LI(r_zeros, 0x0, mode64));
+- addInstr(env, PPCInstr_Store( 4, am_off0, r_zeros, mode64 ));
++ if (IENDIANESS == Iend_LE)
++ addInstr(env, PPCInstr_Store( 4, am_off0, r_src, mode64 ));
++ else
++ addInstr(env, PPCInstr_Store( 4, am_off0, r_zeros, mode64 ));
+ addInstr(env, PPCInstr_Store( 4, am_off4, r_zeros, mode64 ));
+ addInstr(env, PPCInstr_Store( 4, am_off8, r_zeros, mode64 ));
+
+ /* Store r_src in low word of quadword-aligned mem */
+- addInstr(env, PPCInstr_Store( 4, am_off12, r_src, mode64 ));
++ if (IENDIANESS == Iend_LE)
++ addInstr(env, PPCInstr_Store( 4, am_off12, r_zeros, mode64 ));
++ else
++ addInstr(env, PPCInstr_Store( 4, am_off12, r_src, mode64 ));
+
+ /* Load word into low word of quadword vector reg */
+- addInstr(env, PPCInstr_AvLdSt( True/*ld*/, 4, dst, am_off12 ));
++ if (IENDIANESS == Iend_LE)
++ addInstr(env, PPCInstr_AvLdSt( True/*ld*/, 4, dst, am_off0 ));
++ else
++ addInstr(env, PPCInstr_AvLdSt( True/*ld*/, 4, dst, am_off12 ));
+
+ add_to_sp( env, 32 ); // Reset SP
+ return dst;
+@@ -4918,9 +4979,13 @@ static HReg iselVecExpr_wrk ( ISelEnv* env, IRExpr* e )
+ am_off8 = PPCAMode_IR( 8, r_aligned16 );
+
+ /* Store 2*I64 to stack */
+- addInstr(env, PPCInstr_Store( 8, am_off0, rHi, mode64 ));
+- addInstr(env, PPCInstr_Store( 8, am_off8, rLo, mode64 ));
+-
++ if (IENDIANESS == Iend_LE) {
++ addInstr(env, PPCInstr_Store( 8, am_off0, rLo, mode64 ));
++ addInstr(env, PPCInstr_Store( 8, am_off8, rHi, mode64 ));
++ } else {
++ addInstr(env, PPCInstr_Store( 8, am_off0, rHi, mode64 ));
++ addInstr(env, PPCInstr_Store( 8, am_off8, rLo, mode64 ));
++ }
+ /* Fetch result back from stack. */
+ addInstr(env, PPCInstr_AvLdSt(True/*ld*/, 16, dst, am_off0));
+
+@@ -5274,7 +5339,7 @@ static void iselStmt ( ISelEnv* env, IRStmt* stmt )
+ IRType tyd = typeOfIRExpr(env->type_env, stmt->Ist.Store.data);
+ IREndness end = stmt->Ist.Store.end;
+
+- if (end != Iend_BE)
++ if (end != IENDIANESS)
+ goto stmt_fail;
+ if (!mode64 && (tya != Ity_I32))
+ goto stmt_fail;
+@@ -5532,7 +5597,7 @@ static void iselStmt ( ISelEnv* env, IRStmt* stmt )
+ IRType tyRes = typeOfIRTemp(env->type_env, res);
+ IRType tyAddr = typeOfIRExpr(env->type_env, stmt->Ist.LLSC.addr);
+
+- if (stmt->Ist.LLSC.end != Iend_BE)
++ if (stmt->Ist.LLSC.end != IENDIANESS)
+ goto stmt_fail;
+ if (!mode64 && (tyAddr != Ity_I32))
+ goto stmt_fail;
+diff --git a/VEX/priv/main_main.c b/VEX/priv/main_main.c
+index 495942a..c02c425 100644
+--- a/VEX/priv/main_main.c
++++ b/VEX/priv/main_main.c
+@@ -377,7 +377,15 @@ VexTranslateResult LibVEX_Translate ( VexTranslateArgs* vta )
+ emit = (Int(*)(Bool*,UChar*,Int,HInstr*,Bool,
+ void*,void*,void*,void*))
+ emit_PPCInstr;
++#if defined(VGP_ppc64be_linux)
+ host_is_bigendian = True;
++#elif defined(VGP_ppc64le_linux)
++ host_is_bigendian = False;
++#else
++ /* unknown varient of PPC64 */
++ vex_printf("ERROR: call to getUIntPPCendianly(); Unknown variant of PowerPC\n");
++#endif
++
+ host_word_type = Ity_I64;
+ vassert(are_valid_hwcaps(VexArchPPC64, vta->archinfo_host.hwcaps));
+ break;
+diff --git a/coregrind/launcher-darwin.c b/coregrind/launcher-darwin.c
+index 1f99026..8449285 100644
+--- a/coregrind/launcher-darwin.c
++++ b/coregrind/launcher-darwin.c
+@@ -64,6 +64,7 @@ static struct {
+ { CPU_TYPE_ARM, "arm", "arm" },
+ { CPU_TYPE_POWERPC, "ppc", "ppc32" },
+ { CPU_TYPE_POWERPC64BE, "ppc64be", "ppc64be" },
++ { CPU_TYPE_POWERPC64LE, "ppc64le", "ppc64le" },
+ };
+ static int valid_archs_count = sizeof(valid_archs)/sizeof(valid_archs[0]);
+
+diff --git a/coregrind/launcher-linux.c b/coregrind/launcher-linux.c
+index 38e4857..4f6b274 100644
+--- a/coregrind/launcher-linux.c
++++ b/coregrind/launcher-linux.c
+@@ -228,6 +228,10 @@ static const char *select_platform(const char *clientname)
+ (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV ||
+ ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
+ platform = "arm64-linux";
++ } else if (ehdr->e_machine == EM_PPC64 &&
++ (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV ||
++ ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
++ platform = "ppc64le-linux";
+ }
+ } else if (header[EI_DATA] == ELFDATA2MSB) {
+ # if !defined(VGPV_arm_linux_android) \
+@@ -321,6 +325,7 @@ int main(int argc, char** argv, char** envp)
+ (0==strcmp(VG_PLATFORM,"amd64-linux")) ||
+ (0==strcmp(VG_PLATFORM,"ppc32-linux")) ||
+ (0==strcmp(VG_PLATFORM,"ppc64be-linux")) ||
++ (0==strcmp(VG_PLATFORM,"ppc64le-linux")) ||
+ (0==strcmp(VG_PLATFORM,"arm-linux")) ||
+ (0==strcmp(VG_PLATFORM,"arm64-linux")) ||
+ (0==strcmp(VG_PLATFORM,"s390x-linux")) ||
+diff --git a/coregrind/m_coredump/coredump-elf.c b/coregrind/m_coredump/coredump-elf.c
+index 08ddddd..cba4204 100644
+--- a/coregrind/m_coredump/coredump-elf.c
++++ b/coregrind/m_coredump/coredump-elf.c
+@@ -343,6 +343,27 @@ static void fill_prstatus(const ThreadState *tst,
+ regs->dsisr = 0;
+ regs->result = 0;
+
++#elif defined(VGP_ppc64le_linux)
++# define DO(n) regs->gpr[n] = arch->vex.guest_GPR##n
++ DO(0); DO(1); DO(2); DO(3); DO(4); DO(5); DO(6); DO(7);
++ DO(8); DO(9); DO(10); DO(11); DO(12); DO(13); DO(14); DO(15);
++ DO(16); DO(17); DO(18); DO(19); DO(20); DO(21); DO(22); DO(23);
++ DO(24); DO(25); DO(26); DO(27); DO(28); DO(29); DO(30); DO(31);
++# undef DO
++
++ regs->nip = arch->vex.guest_CIA;
++ regs->msr = 0xf033; /* pretty arbitrary */
++ regs->orig_gpr3 = arch->vex.guest_GPR3;
++ regs->ctr = arch->vex.guest_CTR;
++ regs->link = arch->vex.guest_LR;
++ regs->xer = LibVEX_GuestPPC64_get_XER( &((ThreadArchState*)arch)->vex );
++ regs->ccr = LibVEX_GuestPPC64_get_CR( &((ThreadArchState*)arch)->vex );
++ /* regs->mq = 0; */
++ regs->trap = 0;
++ regs->dar = 0; /* should be fault address? */
++ regs->dsisr = 0;
++ regs->result = 0;
++
+ #elif defined(VGP_arm_linux)
+ regs->ARM_r0 = arch->vex.guest_R0;
+ regs->ARM_r1 = arch->vex.guest_R1;
+diff --git a/coregrind/m_debuginfo/debuginfo.c b/coregrind/m_debuginfo/debuginfo.c
+index 421ccf3..923636f 100644
+--- a/coregrind/m_debuginfo/debuginfo.c
++++ b/coregrind/m_debuginfo/debuginfo.c
+@@ -1,4 +1,5 @@
+
++
+ /*--------------------------------------------------------------------*/
+ /*--- Top level management of symbols and debugging information. ---*/
+ /*--- debuginfo.c ---*/
+@@ -4079,6 +4080,7 @@ void VG_(DebugInfo_syms_getidx) ( const DebugInfo *si,
+ Int idx,
+ /*OUT*/Addr* avma,
+ /*OUT*/Addr* tocptr,
++ /*OUT*/Addr* second_ep,
+ /*OUT*/UInt* size,
+ /*OUT*/HChar** pri_name,
+ /*OUT*/HChar*** sec_names,
+@@ -4088,6 +4090,7 @@ void VG_(DebugInfo_syms_getidx) ( const DebugInfo *si,
+ vg_assert(idx >= 0 && idx < si->symtab_used);
+ if (avma) *avma = si->symtab[idx].addr;
+ if (tocptr) *tocptr = si->symtab[idx].tocptr;
++ if (second_ep) *second_ep = si->symtab[idx].second_ep;
+ if (size) *size = si->symtab[idx].size;
+ if (pri_name) *pri_name = si->symtab[idx].pri_name;
+ if (sec_names) *sec_names = (HChar **)si->symtab[idx].sec_names; // FIXME
+diff --git a/coregrind/m_debuginfo/priv_storage.h b/coregrind/m_debuginfo/priv_storage.h
+index 63328ef..d485517 100644
+--- a/coregrind/m_debuginfo/priv_storage.h
++++ b/coregrind/m_debuginfo/priv_storage.h
+@@ -71,7 +71,8 @@
+ typedef
+ struct {
+ Addr addr; /* lowest address of entity */
+- Addr tocptr; /* ppc64-linux only: value that R2 should have */
++ Addr tocptr; /* ppc64be-linux only: value that R2 should have */
++ Addr second_ep; /* address for secondary entry point, ppc64le */
+ HChar* pri_name; /* primary name, never NULL */
+ HChar** sec_names; /* NULL, or a NULL term'd array of other names */
+ // XXX: this could be shrunk (on 32-bit platforms) by using 30
+@@ -791,7 +792,7 @@ struct _DebugInfo {
+ Bool gotplt_present;
+ Addr gotplt_avma;
+ SizeT gotplt_size;
+- /* .opd -- needed on ppc64-linux for finding symbols */
++ /* .opd -- needed on ppc64be-linux for finding symbols */
+ Bool opd_present;
+ Addr opd_avma;
+ SizeT opd_size;
+diff --git a/coregrind/m_debuginfo/readelf.c b/coregrind/m_debuginfo/readelf.c
+index 21a42cb..d8fb8d6 100644
+--- a/coregrind/m_debuginfo/readelf.c
++++ b/coregrind/m_debuginfo/readelf.c
+@@ -240,7 +240,11 @@ Bool get_elf_symbol_info (
+ Bool* from_opd_out, /* ppc64be-linux only: did we deref an
+ .opd entry? */
+ Bool* is_text_out, /* is this a text symbol? */
+- Bool* is_ifunc /* is this a STT_GNU_IFUNC function ?*/
++ Bool* is_ifunc, /* is this a STT_GNU_IFUNC function ?*/
++ Addr* sym_second_ep /* addr for second entry point. PPC64 LE
++ supports a local and global entry point.
++ Use this value to return the local
++ entry point. */
+ )
+ {
+ Bool plausible;
+@@ -258,6 +262,8 @@ Bool get_elf_symbol_info (
+ *sym_tocptr_out = 0; /* unknown/inapplicable */
+ *from_opd_out = False;
+ *is_ifunc = False;
++ *sym_second_ep = 0; /* unknown/inapplicable */
++
+ /* Get the symbol size, but restrict it to fit in a signed 32 bit
+ int. Also, deal with the stupid case of negative size by making
+ the size be 1. Note that sym->st_size has type UWord,
+@@ -670,23 +676,65 @@ Bool get_elf_symbol_info (
+ }
+
+ # if defined(VGP_ppc64be_linux)
+- /* It's crucial that we never add symbol addresses in the .opd
+- section. This would completely mess up function redirection and
+- intercepting. This assert ensures that any symbols that make it
+- into the symbol table on ppc64-linux don't point into .opd. */
+ if (di->opd_present && di->opd_size > 0) {
+ vg_assert(*sym_avma_out + *sym_size_out <= di->opd_avma
+ || *sym_avma_out >= di->opd_avma + di->opd_size);
+ }
++#endif
++
++# if defined(VGP_ppc64le_linux)
++ /* PPC64 LE ABI uses three bits in the st_other field to indicate the number
++ * of instructions between the function's global and local entry points. An
++ * offset of 0 indicates that there is one entry point. The value must be:
++ *
++ * 0 - one entry point, local and global are the same
++ * 1 - reserved
++ * 2 - local entry point is one instruction after the global entry point
++ * 3 - local entry point is two instructions after the global entry point
++ * 4 - local entry point is four instructions after the global entry point
++ * 5 - local entry point is eight instructions after the global entry point
++ * 6 - local entry point is sixteen two instructions after the global entry point
++ * 7 - reserved
++ *
++ * The extract the three bit field from the other field.
++ * (other_field & STO_PPC64_LOCAL_MASK) >> STO_PPC_LOCAL_BIT
++ *
++ * where the #define values are given in include/elf/powerpc.h file for
++ * the PPC binutils.
++ *
++ * coversion of the three bit field to bytes is given by
++ *
++ * ((1 << bit_field) >> 2) << 2
++ */
++
++ #define STO_PPC64_LOCAL_BIT 5
++ #define STO_PPC64_LOCAL_MASK (7 << STO_PPC64_LOCAL_BIT)
++ {
++ unsigned int bit_field, dist_to_local_entry;
++ /* extract the other filed */
++ bit_field = (sym->st_other & STO_PPC64_LOCAL_MASK) >> STO_PPC64_LOCAL_BIT;
++
++ if ((bit_field > 0) && (bit_field < 7)) {
++ /* store the local entry point address */
++ dist_to_local_entry = ((1 << bit_field) >> 2) << 2;
++ *sym_second_ep = *sym_avma_out + dist_to_local_entry;
++
++ if (TRACE_SYMTAB_ENABLED) {
++ HChar* sym_name = ML_(img_strdup)(escn_strtab->img,
++ "di.gesi.5", sym_name_ioff);
++ VG_(printf)("Second entry point: %s at %#010x\n",
++ sym_name, (unsigned int)*sym_second_ep);
++ }
++ }
++ }
+ # endif
+
+ /* Acquire! */
+ return True;
+ }
+
+-
+ /* Read an ELF symbol table (normal or dynamic). This one is for the
+- "normal" case ({x86,amd64,ppc32,arm,mips32,mips64}-linux). */
++ "normal" case ({x86,amd64,ppc32,arm,mips32,mips64, ppc64le}-linux). */
+ static
+ __attribute__((unused)) /* not referred to on all targets */
+ void read_elf_symtab__normal(
+@@ -725,6 +773,7 @@ void read_elf_symtab__normal(
+ Addr sym_avma_really = 0;
+ Int sym_size = 0;
+ Addr sym_tocptr = 0;
++ Addr sym_second_ep = 0;
+ Bool from_opd = False, is_text = False, is_ifunc = False;
+ DiOffT sym_name_really = DiOffT_INVALID;
+ if (get_elf_symbol_info(di, &sym, sym_name, escn_strtab,
+@@ -734,7 +783,8 @@ void read_elf_symtab__normal(
+ &sym_avma_really,
+ &sym_size,
+ &sym_tocptr,
+- &from_opd, &is_text, &is_ifunc)) {
++ &from_opd, &is_text, &is_ifunc,
++ &sym_second_ep)) {
+
+ DiSym disym;
+ VG_(memset)(&disym, 0, sizeof(disym));
+@@ -742,6 +792,9 @@ void read_elf_symtab__normal(
+ "di.res__n.1", sym_name_really);
+ disym.addr = sym_avma_really;
+ disym.tocptr = sym_tocptr;
++# if defined(VGP_ppc64le_linux)
++ disym.second_ep = sym_second_ep;
++#endif
+ disym.pri_name = ML_(addStr) ( di, cstr, -1 );
+ disym.sec_names = NULL;
+ disym.size = sym_size;
+@@ -749,7 +802,7 @@ void read_elf_symtab__normal(
+ disym.isIFunc = is_ifunc;
+ if (cstr) { ML_(dinfo_free)(cstr); cstr = NULL; }
+ vg_assert(disym.pri_name);
+- vg_assert(disym.tocptr == 0); /* has no role except on ppc64-linux */
++ vg_assert(disym.tocptr == 0); /* has no role except on ppc64be-linux */
+ ML_(addSym) ( di, &disym );
+
+ if (TRACE_SYMTAB_ENABLED) {
+@@ -761,6 +814,10 @@ void read_elf_symtab__normal(
+ (Int)disym.size,
+ (HChar*)disym.pri_name
+ );
++ if (sym_second_ep != 0) {
++ TRACE_SYMTAB(" second entry point %#010lx\n",
++ sym_second_ep)
++ }
+ }
+
+ }
+@@ -856,6 +913,7 @@ void read_elf_symtab__ppc64be_linux(
+ Addr sym_avma_really = 0;
+ Int sym_size = 0;
+ Addr sym_tocptr = 0;
++ Addr sym_second_ep = 0;
+ Bool from_opd = False, is_text = False, is_ifunc = False;
+ DiOffT sym_name_really = DiOffT_INVALID;
+ DiSym disym;
+@@ -867,7 +925,8 @@ void read_elf_symtab__ppc64be_linux(
+ &sym_avma_really,
+ &sym_size,
+ &sym_tocptr,
+- &from_opd, &is_text, &is_ifunc)) {
++ &from_opd, &is_text, &is_ifunc,
++ &sym_second_ep)) {
+
+ /* Check if we've seen this (name,addr) key before. */
+ key.addr = sym_avma_really;
+@@ -2776,6 +2835,7 @@ Bool ML_(read_elf_debug_info) ( struct _DebugInfo* di )
+ # if !defined(VGP_amd64_linux) \
+ && !defined(VGP_s390x_linux) \
+ && !defined(VGP_ppc64be_linux) \
++ && !defined(VGP_ppc64le_linux) \
+ && !defined(VGPV_arm_linux_android) \
+ && !defined(VGPV_x86_linux_android) \
+ && !defined(VGP_mips64_linux)
+diff --git a/coregrind/m_debuginfo/readmacho.c b/coregrind/m_debuginfo/readmacho.c
+index 9926237..95b665c 100644
+--- a/coregrind/m_debuginfo/readmacho.c
++++ b/coregrind/m_debuginfo/readmacho.c
+@@ -199,6 +199,8 @@ static DiSlice map_image_aboard ( DebugInfo* di, /* only for err msgs */
+ Int cputype = CPU_TYPE_POWERPC;
+ # elif defined(VGA_ppc64be)
+ Int cputype = CPU_TYPE_POWERPC64BE;
++# elif defined(VGA_ppc64le)
++ Int cputype = CPU_TYPE_POWERPC64LE;
+ # elif defined(VGA_x86)
+ Int cputype = CPU_TYPE_X86;
+ # elif defined(VGA_amd64)
+diff --git a/coregrind/m_dispatch/dispatch-ppc64-linux.S b/coregrind/m_dispatch/dispatch-ppc64-linux.S
+index 35cefdf..0fadef6 100644
+--- a/coregrind/m_dispatch/dispatch-ppc64-linux.S
++++ b/coregrind/m_dispatch/dispatch-ppc64-linux.S
+@@ -35,6 +35,15 @@
+ #include "pub_core_transtab_asm.h"
+ #include "libvex_guest_offsets.h" /* for OFFSET_ppc64_CIA */
+
++/* NOTE: PPC64 supports Big Endian and Little Endian. It also supports the
++ ELF version 1 and ELF version 2 APIs.
++
++ Currently LE uses ELF version 2 and BE uses ELF version 1. However,
++ BE and LE may support the other ELF version in the future. So, the
++ _CALL_ELF is used in the assembly function to enable code for a
++ specific ELF version independently of the Enianess of the machine.
++ The test "#if _CALL_ELF == 2" checks if ELF version 2 is being used.
++*/
+
+ /* References to globals via the TOC */
+
+@@ -74,14 +83,26 @@ void VG_(disp_run_translations)( UWord* two_words,
+ .section ".text"
+ .align 2
+ .globl VG_(disp_run_translations)
++#if !defined VGP_ppc64be_linux || _CALL_ELF == 2
++.type VG_(disp_run_translations), at function
++VG_(disp_run_translations):
++.type .VG_(disp_run_translations), at function
++#else
+ .section ".opd","aw"
+ .align 3
+ VG_(disp_run_translations):
+ .quad .VG_(disp_run_translations),.TOC. at tocbase,0
+ .previous
+ .type .VG_(disp_run_translations), at function
++#endif
+ .globl .VG_(disp_run_translations)
+ .VG_(disp_run_translations):
++#if _CALL_ELF == 2
++0: addis 2, 12,.TOC.-0b at ha
++ addi 2,2,.TOC.-0b at l
++ .localentry VG_(disp_run_translations), .-VG_(disp_run_translations)
++#endif
++
+ /* r3 holds two_words */
+ /* r4 holds guest_state */
+ /* r5 holds host_addr */
+@@ -228,8 +249,13 @@ VG_(disp_run_translations):
+ /* make a stack frame for the code we are calling */
+ stdu 1,-48(1)
+
+- /* Set up the guest state ptr */
++ /* Set up the guest state ptr */
+ mr 31,4 /* r31 (generated code gsp) = r4 */
++#if _CALL_ELF == 2
++/* for the LE ABI need to setup r2 and r12 */
++0: addis 2, 12,.TOC.-0b at ha
++ addi 2,2,.TOC.-0b at l
++#endif
+
+ /* and jump into the code cache. Chained translations in
+ the code cache run, until for whatever reason, they can't
+@@ -384,6 +410,9 @@ VG_(disp_run_translations):
+ mtlr 0
+ addi 1,1,624 /* stack_size */
+ blr
++#if !defined VGP_ppc64be_linux || _CALL_ELF == 2
++ .size VG_(disp_run_translations),.-VG_(disp_run_translations)
++#endif
+
+
+ /*----------------------------------------------------*/
+@@ -394,15 +423,25 @@ VG_(disp_run_translations):
+ .section ".text"
+ .align 2
+ .globl VG_(disp_cp_chain_me_to_slowEP)
+- .section ".opd","aw"
++#if !defined VGP_ppc64be_linux || _CALL_ELF == 2
++ .type VG_(disp_cp_chain_me_to_slowEP), at function
++ VG_(disp_cp_chain_me_to_slowEP):
++#else
++ .section ".opd","aw"
+ .align 3
+ VG_(disp_cp_chain_me_to_slowEP):
+ .quad .VG_(disp_cp_chain_me_to_slowEP),.TOC. at tocbase,0
+ .previous
++#endif
+ .type .VG_(disp_cp_chain_me_to_slowEP), at function
+ .globl .VG_(disp_cp_chain_me_to_slowEP)
+ .VG_(disp_cp_chain_me_to_slowEP):
+- /* We got called. The return address indicates
++#if _CALL_ELF == 2
++0: addis 2, 12,.TOC.-0b at ha
++ addi 2,2,.TOC.-0b at l
++ .localentry VG_(disp_cp_chain_me_to_slowEP), .-VG_(disp_cp_chain_me_to_slowEP)
++#endif
++ /* We got called. The return address indicates
+ where the patching needs to happen. Collect
+ the return address and, exit back to C land,
+ handing the caller the pair (Chain_me_S, RA) */
+@@ -414,20 +453,33 @@ VG_(disp_cp_chain_me_to_slowEP):
+ */
+ subi 7,7,20+4+4
+ b .postamble
++#if !defined VGP_ppc64be_linux || _CALL_ELF == 2
++ .size VG_(disp_cp_chain_me_to_slowEP),.-VG_(disp_cp_chain_me_to_slowEP)
++#endif
+
+ /* ------ Chain me to fast entry point ------ */
+ .section ".text"
+ .align 2
+ .globl VG_(disp_cp_chain_me_to_fastEP)
+- .section ".opd","aw"
++#if !defined VGP_ppc64be_linux || _CALL_ELF == 2
++ .type VG_(disp_cp_chain_me_to_fastEP), at function
++VG_(disp_cp_chain_me_to_fastEP):
++#else
++ .section ".opd","aw"
+ .align 3
+ VG_(disp_cp_chain_me_to_fastEP):
+ .quad .VG_(disp_cp_chain_me_to_fastEP),.TOC. at tocbase,0
+ .previous
++#endif
+ .type .VG_(disp_cp_chain_me_to_fastEP), at function
+ .globl .VG_(disp_cp_chain_me_to_fastEP)
+ .VG_(disp_cp_chain_me_to_fastEP):
+- /* We got called. The return address indicates
++#if _CALL_ELF == 2
++0: addis 2, 12,.TOC.-0b at ha
++ addi 2,2,.TOC.-0b at l
++ .localentry VG_(disp_cp_chain_me_to_fastEP), .-VG_(disp_cp_chain_me_to_fastEP)
++#endif
++ /* We got called. The return address indicates
+ where the patching needs to happen. Collect
+ the return address and, exit back to C land,
+ handing the caller the pair (Chain_me_S, RA) */
+@@ -439,20 +491,33 @@ VG_(disp_cp_chain_me_to_fastEP):
+ */
+ subi 7,7,20+4+4
+ b .postamble
++#if !defined VGP_ppc64be_linux || _CALL_ELF == 2
++ .size VG_(disp_cp_chain_me_to_fastEP),.-VG_(disp_cp_chain_me_to_fastEP)
++#endif
+
+ /* ------ Indirect but boring jump ------ */
+ .section ".text"
+ .align 2
+ .globl VG_(disp_cp_xindir)
+- .section ".opd","aw"
++#if !defined VGP_ppc64be_linux || _CALL_ELF == 2
++ .type VG_(disp_cp_xindir), at function
++VG_(disp_cp_xindir):
++#else
++ .section ".opd","aw"
+ .align 3
+ VG_(disp_cp_xindir):
+ .quad .VG_(disp_cp_xindir),.TOC. at tocbase,0
+ .previous
++#endif
+ .type .VG_(disp_cp_xindir), at function
+ .globl .VG_(disp_cp_xindir)
+ .VG_(disp_cp_xindir):
+- /* Where are we going? */
++#if _CALL_ELF == 2
++0: addis 2, 12,.TOC.-0b at ha
++ addi 2,2,.TOC.-0b at l
++ .localentry VG_(disp_cp_xindir), .-VG_(disp_cp_xindir)
++#endif
++ /* Where are we going? */
+ ld 3,OFFSET_ppc64_CIA(31)
+
+ /* stats only */
+@@ -478,6 +543,9 @@ VG_(disp_cp_xindir):
+ /* Found a match. Jump to .host. */
+ mtctr 7
+ bctr
++#if !defined VGP_ppc64be_linux || _CALL_ELF == 2
++ .size VG_(disp_cp_xindir),.-VG_(disp_cp_xindir)
++#endif
+
+ .fast_lookup_failed:
+ /* stats only */
+@@ -495,36 +563,61 @@ VG_(disp_cp_xindir):
+ .section ".text"
+ .align 2
+ .globl VG_(disp_cp_xassisted)
+- .section ".opd","aw"
++#if !defined VGP_ppc64be_linux || _CALL_ELF == 2
++ .type VG_(disp_cp_xassisted), at function
++VG_(disp_cp_xassisted):
++#else
++ .section ".opd","aw"
+ .align 3
+ VG_(disp_cp_xassisted):
+ .quad .VG_(disp_cp_xassisted),.TOC. at tocbase,0
+ .previous
+- .type .VG_(disp_cp_xassisted), at function
++#endif
++#if _CALL_ELF == 2
++0: addis 2, 12,.TOC.-0b at ha
++ addi 2,2,.TOC.-0b at l
++ .localentry VG_(disp_cp_xassisted), .-VG_(disp_cp_xassisted)
++#endif
++ .type .VG_(disp_cp_xassisted), at function
+ .globl .VG_(disp_cp_xassisted)
+ .VG_(disp_cp_xassisted):
+ /* r31 contains the TRC */
+ mr 6,31
+ li 7,0
+ b .postamble
++#if !defined VGP_ppc64be_linux || _CALL_ELF == 2
++ .size VG_(disp_cp_xassisted),.-VG_(disp_cp_xassisted)
++#endif
+
+ /* ------ Event check failed ------ */
+ .section ".text"
+ .align 2
+ .globl VG_(disp_cp_evcheck_fail)
+- .section ".opd","aw"
++#if !defined VGP_ppc64be_linux || _CALL_ELF == 2
++ .type VG_(disp_cp_evcheck_fail), at function
++VG_(disp_cp_evcheck_fail):
++#else
++ .section ".opd","aw"
+ .align 3
+ VG_(disp_cp_evcheck_fail):
+ .quad .VG_(disp_cp_evcheck_fail),.TOC. at tocbase,0
+ .previous
++#endif
++#if _CALL_ELF == 2
++0: addis 2, 12,.TOC.-0b at ha
++ addi 2,2,.TOC.-0b at l
++ .localentry VG_(disp_cp_evcheck_fail), .-VG_(disp_cp_evcheck_fail)
++#endif
+ .type .VG_(disp_cp_evcheck_fail), at function
+ .globl .VG_(disp_cp_evcheck_fail)
+ .VG_(disp_cp_evcheck_fail):
+ li 6,VG_TRC_INNER_COUNTERZERO
+ li 7,0
+ b .postamble
++#if !defined VGP_ppc64be_linux || _CALL_ELF == 2
++ .size VG_(disp_cp_evcheck_fail),.-VG_(disp_cp_evcheck_fail)
++#endif
+
+-
+ .size .VG_(disp_run_translations), .-.VG_(disp_run_translations)
+
+ /* Let the linker know we don't need an executable stack */
+diff --git a/coregrind/m_initimg/initimg-linux.c b/coregrind/m_initimg/initimg-linux.c
+index b4c6d92..400fa1b 100644
+--- a/coregrind/m_initimg/initimg-linux.c
++++ b/coregrind/m_initimg/initimg-linux.c
+@@ -742,7 +742,7 @@ Addr setup_client_stack( void* init_sp,
+ break;
+
+ # if !defined(VGP_ppc32_linux) && !defined(VGP_ppc64be_linux) \
+- && !defined(VGP_ppc64le)
++ && !defined(VGP_ppc64le_linux)
+ case AT_SYSINFO_EHDR: {
+ /* Trash this, because we don't reproduce it */
+ const NSegment* ehdrseg = VG_(am_find_nsegment)((Addr)auxv->u.a_ptr);
+@@ -1043,6 +1043,9 @@ void VG_(ii_finalise_image)( IIFinaliseImageInfo iifii )
+ arch->vex.guest_GPR1 = iifii.initial_client_SP;
+ arch->vex.guest_GPR2 = iifii.initial_client_TOC;
+ arch->vex.guest_CIA = iifii.initial_client_IP;
++#if defined(VGP_ppc64le_linux)
++ arch->vex.guest_GPR12 = iifii.initial_client_IP;
++#endif
+
+ # elif defined(VGP_arm_linux)
+ /* Zero out the initial state, and set up the simulated FPU in a
+diff --git a/coregrind/m_libcsetjmp.c b/coregrind/m_libcsetjmp.c
+index 488e8e8..df56e3b 100644
+--- a/coregrind/m_libcsetjmp.c
++++ b/coregrind/m_libcsetjmp.c
+@@ -158,7 +158,6 @@ __asm__(
+ ".align 2" "\n"
+ ".p2align 4,,15" "\n"
+ ".globl VG_MINIMAL_SETJMP" "\n"
+-
+ ".section \".opd\",\"aw\"" "\n"
+ ".align 3" "\n"
+ "VG_MINIMAL_SETJMP:" "\n"
+@@ -267,9 +266,114 @@ __asm__(
+ "" "\n"
+
+ ".previous" "\n"
+-".previous" "\n"
+ );
+
++#elif defined(VGP_ppc64le_linux)
++__asm__(
++".section \".toc\",\"aw\"" "\n"
++
++".section \".text\"" "\n"
++".align 2" "\n"
++".p2align 4,,15" "\n"
++".globl VG_MINIMAL_SETJMP" "\n"
++".type VG_MINIMAL_SETJMP, at function" "\n"
++"VG_MINIMAL_SETJMP:" "\n"
++" .localentry VG_MINIMAL_SETJMP, .-VG_MINIMAL_SETJMP" "\n"
++" std 0, 0(3)" "\n"
++" std 1, 8(3)" "\n"
++" std 2, 16(3)" "\n"
++" std 3, 24(3)" "\n"
++" std 4, 32(3)" "\n"
++" std 5, 40(3)" "\n"
++" std 6, 48(3)" "\n"
++" std 7, 56(3)" "\n"
++" std 8, 64(3)" "\n"
++" std 9, 72(3)" "\n"
++" std 10, 80(3)" "\n"
++" std 11, 88(3)" "\n"
++" std 12, 96(3)" "\n"
++" std 13, 104(3)" "\n"
++" std 14, 112(3)" "\n"
++" std 15, 120(3)" "\n"
++" std 16, 128(3)" "\n"
++" std 17, 136(3)" "\n"
++" std 18, 144(3)" "\n"
++" std 19, 152(3)" "\n"
++" std 20, 160(3)" "\n"
++" std 21, 168(3)" "\n"
++" std 22, 176(3)" "\n"
++" std 23, 184(3)" "\n"
++" std 24, 192(3)" "\n"
++" std 25, 200(3)" "\n"
++" std 26, 208(3)" "\n"
++" std 27, 216(3)" "\n"
++" std 28, 224(3)" "\n"
++" std 29, 232(3)" "\n"
++" std 30, 240(3)" "\n"
++" std 31, 248(3)" "\n"
++// must use a caller-save register here as scratch, hence r4
++" mflr 4" "\n"
++" std 4, 256(3)" "\n"
++" mfcr 4" "\n"
++" std 4, 264(3)" "\n"
++" li 3, 0" "\n"
++" blr" "\n"
++"" "\n"
++
++
++".globl VG_MINIMAL_LONGJMP" "\n"
++".type VG_MINIMAL_LONGJMP, @function" "\n"
++"VG_MINIMAL_LONGJMP:" "\n"
++" .localentry VG_MINIMAL_LONGJMP, .-VG_MINIMAL_LONGJMP" "\n"
++ // do r4 = 1
++ // and park it in the restore slot for r3 (the ret reg)
++" li 4, 1" "\n"
++" std 4, 24(3)" "\n"
++ // restore everything except r3
++ // then r3 last of all
++ // then blr
++" ld 0, 256(3)" "\n"
++" mtlr 0" "\n"
++" ld 0, 264(3)" "\n"
++" mtcr 0" "\n"
++" ld 0, 0(3)" "\n"
++" ld 1, 8(3)" "\n"
++" ld 2, 16(3)" "\n"
++ // r3 is done at the end
++" ld 4, 32(3)" "\n"
++" ld 5, 40(3)" "\n"
++" ld 6, 48(3)" "\n"
++" ld 7, 56(3)" "\n"
++" ld 8, 64(3)" "\n"
++" ld 9, 72(3)" "\n"
++" ld 10, 80(3)" "\n"
++" ld 11, 88(3)" "\n"
++" ld 12, 96(3)" "\n"
++" ld 13, 104(3)" "\n"
++" ld 14, 112(3)" "\n"
++" ld 15, 120(3)" "\n"
++" ld 16, 128(3)" "\n"
++" ld 17, 136(3)" "\n"
++" ld 18, 144(3)" "\n"
++" ld 19, 152(3)" "\n"
++" ld 20, 160(3)" "\n"
++" ld 21, 168(3)" "\n"
++" ld 22, 176(3)" "\n"
++" ld 23, 184(3)" "\n"
++" ld 24, 192(3)" "\n"
++" ld 25, 200(3)" "\n"
++" ld 26, 208(3)" "\n"
++" ld 27, 216(3)" "\n"
++" ld 28, 224(3)" "\n"
++" ld 29, 232(3)" "\n"
++" ld 30, 240(3)" "\n"
++" ld 31, 248(3)" "\n"
++" ld 3, 24(3)" "\n"
++" blr" "\n"
++"" "\n"
++
++".previous" "\n"
++);
+ #endif /* VGP_ppc64be_linux */
+
+
+diff --git a/coregrind/m_main.c b/coregrind/m_main.c
+index 9e2ee96..082dc4f 100644
+--- a/coregrind/m_main.c
++++ b/coregrind/m_main.c
+@@ -2625,6 +2625,10 @@ static void final_tidyup(ThreadId tid)
+ VG_(set_IP)(tid, __libc_freeres_wrapper);
+ # if defined(VGP_ppc64be_linux)
+ VG_(threads)[tid].arch.vex.guest_GPR2 = r2;
++# elif defined(VGP_ppc64le_linux)
++ /* setting GPR2 but not really needed, GPR12 is needed */
++ VG_(threads)[tid].arch.vex.guest_GPR2 = __libc_freeres_wrapper;
++ VG_(threads)[tid].arch.vex.guest_GPR12 = __libc_freeres_wrapper;
+ # endif
+ /* mips-linux note: we need to set t9 */
+ # if defined(VGP_mips32_linux) || defined(VGP_mips64_linux)
+@@ -2866,6 +2870,51 @@ asm("\n"
+ "\tnop\n"
+ "\ttrap\n"
+ );
++#elif defined(VGP_ppc64le_linux)
++/* Little Endian uses ELF version 2 but in the future may also
++ * support other ELF versions.
++ */
++asm("\n"
++ "\t.align 2\n"
++ "\t.global _start\n"
++ "\t.type _start, at function\n"
++ "_start:\n"
++ "#if _CALL_ELF == 2 \n"
++ "0: addis 2,12,.TOC.-0b at ha\n"
++ " addi 2,2,.TOC.-0b at l\n"
++ " .localentry _start, .-_start\n"
++ "#endif \n"
++ /* set up the new stack in r16 */
++ "\tlis 16, vgPlain_interim_stack at highest\n"
++ "\tori 16,16,vgPlain_interim_stack at higher\n"
++ "\tsldi 16,16,32\n"
++ "\toris 16,16,vgPlain_interim_stack at h\n"
++ "\tori 16,16,vgPlain_interim_stack at l\n"
++ "\txor 17,17,17\n"
++ "\tlis 17,("VG_STRINGIFY(VG_STACK_GUARD_SZB)" >> 16)\n"
++ "\tori 17,17,("VG_STRINGIFY(VG_STACK_GUARD_SZB)" & 0xFFFF)\n"
++ "\txor 18,18,18\n"
++ "\tlis 18,("VG_STRINGIFY(VG_STACK_ACTIVE_SZB)" >> 16)\n"
++ "\tori 18,18,("VG_STRINGIFY(VG_STACK_ACTIVE_SZB)" & 0xFFFF)\n"
++ "\tadd 16,17,16\n"
++ "\tadd 16,18,16\n"
++ "\trldicr 16,16,0,59\n"
++ /* now r16 = &vgPlain_interim_stack + VG_STACK_GUARD_SZB +
++ VG_STACK_ACTIVE_SZB rounded down to the nearest 16-byte
++ boundary. And r1 is the original SP. Set the SP to r16 and
++ call _start_in_C_linux, passing it the initial SP. */
++ "\tmr 3,1\n"
++ "\tmr 1,16\n"
++ "\tlis 14, _start_in_C_linux at highest\n"
++ "\tori 14,14,_start_in_C_linux at higher\n"
++ "\tsldi 14,14,32\n"
++ "\toris 14,14,_start_in_C_linux at h\n"
++ "\tori 14,14,_start_in_C_linux at l\n"
++ "\tmtctr 14\n"
++ "\tbctrl\n"
++ "\tnop\n"
++ "\ttrap\n"
++);
+ #elif defined(VGP_s390x_linux)
+ /*
+ This is the canonical entry point, usually the first thing in the text
+diff --git a/coregrind/m_redir.c b/coregrind/m_redir.c
+index 26bb94a..71ce230 100644
+--- a/coregrind/m_redir.c
++++ b/coregrind/m_redir.c
+@@ -397,7 +397,7 @@ void VG_(redir_notify_new_DebugInfo)( DebugInfo* newdi )
+ TopSpec* newts;
+ HChar* sym_name_pri;
+ HChar** sym_names_sec;
+- Addr sym_addr, sym_toc;
++ Addr sym_addr, sym_toc, second_ep;
+ HChar demangled_sopatt[N_DEMANGLED];
+ HChar demangled_fnpatt[N_DEMANGLED];
+ Bool check_ppcTOCs = False;
+@@ -499,7 +499,7 @@ void VG_(redir_notify_new_DebugInfo)( DebugInfo* newdi )
+
+ nsyms = VG_(DebugInfo_syms_howmany)( newdi );
+ for (i = 0; i < nsyms; i++) {
+- VG_(DebugInfo_syms_getidx)( newdi, i, &sym_addr, &sym_toc,
++ VG_(DebugInfo_syms_getidx)( newdi, i, &sym_addr, &sym_toc, &second_ep,
+ NULL, &sym_name_pri, &sym_names_sec,
+ &isText, NULL );
+ /* Set up to conveniently iterate over all names for this symbol. */
+@@ -592,7 +592,7 @@ void VG_(redir_notify_new_DebugInfo)( DebugInfo* newdi )
+
+ if (check_ppcTOCs) {
+ for (i = 0; i < nsyms; i++) {
+- VG_(DebugInfo_syms_getidx)( newdi, i, &sym_addr, &sym_toc,
++ VG_(DebugInfo_syms_getidx)( newdi, i, &sym_addr, &sym_toc, &second_ep,
+ NULL, &sym_name_pri, &sym_names_sec,
+ &isText, NULL );
+ HChar* twoslots[2];
+@@ -755,7 +755,9 @@ void generate_and_add_actives (
+ of trashing the caches less. */
+ nsyms = VG_(DebugInfo_syms_howmany)( di );
+ for (i = 0; i < nsyms; i++) {
+- VG_(DebugInfo_syms_getidx)( di, i, &sym_addr, NULL,
++ Addr second_ep = 0;
++
++ VG_(DebugInfo_syms_getidx)( di, i, &sym_addr, NULL, &second_ep,
+ NULL, &sym_name_pri, &sym_names_sec,
+ &isText, &isIFunc );
+ HChar* twoslots[2];
+@@ -783,6 +785,18 @@ void generate_and_add_actives (
+ act.isIFunc = isIFunc;
+ sp->done = True;
+ maybe_add_active( act );
++
++#if defined(VGP_ppc64le_linux)
++ /* If the function being wrapped has a secondary entry point
++ * redirect it to the global entry point. The redirection
++ * must save and setup r2 then setup r12 for the new function.
++ * On return, r2 must be restored.
++ */
++ if (second_ep != 0) {
++ act.from_addr = second_ep;
++ maybe_add_active( act );
++ }
++#endif
+ }
+ } /* for (sp = specs; sp; sp = sp->next) */
+
+@@ -1298,6 +1312,27 @@ void VG_(redir_initialise) ( void )
+ );
+ }
+
++# elif defined(VGP_ppc64le_linux)
++ /* If we're using memcheck, use these intercepts right from
++ * the start, otherwise ld.so makes a lot of noise.
++ */
++ if (0==VG_(strcmp)("Memcheck", VG_(details).name)) {
++
++ /* this is mandatory - can't sanely continue without it */
++ add_hardwired_spec(
++ "ld64.so.2", "strlen",
++ (Addr)&VG_(ppc64_linux_REDIR_FOR_strlen),
++ complain_about_stripped_glibc_ldso
++ );
++
++ add_hardwired_spec(
++ "ld64.so.2", "index",
++ (Addr)&VG_(ppc64_linux_REDIR_FOR_strchr),
++ NULL /* not mandatory - so why bother at all? */
++ /* glibc-2.5 (FC6, ppc64) seems fine without it */
++ );
++ }
++
+ # elif defined(VGP_arm_linux)
+ /* If we're using memcheck, use these intercepts right from the
+ start, otherwise ld.so makes a lot of noise. In most ARM-linux
+@@ -1565,7 +1600,7 @@ static void handle_require_text_symbols ( DebugInfo* di )
+ Bool isText = False;
+ HChar* sym_name_pri = NULL;
+ HChar** sym_names_sec = NULL;
+- VG_(DebugInfo_syms_getidx)( di, j, NULL, NULL,
++ VG_(DebugInfo_syms_getidx)( di, j, NULL, NULL, NULL,
+ NULL, &sym_name_pri, &sym_names_sec,
+ &isText, NULL );
+ HChar* twoslots[2];
+diff --git a/coregrind/m_sigframe/sigframe-ppc64-linux.c b/coregrind/m_sigframe/sigframe-ppc64-linux.c
+index bb53806..17a3c50 100644
+--- a/coregrind/m_sigframe/sigframe-ppc64-linux.c
++++ b/coregrind/m_sigframe/sigframe-ppc64-linux.c
+@@ -252,7 +252,11 @@ void VG_(sigframe_create)( ThreadId tid,
+ # undef DO
+
+ frame->uc.uc_mcontext.gp_regs[VKI_PT_NIP] = tst->arch.vex.guest_CIA;
+- frame->uc.uc_mcontext.gp_regs[VKI_PT_MSR] = 0xf032; /* pretty arbitrary */
++#ifdef VGP_ppc64le_linux
++ frame->uc.uc_mcontext.gp_regs[VKI_PT_MSR] = 0xf033; /* pretty arbitrary */
++#else
++ frame->uc.uc_mcontext.gp_regs[VKI_PT_MSR] = 0xf032; /* pretty arbitrary */
++#endif
+ frame->uc.uc_mcontext.gp_regs[VKI_PT_ORIG_R3] = tst->arch.vex.guest_GPR3;
+ frame->uc.uc_mcontext.gp_regs[VKI_PT_CTR] = tst->arch.vex.guest_CTR;
+ frame->uc.uc_mcontext.gp_regs[VKI_PT_LNK] = tst->arch.vex.guest_LR;
+@@ -302,9 +306,13 @@ void VG_(sigframe_create)( ThreadId tid,
+
+ /* Handler is in fact a standard ppc64-linux function descriptor,
+ so extract the function entry point and also the toc ptr to use. */
++#if defined(VGP_ppc64be_linux)
+ SET_SIGNAL_GPR(tid, 2, (Addr) ((ULong*)handler)[1]);
+ tst->arch.vex.guest_CIA = (Addr) ((ULong*)handler)[0];
+-
++#else
++ SET_SIGNAL_GPR(tid, 12, (Addr) handler);
++ tst->arch.vex.guest_CIA = (Addr) handler;
++#endif
+ priv = &frame->priv;
+ priv->magicPI = 0x31415927;
+ priv->sigNo_private = sigNo;
+diff --git a/coregrind/m_signals.c b/coregrind/m_signals.c
+index 0fd11c4..6ce03f8 100644
+--- a/coregrind/m_signals.c
++++ b/coregrind/m_signals.c
+@@ -866,6 +866,23 @@ extern void my_sigreturn(void);
+ " li 0, " #name "\n" \
+ " sc\n"
+
++#elif defined(VGP_ppc64le_linux)
++/* Little Endian supports ELF version 2. In the future, it may
++ * support other versions.
++ */
++# define _MY_SIGRETURN(name) \
++ ".align 2\n" \
++ ".globl my_sigreturn\n" \
++ ".type .my_sigreturn, at function\n" \
++ "my_sigreturn:\n" \
++ "#if _CALL_ELF == 2 \n" \
++ "0: addis 2,12,.TOC.-0b at ha\n" \
++ " addi 2,2,.TOC.-0b at l\n" \
++ " .localentry my_sigreturn,.-my_sigreturn\n" \
++ "#endif \n" \
++ " sc\n" \
++ " .size my_sigreturn,.-my_sigreturn\n"
++
+ #elif defined(VGP_arm_linux)
+ # define _MY_SIGRETURN(name) \
+ ".text\n" \
+diff --git a/coregrind/m_syscall.c b/coregrind/m_syscall.c
+index b111e5c..cd33958 100644
+--- a/coregrind/m_syscall.c
++++ b/coregrind/m_syscall.c
+@@ -422,6 +422,45 @@ asm(
+ " blr\n"
+ );
+
++#elif defined(VGP_ppc64le_linux)
++/* Due to the need to return 65 bits of result, this is completely
++ different from the ppc32 case. The single arg register points to a
++ 7-word block containing the syscall # and the 6 args. The syscall
++ result proper is put in [0] of the block, and %cr0.so is in the
++ bottom bit of [1]. */
++extern void do_syscall_WRK ( ULong* argblock );
++/* Little Endian supports ELF version 2. In the future, it may support
++ * other versions as well.
++ */
++asm(
++".align 2\n"
++".globl do_syscall_WRK\n"
++".type do_syscall_WRK, at function\n"
++"do_syscall_WRK:\n"
++"#if _CALL_ELF == 2" "\n"
++"0: addis 2,12,.TOC.-0b at ha\n"
++" addi 2,2,.TOC.-0b at l\n"
++" .localentry do_syscall_WRK, .-do_syscall_WRK\n"
++"#endif" "\n"
++" std 3,-16(1)\n" /* stash arg */
++" ld 8, 48(3)\n" /* sc arg 6 */
++" ld 7, 40(3)\n" /* sc arg 5 */
++" ld 6, 32(3)\n" /* sc arg 4 */
++" ld 5, 24(3)\n" /* sc arg 3 */
++" ld 4, 16(3)\n" /* sc arg 2 */
++" ld 0, 0(3)\n" /* sc number */
++" ld 3, 8(3)\n" /* sc arg 1 */
++" sc\n" /* result in r3 and cr0.so */
++" ld 5,-16(1)\n" /* reacquire argblock ptr (r5 is caller-save) */
++" std 3,0(5)\n" /* argblock[0] = r3 */
++" mfcr 3\n"
++" srwi 3,3,28\n"
++" andi. 3,3,1\n"
++" std 3,8(5)\n" /* argblock[1] = cr0.s0 & 1 */
++" blr\n"
++" .size do_syscall_WRK, .-do_syscall_WRK\n"
++);
++
+ #elif defined(VGP_arm_linux)
+ /* I think the conventions are:
+ args in r0 r1 r2 r3 r4 r5
+diff --git a/coregrind/m_syswrap/syscall-ppc64-linux.S b/coregrind/m_syswrap/syscall-ppc64-linux.S
+index df73940..47fda64 100644
+--- a/coregrind/m_syswrap/syscall-ppc64-linux.S
++++ b/coregrind/m_syswrap/syscall-ppc64-linux.S
+@@ -75,12 +75,25 @@
+
+ .align 2
+ .globl ML_(do_syscall_for_client_WRK)
++#if !defined VGP_ppc64be_linux || _CALL_ELF == 2
++.type .ML_(do_syscall_for_client_WRK), at function
++ML_(do_syscall_for_client_WRK):
++0: addis 2,12,.TOC.-0b at ha
++ addi 2,2,.TOC.-0b at l
++ .localentry ML_(do_syscall_for_client_WRK), .-ML_(do_syscall_for_client_WRK)
++#else
+ .section ".opd","aw"
+ .align 3
+-ML_(do_syscall_for_client_WRK):
++ML_(do_syscall_for_client_WRK):
+ .quad .ML_(do_syscall_for_client_WRK),.TOC. at tocbase,0
+ .previous
+-.type .ML_(do_syscall_for_client_WRK), at function
++#endif
++#if _CALL_ELF == 2
++0: addis 2,12,.TOC.-0b at ha
++ addi 2,2,.TOC.-0b at l
++ .localentry ML_(do_syscall_for_client_WRK), .-ML_(do_syscall_for_client_WRK)
++#endif
++.type .ML_(do_syscall_for_client_WRK), at function
+ .globl .ML_(do_syscall_for_client_WRK)
+ .ML_(do_syscall_for_client_WRK):
+ /* make a stack frame */
+@@ -144,7 +157,11 @@ ML_(do_syscall_for_client_WRK):
+ /* failure: return 0x8000 | error code */
+ 7: ori 3,3,0x8000 /* FAILURE -- ensure return value is nonzero */
+ b 5b
+-
++#if !defined VGP_ppc64be_linux || _CALL_ELF == 2
++ .size .ML_(do_syscall_for_client_WRK),.-.ML_(do_syscall_for_client_WRK)
++#else
++ .size .ML_(do_syscall_for_client_WRK),.-.ML_(do_syscall_for_client_WRK)
++#endif
+ .section .rodata
+ /* export the ranges so that
+ VG_(fixup_guest_state_after_syscall_interrupted) can do the
+diff --git a/coregrind/m_syswrap/syswrap-main.c b/coregrind/m_syswrap/syswrap-main.c
+index c26ed5c..ab51ee1 100644
+--- a/coregrind/m_syswrap/syswrap-main.c
++++ b/coregrind/m_syswrap/syswrap-main.c
+@@ -2006,6 +2006,25 @@ void ML_(fixup_guest_state_to_restart_syscall) ( ThreadArchState* arch )
+ vg_assert(p[0] == 0x44 && p[1] == 0x0 && p[2] == 0x0 && p[3] == 0x2);
+ }
+
++#elif defined(VGP_ppc64le_linux)
++ arch->vex.guest_CIA -= 4; // sizeof(ppc32 instr)
++
++ /* Make sure our caller is actually sane, and we're really backing
++ back over a syscall.
++
++ sc == 44 00 00 02
++ */
++ {
++ UChar *p = (UChar *)arch->vex.guest_CIA;
++
++ if (p[3] != 0x44 || p[2] != 0x0 || p[1] != 0x0 || p[0] != 0x02)
++ VG_(message)(Vg_DebugMsg,
++ "?! restarting over syscall at %#llx %02x %02x %02x %02x\n",
++ arch->vex.guest_CIA + 0ULL, p[3], p[2], p[1], p[0]);
++
++ vg_assert(p[3] == 0x44 && p[2] == 0x0 && p[1] == 0x0 && p[0] == 0x2);
++ }
++
+ #elif defined(VGP_arm_linux)
+ if (arch->vex.guest_R15T & 1) {
+ // Thumb mode. SVC is a encoded as
+diff --git a/coregrind/m_syswrap/syswrap-ppc64-linux.c b/coregrind/m_syswrap/syswrap-ppc64-linux.c
+index 5d266b8..0f7ac88 100644
+--- a/coregrind/m_syswrap/syswrap-ppc64-linux.c
++++ b/coregrind/m_syswrap/syswrap-ppc64-linux.c
+@@ -78,6 +78,7 @@ void ML_(call_on_new_stack_0_1) ( Addr stack,
+ address, the second word is the TOC ptr (r2), and the third word is
+ the static chain value. */
+ asm(
++#if defined(VGP_ppc64be_linux)
+ " .align 2\n"
+ " .globl vgModuleLocal_call_on_new_stack_0_1\n"
+ " .section \".opd\",\"aw\"\n"
+@@ -126,6 +127,55 @@ asm(
+ " mtcr 0\n\t" // CAB: Need this?
+ " bctr\n\t" // jump to dst
+ " trap\n" // should never get here
++#else
++// ppc64le_linux
++" .align 2\n"
++" .globl vgModuleLocal_call_on_new_stack_0_1\n"
++"vgModuleLocal_call_on_new_stack_0_1:\n"
++" .type .vgModuleLocal_call_on_new_stack_0_1, at function\n"
++"#if _CALL_ELF == 2 \n"
++"0: addis 2,12,.TOC.-0b at ha\n"
++" addi 2,2,.TOC.-0b at l\n"
++"#endif\n"
++".localentry vgModuleLocal_call_on_new_stack_0_1, .-vgModuleLocal_call_on_new_stack_0_1\n"
++" mr %r1,%r3\n\t" // stack to %sp
++" mtlr %r4\n\t" // retaddr to %lr
++" mtctr %r5\n\t" // f_ptr to count reg
++" mr %r3,%r6\n\t" // arg1 to %r3
++" li 0,0\n\t" // zero all GP regs
++" li 4,0\n\t"
++" li 5,0\n\t"
++" li 6,0\n\t"
++" li 7,0\n\t"
++" li 8,0\n\t"
++" li 9,0\n\t"
++" li 10,0\n\t"
++" li 11,0\n\t"
++" li 12,0\n\t"
++" li 13,0\n\t"
++" li 14,0\n\t"
++" li 15,0\n\t"
++" li 16,0\n\t"
++" li 17,0\n\t"
++" li 18,0\n\t"
++" li 19,0\n\t"
++" li 20,0\n\t"
++" li 21,0\n\t"
++" li 22,0\n\t"
++" li 23,0\n\t"
++" li 24,0\n\t"
++" li 25,0\n\t"
++" li 26,0\n\t"
++" li 27,0\n\t"
++" li 28,0\n\t"
++" li 29,0\n\t"
++" li 30,0\n\t"
++" li 31,0\n\t"
++" mtxer 0\n\t" // CAB: Need this?
++" mtcr 0\n\t" // CAB: Need this?
++" bctr\n\t" // jump to dst
++" trap\n" // should never get here
++#endif
+ );
+
+
+@@ -170,6 +220,7 @@ ULong do_syscall_clone_ppc64_linux ( Word (*fn)(void *),
+ Int* parent_tid,
+ void/*vki_modify_ldt_t*/ * );
+ asm(
++#if defined(VGP_ppc64be_linux)
+ " .align 2\n"
+ " .globl do_syscall_clone_ppc64_linux\n"
+ " .section \".opd\",\"aw\"\n"
+@@ -240,6 +291,78 @@ asm(
+ " ld 31,56(1)\n"
+ " addi 1,1,64\n"
+ " blr\n"
++#else
++" .align 2\n"
++" .globl do_syscall_clone_ppc64_linux\n"
++" .type do_syscall_clone_ppc64_linux, at function\n"
++"do_syscall_clone_ppc64_linux:\n"
++" .globl .do_syscall_clone_ppc64_linux\n"
++".do_syscall_clone_ppc64_linux:\n"
++"#if _CALL_ELF == 2 \n"
++"0: addis 2,12,.TOC.-0b at ha \n"
++" addi 2,2,.TOC.-0b at l \n"
++"#endif \n"
++" .localentry do_syscall_clone_ppc64_linux, .-do_syscall_clone_ppc64_linux \n"
++" stdu 1,-64(1)\n"
++" std 29,40(1)\n"
++" std 30,48(1)\n"
++" std 31,56(1)\n"
++" mr 30,3\n" // preserve fn
++" mr 31,6\n" // preserve arg
++
++ // setup child stack
++" rldicr 4,4, 0,59\n" // trim sp to multiple of 16 bytes
++ // (r4 &= ~0xF)
++" li 0,0\n"
++" stdu 0,-32(4)\n" // make initial stack frame
++" mr 29,4\n" // preserve sp
++
++ // setup syscall
++" li 0,"__NR_CLONE"\n" // syscall number
++" mr 3,5\n" // syscall arg1: flags
++ // r4 already setup // syscall arg2: child_stack
++" mr 5,8\n" // syscall arg3: parent_tid
++" mr 6,13\n" // syscall arg4: REAL THREAD tls
++" mr 7,7\n" // syscall arg5: child_tid
++" mr 8,8\n" // syscall arg6: ????
++" mr 9,9\n" // syscall arg7: ????
++
++" sc\n" // clone()
++
++" mfcr 4\n" // CR now in low half r4
++" sldi 4,4,32\n" // CR now in hi half r4
++
++" sldi 3,3,32\n"
++" srdi 3,3,32\n" // zero out hi half r3
++
++" or 3,3,4\n" // r3 = CR : syscall-retval
++" cmpwi 3,0\n" // child if retval == 0 (note, cmpw)
++" bne 1f\n" // jump if !child
++
++ /* CHILD - call thread function */
++ /* Note: 2.4 kernel doesn't set the child stack pointer,
++ so we do it here.
++ That does leave a small window for a signal to be delivered
++ on the wrong stack, unfortunately. */
++" mr 1,29\n"
++" mtctr 30\n" // ctr reg = fn
++" mr 3,31\n" // r3 = arg
++" bctrl\n" // call fn()
++
++ // exit with result
++" li 0,"__NR_EXIT"\n"
++" sc\n"
++
++ // Exit returned?!
++" .long 0\n"
++
++ // PARENT or ERROR - return
++"1: ld 29,40(1)\n"
++" ld 30,48(1)\n"
++" ld 31,56(1)\n"
++" addi 1,1,64\n"
++" blr\n"
++#endif
+ );
+
+ #undef __NR_CLONE
+@@ -552,7 +675,7 @@ PRE(sys_clone)
+ }
+ if (ARG1 & (VKI_CLONE_CHILD_SETTID | VKI_CLONE_CHILD_CLEARTID)) {
+ PRE_MEM_WRITE("clone(child_tidptr)", ARG5, sizeof(Int));
+- if (!VG_(am_is_valid_for_client)(ARG5, sizeof(Int),
++ if (!VG_(am_is_valid_for_client)(ARG5, sizeof(Int),
+ VKI_PROT_WRITE)) {
+ SET_STATUS_Failure( VKI_EFAULT );
+ return;
+diff --git a/coregrind/m_trampoline.S b/coregrind/m_trampoline.S
+index 8fabec9..0718fd3 100644
+--- a/coregrind/m_trampoline.S
++++ b/coregrind/m_trampoline.S
+@@ -444,6 +444,12 @@ VG_(ppctoc_magic_redirect_return_stub):
+ /* this function is written using the "dotless" ABI convention */
+ .align 2
+ .globl VG_(ppc64_linux_REDIR_FOR_strlen)
++#if !defined VGP_ppc64be_linux || _CALL_ELF == 2
++ /* Little Endian uses ELF version 2 */
++ .type VG_(ppc64_linux_REDIR_FOR_strlen), at function
++VG_(ppc64_linux_REDIR_FOR_strlen):
++#else
++ /* Big Endian uses ELF version 1 */
+ .section ".opd","aw"
+ .align 3
+ VG_(ppc64_linux_REDIR_FOR_strlen):
+@@ -454,7 +460,13 @@ VG_(ppc64_linux_REDIR_FOR_strlen):
+ .type VG_(ppc64_linux_REDIR_FOR_strlen), @function
+
+ .L.VG_(ppc64_linux_REDIR_FOR_strlen):
+- mr 9,3
++#endif
++#if _CALL_ELF == 2
++0: addis 2,12,.TOC.-0b at ha
++ addi 2,2,.TOC.-0b at l
++ .localentry VG_(ppc64_linux_REDIR_FOR_strlen), .-VG_(ppc64_linux_REDIR_FOR_strlen)
++#endif
++ mr 9,3
+ lbz 0,0(3)
+ li 3,0
+ cmpwi 7,0,0
+@@ -467,14 +479,24 @@ VG_(ppc64_linux_REDIR_FOR_strlen):
+ cmpwi 7,0,0
+ bne 7,.L01
+ blr
+- .long 0
++
++#if !defined VGP_ppc64be_linux || _CALL_ELF == 2
++ .size VG_(ppc64_linux_REDIR_FOR_strlen),.-VG_(ppc64_linux_REDIR_FOR_strlen)
++#else
++ .size VG_(ppc64_linux_REDIR_FOR_strlen),.-.L.VG_(ppc64_linux_REDIR_FOR_strlen)
++#endif
++ .long 0
+ .byte 0,0,0,0,0,0,0,0
+ .L0end:
+
+ /* this function is written using the "dotless" ABI convention */
+ .align 2
+ .globl VG_(ppc64_linux_REDIR_FOR_strchr)
+- .section ".opd","aw"
++#if !defined VGP_ppc64be_linux || _CALL_ELF == 2
++ .type VG_(ppc64_linux_REDIR_FOR_strchr), at function
++VG_(ppc64_linux_REDIR_FOR_strchr):
++#else
++ .section ".opd","aw"
+ .align 3
+ VG_(ppc64_linux_REDIR_FOR_strchr):
+ .quad .L.VG_(ppc64_linux_REDIR_FOR_strchr),.TOC. at tocbase,0
+@@ -482,8 +504,14 @@ VG_(ppc64_linux_REDIR_FOR_strchr):
+ .size VG_(ppc64_linux_REDIR_FOR_strchr), \
+ .L1end-.L.VG_(ppc64_linux_REDIR_FOR_strchr)
+ .type VG_(ppc64_linux_REDIR_FOR_strchr), at function
+-
++
+ .L.VG_(ppc64_linux_REDIR_FOR_strchr):
++#endif
++#if _CALL_ELF == 2
++0: addis 2,12,.TOC.-0b at ha
++ addi 2,2,.TOC.-0b at l
++ .localentry VG_(ppc64_linux_REDIR_FOR_strchr), .-VG_(ppc64_linux_REDIR_FOR_strchr)
++#endif
+ lbz 0,0(3)
+ rldicl 4,4,0,56
+ cmpw 7,4,0
+@@ -491,6 +519,11 @@ VG_(ppc64_linux_REDIR_FOR_strchr):
+ cmpdi 7,0,0
+ bne 7,.L18
+ b .L14
++#if !defined VGP_ppc64be_linux || _CALL_ELF == 2
++ .size VG_(ppc64_linux_REDIR_FOR_strchr),.-VG_(ppc64_linux_REDIR_FOR_strchr)
++#else
++ .size VG_(ppc64_linux_REDIR_FOR_strchr),.-.L.VG_(ppc64_linux_REDIR_FOR_strchr)
++#endif
+ .L19:
+ beq 6,.L14
+ .L18:
+diff --git a/coregrind/m_translate.c b/coregrind/m_translate.c
+index 0919394..fc4ca51 100644
+--- a/coregrind/m_translate.c
++++ b/coregrind/m_translate.c
+@@ -1118,6 +1118,10 @@ static IRTemp gen_POP ( IRSB* bb )
+ return res;
+ }
+
++#endif
++
++#if defined(VG_PLAT_USES_PPCTOC)
++
+ /* Generate code to push LR and R2 onto this thread's redir stack,
+ then set R2 to the new value (which is the TOC pointer to be used
+ for the duration of the replacement function, as determined by
+@@ -1140,6 +1144,9 @@ static void gen_push_and_set_LR_R2 ( IRSB* bb, Addr64 new_R2_value )
+ # error Platform is not TOC-afflicted, fortunately
+ # endif
+ }
++#endif
++
++#if defined(VG_PLAT_USES_PPCTOC) || defined(VGP_ppc64le_linux)
+
+ static void gen_pop_R2_LR_then_bLR ( IRSB* bb )
+ {
+@@ -1166,6 +1173,9 @@ static void gen_pop_R2_LR_then_bLR ( IRSB* bb )
+ # error Platform is not TOC-afflicted, fortunately
+ # endif
+ }
++#endif
++
++#if defined(VG_PLAT_USES_PPCTOC) || defined(VGP_ppc64le_linux)
+
+ static
+ Bool mk_preamble__ppctoc_magic_return_stub ( void* closureV, IRSB* bb )
+@@ -1187,6 +1197,30 @@ Bool mk_preamble__ppctoc_magic_return_stub ( void* closureV, IRSB* bb )
+ }
+ #endif
+
++#if defined(VGP_ppc64le_linux)
++/* Generate code to push LR and R2 onto this thread's redir stack.
++ Need to save R2 in case we redirect to a global entry point. The
++ value of R2 is not preserved when entering the global entry point.
++ Need to make sure R2 gets restored on return. Set LR to the magic
++ return stub, so we get to intercept the return and restore R2 and
++ L2 to the values saved here.
++
++ The existing infrastruture for the TOC enabled architectures is
++ being exploited here. So, we need to enable a number of the
++ code sections used by VG_PLAT_USES_PPCTOC.
++*/
++
++static void gen_push_R2_and_set_LR ( IRSB* bb )
++{
++ Addr64 bogus_RA = (Addr64)&VG_(ppctoc_magic_redirect_return_stub);
++ Int offB_GPR2 = offsetof(VexGuestPPC64State,guest_GPR2);
++ Int offB_LR = offsetof(VexGuestPPC64State,guest_LR);
++ gen_PUSH( bb, IRExpr_Get(offB_LR, Ity_I64) );
++ gen_PUSH( bb, IRExpr_Get(offB_GPR2, Ity_I64) );
++ addStmtToIRSB( bb, IRStmt_Put( offB_LR, mkU64( bogus_RA )) );
++}
++# endif
++
+ /* --------------- END helpers for with-TOC platforms --------------- */
+
+
+@@ -1244,6 +1278,19 @@ Bool mk_preamble__set_NRADDR_to_zero ( void* closureV, IRSB* bb )
+ gen_push_and_set_LR_R2 ( bb, VG_(get_tocptr)( closure->readdr ) );
+ }
+ # endif
++
++#if defined(VGP_ppc64le_linux)
++ VgCallbackClosure* closure = (VgCallbackClosure*)closureV;
++ Int offB_GPR12 = offsetof(VexGuestArchState, guest_GPR12);
++ addStmtToIRSB(bb, IRStmt_Put(offB_GPR12, mkU64(closure->readdr)));
++ addStmtToIRSB(bb,
++ IRStmt_Put(
++ offsetof(VexGuestArchState,guest_NRADDR_GPR2),
++ VG_WORDSIZE==8 ? mkU64(0) : mkU32(0)
++ )
++ );
++ gen_push_R2_and_set_LR ( bb );
++#endif
+ return False;
+ }
+
+@@ -1277,7 +1324,7 @@ Bool mk_preamble__set_NRADDR_to_nraddr ( void* closureV, IRSB* bb )
+ Int offB_GPR25 = offsetof(VexGuestMIPS64State, guest_r25);
+ addStmtToIRSB(bb, IRStmt_Put(offB_GPR25, mkU64(closure->readdr)));
+ # endif
+-# if defined(VGP_ppc64be_linux)
++# if defined(VG_PLAT_USES_PPCTOC) && !defined(VGP_ppc64le_linux)
+ addStmtToIRSB(
+ bb,
+ IRStmt_Put(
+@@ -1288,6 +1335,22 @@ Bool mk_preamble__set_NRADDR_to_nraddr ( void* closureV, IRSB* bb )
+ );
+ gen_push_and_set_LR_R2 ( bb, VG_(get_tocptr)( closure->readdr ) );
+ # endif
++#if defined(VGP_ppc64le_linux)
++ /* This saves the r2 before leaving the function. We need to move
++ * guest_NRADDR_GPR2 back to R2 on return.
++ */
++ Int offB_GPR12 = offsetof(VexGuestArchState, guest_GPR12);
++ addStmtToIRSB(
++ bb,
++ IRStmt_Put(
++ offsetof(VexGuestArchState,guest_NRADDR_GPR2),
++ IRExpr_Get(offsetof(VexGuestArchState,guest_GPR2),
++ VG_WORDSIZE==8 ? Ity_I64 : Ity_I32)
++ )
++ );
++ addStmtToIRSB(bb, IRStmt_Put(offB_GPR12, mkU64(closure->readdr)));
++ gen_push_R2_and_set_LR ( bb );
++#endif
+ return False;
+ }
+
+@@ -1485,7 +1548,8 @@ Bool VG_(translate) ( ThreadId tid,
+ if (kind == T_Redir_Wrap)
+ preamble_fn = mk_preamble__set_NRADDR_to_nraddr;
+
+-# if defined(VG_PLAT_USES_PPCTOC)
++ /* LE we setup the LR */
++# if defined(VG_PLAT_USES_PPCTOC) || defined(VGP_ppc64le_linux)
+ if (ULong_to_Ptr(nraddr)
+ == (void*)&VG_(ppctoc_magic_redirect_return_stub)) {
+ /* If entering the special return stub, this means a wrapped or
+@@ -1528,6 +1592,11 @@ Bool VG_(translate) ( ThreadId tid,
+ vex_abiinfo.guest_ppc_zap_RZ_at_bl = const_True;
+ vex_abiinfo.host_ppc_calls_use_fndescrs = True;
+ # endif
++# if defined(VGP_ppc64le_linux)
++ vex_abiinfo.guest_ppc_zap_RZ_at_blr = True;
++ vex_abiinfo.guest_ppc_zap_RZ_at_bl = const_True;
++ vex_abiinfo.host_ppc_calls_use_fndescrs = False;
++# endif
+
+ /* Set up closure args. */
+ closure.tid = tid;
+diff --git a/coregrind/m_ume/elf.c b/coregrind/m_ume/elf.c
+index 910bb7a..fdbd431 100644
+--- a/coregrind/m_ume/elf.c
++++ b/coregrind/m_ume/elf.c
+@@ -310,6 +310,14 @@ Int VG_(load_ELF)(Int fd, const HChar* name, /*MOD*/ExeInfo* info)
+ void *entry;
+ ESZ(Addr) ebase = 0;
+
++#if defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
++ /* The difference between where the interpreter got mapped and
++ where it asked to be mapped. Needed for computing the ppc64 ELF
++ entry point and initial tocptr (R2) value.
++ */
++ ESZ(Word) interp_offset = 0;
++#endif
++
+ # if defined(HAVE_PIE)
+ ebase = info->exe_base;
+ # endif
+@@ -495,7 +503,10 @@ Int VG_(load_ELF)(Int fd, const HChar* name, /*MOD*/ExeInfo* info)
+ VG_(close)(interp->fd);
+
+ entry = (void *)(advised - interp_addr + interp->e.e_entry);
++
++#if defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
+ info->interp_offset = advised - interp_addr;
++#endif
+
+ VG_(free)(interp->p);
+ VG_(free)(interp);
+@@ -514,6 +525,11 @@ Int VG_(load_ELF)(Int fd, const HChar* name, /*MOD*/ExeInfo* info)
+ info->init_toc = ((ULong*)entry)[1];
+ info->init_ip += info->interp_offset;
+ info->init_toc += info->interp_offset;
++#elif defined(VGP_ppc64le_linux)
++ /* On PPC64LE, ELF ver 2. API doesn't use a func ptr */
++ info->init_ip = (Addr)entry;
++ info->init_toc = 0; /* meaningless on this platform */
++ (void) interp_offset; /* stop gcc complaining it is unused */
+ #else
+ info->init_ip = (Addr)entry;
+ info->init_toc = 0; /* meaningless on this platform */
+diff --git a/coregrind/m_ume/macho.c b/coregrind/m_ume/macho.c
+index 7608811..3dfddaf 100644
+--- a/coregrind/m_ume/macho.c
++++ b/coregrind/m_ume/macho.c
+@@ -701,6 +701,8 @@ load_fat_file(int fd, vki_off_t offset, vki_off_t size, unsigned long filetype,
+ good_arch = CPU_TYPE_POWERPC;
+ #elif defined(VGA_ppc64be)
+ good_arch = CPU_TYPE_POWERPC64BE;
++#elif defined(VGA_ppc64le)
++ good_arch = CPU_TYPE_POWERPC64LE;
+ #elif defined(VGA_x86)
+ good_arch = CPU_TYPE_I386;
+ #elif defined(VGA_amd64)
+diff --git a/coregrind/pub_core_machine.h b/coregrind/pub_core_machine.h
+index f1d839a..14ea354 100644
+--- a/coregrind/pub_core_machine.h
++++ b/coregrind/pub_core_machine.h
+@@ -61,6 +61,11 @@
+ # define VG_ELF_MACHINE EM_PPC64
+ # define VG_ELF_CLASS ELFCLASS64
+ # define VG_PLAT_USES_PPCTOC 1
++#elif defined(VGP_ppc64le_linux)
++# define VG_ELF_DATA2XXX ELFDATA2LSB
++# define VG_ELF_MACHINE EM_PPC64
++# define VG_ELF_CLASS ELFCLASS64
++# undef VG_PLAT_USES_PPCTOC
+ #elif defined(VGP_arm_linux)
+ # define VG_ELF_DATA2XXX ELFDATA2LSB
+ # define VG_ELF_MACHINE EM_ARM
+diff --git a/coregrind/vgdb-invoker-ptrace.c b/coregrind/vgdb-invoker-ptrace.c
+index bad4df5..c7aa342 100644
+--- a/coregrind/vgdb-invoker-ptrace.c
++++ b/coregrind/vgdb-invoker-ptrace.c
+@@ -1015,6 +1015,16 @@ Bool invoker_invoke_gdbserver (pid_t pid)
+ user_mod.regs.gpr[3] = check;
+ /* put bad_return return address in Link Register */
+ user_mod.regs.link = bad_return;
++#elif defined(VGA_ppc64le)
++ /* LE does not use the function pointer structure used in BE */
++ user_mod.regs.nip = shared64->invoke_gdbserver;
++ user_mod.regs.gpr[1] = sp - 512;
++ user_mod.regs.gpr[12] = user_mod.regs.nip;
++ user_mod.regs.trap = -1L;
++ /* put check arg in register 3 */
++ user_mod.regs.gpr[3] = check;
++ /* put bad_return return address in Link Register */
++ user_mod.regs.link = bad_return;
+ #elif defined(VGA_s390x)
+ /* put check arg in register r2 */
+ user_mod.regs.gprs[2] = check;
+diff --git a/helgrind/hg_main.c b/helgrind/hg_main.c
+index f5d02b2..b956549 100644
+--- a/helgrind/hg_main.c
++++ b/helgrind/hg_main.c
+@@ -4473,6 +4473,7 @@ static Bool is_in_dynamic_linker_shared_object( Addr64 ga )
+ if (VG_STREQ(soname, VG_U_LD_LINUX_SO_2)) return True;
+ if (VG_STREQ(soname, VG_U_LD_LINUX_X86_64_SO_2)) return True;
+ if (VG_STREQ(soname, VG_U_LD64_SO_1)) return True;
++ if (VG_STREQ(soname, VG_U_LD64_SO_2)) return True;
+ if (VG_STREQ(soname, VG_U_LD_SO_1)) return True;
+ # elif defined(VGO_darwin)
+ if (VG_STREQ(soname, VG_U_DYLD)) return True;
+diff --git a/include/pub_tool_debuginfo.h b/include/pub_tool_debuginfo.h
+index 4f7a09d..4de8508 100644
+--- a/include/pub_tool_debuginfo.h
++++ b/include/pub_tool_debuginfo.h
+@@ -249,6 +249,7 @@ void VG_(DebugInfo_syms_getidx) ( const DebugInfo *di,
+ Int idx,
+ /*OUT*/Addr* avma,
+ /*OUT*/Addr* tocptr,
++ /*OUT*/Addr* second_ep,
+ /*OUT*/UInt* size,
+ /*OUT*/HChar** pri_name,
+ /*OUT*/HChar*** sec_names,
+diff --git a/include/pub_tool_redir.h b/include/pub_tool_redir.h
+index 0a679e1..bf00e2f 100644
+--- a/include/pub_tool_redir.h
++++ b/include/pub_tool_redir.h
+@@ -287,6 +287,7 @@
+
+ #define VG_Z_LD64_SO_1 ld64ZdsoZd1 // ld64.so.1
+ #define VG_U_LD64_SO_1 "ld64.so.1"
++#define VG_U_LD64_SO_2 "ld64.so.2" // PPC LE loader
+
+ #define VG_Z_LD_SO_1 ldZdsoZd1 // ld.so.1
+ #define VG_U_LD_SO_1 "ld.so.1"
+diff --git a/include/valgrind.h b/include/valgrind.h
+index 81c946a..a65f03a 100644
+--- a/include/valgrind.h
++++ b/include/valgrind.h
+@@ -116,6 +116,7 @@
+ #undef PLAT_amd64_linux
+ #undef PLAT_ppc32_linux
+ #undef PLAT_ppc64be_linux
++#undef PLAT_ppc64le_linux
+ #undef PLAT_arm_linux
+ #undef PLAT_arm64_linux
+ #undef PLAT_s390x_linux
+@@ -143,6 +144,9 @@
+ #elif defined(__linux__) && defined(__powerpc__) && defined(__powerpc64__) && _CALL_ELF != 2
+ /* Big Endian uses ELF version 1 */
+ # define PLAT_ppc64be_linux 1
++#elif defined(__linux__) && defined(__powerpc__) && defined(__powerpc64__) && _CALL_ELF == 2
++/* Little Endian uses ELF version 2 */
++# define PLAT_ppc64le_linux 1
+ #elif defined(__linux__) && defined(__arm__) && !defined(__aarch64__)
+ # define PLAT_arm_linux 1
+ #elif defined(__linux__) && defined(__aarch64__) && !defined(__arm__)
+@@ -599,6 +603,82 @@ typedef
+
+ #endif /* PLAT_ppc64be_linux */
+
++#if defined(PLAT_ppc64le_linux)
++
++typedef
++ struct {
++ unsigned long long int nraddr; /* where's the code? */
++ unsigned long long int r2; /* what tocptr do we need? */
++ }
++ OrigFn;
++
++#define __SPECIAL_INSTRUCTION_PREAMBLE \
++ "rotldi 0,0,3 ; rotldi 0,0,13\n\t" \
++ "rotldi 0,0,61 ; rotldi 0,0,51\n\t"
++
++#define VALGRIND_DO_CLIENT_REQUEST_EXPR( \
++ _zzq_default, _zzq_request, \
++ _zzq_arg1, _zzq_arg2, _zzq_arg3, _zzq_arg4, _zzq_arg5) \
++ \
++ __extension__ \
++ ({ unsigned long long int _zzq_args[6]; \
++ unsigned long long int _zzq_result; \
++ unsigned long long int* _zzq_ptr; \
++ _zzq_args[0] = (unsigned long long int)(_zzq_request); \
++ _zzq_args[1] = (unsigned long long int)(_zzq_arg1); \
++ _zzq_args[2] = (unsigned long long int)(_zzq_arg2); \
++ _zzq_args[3] = (unsigned long long int)(_zzq_arg3); \
++ _zzq_args[4] = (unsigned long long int)(_zzq_arg4); \
++ _zzq_args[5] = (unsigned long long int)(_zzq_arg5); \
++ _zzq_ptr = _zzq_args; \
++ __asm__ volatile("mr 3,%1\n\t" /*default*/ \
++ "mr 4,%2\n\t" /*ptr*/ \
++ __SPECIAL_INSTRUCTION_PREAMBLE \
++ /* %R3 = client_request ( %R4 ) */ \
++ "or 1,1,1\n\t" \
++ "mr %0,3" /*result*/ \
++ : "=b" (_zzq_result) \
++ : "b" (_zzq_default), "b" (_zzq_ptr) \
++ : "cc", "memory", "r3", "r4"); \
++ _zzq_result; \
++ })
++
++#define VALGRIND_GET_NR_CONTEXT(_zzq_rlval) \
++ { volatile OrigFn* _zzq_orig = &(_zzq_rlval); \
++ unsigned long long int __addr; \
++ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \
++ /* %R3 = guest_NRADDR */ \
++ "or 2,2,2\n\t" \
++ "mr %0,3" \
++ : "=b" (__addr) \
++ : \
++ : "cc", "memory", "r3" \
++ ); \
++ _zzq_orig->nraddr = __addr; \
++ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \
++ /* %R3 = guest_NRADDR_GPR2 */ \
++ "or 4,4,4\n\t" \
++ "mr %0,3" \
++ : "=b" (__addr) \
++ : \
++ : "cc", "memory", "r3" \
++ ); \
++ _zzq_orig->r2 = __addr; \
++ }
++
++#define VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R12 \
++ __SPECIAL_INSTRUCTION_PREAMBLE \
++ /* branch-and-link-to-noredir *%R12 */ \
++ "or 3,3,3\n\t"
++
++#define VALGRIND_VEX_INJECT_IR() \
++ do { \
++ __asm__ volatile(__SPECIAL_INSTRUCTION_PREAMBLE \
++ "or 5,5,5\n\t" \
++ ); \
++ } while (0)
++
++#endif /* PLAT_ppc64le_linux */
+
+ /* ------------------------- arm-linux ------------------------- */
+
+@@ -3093,6 +3173,562 @@ typedef
+
+ #endif /* PLAT_ppc64be_linux */
+
++/* ------------------------- ppc64le-linux ----------------------- */
++#if defined(PLAT_ppc64le_linux)
++
++/* ARGREGS: r3 r4 r5 r6 r7 r8 r9 r10 (the rest on stack somewhere) */
++
++/* These regs are trashed by the hidden call. */
++#define __CALLER_SAVED_REGS \
++ "lr", "ctr", "xer", \
++ "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", \
++ "r0", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", \
++ "r11", "r12", "r13"
++
++/* Macros to save and align the stack before making a function
++ call and restore it afterwards as gcc may not keep the stack
++ pointer aligned if it doesn't realise calls are being made
++ to other functions. */
++
++#define VALGRIND_ALIGN_STACK \
++ "mr 28,1\n\t" \
++ "rldicr 1,1,0,59\n\t"
++#define VALGRIND_RESTORE_STACK \
++ "mr 1,28\n\t"
++
++/* These CALL_FN_ macros assume that on ppc64-linux, sizeof(unsigned
++ long) == 8. */
++
++#define CALL_FN_W_v(lval, orig) \
++ do { \
++ volatile OrigFn _orig = (orig); \
++ volatile unsigned long _argvec[3+0]; \
++ volatile unsigned long _res; \
++ /* _argvec[0] holds current r2 across the call */ \
++ _argvec[1] = (unsigned long)_orig.r2; \
++ _argvec[2] = (unsigned long)_orig.nraddr; \
++ __asm__ volatile( \
++ VALGRIND_ALIGN_STACK \
++ "mr 12,%1\n\t" \
++ "std 2,-16(12)\n\t" /* save tocptr */ \
++ "ld 2,-8(12)\n\t" /* use nraddr's tocptr */ \
++ "ld 12, 0(12)\n\t" /* target->r12 */ \
++ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R12 \
++ "mr 12,%1\n\t" \
++ "mr %0,3\n\t" \
++ "ld 2,-16(12)\n\t" /* restore tocptr */ \
++ VALGRIND_RESTORE_STACK \
++ : /*out*/ "=r" (_res) \
++ : /*in*/ "r" (&_argvec[2]) \
++ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
++ ); \
++ lval = (__typeof__(lval)) _res; \
++ } while (0)
++
++#define CALL_FN_W_W(lval, orig, arg1) \
++ do { \
++ volatile OrigFn _orig = (orig); \
++ volatile unsigned long _argvec[3+1]; \
++ volatile unsigned long _res; \
++ /* _argvec[0] holds current r2 across the call */ \
++ _argvec[1] = (unsigned long)_orig.r2; \
++ _argvec[2] = (unsigned long)_orig.nraddr; \
++ _argvec[2+1] = (unsigned long)arg1; \
++ __asm__ volatile( \
++ VALGRIND_ALIGN_STACK \
++ "mr 12,%1\n\t" \
++ "std 2,-16(12)\n\t" /* save tocptr */ \
++ "ld 2,-8(12)\n\t" /* use nraddr's tocptr */ \
++ "ld 3, 8(12)\n\t" /* arg1->r3 */ \
++ "ld 12, 0(12)\n\t" /* target->r12 */ \
++ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R12 \
++ "mr 12,%1\n\t" \
++ "mr %0,3\n\t" \
++ "ld 2,-16(12)\n\t" /* restore tocptr */ \
++ VALGRIND_RESTORE_STACK \
++ : /*out*/ "=r" (_res) \
++ : /*in*/ "r" (&_argvec[2]) \
++ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
++ ); \
++ lval = (__typeof__(lval)) _res; \
++ } while (0)
++
++#define CALL_FN_W_WW(lval, orig, arg1,arg2) \
++ do { \
++ volatile OrigFn _orig = (orig); \
++ volatile unsigned long _argvec[3+2]; \
++ volatile unsigned long _res; \
++ /* _argvec[0] holds current r2 across the call */ \
++ _argvec[1] = (unsigned long)_orig.r2; \
++ _argvec[2] = (unsigned long)_orig.nraddr; \
++ _argvec[2+1] = (unsigned long)arg1; \
++ _argvec[2+2] = (unsigned long)arg2; \
++ __asm__ volatile( \
++ VALGRIND_ALIGN_STACK \
++ "mr 12,%1\n\t" \
++ "std 2,-16(12)\n\t" /* save tocptr */ \
++ "ld 2,-8(12)\n\t" /* use nraddr's tocptr */ \
++ "ld 3, 8(12)\n\t" /* arg1->r3 */ \
++ "ld 4, 16(12)\n\t" /* arg2->r4 */ \
++ "ld 12, 0(12)\n\t" /* target->r12 */ \
++ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R12 \
++ "mr 12,%1\n\t" \
++ "mr %0,3\n\t" \
++ "ld 2,-16(12)\n\t" /* restore tocptr */ \
++ VALGRIND_RESTORE_STACK \
++ : /*out*/ "=r" (_res) \
++ : /*in*/ "r" (&_argvec[2]) \
++ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
++ ); \
++ lval = (__typeof__(lval)) _res; \
++ } while (0)
++
++#define CALL_FN_W_WWW(lval, orig, arg1,arg2,arg3) \
++ do { \
++ volatile OrigFn _orig = (orig); \
++ volatile unsigned long _argvec[3+3]; \
++ volatile unsigned long _res; \
++ /* _argvec[0] holds current r2 across the call */ \
++ _argvec[1] = (unsigned long)_orig.r2; \
++ _argvec[2] = (unsigned long)_orig.nraddr; \
++ _argvec[2+1] = (unsigned long)arg1; \
++ _argvec[2+2] = (unsigned long)arg2; \
++ _argvec[2+3] = (unsigned long)arg3; \
++ __asm__ volatile( \
++ VALGRIND_ALIGN_STACK \
++ "mr 12,%1\n\t" \
++ "std 2,-16(12)\n\t" /* save tocptr */ \
++ "ld 2,-8(12)\n\t" /* use nraddr's tocptr */ \
++ "ld 3, 8(12)\n\t" /* arg1->r3 */ \
++ "ld 4, 16(12)\n\t" /* arg2->r4 */ \
++ "ld 5, 24(12)\n\t" /* arg3->r5 */ \
++ "ld 12, 0(12)\n\t" /* target->r12 */ \
++ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R12 \
++ "mr 12,%1\n\t" \
++ "mr %0,3\n\t" \
++ "ld 2,-16(12)\n\t" /* restore tocptr */ \
++ VALGRIND_RESTORE_STACK \
++ : /*out*/ "=r" (_res) \
++ : /*in*/ "r" (&_argvec[2]) \
++ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
++ ); \
++ lval = (__typeof__(lval)) _res; \
++ } while (0)
++
++#define CALL_FN_W_WWWW(lval, orig, arg1,arg2,arg3,arg4) \
++ do { \
++ volatile OrigFn _orig = (orig); \
++ volatile unsigned long _argvec[3+4]; \
++ volatile unsigned long _res; \
++ /* _argvec[0] holds current r2 across the call */ \
++ _argvec[1] = (unsigned long)_orig.r2; \
++ _argvec[2] = (unsigned long)_orig.nraddr; \
++ _argvec[2+1] = (unsigned long)arg1; \
++ _argvec[2+2] = (unsigned long)arg2; \
++ _argvec[2+3] = (unsigned long)arg3; \
++ _argvec[2+4] = (unsigned long)arg4; \
++ __asm__ volatile( \
++ VALGRIND_ALIGN_STACK \
++ "mr 12,%1\n\t" \
++ "std 2,-16(12)\n\t" /* save tocptr */ \
++ "ld 2,-8(12)\n\t" /* use nraddr's tocptr */ \
++ "ld 3, 8(12)\n\t" /* arg1->r3 */ \
++ "ld 4, 16(12)\n\t" /* arg2->r4 */ \
++ "ld 5, 24(12)\n\t" /* arg3->r5 */ \
++ "ld 6, 32(12)\n\t" /* arg4->r6 */ \
++ "ld 12, 0(12)\n\t" /* target->r12 */ \
++ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R12 \
++ "mr 12,%1\n\t" \
++ "mr %0,3\n\t" \
++ "ld 2,-16(12)\n\t" /* restore tocptr */ \
++ VALGRIND_RESTORE_STACK \
++ : /*out*/ "=r" (_res) \
++ : /*in*/ "r" (&_argvec[2]) \
++ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
++ ); \
++ lval = (__typeof__(lval)) _res; \
++ } while (0)
++
++#define CALL_FN_W_5W(lval, orig, arg1,arg2,arg3,arg4,arg5) \
++ do { \
++ volatile OrigFn _orig = (orig); \
++ volatile unsigned long _argvec[3+5]; \
++ volatile unsigned long _res; \
++ /* _argvec[0] holds current r2 across the call */ \
++ _argvec[1] = (unsigned long)_orig.r2; \
++ _argvec[2] = (unsigned long)_orig.nraddr; \
++ _argvec[2+1] = (unsigned long)arg1; \
++ _argvec[2+2] = (unsigned long)arg2; \
++ _argvec[2+3] = (unsigned long)arg3; \
++ _argvec[2+4] = (unsigned long)arg4; \
++ _argvec[2+5] = (unsigned long)arg5; \
++ __asm__ volatile( \
++ VALGRIND_ALIGN_STACK \
++ "mr 12,%1\n\t" \
++ "std 2,-16(12)\n\t" /* save tocptr */ \
++ "ld 2,-8(12)\n\t" /* use nraddr's tocptr */ \
++ "ld 3, 8(12)\n\t" /* arg1->r3 */ \
++ "ld 4, 16(12)\n\t" /* arg2->r4 */ \
++ "ld 5, 24(12)\n\t" /* arg3->r5 */ \
++ "ld 6, 32(12)\n\t" /* arg4->r6 */ \
++ "ld 7, 40(12)\n\t" /* arg5->r7 */ \
++ "ld 12, 0(12)\n\t" /* target->r12 */ \
++ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R12 \
++ "mr 12,%1\n\t" \
++ "mr %0,3\n\t" \
++ "ld 2,-16(12)\n\t" /* restore tocptr */ \
++ VALGRIND_RESTORE_STACK \
++ : /*out*/ "=r" (_res) \
++ : /*in*/ "r" (&_argvec[2]) \
++ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
++ ); \
++ lval = (__typeof__(lval)) _res; \
++ } while (0)
++
++#define CALL_FN_W_6W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6) \
++ do { \
++ volatile OrigFn _orig = (orig); \
++ volatile unsigned long _argvec[3+6]; \
++ volatile unsigned long _res; \
++ /* _argvec[0] holds current r2 across the call */ \
++ _argvec[1] = (unsigned long)_orig.r2; \
++ _argvec[2] = (unsigned long)_orig.nraddr; \
++ _argvec[2+1] = (unsigned long)arg1; \
++ _argvec[2+2] = (unsigned long)arg2; \
++ _argvec[2+3] = (unsigned long)arg3; \
++ _argvec[2+4] = (unsigned long)arg4; \
++ _argvec[2+5] = (unsigned long)arg5; \
++ _argvec[2+6] = (unsigned long)arg6; \
++ __asm__ volatile( \
++ VALGRIND_ALIGN_STACK \
++ "mr 12,%1\n\t" \
++ "std 2,-16(12)\n\t" /* save tocptr */ \
++ "ld 2,-8(12)\n\t" /* use nraddr's tocptr */ \
++ "ld 3, 8(12)\n\t" /* arg1->r3 */ \
++ "ld 4, 16(12)\n\t" /* arg2->r4 */ \
++ "ld 5, 24(12)\n\t" /* arg3->r5 */ \
++ "ld 6, 32(12)\n\t" /* arg4->r6 */ \
++ "ld 7, 40(12)\n\t" /* arg5->r7 */ \
++ "ld 8, 48(12)\n\t" /* arg6->r8 */ \
++ "ld 12, 0(12)\n\t" /* target->r12 */ \
++ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R12 \
++ "mr 12,%1\n\t" \
++ "mr %0,3\n\t" \
++ "ld 2,-16(12)\n\t" /* restore tocptr */ \
++ VALGRIND_RESTORE_STACK \
++ : /*out*/ "=r" (_res) \
++ : /*in*/ "r" (&_argvec[2]) \
++ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
++ ); \
++ lval = (__typeof__(lval)) _res; \
++ } while (0)
++
++#define CALL_FN_W_7W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
++ arg7) \
++ do { \
++ volatile OrigFn _orig = (orig); \
++ volatile unsigned long _argvec[3+7]; \
++ volatile unsigned long _res; \
++ /* _argvec[0] holds current r2 across the call */ \
++ _argvec[1] = (unsigned long)_orig.r2; \
++ _argvec[2] = (unsigned long)_orig.nraddr; \
++ _argvec[2+1] = (unsigned long)arg1; \
++ _argvec[2+2] = (unsigned long)arg2; \
++ _argvec[2+3] = (unsigned long)arg3; \
++ _argvec[2+4] = (unsigned long)arg4; \
++ _argvec[2+5] = (unsigned long)arg5; \
++ _argvec[2+6] = (unsigned long)arg6; \
++ _argvec[2+7] = (unsigned long)arg7; \
++ __asm__ volatile( \
++ VALGRIND_ALIGN_STACK \
++ "mr 12,%1\n\t" \
++ "std 2,-16(12)\n\t" /* save tocptr */ \
++ "ld 2,-8(12)\n\t" /* use nraddr's tocptr */ \
++ "ld 3, 8(12)\n\t" /* arg1->r3 */ \
++ "ld 4, 16(12)\n\t" /* arg2->r4 */ \
++ "ld 5, 24(12)\n\t" /* arg3->r5 */ \
++ "ld 6, 32(12)\n\t" /* arg4->r6 */ \
++ "ld 7, 40(12)\n\t" /* arg5->r7 */ \
++ "ld 8, 48(12)\n\t" /* arg6->r8 */ \
++ "ld 9, 56(12)\n\t" /* arg7->r9 */ \
++ "ld 12, 0(12)\n\t" /* target->r12 */ \
++ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R12 \
++ "mr 12,%1\n\t" \
++ "mr %0,3\n\t" \
++ "ld 2,-16(12)\n\t" /* restore tocptr */ \
++ VALGRIND_RESTORE_STACK \
++ : /*out*/ "=r" (_res) \
++ : /*in*/ "r" (&_argvec[2]) \
++ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
++ ); \
++ lval = (__typeof__(lval)) _res; \
++ } while (0)
++
++#define CALL_FN_W_8W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
++ arg7,arg8) \
++ do { \
++ volatile OrigFn _orig = (orig); \
++ volatile unsigned long _argvec[3+8]; \
++ volatile unsigned long _res; \
++ /* _argvec[0] holds current r2 across the call */ \
++ _argvec[1] = (unsigned long)_orig.r2; \
++ _argvec[2] = (unsigned long)_orig.nraddr; \
++ _argvec[2+1] = (unsigned long)arg1; \
++ _argvec[2+2] = (unsigned long)arg2; \
++ _argvec[2+3] = (unsigned long)arg3; \
++ _argvec[2+4] = (unsigned long)arg4; \
++ _argvec[2+5] = (unsigned long)arg5; \
++ _argvec[2+6] = (unsigned long)arg6; \
++ _argvec[2+7] = (unsigned long)arg7; \
++ _argvec[2+8] = (unsigned long)arg8; \
++ __asm__ volatile( \
++ VALGRIND_ALIGN_STACK \
++ "mr 12,%1\n\t" \
++ "std 2,-16(12)\n\t" /* save tocptr */ \
++ "ld 2,-8(12)\n\t" /* use nraddr's tocptr */ \
++ "ld 3, 8(12)\n\t" /* arg1->r3 */ \
++ "ld 4, 16(12)\n\t" /* arg2->r4 */ \
++ "ld 5, 24(12)\n\t" /* arg3->r5 */ \
++ "ld 6, 32(12)\n\t" /* arg4->r6 */ \
++ "ld 7, 40(12)\n\t" /* arg5->r7 */ \
++ "ld 8, 48(12)\n\t" /* arg6->r8 */ \
++ "ld 9, 56(12)\n\t" /* arg7->r9 */ \
++ "ld 10, 64(12)\n\t" /* arg8->r10 */ \
++ "ld 12, 0(12)\n\t" /* target->r12 */ \
++ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R12 \
++ "mr 12,%1\n\t" \
++ "mr %0,3\n\t" \
++ "ld 2,-16(12)\n\t" /* restore tocptr */ \
++ VALGRIND_RESTORE_STACK \
++ : /*out*/ "=r" (_res) \
++ : /*in*/ "r" (&_argvec[2]) \
++ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
++ ); \
++ lval = (__typeof__(lval)) _res; \
++ } while (0)
++
++#define CALL_FN_W_9W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
++ arg7,arg8,arg9) \
++ do { \
++ volatile OrigFn _orig = (orig); \
++ volatile unsigned long _argvec[3+9]; \
++ volatile unsigned long _res; \
++ /* _argvec[0] holds current r2 across the call */ \
++ _argvec[1] = (unsigned long)_orig.r2; \
++ _argvec[2] = (unsigned long)_orig.nraddr; \
++ _argvec[2+1] = (unsigned long)arg1; \
++ _argvec[2+2] = (unsigned long)arg2; \
++ _argvec[2+3] = (unsigned long)arg3; \
++ _argvec[2+4] = (unsigned long)arg4; \
++ _argvec[2+5] = (unsigned long)arg5; \
++ _argvec[2+6] = (unsigned long)arg6; \
++ _argvec[2+7] = (unsigned long)arg7; \
++ _argvec[2+8] = (unsigned long)arg8; \
++ _argvec[2+9] = (unsigned long)arg9; \
++ __asm__ volatile( \
++ VALGRIND_ALIGN_STACK \
++ "mr 12,%1\n\t" \
++ "std 2,-16(12)\n\t" /* save tocptr */ \
++ "ld 2,-8(12)\n\t" /* use nraddr's tocptr */ \
++ "addi 1,1,-128\n\t" /* expand stack frame */ \
++ /* arg9 */ \
++ "ld 3,72(12)\n\t" \
++ "std 3,96(1)\n\t" \
++ /* args1-8 */ \
++ "ld 3, 8(12)\n\t" /* arg1->r3 */ \
++ "ld 4, 16(12)\n\t" /* arg2->r4 */ \
++ "ld 5, 24(12)\n\t" /* arg3->r5 */ \
++ "ld 6, 32(12)\n\t" /* arg4->r6 */ \
++ "ld 7, 40(12)\n\t" /* arg5->r7 */ \
++ "ld 8, 48(12)\n\t" /* arg6->r8 */ \
++ "ld 9, 56(12)\n\t" /* arg7->r9 */ \
++ "ld 10, 64(12)\n\t" /* arg8->r10 */ \
++ "ld 12, 0(12)\n\t" /* target->r12 */ \
++ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R12 \
++ "mr 12,%1\n\t" \
++ "mr %0,3\n\t" \
++ "ld 2,-16(12)\n\t" /* restore tocptr */ \
++ VALGRIND_RESTORE_STACK \
++ : /*out*/ "=r" (_res) \
++ : /*in*/ "r" (&_argvec[2]) \
++ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
++ ); \
++ lval = (__typeof__(lval)) _res; \
++ } while (0)
++
++#define CALL_FN_W_10W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
++ arg7,arg8,arg9,arg10) \
++ do { \
++ volatile OrigFn _orig = (orig); \
++ volatile unsigned long _argvec[3+10]; \
++ volatile unsigned long _res; \
++ /* _argvec[0] holds current r2 across the call */ \
++ _argvec[1] = (unsigned long)_orig.r2; \
++ _argvec[2] = (unsigned long)_orig.nraddr; \
++ _argvec[2+1] = (unsigned long)arg1; \
++ _argvec[2+2] = (unsigned long)arg2; \
++ _argvec[2+3] = (unsigned long)arg3; \
++ _argvec[2+4] = (unsigned long)arg4; \
++ _argvec[2+5] = (unsigned long)arg5; \
++ _argvec[2+6] = (unsigned long)arg6; \
++ _argvec[2+7] = (unsigned long)arg7; \
++ _argvec[2+8] = (unsigned long)arg8; \
++ _argvec[2+9] = (unsigned long)arg9; \
++ _argvec[2+10] = (unsigned long)arg10; \
++ __asm__ volatile( \
++ VALGRIND_ALIGN_STACK \
++ "mr 12,%1\n\t" \
++ "std 2,-16(12)\n\t" /* save tocptr */ \
++ "ld 2,-8(12)\n\t" /* use nraddr's tocptr */ \
++ "addi 1,1,-128\n\t" /* expand stack frame */ \
++ /* arg10 */ \
++ "ld 3,80(12)\n\t" \
++ "std 3,104(1)\n\t" \
++ /* arg9 */ \
++ "ld 3,72(12)\n\t" \
++ "std 3,96(1)\n\t" \
++ /* args1-8 */ \
++ "ld 3, 8(12)\n\t" /* arg1->r3 */ \
++ "ld 4, 16(12)\n\t" /* arg2->r4 */ \
++ "ld 5, 24(12)\n\t" /* arg3->r5 */ \
++ "ld 6, 32(12)\n\t" /* arg4->r6 */ \
++ "ld 7, 40(12)\n\t" /* arg5->r7 */ \
++ "ld 8, 48(12)\n\t" /* arg6->r8 */ \
++ "ld 9, 56(12)\n\t" /* arg7->r9 */ \
++ "ld 10, 64(12)\n\t" /* arg8->r10 */ \
++ "ld 12, 0(12)\n\t" /* target->r12 */ \
++ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R12 \
++ "mr 12,%1\n\t" \
++ "mr %0,3\n\t" \
++ "ld 2,-16(12)\n\t" /* restore tocptr */ \
++ VALGRIND_RESTORE_STACK \
++ : /*out*/ "=r" (_res) \
++ : /*in*/ "r" (&_argvec[2]) \
++ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
++ ); \
++ lval = (__typeof__(lval)) _res; \
++ } while (0)
++
++#define CALL_FN_W_11W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
++ arg7,arg8,arg9,arg10,arg11) \
++ do { \
++ volatile OrigFn _orig = (orig); \
++ volatile unsigned long _argvec[3+11]; \
++ volatile unsigned long _res; \
++ /* _argvec[0] holds current r2 across the call */ \
++ _argvec[1] = (unsigned long)_orig.r2; \
++ _argvec[2] = (unsigned long)_orig.nraddr; \
++ _argvec[2+1] = (unsigned long)arg1; \
++ _argvec[2+2] = (unsigned long)arg2; \
++ _argvec[2+3] = (unsigned long)arg3; \
++ _argvec[2+4] = (unsigned long)arg4; \
++ _argvec[2+5] = (unsigned long)arg5; \
++ _argvec[2+6] = (unsigned long)arg6; \
++ _argvec[2+7] = (unsigned long)arg7; \
++ _argvec[2+8] = (unsigned long)arg8; \
++ _argvec[2+9] = (unsigned long)arg9; \
++ _argvec[2+10] = (unsigned long)arg10; \
++ _argvec[2+11] = (unsigned long)arg11; \
++ __asm__ volatile( \
++ VALGRIND_ALIGN_STACK \
++ "mr 12,%1\n\t" \
++ "std 2,-16(12)\n\t" /* save tocptr */ \
++ "ld 2,-8(12)\n\t" /* use nraddr's tocptr */ \
++ "addi 1,1,-144\n\t" /* expand stack frame */ \
++ /* arg11 */ \
++ "ld 3,88(12)\n\t" \
++ "std 3,112(1)\n\t" \
++ /* arg10 */ \
++ "ld 3,80(12)\n\t" \
++ "std 3,104(1)\n\t" \
++ /* arg9 */ \
++ "ld 3,72(12)\n\t" \
++ "std 3,96(1)\n\t" \
++ /* args1-8 */ \
++ "ld 3, 8(12)\n\t" /* arg1->r3 */ \
++ "ld 4, 16(12)\n\t" /* arg2->r4 */ \
++ "ld 5, 24(12)\n\t" /* arg3->r5 */ \
++ "ld 6, 32(12)\n\t" /* arg4->r6 */ \
++ "ld 7, 40(12)\n\t" /* arg5->r7 */ \
++ "ld 8, 48(12)\n\t" /* arg6->r8 */ \
++ "ld 9, 56(12)\n\t" /* arg7->r9 */ \
++ "ld 10, 64(12)\n\t" /* arg8->r10 */ \
++ "ld 12, 0(12)\n\t" /* target->r12 */ \
++ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R12 \
++ "mr 12,%1\n\t" \
++ "mr %0,3\n\t" \
++ "ld 2,-16(12)\n\t" /* restore tocptr */ \
++ VALGRIND_RESTORE_STACK \
++ : /*out*/ "=r" (_res) \
++ : /*in*/ "r" (&_argvec[2]) \
++ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
++ ); \
++ lval = (__typeof__(lval)) _res; \
++ } while (0)
++
++#define CALL_FN_W_12W(lval, orig, arg1,arg2,arg3,arg4,arg5,arg6, \
++ arg7,arg8,arg9,arg10,arg11,arg12) \
++ do { \
++ volatile OrigFn _orig = (orig); \
++ volatile unsigned long _argvec[3+12]; \
++ volatile unsigned long _res; \
++ /* _argvec[0] holds current r2 across the call */ \
++ _argvec[1] = (unsigned long)_orig.r2; \
++ _argvec[2] = (unsigned long)_orig.nraddr; \
++ _argvec[2+1] = (unsigned long)arg1; \
++ _argvec[2+2] = (unsigned long)arg2; \
++ _argvec[2+3] = (unsigned long)arg3; \
++ _argvec[2+4] = (unsigned long)arg4; \
++ _argvec[2+5] = (unsigned long)arg5; \
++ _argvec[2+6] = (unsigned long)arg6; \
++ _argvec[2+7] = (unsigned long)arg7; \
++ _argvec[2+8] = (unsigned long)arg8; \
++ _argvec[2+9] = (unsigned long)arg9; \
++ _argvec[2+10] = (unsigned long)arg10; \
++ _argvec[2+11] = (unsigned long)arg11; \
++ _argvec[2+12] = (unsigned long)arg12; \
++ __asm__ volatile( \
++ VALGRIND_ALIGN_STACK \
++ "mr 12,%1\n\t" \
++ "std 2,-16(12)\n\t" /* save tocptr */ \
++ "ld 2,-8(12)\n\t" /* use nraddr's tocptr */ \
++ "addi 1,1,-144\n\t" /* expand stack frame */ \
++ /* arg12 */ \
++ "ld 3,96(12)\n\t" \
++ "std 3,120(1)\n\t" \
++ /* arg11 */ \
++ "ld 3,88(12)\n\t" \
++ "std 3,112(1)\n\t" \
++ /* arg10 */ \
++ "ld 3,80(12)\n\t" \
++ "std 3,104(1)\n\t" \
++ /* arg9 */ \
++ "ld 3,72(12)\n\t" \
++ "std 3,96(1)\n\t" \
++ /* args1-8 */ \
++ "ld 3, 8(12)\n\t" /* arg1->r3 */ \
++ "ld 4, 16(12)\n\t" /* arg2->r4 */ \
++ "ld 5, 24(12)\n\t" /* arg3->r5 */ \
++ "ld 6, 32(12)\n\t" /* arg4->r6 */ \
++ "ld 7, 40(12)\n\t" /* arg5->r7 */ \
++ "ld 8, 48(12)\n\t" /* arg6->r8 */ \
++ "ld 9, 56(12)\n\t" /* arg7->r9 */ \
++ "ld 10, 64(12)\n\t" /* arg8->r10 */ \
++ "ld 12, 0(12)\n\t" /* target->r12 */ \
++ VALGRIND_BRANCH_AND_LINK_TO_NOREDIR_R12 \
++ "mr 12,%1\n\t" \
++ "mr %0,3\n\t" \
++ "ld 2,-16(12)\n\t" /* restore tocptr */ \
++ VALGRIND_RESTORE_STACK \
++ : /*out*/ "=r" (_res) \
++ : /*in*/ "r" (&_argvec[2]) \
++ : /*trash*/ "cc", "memory", __CALLER_SAVED_REGS, "r28" \
++ ); \
++ lval = (__typeof__(lval)) _res; \
++ } while (0)
++
++#endif /* PLAT_ppc64le_linux */
++
+ /* ------------------------- arm-linux ------------------------- */
+
+ #if defined(PLAT_arm_linux)
+@@ -5938,6 +6574,7 @@ VALGRIND_PRINTF_BACKTRACE(const char *format, ...)
+ #undef PLAT_amd64_linux
+ #undef PLAT_ppc32_linux
+ #undef PLAT_ppc64be_linux
++#undef PLAT_ppc64le_linux
+ #undef PLAT_arm_linux
+ #undef PLAT_s390x_linux
+ #undef PLAT_mips32_linux
+diff --git a/include/vki/vki-ppc64-linux.h b/include/vki/vki-ppc64-linux.h
+index dca1c24..33ad840 100644
+--- a/include/vki/vki-ppc64-linux.h
++++ b/include/vki/vki-ppc64-linux.h
+@@ -31,9 +31,11 @@
+ #ifndef __VKI_PPC64_LINUX_H
+ #define __VKI_PPC64_LINUX_H
+
+-// ppc64 is big-endian.
++#if defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux)
+ #define VKI_BIG_ENDIAN 1
+-
++#elif defined(VGP_ppc64le_linux)
++#define VKI_LITTLE_ENDIAN 1
++#endif
+ //----------------------------------------------------------------------
+ // From linux-2.6.13/include/asm-ppc64/types.h
+ //----------------------------------------------------------------------
+diff --git a/memcheck/mc_machine.c b/memcheck/mc_machine.c
+index 36c80aa..cc8be14 100644
+--- a/memcheck/mc_machine.c
++++ b/memcheck/mc_machine.c
+@@ -167,7 +167,11 @@ static Int get_otrack_shadow_offset_wrk ( Int offset, Int szB )
+ return GOF(GPRn);
+ by testing ox instead of o, and setting ox back 4 bytes when sz == 4.
+ */
+- Int ox = sz == 8 ? o : (o - 4);
++#if defined(VGA_ppc64le)
++ Int ox = o;
++#else
++ Int ox = sz == 8 ? o : (o - 4);
++#endif
+ if (ox == GOF(GPR0)) return ox;
+ if (ox == GOF(GPR1)) return ox;
+ if (ox == GOF(GPR2)) return ox;
+@@ -367,7 +371,11 @@ static Int get_otrack_shadow_offset_wrk ( Int offset, Int szB )
+ Int o = offset;
+ Int sz = szB;
+ tl_assert(sz > 0);
++#if defined(VGA_ppc64)
+ tl_assert(host_is_big_endian());
++#elif defined(VGA_ppc64le)
++ tl_assert(host_is_little_endian());
++#endif
+
+ if (o == GOF(GPR0) && sz == 4) return o;
+ if (o == GOF(GPR1) && sz == 4) return o;
+diff --git a/memcheck/tests/atomic_incs.c b/memcheck/tests/atomic_incs.c
+index 0029d8c..1d74d39 100644
+--- a/memcheck/tests/atomic_incs.c
++++ b/memcheck/tests/atomic_incs.c
+@@ -79,6 +79,23 @@ __attribute__((noinline)) void atomic_add_8bit ( char* p, int n )
+ : /*trash*/ "memory", "cc", "r15"
+ );
+ } while (success != 1);
++#elif defined(VGA_ppc64le)
++ /* Nasty hack. Does correctly atomically do *p += n, but only if p
++ is 8-aligned -- guaranteed by caller. */
++ unsigned long success;
++ do {
++ __asm__ __volatile__(
++ "ldarx 15,0,%1" "\n\t"
++ "add 15,15,%2" "\n\t"
++ "stdcx. 15,0,%1" "\n\t"
++ "mfcr %0" "\n\t"
++ "srwi %0,%0,29" "\n\t"
++ "andi. %0,%0,1" "\n"
++ : /*out*/"=b"(success)
++ : /*in*/ "b"(p), "b"(((unsigned long)n))
++ : /*trash*/ "memory", "cc", "r15"
++ );
++ } while (success != 1);
+ #elif defined(VGA_arm)
+ unsigned int block[3]
+ = { (unsigned int)p, (unsigned int)n, 0xFFFFFFFF };
+@@ -278,6 +295,23 @@ __attribute__((noinline)) void atomic_add_16bit ( short* p, int n )
+ : /*trash*/ "memory", "cc", "r15"
+ );
+ } while (success != 1);
++#elif defined(VGA_ppc64le)
++ /* Nasty hack. Does correctly atomically do *p += n, but only if p
++ is 8-aligned -- guaranteed by caller. */
++ unsigned long success;
++ do {
++ __asm__ __volatile__(
++ "ldarx 15,0,%1" "\n\t"
++ "add 15,15,%2" "\n\t"
++ "stdcx. 15,0,%1" "\n\t"
++ "mfcr %0" "\n\t"
++ "srwi %0,%0,29" "\n\t"
++ "andi. %0,%0,1" "\n"
++ : /*out*/"=b"(success)
++ : /*in*/ "b"(p), "b"(((unsigned long)n))
++ : /*trash*/ "memory", "cc", "r15"
++ );
++ } while (success != 1);
+ #elif defined(VGA_arm)
+ unsigned int block[3]
+ = { (unsigned int)p, (unsigned int)n, 0xFFFFFFFF };
+@@ -474,6 +508,23 @@ __attribute__((noinline)) void atomic_add_32bit ( int* p, int n )
+ : /*trash*/ "memory", "cc", "r15"
+ );
+ } while (success != 1);
++#elif defined(VGA_ppc64le)
++ /* Nasty hack. Does correctly atomically do *p += n, but only if p
++ is 8-aligned -- guaranteed by caller. */
++ unsigned long success;
++ do {
++ __asm__ __volatile__(
++ "ldarx 15,0,%1" "\n\t"
++ "add 15,15,%2" "\n\t"
++ "stdcx. 15,0,%1" "\n\t"
++ "mfcr %0" "\n\t"
++ "srwi %0,%0,29" "\n\t"
++ "andi. %0,%0,1" "\n"
++ : /*out*/"=b"(success)
++ : /*in*/ "b"(p), "b"(((unsigned long)n))
++ : /*trash*/ "memory", "cc", "r15"
++ );
++ } while (success != 1);
+ #elif defined(VGA_arm)
+ unsigned int block[3]
+ = { (unsigned int)p, (unsigned int)n, 0xFFFFFFFF };
+diff --git a/tests/arch_test.c b/tests/arch_test.c
+index 2fa3b48..ef00785 100644
+--- a/tests/arch_test.c
++++ b/tests/arch_test.c
+@@ -27,6 +27,7 @@ char* all_archs[] = {
+ "amd64",
+ "ppc32",
+ "ppc64",
++ "ppc64le",
+ "arm",
+ "s390x",
+ "mips32",
+@@ -54,6 +55,9 @@ static Bool go(char* arch)
+ if ( 0 == strcmp( arch, "ppc32" ) ) return True;
+ #endif
+
++#elif defined(VGP_ppc64le_linux)
++ if ( 0 == strcmp( arch, "ppc64" ) ) return True;
++
+ #elif defined(VGP_s390x_linux)
+ if ( 0 == strcmp( arch, "s390x" ) ) return True;
+
+--
+1.8.4.2
+
diff --git a/valgrind-3.9.0-ppc64le-initial.patch b/valgrind-3.9.0-ppc64le-initial.patch
new file mode 100644
index 0000000..dab0eff
--- /dev/null
+++ b/valgrind-3.9.0-ppc64le-initial.patch
@@ -0,0 +1,3456 @@
+From 4f0b04ae746ccb2a848292027defef48873b2598 Mon Sep 17 00:00:00 2001
+From: Carl Love <carll at us.ibm.com>
+Date: Tue, 8 Jul 2014 10:37:46 -0500
+Subject: [PATCH] POWER PC, add initial Little Endian support
+
+The IBM POWER processor now supports both Big Endian and Little Endian.
+This patch renames the #defines with the name ppc64 to ppc64be for the BE
+specific code. This patch adds the Little Endian #define ppc64le to the
+
+Additionally, a few functions are renamed to remove BE from the name if the
+function is used by BE and LE. Functions that are BE specific have BE put
+in the name.
+
+The goals of this patch is to make sure #defines, function names and
+variables consistently use PPC64/ppc64 if it refers to BE and LE,
+PPC64BE/ppc64be if it is specific to BE, PPC64LE/ppc64le if it is LE
+specific. The patch does not break the code for PPC64 Big Endian.
+
+The patch removes the BASH specific use of "BASH_SOURCE[0]" in
+tests/check_isa-2_06_cap and tests/check_isa-2_07 as it is not portable
+across other shells.
+
+Signed-off-by: Carl Love <carll at us.ibm.com>
+---
+ Makefile.all.am | 23 +-
+ Makefile.tool.am | 21 +-
+ VEX/priv/guest_ppc_toIR.c | 356 ++++++++++++++--------------
+ cachegrind/cg_arch.c | 2 +-
+ cachegrind/cg_branchpred.c | 2 +-
+ configure.ac | 57 ++++-
+ coregrind/launcher-darwin.c | 10 +-
+ coregrind/launcher-linux.c | 4 +-
+ coregrind/m_aspacemgr/aspacemgr-common.c | 3 +-
+ coregrind/m_cache.c | 3 +-
+ coregrind/m_coredump/coredump-elf.c | 4 +-
+ coregrind/m_debugger.c | 2 +-
+ coregrind/m_debuginfo/d3basics.c | 5 +-
+ coregrind/m_debuginfo/debuginfo.c | 15 +-
+ coregrind/m_debuginfo/priv_storage.h | 2 +-
+ coregrind/m_debuginfo/readdwarf.c | 15 +-
+ coregrind/m_debuginfo/readelf.c | 47 ++--
+ coregrind/m_debuginfo/readmacho.c | 4 +-
+ coregrind/m_debuginfo/storage.c | 2 +-
+ coregrind/m_debuglog.c | 2 +-
+ coregrind/m_dispatch/dispatch-ppc64-linux.S | 6 +-
+ coregrind/m_gdbserver/target.c | 2 +-
+ coregrind/m_initimg/initimg-linux.c | 18 +-
+ coregrind/m_libcassert.c | 2 +-
+ coregrind/m_libcfile.c | 25 +-
+ coregrind/m_libcproc.c | 6 +-
+ coregrind/m_libcsetjmp.c | 4 +-
+ coregrind/m_machine.c | 26 +-
+ coregrind/m_main.c | 19 +-
+ coregrind/m_redir.c | 2 +-
+ coregrind/m_scheduler/scheduler.c | 4 +-
+ coregrind/m_sigframe/sigframe-ppc64-linux.c | 4 +-
+ coregrind/m_signals.c | 4 +-
+ coregrind/m_stacktrace.c | 13 +-
+ coregrind/m_syscall.c | 4 +-
+ coregrind/m_syswrap/priv_types_n_macros.h | 3 +-
+ coregrind/m_syswrap/syscall-ppc64-linux.S | 4 +-
+ coregrind/m_syswrap/syswrap-linux.c | 8 +-
+ coregrind/m_syswrap/syswrap-main.c | 12 +-
+ coregrind/m_syswrap/syswrap-ppc64-linux.c | 4 +-
+ coregrind/m_trampoline.S | 2 +-
+ coregrind/m_translate.c | 16 +-
+ coregrind/m_ume/elf.c | 6 +-
+ coregrind/m_ume/macho.c | 4 +-
+ coregrind/m_vki.c | 4 +-
+ coregrind/pub_core_aspacemgr.h | 3 +-
+ coregrind/pub_core_basics.h | 2 +-
+ coregrind/pub_core_debuginfo.h | 2 +-
+ coregrind/pub_core_machine.h | 8 +-
+ coregrind/pub_core_mallocfree.h | 15 +-
+ coregrind/pub_core_threadstate.h | 2 +-
+ coregrind/pub_core_trampoline.h | 2 +-
+ coregrind/pub_core_transtab_asm.h | 4 +-
+ coregrind/vgdb-invoker-ptrace.c | 6 +-
+ drd/drd_bitmap.h | 4 +-
+ drd/drd_load_store.c | 2 +-
+ drd/tests/unit_bitmap.c | 3 +-
+ helgrind/tests/annotate_hbefore.c | 2 +-
+ include/pub_tool_basics.h | 7 +-
+ include/pub_tool_libcsetjmp.h | 2 +-
+ include/pub_tool_machine.h | 2 +-
+ include/pub_tool_vkiscnums_asm.h | 2 +-
+ include/valgrind.h | 22 +-
+ include/vki/vki-linux.h | 4 +-
+ memcheck/mc_machine.c | 7 +-
+ memcheck/tests/atomic_incs.c | 8 +-
+ memcheck/tests/unit_libcbase.c | 3 +-
+ tests/Makefile.am | 3 +-
+ tests/arch_test.c | 2 +-
+ tests/check_isa-2_06_cap | 2 +-
+ tests/check_isa-2_07_cap | 2 +-
+ tests/is_ppc64_BE.c | 14 ++
+ tests/power_insn_available.c | 6 +-
+ 73 files changed, 506 insertions(+), 416 deletions(-)
+ create mode 100644 tests/is_ppc64_BE.c
+
+diff --git a/Makefile.all.am b/Makefile.all.am
+index 0d30ed5..f0b638d 100644
+--- a/Makefile.all.am
++++ b/Makefile.all.am
+@@ -229,15 +229,16 @@ if VGCONF_PLATVARIANT_IS_ANDROID
+ PRELOAD_LDFLAGS_COMMON_LINUX += -nostdlib
+ endif
+
+-PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+-PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+-PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+-PRELOAD_LDFLAGS_PPC64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+-PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+-PRELOAD_LDFLAGS_ARM64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+-PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
+-PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
+-PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+-PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+-PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
++PRELOAD_LDFLAGS_X86_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
++PRELOAD_LDFLAGS_AMD64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
++PRELOAD_LDFLAGS_PPC32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
++PRELOAD_LDFLAGS_PPC64BE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
++PRELOAD_LDFLAGS_PPC64LE_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
++PRELOAD_LDFLAGS_ARM_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
++PRELOAD_LDFLAGS_ARM64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
++PRELOAD_LDFLAGS_X86_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch i386
++PRELOAD_LDFLAGS_AMD64_DARWIN = $(PRELOAD_LDFLAGS_COMMON_DARWIN) -arch x86_64
++PRELOAD_LDFLAGS_S390X_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
++PRELOAD_LDFLAGS_MIPS32_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M32@
++PRELOAD_LDFLAGS_MIPS64_LINUX = $(PRELOAD_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+
+diff --git a/Makefile.tool.am b/Makefile.tool.am
+index 6e15ce4..458d5ee 100644
+--- a/Makefile.tool.am
++++ b/Makefile.tool.am
+@@ -46,7 +46,10 @@ TOOL_LDFLAGS_AMD64_LINUX = \
+ TOOL_LDFLAGS_PPC32_LINUX = \
+ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M32@
+
+-TOOL_LDFLAGS_PPC64_LINUX = \
++TOOL_LDFLAGS_PPC64BE_LINUX = \
++ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@
++
++TOOL_LDFLAGS_PPC64LE_LINUX = \
+ $(TOOL_LDFLAGS_COMMON_LINUX) @FLAG_M64@
+
+ TOOL_LDFLAGS_ARM_LINUX = \
+@@ -102,8 +105,11 @@ LIBREPLACEMALLOC_AMD64_LINUX = \
+ LIBREPLACEMALLOC_PPC32_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-ppc32-linux.a
+
+-LIBREPLACEMALLOC_PPC64_LINUX = \
+- $(top_builddir)/coregrind/libreplacemalloc_toolpreload-ppc64-linux.a
++LIBREPLACEMALLOC_PPC64BE_LINUX = \
++ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-ppc64be-linux.a
++
++LIBREPLACEMALLOC_PPC64LE_LINUX = \
++ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-ppc64le-linux.a
+
+ LIBREPLACEMALLOC_ARM_LINUX = \
+ $(top_builddir)/coregrind/libreplacemalloc_toolpreload-arm-linux.a
+@@ -141,9 +147,14 @@ LIBREPLACEMALLOC_LDFLAGS_PPC32_LINUX = \
+ $(LIBREPLACEMALLOC_PPC32_LINUX) \
+ -Wl,--no-whole-archive
+
+-LIBREPLACEMALLOC_LDFLAGS_PPC64_LINUX = \
++LIBREPLACEMALLOC_LDFLAGS_PPC64BE_LINUX = \
++ -Wl,--whole-archive \
++ $(LIBREPLACEMALLOC_PPC64BE_LINUX) \
++ -Wl,--no-whole-archive
++
++LIBREPLACEMALLOC_LDFLAGS_PPC64LE_LINUX = \
+ -Wl,--whole-archive \
+- $(LIBREPLACEMALLOC_PPC64_LINUX) \
++ $(LIBREPLACEMALLOC_PPC64LE_LINUX) \
+ -Wl,--no-whole-archive
+
+ LIBREPLACEMALLOC_LDFLAGS_ARM_LINUX = \
+diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
+index d39debf..e0031a3 100644
+--- a/VEX/priv/guest_ppc_toIR.c
++++ b/VEX/priv/guest_ppc_toIR.c
+@@ -144,6 +144,7 @@
+ #include "guest_ppc_defs.h"
+
+
++#define IENDIANESS Iend_BE
+ /*------------------------------------------------------------*/
+ /*--- Globals ---*/
+ /*------------------------------------------------------------*/
+@@ -503,9 +504,9 @@ static ULong extend_s_32to64 ( UInt x )
+ return (ULong)((((Long)x) << 32) >> 32);
+ }
+
+-/* Do a big-endian load of a 32-bit word, regardless of the endianness
++/* Do a proper-endian load of a 32-bit word, regardless of the endianness
+ of the underlying host. */
+-static UInt getUIntBigendianly ( UChar* p )
++static UInt getUIntPPCendianly ( UChar* p )
+ {
+ UInt w = 0;
+ w = (w << 8) | p[0];
+@@ -526,11 +527,11 @@ static void assign ( IRTemp dst, IRExpr* e )
+ }
+
+ /* This generates a normal (non store-conditional) store. */
+-static void storeBE ( IRExpr* addr, IRExpr* data )
++static void store ( IRExpr* addr, IRExpr* data )
+ {
+ IRType tyA = typeOfIRExpr(irsb->tyenv, addr);
+ vassert(tyA == Ity_I32 || tyA == Ity_I64);
+- stmt( IRStmt_Store(Iend_BE, addr, data) );
++ stmt( IRStmt_Store(IENDIANESS, addr, data) );
+ }
+
+ static IRExpr* unop ( IROp op, IRExpr* a )
+@@ -586,9 +587,9 @@ static IRExpr* mkV128 ( UShort i )
+ }
+
+ /* This generates a normal (non load-linked) load. */
+-static IRExpr* loadBE ( IRType ty, IRExpr* addr )
++static IRExpr* load ( IRType ty, IRExpr* addr )
+ {
+- return IRExpr_Load(Iend_BE, ty, addr);
++ return IRExpr_Load(IENDIANESS, ty, addr);
+ }
+
+ static IRExpr* mkOR1 ( IRExpr* arg1, IRExpr* arg2 )
+@@ -4758,7 +4759,7 @@ static Bool dis_int_load ( UInt theInstr )
+ switch (opc1) {
+ case 0x22: // lbz (Load B & Zero, PPC32 p433)
+ DIP("lbz r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr);
+- val = loadBE(Ity_I8, mkexpr(EA));
++ val = load(Ity_I8, mkexpr(EA));
+ putIReg( rD_addr, mkWidenFrom8(ty, val, False) );
+ break;
+
+@@ -4768,14 +4769,14 @@ static Bool dis_int_load ( UInt theInstr )
+ return False;
+ }
+ DIP("lbzu r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr);
+- val = loadBE(Ity_I8, mkexpr(EA));
++ val = load(Ity_I8, mkexpr(EA));
+ putIReg( rD_addr, mkWidenFrom8(ty, val, False) );
+ putIReg( rA_addr, mkexpr(EA) );
+ break;
+
+ case 0x2A: // lha (Load HW Alg, PPC32 p445)
+ DIP("lha r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr);
+- val = loadBE(Ity_I16, mkexpr(EA));
++ val = load(Ity_I16, mkexpr(EA));
+ putIReg( rD_addr, mkWidenFrom16(ty, val, True) );
+ break;
+
+@@ -4785,14 +4786,14 @@ static Bool dis_int_load ( UInt theInstr )
+ return False;
+ }
+ DIP("lhau r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr);
+- val = loadBE(Ity_I16, mkexpr(EA));
++ val = load(Ity_I16, mkexpr(EA));
+ putIReg( rD_addr, mkWidenFrom16(ty, val, True) );
+ putIReg( rA_addr, mkexpr(EA) );
+ break;
+
+ case 0x28: // lhz (Load HW & Zero, PPC32 p450)
+ DIP("lhz r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr);
+- val = loadBE(Ity_I16, mkexpr(EA));
++ val = load(Ity_I16, mkexpr(EA));
+ putIReg( rD_addr, mkWidenFrom16(ty, val, False) );
+ break;
+
+@@ -4802,14 +4803,14 @@ static Bool dis_int_load ( UInt theInstr )
+ return False;
+ }
+ DIP("lhzu r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr);
+- val = loadBE(Ity_I16, mkexpr(EA));
++ val = load(Ity_I16, mkexpr(EA));
+ putIReg( rD_addr, mkWidenFrom16(ty, val, False) );
+ putIReg( rA_addr, mkexpr(EA) );
+ break;
+
+ case 0x20: // lwz (Load W & Zero, PPC32 p460)
+ DIP("lwz r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr);
+- val = loadBE(Ity_I32, mkexpr(EA));
++ val = load(Ity_I32, mkexpr(EA));
+ putIReg( rD_addr, mkWidenFrom32(ty, val, False) );
+ break;
+
+@@ -4819,7 +4820,7 @@ static Bool dis_int_load ( UInt theInstr )
+ return False;
+ }
+ DIP("lwzu r%u,%d(r%u)\n", rD_addr, (Int)simm16, rA_addr);
+- val = loadBE(Ity_I32, mkexpr(EA));
++ val = load(Ity_I32, mkexpr(EA));
+ putIReg( rD_addr, mkWidenFrom32(ty, val, False) );
+ putIReg( rA_addr, mkexpr(EA) );
+ break;
+@@ -4838,14 +4839,14 @@ static Bool dis_int_load ( UInt theInstr )
+ vex_printf("dis_int_load(ppc)(lwzux,rA_addr|rD_addr)\n");
+ return False;
+ }
+- val = loadBE(Ity_I8, mkexpr(EA));
++ val = load(Ity_I8, mkexpr(EA));
+ putIReg( rD_addr, mkWidenFrom8(ty, val, False) );
+ putIReg( rA_addr, mkexpr(EA) );
+ break;
+
+ case 0x057: // lbzx (Load B & Zero, Indexed, PPC32 p436)
+ DIP("lbzx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
+- val = loadBE(Ity_I8, mkexpr(EA));
++ val = load(Ity_I8, mkexpr(EA));
+ putIReg( rD_addr, mkWidenFrom8(ty, val, False) );
+ break;
+
+@@ -4855,14 +4856,14 @@ static Bool dis_int_load ( UInt theInstr )
+ return False;
+ }
+ DIP("lhaux r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
+- val = loadBE(Ity_I16, mkexpr(EA));
++ val = load(Ity_I16, mkexpr(EA));
+ putIReg( rD_addr, mkWidenFrom16(ty, val, True) );
+ putIReg( rA_addr, mkexpr(EA) );
+ break;
+
+ case 0x157: // lhax (Load HW Alg, Indexed, PPC32 p448)
+ DIP("lhax r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
+- val = loadBE(Ity_I16, mkexpr(EA));
++ val = load(Ity_I16, mkexpr(EA));
+ putIReg( rD_addr, mkWidenFrom16(ty, val, True) );
+ break;
+
+@@ -4872,14 +4873,14 @@ static Bool dis_int_load ( UInt theInstr )
+ return False;
+ }
+ DIP("lhzux r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
+- val = loadBE(Ity_I16, mkexpr(EA));
++ val = load(Ity_I16, mkexpr(EA));
+ putIReg( rD_addr, mkWidenFrom16(ty, val, False) );
+ putIReg( rA_addr, mkexpr(EA) );
+ break;
+
+ case 0x117: // lhzx (Load HW & Zero, Indexed, PPC32 p453)
+ DIP("lhzx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
+- val = loadBE(Ity_I16, mkexpr(EA));
++ val = load(Ity_I16, mkexpr(EA));
+ putIReg( rD_addr, mkWidenFrom16(ty, val, False) );
+ break;
+
+@@ -4889,14 +4890,14 @@ static Bool dis_int_load ( UInt theInstr )
+ return False;
+ }
+ DIP("lwzux r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
+- val = loadBE(Ity_I32, mkexpr(EA));
++ val = load(Ity_I32, mkexpr(EA));
+ putIReg( rD_addr, mkWidenFrom32(ty, val, False) );
+ putIReg( rA_addr, mkexpr(EA) );
+ break;
+
+ case 0x017: // lwzx (Load W & Zero, Indexed, PPC32 p463)
+ DIP("lwzx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
+- val = loadBE(Ity_I32, mkexpr(EA));
++ val = load(Ity_I32, mkexpr(EA));
+ putIReg( rD_addr, mkWidenFrom32(ty, val, False) );
+ break;
+
+@@ -4908,13 +4909,13 @@ static Bool dis_int_load ( UInt theInstr )
+ return False;
+ }
+ DIP("ldux r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
+- putIReg( rD_addr, loadBE(Ity_I64, mkexpr(EA)) );
++ putIReg( rD_addr, load(Ity_I64, mkexpr(EA)) );
+ putIReg( rA_addr, mkexpr(EA) );
+ break;
+
+ case 0x015: // ldx (Load DWord, Indexed, PPC64 p476)
+ DIP("ldx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
+- putIReg( rD_addr, loadBE(Ity_I64, mkexpr(EA)) );
++ putIReg( rD_addr, load(Ity_I64, mkexpr(EA)) );
+ break;
+
+ case 0x175: // lwaux (Load W Alg, Update Indexed, PPC64 p501)
+@@ -4924,14 +4925,14 @@ static Bool dis_int_load ( UInt theInstr )
+ }
+ DIP("lwaux r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
+ putIReg( rD_addr,
+- unop(Iop_32Sto64, loadBE(Ity_I32, mkexpr(EA))) );
++ unop(Iop_32Sto64, load(Ity_I32, mkexpr(EA))) );
+ putIReg( rA_addr, mkexpr(EA) );
+ break;
+
+ case 0x155: // lwax (Load W Alg, Indexed, PPC64 p502)
+ DIP("lwax r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
+ putIReg( rD_addr,
+- unop(Iop_32Sto64, loadBE(Ity_I32, mkexpr(EA))) );
++ unop(Iop_32Sto64, load(Ity_I32, mkexpr(EA))) );
+ break;
+
+ default:
+@@ -4946,7 +4947,7 @@ static Bool dis_int_load ( UInt theInstr )
+ switch ((b1<<1) | b0) {
+ case 0x0: // ld (Load DWord, PPC64 p472)
+ DIP("ld r%u,%d(r%u)\n", rD_addr, simm16, rA_addr);
+- putIReg( rD_addr, loadBE(Ity_I64, mkexpr(EA)) );
++ putIReg( rD_addr, load(Ity_I64, mkexpr(EA)) );
+ break;
+
+ case 0x1: // ldu (Load DWord, Update, PPC64 p474)
+@@ -4955,14 +4956,14 @@ static Bool dis_int_load ( UInt theInstr )
+ return False;
+ }
+ DIP("ldu r%u,%d(r%u)\n", rD_addr, simm16, rA_addr);
+- putIReg( rD_addr, loadBE(Ity_I64, mkexpr(EA)) );
++ putIReg( rD_addr, load(Ity_I64, mkexpr(EA)) );
+ putIReg( rA_addr, mkexpr(EA) );
+ break;
+
+ case 0x2: // lwa (Load Word Alg, PPC64 p499)
+ DIP("lwa r%u,%d(r%u)\n", rD_addr, simm16, rA_addr);
+ putIReg( rD_addr,
+- unop(Iop_32Sto64, loadBE(Ity_I32, mkexpr(EA))) );
++ unop(Iop_32Sto64, load(Ity_I32, mkexpr(EA))) );
+ break;
+
+ default:
+@@ -4981,17 +4982,17 @@ static Bool dis_int_load ( UInt theInstr )
+ */
+ // trap if EA misaligned on 16 byte address
+ if (mode64) {
+- assign(high, loadBE(ty, mkexpr( EA ) ) );
+- assign(low, loadBE(ty, binop( Iop_Add64,
+- mkexpr( EA ),
+- mkU64( 8 ) ) ) );
++ assign(high, load(ty, mkexpr( EA ) ) );
++ assign(low, load(ty, binop( Iop_Add64,
++ mkexpr( EA ),
++ mkU64( 8 ) ) ) );
+ } else {
+- assign(high, loadBE(ty, binop( Iop_Add32,
+- mkexpr( EA ),
+- mkU32( 4 ) ) ) );
+- assign(low, loadBE(ty, binop( Iop_Add32,
+- mkexpr( EA ),
+- mkU32( 12 ) ) ) );
++ assign(high, load(ty, binop( Iop_Add32,
++ mkexpr( EA ),
++ mkU32( 4 ) ) ) );
++ assign(low, load(ty, binop( Iop_Add32,
++ mkexpr( EA ),
++ mkU32( 12 ) ) ) );
+ }
+ gen_SIGBUS_if_misaligned( EA, 16 );
+ putIReg( rD_addr, mkexpr( high) );
+@@ -5046,7 +5047,7 @@ static Bool dis_int_store ( UInt theInstr, VexAbiInfo* vbi )
+ switch (opc1) {
+ case 0x26: // stb (Store B, PPC32 p509)
+ DIP("stb r%u,%d(r%u)\n", rS_addr, simm16, rA_addr);
+- storeBE( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)) );
++ store( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)) );
+ break;
+
+ case 0x27: // stbu (Store B, Update, PPC32 p510)
+@@ -5056,12 +5057,12 @@ static Bool dis_int_store ( UInt theInstr, VexAbiInfo* vbi )
+ }
+ DIP("stbu r%u,%d(r%u)\n", rS_addr, simm16, rA_addr);
+ putIReg( rA_addr, mkexpr(EA) );
+- storeBE( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)) );
++ store( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)) );
+ break;
+
+ case 0x2C: // sth (Store HW, PPC32 p522)
+ DIP("sth r%u,%d(r%u)\n", rS_addr, simm16, rA_addr);
+- storeBE( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)) );
++ store( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)) );
+ break;
+
+ case 0x2D: // sthu (Store HW, Update, PPC32 p524)
+@@ -5071,12 +5072,12 @@ static Bool dis_int_store ( UInt theInstr, VexAbiInfo* vbi )
+ }
+ DIP("sthu r%u,%d(r%u)\n", rS_addr, simm16, rA_addr);
+ putIReg( rA_addr, mkexpr(EA) );
+- storeBE( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)) );
++ store( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)) );
+ break;
+
+ case 0x24: // stw (Store W, PPC32 p530)
+ DIP("stw r%u,%d(r%u)\n", rS_addr, simm16, rA_addr);
+- storeBE( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)) );
++ store( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)) );
+ break;
+
+ case 0x25: // stwu (Store W, Update, PPC32 p534)
+@@ -5086,7 +5087,7 @@ static Bool dis_int_store ( UInt theInstr, VexAbiInfo* vbi )
+ }
+ DIP("stwu r%u,%d(r%u)\n", rS_addr, simm16, rA_addr);
+ putIReg( rA_addr, mkexpr(EA) );
+- storeBE( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)) );
++ store( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)) );
+ break;
+
+ /* X Form : all these use EA_indexed */
+@@ -5104,12 +5105,12 @@ static Bool dis_int_store ( UInt theInstr, VexAbiInfo* vbi )
+ }
+ DIP("stbux r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);
+ putIReg( rA_addr, mkexpr(EA) );
+- storeBE( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)) );
++ store( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)) );
+ break;
+
+ case 0x0D7: // stbx (Store B Indexed, PPC32 p512)
+ DIP("stbx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);
+- storeBE( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)) );
++ store( mkexpr(EA), mkNarrowTo8(ty, mkexpr(rS)) );
+ break;
+
+ case 0x1B7: // sthux (Store HW, Update Indexed, PPC32 p525)
+@@ -5119,12 +5120,12 @@ static Bool dis_int_store ( UInt theInstr, VexAbiInfo* vbi )
+ }
+ DIP("sthux r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);
+ putIReg( rA_addr, mkexpr(EA) );
+- storeBE( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)) );
++ store( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)) );
+ break;
+
+ case 0x197: // sthx (Store HW Indexed, PPC32 p526)
+ DIP("sthx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);
+- storeBE( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)) );
++ store( mkexpr(EA), mkNarrowTo16(ty, mkexpr(rS)) );
+ break;
+
+ case 0x0B7: // stwux (Store W, Update Indexed, PPC32 p535)
+@@ -5134,12 +5135,12 @@ static Bool dis_int_store ( UInt theInstr, VexAbiInfo* vbi )
+ }
+ DIP("stwux r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);
+ putIReg( rA_addr, mkexpr(EA) );
+- storeBE( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)) );
++ store( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)) );
+ break;
+
+ case 0x097: // stwx (Store W Indexed, PPC32 p536)
+ DIP("stwx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);
+- storeBE( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)) );
++ store( mkexpr(EA), mkNarrowTo32(ty, mkexpr(rS)) );
+ break;
+
+
+@@ -5151,12 +5152,12 @@ static Bool dis_int_store ( UInt theInstr, VexAbiInfo* vbi )
+ }
+ DIP("stdux r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);
+ putIReg( rA_addr, mkexpr(EA) );
+- storeBE( mkexpr(EA), mkexpr(rS) );
++ store( mkexpr(EA), mkexpr(rS) );
+ break;
+
+ case 0x095: // stdx (Store DWord Indexed, PPC64 p585)
+ DIP("stdx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);
+- storeBE( mkexpr(EA), mkexpr(rS) );
++ store( mkexpr(EA), mkexpr(rS) );
+ break;
+
+ default:
+@@ -5174,7 +5175,7 @@ static Bool dis_int_store ( UInt theInstr, VexAbiInfo* vbi )
+ return False;
+
+ DIP("std r%u,%d(r%u)\n", rS_addr, simm16, rA_addr);
+- storeBE( mkexpr(EA), mkexpr(rS) );
++ store( mkexpr(EA), mkexpr(rS) );
+ break;
+
+ case 0x1: // stdu (Store DWord, Update, PPC64 p583)
+@@ -5183,7 +5184,7 @@ static Bool dis_int_store ( UInt theInstr, VexAbiInfo* vbi )
+
+ DIP("stdu r%u,%d(r%u)\n", rS_addr, simm16, rA_addr);
+ putIReg( rA_addr, mkexpr(EA) );
+- storeBE( mkexpr(EA), mkexpr(rS) );
++ store( mkexpr(EA), mkexpr(rS) );
+ break;
+
+ case 0x2: { // stq (Store QuadWord, Update, PPC64 p583)
+@@ -5205,9 +5206,9 @@ static Bool dis_int_store ( UInt theInstr, VexAbiInfo* vbi )
+ assign( EA_lo, ea_rAor0_simm( rA_addr, simm16+12 ) );
+ }
+ putIReg( rA_addr, mkexpr(EA_hi) );
+- storeBE( mkexpr(EA_hi), mkexpr(rS) );
++ store( mkexpr(EA_hi), mkexpr(rS) );
+ putIReg( rA_addr, mkexpr( EA_lo) );
+- storeBE( mkexpr(EA_lo), getIReg( rS_addr+1 ) );
++ store( mkexpr(EA_lo), getIReg( rS_addr+1 ) );
+ break;
+ }
+ default:
+@@ -5256,7 +5257,7 @@ static Bool dis_int_ldst_mult ( UInt theInstr )
+ DIP("lmw r%u,%d(r%u)\n", rD_addr, simm16, rA_addr);
+ for (r = rD_addr; r <= 31; r++) {
+ irx_addr = binop(mkAdd, mkexpr(EA), mode64 ? mkU64(ea_off) : mkU32(ea_off));
+- putIReg( r, mkWidenFrom32(ty, loadBE(Ity_I32, irx_addr ),
++ putIReg( r, mkWidenFrom32(ty, load(Ity_I32, irx_addr ),
+ False) );
+ ea_off += 4;
+ }
+@@ -5266,7 +5267,7 @@ static Bool dis_int_ldst_mult ( UInt theInstr )
+ DIP("stmw r%u,%d(r%u)\n", rS_addr, simm16, rA_addr);
+ for (r = rS_addr; r <= 31; r++) {
+ irx_addr = binop(mkAdd, mkexpr(EA), mode64 ? mkU64(ea_off) : mkU32(ea_off));
+- storeBE( irx_addr, mkNarrowTo32(ty, getIReg(r)) );
++ store( irx_addr, mkNarrowTo32(ty, getIReg(r)) );
+ ea_off += 4;
+ }
+ break;
+@@ -5321,8 +5322,9 @@ void generate_lsw_sequence ( IRTemp tNBytes, // # bytes, :: Ity_I32
+ Iop_Shl32,
+ unop(
+ Iop_8Uto32,
+- loadBE(Ity_I8,
+- binop(mkSzOp(ty,Iop_Add8), e_EA, mkSzImm(ty,i)))
++ load( Ity_I8,
++ binop( mkSzOp(ty,Iop_Add8),
++ e_EA, mkSzImm(ty,i)))
+ ),
+ mkU8(toUChar(shift))
+ )
+@@ -5360,12 +5362,12 @@ void generate_stsw_sequence ( IRTemp tNBytes, // # bytes, :: Ity_I32
+ }
+ /* *(EA+i) = 32to8(rS >> shift) */
+ vassert(shift == 0 || shift == 8 || shift == 16 || shift == 24);
+- storeBE(
+- binop(mkSzOp(ty,Iop_Add8), e_EA, mkSzImm(ty,i)),
+- unop(Iop_32to8,
+- binop(Iop_Shr32,
+- mkNarrowTo32(ty, getIReg(rS)),
+- mkU8(toUChar(shift))))
++ store(
++ binop( mkSzOp(ty,Iop_Add8), e_EA, mkSzImm(ty,i)),
++ unop( Iop_32to8,
++ binop( Iop_Shr32,
++ mkNarrowTo32( ty, getIReg(rS) ),
++ mkU8( toUChar(shift) )))
+ );
+ shift -= 8;
+ }
+@@ -5404,10 +5406,10 @@ static Bool dis_int_ldst_str ( UInt theInstr, /*OUT*/Bool* stopHere )
+ /* Special case hack */
+ /* rD = Mem[EA]; (rD+1)%32 = Mem[EA+4] */
+ putIReg( rD_addr,
+- loadBE(Ity_I32, mkexpr(t_EA)) );
++ load(Ity_I32, mkexpr(t_EA)) );
+ putIReg( (rD_addr+1) % 32,
+- loadBE(Ity_I32,
+- binop(Iop_Add32, mkexpr(t_EA), mkU32(4))) );
++ load(Ity_I32,
++ binop(Iop_Add32, mkexpr(t_EA), mkU32(4))) );
+ } else {
+ t_nbytes = newTemp(Ity_I32);
+ assign( t_nbytes, mkU32(NumBytes==0 ? 32 : NumBytes) );
+@@ -5439,10 +5441,10 @@ static Bool dis_int_ldst_str ( UInt theInstr, /*OUT*/Bool* stopHere )
+ if (NumBytes == 8 && !mode64) {
+ /* Special case hack */
+ /* Mem[EA] = rD; Mem[EA+4] = (rD+1)%32 */
+- storeBE( mkexpr(t_EA),
+- getIReg(rD_addr) );
+- storeBE( binop(Iop_Add32, mkexpr(t_EA), mkU32(4)),
+- getIReg((rD_addr+1) % 32) );
++ store( mkexpr(t_EA),
++ getIReg(rD_addr) );
++ store( binop(Iop_Add32, mkexpr(t_EA), mkU32(4)),
++ getIReg((rD_addr+1) % 32) );
+ } else {
+ t_nbytes = newTemp(Ity_I32);
+ assign( t_nbytes, mkU32(NumBytes==0 ? 32 : NumBytes) );
+@@ -6145,7 +6147,7 @@ static Bool dis_memsync ( UInt theInstr )
+
+ // and actually do the load
+ res = newTemp(Ity_I32);
+- stmt( IRStmt_LLSC(Iend_BE, res, mkexpr(EA), NULL/*this is a load*/) );
++ stmt( IRStmt_LLSC(IENDIANESS, res, mkexpr(EA), NULL/*this is a load*/) );
+
+ putIReg( rD_addr, mkWidenFrom32(ty, mkexpr(res), False) );
+ break;
+@@ -6171,7 +6173,7 @@ static Bool dis_memsync ( UInt theInstr )
+
+ // Do the store, and get success/failure bit into resSC
+ resSC = newTemp(Ity_I1);
+- stmt( IRStmt_LLSC(Iend_BE, resSC, mkexpr(EA), mkexpr(rS)) );
++ stmt( IRStmt_LLSC(IENDIANESS, resSC, mkexpr(EA), mkexpr(rS)) );
+
+ // Set CR0[LT GT EQ S0] = 0b000 || XER[SO] on failure
+ // Set CR0[LT GT EQ S0] = 0b001 || XER[SO] on success
+@@ -6238,7 +6240,7 @@ static Bool dis_memsync ( UInt theInstr )
+
+ // and actually do the load
+ res = newTemp(Ity_I64);
+- stmt( IRStmt_LLSC(Iend_BE, res, mkexpr(EA), NULL/*this is a load*/) );
++ stmt( IRStmt_LLSC(IENDIANESS, res, mkexpr(EA), NULL/*this is a load*/) );
+
+ putIReg( rD_addr, mkexpr(res) );
+ break;
+@@ -6264,7 +6266,7 @@ static Bool dis_memsync ( UInt theInstr )
+
+ // Do the store, and get success/failure bit into resSC
+ resSC = newTemp(Ity_I1);
+- stmt( IRStmt_LLSC(Iend_BE, resSC, mkexpr(EA), mkexpr(rS)) );
++ stmt( IRStmt_LLSC(IENDIANESS, resSC, mkexpr(EA), mkexpr(rS)) );
+
+ // Set CR0[LT GT EQ S0] = 0b000 || XER[SO] on failure
+ // Set CR0[LT GT EQ S0] = 0b001 || XER[SO] on success
+@@ -6294,16 +6296,16 @@ static Bool dis_memsync ( UInt theInstr )
+
+ // and actually do the load
+ if (mode64) {
+- stmt( IRStmt_LLSC( Iend_BE, res_hi,
++ stmt( IRStmt_LLSC( IENDIANESS, res_hi,
+ mkexpr(EA), NULL/*this is a load*/) );
+- stmt( IRStmt_LLSC( Iend_BE, res_lo,
++ stmt( IRStmt_LLSC( IENDIANESS, res_lo,
+ binop(Iop_Add64, mkexpr(EA), mkU64(8) ),
+ NULL/*this is a load*/) );
+ } else {
+- stmt( IRStmt_LLSC( Iend_BE, res_hi,
++ stmt( IRStmt_LLSC( IENDIANESS, res_hi,
+ binop( Iop_Add32, mkexpr(EA), mkU32(4) ),
+ NULL/*this is a load*/) );
+- stmt( IRStmt_LLSC( Iend_BE, res_lo,
++ stmt( IRStmt_LLSC( IENDIANESS, res_lo,
+ binop( Iop_Add32, mkexpr(EA), mkU32(12) ),
+ NULL/*this is a load*/) );
+ }
+@@ -6334,14 +6336,14 @@ static Bool dis_memsync ( UInt theInstr )
+ resSC = newTemp(Ity_I1);
+
+ if (mode64) {
+- stmt( IRStmt_LLSC( Iend_BE, resSC, mkexpr(EA), mkexpr(rS_hi) ) );
+- storeBE(binop( Iop_Add64, mkexpr(EA), mkU64(8) ), mkexpr(rS_lo) );
++ stmt( IRStmt_LLSC( IENDIANESS, resSC, mkexpr(EA), mkexpr(rS_hi) ) );
++ store( binop( Iop_Add64, mkexpr(EA), mkU64(8) ), mkexpr(rS_lo) );
+ } else {
+- stmt( IRStmt_LLSC( Iend_BE, resSC, binop( Iop_Add32,
+- mkexpr(EA),
+- mkU32(4) ),
+- mkexpr(rS_hi) ) );
+- storeBE(binop(Iop_Add32, mkexpr(EA), mkU32(12) ), mkexpr(rS_lo) );
++ stmt( IRStmt_LLSC( IENDIANESS, resSC, binop( Iop_Add32,
++ mkexpr(EA),
++ mkU32(4) ),
++ mkexpr(rS_hi) ) );
++ store( binop(Iop_Add32, mkexpr(EA), mkU32(12) ), mkexpr(rS_lo) );
+ }
+
+ // Set CR0[LT GT EQ S0] = 0b000 || XER[SO] on failure
+@@ -6664,7 +6666,7 @@ static Bool dis_int_ldst_rev ( UInt theInstr )
+
+ case 0x316: // lhbrx (Load Halfword Byte-Reverse Indexed, PPC32 p449)
+ DIP("lhbrx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
+- assign( w1, unop(Iop_16Uto32, loadBE(Ity_I16, mkexpr(EA))) );
++ assign( w1, unop(Iop_16Uto32, load(Ity_I16, mkexpr(EA))) );
+ assign( w2, gen_byterev16(w1) );
+ putIReg( rD_addr, mkWidenFrom32(ty, mkexpr(w2),
+ /* Signed */False) );
+@@ -6672,7 +6674,7 @@ static Bool dis_int_ldst_rev ( UInt theInstr )
+
+ case 0x216: // lwbrx (Load Word Byte-Reverse Indexed, PPC32 p459)
+ DIP("lwbrx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
+- assign( w1, loadBE(Ity_I32, mkexpr(EA)) );
++ assign( w1, load(Ity_I32, mkexpr(EA)) );
+ assign( w2, gen_byterev32(w1) );
+ putIReg( rD_addr, mkWidenFrom32(ty, mkexpr(w2),
+ /* Signed */False) );
+@@ -6684,11 +6686,11 @@ static Bool dis_int_ldst_rev ( UInt theInstr )
+ IRTemp w3 = newTemp( Ity_I32 );
+ IRTemp w4 = newTemp( Ity_I32 );
+ DIP("ldbrx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
+- assign( w1, loadBE( Ity_I32, mkexpr( EA ) ) );
++ assign( w1, load( Ity_I32, mkexpr( EA ) ) );
+ assign( w2, gen_byterev32( w1 ) );
+ nextAddr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( 4 ) : mkU32( 4 ) );
+- assign( w3, loadBE( Ity_I32, nextAddr ) );
++ assign( w3, load( Ity_I32, nextAddr ) );
+ assign( w4, gen_byterev32( w3 ) );
+ putIReg( rD_addr, binop( Iop_32HLto64, mkexpr( w4 ), mkexpr( w2 ) ) );
+ break;
+@@ -6697,13 +6699,13 @@ static Bool dis_int_ldst_rev ( UInt theInstr )
+ case 0x396: // sthbrx (Store Half Word Byte-Reverse Indexed, PPC32 p523)
+ DIP("sthbrx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);
+ assign( w1, mkNarrowTo32(ty, getIReg(rS_addr)) );
+- storeBE( mkexpr(EA), unop(Iop_32to16, gen_byterev16(w1)) );
++ store( mkexpr(EA), unop(Iop_32to16, gen_byterev16(w1)) );
+ break;
+
+ case 0x296: // stwbrx (Store Word Byte-Reverse Indxd, PPC32 p531)
+ DIP("stwbrx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);
+ assign( w1, mkNarrowTo32(ty, getIReg(rS_addr)) );
+- storeBE( mkexpr(EA), gen_byterev32(w1) );
++ store( mkexpr(EA), gen_byterev32(w1) );
+ break;
+
+ case 0x294: // stdbrx (Store Doubleword Byte-Reverse Indexed)
+@@ -6715,8 +6717,9 @@ static Bool dis_int_ldst_rev ( UInt theInstr )
+ DIP("stdbrx r%u,r%u,r%u\n", rS_addr, rA_addr, rB_addr);
+ assign(lo, unop(Iop_64HIto32, mkexpr(rS)));
+ assign(hi, unop(Iop_64to32, mkexpr(rS)));
+- storeBE( mkexpr( EA ),
+- binop( Iop_32HLto64, gen_byterev32( hi ), gen_byterev32( lo ) ) );
++ store( mkexpr( EA ),
++ binop( Iop_32HLto64, gen_byterev32( hi ),
++ gen_byterev32( lo ) ) );
+ break;
+ }
+
+@@ -7234,7 +7237,7 @@ static Bool dis_cache_manage ( UInt theInstr,
+
+ for (i = 0; i < clearszB / 8; i++) {
+ irx_addr = binop( Iop_Add64, mkexpr(addr), mkU64(i*8) );
+- storeBE( irx_addr, mkU64(0) );
++ store( irx_addr, mkU64(0) );
+ }
+ } else {
+ /* Round EA down to the start of the containing block. */
+@@ -7244,7 +7247,7 @@ static Bool dis_cache_manage ( UInt theInstr,
+
+ for (i = 0; i < clearszB / 4; i++) {
+ irx_addr = binop( Iop_Add32, mkexpr(addr), mkU32(i*4) );
+- storeBE( irx_addr, mkU32(0) );
++ store( irx_addr, mkU32(0) );
+ }
+ }
+ break;
+@@ -7464,7 +7467,7 @@ static Bool dis_fp_load ( UInt theInstr )
+ DIP("lfs fr%u,%d(r%u)\n", frD_addr, simm16, rA_addr);
+ assign( EA, ea_rAor0_simm(rA_addr, simm16) );
+ putFReg( frD_addr,
+- unop(Iop_F32toF64, loadBE(Ity_F32, mkexpr(EA))) );
++ unop(Iop_F32toF64, load(Ity_F32, mkexpr(EA))) );
+ break;
+
+ case 0x31: // lfsu (Load Float Single, Update, PPC32 p442)
+@@ -7473,14 +7476,14 @@ static Bool dis_fp_load ( UInt theInstr )
+ DIP("lfsu fr%u,%d(r%u)\n", frD_addr, simm16, rA_addr);
+ assign( EA, ea_rA_simm(rA_addr, simm16) );
+ putFReg( frD_addr,
+- unop(Iop_F32toF64, loadBE(Ity_F32, mkexpr(EA))) );
++ unop(Iop_F32toF64, load(Ity_F32, mkexpr(EA))) );
+ putIReg( rA_addr, mkexpr(EA) );
+ break;
+
+ case 0x32: // lfd (Load Float Double, PPC32 p437)
+ DIP("lfd fr%u,%d(r%u)\n", frD_addr, simm16, rA_addr);
+ assign( EA, ea_rAor0_simm(rA_addr, simm16) );
+- putFReg( frD_addr, loadBE(Ity_F64, mkexpr(EA)) );
++ putFReg( frD_addr, load(Ity_F64, mkexpr(EA)) );
+ break;
+
+ case 0x33: // lfdu (Load Float Double, Update, PPC32 p438)
+@@ -7488,7 +7491,7 @@ static Bool dis_fp_load ( UInt theInstr )
+ return False;
+ DIP("lfdu fr%u,%d(r%u)\n", frD_addr, simm16, rA_addr);
+ assign( EA, ea_rA_simm(rA_addr, simm16) );
+- putFReg( frD_addr, loadBE(Ity_F64, mkexpr(EA)) );
++ putFReg( frD_addr, load(Ity_F64, mkexpr(EA)) );
+ putIReg( rA_addr, mkexpr(EA) );
+ break;
+
+@@ -7503,7 +7506,7 @@ static Bool dis_fp_load ( UInt theInstr )
+ DIP("lfsx fr%u,r%u,r%u\n", frD_addr, rA_addr, rB_addr);
+ assign( EA, ea_rAor0_idxd(rA_addr, rB_addr) );
+ putFReg( frD_addr, unop( Iop_F32toF64,
+- loadBE(Ity_F32, mkexpr(EA))) );
++ load(Ity_F32, mkexpr(EA))) );
+ break;
+
+ case 0x237: // lfsux (Load Float Single, Update Indxd, PPC32 p443)
+@@ -7512,14 +7515,14 @@ static Bool dis_fp_load ( UInt theInstr )
+ DIP("lfsux fr%u,r%u,r%u\n", frD_addr, rA_addr, rB_addr);
+ assign( EA, ea_rA_idxd(rA_addr, rB_addr) );
+ putFReg( frD_addr,
+- unop(Iop_F32toF64, loadBE(Ity_F32, mkexpr(EA))) );
++ unop(Iop_F32toF64, load(Ity_F32, mkexpr(EA))) );
+ putIReg( rA_addr, mkexpr(EA) );
+ break;
+
+ case 0x257: // lfdx (Load Float Double Indexed, PPC32 p440)
+ DIP("lfdx fr%u,r%u,r%u\n", frD_addr, rA_addr, rB_addr);
+ assign( EA, ea_rAor0_idxd(rA_addr, rB_addr) );
+- putFReg( frD_addr, loadBE(Ity_F64, mkexpr(EA)) );
++ putFReg( frD_addr, load(Ity_F64, mkexpr(EA)) );
+ break;
+
+ case 0x277: // lfdux (Load Float Double, Update Indxd, PPC32 p439)
+@@ -7527,14 +7530,14 @@ static Bool dis_fp_load ( UInt theInstr )
+ return False;
+ DIP("lfdux fr%u,r%u,r%u\n", frD_addr, rA_addr, rB_addr);
+ assign( EA, ea_rA_idxd(rA_addr, rB_addr) );
+- putFReg( frD_addr, loadBE(Ity_F64, mkexpr(EA)) );
++ putFReg( frD_addr, load(Ity_F64, mkexpr(EA)) );
+ putIReg( rA_addr, mkexpr(EA) );
+ break;
+
+ case 0x357: // lfiwax (Load Float As Integer, Indxd, ISA 2.05 p120)
+ DIP("lfiwax fr%u,r%u,r%u\n", frD_addr, rA_addr, rB_addr);
+ assign( EA, ea_rAor0_idxd( rA_addr, rB_addr ) );
+- assign( iLo, loadBE(Ity_I32, mkexpr(EA)) );
++ assign( iLo, load(Ity_I32, mkexpr(EA)) );
+ assign( iHi, binop(Iop_Sub32,
+ mkU32(0),
+ binop(Iop_Shr32, mkexpr(iLo), mkU8(31))) );
+@@ -7547,7 +7550,7 @@ static Bool dis_fp_load ( UInt theInstr )
+ IRTemp dw = newTemp( Ity_I64 );
+ DIP("lfiwzx fr%u,r%u,r%u\n", frD_addr, rA_addr, rB_addr);
+ assign( EA, ea_rAor0_idxd( rA_addr, rB_addr ) );
+- assign( iLo, loadBE(Ity_I32, mkexpr(EA)) );
++ assign( iLo, load(Ity_I32, mkexpr(EA)) );
+ assign( dw, binop( Iop_32HLto64, mkU32( 0 ), mkexpr( iLo ) ) );
+ putFReg( frD_addr, unop( Iop_ReinterpI64asF64, mkexpr( dw ) ) );
+ break;
+@@ -7606,8 +7609,7 @@ static Bool dis_fp_store ( UInt theInstr )
+ /* Use Iop_TruncF64asF32 to truncate and possible denormalise
+ the value to be stored in the correct way, without any
+ rounding. */
+- storeBE( mkexpr(EA),
+- unop(Iop_TruncF64asF32, mkexpr(frS)) );
++ store( mkexpr(EA), unop(Iop_TruncF64asF32, mkexpr(frS)) );
+ break;
+
+ case 0x35: // stfsu (Store Float Single, Update, PPC32 p519)
+@@ -7616,15 +7618,14 @@ static Bool dis_fp_store ( UInt theInstr )
+ DIP("stfsu fr%u,%d(r%u)\n", frS_addr, simm16, rA_addr);
+ assign( EA, ea_rA_simm(rA_addr, simm16) );
+ /* See comment for stfs */
+- storeBE( mkexpr(EA),
+- unop(Iop_TruncF64asF32, mkexpr(frS)) );
++ store( mkexpr(EA), unop(Iop_TruncF64asF32, mkexpr(frS)) );
+ putIReg( rA_addr, mkexpr(EA) );
+ break;
+
+ case 0x36: // stfd (Store Float Double, PPC32 p513)
+ DIP("stfd fr%u,%d(r%u)\n", frS_addr, simm16, rA_addr);
+ assign( EA, ea_rAor0_simm(rA_addr, simm16) );
+- storeBE( mkexpr(EA), mkexpr(frS) );
++ store( mkexpr(EA), mkexpr(frS) );
+ break;
+
+ case 0x37: // stfdu (Store Float Double, Update, PPC32 p514)
+@@ -7632,7 +7633,7 @@ static Bool dis_fp_store ( UInt theInstr )
+ return False;
+ DIP("stfdu fr%u,%d(r%u)\n", frS_addr, simm16, rA_addr);
+ assign( EA, ea_rA_simm(rA_addr, simm16) );
+- storeBE( mkexpr(EA), mkexpr(frS) );
++ store( mkexpr(EA), mkexpr(frS) );
+ putIReg( rA_addr, mkexpr(EA) );
+ break;
+
+@@ -7646,8 +7647,8 @@ static Bool dis_fp_store ( UInt theInstr )
+ DIP("stfsx fr%u,r%u,r%u\n", frS_addr, rA_addr, rB_addr);
+ assign( EA, ea_rAor0_idxd(rA_addr, rB_addr) );
+ /* See note for stfs */
+- storeBE( mkexpr(EA),
+- unop(Iop_TruncF64asF32, mkexpr(frS)) );
++ store( mkexpr(EA),
++ unop(Iop_TruncF64asF32, mkexpr(frS)) );
+ break;
+
+ case 0x2B7: // stfsux (Store Float Sgl, Update Indxd, PPC32 p520)
+@@ -7656,15 +7657,14 @@ static Bool dis_fp_store ( UInt theInstr )
+ DIP("stfsux fr%u,r%u,r%u\n", frS_addr, rA_addr, rB_addr);
+ assign( EA, ea_rA_idxd(rA_addr, rB_addr) );
+ /* See note for stfs */
+- storeBE( mkexpr(EA),
+- unop(Iop_TruncF64asF32, mkexpr(frS)) );
++ store( mkexpr(EA), unop(Iop_TruncF64asF32, mkexpr(frS)) );
+ putIReg( rA_addr, mkexpr(EA) );
+ break;
+
+ case 0x2D7: // stfdx (Store Float Double Indexed, PPC32 p516)
+ DIP("stfdx fr%u,r%u,r%u\n", frS_addr, rA_addr, rB_addr);
+ assign( EA, ea_rAor0_idxd(rA_addr, rB_addr) );
+- storeBE( mkexpr(EA), mkexpr(frS) );
++ store( mkexpr(EA), mkexpr(frS) );
+ break;
+
+ case 0x2F7: // stfdux (Store Float Dbl, Update Indxd, PPC32 p515)
+@@ -7672,7 +7672,7 @@ static Bool dis_fp_store ( UInt theInstr )
+ return False;
+ DIP("stfdux fr%u,r%u,r%u\n", frS_addr, rA_addr, rB_addr);
+ assign( EA, ea_rA_idxd(rA_addr, rB_addr) );
+- storeBE( mkexpr(EA), mkexpr(frS) );
++ store( mkexpr(EA), mkexpr(frS) );
+ putIReg( rA_addr, mkexpr(EA) );
+ break;
+
+@@ -7680,8 +7680,8 @@ static Bool dis_fp_store ( UInt theInstr )
+ // NOTE: POWERPC OPTIONAL, "Graphics Group" (PPC32_GX)
+ DIP("stfiwx fr%u,r%u,r%u\n", frS_addr, rA_addr, rB_addr);
+ assign( EA, ea_rAor0_idxd(rA_addr, rB_addr) );
+- storeBE( mkexpr(EA),
+- unop(Iop_64to32, unop(Iop_ReinterpF64asI64, mkexpr(frS))) );
++ store( mkexpr(EA),
++ unop(Iop_64to32, unop(Iop_ReinterpF64asI64, mkexpr(frS))) );
+ break;
+
+ default:
+@@ -8867,11 +8867,11 @@ static Bool dis_fp_pair ( UInt theInstr )
+ assign( frT_lo, getFReg(frT_lo_addr) );
+
+ if (is_load) {
+- putFReg( frT_hi_addr, loadBE(Ity_F64, mkexpr(EA_hi)) );
+- putFReg( frT_lo_addr, loadBE(Ity_F64, mkexpr(EA_lo)) );
++ putFReg( frT_hi_addr, load(Ity_F64, mkexpr(EA_hi)) );
++ putFReg( frT_lo_addr, load(Ity_F64, mkexpr(EA_lo)) );
+ } else {
+- storeBE( mkexpr(EA_hi), mkexpr(frT_hi) );
+- storeBE( mkexpr(EA_lo), mkexpr(frT_lo) );
++ store( mkexpr(EA_hi), mkexpr(frT_hi) );
++ store( mkexpr(EA_lo), mkexpr(frT_lo) );
+ }
+
+ return True;
+@@ -15072,7 +15072,7 @@ dis_vx_load ( UInt theInstr )
+ {
+ IRExpr * exp;
+ DIP("lxsiwzx %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr);
+- exp = unop( Iop_64HIto32, loadBE( Ity_I64, mkexpr( EA ) ) );
++ exp = unop( Iop_64HIto32, load( Ity_I64, mkexpr( EA ) ) );
+ putVSReg( XT, binop( Iop_64HLtoV128,
+ unop( Iop_32Uto64, exp),
+ mkU64(0) ) );
+@@ -15082,7 +15082,7 @@ dis_vx_load ( UInt theInstr )
+ {
+ IRExpr * exp;
+ DIP("lxsiwax %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr);
+- exp = unop( Iop_64HIto32, loadBE( Ity_I64, mkexpr( EA ) ) );
++ exp = unop( Iop_64HIto32, load( Ity_I64, mkexpr( EA ) ) );
+ putVSReg( XT, binop( Iop_64HLtoV128,
+ unop( Iop_32Sto64, exp),
+ mkU64(0) ) );
+@@ -15099,8 +15099,7 @@ dis_vx_load ( UInt theInstr )
+ exp = unop( Iop_ReinterpF64asI64,
+ unop( Iop_F32toF64,
+ unop( Iop_ReinterpI32asF32,
+- unop( Iop_64HIto32,
+- loadBE( Ity_I64, mkexpr( EA ) ) ) ) ) );
++ load( Ity_I32, mkexpr( EA ) ) ) ) );
+
+ putVSReg( XT, binop( Iop_64HLtoV128, exp, mkU64( 0 ) ) );
+ break;
+@@ -15109,7 +15108,7 @@ dis_vx_load ( UInt theInstr )
+ {
+ IRExpr * exp;
+ DIP("lxsdx %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr);
+- exp = loadBE( Ity_I64, mkexpr( EA ) );
++ exp = load( Ity_I64, mkexpr( EA ) );
+ // We need to pass an expression of type Ity_V128 with putVSReg, but the load
+ // we just performed is only a DW. But since the contents of VSR[XT] element 1
+ // are undefined after this operation, we can just do a splat op.
+@@ -15123,10 +15122,10 @@ dis_vx_load ( UInt theInstr )
+ ULong ea_off = 8;
+ IRExpr* high_addr;
+ DIP("lxvd2x %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr);
+- high = loadBE( Ity_I64, mkexpr( EA ) );
++ high = load( Ity_I64, mkexpr( EA ) );
+ high_addr = binop( addOp, mkexpr( EA ), ty == Ity_I64 ? mkU64( ea_off )
+ : mkU32( ea_off ) );
+- low = loadBE( Ity_I64, high_addr );
++ low = load( Ity_I64, high_addr );
+ putVSReg( XT, binop( Iop_64HLtoV128, high, low ) );
+ break;
+ }
+@@ -15134,7 +15133,7 @@ dis_vx_load ( UInt theInstr )
+ {
+ IRTemp data = newTemp(Ity_I64);
+ DIP("lxvdsx %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr);
+- assign( data, loadBE( Ity_I64, mkexpr( EA ) ) );
++ assign( data, load( Ity_I64, mkexpr( EA ) ) );
+ putVSReg( XT, binop( Iop_64HLtoV128, mkexpr( data ), mkexpr( data ) ) );
+ break;
+ }
+@@ -15145,19 +15144,19 @@ dis_vx_load ( UInt theInstr )
+ IRExpr* irx_addr;
+
+ DIP("lxvw4x %d,r%u,r%u\n", (UInt)XT, rA_addr, rB_addr);
+- t3 = loadBE( Ity_I32, mkexpr( EA ) );
++ t3 = load( Ity_I32, mkexpr( EA ) );
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+- t2 = loadBE( Ity_I32, irx_addr );
++ t2 = load( Ity_I32, irx_addr );
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+- t1 = loadBE( Ity_I32, irx_addr );
++ t1 = load( Ity_I32, irx_addr );
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+- t0 = loadBE( Ity_I32, irx_addr );
++ t0 = load( Ity_I32, irx_addr );
+ putVSReg( XT, binop( Iop_64HLtoV128, binop( Iop_32HLto64, t3, t2 ),
+ binop( Iop_32HLto64, t1, t0 ) ) );
+ break;
+@@ -15205,7 +15204,7 @@ dis_vx_store ( UInt theInstr )
+ DIP("stxsiwx %d,r%u,r%u\n", (UInt)XS, rA_addr, rB_addr);
+ high64 = unop( Iop_V128HIto64, mkexpr( vS ) );
+ low32 = unop( Iop_64to32, high64 );
+- storeBE( mkexpr( EA ), low32 );
++ store( mkexpr( EA ), low32 );
+ break;
+ }
+ case 0x28C:
+@@ -15218,7 +15217,7 @@ dis_vx_store ( UInt theInstr )
+ assign(val32, unop( Iop_ReinterpF32asI32,
+ unop( Iop_TruncF64asF32,
+ mkexpr(high64) ) ) );
+- storeBE( mkexpr( EA ), mkexpr( val32 ) );
++ store( mkexpr( EA ), mkexpr( val32 ) );
+ break;
+ }
+ case 0x2CC:
+@@ -15226,7 +15225,7 @@ dis_vx_store ( UInt theInstr )
+ IRExpr * high64;
+ DIP("stxsdx %d,r%u,r%u\n", (UInt)XS, rA_addr, rB_addr);
+ high64 = unop( Iop_V128HIto64, mkexpr( vS ) );
+- storeBE( mkexpr( EA ), high64 );
++ store( mkexpr( EA ), high64 );
+ break;
+ }
+ case 0x3CC:
+@@ -15235,9 +15234,9 @@ dis_vx_store ( UInt theInstr )
+ DIP("stxvd2x %d,r%u,r%u\n", (UInt)XS, rA_addr, rB_addr);
+ high64 = unop( Iop_V128HIto64, mkexpr( vS ) );
+ low64 = unop( Iop_V128to64, mkexpr( vS ) );
+- storeBE( mkexpr( EA ), high64 );
+- storeBE( binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ), ty == Ity_I64 ? mkU64( 8 )
+- : mkU32( 8 ) ), low64 );
++ store( mkexpr( EA ), high64 );
++ store( binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
++ ty == Ity_I64 ? mkU64( 8 ) : mkU32( 8 ) ), low64 );
+ break;
+ }
+ case 0x38C:
+@@ -15253,20 +15252,19 @@ dis_vx_store ( UInt theInstr )
+ // quad-word aligned. Therefore, do 4 individual word-size stores.
+ assign( hi64, unop( Iop_V128HIto64, mkexpr( vS ) ) );
+ assign( lo64, unop( Iop_V128to64, mkexpr( vS ) ) );
+-
+- storeBE( mkexpr( EA ), unop( Iop_64HIto32, mkexpr( hi64 ) ) );
++ store( mkexpr( EA ), unop( Iop_64HIto32, mkexpr( hi64 ) ) );
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+- storeBE( irx_addr, unop( Iop_64to32, mkexpr( hi64 ) ) );
++ store( irx_addr, unop( Iop_64to32, mkexpr( hi64 ) ) );
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+- storeBE( irx_addr, unop( Iop_64HIto32, mkexpr( lo64 ) ) );
++ store( irx_addr, unop( Iop_64HIto32, mkexpr( lo64 ) ) );
+ ea_off += 4;
+ irx_addr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
+ ty == Ity_I64 ? mkU64( ea_off ) : mkU32( ea_off ) );
+- storeBE( irx_addr, unop( Iop_64to32, mkexpr( lo64 ) ) );
++ store( irx_addr, unop( Iop_64to32, mkexpr( lo64 ) ) );
+
+ break;
+ }
+@@ -15498,29 +15496,29 @@ static Bool dis_av_load ( VexAbiInfo* vbi, UInt theInstr )
+ /* loads addressed byte into vector[EA[0:3]
+ since all other destination bytes are undefined,
+ can simply load entire vector from 16-aligned EA */
+- putVReg( vD_addr, loadBE(Ity_V128, mkexpr(EA_align16)) );
++ putVReg( vD_addr, load(Ity_V128, mkexpr(EA_align16)) );
+ break;
+
+ case 0x027: // lvehx (Load Vector Element Half Word Indexed, AV p121)
+ DIP("lvehx v%d,r%u,r%u\n", vD_addr, rA_addr, rB_addr);
+ /* see note for lvebx */
+- putVReg( vD_addr, loadBE(Ity_V128, mkexpr(EA_align16)) );
++ putVReg( vD_addr, load(Ity_V128, mkexpr(EA_align16)) );
+ break;
+
+ case 0x047: // lvewx (Load Vector Element Word Indexed, AV p122)
+ DIP("lvewx v%d,r%u,r%u\n", vD_addr, rA_addr, rB_addr);
+ /* see note for lvebx */
+- putVReg( vD_addr, loadBE(Ity_V128, mkexpr(EA_align16)) );
++ putVReg( vD_addr, load(Ity_V128, mkexpr(EA_align16)) );
+ break;
+
+ case 0x067: // lvx (Load Vector Indexed, AV p127)
+ DIP("lvx v%d,r%u,r%u\n", vD_addr, rA_addr, rB_addr);
+- putVReg( vD_addr, loadBE(Ity_V128, mkexpr(EA_align16)) );
++ putVReg( vD_addr, load(Ity_V128, mkexpr(EA_align16)) );
+ break;
+
+ case 0x167: // lvxl (Load Vector Indexed LRU, AV p128)
+ DIP("lvxl v%d,r%u,r%u\n", vD_addr, rA_addr, rB_addr);
+- putVReg( vD_addr, loadBE(Ity_V128, mkexpr(EA_align16)) );
++ putVReg( vD_addr, load(Ity_V128, mkexpr(EA_align16)) );
+ break;
+
+ default:
+@@ -15567,9 +15565,9 @@ static Bool dis_av_store ( UInt theInstr )
+ assign( idx, binop(Iop_Shl8,
+ binop(Iop_Sub8, mkU8(15), mkexpr(eb)),
+ mkU8(3)) );
+- storeBE( mkexpr(EA),
+- unop(Iop_32to8, unop(Iop_V128to32,
+- binop(Iop_ShrV128, mkexpr(vS), mkexpr(idx)))) );
++ store( mkexpr(EA),
++ unop( Iop_32to8, unop(Iop_V128to32,
++ binop(Iop_ShrV128, mkexpr(vS), mkexpr(idx)))) );
+ break;
+ }
+ case 0x0A7: { // stvehx (Store Vector Half Word Indexed, AV p132)
+@@ -15580,9 +15578,9 @@ static Bool dis_av_store ( UInt theInstr )
+ assign( idx, binop(Iop_Shl8,
+ binop(Iop_Sub8, mkU8(14), mkexpr(eb)),
+ mkU8(3)) );
+- storeBE( mkexpr(addr_aligned),
+- unop(Iop_32to16, unop(Iop_V128to32,
+- binop(Iop_ShrV128, mkexpr(vS), mkexpr(idx)))) );
++ store( mkexpr(addr_aligned),
++ unop( Iop_32to16, unop(Iop_V128to32,
++ binop(Iop_ShrV128, mkexpr(vS), mkexpr(idx)))) );
+ break;
+ }
+ case 0x0C7: { // stvewx (Store Vector Word Indexed, AV p133)
+@@ -15593,20 +15591,20 @@ static Bool dis_av_store ( UInt theInstr )
+ assign( idx, binop(Iop_Shl8,
+ binop(Iop_Sub8, mkU8(12), mkexpr(eb)),
+ mkU8(3)) );
+- storeBE( mkexpr(addr_aligned),
+- unop(Iop_V128to32,
+- binop(Iop_ShrV128, mkexpr(vS), mkexpr(idx))) );
++ store( mkexpr( addr_aligned),
++ unop( Iop_V128to32,
++ binop(Iop_ShrV128, mkexpr(vS), mkexpr(idx))) );
+ break;
+ }
+
+ case 0x0E7: // stvx (Store Vector Indexed, AV p134)
+ DIP("stvx v%d,r%u,r%u\n", vS_addr, rA_addr, rB_addr);
+- storeBE( addr_align( mkexpr(EA), 16 ), mkexpr(vS) );
++ store( addr_align( mkexpr(EA), 16 ), mkexpr(vS) );
+ break;
+
+ case 0x1E7: // stvxl (Store Vector Indexed LRU, AV p135)
+ DIP("stvxl v%d,r%u,r%u\n", vS_addr, rA_addr, rB_addr);
+- storeBE( addr_align( mkexpr(EA), 16 ), mkexpr(vS) );
++ store( addr_align( mkexpr(EA), 16 ), mkexpr(vS) );
+ break;
+
+ default:
+@@ -18535,7 +18533,7 @@ DisResult disInstr_PPC_WRK (
+ /* At least this is simple on PPC32: insns are all 4 bytes long, and
+ 4-aligned. So just fish the whole thing out of memory right now
+ and have done. */
+- theInstr = getUIntBigendianly( (UChar*)(&guest_code[delta]) );
++ theInstr = getUIntPPCendianly( (UChar*)(&guest_code[delta]) );
+
+ if (0) vex_printf("insn: 0x%x\n", theInstr);
+
+@@ -18560,12 +18558,12 @@ DisResult disInstr_PPC_WRK (
+ UInt word2 = mode64 ? 0x78006800 : 0x5400683E;
+ UInt word3 = mode64 ? 0x7800E802 : 0x5400E83E;
+ UInt word4 = mode64 ? 0x78009802 : 0x5400983E;
+- if (getUIntBigendianly(code+ 0) == word1 &&
+- getUIntBigendianly(code+ 4) == word2 &&
+- getUIntBigendianly(code+ 8) == word3 &&
+- getUIntBigendianly(code+12) == word4) {
++ if (getUIntPPCendianly(code+ 0) == word1 &&
++ getUIntPPCendianly(code+ 4) == word2 &&
++ getUIntPPCendianly(code+ 8) == word3 &&
++ getUIntPPCendianly(code+12) == word4) {
+ /* Got a "Special" instruction preamble. Which one is it? */
+- if (getUIntBigendianly(code+16) == 0x7C210B78 /* or 1,1,1 */) {
++ if (getUIntPPCendianly(code+16) == 0x7C210B78 /* or 1,1,1 */) {
+ /* %R3 = client_request ( %R4 ) */
+ DIP("r3 = client_request ( %%r4 )\n");
+ delta += 20;
+@@ -18575,7 +18573,7 @@ DisResult disInstr_PPC_WRK (
+ goto decode_success;
+ }
+ else
+- if (getUIntBigendianly(code+16) == 0x7C421378 /* or 2,2,2 */) {
++ if (getUIntPPCendianly(code+16) == 0x7C421378 /* or 2,2,2 */) {
+ /* %R3 = guest_NRADDR */
+ DIP("r3 = guest_NRADDR\n");
+ delta += 20;
+@@ -18584,7 +18582,7 @@ DisResult disInstr_PPC_WRK (
+ goto decode_success;
+ }
+ else
+- if (getUIntBigendianly(code+16) == 0x7C631B78 /* or 3,3,3 */) {
++ if (getUIntPPCendianly(code+16) == 0x7C631B78 /* or 3,3,3 */) {
+ /* branch-and-link-to-noredir %R11 */
+ DIP("branch-and-link-to-noredir r11\n");
+ delta += 20;
+@@ -18595,7 +18593,7 @@ DisResult disInstr_PPC_WRK (
+ goto decode_success;
+ }
+ else
+- if (getUIntBigendianly(code+16) == 0x7C842378 /* or 4,4,4 */) {
++ if (getUIntPPCendianly(code+16) == 0x7C842378 /* or 4,4,4 */) {
+ /* %R3 = guest_NRADDR_GPR2 */
+ DIP("r3 = guest_NRADDR_GPR2\n");
+ delta += 20;
+@@ -18604,10 +18602,10 @@ DisResult disInstr_PPC_WRK (
+ goto decode_success;
+ }
+ else
+- if (getUIntBigendianly(code+16) == 0x7CA52B78 /* or 5,5,5 */) {
++ if (getUIntPPCendianly(code+16) == 0x7CA52B78 /* or 5,5,5 */) {
+ DIP("IR injection\n");
+
+- vex_inject_ir(irsb, Iend_BE);
++ vex_inject_ir(irsb, IENDIANESS);
+
+ delta += 20;
+ dres.len = 20;
+@@ -18627,7 +18625,7 @@ DisResult disInstr_PPC_WRK (
+ }
+ /* We don't know what it is. Set opc1/opc2 so decode_failure
+ can print the insn following the Special-insn preamble. */
+- theInstr = getUIntBigendianly(code+16);
++ theInstr = getUIntPPCendianly(code+16);
+ opc1 = ifieldOPC(theInstr);
+ opc2 = ifieldOPClo10(theInstr);
+ goto decode_failure;
+@@ -19323,7 +19321,7 @@ DisResult disInstr_PPC_WRK (
+ case 0x32E: case 0x34E: case 0x36E: // tabortdc., tabortwci., tabortdci.
+ case 0x38E: case 0x3AE: case 0x3EE: // tabort., treclaim., trechkpt.
+ if (dis_transactional_memory( theInstr,
+- getUIntBigendianly( (UChar*)(&guest_code[delta + 4])),
++ getUIntPPCendianly( (UChar*)(&guest_code[delta + 4])),
+ abiinfo, &dres,
+ resteerOkFn, callback_opaque))
+ goto decode_success;
+diff --git a/cachegrind/cg_arch.c b/cachegrind/cg_arch.c
+index 0b39c52..170e4cc 100644
+--- a/cachegrind/cg_arch.c
++++ b/cachegrind/cg_arch.c
+@@ -353,7 +353,7 @@ configure_caches(cache_t *I1c, cache_t *D1c, cache_t *LLc,
+ *D1c = (cache_t) { 65536, 2, 64 };
+ *LLc = (cache_t) { 262144, 8, 64 };
+
+-#elif defined(VGA_ppc64)
++#elif defined(VGA_ppc64be) || defined(VGA_ppc64le)
+
+ // Default cache configuration
+ *I1c = (cache_t) { 65536, 2, 64 };
+diff --git a/cachegrind/cg_branchpred.c b/cachegrind/cg_branchpred.c
+index b385f66..9ee5c62 100644
+--- a/cachegrind/cg_branchpred.c
++++ b/cachegrind/cg_branchpred.c
+@@ -44,7 +44,7 @@
+
+ /* How many bits at the bottom of an instruction address are
+ guaranteed to be zero? */
+-#if defined(VGA_ppc32) || defined(VGA_ppc64) \
++#if defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le) \
+ || defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_arm64)
+ # define N_IADDR_LO_ZERO_BITS 2
+ #elif defined(VGA_x86) || defined(VGA_amd64)
+diff --git a/configure.ac b/configure.ac
+index c91ea94..5b65439 100644
+--- a/configure.ac
++++ b/configure.ac
+@@ -163,6 +163,18 @@ AC_MSG_CHECKING([for a supported CPU])
+ # is a 64-bit capable PowerPC, then it must be set to ppc64 and not ppc32.
+ # Ditto for amd64. It is used for more configuration below, but is not used
+ # outside this file.
++#
++# Power PC returns powerpc for Big Endian. This was not changed when Little
++# Endian support was added to the 64-bit architecture. The 64-bit Little
++# Endian systems explicitly state le in the host_cpu. For clarity in the
++# Valgrind code, the ARCH_MAX name will state LE or BE for the endianess of
++# the 64-bit system. Big Endian is the only mode supported on 32-bit Power PC.
++# The abreviation PPC or ppc refers to 32-bit and 64-bit systems with either
++# Endianess. The name PPC64 or ppc64 to 64-bit systems of either Endianess.
++# The names ppc64be or PPC64BE refer to only 64-bit systems that are Big
++# Endian. Similarly, ppc64le or PPC64LE refer to only 64-bit systems that are
++# Little Endian.
++
+ case "${host_cpu}" in
+ i?86)
+ AC_MSG_RESULT([ok (${host_cpu})])
+@@ -175,8 +187,15 @@ case "${host_cpu}" in
+ ;;
+
+ powerpc64)
++ # this only referrs to 64-bit Big Endian
+ AC_MSG_RESULT([ok (${host_cpu})])
+- ARCH_MAX="ppc64"
++ ARCH_MAX="ppc64be"
++ ;;
++
++ powerpc64le)
++ # this only referrs to 64-bit Little Endian
++ AC_MSG_RESULT([ok (${host_cpu})])
++ ARCH_MAX="ppc64le"
+ ;;
+
+ powerpc)
+@@ -378,7 +397,7 @@ esac
+ # does not support building 32 bit programs
+
+ case "$ARCH_MAX-$VGCONF_OS" in
+- amd64-linux|ppc64-linux)
++ amd64-linux|ppc64be-linux)
+ AC_MSG_CHECKING([for 32 bit build support])
+ safe_CFLAGS=$CFLAGS
+ CFLAGS="-m32"
+@@ -496,13 +515,13 @@ case "$ARCH_MAX-$VGCONF_OS" in
+ valt_load_address_sec_inner="0xUNSET"
+ AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
+ ;;
+- ppc64-linux)
++ ppc64be-linux)
+ valt_load_address_sec_norml="0xUNSET"
+ valt_load_address_sec_inner="0xUNSET"
+ if test x$vg_cv_only64bit = xyes; then
+- VGCONF_ARCH_PRI="ppc64"
++ VGCONF_ARCH_PRI="ppc64be"
+ VGCONF_ARCH_SEC=""
+- VGCONF_PLATFORM_PRI_CAPS="PPC64_LINUX"
++ VGCONF_PLATFORM_PRI_CAPS="PPC64BE_LINUX"
+ VGCONF_PLATFORM_SEC_CAPS=""
+ valt_load_address_pri_norml="0x38000000"
+ valt_load_address_pri_inner="0x28000000"
+@@ -514,9 +533,9 @@ case "$ARCH_MAX-$VGCONF_OS" in
+ valt_load_address_pri_norml="0x38000000"
+ valt_load_address_pri_inner="0x28000000"
+ else
+- VGCONF_ARCH_PRI="ppc64"
++ VGCONF_ARCH_PRI="ppc64be"
+ VGCONF_ARCH_SEC="ppc32"
+- VGCONF_PLATFORM_PRI_CAPS="PPC64_LINUX"
++ VGCONF_PLATFORM_PRI_CAPS="PPC64BE_LINUX"
+ VGCONF_PLATFORM_SEC_CAPS="PPC32_LINUX"
+ valt_load_address_pri_norml="0x38000000"
+ valt_load_address_pri_inner="0x28000000"
+@@ -525,6 +544,18 @@ case "$ARCH_MAX-$VGCONF_OS" in
+ fi
+ AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
+ ;;
++ ppc64le-linux)
++ # Little Endian is only supported on PPC64
++ valt_load_address_sec_norml="0xUNSET"
++ valt_load_address_sec_inner="0xUNSET"
++ VGCONF_ARCH_PRI="ppc64le"
++ VGCONF_ARCH_SEC=""
++ VGCONF_PLATFORM_PRI_CAPS="PPC64LE_LINUX"
++ VGCONF_PLATFORM_SEC_CAPS=""
++ valt_load_address_pri_norml="0x38000000"
++ valt_load_address_pri_inner="0x28000000"
++ AC_MSG_RESULT([ok (${ARCH_MAX}-${VGCONF_OS})])
++ ;;
+ # Darwin gets identified as 32-bit even when it supports 64-bit.
+ # (Not sure why, possibly because 'uname' returns "i386"?) Just about
+ # all Macs support both 32-bit and 64-bit, so we just build both. If
+@@ -663,7 +694,8 @@ AM_CONDITIONAL(VGCONF_ARCHS_INCLUDE_PPC32,
+ test x$VGCONF_PLATFORM_PRI_CAPS = xPPC32_LINUX \
+ -o x$VGCONF_PLATFORM_SEC_CAPS = xPPC32_LINUX )
+ AM_CONDITIONAL(VGCONF_ARCHS_INCLUDE_PPC64,
+- test x$VGCONF_PLATFORM_PRI_CAPS = xPPC64_LINUX )
++ test x$VGCONF_PLATFORM_PRI_CAPS = xPPC64BE_LINUX \
++ -o x$VGCONF_PLATFORM_PRI_CAPS = xPPC64LE_LINUX )
+ AM_CONDITIONAL(VGCONF_ARCHS_INCLUDE_ARM,
+ test x$VGCONF_PLATFORM_PRI_CAPS = xARM_LINUX \
+ -o x$VGCONF_PLATFORM_SEC_CAPS = xARM_LINUX )
+@@ -686,8 +718,10 @@ AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_AMD64_LINUX,
+ AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_PPC32_LINUX,
+ test x$VGCONF_PLATFORM_PRI_CAPS = xPPC32_LINUX \
+ -o x$VGCONF_PLATFORM_SEC_CAPS = xPPC32_LINUX)
+-AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_PPC64_LINUX,
+- test x$VGCONF_PLATFORM_PRI_CAPS = xPPC64_LINUX)
++AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_PPC64BE_LINUX,
++ test x$VGCONF_PLATFORM_PRI_CAPS = xPPC64BE_LINUX)
++AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_PPC64LE_LINUX,
++ test x$VGCONF_PLATFORM_PRI_CAPS = xPPC64LE_LINUX)
+ AM_CONDITIONAL(VGCONF_PLATFORMS_INCLUDE_ARM_LINUX,
+ test x$VGCONF_PLATFORM_PRI_CAPS = xARM_LINUX \
+ -o x$VGCONF_PLATFORM_SEC_CAPS = xARM_LINUX)
+@@ -714,7 +748,8 @@ AM_CONDITIONAL(VGCONF_OS_IS_LINUX,
+ test x$VGCONF_PLATFORM_PRI_CAPS = xX86_LINUX \
+ -o x$VGCONF_PLATFORM_PRI_CAPS = xAMD64_LINUX \
+ -o x$VGCONF_PLATFORM_PRI_CAPS = xPPC32_LINUX \
+- -o x$VGCONF_PLATFORM_PRI_CAPS = xPPC64_LINUX \
++ -o x$VGCONF_PLATFORM_PRI_CAPS = xPPC64BE_LINUX \
++ -o x$VGCONF_PLATFORM_PRI_CAPS = xPPC64LE_LINUX \
+ -o x$VGCONF_PLATFORM_PRI_CAPS = xARM_LINUX \
+ -o x$VGCONF_PLATFORM_PRI_CAPS = xARM64_LINUX \
+ -o x$VGCONF_PLATFORM_PRI_CAPS = xS390X_LINUX \
+diff --git a/coregrind/launcher-darwin.c b/coregrind/launcher-darwin.c
+index 8e3d63e..1f99026 100644
+--- a/coregrind/launcher-darwin.c
++++ b/coregrind/launcher-darwin.c
+@@ -59,11 +59,11 @@ static struct {
+ const char *apple_name; // e.g. x86_64
+ const char *valgrind_name; // e.g. amd64
+ } valid_archs[] = {
+- { CPU_TYPE_X86, "i386", "x86" },
+- { CPU_TYPE_X86_64, "x86_64", "amd64" },
+- { CPU_TYPE_ARM, "arm", "arm" },
+- { CPU_TYPE_POWERPC, "ppc", "ppc32" },
+- { CPU_TYPE_POWERPC64, "ppc64", "ppc64" },
++ { CPU_TYPE_X86, "i386", "x86" },
++ { CPU_TYPE_X86_64, "x86_64", "amd64" },
++ { CPU_TYPE_ARM, "arm", "arm" },
++ { CPU_TYPE_POWERPC, "ppc", "ppc32" },
++ { CPU_TYPE_POWERPC64BE, "ppc64be", "ppc64be" },
+ };
+ static int valid_archs_count = sizeof(valid_archs)/sizeof(valid_archs[0]);
+
+diff --git a/coregrind/launcher-linux.c b/coregrind/launcher-linux.c
+index 83035ea..38e4857 100644
+--- a/coregrind/launcher-linux.c
++++ b/coregrind/launcher-linux.c
+@@ -236,7 +236,7 @@ static const char *select_platform(const char *clientname)
+ if (ehdr->e_machine == EM_PPC64 &&
+ (ehdr->e_ident[EI_OSABI] == ELFOSABI_SYSV ||
+ ehdr->e_ident[EI_OSABI] == ELFOSABI_LINUX)) {
+- platform = "ppc64-linux";
++ platform = "ppc64be-linux";
+ }
+ else
+ if (ehdr->e_machine == EM_S390 &&
+@@ -320,7 +320,7 @@ int main(int argc, char** argv, char** envp)
+ if ((0==strcmp(VG_PLATFORM,"x86-linux")) ||
+ (0==strcmp(VG_PLATFORM,"amd64-linux")) ||
+ (0==strcmp(VG_PLATFORM,"ppc32-linux")) ||
+- (0==strcmp(VG_PLATFORM,"ppc64-linux")) ||
++ (0==strcmp(VG_PLATFORM,"ppc64be-linux")) ||
+ (0==strcmp(VG_PLATFORM,"arm-linux")) ||
+ (0==strcmp(VG_PLATFORM,"arm64-linux")) ||
+ (0==strcmp(VG_PLATFORM,"s390x-linux")) ||
+diff --git a/coregrind/m_aspacemgr/aspacemgr-common.c b/coregrind/m_aspacemgr/aspacemgr-common.c
+index b8d694d..903f924 100644
+--- a/coregrind/m_aspacemgr/aspacemgr-common.c
++++ b/coregrind/m_aspacemgr/aspacemgr-common.c
+@@ -162,7 +162,8 @@ SysRes VG_(am_do_mmap_NO_NOTIFY)( Addr start, SizeT length, UInt prot,
+ aspacem_assert((offset % 4096) == 0);
+ res = VG_(do_syscall6)(__NR_mmap2, (UWord)start, length,
+ prot, flags, fd, offset / 4096);
+-# elif defined(VGP_amd64_linux) || defined(VGP_ppc64_linux) \
++# elif defined(VGP_amd64_linux) \
++ || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \
+ || defined(VGP_s390x_linux) || defined(VGP_mips32_linux) \
+ || defined(VGP_mips64_linux) || defined(VGP_arm64_linux)
+ res = VG_(do_syscall6)(__NR_mmap, (UWord)start, length,
+diff --git a/coregrind/m_cache.c b/coregrind/m_cache.c
+index 0321db4..d208a53 100644
+--- a/coregrind/m_cache.c
++++ b/coregrind/m_cache.c
+@@ -538,7 +538,8 @@ get_cache_info(VexArchInfo *vai)
+ return ret == 0 ? True : False;
+ }
+
+-#elif defined(VGA_arm) || defined(VGA_ppc32) || defined(VGA_ppc64) || \
++#elif defined(VGA_arm) || defined(VGA_ppc32) || \
++ defined(VGA_ppc64be) || defined(VGA_ppc64le) || \
+ defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_arm64)
+
+ static Bool
+diff --git a/coregrind/m_coredump/coredump-elf.c b/coregrind/m_coredump/coredump-elf.c
+index fcc16ec..08ddddd 100644
+--- a/coregrind/m_coredump/coredump-elf.c
++++ b/coregrind/m_coredump/coredump-elf.c
+@@ -322,7 +322,7 @@ static void fill_prstatus(const ThreadState *tst,
+ regs->dsisr = 0;
+ regs->result = 0;
+
+-#elif defined(VGP_ppc64_linux)
++#elif defined(VGP_ppc64be_linux)
+ # define DO(n) regs->gpr[n] = arch->vex.guest_GPR##n
+ DO(0); DO(1); DO(2); DO(3); DO(4); DO(5); DO(6); DO(7);
+ DO(8); DO(9); DO(10); DO(11); DO(12); DO(13); DO(14); DO(15);
+@@ -458,7 +458,7 @@ static void fill_fpu(const ThreadState *tst, vki_elf_fpregset_t *fpu)
+ DO(24); DO(25); DO(26); DO(27); DO(28); DO(29); DO(30); DO(31);
+ # undef DO
+
+-#elif defined(VGP_ppc64_linux)
++#elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
+ /* The guest state has the FPR fields declared as ULongs, so need
+ to fish out the values without converting them.
+ NOTE: The 32 FP registers map to the first 32 VSX registers.*/
+diff --git a/coregrind/m_debugger.c b/coregrind/m_debugger.c
+index 3a61361..4af8f18 100644
+--- a/coregrind/m_debugger.c
++++ b/coregrind/m_debugger.c
+@@ -152,7 +152,7 @@ static Int ptrace_setregs(Int pid, VexGuestArchState* vex)
+ (void*)LibVEX_GuestPPC32_get_XER(vex));
+ return rc;
+
+-#elif defined(VGP_ppc64_linux)
++#elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
+ Int rc = 0;
+ /* FRJ: copied nearly verbatim from the ppc32 case. I compared the
+ vki-ppc64-linux.h with its ppc32 counterpart and saw no
+diff --git a/coregrind/m_debuginfo/d3basics.c b/coregrind/m_debuginfo/d3basics.c
+index 3999533..02e8dad 100644
+--- a/coregrind/m_debuginfo/d3basics.c
++++ b/coregrind/m_debuginfo/d3basics.c
+@@ -406,7 +406,7 @@ static Bool get_Dwarf_Reg( /*OUT*/Addr* a, Word regno, RegSummary* regs )
+ if (regno == 7/*RSP*/) { *a = regs->sp; return True; }
+ # elif defined(VGP_ppc32_linux)
+ if (regno == 1/*SP*/) { *a = regs->sp; return True; }
+-# elif defined(VGP_ppc64_linux)
++# elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
+ if (regno == 1/*SP*/) { *a = regs->sp; return True; }
+ # elif defined(VGP_arm_linux)
+ if (regno == 13) { *a = regs->sp; return True; }
+@@ -863,7 +863,8 @@ GXResult ML_(evaluate_Dwarf3_Expr) ( UChar* expr, UWord exprszB,
+ if (!regs)
+ FAIL("evaluate_Dwarf3_Expr: "
+ "DW_OP_call_frame_cfa but no reg info");
+-#if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux)
++#if defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux) \
++ || defined(VGP_ppc64le_linux)
+ /* Valgrind on ppc32/ppc64 currently doesn't use unwind info. */
+ uw1 = ML_(read_Addr)((UChar*)regs->sp);
+ #else
+diff --git a/coregrind/m_debuginfo/debuginfo.c b/coregrind/m_debuginfo/debuginfo.c
+index 13d27f0..90b6f0c 100644
+--- a/coregrind/m_debuginfo/debuginfo.c
++++ b/coregrind/m_debuginfo/debuginfo.c
+@@ -833,8 +833,8 @@ ULong VG_(di_notify_mmap)( Addr a, Bool allow_SkFileV, Int use_fd )
+ || defined(VGA_mips64)
+ is_rx_map = seg->hasR && seg->hasX;
+ is_rw_map = seg->hasR && seg->hasW;
+-# elif defined(VGA_amd64) || defined(VGA_ppc64) || defined(VGA_arm) \
+- || defined(VGA_arm64)
++# elif defined(VGA_amd64) || defined(VGA_ppc64be) || defined(VGA_ppc64le) \
++ || defined(VGA_arm) || defined(VGA_arm64)
+ is_rx_map = seg->hasR && seg->hasX && !seg->hasW;
+ is_rw_map = seg->hasR && seg->hasW && !seg->hasX;
+ # elif defined(VGP_s390x_linux)
+@@ -1675,7 +1675,7 @@ Bool get_sym_name ( Bool do_cxx_demangling, Bool do_z_demangling,
+ return True;
+ }
+
+-/* ppc64-linux only: find the TOC pointer (R2 value) that should be in
++/* ppc64be-linux only: find the TOC pointer (R2 value) that should be in
+ force at the entry point address of the function containing
+ guest_code_addr. Returns 0 if not known. */
+ Addr VG_(get_tocptr) ( Addr guest_code_addr )
+@@ -2370,7 +2370,8 @@ UWord evalCfiExpr ( XArray* exprs, Int ix,
+ case Creg_IA_SP: return eec->uregs->sp;
+ case Creg_IA_BP: return eec->uregs->fp;
+ case Creg_MIPS_RA: return eec->uregs->ra;
+-# elif defined(VGA_ppc32) || defined(VGA_ppc64)
++# elif defined(VGA_ppc32) || defined(VGA_ppc64be) \
++ || defined(VGA_ppc64le)
+ # elif defined(VGP_arm64_linux)
+ case Creg_ARM64_X30: return eec->uregs->x30;
+ # else
+@@ -2620,7 +2621,7 @@ static Addr compute_cfa ( D3UnwindRegs* uregs,
+ case CFIC_IA_BPREL:
+ cfa = cfsi_m->cfa_off + uregs->fp;
+ break;
+-# elif defined(VGA_ppc32) || defined(VGA_ppc64)
++# elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le)
+ # elif defined(VGP_arm64_linux)
+ case CFIC_ARM64_SPREL:
+ cfa = cfsi_m->cfa_off + uregs->sp;
+@@ -2728,7 +2729,7 @@ Bool VG_(use_CF_info) ( /*MOD*/D3UnwindRegs* uregsHere,
+ ipHere = uregsHere->ia;
+ # elif defined(VGA_mips32) || defined(VGA_mips64)
+ ipHere = uregsHere->pc;
+-# elif defined(VGA_ppc32) || defined(VGA_ppc64)
++# elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le)
+ # elif defined(VGP_arm64_linux)
+ ipHere = uregsHere->pc;
+ # else
+@@ -2810,7 +2811,7 @@ Bool VG_(use_CF_info) ( /*MOD*/D3UnwindRegs* uregsHere,
+ COMPUTE(uregsPrev.pc, uregsHere->pc, cfsi_m->ra_how, cfsi_m->ra_off);
+ COMPUTE(uregsPrev.sp, uregsHere->sp, cfsi_m->sp_how, cfsi_m->sp_off);
+ COMPUTE(uregsPrev.fp, uregsHere->fp, cfsi_m->fp_how, cfsi_m->fp_off);
+-# elif defined(VGA_ppc32) || defined(VGA_ppc64)
++# elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le)
+ # elif defined(VGP_arm64_linux)
+ COMPUTE(uregsPrev.pc, uregsHere->pc, cfsi_m->ra_how, cfsi_m->ra_off);
+ COMPUTE(uregsPrev.sp, uregsHere->sp, cfsi_m->sp_how, cfsi_m->sp_off);
+diff --git a/coregrind/m_debuginfo/priv_storage.h b/coregrind/m_debuginfo/priv_storage.h
+index 000d5f1..f002878 100644
+--- a/coregrind/m_debuginfo/priv_storage.h
++++ b/coregrind/m_debuginfo/priv_storage.h
+@@ -285,7 +285,7 @@ typedef
+ Int x29_off;
+ }
+ DiCfSI_m;
+-#elif defined(VGA_ppc32) || defined(VGA_ppc64)
++#elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le)
+ /* Just have a struct with the common fields in, so that code that
+ processes the common fields doesn't have to be ifdef'd against
+ VGP_/VGA_ symbols. These are not used in any way on ppc32/64-linux
+diff --git a/coregrind/m_debuginfo/readdwarf.c b/coregrind/m_debuginfo/readdwarf.c
+index c6e9ebe..158f614 100644
+--- a/coregrind/m_debuginfo/readdwarf.c
++++ b/coregrind/m_debuginfo/readdwarf.c
+@@ -1833,7 +1833,7 @@ void ML_(read_debuginfo_dwarf1) (
+ # define FP_REG 1
+ # define SP_REG 1
+ # define RA_REG_DEFAULT 65
+-#elif defined(VGP_ppc64_linux)
++#elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
+ # define FP_REG 1
+ # define SP_REG 1
+ # define RA_REG_DEFAULT 65
+@@ -1873,8 +1873,9 @@ void ML_(read_debuginfo_dwarf1) (
+ arm-linux (320) seems ludicrously high, but the ARM IHI 0040A page
+ 7 (DWARF for the ARM Architecture) specifies that values up to 320
+ might exist, for Neon/VFP-v3. */
+-#if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) \
+- || defined(VGP_mips32_linux) || defined(VGP_mips64_linux)
++#if defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux) \
++ || defined(VGP_ppc64le_linux) || defined(VGP_mips32_linux) \
++ || defined(VGP_mips64_linux)
+ # define N_CFI_REGS 72
+ #elif defined(VGP_arm_linux)
+ # define N_CFI_REGS 320
+@@ -2491,7 +2492,7 @@ static Bool summarise_context(/*OUT*/Addr* base,
+
+ return True;
+
+-# elif defined(VGA_ppc32) || defined(VGA_ppc64)
++# elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le)
+ /* These don't use CFI based unwinding (is that really true?) */
+
+ # else
+@@ -2585,7 +2586,8 @@ static Int copy_convert_CfiExpr_tree ( XArray* dstxa,
+ return ML_(CfiExpr_CfiReg)( dstxa, Creg_IA_IP );
+ # elif defined(VGA_arm64)
+ I_die_here;
+-# elif defined(VGA_ppc32) || defined(VGA_ppc64)
++# elif defined(VGA_ppc32) || defined(VGA_ppc64be) \
++ || defined(VGA_ppc64le)
+ # else
+ # error "Unknown arch"
+ # endif
+@@ -3756,7 +3758,8 @@ void ML_(read_callframe_info_dwarf3)
+ if (!is_ehframe)
+ vg_assert(frame_avma == 0);
+
+-# if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux)
++# if defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux) \
++ || defined(VGP_ppc64le_linux)
+ /* These targets don't use CFI-based stack unwinding. */
+ return;
+ # endif
+diff --git a/coregrind/m_debuginfo/readelf.c b/coregrind/m_debuginfo/readelf.c
+index c57ac22..732ca0a 100644
+--- a/coregrind/m_debuginfo/readelf.c
++++ b/coregrind/m_debuginfo/readelf.c
+@@ -204,19 +204,19 @@ void show_raw_elf_symbol ( DiImage* strtab_img,
+ .data, size of .data + size of .bss). I don't know if this is
+ really correct/justifiable, or not.
+
+- For ppc64-linux it's more complex. If the symbol is seen to be in
++ For ppc64be-linux it's more complex. If the symbol is seen to be in
+ the .opd section, it is taken to be a function descriptor, and so
+ a dereference is attempted, in order to get hold of the real entry
+ point address. Also as part of the dereference, there is an attempt
+ to calculate the TOC pointer (R2 value) associated with the symbol.
+
+- To support the ppc64-linux pre-"dotless" ABI (prior to gcc 4.0.0),
++ To support the ppc64be-linux pre-"dotless" ABI (prior to gcc 4.0.0),
+ if the symbol is seen to be outside the .opd section and its name
+ starts with a dot, an .opd deference is not attempted, and no TOC
+ pointer is calculated, but the the leading dot is removed from the
+ name.
+
+- As a result, on ppc64-linux, the caller of this function may have
++ As a result, on ppc64be-linux, the caller of this function may have
+ to piece together the real size, address, name of the symbol from
+ multiple calls to this function. Ugly and confusing.
+ */
+@@ -229,22 +229,22 @@ Bool get_elf_symbol_info (
+ DiSlice* escn_strtab, /* holds the name */
+ Addr sym_svma, /* address as stated in the object file */
+ Bool symtab_in_debug, /* symbol table is in the debug file */
+- DiSlice* escn_opd, /* the .opd (ppc64-linux only) */
++ DiSlice* escn_opd, /* the .opd (ppc64be-linux only) */
+ PtrdiffT opd_bias, /* for biasing AVMAs found in .opd */
+ /* OUTPUTS */
+ DiOffT* sym_name_out_ioff, /* name (in strtab) we should record */
+ Addr* sym_avma_out, /* addr we should record */
+ Int* sym_size_out, /* symbol size */
+- Addr* sym_tocptr_out, /* ppc64-linux only: R2 value to be
++ Addr* sym_tocptr_out, /* ppc64be-linux only: R2 value to be
+ used on entry */
+- Bool* from_opd_out, /* ppc64-linux only: did we deref an
++ Bool* from_opd_out, /* ppc64be-linux only: did we deref an
+ .opd entry? */
+ Bool* is_text_out, /* is this a text symbol? */
+ Bool* is_ifunc /* is this a STT_GNU_IFUNC function ?*/
+ )
+ {
+ Bool plausible;
+-# if defined(VGP_ppc64_linux)
++# if defined(VGP_ppc64be_linux)
+ Bool is_in_opd;
+ # endif
+ Bool in_text, in_data, in_sdata, in_rodata, in_bss, in_sbss;
+@@ -374,9 +374,9 @@ Bool get_elf_symbol_info (
+ }
+ # endif
+
+-# if defined(VGP_ppc64_linux)
++# if defined(VGP_ppc64be_linux)
+ /* Allow STT_NOTYPE in the very special case where we're running on
+- ppc64-linux and the symbol is one which the .opd-chasing hack
++ ppc64be-linux and the symbol is one which the .opd-chasing hack
+ below will chase. */
+ if (!plausible
+ && *is_text_out
+@@ -473,7 +473,7 @@ Bool get_elf_symbol_info (
+ return False;
+ }
+
+- /* ppc64-linux nasty hack: if the symbol is in an .opd section,
++ /* ppc64be-linux nasty hack: if the symbol is in an .opd section,
+ then really what we have is the address of a function
+ descriptor. So use the first word of that as the function's
+ text.
+@@ -481,7 +481,8 @@ Bool get_elf_symbol_info (
+ See thread starting at
+ http://gcc.gnu.org/ml/gcc-patches/2004-08/msg00557.html
+ */
+-# if defined(VGP_ppc64_linux)
++# if defined(VGP_ppc64be_linux)
++ /* Host and guest may have different Endianess, used by BE only */
+ is_in_opd = False;
+ # endif
+
+@@ -489,7 +490,7 @@ Bool get_elf_symbol_info (
+ && di->opd_size > 0
+ && *sym_avma_out >= di->opd_avma
+ && *sym_avma_out < di->opd_avma + di->opd_size) {
+-# if !defined(VGP_ppc64_linux)
++# if !defined(VGP_ppc64be_linux)
+ if (TRACE_SYMTAB_ENABLED) {
+ HChar* sym_name = ML_(img_strdup)(escn_strtab->img,
+ "di.gesi.6", sym_name_ioff);
+@@ -584,7 +585,7 @@ Bool get_elf_symbol_info (
+
+ /* Here's yet another ppc64-linux hack. Get rid of leading dot if
+ the symbol is outside .opd. */
+-# if defined(VGP_ppc64_linux)
++# if defined(VGP_ppc64be_linux)
+ if (di->opd_size > 0
+ && !is_in_opd
+ && *sym_name_out_ioff != DiOffT_INVALID
+@@ -668,7 +669,7 @@ Bool get_elf_symbol_info (
+ }
+ }
+
+-# if defined(VGP_ppc64_linux)
++# if defined(VGP_ppc64be_linux)
+ /* It's crucial that we never add symbol addresses in the .opd
+ section. This would completely mess up function redirection and
+ intercepting. This assert ensures that any symbols that make it
+@@ -692,7 +693,7 @@ void read_elf_symtab__normal(
+ struct _DebugInfo* di, const HChar* tab_name,
+ DiSlice* escn_symtab,
+ DiSlice* escn_strtab,
+- DiSlice* escn_opd, /* ppc64-linux only */
++ DiSlice* escn_opd, /* ppc64be-linux only */
+ Bool symtab_in_debug
+ )
+ {
+@@ -768,7 +769,7 @@ void read_elf_symtab__normal(
+
+
+ /* Read an ELF symbol table (normal or dynamic). This one is for
+- ppc64-linux, which requires special treatment. */
++ ppc64be-linux, which requires special treatment. */
+
+ typedef
+ struct {
+@@ -806,7 +807,7 @@ static Word cmp_TempSymKey ( TempSymKey* key1, TempSym* elem2 )
+
+ static
+ __attribute__((unused)) /* not referred to on all targets */
+-void read_elf_symtab__ppc64_linux(
++void read_elf_symtab__ppc64be_linux(
+ struct _DebugInfo* di, const HChar* tab_name,
+ DiSlice* escn_symtab,
+ DiSlice* escn_strtab,
+@@ -830,7 +831,7 @@ void read_elf_symtab__ppc64_linux(
+ return;
+ }
+
+- TRACE_SYMTAB("\n--- Reading (ELF, ppc64-linux) %s (%lld entries) ---\n",
++ TRACE_SYMTAB("\n--- Reading (ELF, ppc64be-linux) %s (%lld entries) ---\n",
+ tab_name, escn_symtab->szB/sizeof(ElfXX_Sym) );
+
+ oset = VG_(OSetGen_Create)( offsetof(TempSym,key),
+@@ -2116,7 +2117,7 @@ Bool ML_(read_elf_debug_info) ( struct _DebugInfo* di )
+ BAD(".plt");
+ }
+ }
+-# elif defined(VGP_ppc64_linux)
++# elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
+ /* Accept .plt where mapped as rw (data), or unmapped */
+ if (0 == VG_(strcmp)(name, ".plt")) {
+ if (inrw && !di->plt_present) {
+@@ -2229,7 +2230,7 @@ Bool ML_(read_elf_debug_info) ( struct _DebugInfo* di )
+ DiSlice dwarf1d_escn = DiSlice_INVALID; // .debug (dwarf1)
+ DiSlice dwarf1l_escn = DiSlice_INVALID; // .line (dwarf1)
+ DiSlice opd_escn = DiSlice_INVALID; // .opd (dwarf2,
+- // ppc64-linux)
++ // ppc64be-linux)
+ DiSlice ehframe_escn[N_EHFRAME_SECTS]; // .eh_frame (dwarf2)
+
+ for (i = 0; i < N_EHFRAME_SECTS; i++)
+@@ -2733,8 +2734,8 @@ Bool ML_(read_elf_debug_info) ( struct _DebugInfo* di )
+ void (*read_elf_symtab)(struct _DebugInfo*, const HChar*,
+ DiSlice*, DiSlice*, DiSlice*, Bool);
+ Bool symtab_in_debug;
+-# if defined(VGP_ppc64_linux)
+- read_elf_symtab = read_elf_symtab__ppc64_linux;
++# if defined(VGP_ppc64be_linux)
++ read_elf_symtab = read_elf_symtab__ppc64be_linux;
+ # else
+ read_elf_symtab = read_elf_symtab__normal;
+ # endif
+@@ -2776,7 +2777,7 @@ Bool ML_(read_elf_debug_info) ( struct _DebugInfo* di )
+ seems OK though. Also skip on Android. */
+ # if !defined(VGP_amd64_linux) \
+ && !defined(VGP_s390x_linux) \
+- && !defined(VGP_ppc64_linux) \
++ && !defined(VGP_ppc64be_linux) \
+ && !defined(VGPV_arm_linux_android) \
+ && !defined(VGPV_x86_linux_android) \
+ && !defined(VGP_mips64_linux)
+diff --git a/coregrind/m_debuginfo/readmacho.c b/coregrind/m_debuginfo/readmacho.c
+index d20a464..9926237 100644
+--- a/coregrind/m_debuginfo/readmacho.c
++++ b/coregrind/m_debuginfo/readmacho.c
+@@ -197,8 +197,8 @@ static DiSlice map_image_aboard ( DebugInfo* di, /* only for err msgs */
+ f++, arch_be_ioff += sizeof(struct fat_arch)) {
+ # if defined(VGA_ppc)
+ Int cputype = CPU_TYPE_POWERPC;
+-# elif defined(VGA_ppc64)
+- Int cputype = CPU_TYPE_POWERPC64;
++# elif defined(VGA_ppc64be)
++ Int cputype = CPU_TYPE_POWERPC64BE;
+ # elif defined(VGA_x86)
+ Int cputype = CPU_TYPE_X86;
+ # elif defined(VGA_amd64)
+diff --git a/coregrind/m_debuginfo/storage.c b/coregrind/m_debuginfo/storage.c
+index 78bcdf6..c6a17ca 100644
+--- a/coregrind/m_debuginfo/storage.c
++++ b/coregrind/m_debuginfo/storage.c
+@@ -199,7 +199,7 @@ void ML_(ppDiCfSI) ( XArray* /* of CfiExpr */ exprs,
+ SHOW_HOW(si_m->r11_how, si_m->r11_off);
+ VG_(printf)(" R7=");
+ SHOW_HOW(si_m->r7_how, si_m->r7_off);
+-# elif defined(VGA_ppc32) || defined(VGA_ppc64)
++# elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le)
+ # elif defined(VGA_s390x) || defined(VGA_mips32) || defined(VGA_mips64)
+ VG_(printf)(" SP=");
+ SHOW_HOW(si_m->sp_how, si_m->sp_off);
+diff --git a/coregrind/m_debuglog.c b/coregrind/m_debuglog.c
+index 2657c3a..8a22ca2 100644
+--- a/coregrind/m_debuglog.c
++++ b/coregrind/m_debuglog.c
+@@ -189,7 +189,7 @@ static UInt local_sys_getpid ( void )
+ return __res;
+ }
+
+-#elif defined(VGP_ppc64_linux)
++#elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
+
+ static UInt local_sys_write_stderr ( const HChar* buf, Int n )
+ {
+diff --git a/coregrind/m_dispatch/dispatch-ppc64-linux.S b/coregrind/m_dispatch/dispatch-ppc64-linux.S
+index ac1c4cb..35cefdf 100644
+--- a/coregrind/m_dispatch/dispatch-ppc64-linux.S
++++ b/coregrind/m_dispatch/dispatch-ppc64-linux.S
+@@ -28,7 +28,7 @@
+ The GNU General Public License is contained in the file COPYING.
+ */
+
+-#if defined(VGP_ppc64_linux)
++#if defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
+
+ #include "pub_core_basics_asm.h"
+ #include "pub_core_dispatch_asm.h"
+@@ -193,7 +193,7 @@ VG_(disp_run_translations):
+ /* 88(sp) used later to load fpscr with zero */
+ /* 48:87(sp) free */
+
+- /* Linkage Area (reserved)
++ /* Linkage Area (reserved) BE ABI
+ 40(sp) : TOC
+ 32(sp) : link editor doubleword
+ 24(sp) : compiler doubleword
+@@ -530,7 +530,7 @@ VG_(disp_cp_evcheck_fail):
+ /* Let the linker know we don't need an executable stack */
+ .section .note.GNU-stack,"", at progbits
+
+-#endif // defined(VGP_ppc64_linux)
++#endif // defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
+
+ /*--------------------------------------------------------------------*/
+ /*--- end ---*/
+diff --git a/coregrind/m_gdbserver/target.c b/coregrind/m_gdbserver/target.c
+index 4c4c1b5..2fde954 100644
+--- a/coregrind/m_gdbserver/target.c
++++ b/coregrind/m_gdbserver/target.c
+@@ -657,7 +657,7 @@ void valgrind_initialize_target(void)
+ arm64_init_architecture(&the_low_target);
+ #elif defined(VGA_ppc32)
+ ppc32_init_architecture(&the_low_target);
+-#elif defined(VGA_ppc64)
++#elif defined(VGA_ppc64be) || defined(VGA_ppc64le)
+ ppc64_init_architecture(&the_low_target);
+ #elif defined(VGA_s390x)
+ s390x_init_architecture(&the_low_target);
+diff --git a/coregrind/m_initimg/initimg-linux.c b/coregrind/m_initimg/initimg-linux.c
+index 54efdea..b4c6d92 100644
+--- a/coregrind/m_initimg/initimg-linux.c
++++ b/coregrind/m_initimg/initimg-linux.c
+@@ -366,7 +366,7 @@ struct auxv *find_auxv(UWord* sp)
+ sp++;
+ sp++;
+
+-#if defined(VGA_ppc32) || defined(VGA_ppc64)
++#if defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le)
+ # if defined AT_IGNOREPPC
+ while (*sp == AT_IGNOREPPC) // skip AT_IGNOREPPC entries
+ sp += 2;
+@@ -457,7 +457,8 @@ Addr setup_client_stack( void* init_sp,
+ auxsize += sizeof(*cauxv);
+ }
+
+-# if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux)
++# if defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux) \
++ || defined(VGP_ppc64le_linux)
+ auxsize += 2 * sizeof(*cauxv);
+ # endif
+
+@@ -614,7 +615,8 @@ Addr setup_client_stack( void* init_sp,
+ // We do not take ULong* (as ULong 8 bytes on a 32 bits),
+ // => we take UWord*
+
+-# if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux)
++# if defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux) \
++ || defined(VGP_ppc64le_linux)
+ auxv[0].a_type = AT_IGNOREPPC;
+ auxv[0].u.a_val = AT_IGNOREPPC;
+ auxv[1].a_type = AT_IGNOREPPC;
+@@ -707,7 +709,7 @@ Addr setup_client_stack( void* init_sp,
+ "PPC32 icache line size %u (type %u)\n",
+ (UInt)auxv->u.a_val, (UInt)auxv->a_type );
+ }
+-# elif defined(VGP_ppc64_linux)
++# elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
+ /* acquire cache info */
+ if (auxv->u.a_val > 0) {
+ VG_(machine_ppc64_set_clszB)( auxv->u.a_val );
+@@ -718,7 +720,8 @@ Addr setup_client_stack( void* init_sp,
+ # endif
+ break;
+
+-# if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux)
++# if defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux) \
++ || defined(VGP_ppc64le_linux)
+ case AT_IGNOREPPC:
+ break;
+ # endif
+@@ -738,7 +741,8 @@ Addr setup_client_stack( void* init_sp,
+ auxv->a_type = AT_IGNORE;
+ break;
+
+-# if !defined(VGP_ppc32_linux) && !defined(VGP_ppc64_linux)
++# if !defined(VGP_ppc32_linux) && !defined(VGP_ppc64be_linux) \
++ && !defined(VGP_ppc64le)
+ case AT_SYSINFO_EHDR: {
+ /* Trash this, because we don't reproduce it */
+ const NSegment* ehdrseg = VG_(am_find_nsegment)((Addr)auxv->u.a_ptr);
+@@ -1024,7 +1028,7 @@ void VG_(ii_finalise_image)( IIFinaliseImageInfo iifii )
+ arch->vex.guest_GPR1 = iifii.initial_client_SP;
+ arch->vex.guest_CIA = iifii.initial_client_IP;
+
+-# elif defined(VGP_ppc64_linux)
++# elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
+ vg_assert(0 == sizeof(VexGuestPPC64State) % 16);
+
+ /* Zero out the initial state, and set up the simulated FPU in a
+diff --git a/coregrind/m_libcassert.c b/coregrind/m_libcassert.c
+index f8a957b..5e77f9f 100644
+--- a/coregrind/m_libcassert.c
++++ b/coregrind/m_libcassert.c
+@@ -98,7 +98,7 @@
+ (srP)->r_sp = (ULong)r1; \
+ (srP)->misc.PPC32.r_lr = lr; \
+ }
+-#elif defined(VGP_ppc64_linux)
++#elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
+ # define GET_STARTREGS(srP) \
+ { ULong cia, r1, lr; \
+ __asm__ __volatile__( \
+diff --git a/coregrind/m_libcfile.c b/coregrind/m_libcfile.c
+index 0688bbb..9ff6b61 100644
+--- a/coregrind/m_libcfile.c
++++ b/coregrind/m_libcfile.c
+@@ -677,8 +677,8 @@ SysRes VG_(pread) ( Int fd, void* buf, Int count, OffT offset )
+ res = VG_(do_syscall6)(__NR_pread64, fd, (UWord)buf, count,
+ 0, 0, offset);
+ return res;
+-# elif defined(VGP_amd64_linux) \
+- || defined(VGP_ppc64_linux) || defined(VGP_s390x_linux) \
++# elif defined(VGP_amd64_linux) || defined(VGP_s390x_linux) \
++ || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \
+ || defined(VGP_mips64_linux) \
+ || defined(VGP_arm64_linux)
+ res = VG_(do_syscall4)(__NR_pread64, fd, (UWord)buf, count, offset);
+@@ -923,7 +923,8 @@ static Int parse_inet_addr_and_port ( const HChar* str, UInt* ip_addr, UShort* p
+ Int VG_(socket) ( Int domain, Int type, Int protocol )
+ {
+ # if defined(VGP_x86_linux) || defined(VGP_ppc32_linux) \
+- || defined(VGP_ppc64_linux) || defined(VGP_s390x_linux)
++ || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \
++ || defined(VGP_s390x_linux)
+ SysRes res;
+ UWord args[3];
+ args[0] = domain;
+@@ -963,7 +964,8 @@ static
+ Int my_connect ( Int sockfd, struct vki_sockaddr_in* serv_addr, Int addrlen )
+ {
+ # if defined(VGP_x86_linux) || defined(VGP_ppc32_linux) \
+- || defined(VGP_ppc64_linux) || defined(VGP_s390x_linux)
++ || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \
++ || defined(VGP_s390x_linux)
+ SysRes res;
+ UWord args[3];
+ args[0] = sockfd;
+@@ -1002,7 +1004,8 @@ Int VG_(write_socket)( Int sd, const void *msg, Int count )
+ SIGPIPE */
+
+ # if defined(VGP_x86_linux) || defined(VGP_ppc32_linux) \
+- || defined(VGP_ppc64_linux) || defined(VGP_s390x_linux)
++ || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \
++ || defined(VGP_s390x_linux)
+ SysRes res;
+ UWord args[4];
+ args[0] = sd;
+@@ -1033,7 +1036,8 @@ Int VG_(write_socket)( Int sd, const void *msg, Int count )
+ Int VG_(getsockname) ( Int sd, struct vki_sockaddr *name, Int *namelen)
+ {
+ # if defined(VGP_x86_linux) || defined(VGP_ppc32_linux) \
+- || defined(VGP_ppc64_linux) || defined(VGP_s390x_linux) \
++ || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \
++ || defined(VGP_s390x_linux) \
+ || defined(VGP_mips32_linux)
+ SysRes res;
+ UWord args[3];
+@@ -1064,7 +1068,8 @@ Int VG_(getsockname) ( Int sd, struct vki_sockaddr *name, Int *namelen)
+ Int VG_(getpeername) ( Int sd, struct vki_sockaddr *name, Int *namelen)
+ {
+ # if defined(VGP_x86_linux) || defined(VGP_ppc32_linux) \
+- || defined(VGP_ppc64_linux) || defined(VGP_s390x_linux) \
++ || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \
++ || defined(VGP_s390x_linux) \
+ || defined(VGP_mips32_linux)
+ SysRes res;
+ UWord args[3];
+@@ -1096,7 +1101,8 @@ Int VG_(getsockopt) ( Int sd, Int level, Int optname, void *optval,
+ Int *optlen)
+ {
+ # if defined(VGP_x86_linux) || defined(VGP_ppc32_linux) \
+- || defined(VGP_ppc64_linux) || defined(VGP_s390x_linux)
++ || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \
++ || defined(VGP_s390x_linux)
+ SysRes res;
+ UWord args[5];
+ args[0] = sd;
+@@ -1133,7 +1139,8 @@ Int VG_(setsockopt) ( Int sd, Int level, Int optname, void *optval,
+ Int optlen)
+ {
+ # if defined(VGP_x86_linux) || defined(VGP_ppc32_linux) \
+- || defined(VGP_ppc64_linux) || defined(VGP_s390x_linux)
++ || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \
++ || defined(VGP_s390x_linux)
+ SysRes res;
+ UWord args[5];
+ args[0] = sd;
+diff --git a/coregrind/m_libcproc.c b/coregrind/m_libcproc.c
+index 25b295c..41bca83 100644
+--- a/coregrind/m_libcproc.c
++++ b/coregrind/m_libcproc.c
+@@ -555,8 +555,8 @@ Int VG_(getgroups)( Int size, UInt* list )
+ list[i] = (UInt)list16[i];
+ return sr_Res(sres);
+
+-# elif defined(VGP_amd64_linux) || defined(VGP_ppc64_linux) \
+- || defined(VGP_arm_linux) \
++# elif defined(VGP_amd64_linux) || defined(VGP_arm_linux) \
++ || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \
+ || defined(VGO_darwin) || defined(VGP_s390x_linux) \
+ || defined(VGP_mips32_linux) || defined(VGP_arm64_linux)
+ SysRes sres;
+@@ -741,7 +741,7 @@ void VG_(invalidate_icache) ( void *ptr, SizeT nbytes )
+ // If I-caches are coherent, nothing needs to be done here
+ if (vai.hwcache_info.icaches_maintain_coherence) return;
+
+-# if defined(VGA_ppc32) || defined(VGA_ppc64)
++# if defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le)
+ Addr startaddr = (Addr) ptr;
+ Addr endaddr = startaddr + nbytes;
+ Addr cls;
+diff --git a/coregrind/m_libcsetjmp.c b/coregrind/m_libcsetjmp.c
+index 5b72182..488e8e8 100644
+--- a/coregrind/m_libcsetjmp.c
++++ b/coregrind/m_libcsetjmp.c
+@@ -149,7 +149,7 @@ __asm__(
+
+ /* ------------ ppc64-linux ------------ */
+
+-#if defined(VGP_ppc64_linux)
++#if defined(VGP_ppc64be_linux)
+
+ __asm__(
+ ".section \".toc\",\"aw\"" "\n"
+@@ -270,7 +270,7 @@ __asm__(
+ ".previous" "\n"
+ );
+
+-#endif /* VGP_ppc64_linux */
++#endif /* VGP_ppc64be_linux */
+
+
+ /* ------------ amd64-{linux,darwin} ------------ */
+diff --git a/coregrind/m_machine.c b/coregrind/m_machine.c
+index c09d528..45b0fa7 100644
+--- a/coregrind/m_machine.c
++++ b/coregrind/m_machine.c
+@@ -81,7 +81,7 @@ void VG_(get_UnwindStartRegs) ( /*OUT*/UnwindStartRegs* regs,
+ regs->r_sp = (ULong)VG_(threads)[tid].arch.vex.guest_GPR1;
+ regs->misc.PPC32.r_lr
+ = VG_(threads)[tid].arch.vex.guest_LR;
+-# elif defined(VGA_ppc64)
++# elif defined(VGA_ppc64be) || defined(VGA_ppc64le)
+ regs->r_pc = VG_(threads)[tid].arch.vex.guest_CIA;
+ regs->r_sp = VG_(threads)[tid].arch.vex.guest_GPR1;
+ regs->misc.PPC64.r_lr
+@@ -212,7 +212,7 @@ static void apply_to_GPs_of_tid(ThreadId tid, void (*f)(ThreadId,
+ (*f)(tid, "R13", vex->guest_R13);
+ (*f)(tid, "R14", vex->guest_R14);
+ (*f)(tid, "R15", vex->guest_R15);
+-#elif defined(VGA_ppc32) || defined(VGA_ppc64)
++#elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le)
+ (*f)(tid, "GPR0" , vex->guest_GPR0 );
+ (*f)(tid, "GPR1" , vex->guest_GPR1 );
+ (*f)(tid, "GPR2" , vex->guest_GPR2 );
+@@ -442,7 +442,7 @@ UInt VG_(machine_x86_have_mxcsr) = 0;
+ UInt VG_(machine_ppc32_has_FP) = 0;
+ UInt VG_(machine_ppc32_has_VMX) = 0;
+ #endif
+-#if defined(VGA_ppc64)
++#if defined(VGA_ppc64be) || defined(VGA_ppc64le)
+ ULong VG_(machine_ppc64_has_VMX) = 0;
+ #endif
+ #if defined(VGA_arm)
+@@ -452,7 +452,7 @@ Int VG_(machine_arm_archlevel) = 4;
+
+ /* For hwcaps detection on ppc32/64, s390x, and arm we'll need to do SIGILL
+ testing, so we need a VG_MINIMAL_JMP_BUF. */
+-#if defined(VGA_ppc32) || defined(VGA_ppc64) \
++#if defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le) \
+ || defined(VGA_arm) || defined(VGA_s390x) || defined(VGA_mips32)
+ #include "pub_core_libcsetjmp.h"
+ static VG_MINIMAL_JMP_BUF(env_unsup_insn);
+@@ -470,7 +470,7 @@ static void handler_unsup_insn ( Int x ) {
+ * Not very defensive: assumes that as long as the dcbz/dcbzl
+ * instructions don't raise a SIGILL, that they will zero an aligned,
+ * contiguous block of memory of a sensible size. */
+-#if defined(VGA_ppc32) || defined(VGA_ppc64)
++#if defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le)
+ static void find_ppc_dcbz_sz(VexArchInfo *arch_info)
+ {
+ Int dcbz_szB = 0;
+@@ -523,7 +523,7 @@ static void find_ppc_dcbz_sz(VexArchInfo *arch_info)
+ dcbz_szB, dcbzl_szB);
+ # undef MAX_DCBZL_SZB
+ }
+-#endif /* defined(VGA_ppc32) || defined(VGA_ppc64) */
++#endif /* defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le) */
+
+ #ifdef VGA_s390x
+
+@@ -1064,7 +1064,7 @@ Bool VG_(machine_get_hwcaps)( void )
+ return True;
+ }
+
+-#elif defined(VGA_ppc64)
++#elif defined(VGA_ppc64be)|| defined(VGA_ppc64le)
+ {
+ /* Same instruction set detection algorithm as for ppc32. */
+ vki_sigset_t saved_set, tmp_set;
+@@ -1178,7 +1178,7 @@ Bool VG_(machine_get_hwcaps)( void )
+ (Int)have_F, (Int)have_V, (Int)have_FX,
+ (Int)have_GX, (Int)have_VX, (Int)have_DFP,
+ (Int)have_isa_2_07);
+- /* on ppc64, if we don't even have FP, just give up. */
++ /* on ppc64be, if we don't even have FP, just give up. */
+ if (!have_F)
+ return False;
+
+@@ -1599,7 +1599,7 @@ void VG_(machine_ppc32_set_clszB)( Int szB )
+
+
+ /* Notify host cpu instruction cache line size. */
+-#if defined(VGA_ppc64)
++#if defined(VGA_ppc64be)|| defined(VGA_ppc64le)
+ void VG_(machine_ppc64_set_clszB)( Int szB )
+ {
+ vg_assert(hwcaps_done);
+@@ -1681,7 +1681,7 @@ Int VG_(machine_get_size_of_largest_guest_register) ( void )
+ if (vai.hwcaps & VEX_HWCAPS_PPC32_DFP) return 16;
+ return 8;
+
+-# elif defined(VGA_ppc64)
++# elif defined(VGA_ppc64be) || defined(VGA_ppc64le)
+ /* 8 if boring; 16 if signs of Altivec or other exotic stuff */
+ if (vai.hwcaps & VEX_HWCAPS_PPC64_V) return 16;
+ if (vai.hwcaps & VEX_HWCAPS_PPC64_VX) return 16;
+@@ -1719,12 +1719,12 @@ Int VG_(machine_get_size_of_largest_guest_register) ( void )
+ void* VG_(fnptr_to_fnentry)( void* f )
+ {
+ # if defined(VGP_x86_linux) || defined(VGP_amd64_linux) \
+- || defined(VGP_arm_linux) \
+- || defined(VGP_ppc32_linux) || defined(VGO_darwin) \
++ || defined(VGP_arm_linux) || defined(VGO_darwin) \
++ || defined(VGP_ppc32_linux) || defined(VGP_ppc64le_linux) \
+ || defined(VGP_s390x_linux) || defined(VGP_mips32_linux) \
+ || defined(VGP_mips64_linux) || defined(VGP_arm64_linux)
+ return f;
+-# elif defined(VGP_ppc64_linux)
++# elif defined(VGP_ppc64be_linux)
+ /* ppc64-linux uses the AIX scheme, in which f is a pointer to a
+ 3-word function descriptor, of which the first word is the entry
+ address. */
+diff --git a/coregrind/m_main.c b/coregrind/m_main.c
+index d2ce001..96ef31c 100644
+--- a/coregrind/m_main.c
++++ b/coregrind/m_main.c
+@@ -2023,7 +2023,8 @@ Int valgrind_main ( Int argc, HChar **argv, HChar **envp )
+
+ # if defined(VGP_x86_linux)
+ iters = 10;
+-# elif defined(VGP_amd64_linux) || defined(VGP_ppc64_linux)
++# elif defined(VGP_amd64_linux) || defined(VGP_ppc64be_linux) \
++ || defined(VGP_ppc64le_linux)
+ iters = 10;
+ # elif defined(VGP_ppc32_linux)
+ iters = 5;
+@@ -2602,7 +2603,7 @@ void shutdown_actions_NORETURN( ThreadId tid,
+ static void final_tidyup(ThreadId tid)
+ {
+ #if !defined(VGO_darwin)
+-# if defined(VGP_ppc64_linux)
++# if defined(VGP_ppc64be_linux)
+ Addr r2;
+ # endif
+ Addr __libc_freeres_wrapper = VG_(client___libc_freeres_wrapper);
+@@ -2614,7 +2615,7 @@ static void final_tidyup(ThreadId tid)
+ 0 == __libc_freeres_wrapper )
+ return; /* can't/won't do it */
+
+-# if defined(VGP_ppc64_linux)
++# if defined(VGP_ppc64be_linux)
+ r2 = VG_(get_tocptr)( __libc_freeres_wrapper );
+ if (r2 == 0) {
+ VG_(message)(Vg_UserMsg,
+@@ -2632,12 +2633,12 @@ static void final_tidyup(ThreadId tid)
+ "Caught __NR_exit; running __libc_freeres()\n");
+
+ /* set thread context to point to libc_freeres_wrapper */
+- /* ppc64-linux note: __libc_freeres_wrapper gives us the real
++ /* ppc64be-linux note: __libc_freeres_wrapper gives us the real
+ function entry point, not a fn descriptor, so can use it
+ directly. However, we need to set R2 (the toc pointer)
+ appropriately. */
+ VG_(set_IP)(tid, __libc_freeres_wrapper);
+-# if defined(VGP_ppc64_linux)
++# if defined(VGP_ppc64be_linux)
+ VG_(threads)[tid].arch.vex.guest_GPR2 = r2;
+ # endif
+ /* mips-linux note: we need to set t9 */
+@@ -2834,7 +2835,7 @@ asm("\n"
+ "\ttrap\n"
+ ".previous\n"
+ );
+-#elif defined(VGP_ppc64_linux)
++#elif defined(VGP_ppc64be_linux)
+ asm("\n"
+ /* PPC64 ELF ABI says '_start' points to a function descriptor.
+ So we must have one, and that is what goes into the .opd section. */
+@@ -3093,10 +3094,10 @@ void _start_in_C_linux ( UWord* pArgc )
+
+ the_iicii.sp_at_startup = (Addr)pArgc;
+
+-# if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) \
+- || defined(VGP_arm64_linux)
++# if defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux) \
++ || defined(VGP_ppc64le_linux) || defined(VGP_arm64_linux)
+ {
+- /* ppc/ppc64 can be configured with different page sizes.
++ /* ppc32/ppc64 can be configured with different page sizes.
+ Determine this early. This is an ugly hack and really should
+ be moved into valgrind_main. */
+ UWord *sp = &pArgc[1+argc+1];
+diff --git a/coregrind/m_redir.c b/coregrind/m_redir.c
+index b13b3fb..dc77119 100644
+--- a/coregrind/m_redir.c
++++ b/coregrind/m_redir.c
+@@ -1278,7 +1278,7 @@ void VG_(redir_initialise) ( void )
+ );
+ }
+
+-# elif defined(VGP_ppc64_linux)
++# elif defined(VGP_ppc64be_linux)
+ /* If we're using memcheck, use these intercepts right from
+ the start, otherwise ld.so makes a lot of noise. */
+ if (0==VG_(strcmp)("Memcheck", VG_(details).name)) {
+diff --git a/coregrind/m_scheduler/scheduler.c b/coregrind/m_scheduler/scheduler.c
+index 8808abc..64d45cb 100644
+--- a/coregrind/m_scheduler/scheduler.c
++++ b/coregrind/m_scheduler/scheduler.c
+@@ -768,7 +768,7 @@ static void do_pre_run_checks ( ThreadState* tst )
+ vg_assert(VG_IS_8_ALIGNED(offsetof(VexGuestAMD64State,guest_RIP)));
+ # endif
+
+-# if defined(VGA_ppc32) || defined(VGA_ppc64)
++# if defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le)
+ /* ppc guest_state vector regs must be 16 byte aligned for
+ loads/stores. This is important! */
+ vg_assert(VG_IS_16_ALIGNED(& tst->arch.vex.guest_VSR0));
+@@ -1622,7 +1622,7 @@ void VG_(nuke_all_threads_except) ( ThreadId me, VgSchedReturnCode src )
+ #elif defined(VGA_amd64)
+ # define VG_CLREQ_ARGS guest_RAX
+ # define VG_CLREQ_RET guest_RDX
+-#elif defined(VGA_ppc32) || defined(VGA_ppc64)
++#elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le)
+ # define VG_CLREQ_ARGS guest_GPR4
+ # define VG_CLREQ_RET guest_GPR3
+ #elif defined(VGA_arm)
+diff --git a/coregrind/m_sigframe/sigframe-ppc64-linux.c b/coregrind/m_sigframe/sigframe-ppc64-linux.c
+index 3e5fa74..bb53806 100644
+--- a/coregrind/m_sigframe/sigframe-ppc64-linux.c
++++ b/coregrind/m_sigframe/sigframe-ppc64-linux.c
+@@ -31,7 +31,7 @@
+ The GNU General Public License is contained in the file COPYING.
+ */
+
+-#if defined(VGP_ppc64_linux)
++#if defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
+
+ #include "pub_core_basics.h"
+ #include "pub_core_vki.h"
+@@ -388,7 +388,7 @@ void VG_(sigframe_destroy)( ThreadId tid, Bool isRT )
+ VG_TRACK( post_deliver_signal, tid, sigNo );
+ }
+
+-#endif // defined(VGP_ppc64_linux)
++#endif // defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
+
+ /*--------------------------------------------------------------------*/
+ /*--- end ---*/
+diff --git a/coregrind/m_signals.c b/coregrind/m_signals.c
+index 40bd7ea..0fd11c4 100644
+--- a/coregrind/m_signals.c
++++ b/coregrind/m_signals.c
+@@ -348,7 +348,7 @@ typedef struct SigQueue {
+ (srP)->misc.PPC32.r_lr = (uc)->uc_regs->mc_gregs[VKI_PT_LNK]; \
+ }
+
+-#elif defined(VGP_ppc64_linux)
++#elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
+ # define VG_UCONTEXT_INSTR_PTR(uc) ((uc)->uc_mcontext.gp_regs[VKI_PT_NIP])
+ # define VG_UCONTEXT_STACK_PTR(uc) ((uc)->uc_mcontext.gp_regs[VKI_PT_R1])
+ /* Dubious hack: if there is an error, only consider the lowest 8
+@@ -851,7 +851,7 @@ extern void my_sigreturn(void);
+ " sc\n" \
+ ".previous\n"
+
+-#elif defined(VGP_ppc64_linux)
++#elif defined(VGP_ppc64be_linux)
+ # define _MY_SIGRETURN(name) \
+ ".align 2\n" \
+ ".globl my_sigreturn\n" \
+diff --git a/coregrind/m_stacktrace.c b/coregrind/m_stacktrace.c
+index 6e73e17..64e1ac4 100644
+--- a/coregrind/m_stacktrace.c
++++ b/coregrind/m_stacktrace.c
+@@ -622,7 +622,8 @@ UInt VG_(get_StackTrace_wrk) ( ThreadId tid_if_known,
+
+ /* -----------------------ppc32/64 ---------------------- */
+
+-#if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux)
++#if defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux) \
++ || defined(VGP_ppc64le_linux)
+
+ UInt VG_(get_StackTrace_wrk) ( ThreadId tid_if_known,
+ /*OUT*/Addr* ips, UInt max_n_ips,
+@@ -631,7 +632,7 @@ UInt VG_(get_StackTrace_wrk) ( ThreadId tid_if_known,
+ Addr fp_max_orig )
+ {
+ Bool lr_is_first_RA = False;
+-# if defined(VG_PLAT_USES_PPCTOC)
++# if defined(VG_PLAT_USES_PPCTOC) || defined(VGP_ppc64le_linux)
+ Word redir_stack_size = 0;
+ Word redirs_used = 0;
+ # endif
+@@ -650,7 +651,7 @@ UInt VG_(get_StackTrace_wrk) ( ThreadId tid_if_known,
+ Addr fp = sp;
+ # if defined(VGP_ppc32_linux)
+ Addr lr = startRegs->misc.PPC32.r_lr;
+-# elif defined(VGP_ppc64_linux)
++# elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
+ Addr lr = startRegs->misc.PPC64.r_lr;
+ # endif
+ Addr fp_min = sp;
+@@ -686,7 +687,7 @@ UInt VG_(get_StackTrace_wrk) ( ThreadId tid_if_known,
+ /* fp is %r1. ip is %cia. Note, ppc uses r1 as both the stack and
+ frame pointers. */
+
+-# if defined(VGP_ppc64_linux)
++# if defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
+ redir_stack_size = VEX_GUEST_PPC64_REDIR_STACK_SIZE;
+ redirs_used = 0;
+ # endif
+@@ -742,7 +743,7 @@ UInt VG_(get_StackTrace_wrk) ( ThreadId tid_if_known,
+ /* On ppc64-linux (ppc64-elf, really), the lr save
+ slot is 2 words back from sp, whereas on ppc32-elf(?) it's
+ only one word back. */
+-# if defined(VG_PLAT_USES_PPCTOC)
++# if defined(VG_PLAT_USES_PPCTOC) || defined(VGP_ppc64le_linux)
+ const Int lr_offset = 2;
+ # else
+ const Int lr_offset = 1;
+@@ -761,7 +762,7 @@ UInt VG_(get_StackTrace_wrk) ( ThreadId tid_if_known,
+ else
+ ip = (((UWord*)fp)[lr_offset]);
+
+-# if defined(VG_PLAT_USES_PPCTOC)
++# if defined(VG_PLAT_USES_PPCTOC) || defined(VGP_ppc64le_linux)
+ /* Nasty hack to do with function replacement/wrapping on
+ ppc64-linux. If LR points to our magic return stub,
+ then we are in a wrapped or intercepted function, in
+diff --git a/coregrind/m_syscall.c b/coregrind/m_syscall.c
+index 161be15..b111e5c 100644
+--- a/coregrind/m_syscall.c
++++ b/coregrind/m_syscall.c
+@@ -386,7 +386,7 @@ asm(
+ ".previous\n"
+ );
+
+-#elif defined(VGP_ppc64_linux)
++#elif defined(VGP_ppc64be_linux)
+ /* Due to the need to return 65 bits of result, this is completely
+ different from the ppc32 case. The single arg register points to a
+ 7-word block containing the syscall # and the 6 args. The syscall
+@@ -720,7 +720,7 @@ SysRes VG_(do_syscall) ( UWord sysno, UWord a1, UWord a2, UWord a3,
+ UInt cr0so = (UInt)(ret);
+ return VG_(mk_SysRes_ppc32_linux)( val, cr0so );
+
+-# elif defined(VGP_ppc64_linux)
++# elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
+ ULong argblock[7];
+ argblock[0] = sysno;
+ argblock[1] = a1;
+diff --git a/coregrind/m_syswrap/priv_types_n_macros.h b/coregrind/m_syswrap/priv_types_n_macros.h
+index 325c53a..e69bdf3 100644
+--- a/coregrind/m_syswrap/priv_types_n_macros.h
++++ b/coregrind/m_syswrap/priv_types_n_macros.h
+@@ -90,7 +90,8 @@ typedef
+ // field names), the s_arg value is the offset from the stack pointer.
+ Int o_sysno;
+ # if defined(VGP_x86_linux) || defined(VGP_amd64_linux) \
+- || defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) \
++ || defined(VGP_ppc32_linux) \
++ || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \
+ || defined(VGP_arm_linux) || defined(VGP_s390x_linux) \
+ || defined(VGP_mips64_linux) || defined(VGP_arm64_linux)
+ Int o_arg1;
+diff --git a/coregrind/m_syswrap/syscall-ppc64-linux.S b/coregrind/m_syswrap/syscall-ppc64-linux.S
+index 30ae594..df73940 100644
+--- a/coregrind/m_syswrap/syscall-ppc64-linux.S
++++ b/coregrind/m_syswrap/syscall-ppc64-linux.S
+@@ -27,7 +27,7 @@
+ The GNU General Public License is contained in the file COPYING.
+ */
+
+-#if defined(VGP_ppc64_linux)
++#if defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
+
+ #include "pub_core_basics_asm.h"
+ #include "pub_core_vkiscnums_asm.h"
+@@ -165,7 +165,7 @@ ML_(blksys_finished): .quad 5b
+ /* Let the linker know we don't need an executable stack */
+ .section .note.GNU-stack,"", at progbits
+
+-#endif // defined(VGP_ppc64_linux)
++#endif // defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
+
+ /*--------------------------------------------------------------------*/
+ /*--- end ---*/
+diff --git a/coregrind/m_syswrap/syswrap-linux.c b/coregrind/m_syswrap/syswrap-linux.c
+index c195ca2..d224207 100644
+--- a/coregrind/m_syswrap/syswrap-linux.c
++++ b/coregrind/m_syswrap/syswrap-linux.c
+@@ -244,7 +244,8 @@ static void run_a_thread_NORETURN ( Word tidW )
+ : "n" (VgTs_Empty), "n" (__NR_exit), "m" (tst->os_state.exitcode)
+ : "rax", "rdi"
+ );
+-#elif defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux)
++#elif defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux) \
++ || defined(VGP_ppc64le_linux)
+ { UInt vgts_empty = (UInt)VgTs_Empty;
+ asm volatile (
+ "stw %1,%0\n\t" /* set tst->status = VgTs_Empty */
+@@ -385,7 +386,7 @@ void VG_(main_thread_wrapper_NORETURN)(ThreadId tid)
+ sp -= 16;
+ sp &= ~0xF;
+ *(UWord *)sp = 0;
+-#elif defined(VGP_ppc64_linux)
++#elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
+ /* make a stack frame */
+ sp -= 112;
+ sp &= ~((Addr)0xF);
+@@ -438,7 +439,8 @@ SysRes ML_(do_fork_clone) ( ThreadId tid, UInt flags,
+ /* Since this is the fork() form of clone, we don't need all that
+ VG_(clone) stuff */
+ #if defined(VGP_x86_linux) \
+- || defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) \
++ || defined(VGP_ppc32_linux) \
++ || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \
+ || defined(VGP_arm_linux) || defined(VGP_mips32_linux) \
+ || defined(VGP_mips64_linux) || defined(VGP_arm64_linux)
+ res = VG_(do_syscall5)( __NR_clone, flags,
+diff --git a/coregrind/m_syswrap/syswrap-main.c b/coregrind/m_syswrap/syswrap-main.c
+index 8f25497..077a9b4 100644
+--- a/coregrind/m_syswrap/syswrap-main.c
++++ b/coregrind/m_syswrap/syswrap-main.c
+@@ -442,7 +442,7 @@ void getSyscallArgsFromGuestState ( /*OUT*/SyscallArgs* canonical,
+ canonical->arg7 = 0;
+ canonical->arg8 = 0;
+
+-#elif defined(VGP_ppc64_linux)
++#elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
+ VexGuestPPC64State* gst = (VexGuestPPC64State*)gst_vanilla;
+ canonical->sysno = gst->guest_GPR0;
+ canonical->arg1 = gst->guest_GPR3;
+@@ -688,7 +688,7 @@ void putSyscallArgsIntoGuestState ( /*IN*/ SyscallArgs* canonical,
+ gst->guest_GPR7 = canonical->arg5;
+ gst->guest_GPR8 = canonical->arg6;
+
+-#elif defined(VGP_ppc64_linux)
++#elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
+ VexGuestPPC64State* gst = (VexGuestPPC64State*)gst_vanilla;
+ gst->guest_GPR0 = canonical->sysno;
+ gst->guest_GPR3 = canonical->arg1;
+@@ -819,7 +819,7 @@ void getSyscallStatusFromGuestState ( /*OUT*/SyscallStatus* canonical,
+ canonical->sres = VG_(mk_SysRes_ppc32_linux)( gst->guest_GPR3, cr0so );
+ canonical->what = SsComplete;
+
+-# elif defined(VGP_ppc64_linux)
++# elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
+ VexGuestPPC64State* gst = (VexGuestPPC64State*)gst_vanilla;
+ UInt cr = LibVEX_GuestPPC64_get_CR( gst );
+ UInt cr0so = (cr >> 28) & 1;
+@@ -977,7 +977,7 @@ void putSyscallStatusIntoGuestState ( /*IN*/ ThreadId tid,
+ VG_TRACK( post_reg_write, Vg_CoreSysCall, tid,
+ OFFSET_ppc32_CR0_0, sizeof(UChar) );
+
+-# elif defined(VGP_ppc64_linux)
++# elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
+ VexGuestPPC64State* gst = (VexGuestPPC64State*)gst_vanilla;
+ UInt old_cr = LibVEX_GuestPPC64_get_CR(gst);
+ vg_assert(canonical->what == SsComplete);
+@@ -1182,7 +1182,7 @@ void getSyscallArgLayout ( /*OUT*/SyscallArgLayout* layout )
+ layout->uu_arg7 = -1; /* impossible value */
+ layout->uu_arg8 = -1; /* impossible value */
+
+-#elif defined(VGP_ppc64_linux)
++#elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
+ layout->o_sysno = OFFSET_ppc64_GPR0;
+ layout->o_arg1 = OFFSET_ppc64_GPR3;
+ layout->o_arg2 = OFFSET_ppc64_GPR4;
+@@ -1988,7 +1988,7 @@ void ML_(fixup_guest_state_to_restart_syscall) ( ThreadArchState* arch )
+ vg_assert(p[0] == 0x0F && p[1] == 0x05);
+ }
+
+-#elif defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux)
++#elif defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux)
+ arch->vex.guest_CIA -= 4; // sizeof(ppc32 instr)
+
+ /* Make sure our caller is actually sane, and we're really backing
+diff --git a/coregrind/m_syswrap/syswrap-ppc64-linux.c b/coregrind/m_syswrap/syswrap-ppc64-linux.c
+index 4673dda..5d266b8 100644
+--- a/coregrind/m_syswrap/syswrap-ppc64-linux.c
++++ b/coregrind/m_syswrap/syswrap-ppc64-linux.c
+@@ -28,7 +28,7 @@
+ The GNU General Public License is contained in the file COPYING.
+ */
+
+-#if defined(VGP_ppc64_linux)
++#if defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
+
+ #include "pub_core_basics.h"
+ #include "pub_core_vki.h"
+@@ -1074,7 +1074,7 @@ SyscallTableEntry* ML_(get_linux_syscall_entry) ( UInt sysno )
+ return NULL;
+ }
+
+-#endif // defined(VGP_ppc64_linux)
++#endif // defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
+
+ /*--------------------------------------------------------------------*/
+ /*--- end ---*/
+diff --git a/coregrind/m_trampoline.S b/coregrind/m_trampoline.S
+index 5dd362c..c859bdd 100644
+--- a/coregrind/m_trampoline.S
++++ b/coregrind/m_trampoline.S
+@@ -416,7 +416,7 @@ VG_(trampoline_stuff_end):
+
+ /*---------------- ppc64-linux ----------------*/
+ #else
+-#if defined(VGP_ppc64_linux)
++#if defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
+
+ # define UD2_16 trap ; trap ; trap; trap
+ # define UD2_64 UD2_16 ; UD2_16 ; UD2_16 ; UD2_16
+diff --git a/coregrind/m_translate.c b/coregrind/m_translate.c
+index d1757bb..0919394 100644
+--- a/coregrind/m_translate.c
++++ b/coregrind/m_translate.c
+@@ -868,7 +868,7 @@ static Bool chase_into_ok ( void* closureV, Addr64 addr64 )
+ if (addr != VG_(redir_do_lookup)(addr, NULL))
+ goto dontchase;
+
+-# if defined(VG_PLAT_USES_PPCTOC)
++# if defined(VG_PLAT_USES_PPCTOC) || defined(VGP_ppc64le_linux)
+ /* This needs to be at the start of its own block. Don't chase. Re
+ ULong_to_Ptr, be careful to ensure we only compare 32 bits on a
+ 32-bit target.*/
+@@ -918,7 +918,7 @@ static IRExpr* mkU32 ( UInt n ) {
+ return IRExpr_Const(IRConst_U32(n));
+ }
+
+-#if defined(VG_PLAT_USES_PPCTOC)
++#if defined(VG_PLAT_USES_PPCTOC) || defined(VGP_ppc64le_linux)
+ static IRExpr* mkU8 ( UChar n ) {
+ return IRExpr_Const(IRConst_U8(n));
+ }
+@@ -941,7 +941,7 @@ static void gen_PUSH ( IRSB* bb, IRExpr* e )
+ IRTemp t1;
+ IRExpr* one;
+
+-# if defined(VGP_ppc64_linux)
++# if defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
+ Int stack_size = VEX_GUEST_PPC64_REDIR_STACK_SIZE;
+ Int offB_REDIR_SP = offsetof(VexGuestPPC64State,guest_REDIR_SP);
+ Int offB_REDIR_STACK = offsetof(VexGuestPPC64State,guest_REDIR_STACK);
+@@ -1035,7 +1035,7 @@ static void gen_PUSH ( IRSB* bb, IRExpr* e )
+
+ static IRTemp gen_POP ( IRSB* bb )
+ {
+-# if defined(VGP_ppc64_linux)
++# if defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
+ Int stack_size = VEX_GUEST_PPC64_REDIR_STACK_SIZE;
+ Int offB_REDIR_SP = offsetof(VexGuestPPC64State,guest_REDIR_SP);
+ Int offB_REDIR_STACK = offsetof(VexGuestPPC64State,guest_REDIR_STACK);
+@@ -1127,7 +1127,7 @@ static IRTemp gen_POP ( IRSB* bb )
+
+ static void gen_push_and_set_LR_R2 ( IRSB* bb, Addr64 new_R2_value )
+ {
+-# if defined(VGP_ppc64_linux)
++# if defined(VGP_ppc64be_linux)
+ Addr64 bogus_RA = (Addr64)&VG_(ppctoc_magic_redirect_return_stub);
+ Int offB_GPR2 = offsetof(VexGuestPPC64State,guest_GPR2);
+ Int offB_LR = offsetof(VexGuestPPC64State,guest_LR);
+@@ -1143,7 +1143,7 @@ static void gen_push_and_set_LR_R2 ( IRSB* bb, Addr64 new_R2_value )
+
+ static void gen_pop_R2_LR_then_bLR ( IRSB* bb )
+ {
+-# if defined(VGP_ppc64_linux)
++# if defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
+ Int offB_GPR2 = offsetof(VexGuestPPC64State,guest_GPR2);
+ Int offB_LR = offsetof(VexGuestPPC64State,guest_LR);
+ Int offB_CIA = offsetof(VexGuestPPC64State,guest_CIA);
+@@ -1277,7 +1277,7 @@ Bool mk_preamble__set_NRADDR_to_nraddr ( void* closureV, IRSB* bb )
+ Int offB_GPR25 = offsetof(VexGuestMIPS64State, guest_r25);
+ addStmtToIRSB(bb, IRStmt_Put(offB_GPR25, mkU64(closure->readdr)));
+ # endif
+-# if defined(VGP_ppc64_linux)
++# if defined(VGP_ppc64be_linux)
+ addStmtToIRSB(
+ bb,
+ IRStmt_Put(
+@@ -1523,7 +1523,7 @@ Bool VG_(translate) ( ThreadId tid,
+ vex_abiinfo.guest_ppc_zap_RZ_at_blr = False;
+ vex_abiinfo.guest_ppc_zap_RZ_at_bl = NULL;
+ # endif
+-# if defined(VGP_ppc64_linux)
++# if defined(VGP_ppc64be_linux)
+ vex_abiinfo.guest_ppc_zap_RZ_at_blr = True;
+ vex_abiinfo.guest_ppc_zap_RZ_at_bl = const_True;
+ vex_abiinfo.host_ppc_calls_use_fndescrs = True;
+diff --git a/coregrind/m_ume/elf.c b/coregrind/m_ume/elf.c
+index 7d79f96..910bb7a 100644
+--- a/coregrind/m_ume/elf.c
++++ b/coregrind/m_ume/elf.c
+@@ -505,9 +505,9 @@ Int VG_(load_ELF)(Int fd, const HChar* name, /*MOD*/ExeInfo* info)
+ info->exe_base = minaddr + ebase;
+ info->exe_end = maxaddr + ebase;
+
+-#if defined(VGP_ppc64_linux)
+- /* On PPC64, a func ptr is represented by a TOC entry ptr. This
+- TOC entry contains three words; the first word is the function
++#if defined(VGP_ppc64be_linux)
++ /* On PPC64BE, ELF ver 1, a func ptr is represented by a TOC entry ptr.
++ This TOC entry contains three words; the first word is the function
+ address, the second word is the TOC ptr (r2), and the third word
+ is the static chain value. */
+ info->init_ip = ((ULong*)entry)[0];
+diff --git a/coregrind/m_ume/macho.c b/coregrind/m_ume/macho.c
+index f79a561..7608811 100644
+--- a/coregrind/m_ume/macho.c
++++ b/coregrind/m_ume/macho.c
+@@ -699,8 +699,8 @@ load_fat_file(int fd, vki_off_t offset, vki_off_t size, unsigned long filetype,
+
+ #if defined(VGA_ppc32)
+ good_arch = CPU_TYPE_POWERPC;
+-#elif defined(VGA_ppc64)
+- good_arch = CPU_TYPE_POWERPC64;
++#elif defined(VGA_ppc64be)
++ good_arch = CPU_TYPE_POWERPC64BE;
+ #elif defined(VGA_x86)
+ good_arch = CPU_TYPE_I386;
+ #elif defined(VGA_amd64)
+diff --git a/coregrind/m_vki.c b/coregrind/m_vki.c
+index 1563623..2e1626b 100644
+--- a/coregrind/m_vki.c
++++ b/coregrind/m_vki.c
+@@ -42,8 +42,8 @@
+ /* ppc32/64-linux determines page size at startup, hence m_vki is
+ the logical place to store that info. */
+
+-#if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) \
+- || defined(VGP_arm64_linux)
++#if defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux) \
++ || defined(VGP_ppc64le_linux) || defined(VGP_arm64_linux)
+ unsigned long VKI_PAGE_SHIFT = 12;
+ unsigned long VKI_PAGE_SIZE = 1UL << 12;
+ #endif
+diff --git a/coregrind/pub_core_aspacemgr.h b/coregrind/pub_core_aspacemgr.h
+index ba5df5a..4dd62cb 100644
+--- a/coregrind/pub_core_aspacemgr.h
++++ b/coregrind/pub_core_aspacemgr.h
+@@ -334,7 +334,8 @@ extern Bool VG_(am_relocate_nooverlap_client)( /*OUT*/Bool* need_discard,
+ // stacks. The address space manager provides and suitably
+ // protects such stacks.
+
+-#if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux) \
++#if defined(VGP_ppc32_linux) \
++ || defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux) \
+ || defined(VGP_mips32_linux) || defined(VGP_mips64_linux) \
+ || defined(VGP_arm64_linux)
+ # define VG_STACK_GUARD_SZB 65536 // 1 or 16 pages
+diff --git a/coregrind/pub_core_basics.h b/coregrind/pub_core_basics.h
+index 2959015..05b3d66 100644
+--- a/coregrind/pub_core_basics.h
++++ b/coregrind/pub_core_basics.h
+@@ -54,7 +54,7 @@
+ # include "libvex_guest_amd64.h"
+ #elif defined(VGA_ppc32)
+ # include "libvex_guest_ppc32.h"
+-#elif defined(VGA_ppc64)
++#elif defined(VGA_ppc64be) || defined(VGA_ppc64le)
+ # include "libvex_guest_ppc64.h"
+ #elif defined(VGA_arm)
+ # include "libvex_guest_arm.h"
+diff --git a/coregrind/pub_core_debuginfo.h b/coregrind/pub_core_debuginfo.h
+index 697969a..5e93793 100644
+--- a/coregrind/pub_core_debuginfo.h
++++ b/coregrind/pub_core_debuginfo.h
+@@ -118,7 +118,7 @@ typedef
+ typedef
+ struct { Addr pc; Addr sp; Addr x30; Addr x29; } /* PC, SP, LR, FP */
+ D3UnwindRegs;
+-#elif defined(VGA_ppc32) || defined(VGA_ppc64)
++#elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le)
+ typedef
+ UChar /* should be void, but gcc complains at use points */
+ D3UnwindRegs;
+diff --git a/coregrind/pub_core_machine.h b/coregrind/pub_core_machine.h
+index 0cd5cf8..f1d839a 100644
+--- a/coregrind/pub_core_machine.h
++++ b/coregrind/pub_core_machine.h
+@@ -56,7 +56,7 @@
+ # define VG_ELF_MACHINE EM_PPC
+ # define VG_ELF_CLASS ELFCLASS32
+ # undef VG_PLAT_USES_PPCTOC
+-#elif defined(VGP_ppc64_linux)
++#elif defined(VGP_ppc64be_linux)
+ # define VG_ELF_DATA2XXX ELFDATA2MSB
+ # define VG_ELF_MACHINE EM_PPC64
+ # define VG_ELF_CLASS ELFCLASS64
+@@ -119,7 +119,7 @@
+ # define VG_INSTR_PTR guest_CIA
+ # define VG_STACK_PTR guest_GPR1
+ # define VG_FRAME_PTR guest_GPR1 // No frame ptr for PPC
+-#elif defined(VGA_ppc64)
++#elif defined(VGA_ppc64be) || defined(VGA_ppc64le)
+ # define VG_INSTR_PTR guest_CIA
+ # define VG_STACK_PTR guest_GPR1
+ # define VG_FRAME_PTR guest_GPR1 // No frame ptr for PPC
+@@ -233,7 +233,7 @@ extern Bool VG_(machine_get_cache_info)( VexArchInfo * );
+ extern void VG_(machine_ppc32_set_clszB)( Int );
+ #endif
+
+-#if defined(VGA_ppc64)
++#if defined(VGA_ppc64be) || defined(VGA_ppc64le)
+ extern void VG_(machine_ppc64_set_clszB)( Int );
+ #endif
+
+@@ -265,7 +265,7 @@ extern UInt VG_(machine_ppc32_has_VMX);
+ /* PPC64: set to 1 if Altivec instructions are supported in
+ user-space, else 0. Is referenced from assembly code, so do not
+ change from a 64-bit int. */
+-#if defined(VGA_ppc64)
++#if defined(VGA_ppc64be) || defined(VGA_ppc64le)
+ extern ULong VG_(machine_ppc64_has_VMX);
+ #endif
+
+diff --git a/coregrind/pub_core_mallocfree.h b/coregrind/pub_core_mallocfree.h
+index 552da97..fafe707 100644
+--- a/coregrind/pub_core_mallocfree.h
++++ b/coregrind/pub_core_mallocfree.h
+@@ -71,13 +71,14 @@ typedef Int ArenaId;
+ // for any AltiVec- or SSE-related type. This matches the Darwin libc.
+ // Also, use 16 bytes for any PPC variant, since 16 is required to make
+ // Altiveccery work right.
+-#elif defined(VGP_amd64_linux) || \
+- defined(VGP_ppc32_linux) || \
+- defined(VGP_ppc64_linux) || \
+- defined(VGP_s390x_linux) || \
+- defined(VGP_mips64_linux) || \
+- defined(VGP_x86_darwin) || \
+- defined(VGP_amd64_darwin) || \
++#elif defined(VGP_amd64_linux) || \
++ defined(VGP_ppc32_linux) || \
++ defined(VGP_ppc64be_linux) || \
++ defined(VGP_ppc64le_linux) || \
++ defined(VGP_s390x_linux) || \
++ defined(VGP_mips64_linux) || \
++ defined(VGP_x86_darwin) || \
++ defined(VGP_amd64_darwin) || \
+ defined(VGP_arm64_linux)
+ # define VG_MIN_MALLOC_SZB 16
+ #else
+diff --git a/coregrind/pub_core_threadstate.h b/coregrind/pub_core_threadstate.h
+index ad6ff82..c2ebb1c 100644
+--- a/coregrind/pub_core_threadstate.h
++++ b/coregrind/pub_core_threadstate.h
+@@ -84,7 +84,7 @@ typedef
+ typedef VexGuestAMD64State VexGuestArchState;
+ #elif defined(VGA_ppc32)
+ typedef VexGuestPPC32State VexGuestArchState;
+-#elif defined(VGA_ppc64)
++#elif defined(VGA_ppc64be) || defined(VGA_ppc64le)
+ typedef VexGuestPPC64State VexGuestArchState;
+ #elif defined(VGA_arm)
+ typedef VexGuestARMState VexGuestArchState;
+diff --git a/coregrind/pub_core_trampoline.h b/coregrind/pub_core_trampoline.h
+index 96710fe..b4c056b 100644
+--- a/coregrind/pub_core_trampoline.h
++++ b/coregrind/pub_core_trampoline.h
+@@ -81,7 +81,7 @@ extern UInt VG_(ppc32_linux_REDIR_FOR_strcmp)( void*, void* );
+ extern void* VG_(ppc32_linux_REDIR_FOR_strchr)( void*, Int );
+ #endif
+
+-#if defined(VGP_ppc64_linux)
++#if defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
+ extern Addr VG_(ppc64_linux_SUBST_FOR_rt_sigreturn);
+ extern UInt VG_(ppc64_linux_REDIR_FOR_strlen)( void* );
+ extern void* VG_(ppc64_linux_REDIR_FOR_strchr)( void*, Int );
+diff --git a/coregrind/pub_core_transtab_asm.h b/coregrind/pub_core_transtab_asm.h
+index 2a3f0f1..b063d54 100644
+--- a/coregrind/pub_core_transtab_asm.h
++++ b/coregrind/pub_core_transtab_asm.h
+@@ -62,8 +62,8 @@
+ #elif defined(VGA_s390x) || defined(VGA_arm)
+ # define VG_TT_FAST_HASH(_addr) ((((UWord)(_addr)) >> 1) & VG_TT_FAST_MASK)
+
+-#elif defined(VGA_ppc32) || defined(VGA_ppc64) || defined(VGA_mips32) \
+- || defined(VGA_mips64) || defined(VGA_arm64)
++#elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le) \
++ || defined(VGA_mips32) || defined(VGA_mips64) || defined(VGA_arm64)
+ # define VG_TT_FAST_HASH(_addr) ((((UWord)(_addr)) >> 2) & VG_TT_FAST_MASK)
+
+ #else
+diff --git a/coregrind/vgdb-invoker-ptrace.c b/coregrind/vgdb-invoker-ptrace.c
+index 0ad631a..bad4df5 100644
+--- a/coregrind/vgdb-invoker-ptrace.c
++++ b/coregrind/vgdb-invoker-ptrace.c
+@@ -843,7 +843,7 @@ Bool invoker_invoke_gdbserver (pid_t pid)
+ sp = user_mod.sp;
+ #elif defined(VGA_ppc32)
+ sp = user_mod.regs.gpr[1];
+-#elif defined(VGA_ppc64)
++#elif defined(VGA_ppc64be) || defined(VGA_ppc64le)
+ sp = user_mod.regs.gpr[1];
+ #elif defined(VGA_s390x)
+ sp = user_mod.regs.gprs[15];
+@@ -907,7 +907,7 @@ Bool invoker_invoke_gdbserver (pid_t pid)
+ I_die_here : not x86 or amd64 in x86/amd64 section/
+ #endif
+
+-#elif defined(VGA_ppc32) || defined(VGA_ppc64)
++#elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le)
+ user_mod.regs.nip = shared32->invoke_gdbserver;
+ user_mod.regs.trap = -1L;
+ /* put check arg in register 3 */
+@@ -984,7 +984,7 @@ Bool invoker_invoke_gdbserver (pid_t pid)
+
+ #elif defined(VGA_ppc32)
+ assert(0); // cannot vgdb a 64 bits executable with a 32 bits exe
+-#elif defined(VGA_ppc64)
++#elif defined(VGA_ppc64be)
+ Addr64 func_addr;
+ Addr64 toc_addr;
+ int rw;
+diff --git a/drd/drd_bitmap.h b/drd/drd_bitmap.h
+index 939afe4..86d53f3 100644
+--- a/drd/drd_bitmap.h
++++ b/drd/drd_bitmap.h
+@@ -139,8 +139,8 @@ Addr make_address(const UWord a1, const UWord a0)
+ #if defined(VGA_x86) || defined(VGA_ppc32) || defined(VGA_arm) \
+ || defined(VGA_mips32)
+ #define BITS_PER_BITS_PER_UWORD 5
+-#elif defined(VGA_amd64) || defined(VGA_ppc64) || defined(VGA_s390x) \
+- || defined(VGA_mips64) || defined(VGA_arm64)
++#elif defined(VGA_amd64) || defined(VGA_ppc64be) || defined(VGA_ppc64le) \
++ || defined(VGA_s390x) || defined(VGA_mips64) || defined(VGA_arm64)
+ #define BITS_PER_BITS_PER_UWORD 6
+ #else
+ #error Unknown platform.
+diff --git a/drd/drd_load_store.c b/drd/drd_load_store.c
+index 59c2e36..973bdda 100644
+--- a/drd/drd_load_store.c
++++ b/drd/drd_load_store.c
+@@ -43,7 +43,7 @@
+ #define STACK_POINTER_OFFSET OFFSET_amd64_RSP
+ #elif defined(VGA_ppc32)
+ #define STACK_POINTER_OFFSET OFFSET_ppc32_GPR1
+-#elif defined(VGA_ppc64)
++#elif defined(VGA_ppc64be) || defined(VGA_ppc64le)
+ #define STACK_POINTER_OFFSET OFFSET_ppc64_GPR1
+ #elif defined(VGA_arm)
+ #define STACK_POINTER_OFFSET OFFSET_arm_R13
+diff --git a/drd/tests/unit_bitmap.c b/drd/tests/unit_bitmap.c
+index e537e6d..6e8064a 100644
+--- a/drd/tests/unit_bitmap.c
++++ b/drd/tests/unit_bitmap.c
+@@ -83,7 +83,8 @@ struct { Addr address; SizeT size; BmAccessTypeT access_type; }
+ { 0x00ffffffULL, 1, eLoad },
+ { 0xffffffffULL - (((1 << ADDR_LSB_BITS) + 1) << ADDR_IGNORED_BITS),
+ 1, eStore },
+-#if defined(VGP_amd64_linux) || defined(VGP_ppc64_linux)
++#if defined(VGP_amd64_linux) || defined(VGP_ppc64be_linux) \
++ || defined(VGP_ppc64le_linux)
+ { 0xffffffffULL - (1 << ADDR_LSB_BITS << ADDR_IGNORED_BITS),
+ 1, eStore },
+ { 0xffffffffULL, 1, eStore },
+diff --git a/helgrind/tests/annotate_hbefore.c b/helgrind/tests/annotate_hbefore.c
+index 3368c56..74cf9d8 100644
+--- a/helgrind/tests/annotate_hbefore.c
++++ b/helgrind/tests/annotate_hbefore.c
+@@ -20,7 +20,7 @@
+
+ typedef unsigned long int UWord;
+
+-#if defined(VGA_ppc64)
++#if defined(VGA_ppc64be) || defined(VGA_ppc64le)
+
+ // ppc64
+ /* return 1 if success, 0 if failure */
+diff --git a/include/pub_tool_basics.h b/include/pub_tool_basics.h
+index 2236d00..4e30160 100644
+--- a/include/pub_tool_basics.h
++++ b/include/pub_tool_basics.h
+@@ -270,9 +270,9 @@ static inline Bool sr_EQ ( SysRes sr1, SysRes sr2 ) {
+
+ #if defined(VGA_x86) || defined(VGA_amd64) || defined (VGA_arm) \
+ || ((defined(VGA_mips32) || defined(VGA_mips64)) && defined (_MIPSEL)) \
+- || defined(VGA_arm64)
++ || defined(VGA_arm64) || defined(VGA_ppc64le)
+ # define VG_LITTLEENDIAN 1
+-#elif defined(VGA_ppc32) || defined(VGA_ppc64) || defined(VGA_s390x) \
++#elif defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_s390x) \
+ || ((defined(VGA_mips32) || defined(VGA_mips64)) && defined (_MIPSEB))
+ # define VG_BIGENDIAN 1
+ #else
+@@ -283,7 +283,8 @@ static inline Bool sr_EQ ( SysRes sr1, SysRes sr2 ) {
+ #if defined(VGA_x86)
+ # define VG_REGPARM(n) __attribute__((regparm(n)))
+ #elif defined(VGA_amd64) || defined(VGA_ppc32) \
+- || defined(VGA_ppc64) || defined(VGA_arm) || defined(VGA_s390x) \
++ || defined(VGA_ppc64be) || defined(VGA_ppc64le) \
++ || defined(VGA_arm) || defined(VGA_s390x) \
+ || defined(VGA_mips32) || defined(VGA_mips64) \
+ || defined(VGA_arm64)
+ # define VG_REGPARM(n) /* */
+diff --git a/include/pub_tool_libcsetjmp.h b/include/pub_tool_libcsetjmp.h
+index 4bd3270..ff01058 100644
+--- a/include/pub_tool_libcsetjmp.h
++++ b/include/pub_tool_libcsetjmp.h
+@@ -82,7 +82,7 @@ __attribute__((noreturn))
+ void VG_MINIMAL_LONGJMP(VG_MINIMAL_JMP_BUF(_env));
+
+
+-#elif defined(VGP_ppc64_linux)
++#elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
+
+ #define VG_MINIMAL_JMP_BUF(_name) ULong _name [32+1+1]
+ __attribute__((returns_twice))
+diff --git a/include/pub_tool_machine.h b/include/pub_tool_machine.h
+index e956419..0f004f1 100644
+--- a/include/pub_tool_machine.h
++++ b/include/pub_tool_machine.h
+@@ -53,7 +53,7 @@
+ # define VG_CLREQ_SZB 20
+ # define VG_STACK_REDZONE_SZB 0
+
+-#elif defined(VGP_ppc64_linux)
++#elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
+ # define VG_MIN_INSTR_SZB 4
+ # define VG_MAX_INSTR_SZB 4
+ # define VG_CLREQ_SZB 20
+diff --git a/include/pub_tool_vkiscnums_asm.h b/include/pub_tool_vkiscnums_asm.h
+index 6f84651..7f7f03e 100644
+--- a/include/pub_tool_vkiscnums_asm.h
++++ b/include/pub_tool_vkiscnums_asm.h
+@@ -42,7 +42,7 @@
+ #elif defined(VGP_ppc32_linux)
+ # include "vki/vki-scnums-ppc32-linux.h"
+
+-#elif defined(VGP_ppc64_linux)
++#elif defined(VGP_ppc64be_linux) || defined(VGP_ppc64le_linux)
+ # include "vki/vki-scnums-ppc64-linux.h"
+
+ #elif defined(VGP_s390x_linux)
+diff --git a/include/valgrind.h b/include/valgrind.h
+index a4380d1..01a372b 100644
+--- a/include/valgrind.h
++++ b/include/valgrind.h
+@@ -115,7 +115,7 @@
+ #undef PLAT_x86_linux
+ #undef PLAT_amd64_linux
+ #undef PLAT_ppc32_linux
+-#undef PLAT_ppc64_linux
++#undef PLAT_ppc64be_linux
+ #undef PLAT_arm_linux
+ #undef PLAT_arm64_linux
+ #undef PLAT_s390x_linux
+@@ -140,8 +140,9 @@
+ # define PLAT_amd64_linux 1
+ #elif defined(__linux__) && defined(__powerpc__) && !defined(__powerpc64__)
+ # define PLAT_ppc32_linux 1
+-#elif defined(__linux__) && defined(__powerpc__) && defined(__powerpc64__)
+-# define PLAT_ppc64_linux 1
++#elif defined(__linux__) && defined(__powerpc__) && defined(__powerpc64__) && _CALL_ELF != 2
++/* Big Endian uses ELF version 1 */
++# define PLAT_ppc64be_linux 1
+ #elif defined(__linux__) && defined(__arm__) && !defined(__aarch64__)
+ # define PLAT_arm_linux 1
+ #elif defined(__linux__) && defined(__aarch64__) && !defined(__arm__)
+@@ -519,9 +520,9 @@ typedef
+
+ #endif /* PLAT_ppc32_linux */
+
+-/* ------------------------ ppc64-linux ------------------------ */
++/* ---------------------- ppc64be-linux ------------------------ */
+
+-#if defined(PLAT_ppc64_linux)
++#if defined(PLAT_ppc64be_linux)
+
+ typedef
+ struct {
+@@ -596,7 +597,8 @@ typedef
+ ); \
+ } while (0)
+
+-#endif /* PLAT_ppc64_linux */
++#endif /* PLAT_ppc64be_linux */
++
+
+ /* ------------------------- arm-linux ------------------------- */
+
+@@ -2534,9 +2536,9 @@ typedef
+
+ #endif /* PLAT_ppc32_linux */
+
+-/* ------------------------ ppc64-linux ------------------------ */
++/* ---------------------- ppc64be-linux ------------------------ */
+
+-#if defined(PLAT_ppc64_linux)
++#if defined(PLAT_ppc64be_linux)
+
+ /* ARGREGS: r3 r4 r5 r6 r7 r8 r9 r10 (the rest on stack somewhere) */
+
+@@ -3089,7 +3091,7 @@ typedef
+ lval = (__typeof__(lval)) _res; \
+ } while (0)
+
+-#endif /* PLAT_ppc64_linux */
++#endif /* PLAT_ppc64be_linux */
+
+ /* ------------------------- arm-linux ------------------------- */
+
+@@ -5935,7 +5937,7 @@ VALGRIND_PRINTF_BACKTRACE(const char *format, ...)
+ #undef PLAT_x86_linux
+ #undef PLAT_amd64_linux
+ #undef PLAT_ppc32_linux
+-#undef PLAT_ppc64_linux
++#undef PLAT_ppc64be_linux
+ #undef PLAT_arm_linux
+ #undef PLAT_s390x_linux
+ #undef PLAT_mips32_linux
+diff --git a/include/vki/vki-linux.h b/include/vki/vki-linux.h
+index 6043842..9111e0f 100644
+--- a/include/vki/vki-linux.h
++++ b/include/vki/vki-linux.h
+@@ -85,7 +85,7 @@
+ # include "vki-posixtypes-amd64-linux.h"
+ #elif defined(VGA_ppc32)
+ # include "vki-posixtypes-ppc32-linux.h"
+-#elif defined(VGA_ppc64)
++#elif defined(VGA_ppc64be) || defined(VGA_ppc64le)
+ # include "vki-posixtypes-ppc64-linux.h"
+ #elif defined(VGA_arm)
+ # include "vki-posixtypes-arm-linux.h"
+@@ -211,7 +211,7 @@ typedef unsigned int vki_uint;
+ # include "vki-amd64-linux.h"
+ #elif defined(VGA_ppc32)
+ # include "vki-ppc32-linux.h"
+-#elif defined(VGA_ppc64)
++#elif defined(VGA_ppc64be) || defined(VGA_ppc64le)
+ # include "vki-ppc64-linux.h"
+ #elif defined(VGA_arm)
+ # include "vki-arm-linux.h"
+diff --git a/memcheck/mc_machine.c b/memcheck/mc_machine.c
+index 7074107..ccb431f 100644
+--- a/memcheck/mc_machine.c
++++ b/memcheck/mc_machine.c
+@@ -61,7 +61,7 @@
+ # define MC_SIZEOF_GUEST_STATE sizeof(VexGuestPPC32State)
+ #endif
+
+-#if defined(VGA_ppc64)
++#if defined(VGA_ppc64be) || defined(VGA_ppc64le)
+ # include "libvex_guest_ppc64.h"
+ # define MC_SIZEOF_GUEST_STATE sizeof(VexGuestPPC64State)
+ #endif
+@@ -150,7 +150,7 @@ static Int get_otrack_shadow_offset_wrk ( Int offset, Int szB )
+ {
+ /* -------------------- ppc64 -------------------- */
+
+-# if defined(VGA_ppc64)
++# if defined(VGA_ppc64be) || defined(VGA_ppc64le)
+
+ # define GOF(_fieldname) \
+ (offsetof(VexGuestPPC64State,guest_##_fieldname))
+@@ -160,7 +160,6 @@ static Int get_otrack_shadow_offset_wrk ( Int offset, Int szB )
+ Int sz = szB;
+ Int o = offset;
+ tl_assert(sz > 0);
+- tl_assert(host_is_big_endian());
+
+ if (sz == 8 || sz == 4) {
+ /* The point of this is to achieve
+@@ -1282,7 +1281,7 @@ static Int get_otrack_shadow_offset_wrk ( Int offset, Int szB )
+ IRType MC_(get_otrack_reg_array_equiv_int_type) ( IRRegArray* arr )
+ {
+ /* -------------------- ppc64 -------------------- */
+-# if defined(VGA_ppc64)
++# if defined(VGA_ppc64be) || defined(VGA_ppc64le)
+ /* The redir stack. */
+ if (arr->base == offsetof(VexGuestPPC64State,guest_REDIR_STACK[0])
+ && arr->elemTy == Ity_I64
+diff --git a/memcheck/tests/atomic_incs.c b/memcheck/tests/atomic_incs.c
+index 50c29e9..0029d8c 100644
+--- a/memcheck/tests/atomic_incs.c
++++ b/memcheck/tests/atomic_incs.c
+@@ -62,7 +62,7 @@ __attribute__((noinline)) void atomic_add_8bit ( char* p, int n )
+ : /*trash*/ "memory", "cc", "r15"
+ );
+ } while (success != 1);
+-#elif defined(VGA_ppc64)
++#elif defined(VGA_ppc64be)
+ /* Nasty hack. Does correctly atomically do *p += n, but only if p
+ is 8-aligned -- guaranteed by caller. */
+ unsigned long success;
+@@ -261,7 +261,7 @@ __attribute__((noinline)) void atomic_add_16bit ( short* p, int n )
+ : /*trash*/ "memory", "cc", "r15"
+ );
+ } while (success != 1);
+-#elif defined(VGA_ppc64)
++#elif defined(VGA_ppc64be)
+ /* Nasty hack. Does correctly atomically do *p += n, but only if p
+ is 8-aligned -- guaranteed by caller. */
+ unsigned long success;
+@@ -457,7 +457,7 @@ __attribute__((noinline)) void atomic_add_32bit ( int* p, int n )
+ : /*trash*/ "memory", "cc", "r15"
+ );
+ } while (success != 1);
+-#elif defined(VGA_ppc64)
++#elif defined(VGA_ppc64be)
+ /* Nasty hack. Does correctly atomically do *p += n, but only if p
+ is 8-aligned -- guaranteed by caller. */
+ unsigned long success;
+@@ -574,7 +574,7 @@ __attribute__((noinline)) void atomic_add_64bit ( long long int* p, int n )
+ "lock; addq %%rbx,(%%rax)" "\n"
+ : : "S"(&block[0])/* S means "rsi only" */ : "memory","cc","rax","rbx"
+ );
+-#elif defined(VGA_ppc64)
++#elif defined(VGA_ppc64be) || defined(VGA_ppc64le)
+ unsigned long success;
+ do {
+ __asm__ __volatile__(
+diff --git a/memcheck/tests/unit_libcbase.c b/memcheck/tests/unit_libcbase.c
+index 019b67a..d61ecf9 100644
+--- a/memcheck/tests/unit_libcbase.c
++++ b/memcheck/tests/unit_libcbase.c
+@@ -56,7 +56,8 @@ void test_VG_STREQN(void)
+ }
+
+ // On PPC/Linux VKI_PAGE_SIZE is a variable, not a macro.
+-#if defined(VGP_ppc32_linux) || defined(VGP_ppc64_linux)
++#if defined(VGP_ppc32_linux) || defined(VGP_ppc64be_linux) \
++ || defined(VGP_ppc64le_linux)
+ unsigned long VKI_PAGE_SIZE = 1UL << 12;
+ #elif defined(VGP_arm64_linux)
+ unsigned long VKI_PAGE_SIZE = 1UL << 16;
+diff --git a/tests/Makefile.am b/tests/Makefile.am
+index adfbec4..b01cfb7 100644
+--- a/tests/Makefile.am
++++ b/tests/Makefile.am
+@@ -31,7 +31,8 @@ check_PROGRAMS = \
+ x86_amd64_features \
+ s390x_features \
+ mips_features \
+- power_insn_available
++ power_insn_available \
++ is_ppc64_BE
+
+ AM_CFLAGS += $(AM_FLAG_M3264_PRI)
+ AM_CXXFLAGS += $(AM_FLAG_M3264_PRI)
+diff --git a/tests/arch_test.c b/tests/arch_test.c
+index d1a337b..2fa3b48 100644
+--- a/tests/arch_test.c
++++ b/tests/arch_test.c
+@@ -48,7 +48,7 @@ static Bool go(char* arch)
+ #elif defined(VGP_ppc32_linux)
+ if ( 0 == strcmp( arch, "ppc32" ) ) return True;
+
+-#elif defined(VGP_ppc64_linux)
++#elif defined(VGP_ppc64be_linux)
+ if ( 0 == strcmp( arch, "ppc64" ) ) return True;
+ #if defined(VGA_SEC_ppc32)
+ if ( 0 == strcmp( arch, "ppc32" ) ) return True;
+diff --git a/tests/check_isa-2_06_cap b/tests/check_isa-2_06_cap
+index c5fc05a..b8ec37f 100755
+--- a/tests/check_isa-2_06_cap
++++ b/tests/check_isa-2_06_cap
+@@ -1,7 +1,7 @@
+ #!/bin/sh
+
+ # We use this script to check whether or not the processor supports Power ISA 2.06 or later.
+-DIR="$( cd "$( dirname "${BASH_SOURCE[0]}" )" && pwd )"
++DIR="$( cd "$( dirname "$0" )" && pwd )"
+ LD_SHOW_AUXV=1 $DIR/true | grep arch_2_06 > /dev/null 2>&1
+
+ if [ "$?" -ne "0" ]; then
+diff --git a/tests/check_isa-2_07_cap b/tests/check_isa-2_07_cap
+index ee777c1..8b991e5 100755
+--- a/tests/check_isa-2_07_cap
++++ b/tests/check_isa-2_07_cap
+@@ -2,7 +2,7 @@
+
+ # We use this script to check whether or not the processor supports
+ # Power ISA 2.07.
+-DIR="$( cd "$( dirname "${BASH_SOURCE[0]}" )" && pwd )"
++DIR="$( cd "$( dirname "$0" )" && pwd )"
+ LD_SHOW_AUXV=1 $DIR/true | grep arch_2_07 > /dev/null 2>&1
+
+ if [ "$?" -ne "0" ]; then
+diff --git a/tests/is_ppc64_BE.c b/tests/is_ppc64_BE.c
+new file mode 100644
+index 0000000..6c12fb3
+--- /dev/null
++++ b/tests/is_ppc64_BE.c
+@@ -0,0 +1,14 @@
++#include <stdio.h>
++#include <stdlib.h>
++#include <string.h>
++
++// This program returns 0 if executing on ppc64 big endian; otherwise returns 1
++
++int main(void)
++{
++#if defined(VGP_ppc64be_linux)
++ return 0;
++#else
++ return 1;
++#endif
++}
+diff --git a/tests/power_insn_available.c b/tests/power_insn_available.c
+index 1bfea2a..1c53918 100644
+--- a/tests/power_insn_available.c
++++ b/tests/power_insn_available.c
+@@ -7,7 +7,7 @@
+
+ typedef enum exit_codes_ {
+
+-#if defined(VGA_ppc32) || defined(VGA_ppc64)
++#if defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le)
+ /* If the insn that got queried for: exists */
+ POWER_INSN_AVAILABLE = 0,
+ /* If the insn that got queried for: does not exist on this platform */
+@@ -24,7 +24,7 @@ typedef enum exit_codes_ {
+
+ } exit_code;
+
+-#if defined(VGA_ppc32) || defined(VGA_ppc64)
++#if defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le)
+ /* Signal Handling support for unsupported instructions. */
+ static jmp_buf unsup_insn_env;
+ static void unsup_insn_handler(int signal_number)
+@@ -72,7 +72,7 @@ int main(int argc, char **argv)
+ {
+ exit_code status;
+
+-#if defined(VGA_ppc32) || defined(VGA_ppc64)
++#if defined(VGA_ppc32) || defined(VGA_ppc64be) || defined(VGA_ppc64le)
+ char *insn;
+ if (argc != 2) {
+ fprintf(stderr, "usage: power_insn_available <insn>\n" );
+--
+1.8.4.2
+
diff --git a/valgrind-3.9.0-ppc64le-test.patch b/valgrind-3.9.0-ppc64le-test.patch
new file mode 100644
index 0000000..c0719c1
--- /dev/null
+++ b/valgrind-3.9.0-ppc64le-test.patch
@@ -0,0 +1,25843 @@
+From fa7cc53e455f86e7d47dc67500219996b054e41e Mon Sep 17 00:00:00 2001
+From: Carl Love <carll at us.ibm.com>
+Date: Mon, 2 Jun 2014 11:10:27 -0500
+Subject: [PATCH 3/3] PP64 Little Endian test case fixes.
+
+This patch adds new LE and BE expect files where needed. In other
+cases, the test was fixed to run correctly on LE and BE using based on
+testing to see which platform is being used.
+
+Signed-off-by: Carl Love <carll at us.ibm.com>
+---
+ memcheck/tests/atomic_incs.c | 108 +-
+ memcheck/tests/badjump.c | 2 +-
+ memcheck/tests/ppc64/power_ISA2_05.c | 29 +-
+ memcheck/tests/ppc64/power_ISA2_05.stdout.exp | 6 +-
+ none/tests/ppc32/Makefile.am | 36 +-
+ none/tests/ppc32/jm-fp.stdout.exp-BE2 | 1431 ++++++
+ none/tests/ppc32/jm-insns.c | 61 +-
+ none/tests/ppc32/jm-int.stdout.exp | 80 +-
+ none/tests/ppc32/jm-vmx.stdout.exp | 154 +-
+ none/tests/ppc32/jm_vec_isa_2_07.stdout.exp | 4 +-
+ none/tests/ppc32/ldst_multiple.c | 2 +-
+ none/tests/ppc32/round.stdout.exp | 532 +--
+ none/tests/ppc32/round.stdout.exp-RM-fix | 2335 ++++++++++
+ none/tests/ppc32/test_dfp4.c | 28 +-
+ none/tests/ppc32/test_dfp5.c | 47 +-
+ none/tests/ppc32/test_isa_2_06_part1.c | 1355 +++---
+ none/tests/ppc32/test_isa_2_06_part1.stdout.exp | 23 +-
+ none/tests/ppc32/test_isa_2_06_part2.c | 68 +-
+ none/tests/ppc32/test_isa_2_06_part3.c | 76 +-
+ none/tests/ppc32/test_isa_2_07_part2.stdout.exp | 96 +-
+ none/tests/ppc64/Makefile.am | 44 +-
+ none/tests/ppc64/jm-fp.stdout.exp | 128 +-
+ none/tests/ppc64/jm-fp.stdout.exp-BE2 | 1533 +++++++
+ none/tests/ppc64/jm-fp.stdout.exp-LE | 1533 +++++++
+ none/tests/ppc64/jm-fp.stdout.exp-LE2 | 1533 +++++++
+ none/tests/ppc64/jm-int.stdout.exp | 110 +-
+ none/tests/ppc64/jm-int.stdout.exp-LE | 4773 ++++++++++++++++++++
+ none/tests/ppc64/jm-vmx.stdout.exp | 154 +-
+ none/tests/ppc64/jm-vmx.stdout.exp-LE | 3614 +++++++++++++++
+ none/tests/ppc64/jm_vec_isa_2_07.stdout.exp | 4 +-
+ none/tests/ppc64/lsw.vgtest | 1 +
+ none/tests/ppc64/round.c | 15 +-
+ none/tests/ppc64/round.stdout.exp-RM-fix | 2384 ++++++++++
+ none/tests/ppc64/std_reg_imm.stdout.exp-LE | 1 +
+ none/tests/ppc64/test_isa_2_06_part1.stdout.exp | 29 +-
+ none/tests/ppc64/test_isa_2_06_part1.stdout.exp-LE | 1044 +++++
+ none/tests/ppc64/test_isa_2_07_part1.c | 165 +-
+ none/tests/ppc64/test_isa_2_07_part2.c | 300 +-
+ none/tests/ppc64/test_isa_2_07_part2.stdout.exp | 96 +-
+ tests/Makefile.am | 3 +-
+ tests/check_isa-2_06_cap | 2 +-
+ tests/check_isa-2_07_cap | 2 +-
+ tests/is_ppc64_BE.c | 15 +
+ tests/power_insn_available.c | 6 +-
+ 44 files changed, 22209 insertions(+), 1753 deletions(-)
+ create mode 100644 none/tests/ppc32/jm-fp.stdout.exp-BE2
+ create mode 100644 none/tests/ppc32/round.stdout.exp-RM-fix
+ create mode 100644 none/tests/ppc64/jm-fp.stdout.exp-BE2
+ create mode 100644 none/tests/ppc64/jm-fp.stdout.exp-LE
+ create mode 100644 none/tests/ppc64/jm-fp.stdout.exp-LE2
+ create mode 100644 none/tests/ppc64/jm-int.stdout.exp-LE
+ create mode 100644 none/tests/ppc64/jm-vmx.stdout.exp-LE
+ create mode 100644 none/tests/ppc64/round.stdout.exp-RM-fix
+ create mode 100644 none/tests/ppc64/std_reg_imm.stdout.exp-LE
+ create mode 100644 none/tests/ppc64/test_isa_2_06_part1.stdout.exp-LE
+ create mode 100644 tests/is_ppc64_BE.c
+
+diff --git a/memcheck/tests/badjump.c b/memcheck/tests/badjump.c
+index 9cf5267..923635f 100644
+--- a/memcheck/tests/badjump.c
++++ b/memcheck/tests/badjump.c
+@@ -2,7 +2,7 @@
+
+ int main ( void )
+ {
+-#if defined(__powerpc64__)
++#if defined(__powerpc64__) && _CALL_ELF != 2
+ /* on ppc64-linux, a function pointer points to a function
+ descriptor, not to the function's entry point. Hence to get
+ uniform behaviour on all supported targets - a jump to an
+diff --git a/memcheck/tests/ppc64/power_ISA2_05.c b/memcheck/tests/ppc64/power_ISA2_05.c
+index f552dc4..5583d35 100644
+--- a/memcheck/tests/ppc64/power_ISA2_05.c
++++ b/memcheck/tests/ppc64/power_ISA2_05.c
+@@ -41,19 +41,25 @@ void test_parity_instrs()
+ void test_lfiwax()
+ {
+ unsigned long base;
++ float foo_s;
+
+ typedef struct {
++#if defined(VGP_ppc64le_linux)
++ unsigned int lo;
++ unsigned int hi;
++#else
+ unsigned int hi;
+ unsigned int lo;
++#endif
+ } int_pair_t;
+
+ int_pair_t *ip;
+- foo = -1024.0;
+- base = (unsigned long) &foo;
++ foo_s = -1024.0;
++ base = (unsigned long) &foo_s;
+
+ __asm__ volatile ("lfiwax %0, 0, %1":"=f" (FRT1):"r"(base));
+ ip = (int_pair_t *) & FRT1;
+- printf("lfiwax (%f) => FRT=(%x, %x)\n", foo, ip->hi, ip->lo);
++ printf("lfiwax (%f) => FRT=(%x, %x)\n", foo_s, ip->hi, ip->lo);
+
+
+ }
+@@ -167,24 +173,27 @@ void test_fcpsgn()
+ void test_reservation()
+ {
+
+- int RT;
++ unsigned long long RT;
+ unsigned long base;
+ unsigned long offset;
+- long arr[4] = { 0xdeadbeef, 0xbad0beef, 0xbeefdead, 0xbeef0bad };
++ long arrL[] __attribute__ ((aligned (8))) = { 0xdeadbeef00112233ULL, 0xbad0beef44556677ULL, 0xbeefdead8899aabbULL, 0xbeef0badccddeeffULL };
++ int arrI[] __attribute__ ((aligned (4))) = { 0xdeadbeef, 0xbad0beef, 0xbeefdead, 0xbeef0bad };
+
+
+- base = (unsigned long) &arr;
+- offset = (unsigned long) &arr[1] - base;
++ base = (unsigned long) &arrI;
++ offset = ((unsigned long) &arrI[1]) - base;
+ __asm__ volatile ("ori 20, %0, 0"::"r" (base));
+ __asm__ volatile ("ori 21, %0, 0"::"r" (offset));
+ __asm__ volatile ("lwarx %0, 20, 21, 1":"=r" (RT));
+- printf("lwarx => %x\n", RT);
++ printf("lwarx => 0x%llx\n", RT);
+
+ #ifdef __powerpc64__
+- offset = (unsigned long) &arr[1] - base;
++ base = (unsigned long) &arrL;
++ offset = ((unsigned long) &arrL[1]) - base;
++ __asm__ volatile ("ori 20, %0, 0"::"r" (base));
+ __asm__ volatile ("ori 21, %0, 0"::"r" (offset));
+ __asm__ volatile ("ldarx %0, 20, 21, 1":"=r" (RT));
+- printf("ldarx => %x\n", RT);
++ printf("ldarx => 0x%llx\n", RT);
+ #endif
+
+ }
+diff --git a/memcheck/tests/ppc64/power_ISA2_05.stdout.exp b/memcheck/tests/ppc64/power_ISA2_05.stdout.exp
+index 3297838..a87e75b 100644
+--- a/memcheck/tests/ppc64/power_ISA2_05.stdout.exp
++++ b/memcheck/tests/ppc64/power_ISA2_05.stdout.exp
+@@ -1,5 +1,5 @@
+-lwarx => 0
+-ldarx => bad0beef
++lwarx => 0xbad0beef
++ldarx => 0xbad0beef44556677
+ fcpsgn sign=10.101010, base=11.111111 => 11.111111
+ fcpsgn sign=10.101010, base=-0.000000 => 0.000000
+ fcpsgn sign=10.101010, base=0.000000 => 0.000000
+@@ -20,7 +20,7 @@ lfdp (-1024.000000, 1025.000000) => F_hi=-1024.000000, F_lo=1025.000000
+ stfdp (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400
+ lfdpx (2.204800, -4.102400) => F_hi=2.204800, F_lo=-4.102400
+ stfdpx (2.204800, 2.204800) => F_hi=2.204800, F_lo=2.204800
+-lfiwax (-1024.000000) => FRT=(ffffffff, c0900000)
++lfiwax (-1024.000000) => FRT=(ffffffff, c4800000)
+ prtyd (0) => parity=0
+ prtyw (0) => parity=0
+ prtyd (1) => parity=1
+diff --git a/none/tests/ppc32/Makefile.am b/none/tests/ppc32/Makefile.am
+index 5b3fef9..6aa63d5 100644
+--- a/none/tests/ppc32/Makefile.am
++++ b/none/tests/ppc32/Makefile.am
+@@ -11,13 +11,13 @@ EXTRA_DIST = \
+ ldstrev.stderr.exp ldstrev.stdout.exp ldstrev.vgtest \
+ lsw.stderr.exp lsw.stdout.exp lsw.vgtest \
+ jm-int.stderr.exp jm-int.stdout.exp jm-int.vgtest \
+- jm-fp.stderr.exp jm-fp.stdout.exp jm-fp.vgtest \
++ jm-fp.stderr.exp jm-fp.stdout.exp jm-fp.vgtest jm-fp.stdout.exp-BE2 \
+ jm-vmx.stderr.exp jm-vmx.stdout.exp jm-vmx.stdout.exp_Minus_nan \
+ jm-vmx.vgtest \
+ jm-misc.stderr.exp jm-misc.stdout.exp jm-misc.vgtest \
+ mftocrf.stderr.exp mftocrf.stdout.exp mftocrf.vgtest \
+ mcrfs.stderr.exp mcrfs.stdout.exp mcrfs.vgtest \
+- round.stderr.exp round.stdout.exp round.vgtest \
++ round.stderr.exp round.stdout.exp round.vgtest round.stdout.exp-RM-fix\
+ test_fx.stderr.exp test_fx.stdout.exp test_fx.stdout.exp_Minus_nan \
+ test_fx.vgtest \
+ test_gx.stderr.exp test_gx.stdout.exp test_gx.stdout.exp_Minus_nan \
+@@ -113,29 +113,41 @@ test_isa_2_06_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_
+ test_isa_2_06_part2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) \
+ @FLAG_M32@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX)
+
+-test_isa_2_06_part3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(VSX_FLAG) \
++test_isa_2_06_part3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) \
+ @FLAG_M32@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX)
+
+-test_dfp1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
++test_dfp1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
+ @FLAG_M32@ $(BUILD_FLAGS_DFP)
+-test_dfp2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
++test_dfp2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
+ @FLAG_M32@ $(BUILD_FLAGS_DFP)
+-test_dfp3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
++test_dfp3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
+ @FLAG_M32@ $(BUILD_FLAGS_DFP)
+
+-test_dfp4_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
++test_dfp4_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
+ @FLAG_M32@ $(BUILD_FLAGS_DFP)
+
+-test_dfp5_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
++test_dfp5_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
+ @FLAG_M32@ $(BUILD_FLAGS_DFP)
+
+-test_isa_2_07_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \
++test_isa_2_07_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_2_07_FLAG) \
+ @FLAG_M32@ $(BUILD_FLAGS_ISA_2_07)
+
+-test_isa_2_07_part2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \
++test_isa_2_07_part2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_2_07_FLAG) \
+ @FLAG_M32@ $(BUILD_FLAGS_ISA_2_07)
+
+-test_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \
++test_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_2_07_FLAG) \
+ @FLAG_M32@ $(BUILD_FLAGS_ISA_2_07)
+-test_touch_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \
++test_touch_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_2_07_FLAG) \
+ @FLAG_M32@ $(BUILD_FLAGS_ISA_2_07)
++
++test_isa_2_06_part3_LDADD = -lm
++test_dfp1_LDADD = -lm
++test_dfp2_LDADD = -lm
++test_dfp3_LDADD = -lm
++test_dfp4_LDADD = -lm
++test_dfp5_LDADD = -lm
++test_isa_2_07_part1_LDADD = -lm
++test_isa_2_07_part2_LDADD = -lm
++test_tm_LDADD = -lm
++test_touch_tm_LDADD = -lm
++
+diff --git a/none/tests/ppc32/jm-fp.stdout.exp-BE2 b/none/tests/ppc32/jm-fp.stdout.exp-BE2
+new file mode 100644
+index 0000000..cced224
+--- /dev/null
++++ b/none/tests/ppc32/jm-fp.stdout.exp-BE2
+@@ -0,0 +1,1431 @@
++PPC floating point arith insns with three args:
++ fsel 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
++ fsel 0010000000000001, 0010000000000001, bfe00094e0000359 => 0010000000000000
++ fsel 0010000000000001, 80100094e0000359, 0010000000000001 => 80100094e0000300
++ fsel 0010000000000001, 80100094e0000359, bfe00094e0000359 => 80100094e0000300
++ fsel 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0010000000000000
++ fsel 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 0010000000000000
++ fsel 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80100094e0000300
++ fsel 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 80100094e0000300
++ fsel bfe0000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
++ fsel bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fsel bfe0000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
++ fsel bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++
++ fmadd 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
++ fmadd 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fmadd 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
++ fmadd 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++ fmadd 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0018004a70000100
++ fmadd 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fmadd 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0007ff6b1d4b5e00
++ fmadd 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++ fmadd bfe0000000000001, 0010000000000001, 0010000000000001 => 0008000000000000
++ fmadd bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fmadd bfe0000000000001, 80100094e0000359, 0010000000000001 => 0018004a70000100
++ fmadd bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++
++ fmadds 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
++ fmadds 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fmadds 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fmadds 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++ fmadds 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000
++ fmadds 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fmadds 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fmadds 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++ fmadds bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
++ fmadds bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fmadds bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fmadds bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++
++ fmsub 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000
++ fmsub 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fmsub 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000
++ fmsub 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++ fmsub 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8007ffb58ffffe00
++ fmsub 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fmsub 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80180094e2b4a100
++ fmsub 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++ fmsub bfe0000000000001, 0010000000000001, 0010000000000001 => 8018000000000000
++ fmsub bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fmsub bfe0000000000001, 80100094e0000359, 0010000000000001 => 8007ffb58ffffe00
++ fmsub bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++
++ fmsubs 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
++ fmsubs 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fmsubs 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fmsubs 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++ fmsubs 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000
++ fmsubs 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fmsubs 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fmsubs 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++ fmsubs bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
++ fmsubs bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fmsubs bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fmsubs bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++
++ fnmadd 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000
++ fnmadd 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fnmadd 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000
++ fnmadd 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++ fnmadd 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8018004a70000100
++ fnmadd 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fnmadd 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8007ff6b1d4b5e00
++ fnmadd 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++ fnmadd bfe0000000000001, 0010000000000001, 0010000000000001 => 8008000000000000
++ fnmadd bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fnmadd bfe0000000000001, 80100094e0000359, 0010000000000001 => 8018004a70000100
++ fnmadd bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++
++ fnmadds 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
++ fnmadds 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fnmadds 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fnmadds 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++ fnmadds 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000
++ fnmadds 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fnmadds 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fnmadds 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++ fnmadds bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
++ fnmadds bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fnmadds bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fnmadds bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++
++ fnmsub 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
++ fnmsub 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fnmsub 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
++ fnmsub 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++ fnmsub 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0007ffb58ffffe00
++ fnmsub 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fnmsub 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 00180094e2b4a100
++ fnmsub 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++ fnmsub bfe0000000000001, 0010000000000001, 0010000000000001 => 0018000000000000
++ fnmsub bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fnmsub bfe0000000000001, 80100094e0000359, 0010000000000001 => 0007ffb58ffffe00
++ fnmsub bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++
++ fnmsubs 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
++ fnmsubs 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fnmsubs 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fnmsubs 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++ fnmsubs 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000
++ fnmsubs 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fnmsubs 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fnmsubs 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++ fnmsubs bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
++ fnmsubs bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fnmsubs bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fnmsubs bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++
++PPC floating point arith insns
++ with three args with flags update:
++ fsel. 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
++ fsel. 0010000000000001, 0010000000000001, bfe00094e0000359 => 0010000000000000
++ fsel. 0010000000000001, 80100094e0000359, 0010000000000001 => 80100094e0000300
++ fsel. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 80100094e0000300
++ fsel. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0010000000000000
++ fsel. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 0010000000000000
++ fsel. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80100094e0000300
++ fsel. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 80100094e0000300
++ fsel. bfe0000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
++ fsel. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fsel. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
++ fsel. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++
++ fmadd. 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
++ fmadd. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fmadd. 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
++ fmadd. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++ fmadd. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0018004a70000100
++ fmadd. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fmadd. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0007ff6b1d4b5e00
++ fmadd. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++ fmadd. bfe0000000000001, 0010000000000001, 0010000000000001 => 0008000000000000
++ fmadd. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fmadd. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0018004a70000100
++ fmadd. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++
++ fmadds. 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
++ fmadds. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fmadds. 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fmadds. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++ fmadds. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000
++ fmadds. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fmadds. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fmadds. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++ fmadds. bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
++ fmadds. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fmadds. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fmadds. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++
++ fmsub. 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000
++ fmsub. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fmsub. 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000
++ fmsub. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++ fmsub. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8007ffb58ffffe00
++ fmsub. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fmsub. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80180094e2b4a100
++ fmsub. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++ fmsub. bfe0000000000001, 0010000000000001, 0010000000000001 => 8018000000000000
++ fmsub. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fmsub. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8007ffb58ffffe00
++ fmsub. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++
++ fmsubs. 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
++ fmsubs. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fmsubs. 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fmsubs. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++ fmsubs. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000
++ fmsubs. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fmsubs. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fmsubs. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++ fmsubs. bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
++ fmsubs. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fmsubs. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fmsubs. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++
++ fnmadd. 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000
++ fnmadd. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fnmadd. 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000
++ fnmadd. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++ fnmadd. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8018004a70000100
++ fnmadd. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fnmadd. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8007ff6b1d4b5e00
++ fnmadd. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++ fnmadd. bfe0000000000001, 0010000000000001, 0010000000000001 => 8008000000000000
++ fnmadd. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fnmadd. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8018004a70000100
++ fnmadd. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++
++ fnmadds. 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
++ fnmadds. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fnmadds. 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fnmadds. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++ fnmadds. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000
++ fnmadds. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fnmadds. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fnmadds. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++ fnmadds. bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
++ fnmadds. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fnmadds. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fnmadds. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++
++ fnmsub. 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
++ fnmsub. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fnmsub. 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
++ fnmsub. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++ fnmsub. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0007ffb58ffffe00
++ fnmsub. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fnmsub. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 00180094e2b4a100
++ fnmsub. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++ fnmsub. bfe0000000000001, 0010000000000001, 0010000000000001 => 0018000000000000
++ fnmsub. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fnmsub. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0007ffb58ffffe00
++ fnmsub. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++
++ fnmsubs. 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
++ fnmsubs. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fnmsubs. 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fnmsubs. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++ fnmsubs. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000
++ fnmsubs. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fnmsubs. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fnmsubs. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++ fnmsubs. bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
++ fnmsubs. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fnmsubs. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fnmsubs. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++
++PPC floating point arith insns with two args:
++ fadd 0010000000000001, 0010000000000001 => 0020000000000001
++ fadd 0010000000000001, 80100094e0000359 => 80000094e0000358
++ fadd 0010000000000001, 7ff0000000000000 => 7ff0000000000000
++ fadd 0010000000000001, fff8000000000000 => fff8000000000000
++ fadd 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359
++ fadd 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359
++ fadd 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
++ fadd 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fadd bfe0000000000001, 0010000000000001 => bfe0000000000001
++ fadd bfe0000000000001, 80100094e0000359 => bfe0000000000001
++ fadd bfe0000000000001, 7ff0000000000000 => 7ff0000000000000
++ fadd bfe0000000000001, fff8000000000000 => fff8000000000000
++ fadd 8000000000000000, 0010000000000001 => 0010000000000001
++ fadd 8000000000000000, 80100094e0000359 => 80100094e0000359
++ fadd 8000000000000000, 7ff0000000000000 => 7ff0000000000000
++ fadd 8000000000000000, fff8000000000000 => fff8000000000000
++ fadd 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
++ fadd 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
++ fadd 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
++ fadd 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
++ fadd fff8000000000000, 0010000000000001 => fff8000000000000
++ fadd fff8000000000000, 80100094e0000359 => fff8000000000000
++ fadd fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fadd fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fadds 0010000000000001, 0010000000000001 => 0000000000000000
++ fadds 0010000000000001, 80100094e0000359 => 8000000000000000
++ fadds 0010000000000001, 7ff0000000000000 => 7ff0000000000000
++ fadds 0010000000000001, fff8000000000000 => fff8000000000000
++ fadds 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000
++ fadds 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000
++ fadds 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
++ fadds 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fadds bfe0000000000001, 0010000000000001 => bfe0000000000000
++ fadds bfe0000000000001, 80100094e0000359 => bfe0000000000000
++ fadds bfe0000000000001, 7ff0000000000000 => 7ff0000000000000
++ fadds bfe0000000000001, fff8000000000000 => fff8000000000000
++ fadds 8000000000000000, 0010000000000001 => 0000000000000000
++ fadds 8000000000000000, 80100094e0000359 => 8000000000000000
++ fadds 8000000000000000, 7ff0000000000000 => 7ff0000000000000
++ fadds 8000000000000000, fff8000000000000 => fff8000000000000
++ fadds 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
++ fadds 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
++ fadds 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
++ fadds 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
++ fadds fff8000000000000, 0010000000000001 => fff8000000000000
++ fadds fff8000000000000, 80100094e0000359 => fff8000000000000
++ fadds fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fadds fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fsub 0010000000000001, 0010000000000001 => 0000000000000000
++ fsub 0010000000000001, 80100094e0000359 => 0020004a700001ad
++ fsub 0010000000000001, 7ff0000000000000 => fff0000000000000
++ fsub 0010000000000001, fff8000000000000 => fff8000000000000
++ fsub 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359
++ fsub 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359
++ fsub 3fe00094e0000359, 7ff0000000000000 => fff0000000000000
++ fsub 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fsub bfe0000000000001, 0010000000000001 => bfe0000000000001
++ fsub bfe0000000000001, 80100094e0000359 => bfe0000000000001
++ fsub bfe0000000000001, 7ff0000000000000 => fff0000000000000
++ fsub bfe0000000000001, fff8000000000000 => fff8000000000000
++ fsub 8000000000000000, 0010000000000001 => 8010000000000001
++ fsub 8000000000000000, 80100094e0000359 => 00100094e0000359
++ fsub 8000000000000000, 7ff0000000000000 => fff0000000000000
++ fsub 8000000000000000, fff8000000000000 => fff8000000000000
++ fsub 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
++ fsub 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
++ fsub 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
++ fsub 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
++ fsub fff8000000000000, 0010000000000001 => fff8000000000000
++ fsub fff8000000000000, 80100094e0000359 => fff8000000000000
++ fsub fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fsub fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fsubs 0010000000000001, 0010000000000001 => 0000000000000000
++ fsubs 0010000000000001, 80100094e0000359 => 0000000000000000
++ fsubs 0010000000000001, 7ff0000000000000 => fff0000000000000
++ fsubs 0010000000000001, fff8000000000000 => fff8000000000000
++ fsubs 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000
++ fsubs 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000
++ fsubs 3fe00094e0000359, 7ff0000000000000 => fff0000000000000
++ fsubs 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fsubs bfe0000000000001, 0010000000000001 => bfe0000000000000
++ fsubs bfe0000000000001, 80100094e0000359 => bfe0000000000000
++ fsubs bfe0000000000001, 7ff0000000000000 => fff0000000000000
++ fsubs bfe0000000000001, fff8000000000000 => fff8000000000000
++ fsubs 8000000000000000, 0010000000000001 => 8000000000000000
++ fsubs 8000000000000000, 80100094e0000359 => 0000000000000000
++ fsubs 8000000000000000, 7ff0000000000000 => fff0000000000000
++ fsubs 8000000000000000, fff8000000000000 => fff8000000000000
++ fsubs 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
++ fsubs 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
++ fsubs 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
++ fsubs 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
++ fsubs fff8000000000000, 0010000000000001 => fff8000000000000
++ fsubs fff8000000000000, 80100094e0000359 => fff8000000000000
++ fsubs fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fsubs fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fmul 0010000000000001, 0010000000000001 => 0000000000000000
++ fmul 0010000000000001, 80100094e0000359 => 8000000000000000
++ fmul 0010000000000001, 7ff0000000000000 => 7ff0000000000000
++ fmul 0010000000000001, fff8000000000000 => fff8000000000000
++ fmul 3fe00094e0000359, 0010000000000001 => 0008004a700001ad
++ fmul 3fe00094e0000359, 80100094e0000359 => 80080094e2b4a179
++ fmul 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
++ fmul 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fmul bfe0000000000001, 0010000000000001 => 8008000000000001
++ fmul bfe0000000000001, 80100094e0000359 => 0008004a700001ad
++ fmul bfe0000000000001, 7ff0000000000000 => fff0000000000000
++ fmul bfe0000000000001, fff8000000000000 => fff8000000000000
++ fmul 8000000000000000, 0010000000000001 => 8000000000000000
++ fmul 8000000000000000, 80100094e0000359 => 0000000000000000
++ fmul 8000000000000000, 7ff0000000000000 => 7ff8000000000000
++ fmul 8000000000000000, fff8000000000000 => fff8000000000000
++ fmul 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
++ fmul 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
++ fmul 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
++ fmul 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
++ fmul fff8000000000000, 0010000000000001 => fff8000000000000
++ fmul fff8000000000000, 80100094e0000359 => fff8000000000000
++ fmul fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fmul fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fmuls 0010000000000001, 0010000000000001 => 0000000000000000
++ fmuls 0010000000000001, 80100094e0000359 => 8000000000000000
++ fmuls 0010000000000001, 7ff0000000000000 => 7ff0000000000000
++ fmuls 0010000000000001, fff8000000000000 => fff8000000000000
++ fmuls 3fe00094e0000359, 0010000000000001 => 0000000000000000
++ fmuls 3fe00094e0000359, 80100094e0000359 => 8000000000000000
++ fmuls 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
++ fmuls 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fmuls bfe0000000000001, 0010000000000001 => 8000000000000000
++ fmuls bfe0000000000001, 80100094e0000359 => 0000000000000000
++ fmuls bfe0000000000001, 7ff0000000000000 => fff0000000000000
++ fmuls bfe0000000000001, fff8000000000000 => fff8000000000000
++ fmuls 8000000000000000, 0010000000000001 => 8000000000000000
++ fmuls 8000000000000000, 80100094e0000359 => 0000000000000000
++ fmuls 8000000000000000, 7ff0000000000000 => 7ff8000000000000
++ fmuls 8000000000000000, fff8000000000000 => fff8000000000000
++ fmuls 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
++ fmuls 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
++ fmuls 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
++ fmuls 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
++ fmuls fff8000000000000, 0010000000000001 => fff8000000000000
++ fmuls fff8000000000000, 80100094e0000359 => fff8000000000000
++ fmuls fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fmuls fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fdiv 0010000000000001, 0010000000000001 => 3ff0000000000000
++ fdiv 0010000000000001, 80100094e0000359 => bfeffed64ad20d22
++ fdiv 0010000000000001, 7ff0000000000000 => 0000000000000000
++ fdiv 0010000000000001, fff8000000000000 => fff8000000000000
++ fdiv 3fe00094e0000359, 0010000000000001 => 7fc00094e0000358
++ fdiv 3fe00094e0000359, 80100094e0000359 => ffc0000000000000
++ fdiv 3fe00094e0000359, 7ff0000000000000 => 0000000000000000
++ fdiv 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fdiv bfe0000000000001, 0010000000000001 => ffc0000000000000
++ fdiv bfe0000000000001, 80100094e0000359 => 7fbffed64ad20d22
++ fdiv bfe0000000000001, 7ff0000000000000 => 8000000000000000
++ fdiv bfe0000000000001, fff8000000000000 => fff8000000000000
++ fdiv 8000000000000000, 0010000000000001 => 8000000000000000
++ fdiv 8000000000000000, 80100094e0000359 => 0000000000000000
++ fdiv 8000000000000000, 7ff0000000000000 => 8000000000000000
++ fdiv 8000000000000000, fff8000000000000 => fff8000000000000
++ fdiv 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
++ fdiv 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
++ fdiv 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
++ fdiv 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
++ fdiv fff8000000000000, 0010000000000001 => fff8000000000000
++ fdiv fff8000000000000, 80100094e0000359 => fff8000000000000
++ fdiv fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fdiv fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fdivs 0010000000000001, 0010000000000001 => 3ff0000000000000
++ fdivs 0010000000000001, 80100094e0000359 => bfeffed640000000
++ fdivs 0010000000000001, 7ff0000000000000 => 0000000000000000
++ fdivs 0010000000000001, fff8000000000000 => fff8000000000000
++ fdivs 3fe00094e0000359, 0010000000000001 => 7ff0000000000000
++ fdivs 3fe00094e0000359, 80100094e0000359 => fff0000000000000
++ fdivs 3fe00094e0000359, 7ff0000000000000 => 0000000000000000
++ fdivs 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fdivs bfe0000000000001, 0010000000000001 => fff0000000000000
++ fdivs bfe0000000000001, 80100094e0000359 => 7ff0000000000000
++ fdivs bfe0000000000001, 7ff0000000000000 => 8000000000000000
++ fdivs bfe0000000000001, fff8000000000000 => fff8000000000000
++ fdivs 8000000000000000, 0010000000000001 => 8000000000000000
++ fdivs 8000000000000000, 80100094e0000359 => 0000000000000000
++ fdivs 8000000000000000, 7ff0000000000000 => 8000000000000000
++ fdivs 8000000000000000, fff8000000000000 => fff8000000000000
++ fdivs 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
++ fdivs 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
++ fdivs 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
++ fdivs 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
++ fdivs fff8000000000000, 0010000000000001 => fff8000000000000
++ fdivs fff8000000000000, 80100094e0000359 => fff8000000000000
++ fdivs fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fdivs fff8000000000000, fff8000000000000 => fff8000000000000
++
++PPC floating point arith insns
++ with two args with flags update:
++ fadd. 0010000000000001, 0010000000000001 => 0020000000000001
++ fadd. 0010000000000001, 80100094e0000359 => 80000094e0000358
++ fadd. 0010000000000001, 7ff0000000000000 => 7ff0000000000000
++ fadd. 0010000000000001, fff8000000000000 => fff8000000000000
++ fadd. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359
++ fadd. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359
++ fadd. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
++ fadd. 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fadd. bfe0000000000001, 0010000000000001 => bfe0000000000001
++ fadd. bfe0000000000001, 80100094e0000359 => bfe0000000000001
++ fadd. bfe0000000000001, 7ff0000000000000 => 7ff0000000000000
++ fadd. bfe0000000000001, fff8000000000000 => fff8000000000000
++ fadd. 8000000000000000, 0010000000000001 => 0010000000000001
++ fadd. 8000000000000000, 80100094e0000359 => 80100094e0000359
++ fadd. 8000000000000000, 7ff0000000000000 => 7ff0000000000000
++ fadd. 8000000000000000, fff8000000000000 => fff8000000000000
++ fadd. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
++ fadd. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
++ fadd. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
++ fadd. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
++ fadd. fff8000000000000, 0010000000000001 => fff8000000000000
++ fadd. fff8000000000000, 80100094e0000359 => fff8000000000000
++ fadd. fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fadd. fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fadds. 0010000000000001, 0010000000000001 => 0000000000000000
++ fadds. 0010000000000001, 80100094e0000359 => 8000000000000000
++ fadds. 0010000000000001, 7ff0000000000000 => 7ff0000000000000
++ fadds. 0010000000000001, fff8000000000000 => fff8000000000000
++ fadds. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000
++ fadds. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000
++ fadds. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
++ fadds. 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fadds. bfe0000000000001, 0010000000000001 => bfe0000000000000
++ fadds. bfe0000000000001, 80100094e0000359 => bfe0000000000000
++ fadds. bfe0000000000001, 7ff0000000000000 => 7ff0000000000000
++ fadds. bfe0000000000001, fff8000000000000 => fff8000000000000
++ fadds. 8000000000000000, 0010000000000001 => 0000000000000000
++ fadds. 8000000000000000, 80100094e0000359 => 8000000000000000
++ fadds. 8000000000000000, 7ff0000000000000 => 7ff0000000000000
++ fadds. 8000000000000000, fff8000000000000 => fff8000000000000
++ fadds. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
++ fadds. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
++ fadds. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
++ fadds. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
++ fadds. fff8000000000000, 0010000000000001 => fff8000000000000
++ fadds. fff8000000000000, 80100094e0000359 => fff8000000000000
++ fadds. fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fadds. fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fsub. 0010000000000001, 0010000000000001 => 0000000000000000
++ fsub. 0010000000000001, 80100094e0000359 => 0020004a700001ad
++ fsub. 0010000000000001, 7ff0000000000000 => fff0000000000000
++ fsub. 0010000000000001, fff8000000000000 => fff8000000000000
++ fsub. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359
++ fsub. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359
++ fsub. 3fe00094e0000359, 7ff0000000000000 => fff0000000000000
++ fsub. 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fsub. bfe0000000000001, 0010000000000001 => bfe0000000000001
++ fsub. bfe0000000000001, 80100094e0000359 => bfe0000000000001
++ fsub. bfe0000000000001, 7ff0000000000000 => fff0000000000000
++ fsub. bfe0000000000001, fff8000000000000 => fff8000000000000
++ fsub. 8000000000000000, 0010000000000001 => 8010000000000001
++ fsub. 8000000000000000, 80100094e0000359 => 00100094e0000359
++ fsub. 8000000000000000, 7ff0000000000000 => fff0000000000000
++ fsub. 8000000000000000, fff8000000000000 => fff8000000000000
++ fsub. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
++ fsub. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
++ fsub. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
++ fsub. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
++ fsub. fff8000000000000, 0010000000000001 => fff8000000000000
++ fsub. fff8000000000000, 80100094e0000359 => fff8000000000000
++ fsub. fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fsub. fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fsubs. 0010000000000001, 0010000000000001 => 0000000000000000
++ fsubs. 0010000000000001, 80100094e0000359 => 0000000000000000
++ fsubs. 0010000000000001, 7ff0000000000000 => fff0000000000000
++ fsubs. 0010000000000001, fff8000000000000 => fff8000000000000
++ fsubs. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000
++ fsubs. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000
++ fsubs. 3fe00094e0000359, 7ff0000000000000 => fff0000000000000
++ fsubs. 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fsubs. bfe0000000000001, 0010000000000001 => bfe0000000000000
++ fsubs. bfe0000000000001, 80100094e0000359 => bfe0000000000000
++ fsubs. bfe0000000000001, 7ff0000000000000 => fff0000000000000
++ fsubs. bfe0000000000001, fff8000000000000 => fff8000000000000
++ fsubs. 8000000000000000, 0010000000000001 => 8000000000000000
++ fsubs. 8000000000000000, 80100094e0000359 => 0000000000000000
++ fsubs. 8000000000000000, 7ff0000000000000 => fff0000000000000
++ fsubs. 8000000000000000, fff8000000000000 => fff8000000000000
++ fsubs. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
++ fsubs. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
++ fsubs. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
++ fsubs. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
++ fsubs. fff8000000000000, 0010000000000001 => fff8000000000000
++ fsubs. fff8000000000000, 80100094e0000359 => fff8000000000000
++ fsubs. fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fsubs. fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fmul. 0010000000000001, 0010000000000001 => 0000000000000000
++ fmul. 0010000000000001, 80100094e0000359 => 8000000000000000
++ fmul. 0010000000000001, 7ff0000000000000 => 7ff0000000000000
++ fmul. 0010000000000001, fff8000000000000 => fff8000000000000
++ fmul. 3fe00094e0000359, 0010000000000001 => 0008004a700001ad
++ fmul. 3fe00094e0000359, 80100094e0000359 => 80080094e2b4a179
++ fmul. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
++ fmul. 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fmul. bfe0000000000001, 0010000000000001 => 8008000000000001
++ fmul. bfe0000000000001, 80100094e0000359 => 0008004a700001ad
++ fmul. bfe0000000000001, 7ff0000000000000 => fff0000000000000
++ fmul. bfe0000000000001, fff8000000000000 => fff8000000000000
++ fmul. 8000000000000000, 0010000000000001 => 8000000000000000
++ fmul. 8000000000000000, 80100094e0000359 => 0000000000000000
++ fmul. 8000000000000000, 7ff0000000000000 => 7ff8000000000000
++ fmul. 8000000000000000, fff8000000000000 => fff8000000000000
++ fmul. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
++ fmul. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
++ fmul. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
++ fmul. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
++ fmul. fff8000000000000, 0010000000000001 => fff8000000000000
++ fmul. fff8000000000000, 80100094e0000359 => fff8000000000000
++ fmul. fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fmul. fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fmuls. 0010000000000001, 0010000000000001 => 0000000000000000
++ fmuls. 0010000000000001, 80100094e0000359 => 8000000000000000
++ fmuls. 0010000000000001, 7ff0000000000000 => 7ff0000000000000
++ fmuls. 0010000000000001, fff8000000000000 => fff8000000000000
++ fmuls. 3fe00094e0000359, 0010000000000001 => 0000000000000000
++ fmuls. 3fe00094e0000359, 80100094e0000359 => 8000000000000000
++ fmuls. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
++ fmuls. 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fmuls. bfe0000000000001, 0010000000000001 => 8000000000000000
++ fmuls. bfe0000000000001, 80100094e0000359 => 0000000000000000
++ fmuls. bfe0000000000001, 7ff0000000000000 => fff0000000000000
++ fmuls. bfe0000000000001, fff8000000000000 => fff8000000000000
++ fmuls. 8000000000000000, 0010000000000001 => 8000000000000000
++ fmuls. 8000000000000000, 80100094e0000359 => 0000000000000000
++ fmuls. 8000000000000000, 7ff0000000000000 => 7ff8000000000000
++ fmuls. 8000000000000000, fff8000000000000 => fff8000000000000
++ fmuls. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
++ fmuls. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
++ fmuls. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
++ fmuls. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
++ fmuls. fff8000000000000, 0010000000000001 => fff8000000000000
++ fmuls. fff8000000000000, 80100094e0000359 => fff8000000000000
++ fmuls. fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fmuls. fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fdiv. 0010000000000001, 0010000000000001 => 3ff0000000000000
++ fdiv. 0010000000000001, 80100094e0000359 => bfeffed64ad20d22
++ fdiv. 0010000000000001, 7ff0000000000000 => 0000000000000000
++ fdiv. 0010000000000001, fff8000000000000 => fff8000000000000
++ fdiv. 3fe00094e0000359, 0010000000000001 => 7fc00094e0000358
++ fdiv. 3fe00094e0000359, 80100094e0000359 => ffc0000000000000
++ fdiv. 3fe00094e0000359, 7ff0000000000000 => 0000000000000000
++ fdiv. 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fdiv. bfe0000000000001, 0010000000000001 => ffc0000000000000
++ fdiv. bfe0000000000001, 80100094e0000359 => 7fbffed64ad20d22
++ fdiv. bfe0000000000001, 7ff0000000000000 => 8000000000000000
++ fdiv. bfe0000000000001, fff8000000000000 => fff8000000000000
++ fdiv. 8000000000000000, 0010000000000001 => 8000000000000000
++ fdiv. 8000000000000000, 80100094e0000359 => 0000000000000000
++ fdiv. 8000000000000000, 7ff0000000000000 => 8000000000000000
++ fdiv. 8000000000000000, fff8000000000000 => fff8000000000000
++ fdiv. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
++ fdiv. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
++ fdiv. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
++ fdiv. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
++ fdiv. fff8000000000000, 0010000000000001 => fff8000000000000
++ fdiv. fff8000000000000, 80100094e0000359 => fff8000000000000
++ fdiv. fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fdiv. fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fdivs. 0010000000000001, 0010000000000001 => 3ff0000000000000
++ fdivs. 0010000000000001, 80100094e0000359 => bfeffed640000000
++ fdivs. 0010000000000001, 7ff0000000000000 => 0000000000000000
++ fdivs. 0010000000000001, fff8000000000000 => fff8000000000000
++ fdivs. 3fe00094e0000359, 0010000000000001 => 7ff0000000000000
++ fdivs. 3fe00094e0000359, 80100094e0000359 => fff0000000000000
++ fdivs. 3fe00094e0000359, 7ff0000000000000 => 0000000000000000
++ fdivs. 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fdivs. bfe0000000000001, 0010000000000001 => fff0000000000000
++ fdivs. bfe0000000000001, 80100094e0000359 => 7ff0000000000000
++ fdivs. bfe0000000000001, 7ff0000000000000 => 8000000000000000
++ fdivs. bfe0000000000001, fff8000000000000 => fff8000000000000
++ fdivs. 8000000000000000, 0010000000000001 => 8000000000000000
++ fdivs. 8000000000000000, 80100094e0000359 => 0000000000000000
++ fdivs. 8000000000000000, 7ff0000000000000 => 8000000000000000
++ fdivs. 8000000000000000, fff8000000000000 => fff8000000000000
++ fdivs. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
++ fdivs. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
++ fdivs. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
++ fdivs. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
++ fdivs. fff8000000000000, 0010000000000001 => fff8000000000000
++ fdivs. fff8000000000000, 80100094e0000359 => fff8000000000000
++ fdivs. fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fdivs. fff8000000000000, fff8000000000000 => fff8000000000000
++
++PPC floating point compare insns (two args):
++ fcmpo 0010000000000001, 0010000000000001 => fff8000000000000
++ fcmpo 0010000000000001, 80100094e0000359 => fff8000000000000
++ fcmpo 0010000000000001, 7ff0000000000000 => fff8000000000000
++ fcmpo 0010000000000001, fff8000000000000 => fff8000000000000
++ fcmpo 3fe00094e0000359, 0010000000000001 => fff8000000000000
++ fcmpo 3fe00094e0000359, 80100094e0000359 => fff8000000000000
++ fcmpo 3fe00094e0000359, 7ff0000000000000 => fff8000000000000
++ fcmpo 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fcmpo bfe0000000000001, 0010000000000001 => fff8000000000000
++ fcmpo bfe0000000000001, 80100094e0000359 => fff8000000000000
++ fcmpo bfe0000000000001, 7ff0000000000000 => fff8000000000000
++ fcmpo bfe0000000000001, fff8000000000000 => fff8000000000000
++ fcmpo 8000000000000000, 0010000000000001 => fff8000000000000
++ fcmpo 8000000000000000, 80100094e0000359 => fff8000000000000
++ fcmpo 8000000000000000, 7ff0000000000000 => fff8000000000000
++ fcmpo 8000000000000000, fff8000000000000 => fff8000000000000
++ fcmpo 7ff7ffffffffffff, 0010000000000001 => fff8000000000000
++ fcmpo 7ff7ffffffffffff, 80100094e0000359 => fff8000000000000
++ fcmpo 7ff7ffffffffffff, 7ff0000000000000 => fff8000000000000
++ fcmpo 7ff7ffffffffffff, fff8000000000000 => fff8000000000000
++ fcmpo fff8000000000000, 0010000000000001 => fff8000000000000
++ fcmpo fff8000000000000, 80100094e0000359 => fff8000000000000
++ fcmpo fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fcmpo fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fcmpu 0010000000000001, 0010000000000001 => fff8000000000000
++ fcmpu 0010000000000001, 80100094e0000359 => fff8000000000000
++ fcmpu 0010000000000001, 7ff0000000000000 => fff8000000000000
++ fcmpu 0010000000000001, fff8000000000000 => fff8000000000000
++ fcmpu 3fe00094e0000359, 0010000000000001 => fff8000000000000
++ fcmpu 3fe00094e0000359, 80100094e0000359 => fff8000000000000
++ fcmpu 3fe00094e0000359, 7ff0000000000000 => fff8000000000000
++ fcmpu 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fcmpu bfe0000000000001, 0010000000000001 => fff8000000000000
++ fcmpu bfe0000000000001, 80100094e0000359 => fff8000000000000
++ fcmpu bfe0000000000001, 7ff0000000000000 => fff8000000000000
++ fcmpu bfe0000000000001, fff8000000000000 => fff8000000000000
++ fcmpu 8000000000000000, 0010000000000001 => fff8000000000000
++ fcmpu 8000000000000000, 80100094e0000359 => fff8000000000000
++ fcmpu 8000000000000000, 7ff0000000000000 => fff8000000000000
++ fcmpu 8000000000000000, fff8000000000000 => fff8000000000000
++ fcmpu 7ff7ffffffffffff, 0010000000000001 => fff8000000000000
++ fcmpu 7ff7ffffffffffff, 80100094e0000359 => fff8000000000000
++ fcmpu 7ff7ffffffffffff, 7ff0000000000000 => fff8000000000000
++ fcmpu 7ff7ffffffffffff, fff8000000000000 => fff8000000000000
++ fcmpu fff8000000000000, 0010000000000001 => fff8000000000000
++ fcmpu fff8000000000000, 80100094e0000359 => fff8000000000000
++ fcmpu fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fcmpu fff8000000000000, fff8000000000000 => fff8000000000000
++
++PPC floating point arith insns with one arg:
++ fres 0010000000000001 => 7ff0000000000000
++ fres 00100094e0000359 => 7ff0000000000000
++ fres 3fe0000000000001 => 4000000000000000
++ fres 3fe00094e0000359 => 3ffff00000000000
++ fres 8010000000000001 => fff0000000000000
++ fres 80100094e0000359 => fff0000000000000
++ fres bfe0000000000001 => c000000000000000
++ fres bfe00094e0000359 => bffff00000000000
++ fres 0000000000000000 => 7ff0000000000000
++ fres 8000000000000000 => fff0000000000000
++ fres 7ff0000000000000 => 0000000000000000
++ fres fff0000000000000 => 8000000000000000
++ fres 7ff7ffffffffffff => 7ffff00000000000
++ fres fff7ffffffffffff => fffff00000000000
++ fres 7ff8000000000000 => 7ff8000000000000
++ fres fff8000000000000 => fff8000000000000
++
++ frsqrte 0010000000000001 => 5fdf000000000000
++ frsqrte 00100094e0000359 => 5fdf000000000000
++ frsqrte 3fe0000000000001 => 3ff6000000000000
++ frsqrte 3fe00094e0000359 => 3ff6000000000000
++ frsqrte 8010000000000001 => 7ff8000000000000
++ frsqrte 80100094e0000359 => 7ff8000000000000
++ frsqrte bfe0000000000001 => 7ff8000000000000
++ frsqrte bfe00094e0000359 => 7ff8000000000000
++ frsqrte 0000000000000000 => 7ff0000000000000
++ frsqrte 8000000000000000 => fff0000000000000
++ frsqrte 7ff0000000000000 => 0000000000000000
++ frsqrte fff0000000000000 => 7ff8000000000000
++ frsqrte 7ff7ffffffffffff => 7fff000000000000
++ frsqrte fff7ffffffffffff => ffff000000000000
++ frsqrte 7ff8000000000000 => 7ff8000000000000
++ frsqrte fff8000000000000 => fff8000000000000
++
++ frsp 0010000000000001 => 0000000000000000
++ frsp 00100094e0000359 => 0000000000000000
++ frsp 3fe0000000000001 => 3fe0000000000000
++ frsp 3fe00094e0000359 => 3fe00094e0000000
++ frsp 8010000000000001 => 8000000000000000
++ frsp 80100094e0000359 => 8000000000000000
++ frsp bfe0000000000001 => bfe0000000000000
++ frsp bfe00094e0000359 => bfe00094e0000000
++ frsp 0000000000000000 => 0000000000000000
++ frsp 8000000000000000 => 8000000000000000
++ frsp 7ff0000000000000 => 7ff0000000000000
++ frsp fff0000000000000 => fff0000000000000
++ frsp 7ff7ffffffffffff => 7fffffffe0000000
++ frsp fff7ffffffffffff => ffffffffe0000000
++ frsp 7ff8000000000000 => 7ff8000000000000
++ frsp fff8000000000000 => fff8000000000000
++
++ fctiw 0010000000000001 => 0000000000000000
++ fctiw 00100094e0000359 => 0000000000000000
++ fctiw 3fe0000000000001 => 0000000000000001
++ fctiw 3fe00094e0000359 => 0000000000000001
++ fctiw 8010000000000001 => 0000000000000000
++ fctiw 80100094e0000359 => 0000000000000000
++ fctiw bfe0000000000001 => 00000000ffffffff
++ fctiw bfe00094e0000359 => 00000000ffffffff
++ fctiw 0000000000000000 => 0000000000000000
++ fctiw 8000000000000000 => 0000000000000000
++ fctiw 7ff0000000000000 => 000000007fffffff
++ fctiw fff0000000000000 => 0000000080000000
++ fctiw 7ff7ffffffffffff => 0000000080000000
++ fctiw fff7ffffffffffff => 0000000080000000
++ fctiw 7ff8000000000000 => 0000000080000000
++ fctiw fff8000000000000 => 0000000080000000
++
++ fctiwz 0010000000000001 => 0000000000000000
++ fctiwz 00100094e0000359 => 0000000000000000
++ fctiwz 3fe0000000000001 => 0000000000000000
++ fctiwz 3fe00094e0000359 => 0000000000000000
++ fctiwz 8010000000000001 => 0000000000000000
++ fctiwz 80100094e0000359 => 0000000000000000
++ fctiwz bfe0000000000001 => 0000000000000000
++ fctiwz bfe00094e0000359 => 0000000000000000
++ fctiwz 0000000000000000 => 0000000000000000
++ fctiwz 8000000000000000 => 0000000000000000
++ fctiwz 7ff0000000000000 => 000000007fffffff
++ fctiwz fff0000000000000 => 0000000080000000
++ fctiwz 7ff7ffffffffffff => 0000000080000000
++ fctiwz fff7ffffffffffff => 0000000080000000
++ fctiwz 7ff8000000000000 => 0000000080000000
++ fctiwz fff8000000000000 => 0000000080000000
++
++ fmr 0010000000000001 => 0010000000000001
++ fmr 00100094e0000359 => 00100094e0000359
++ fmr 3fe0000000000001 => 3fe0000000000001
++ fmr 3fe00094e0000359 => 3fe00094e0000359
++ fmr 8010000000000001 => 8010000000000001
++ fmr 80100094e0000359 => 80100094e0000359
++ fmr bfe0000000000001 => bfe0000000000001
++ fmr bfe00094e0000359 => bfe00094e0000359
++ fmr 0000000000000000 => 0000000000000000
++ fmr 8000000000000000 => 8000000000000000
++ fmr 7ff0000000000000 => 7ff0000000000000
++ fmr fff0000000000000 => fff0000000000000
++ fmr 7ff7ffffffffffff => 7ff7ffffffffffff
++ fmr fff7ffffffffffff => fff7ffffffffffff
++ fmr 7ff8000000000000 => 7ff8000000000000
++ fmr fff8000000000000 => fff8000000000000
++
++ fneg 0010000000000001 => 8010000000000001
++ fneg 00100094e0000359 => 80100094e0000359
++ fneg 3fe0000000000001 => bfe0000000000001
++ fneg 3fe00094e0000359 => bfe00094e0000359
++ fneg 8010000000000001 => 0010000000000001
++ fneg 80100094e0000359 => 00100094e0000359
++ fneg bfe0000000000001 => 3fe0000000000001
++ fneg bfe00094e0000359 => 3fe00094e0000359
++ fneg 0000000000000000 => 8000000000000000
++ fneg 8000000000000000 => 0000000000000000
++ fneg 7ff0000000000000 => fff0000000000000
++ fneg fff0000000000000 => 7ff0000000000000
++ fneg 7ff7ffffffffffff => fff7ffffffffffff
++ fneg fff7ffffffffffff => 7ff7ffffffffffff
++ fneg 7ff8000000000000 => fff8000000000000
++ fneg fff8000000000000 => 7ff8000000000000
++
++ fabs 0010000000000001 => 0010000000000001
++ fabs 00100094e0000359 => 00100094e0000359
++ fabs 3fe0000000000001 => 3fe0000000000001
++ fabs 3fe00094e0000359 => 3fe00094e0000359
++ fabs 8010000000000001 => 0010000000000001
++ fabs 80100094e0000359 => 00100094e0000359
++ fabs bfe0000000000001 => 3fe0000000000001
++ fabs bfe00094e0000359 => 3fe00094e0000359
++ fabs 0000000000000000 => 0000000000000000
++ fabs 8000000000000000 => 0000000000000000
++ fabs 7ff0000000000000 => 7ff0000000000000
++ fabs fff0000000000000 => 7ff0000000000000
++ fabs 7ff7ffffffffffff => 7ff7ffffffffffff
++ fabs fff7ffffffffffff => 7ff7ffffffffffff
++ fabs 7ff8000000000000 => 7ff8000000000000
++ fabs fff8000000000000 => 7ff8000000000000
++
++ fnabs 0010000000000001 => 8010000000000001
++ fnabs 00100094e0000359 => 80100094e0000359
++ fnabs 3fe0000000000001 => bfe0000000000001
++ fnabs 3fe00094e0000359 => bfe00094e0000359
++ fnabs 8010000000000001 => 8010000000000001
++ fnabs 80100094e0000359 => 80100094e0000359
++ fnabs bfe0000000000001 => bfe0000000000001
++ fnabs bfe00094e0000359 => bfe00094e0000359
++ fnabs 0000000000000000 => 8000000000000000
++ fnabs 8000000000000000 => 8000000000000000
++ fnabs 7ff0000000000000 => fff0000000000000
++ fnabs fff0000000000000 => fff0000000000000
++ fnabs 7ff7ffffffffffff => fff7ffffffffffff
++ fnabs fff7ffffffffffff => fff7ffffffffffff
++ fnabs 7ff8000000000000 => fff8000000000000
++ fnabs fff8000000000000 => fff8000000000000
++
++ fsqrt 0010000000000001 => 2000000000000000
++ fsqrt 00100094e0000359 => 2000004a6f52dd4a
++ fsqrt 3fe0000000000001 => 3fe6a09e667f3bcd
++ fsqrt 3fe00094e0000359 => 3fe6a107aacb50df
++ fsqrt 8010000000000001 => 7ff8000000000000
++ fsqrt 80100094e0000359 => 7ff8000000000000
++ fsqrt bfe0000000000001 => 7ff8000000000000
++ fsqrt bfe00094e0000359 => 7ff8000000000000
++ fsqrt 0000000000000000 => 0000000000000000
++ fsqrt 8000000000000000 => 8000000000000000
++ fsqrt 7ff0000000000000 => 7ff0000000000000
++ fsqrt fff0000000000000 => 7ff8000000000000
++ fsqrt 7ff7ffffffffffff => 7fffffffffffffff
++ fsqrt fff7ffffffffffff => ffffffffffffffff
++ fsqrt 7ff8000000000000 => 7ff8000000000000
++ fsqrt fff8000000000000 => fff8000000000000
++
++PPC floating point arith insns
++ with one arg with flags update:
++ fres. 0010000000000001 => 7ff0000000000000
++ fres. 00100094e0000359 => 7ff0000000000000
++ fres. 3fe0000000000001 => 4000000000000000
++ fres. 3fe00094e0000359 => 3ffff00000000000
++ fres. 8010000000000001 => fff0000000000000
++ fres. 80100094e0000359 => fff0000000000000
++ fres. bfe0000000000001 => c000000000000000
++ fres. bfe00094e0000359 => bffff00000000000
++ fres. 0000000000000000 => 7ff0000000000000
++ fres. 8000000000000000 => fff0000000000000
++ fres. 7ff0000000000000 => 0000000000000000
++ fres. fff0000000000000 => 8000000000000000
++ fres. 7ff7ffffffffffff => 7ffff00000000000
++ fres. fff7ffffffffffff => fffff00000000000
++ fres. 7ff8000000000000 => 7ff8000000000000
++ fres. fff8000000000000 => fff8000000000000
++
++ frsqrte. 0010000000000001 => 5fdf000000000000
++ frsqrte. 00100094e0000359 => 5fdf000000000000
++ frsqrte. 3fe0000000000001 => 3ff6000000000000
++ frsqrte. 3fe00094e0000359 => 3ff6000000000000
++ frsqrte. 8010000000000001 => 7ff8000000000000
++ frsqrte. 80100094e0000359 => 7ff8000000000000
++ frsqrte. bfe0000000000001 => 7ff8000000000000
++ frsqrte. bfe00094e0000359 => 7ff8000000000000
++ frsqrte. 0000000000000000 => 7ff0000000000000
++ frsqrte. 8000000000000000 => fff0000000000000
++ frsqrte. 7ff0000000000000 => 0000000000000000
++ frsqrte. fff0000000000000 => 7ff8000000000000
++ frsqrte. 7ff7ffffffffffff => 7fff000000000000
++ frsqrte. fff7ffffffffffff => ffff000000000000
++ frsqrte. 7ff8000000000000 => 7ff8000000000000
++ frsqrte. fff8000000000000 => fff8000000000000
++
++ frsp. 0010000000000001 => 0000000000000000
++ frsp. 00100094e0000359 => 0000000000000000
++ frsp. 3fe0000000000001 => 3fe0000000000000
++ frsp. 3fe00094e0000359 => 3fe00094e0000000
++ frsp. 8010000000000001 => 8000000000000000
++ frsp. 80100094e0000359 => 8000000000000000
++ frsp. bfe0000000000001 => bfe0000000000000
++ frsp. bfe00094e0000359 => bfe00094e0000000
++ frsp. 0000000000000000 => 0000000000000000
++ frsp. 8000000000000000 => 8000000000000000
++ frsp. 7ff0000000000000 => 7ff0000000000000
++ frsp. fff0000000000000 => fff0000000000000
++ frsp. 7ff7ffffffffffff => 7fffffffe0000000
++ frsp. fff7ffffffffffff => ffffffffe0000000
++ frsp. 7ff8000000000000 => 7ff8000000000000
++ frsp. fff8000000000000 => fff8000000000000
++
++ fctiw. 0010000000000001 => 0000000000000000
++ fctiw. 00100094e0000359 => 0000000000000000
++ fctiw. 3fe0000000000001 => 0000000000000001
++ fctiw. 3fe00094e0000359 => 0000000000000001
++ fctiw. 8010000000000001 => 0000000000000000
++ fctiw. 80100094e0000359 => 0000000000000000
++ fctiw. bfe0000000000001 => 00000000ffffffff
++ fctiw. bfe00094e0000359 => 00000000ffffffff
++ fctiw. 0000000000000000 => 0000000000000000
++ fctiw. 8000000000000000 => 0000000000000000
++ fctiw. 7ff0000000000000 => 000000007fffffff
++ fctiw. fff0000000000000 => 0000000080000000
++ fctiw. 7ff7ffffffffffff => 0000000080000000
++ fctiw. fff7ffffffffffff => 0000000080000000
++ fctiw. 7ff8000000000000 => 0000000080000000
++ fctiw. fff8000000000000 => 0000000080000000
++
++ fctiwz. 0010000000000001 => 0000000000000000
++ fctiwz. 00100094e0000359 => 0000000000000000
++ fctiwz. 3fe0000000000001 => 0000000000000000
++ fctiwz. 3fe00094e0000359 => 0000000000000000
++ fctiwz. 8010000000000001 => 0000000000000000
++ fctiwz. 80100094e0000359 => 0000000000000000
++ fctiwz. bfe0000000000001 => 0000000000000000
++ fctiwz. bfe00094e0000359 => 0000000000000000
++ fctiwz. 0000000000000000 => 0000000000000000
++ fctiwz. 8000000000000000 => 0000000000000000
++ fctiwz. 7ff0000000000000 => 000000007fffffff
++ fctiwz. fff0000000000000 => 0000000080000000
++ fctiwz. 7ff7ffffffffffff => 0000000080000000
++ fctiwz. fff7ffffffffffff => 0000000080000000
++ fctiwz. 7ff8000000000000 => 0000000080000000
++ fctiwz. fff8000000000000 => 0000000080000000
++
++ fmr. 0010000000000001 => 0010000000000001
++ fmr. 00100094e0000359 => 00100094e0000359
++ fmr. 3fe0000000000001 => 3fe0000000000001
++ fmr. 3fe00094e0000359 => 3fe00094e0000359
++ fmr. 8010000000000001 => 8010000000000001
++ fmr. 80100094e0000359 => 80100094e0000359
++ fmr. bfe0000000000001 => bfe0000000000001
++ fmr. bfe00094e0000359 => bfe00094e0000359
++ fmr. 0000000000000000 => 0000000000000000
++ fmr. 8000000000000000 => 8000000000000000
++ fmr. 7ff0000000000000 => 7ff0000000000000
++ fmr. fff0000000000000 => fff0000000000000
++ fmr. 7ff7ffffffffffff => 7ff7ffffffffffff
++ fmr. fff7ffffffffffff => fff7ffffffffffff
++ fmr. 7ff8000000000000 => 7ff8000000000000
++ fmr. fff8000000000000 => fff8000000000000
++
++ fneg. 0010000000000001 => 8010000000000001
++ fneg. 00100094e0000359 => 80100094e0000359
++ fneg. 3fe0000000000001 => bfe0000000000001
++ fneg. 3fe00094e0000359 => bfe00094e0000359
++ fneg. 8010000000000001 => 0010000000000001
++ fneg. 80100094e0000359 => 00100094e0000359
++ fneg. bfe0000000000001 => 3fe0000000000001
++ fneg. bfe00094e0000359 => 3fe00094e0000359
++ fneg. 0000000000000000 => 8000000000000000
++ fneg. 8000000000000000 => 0000000000000000
++ fneg. 7ff0000000000000 => fff0000000000000
++ fneg. fff0000000000000 => 7ff0000000000000
++ fneg. 7ff7ffffffffffff => fff7ffffffffffff
++ fneg. fff7ffffffffffff => 7ff7ffffffffffff
++ fneg. 7ff8000000000000 => fff8000000000000
++ fneg. fff8000000000000 => 7ff8000000000000
++
++ fabs. 0010000000000001 => 0010000000000001
++ fabs. 00100094e0000359 => 00100094e0000359
++ fabs. 3fe0000000000001 => 3fe0000000000001
++ fabs. 3fe00094e0000359 => 3fe00094e0000359
++ fabs. 8010000000000001 => 0010000000000001
++ fabs. 80100094e0000359 => 00100094e0000359
++ fabs. bfe0000000000001 => 3fe0000000000001
++ fabs. bfe00094e0000359 => 3fe00094e0000359
++ fabs. 0000000000000000 => 0000000000000000
++ fabs. 8000000000000000 => 0000000000000000
++ fabs. 7ff0000000000000 => 7ff0000000000000
++ fabs. fff0000000000000 => 7ff0000000000000
++ fabs. 7ff7ffffffffffff => 7ff7ffffffffffff
++ fabs. fff7ffffffffffff => 7ff7ffffffffffff
++ fabs. 7ff8000000000000 => 7ff8000000000000
++ fabs. fff8000000000000 => 7ff8000000000000
++
++ fnabs. 0010000000000001 => 8010000000000001
++ fnabs. 00100094e0000359 => 80100094e0000359
++ fnabs. 3fe0000000000001 => bfe0000000000001
++ fnabs. 3fe00094e0000359 => bfe00094e0000359
++ fnabs. 8010000000000001 => 8010000000000001
++ fnabs. 80100094e0000359 => 80100094e0000359
++ fnabs. bfe0000000000001 => bfe0000000000001
++ fnabs. bfe00094e0000359 => bfe00094e0000359
++ fnabs. 0000000000000000 => 8000000000000000
++ fnabs. 8000000000000000 => 8000000000000000
++ fnabs. 7ff0000000000000 => fff0000000000000
++ fnabs. fff0000000000000 => fff0000000000000
++ fnabs. 7ff7ffffffffffff => fff7ffffffffffff
++ fnabs. fff7ffffffffffff => fff7ffffffffffff
++ fnabs. 7ff8000000000000 => fff8000000000000
++ fnabs. fff8000000000000 => fff8000000000000
++
++PPC floating point status register manipulation insns:
++PPC floating point status register manipulation insns
++ with flags update:
++PPC float load insns
++ with one register + one 16 bits immediate args with flags update:
++ lfs 0010000000000001, 65416 => 37e0000000000000, 0
++ lfs 00100094e0000359, 65424 => 37e0009400000000, 0
++ lfs 3fe0000000000001, 65432 => 3ffc000000000000, 0
++ lfs 3fe00094e0000359, 65440 => 3ffc001280000000, 0
++ lfs 8010000000000001, 65448 => b7e0000000000000, 0
++ lfs 80100094e0000359, 65456 => b7e0009400000000, 0
++ lfs bfe0000000000001, 65464 => bffc000000000000, 0
++ lfs bfe00094e0000359, 65472 => bffc001280000000, 0
++ lfs 0000000000000000, 65480 => 0000000000000000, 0
++ lfs 8000000000000000, 65488 => 8000000000000000, 0
++ lfs 7ff0000000000000, 65496 => 7ffe000000000000, 0
++ lfs fff0000000000000, 65504 => fffe000000000000, 0
++ lfs 7ff7ffffffffffff, 65512 => 7ffeffffe0000000, 0
++ lfs fff7ffffffffffff, 65520 => fffeffffe0000000, 0
++ lfs 7ff8000000000000, 65528 => 7fff000000000000, 0
++ lfs 0010000000000001, 0 => 37e0000000000000, 0
++ lfs 00100094e0000359, 8 => 37e0009400000000, 0
++ lfs 3fe0000000000001, 16 => 3ffc000000000000, 0
++ lfs 3fe00094e0000359, 24 => 3ffc001280000000, 0
++ lfs 8010000000000001, 32 => b7e0000000000000, 0
++ lfs 80100094e0000359, 40 => b7e0009400000000, 0
++ lfs bfe0000000000001, 48 => bffc000000000000, 0
++ lfs bfe00094e0000359, 56 => bffc001280000000, 0
++ lfs 0000000000000000, 64 => 0000000000000000, 0
++ lfs 8000000000000000, 72 => 8000000000000000, 0
++ lfs 7ff0000000000000, 80 => 7ffe000000000000, 0
++ lfs fff0000000000000, 88 => fffe000000000000, 0
++ lfs 7ff7ffffffffffff, 96 => 7ffeffffe0000000, 0
++ lfs fff7ffffffffffff, 104 => fffeffffe0000000, 0
++ lfs 7ff8000000000000, 112 => 7fff000000000000, 0
++ lfs fff8000000000000, 120 => ffff000000000000, 0
++
++ lfsu 0010000000000001, 65416 => 37e0000000000000, -120
++ lfsu 00100094e0000359, 65424 => 37e0009400000000, -112
++ lfsu 3fe0000000000001, 65432 => 3ffc000000000000, -104
++ lfsu 3fe00094e0000359, 65440 => 3ffc001280000000, -96
++ lfsu 8010000000000001, 65448 => b7e0000000000000, -88
++ lfsu 80100094e0000359, 65456 => b7e0009400000000, -80
++ lfsu bfe0000000000001, 65464 => bffc000000000000, -72
++ lfsu bfe00094e0000359, 65472 => bffc001280000000, -64
++ lfsu 0000000000000000, 65480 => 0000000000000000, -56
++ lfsu 8000000000000000, 65488 => 8000000000000000, -48
++ lfsu 7ff0000000000000, 65496 => 7ffe000000000000, -40
++ lfsu fff0000000000000, 65504 => fffe000000000000, -32
++ lfsu 7ff7ffffffffffff, 65512 => 7ffeffffe0000000, -24
++ lfsu fff7ffffffffffff, 65520 => fffeffffe0000000, -16
++ lfsu 7ff8000000000000, 65528 => 7fff000000000000, -8
++ lfsu 0010000000000001, 0 => 37e0000000000000, 0
++ lfsu 00100094e0000359, 8 => 37e0009400000000, 8
++ lfsu 3fe0000000000001, 16 => 3ffc000000000000, 16
++ lfsu 3fe00094e0000359, 24 => 3ffc001280000000, 24
++ lfsu 8010000000000001, 32 => b7e0000000000000, 32
++ lfsu 80100094e0000359, 40 => b7e0009400000000, 40
++ lfsu bfe0000000000001, 48 => bffc000000000000, 48
++ lfsu bfe00094e0000359, 56 => bffc001280000000, 56
++ lfsu 0000000000000000, 64 => 0000000000000000, 64
++ lfsu 8000000000000000, 72 => 8000000000000000, 72
++ lfsu 7ff0000000000000, 80 => 7ffe000000000000, 80
++ lfsu fff0000000000000, 88 => fffe000000000000, 88
++ lfsu 7ff7ffffffffffff, 96 => 7ffeffffe0000000, 96
++ lfsu fff7ffffffffffff, 104 => fffeffffe0000000, 104
++ lfsu 7ff8000000000000, 112 => 7fff000000000000, 112
++ lfsu fff8000000000000, 120 => ffff000000000000, 120
++
++ lfd 0010000000000001, 65416 => 0010000000000001, 0
++ lfd 00100094e0000359, 65424 => 00100094e0000359, 0
++ lfd 3fe0000000000001, 65432 => 3fe0000000000001, 0
++ lfd 3fe00094e0000359, 65440 => 3fe00094e0000359, 0
++ lfd 8010000000000001, 65448 => 8010000000000001, 0
++ lfd 80100094e0000359, 65456 => 80100094e0000359, 0
++ lfd bfe0000000000001, 65464 => bfe0000000000001, 0
++ lfd bfe00094e0000359, 65472 => bfe00094e0000359, 0
++ lfd 0000000000000000, 65480 => 0000000000000000, 0
++ lfd 8000000000000000, 65488 => 8000000000000000, 0
++ lfd 7ff0000000000000, 65496 => 7ff0000000000000, 0
++ lfd fff0000000000000, 65504 => fff0000000000000, 0
++ lfd 7ff7ffffffffffff, 65512 => 7ff7ffffffffffff, 0
++ lfd fff7ffffffffffff, 65520 => fff7ffffffffffff, 0
++ lfd 7ff8000000000000, 65528 => 7ff8000000000000, 0
++ lfd 0010000000000001, 0 => 0010000000000001, 0
++ lfd 00100094e0000359, 8 => 00100094e0000359, 0
++ lfd 3fe0000000000001, 16 => 3fe0000000000001, 0
++ lfd 3fe00094e0000359, 24 => 3fe00094e0000359, 0
++ lfd 8010000000000001, 32 => 8010000000000001, 0
++ lfd 80100094e0000359, 40 => 80100094e0000359, 0
++ lfd bfe0000000000001, 48 => bfe0000000000001, 0
++ lfd bfe00094e0000359, 56 => bfe00094e0000359, 0
++ lfd 0000000000000000, 64 => 0000000000000000, 0
++ lfd 8000000000000000, 72 => 8000000000000000, 0
++ lfd 7ff0000000000000, 80 => 7ff0000000000000, 0
++ lfd fff0000000000000, 88 => fff0000000000000, 0
++ lfd 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0
++ lfd fff7ffffffffffff, 104 => fff7ffffffffffff, 0
++ lfd 7ff8000000000000, 112 => 7ff8000000000000, 0
++ lfd fff8000000000000, 120 => fff8000000000000, 0
++
++ lfdu 0010000000000001, 65416 => 0010000000000001, -120
++ lfdu 00100094e0000359, 65424 => 00100094e0000359, -112
++ lfdu 3fe0000000000001, 65432 => 3fe0000000000001, -104
++ lfdu 3fe00094e0000359, 65440 => 3fe00094e0000359, -96
++ lfdu 8010000000000001, 65448 => 8010000000000001, -88
++ lfdu 80100094e0000359, 65456 => 80100094e0000359, -80
++ lfdu bfe0000000000001, 65464 => bfe0000000000001, -72
++ lfdu bfe00094e0000359, 65472 => bfe00094e0000359, -64
++ lfdu 0000000000000000, 65480 => 0000000000000000, -56
++ lfdu 8000000000000000, 65488 => 8000000000000000, -48
++ lfdu 7ff0000000000000, 65496 => 7ff0000000000000, -40
++ lfdu fff0000000000000, 65504 => fff0000000000000, -32
++ lfdu 7ff7ffffffffffff, 65512 => 7ff7ffffffffffff, -24
++ lfdu fff7ffffffffffff, 65520 => fff7ffffffffffff, -16
++ lfdu 7ff8000000000000, 65528 => 7ff8000000000000, -8
++ lfdu 0010000000000001, 0 => 0010000000000001, 0
++ lfdu 00100094e0000359, 8 => 00100094e0000359, 8
++ lfdu 3fe0000000000001, 16 => 3fe0000000000001, 16
++ lfdu 3fe00094e0000359, 24 => 3fe00094e0000359, 24
++ lfdu 8010000000000001, 32 => 8010000000000001, 32
++ lfdu 80100094e0000359, 40 => 80100094e0000359, 40
++ lfdu bfe0000000000001, 48 => bfe0000000000001, 48
++ lfdu bfe00094e0000359, 56 => bfe00094e0000359, 56
++ lfdu 0000000000000000, 64 => 0000000000000000, 64
++ lfdu 8000000000000000, 72 => 8000000000000000, 72
++ lfdu 7ff0000000000000, 80 => 7ff0000000000000, 80
++ lfdu fff0000000000000, 88 => fff0000000000000, 88
++ lfdu 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96
++ lfdu fff7ffffffffffff, 104 => fff7ffffffffffff, 104
++ lfdu 7ff8000000000000, 112 => 7ff8000000000000, 112
++ lfdu fff8000000000000, 120 => fff8000000000000, 120
++
++PPC float load insns with two register args:
++ lfsx 0010000000000001, -120 => 37e0000000000000, 0
++ lfsx 00100094e0000359, -112 => 37e0009400000000, 0
++ lfsx 3fe0000000000001, -104 => 3ffc000000000000, 0
++ lfsx 3fe00094e0000359, -96 => 3ffc001280000000, 0
++ lfsx 8010000000000001, -88 => b7e0000000000000, 0
++ lfsx 80100094e0000359, -80 => b7e0009400000000, 0
++ lfsx bfe0000000000001, -72 => bffc000000000000, 0
++ lfsx bfe00094e0000359, -64 => bffc001280000000, 0
++ lfsx 0000000000000000, -56 => 0000000000000000, 0
++ lfsx 8000000000000000, -48 => 8000000000000000, 0
++ lfsx 7ff0000000000000, -40 => 7ffe000000000000, 0
++ lfsx fff0000000000000, -32 => fffe000000000000, 0
++ lfsx 7ff7ffffffffffff, -24 => 7ffeffffe0000000, 0
++ lfsx fff7ffffffffffff, -16 => fffeffffe0000000, 0
++ lfsx 7ff8000000000000, -8 => 7fff000000000000, 0
++ lfsx 0010000000000001, 0 => 37e0000000000000, 0
++ lfsx 00100094e0000359, 8 => 37e0009400000000, 0
++ lfsx 3fe0000000000001, 16 => 3ffc000000000000, 0
++ lfsx 3fe00094e0000359, 24 => 3ffc001280000000, 0
++ lfsx 8010000000000001, 32 => b7e0000000000000, 0
++ lfsx 80100094e0000359, 40 => b7e0009400000000, 0
++ lfsx bfe0000000000001, 48 => bffc000000000000, 0
++ lfsx bfe00094e0000359, 56 => bffc001280000000, 0
++ lfsx 0000000000000000, 64 => 0000000000000000, 0
++ lfsx 8000000000000000, 72 => 8000000000000000, 0
++ lfsx 7ff0000000000000, 80 => 7ffe000000000000, 0
++ lfsx fff0000000000000, 88 => fffe000000000000, 0
++ lfsx 7ff7ffffffffffff, 96 => 7ffeffffe0000000, 0
++ lfsx fff7ffffffffffff, 104 => fffeffffe0000000, 0
++ lfsx 7ff8000000000000, 112 => 7fff000000000000, 0
++ lfsx fff8000000000000, 120 => ffff000000000000, 0
++
++ lfsux 0010000000000001, -120 => 37e0000000000000, -120
++ lfsux 00100094e0000359, -112 => 37e0009400000000, -112
++ lfsux 3fe0000000000001, -104 => 3ffc000000000000, -104
++ lfsux 3fe00094e0000359, -96 => 3ffc001280000000, -96
++ lfsux 8010000000000001, -88 => b7e0000000000000, -88
++ lfsux 80100094e0000359, -80 => b7e0009400000000, -80
++ lfsux bfe0000000000001, -72 => bffc000000000000, -72
++ lfsux bfe00094e0000359, -64 => bffc001280000000, -64
++ lfsux 0000000000000000, -56 => 0000000000000000, -56
++ lfsux 8000000000000000, -48 => 8000000000000000, -48
++ lfsux 7ff0000000000000, -40 => 7ffe000000000000, -40
++ lfsux fff0000000000000, -32 => fffe000000000000, -32
++ lfsux 7ff7ffffffffffff, -24 => 7ffeffffe0000000, -24
++ lfsux fff7ffffffffffff, -16 => fffeffffe0000000, -16
++ lfsux 7ff8000000000000, -8 => 7fff000000000000, -8
++ lfsux 0010000000000001, 0 => 37e0000000000000, 0
++ lfsux 00100094e0000359, 8 => 37e0009400000000, 8
++ lfsux 3fe0000000000001, 16 => 3ffc000000000000, 16
++ lfsux 3fe00094e0000359, 24 => 3ffc001280000000, 24
++ lfsux 8010000000000001, 32 => b7e0000000000000, 32
++ lfsux 80100094e0000359, 40 => b7e0009400000000, 40
++ lfsux bfe0000000000001, 48 => bffc000000000000, 48
++ lfsux bfe00094e0000359, 56 => bffc001280000000, 56
++ lfsux 0000000000000000, 64 => 0000000000000000, 64
++ lfsux 8000000000000000, 72 => 8000000000000000, 72
++ lfsux 7ff0000000000000, 80 => 7ffe000000000000, 80
++ lfsux fff0000000000000, 88 => fffe000000000000, 88
++ lfsux 7ff7ffffffffffff, 96 => 7ffeffffe0000000, 96
++ lfsux fff7ffffffffffff, 104 => fffeffffe0000000, 104
++ lfsux 7ff8000000000000, 112 => 7fff000000000000, 112
++ lfsux fff8000000000000, 120 => ffff000000000000, 120
++
++ lfdx 0010000000000001, -120 => 0010000000000001, 0
++ lfdx 00100094e0000359, -112 => 00100094e0000359, 0
++ lfdx 3fe0000000000001, -104 => 3fe0000000000001, 0
++ lfdx 3fe00094e0000359, -96 => 3fe00094e0000359, 0
++ lfdx 8010000000000001, -88 => 8010000000000001, 0
++ lfdx 80100094e0000359, -80 => 80100094e0000359, 0
++ lfdx bfe0000000000001, -72 => bfe0000000000001, 0
++ lfdx bfe00094e0000359, -64 => bfe00094e0000359, 0
++ lfdx 0000000000000000, -56 => 0000000000000000, 0
++ lfdx 8000000000000000, -48 => 8000000000000000, 0
++ lfdx 7ff0000000000000, -40 => 7ff0000000000000, 0
++ lfdx fff0000000000000, -32 => fff0000000000000, 0
++ lfdx 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, 0
++ lfdx fff7ffffffffffff, -16 => fff7ffffffffffff, 0
++ lfdx 7ff8000000000000, -8 => 7ff8000000000000, 0
++ lfdx 0010000000000001, 0 => 0010000000000001, 0
++ lfdx 00100094e0000359, 8 => 00100094e0000359, 0
++ lfdx 3fe0000000000001, 16 => 3fe0000000000001, 0
++ lfdx 3fe00094e0000359, 24 => 3fe00094e0000359, 0
++ lfdx 8010000000000001, 32 => 8010000000000001, 0
++ lfdx 80100094e0000359, 40 => 80100094e0000359, 0
++ lfdx bfe0000000000001, 48 => bfe0000000000001, 0
++ lfdx bfe00094e0000359, 56 => bfe00094e0000359, 0
++ lfdx 0000000000000000, 64 => 0000000000000000, 0
++ lfdx 8000000000000000, 72 => 8000000000000000, 0
++ lfdx 7ff0000000000000, 80 => 7ff0000000000000, 0
++ lfdx fff0000000000000, 88 => fff0000000000000, 0
++ lfdx 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0
++ lfdx fff7ffffffffffff, 104 => fff7ffffffffffff, 0
++ lfdx 7ff8000000000000, 112 => 7ff8000000000000, 0
++ lfdx fff8000000000000, 120 => fff8000000000000, 0
++
++ lfdux 0010000000000001, -120 => 0010000000000001, -120
++ lfdux 00100094e0000359, -112 => 00100094e0000359, -112
++ lfdux 3fe0000000000001, -104 => 3fe0000000000001, -104
++ lfdux 3fe00094e0000359, -96 => 3fe00094e0000359, -96
++ lfdux 8010000000000001, -88 => 8010000000000001, -88
++ lfdux 80100094e0000359, -80 => 80100094e0000359, -80
++ lfdux bfe0000000000001, -72 => bfe0000000000001, -72
++ lfdux bfe00094e0000359, -64 => bfe00094e0000359, -64
++ lfdux 0000000000000000, -56 => 0000000000000000, -56
++ lfdux 8000000000000000, -48 => 8000000000000000, -48
++ lfdux 7ff0000000000000, -40 => 7ff0000000000000, -40
++ lfdux fff0000000000000, -32 => fff0000000000000, -32
++ lfdux 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, -24
++ lfdux fff7ffffffffffff, -16 => fff7ffffffffffff, -16
++ lfdux 7ff8000000000000, -8 => 7ff8000000000000, -8
++ lfdux 0010000000000001, 0 => 0010000000000001, 0
++ lfdux 00100094e0000359, 8 => 00100094e0000359, 8
++ lfdux 3fe0000000000001, 16 => 3fe0000000000001, 16
++ lfdux 3fe00094e0000359, 24 => 3fe00094e0000359, 24
++ lfdux 8010000000000001, 32 => 8010000000000001, 32
++ lfdux 80100094e0000359, 40 => 80100094e0000359, 40
++ lfdux bfe0000000000001, 48 => bfe0000000000001, 48
++ lfdux bfe00094e0000359, 56 => bfe00094e0000359, 56
++ lfdux 0000000000000000, 64 => 0000000000000000, 64
++ lfdux 8000000000000000, 72 => 8000000000000000, 72
++ lfdux 7ff0000000000000, 80 => 7ff0000000000000, 80
++ lfdux fff0000000000000, 88 => fff0000000000000, 88
++ lfdux 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96
++ lfdux fff7ffffffffffff, 104 => fff7ffffffffffff, 104
++ lfdux 7ff8000000000000, 112 => 7ff8000000000000, 112
++ lfdux fff8000000000000, 120 => fff8000000000000, 120
++
++PPC float store insns
++ with one register + one 16 bits immediate args with flags update:
++ stfs 0010000000000001, -56 => 0000000000000000, 0
++ stfs 00100094e0000359, -48 => 0000000000000000, 0
++ stfs 3fe0000000000001, -40 => 3f00000000000000, 0
++ stfs 3fe00094e0000359, -32 => 3f0004a700000000, 0
++ stfs 8010000000000001, -24 => 8000000000000000, 0
++ stfs 80100094e0000359, -16 => 8000000000000000, 0
++ stfs bfe0000000000001, -8 => bf00000000000000, 0
++ stfs 0010000000000001, 0 => 0000000000000000, 0
++ stfs 00100094e0000359, 8 => 0000000000000000, 0
++ stfs 3fe0000000000001, 16 => 3f00000000000000, 0
++ stfs 3fe00094e0000359, 24 => 3f0004a700000000, 0
++ stfs 8010000000000001, 32 => 8000000000000000, 0
++ stfs 80100094e0000359, 40 => 8000000000000000, 0
++ stfs bfe0000000000001, 48 => bf00000000000000, 0
++ stfs bfe00094e0000359, 56 => bf0004a700000000, 0
++
++ stfsu 0010000000000001, -56 => 0000000000000000, -56
++ stfsu 00100094e0000359, -48 => 0000000000000000, -48
++ stfsu 3fe0000000000001, -40 => 3f00000000000000, -40
++ stfsu 3fe00094e0000359, -32 => 3f0004a700000000, -32
++ stfsu 8010000000000001, -24 => 8000000000000000, -24
++ stfsu 80100094e0000359, -16 => 8000000000000000, -16
++ stfsu bfe0000000000001, -8 => bf00000000000000, -8
++ stfsu 0010000000000001, 0 => 0000000000000000, 0
++ stfsu 00100094e0000359, 8 => 0000000000000000, 8
++ stfsu 3fe0000000000001, 16 => 3f00000000000000, 16
++ stfsu 3fe00094e0000359, 24 => 3f0004a700000000, 24
++ stfsu 8010000000000001, 32 => 8000000000000000, 32
++ stfsu 80100094e0000359, 40 => 8000000000000000, 40
++ stfsu bfe0000000000001, 48 => bf00000000000000, 48
++ stfsu bfe00094e0000359, 56 => bf0004a700000000, 56
++
++ stfd 0010000000000001, -120 => 0010000000000001, 0
++ stfd 00100094e0000359, -112 => 00100094e0000359, 0
++ stfd 3fe0000000000001, -104 => 3fe0000000000001, 0
++ stfd 3fe00094e0000359, -96 => 3fe00094e0000359, 0
++ stfd 8010000000000001, -88 => 8010000000000001, 0
++ stfd 80100094e0000359, -80 => 80100094e0000359, 0
++ stfd bfe0000000000001, -72 => bfe0000000000001, 0
++ stfd bfe00094e0000359, -64 => bfe00094e0000359, 0
++ stfd 0000000000000000, -56 => 0000000000000000, 0
++ stfd 8000000000000000, -48 => 8000000000000000, 0
++ stfd 7ff0000000000000, -40 => 7ff0000000000000, 0
++ stfd fff0000000000000, -32 => fff0000000000000, 0
++ stfd 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, 0
++ stfd fff7ffffffffffff, -16 => fff7ffffffffffff, 0
++ stfd 7ff8000000000000, -8 => 7ff8000000000000, 0
++ stfd 0010000000000001, 0 => 0010000000000001, 0
++ stfd 00100094e0000359, 8 => 00100094e0000359, 0
++ stfd 3fe0000000000001, 16 => 3fe0000000000001, 0
++ stfd 3fe00094e0000359, 24 => 3fe00094e0000359, 0
++ stfd 8010000000000001, 32 => 8010000000000001, 0
++ stfd 80100094e0000359, 40 => 80100094e0000359, 0
++ stfd bfe0000000000001, 48 => bfe0000000000001, 0
++ stfd bfe00094e0000359, 56 => bfe00094e0000359, 0
++ stfd 0000000000000000, 64 => 0000000000000000, 0
++ stfd 8000000000000000, 72 => 8000000000000000, 0
++ stfd 7ff0000000000000, 80 => 7ff0000000000000, 0
++ stfd fff0000000000000, 88 => fff0000000000000, 0
++ stfd 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0
++ stfd fff7ffffffffffff, 104 => fff7ffffffffffff, 0
++ stfd 7ff8000000000000, 112 => 7ff8000000000000, 0
++ stfd fff8000000000000, 120 => fff8000000000000, 0
++
++ stfdu 0010000000000001, -120 => 0010000000000001, -120
++ stfdu 00100094e0000359, -112 => 00100094e0000359, -112
++ stfdu 3fe0000000000001, -104 => 3fe0000000000001, -104
++ stfdu 3fe00094e0000359, -96 => 3fe00094e0000359, -96
++ stfdu 8010000000000001, -88 => 8010000000000001, -88
++ stfdu 80100094e0000359, -80 => 80100094e0000359, -80
++ stfdu bfe0000000000001, -72 => bfe0000000000001, -72
++ stfdu bfe00094e0000359, -64 => bfe00094e0000359, -64
++ stfdu 0000000000000000, -56 => 0000000000000000, -56
++ stfdu 8000000000000000, -48 => 8000000000000000, -48
++ stfdu 7ff0000000000000, -40 => 7ff0000000000000, -40
++ stfdu fff0000000000000, -32 => fff0000000000000, -32
++ stfdu 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, -24
++ stfdu fff7ffffffffffff, -16 => fff7ffffffffffff, -16
++ stfdu 7ff8000000000000, -8 => 7ff8000000000000, -8
++ stfdu 0010000000000001, 0 => 0010000000000001, 0
++ stfdu 00100094e0000359, 8 => 00100094e0000359, 8
++ stfdu 3fe0000000000001, 16 => 3fe0000000000001, 16
++ stfdu 3fe00094e0000359, 24 => 3fe00094e0000359, 24
++ stfdu 8010000000000001, 32 => 8010000000000001, 32
++ stfdu 80100094e0000359, 40 => 80100094e0000359, 40
++ stfdu bfe0000000000001, 48 => bfe0000000000001, 48
++ stfdu bfe00094e0000359, 56 => bfe00094e0000359, 56
++ stfdu 0000000000000000, 64 => 0000000000000000, 64
++ stfdu 8000000000000000, 72 => 8000000000000000, 72
++ stfdu 7ff0000000000000, 80 => 7ff0000000000000, 80
++ stfdu fff0000000000000, 88 => fff0000000000000, 88
++ stfdu 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96
++ stfdu fff7ffffffffffff, 104 => fff7ffffffffffff, 104
++ stfdu 7ff8000000000000, 112 => 7ff8000000000000, 112
++ stfdu fff8000000000000, 120 => fff8000000000000, 120
++
++PPC float store insns with three register args:
++ stfsx 0010000000000001, 0 => 0000000000000000, 0
++ stfsx 00100094e0000359, 8 => 0000000000000000, 0
++ stfsx 3fe0000000000001, 16 => 3f00000000000000, 0
++ stfsx 3fe00094e0000359, 24 => 3f0004a700000000, 0
++ stfsx 8010000000000001, 32 => 8000000000000000, 0
++ stfsx 80100094e0000359, 40 => 8000000000000000, 0
++ stfsx bfe0000000000001, 48 => bf00000000000000, 0
++ stfsx bfe00094e0000359, 56 => bf0004a700000000, 0
++
++ stfsux 0010000000000001, 0 => 0000000000000000, 0
++ stfsux 00100094e0000359, 8 => 0000000000000000, 8
++ stfsux 3fe0000000000001, 16 => 3f00000000000000, 16
++ stfsux 3fe00094e0000359, 24 => 3f0004a700000000, 24
++ stfsux 8010000000000001, 32 => 8000000000000000, 32
++ stfsux 80100094e0000359, 40 => 8000000000000000, 40
++ stfsux bfe0000000000001, 48 => bf00000000000000, 48
++ stfsux bfe00094e0000359, 56 => bf0004a700000000, 56
++
++ stfdx 0010000000000001, 0 => 0010000000000001, 0
++ stfdx 00100094e0000359, 8 => 00100094e0000359, 0
++ stfdx 3fe0000000000001, 16 => 3fe0000000000001, 0
++ stfdx 3fe00094e0000359, 24 => 3fe00094e0000359, 0
++ stfdx 8010000000000001, 32 => 8010000000000001, 0
++ stfdx 80100094e0000359, 40 => 80100094e0000359, 0
++ stfdx bfe0000000000001, 48 => bfe0000000000001, 0
++ stfdx bfe00094e0000359, 56 => bfe00094e0000359, 0
++ stfdx 0000000000000000, 64 => 0000000000000000, 0
++ stfdx 8000000000000000, 72 => 8000000000000000, 0
++ stfdx 7ff0000000000000, 80 => 7ff0000000000000, 0
++ stfdx fff0000000000000, 88 => fff0000000000000, 0
++ stfdx 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0
++ stfdx fff7ffffffffffff, 104 => fff7ffffffffffff, 0
++ stfdx 7ff8000000000000, 112 => 7ff8000000000000, 0
++ stfdx fff8000000000000, 120 => fff8000000000000, 0
++
++ stfdux 0010000000000001, 0 => 0010000000000001, 0
++ stfdux 00100094e0000359, 8 => 00100094e0000359, 8
++ stfdux 3fe0000000000001, 16 => 3fe0000000000001, 16
++ stfdux 3fe00094e0000359, 24 => 3fe00094e0000359, 24
++ stfdux 8010000000000001, 32 => 8010000000000001, 32
++ stfdux 80100094e0000359, 40 => 80100094e0000359, 40
++ stfdux bfe0000000000001, 48 => bfe0000000000001, 48
++ stfdux bfe00094e0000359, 56 => bfe00094e0000359, 56
++ stfdux 0000000000000000, 64 => 0000000000000000, 64
++ stfdux 8000000000000000, 72 => 8000000000000000, 72
++ stfdux 7ff0000000000000, 80 => 7ff0000000000000, 80
++ stfdux fff0000000000000, 88 => fff0000000000000, 88
++ stfdux 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96
++ stfdux fff7ffffffffffff, 104 => fff7ffffffffffff, 104
++ stfdux 7ff8000000000000, 112 => 7ff8000000000000, 112
++ stfdux fff8000000000000, 120 => fff8000000000000, 120
++
++All done. Tested 71 different instructions
+diff --git a/none/tests/ppc32/jm-insns.c b/none/tests/ppc32/jm-insns.c
+index cca565c..ef36adb 100644
+--- a/none/tests/ppc32/jm-insns.c
++++ b/none/tests/ppc32/jm-insns.c
+@@ -260,6 +260,7 @@ asm(".section \".text\"\n" \
+ "\t.previous\n" \
+ )
+ #else
++#if defined(VGP_ppc64be_linux)
+ #define ASSEMBLY_FUNC(__fname, __insn) \
+ asm(".section \".text\"\n" \
+ "\t.align 2\n" \
+@@ -275,6 +276,16 @@ asm(".section \".text\"\n" \
+ "\t"__insn"\n" \
+ "\tblr\n" \
+ )
++#elif defined(VGP_ppc64le_linux)
++#define ASSEMBLY_FUNC(__fname, __insn) \
++asm(".section \".text\"\n" \
++ "\t.align 2\n" \
++ "\t.global "__fname"\n" \
++ ""__fname":\n" \
++ "\t"__insn"\n" \
++ "\tblr\n" \
++ )
++#endif // VGP_ppc64be or VGP_ppc64le
+ #endif // #ifndef __powerpc64__
+
+
+@@ -4849,7 +4860,7 @@ static inline
+ test_func_t init_function( test_func_t p_func_F, uint32_t func_buf[] )
+ {
+ uint32_t* p_func = (uint32_t*)p_func_F;
+-#ifndef __powerpc64__
++#if !defined(__powerpc64__) || _CALL_ELF == 2
+ func_buf[0] = p_func[0];
+ func_buf[1] = p_func[1];
+ return (test_func_t)&func_buf[0];
+@@ -5521,20 +5532,21 @@ static void test_int_ld_one_reg_imm16 (const char* name,
+ uint32_t* func_buf = get_rwx_area();
+ volatile HWord_t res, base;
+ volatile uint32_t flags, xer;
+- int i, offs, is_lwa=0;
++ int i, offs, shift_offset = 0;
+
+ #ifdef __powerpc64__
+- is_lwa = strstr(name, "lwa") != NULL;
++ if (strstr(name, "lwa") || strstr(name, "ld") || strstr(name, "ldu"))
++ shift_offset = 1;
+ #endif
+
+ // +ve d
+ base = (HWord_t)&iargs[0];
+ for (i=0; i<nb_iargs; i++) {
+- offs = i * sizeof(HWord_t);
++ offs = (i == 0) ? i : (i * sizeof(HWord_t)) - 1;
+
+ /* Patch up the instruction */
+ func = init_function( func_IN, func_buf );
+- if (is_lwa)
++ if (shift_offset)
+ patch_op_imm(&func_buf[0], offs>>2, 2, 14);
+ else
+ patch_op_imm16(&func_buf[0], offs);
+@@ -5557,8 +5569,8 @@ static void test_int_ld_one_reg_imm16 (const char* name,
+
+ // -ve d
+ base = (HWord_t)&iargs[nb_iargs-1];
+- for (i = -nb_iargs+1; i<=0; i++) {
+- offs = i * sizeof(HWord_t);
++ for (i = 0; i > -nb_iargs; i--) {
++ offs = (i * sizeof(HWord_t)) + 1;
+
+ /* Patch up the instruction */
+ func = init_function( func, func_buf );
+@@ -5574,9 +5586,9 @@ static void test_int_ld_one_reg_imm16 (const char* name,
+ #ifndef __powerpc64__
+ printf("%s %2d, (%08x) => %08x, %2d (%08x %08x)\n",
+ #else
+- printf("%s %3d, (%016llx) => %016llx, %3lld (%08x %08x)\n",
++ printf("%s %3d, (%016x) => %016llx, %3lld (%08x %08x)\n",
+ #endif
+- name, offs, iargs[nb_iargs-1+i], res, r14-base, flags, xer);
++ name, offs, iargs[nb_iargs-1 + i], res, r14-base, flags, xer);
+ }
+ }
+
+@@ -5767,7 +5779,6 @@ static void test_float_three_args (const char* name, test_func_t func,
+ /* Note: using nb_normal_fargs:
+ - not testing special values for these insns
+ */
+-
+ for (i=0; i<nb_normal_fargs; i+=3) {
+ for (j=0; j<nb_normal_fargs; j+=5) {
+ for (k=0; k<nb_normal_fargs; k+=7) {
+@@ -5965,10 +5976,11 @@ static void test_float_ld_one_reg_imm16 (const char* name,
+ {
+ volatile test_func_t func;
+ uint32_t* func_buf = get_rwx_area();
+- uint32_t base;
++ HWord_t base;
+ volatile uint32_t flags, xer;
+ volatile double src, res;
+- int i, offs;
++ int i;
++ uint16_t offs;
+
+ /* offset within [1-nb_fargs:nb_fargs] */
+ for (i=1-nb_fargs; i<nb_fargs; i++) {
+@@ -6016,7 +6028,7 @@ static void test_float_ld_two_regs (const char* name,
+ volatile uint32_t flags, xer;
+ volatile double src, res;
+ int i, offs;
+-
++
+ /* offset within [1-nb_fargs:nb_fargs] */
+ for (i=1-nb_fargs; i<nb_fargs; i++) {
+ offs = i * 8; // offset = i * sizeof(double)
+@@ -6721,8 +6733,9 @@ static void lvs_cb (const char *name, test_func_t func,
+ volatile uint32_t flags, tmpcr;
+ volatile vector unsigned int tmpvscr;
+ volatile vector unsigned int vec_out, vscr;
+- unsigned int *dst;
+- int i;
++ unsigned shift;
++ unsigned char * dst;
++ int i, j;
+ #if defined TEST_VSCR_SAT
+ unsigned int* p_vscr;
+ #endif
+@@ -6731,7 +6744,8 @@ static void lvs_cb (const char *name, test_func_t func,
+ vec_out = (vector unsigned int){ 0,0,0,0 };
+
+ // make sure start address is 16 aligned - use viargs[0]
+- r15 = (HWord_t)&viargs[0];
++ HWord_t * r15_in_ptr = (HWord_t *)&viargs[0];
++ r15 = *r15_in_ptr;
+ r14 = i;
+
+ /* Save flags */
+@@ -6758,11 +6772,18 @@ static void lvs_cb (const char *name, test_func_t func,
+ __asm__ __volatile__ ("mtcr %0" : : "r" (tmpcr));
+ __asm__ __volatile__ ("mtvscr %0" : : "v" (tmpvscr));
+
+- dst = (unsigned int*)&vec_out;
++ dst = (unsigned char*)&vec_out;
++
++ shift = ((unsigned int)i + *r15_in_ptr) & 0xf;
++ printf("%s %x, %3d", name, shift, 0);
++ printf(" => 0x");
++ for (j = 0; j < 16; j++) {
++ printf("%02x", dst[j]);
++ if (j == 7)
++ printf(" 0x");
++ }
+
+- printf("%s %3d, %3d", name, i, 0);
+- printf(" => %08x %08x %08x %08x ", dst[0], dst[1], dst[2], dst[3]);
+- printf("(%08x)\n", flags);
++ printf(" (%08x)\n", flags);
+ }
+ if (verbose) printf("\n");
+ }
+diff --git a/none/tests/ppc32/jm-int.stdout.exp b/none/tests/ppc32/jm-int.stdout.exp
+index 5198d02..9035084 100644
+--- a/none/tests/ppc32/jm-int.stdout.exp
++++ b/none/tests/ppc32/jm-int.stdout.exp
+@@ -1439,60 +1439,60 @@ PPC logical insns with special forms with flags update:
+ PPC integer load insns
+ with one register + one 16 bits immediate args with flags update:
+ lbz 0, (00000000) => 00000000, 0 (00000000 00000000)
+- lbz 4, (000f423f) => 00000000, 0 (00000000 00000000)
+- lbz 8, (ffffffff) => 000000ff, 0 (00000000 00000000)
+- lbz -8, (00000000) => 00000000, 0 (00000000 00000000)
+- lbz -4, (000f423f) => 00000000, 0 (00000000 00000000)
+- lbz 0, (ffffffff) => 000000ff, 0 (00000000 00000000)
++ lbz 3, (000f423f) => 00000000, 0 (00000000 00000000)
++ lbz 7, (ffffffff) => 0000003f, 0 (00000000 00000000)
++ lbz 1, (ffffffff) => 000000ff, 0 (00000000 00000000)
++ lbz -3, (000f423f) => 0000000f, 0 (00000000 00000000)
++ lbz -7, (00000000) => 00000000, 0 (00000000 00000000)
+
+ lbzu 0, (00000000) => 00000000, 0 (00000000 00000000)
+- lbzu 4, (000f423f) => 00000000, 4 (00000000 00000000)
+- lbzu 8, (ffffffff) => 000000ff, 8 (00000000 00000000)
+- lbzu -8, (00000000) => 00000000, -8 (00000000 00000000)
+- lbzu -4, (000f423f) => 00000000, -4 (00000000 00000000)
+- lbzu 0, (ffffffff) => 000000ff, 0 (00000000 00000000)
++ lbzu 3, (000f423f) => 00000000, 3 (00000000 00000000)
++ lbzu 7, (ffffffff) => 0000003f, 7 (00000000 00000000)
++ lbzu 1, (ffffffff) => 000000ff, 1 (00000000 00000000)
++ lbzu -3, (000f423f) => 0000000f, -3 (00000000 00000000)
++ lbzu -7, (00000000) => 00000000, -7 (00000000 00000000)
+
+ lha 0, (00000000) => 00000000, 0 (00000000 00000000)
+- lha 4, (000f423f) => 0000000f, 0 (00000000 00000000)
+- lha 8, (ffffffff) => ffffffff, 0 (00000000 00000000)
+- lha -8, (00000000) => 00000000, 0 (00000000 00000000)
+- lha -4, (000f423f) => 0000000f, 0 (00000000 00000000)
+- lha 0, (ffffffff) => ffffffff, 0 (00000000 00000000)
++ lha 3, (000f423f) => 00000000, 0 (00000000 00000000)
++ lha 7, (ffffffff) => 00003fff, 0 (00000000 00000000)
++ lha 1, (ffffffff) => ffffffff, 0 (00000000 00000000)
++ lha -3, (000f423f) => 00000f42, 0 (00000000 00000000)
++ lha -7, (00000000) => 00000000, 0 (00000000 00000000)
+
+ lhau 0, (00000000) => 00000000, 0 (00000000 00000000)
+- lhau 4, (000f423f) => 0000000f, 4 (00000000 00000000)
+- lhau 8, (ffffffff) => ffffffff, 8 (00000000 00000000)
+- lhau -8, (00000000) => 00000000, -8 (00000000 00000000)
+- lhau -4, (000f423f) => 0000000f, -4 (00000000 00000000)
+- lhau 0, (ffffffff) => ffffffff, 0 (00000000 00000000)
++ lhau 3, (000f423f) => 00000000, 3 (00000000 00000000)
++ lhau 7, (ffffffff) => 00003fff, 7 (00000000 00000000)
++ lhau 1, (ffffffff) => ffffffff, 1 (00000000 00000000)
++ lhau -3, (000f423f) => 00000f42, -3 (00000000 00000000)
++ lhau -7, (00000000) => 00000000, -7 (00000000 00000000)
+
+ lhz 0, (00000000) => 00000000, 0 (00000000 00000000)
+- lhz 4, (000f423f) => 0000000f, 0 (00000000 00000000)
+- lhz 8, (ffffffff) => 0000ffff, 0 (00000000 00000000)
+- lhz -8, (00000000) => 00000000, 0 (00000000 00000000)
+- lhz -4, (000f423f) => 0000000f, 0 (00000000 00000000)
+- lhz 0, (ffffffff) => 0000ffff, 0 (00000000 00000000)
++ lhz 3, (000f423f) => 00000000, 0 (00000000 00000000)
++ lhz 7, (ffffffff) => 00003fff, 0 (00000000 00000000)
++ lhz 1, (ffffffff) => 0000ffff, 0 (00000000 00000000)
++ lhz -3, (000f423f) => 00000f42, 0 (00000000 00000000)
++ lhz -7, (00000000) => 00000000, 0 (00000000 00000000)
+
+ lhzu 0, (00000000) => 00000000, 0 (00000000 00000000)
+- lhzu 4, (000f423f) => 0000000f, 4 (00000000 00000000)
+- lhzu 8, (ffffffff) => 0000ffff, 8 (00000000 00000000)
+- lhzu -8, (00000000) => 00000000, -8 (00000000 00000000)
+- lhzu -4, (000f423f) => 0000000f, -4 (00000000 00000000)
+- lhzu 0, (ffffffff) => 0000ffff, 0 (00000000 00000000)
++ lhzu 3, (000f423f) => 00000000, 3 (00000000 00000000)
++ lhzu 7, (ffffffff) => 00003fff, 7 (00000000 00000000)
++ lhzu 1, (ffffffff) => 0000ffff, 1 (00000000 00000000)
++ lhzu -3, (000f423f) => 00000f42, -3 (00000000 00000000)
++ lhzu -7, (00000000) => 00000000, -7 (00000000 00000000)
+
+ lwz 0, (00000000) => 00000000, 0 (00000000 00000000)
+- lwz 4, (000f423f) => 000f423f, 0 (00000000 00000000)
+- lwz 8, (ffffffff) => ffffffff, 0 (00000000 00000000)
+- lwz -8, (00000000) => 00000000, 0 (00000000 00000000)
+- lwz -4, (000f423f) => 000f423f, 0 (00000000 00000000)
+- lwz 0, (ffffffff) => ffffffff, 0 (00000000 00000000)
++ lwz 3, (000f423f) => 00000f42, 0 (00000000 00000000)
++ lwz 7, (ffffffff) => 3fffffff, 0 (00000000 00000000)
++ lwz 1, (ffffffff) => ffffff00, 0 (00000000 00000000)
++ lwz -3, (000f423f) => 0f423fff, 0 (00000000 00000000)
++ lwz -7, (00000000) => 00000000, 0 (00000000 00000000)
+
+ lwzu 0, (00000000) => 00000000, 0 (00000000 00000000)
+- lwzu 4, (000f423f) => 000f423f, 4 (00000000 00000000)
+- lwzu 8, (ffffffff) => ffffffff, 8 (00000000 00000000)
+- lwzu -8, (00000000) => 00000000, -8 (00000000 00000000)
+- lwzu -4, (000f423f) => 000f423f, -4 (00000000 00000000)
+- lwzu 0, (ffffffff) => ffffffff, 0 (00000000 00000000)
++ lwzu 3, (000f423f) => 00000f42, 3 (00000000 00000000)
++ lwzu 7, (ffffffff) => 3fffffff, 7 (00000000 00000000)
++ lwzu 1, (ffffffff) => ffffff00, 1 (00000000 00000000)
++ lwzu -3, (000f423f) => 0f423fff, -3 (00000000 00000000)
++ lwzu -7, (00000000) => 00000000, -7 (00000000 00000000)
+
+ PPC integer load insns with two register args:
+ lbzx 0 (00000000) => 00000000, 0 (00000000 00000000)
+diff --git a/none/tests/ppc32/jm-vmx.stdout.exp b/none/tests/ppc32/jm-vmx.stdout.exp
+index 3e19e63..43faa1a 100644
+--- a/none/tests/ppc32/jm-vmx.stdout.exp
++++ b/none/tests/ppc32/jm-vmx.stdout.exp
+@@ -1407,43 +1407,43 @@ Altivec integer special insns:
+ vsldoi: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 14
+ vsldoi: => fefff1f2 f3f4f5f6 f7f8f9fa fbfcfefd] (00000000)
+
+- lvsl -1, 0 => 0f101112 13141516 1718191a 1b1c1d1e (00000000)
+- lvsl 0, 0 => 00010203 04050607 08090a0b 0c0d0e0f (00000000)
+- lvsl 1, 0 => 01020304 05060708 090a0b0c 0d0e0f10 (00000000)
+- lvsl 2, 0 => 02030405 06070809 0a0b0c0d 0e0f1011 (00000000)
+- lvsl 3, 0 => 03040506 0708090a 0b0c0d0e 0f101112 (00000000)
+- lvsl 4, 0 => 04050607 08090a0b 0c0d0e0f 10111213 (00000000)
+- lvsl 5, 0 => 05060708 090a0b0c 0d0e0f10 11121314 (00000000)
+- lvsl 6, 0 => 06070809 0a0b0c0d 0e0f1011 12131415 (00000000)
+- lvsl 7, 0 => 0708090a 0b0c0d0e 0f101112 13141516 (00000000)
+- lvsl 8, 0 => 08090a0b 0c0d0e0f 10111213 14151617 (00000000)
+- lvsl 9, 0 => 090a0b0c 0d0e0f10 11121314 15161718 (00000000)
+- lvsl 10, 0 => 0a0b0c0d 0e0f1011 12131415 16171819 (00000000)
+- lvsl 11, 0 => 0b0c0d0e 0f101112 13141516 1718191a (00000000)
+- lvsl 12, 0 => 0c0d0e0f 10111213 14151617 18191a1b (00000000)
+- lvsl 13, 0 => 0d0e0f10 11121314 15161718 191a1b1c (00000000)
+- lvsl 14, 0 => 0e0f1011 12131415 16171819 1a1b1c1d (00000000)
+- lvsl 15, 0 => 0f101112 13141516 1718191a 1b1c1d1e (00000000)
+- lvsl 16, 0 => 00010203 04050607 08090a0b 0c0d0e0f (00000000)
+-
+- lvsr -1, 0 => 01020304 05060708 090a0b0c 0d0e0f10 (00000000)
+- lvsr 0, 0 => 10111213 14151617 18191a1b 1c1d1e1f (00000000)
+- lvsr 1, 0 => 0f101112 13141516 1718191a 1b1c1d1e (00000000)
+- lvsr 2, 0 => 0e0f1011 12131415 16171819 1a1b1c1d (00000000)
+- lvsr 3, 0 => 0d0e0f10 11121314 15161718 191a1b1c (00000000)
+- lvsr 4, 0 => 0c0d0e0f 10111213 14151617 18191a1b (00000000)
+- lvsr 5, 0 => 0b0c0d0e 0f101112 13141516 1718191a (00000000)
+- lvsr 6, 0 => 0a0b0c0d 0e0f1011 12131415 16171819 (00000000)
+- lvsr 7, 0 => 090a0b0c 0d0e0f10 11121314 15161718 (00000000)
+- lvsr 8, 0 => 08090a0b 0c0d0e0f 10111213 14151617 (00000000)
+- lvsr 9, 0 => 0708090a 0b0c0d0e 0f101112 13141516 (00000000)
+- lvsr 10, 0 => 06070809 0a0b0c0d 0e0f1011 12131415 (00000000)
+- lvsr 11, 0 => 05060708 090a0b0c 0d0e0f10 11121314 (00000000)
+- lvsr 12, 0 => 04050607 08090a0b 0c0d0e0f 10111213 (00000000)
+- lvsr 13, 0 => 03040506 0708090a 0b0c0d0e 0f101112 (00000000)
+- lvsr 14, 0 => 02030405 06070809 0a0b0c0d 0e0f1011 (00000000)
+- lvsr 15, 0 => 01020304 05060708 090a0b0c 0d0e0f10 (00000000)
+- lvsr 16, 0 => 10111213 14151617 18191a1b 1c1d1e1f (00000000)
++ lvsl 3, 0 => 0x030405060708090a 0x0b0c0d0e0f101112 (00000000)
++ lvsl 4, 0 => 0x0405060708090a0b 0x0c0d0e0f10111213 (00000000)
++ lvsl 5, 0 => 0x05060708090a0b0c 0x0d0e0f1011121314 (00000000)
++ lvsl 6, 0 => 0x060708090a0b0c0d 0x0e0f101112131415 (00000000)
++ lvsl 7, 0 => 0x0708090a0b0c0d0e 0x0f10111213141516 (00000000)
++ lvsl 8, 0 => 0x08090a0b0c0d0e0f 0x1011121314151617 (00000000)
++ lvsl 9, 0 => 0x090a0b0c0d0e0f10 0x1112131415161718 (00000000)
++ lvsl a, 0 => 0x0a0b0c0d0e0f1011 0x1213141516171819 (00000000)
++ lvsl b, 0 => 0x0b0c0d0e0f101112 0x131415161718191a (00000000)
++ lvsl c, 0 => 0x0c0d0e0f10111213 0x1415161718191a1b (00000000)
++ lvsl d, 0 => 0x0d0e0f1011121314 0x15161718191a1b1c (00000000)
++ lvsl e, 0 => 0x0e0f101112131415 0x161718191a1b1c1d (00000000)
++ lvsl f, 0 => 0x0f10111213141516 0x1718191a1b1c1d1e (00000000)
++ lvsl 0, 0 => 0x0001020304050607 0x08090a0b0c0d0e0f (00000000)
++ lvsl 1, 0 => 0x0102030405060708 0x090a0b0c0d0e0f10 (00000000)
++ lvsl 2, 0 => 0x0203040506070809 0x0a0b0c0d0e0f1011 (00000000)
++ lvsl 3, 0 => 0x030405060708090a 0x0b0c0d0e0f101112 (00000000)
++ lvsl 4, 0 => 0x0405060708090a0b 0x0c0d0e0f10111213 (00000000)
++
++ lvsr 3, 0 => 0x0d0e0f1011121314 0x15161718191a1b1c (00000000)
++ lvsr 4, 0 => 0x0c0d0e0f10111213 0x1415161718191a1b (00000000)
++ lvsr 5, 0 => 0x0b0c0d0e0f101112 0x131415161718191a (00000000)
++ lvsr 6, 0 => 0x0a0b0c0d0e0f1011 0x1213141516171819 (00000000)
++ lvsr 7, 0 => 0x090a0b0c0d0e0f10 0x1112131415161718 (00000000)
++ lvsr 8, 0 => 0x08090a0b0c0d0e0f 0x1011121314151617 (00000000)
++ lvsr 9, 0 => 0x0708090a0b0c0d0e 0x0f10111213141516 (00000000)
++ lvsr a, 0 => 0x060708090a0b0c0d 0x0e0f101112131415 (00000000)
++ lvsr b, 0 => 0x05060708090a0b0c 0x0d0e0f1011121314 (00000000)
++ lvsr c, 0 => 0x0405060708090a0b 0x0c0d0e0f10111213 (00000000)
++ lvsr d, 0 => 0x030405060708090a 0x0b0c0d0e0f101112 (00000000)
++ lvsr e, 0 => 0x0203040506070809 0x0a0b0c0d0e0f1011 (00000000)
++ lvsr f, 0 => 0x0102030405060708 0x090a0b0c0d0e0f10 (00000000)
++ lvsr 0, 0 => 0x1011121314151617 0x18191a1b1c1d1e1f (00000000)
++ lvsr 1, 0 => 0x0f10111213141516 0x1718191a1b1c1d1e (00000000)
++ lvsr 2, 0 => 0x0e0f101112131415 0x161718191a1b1c1d (00000000)
++ lvsr 3, 0 => 0x0d0e0f1011121314 0x15161718191a1b1c (00000000)
++ lvsr 4, 0 => 0x0c0d0e0f10111213 0x1415161718191a1b (00000000)
+
+ Altivec load insns with two register args:
+ lvebx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01000000 00000000 00000000 00000000 (00000000)
+@@ -3451,18 +3451,18 @@ Altivec float special insns:
+ vcfux: 7fffffff ( nan), 9 => 4a800000 ( 4.194304e+06) (00000000)
+ vcfux: 7fffffff ( nan), 18 => 46000000 ( 8.192000e+03) (00000000)
+ vcfux: 7fffffff ( nan), 27 => 41800000 ( 1.600000e+01) (00000000)
+- vcfux: ffffffff ( nan), 0 => 4f800000 ( 4.294967e+09) (00000000)
+- vcfux: ffffffff ( nan), 9 => 4b000000 ( 8.388608e+06) (00000000)
+- vcfux: ffffffff ( nan), 18 => 46800000 ( 1.638400e+04) (00000000)
+- vcfux: ffffffff ( nan), 27 => 42000000 ( 3.200000e+01) (00000000)
++ vcfux: ffffffff ( -nan), 0 => 4f800000 ( 4.294967e+09) (00000000)
++ vcfux: ffffffff ( -nan), 9 => 4b000000 ( 8.388608e+06) (00000000)
++ vcfux: ffffffff ( -nan), 18 => 46800000 ( 1.638400e+04) (00000000)
++ vcfux: ffffffff ( -nan), 27 => 42000000 ( 3.200000e+01) (00000000)
+ vcfux: 7fbfffff ( nan), 0 => 4eff8000 ( 2.143289e+09) (00000000)
+ vcfux: 7fbfffff ( nan), 9 => 4a7f8000 ( 4.186112e+06) (00000000)
+ vcfux: 7fbfffff ( nan), 18 => 45ff8000 ( 8.176000e+03) (00000000)
+ vcfux: 7fbfffff ( nan), 27 => 417f8000 ( 1.596875e+01) (00000000)
+- vcfux: ffbfffff ( nan), 0 => 4f7fc000 ( 4.290773e+09) (00000000)
+- vcfux: ffbfffff ( nan), 9 => 4affc000 ( 8.380416e+06) (00000000)
+- vcfux: ffbfffff ( nan), 18 => 467fc000 ( 1.636800e+04) (00000000)
+- vcfux: ffbfffff ( nan), 27 => 41ffc000 ( 3.196875e+01) (00000000)
++ vcfux: ffbfffff ( -nan), 0 => 4f7fc000 ( 4.290773e+09) (00000000)
++ vcfux: ffbfffff ( -nan), 9 => 4affc000 ( 8.380416e+06) (00000000)
++ vcfux: ffbfffff ( -nan), 18 => 467fc000 ( 1.636800e+04) (00000000)
++ vcfux: ffbfffff ( -nan), 27 => 41ffc000 ( 3.196875e+01) (00000000)
+
+ vcfsx: 02bfffff ( 2.821186e-37), 0 => 4c300000 ( 4.613734e+07) (00000000)
+ vcfsx: 02bfffff ( 2.821186e-37), 9 => 47b00000 ( 9.011200e+04) (00000000)
+@@ -3500,27 +3500,27 @@ Altivec float special insns:
+ vcfsx: 7fffffff ( nan), 9 => 4a800000 ( 4.194304e+06) (00000000)
+ vcfsx: 7fffffff ( nan), 18 => 46000000 ( 8.192000e+03) (00000000)
+ vcfsx: 7fffffff ( nan), 27 => 41800000 ( 1.600000e+01) (00000000)
+- vcfsx: ffffffff ( nan), 0 => bf800000 (-1.000000e+00) (00000000)
+- vcfsx: ffffffff ( nan), 9 => bb000000 (-1.953125e-03) (00000000)
+- vcfsx: ffffffff ( nan), 18 => b6800000 (-3.814697e-06) (00000000)
+- vcfsx: ffffffff ( nan), 27 => b2000000 (-7.450581e-09) (00000000)
++ vcfsx: ffffffff ( -nan), 0 => bf800000 (-1.000000e+00) (00000000)
++ vcfsx: ffffffff ( -nan), 9 => bb000000 (-1.953125e-03) (00000000)
++ vcfsx: ffffffff ( -nan), 18 => b6800000 (-3.814697e-06) (00000000)
++ vcfsx: ffffffff ( -nan), 27 => b2000000 (-7.450581e-09) (00000000)
+ vcfsx: 7fbfffff ( nan), 0 => 4eff8000 ( 2.143289e+09) (00000000)
+ vcfsx: 7fbfffff ( nan), 9 => 4a7f8000 ( 4.186112e+06) (00000000)
+ vcfsx: 7fbfffff ( nan), 18 => 45ff8000 ( 8.176000e+03) (00000000)
+ vcfsx: 7fbfffff ( nan), 27 => 417f8000 ( 1.596875e+01) (00000000)
+- vcfsx: ffbfffff ( nan), 0 => ca800002 (-4.194305e+06) (00000000)
+- vcfsx: ffbfffff ( nan), 9 => c6000002 (-8.192002e+03) (00000000)
+- vcfsx: ffbfffff ( nan), 18 => c1800002 (-1.600000e+01) (00000000)
+- vcfsx: ffbfffff ( nan), 27 => bd000002 (-3.125001e-02) (00000000)
++ vcfsx: ffbfffff ( -nan), 0 => ca800002 (-4.194305e+06) (00000000)
++ vcfsx: ffbfffff ( -nan), 9 => c6000002 (-8.192002e+03) (00000000)
++ vcfsx: ffbfffff ( -nan), 18 => c1800002 (-1.600000e+01) (00000000)
++ vcfsx: ffbfffff ( -nan), 27 => bd000002 (-3.125001e-02) (00000000)
+
+ vctuxs: 02bfffff ( 2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 02bfffff ( 2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 02bfffff ( 2.821186e-37), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 02bfffff ( 2.821186e-37), 27 => 00000000 ( 0.000000e+00) (00000000)
+- vctuxs: 513fffff ( 5.153960e+10), 0 => ffffffff ( nan) (00000000)
+- vctuxs: 513fffff ( 5.153960e+10), 9 => ffffffff ( nan) (00000000)
+- vctuxs: 513fffff ( 5.153960e+10), 18 => ffffffff ( nan) (00000000)
+- vctuxs: 513fffff ( 5.153960e+10), 27 => ffffffff ( nan) (00000000)
++ vctuxs: 513fffff ( 5.153960e+10), 0 => ffffffff ( -nan) (00000000)
++ vctuxs: 513fffff ( 5.153960e+10), 9 => ffffffff ( -nan) (00000000)
++ vctuxs: 513fffff ( 5.153960e+10), 18 => ffffffff ( -nan) (00000000)
++ vctuxs: 513fffff ( 5.153960e+10), 27 => ffffffff ( -nan) (00000000)
+ vctuxs: 82bfffff (-2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 82bfffff (-2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 82bfffff (-2.821186e-37), 18 => 00000000 ( 0.000000e+00) (00000000)
+@@ -3537,10 +3537,10 @@ Altivec float special insns:
+ vctuxs: 80000000 (-0.000000e+00), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 80000000 (-0.000000e+00), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 80000000 (-0.000000e+00), 27 => 00000000 ( 0.000000e+00) (00000000)
+- vctuxs: 7f800000 ( inf), 0 => ffffffff ( nan) (00000000)
+- vctuxs: 7f800000 ( inf), 9 => ffffffff ( nan) (00000000)
+- vctuxs: 7f800000 ( inf), 18 => ffffffff ( nan) (00000000)
+- vctuxs: 7f800000 ( inf), 27 => ffffffff ( nan) (00000000)
++ vctuxs: 7f800000 ( inf), 0 => ffffffff ( -nan) (00000000)
++ vctuxs: 7f800000 ( inf), 9 => ffffffff ( -nan) (00000000)
++ vctuxs: 7f800000 ( inf), 18 => ffffffff ( -nan) (00000000)
++ vctuxs: 7f800000 ( inf), 27 => ffffffff ( -nan) (00000000)
+ vctuxs: ff800000 ( -inf), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: ff800000 ( -inf), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: ff800000 ( -inf), 18 => 00000000 ( 0.000000e+00) (00000000)
+@@ -3549,18 +3549,18 @@ Altivec float special insns:
+ vctuxs: 7fffffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 7fffffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 7fffffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
+- vctuxs: ffffffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
+- vctuxs: ffffffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
+- vctuxs: ffffffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
+- vctuxs: ffffffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: ffffffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: ffffffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: ffffffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: ffffffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 7fbfffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 7fbfffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 7fbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 7fbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
+- vctuxs: ffbfffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
+- vctuxs: ffbfffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
+- vctuxs: ffbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
+- vctuxs: ffbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: ffbfffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: ffbfffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: ffbfffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: ffbfffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000)
+
+ vctsxs: 02bfffff ( 2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 02bfffff ( 2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000)
+@@ -3598,17 +3598,17 @@ Altivec float special insns:
+ vctsxs: 7fffffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 7fffffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 7fffffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
+- vctsxs: ffffffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
+- vctsxs: ffffffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
+- vctsxs: ffffffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
+- vctsxs: ffffffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: ffffffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: ffffffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: ffffffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: ffffffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 7fbfffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 7fbfffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 7fbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 7fbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
+- vctsxs: ffbfffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
+- vctsxs: ffbfffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
+- vctsxs: ffbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
+- vctsxs: ffbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: ffbfffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: ffbfffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: ffbfffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: ffbfffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000)
+
+ All done. Tested 165 different instructions
+diff --git a/none/tests/ppc32/jm_vec_isa_2_07.stdout.exp b/none/tests/ppc32/jm_vec_isa_2_07.stdout.exp
+index 300b95c..8ee724a 100644
+--- a/none/tests/ppc32/jm_vec_isa_2_07.stdout.exp
++++ b/none/tests/ppc32/jm_vec_isa_2_07.stdout.exp
+@@ -443,9 +443,9 @@ vsubuqm: 0102030405060708090a0b0c0e0d0e0f @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==
+ vsubuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f ==> f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0
+ vsubuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==> 00000000000000000000000000000000
+
+-vbpermq: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f ==> 0000000000000000000000000000020a
++vbpermq: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f ==> 000000000000020a0000000000000000
+ vbpermq: 0102030405060708090a0b0c0e0d0e0f @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==> 00000000000000000000000000000000
+-vbpermq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f ==> 0000000000000000000000000000e3ea
++vbpermq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f ==> 000000000000e3ea0000000000000000
+ vbpermq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==> 00000000000000000000000000000000
+
+ vaddecuq: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000000 ==> 00000000000000000000000000000000
+diff --git a/none/tests/ppc32/round.stdout.exp b/none/tests/ppc32/round.stdout.exp
+index 7e88dd7..18efe48 100644
+--- a/none/tests/ppc32/round.stdout.exp
++++ b/none/tests/ppc32/round.stdout.exp
+@@ -324,38 +324,38 @@ zero:PASSED:fsubs(1.125000 , 0x1.00001ep-3) = 0x1p+0
+ +inf:PASSED:fsubs(-1.125000 , -0x1.00001ap-3) = -0x1p+0
+ +inf:PASSED:fsubs(-1.125000 , -0x1.00001cp-3) = -0x1p+0
+ +inf:PASSED:fsubs(-1.125000 , -0x1.00001ep-3) = -0x1p+0
+-+inf:PASSED:fsubs(1.125000 , 0x1p-3 ) = 0x1.000004p+0
+-+inf:PASSED:fsubs(1.125000 , 0x1.000002p-3) = 0x1.000004p+0
+-+inf:PASSED:fsubs(1.125000 , 0x1.000004p-3) = 0x1.000004p+0
+-+inf:PASSED:fsubs(1.125000 , 0x1.000006p-3) = 0x1.000004p+0
+-+inf:PASSED:fsubs(1.125000 , 0x1.000008p-3) = 0x1.000004p+0
+-+inf:PASSED:fsubs(1.125000 , 0x1.00000ap-3) = 0x1.000004p+0
+-+inf:PASSED:fsubs(1.125000 , 0x1.00000cp-3) = 0x1.000004p+0
+-+inf:PASSED:fsubs(1.125000 , 0x1.00000ep-3) = 0x1.000004p+0
+-+inf:PASSED:fsubs(1.125000 , 0x1.00001p-3 ) = 0x1.000002p+0
+-+inf:PASSED:fsubs(1.125000 , 0x1.000012p-3) = 0x1.000002p+0
+-+inf:PASSED:fsubs(1.125000 , 0x1.000014p-3) = 0x1.000002p+0
+-+inf:PASSED:fsubs(1.125000 , 0x1.000016p-3) = 0x1.000002p+0
+-+inf:PASSED:fsubs(1.125000 , 0x1.000018p-3) = 0x1.000002p+0
+-+inf:PASSED:fsubs(1.125000 , 0x1.00001ap-3) = 0x1.000002p+0
+-+inf:PASSED:fsubs(1.125000 , 0x1.00001cp-3) = 0x1.000002p+0
+-+inf:PASSED:fsubs(1.125000 , 0x1.00001ep-3) = 0x1.000002p+0
+--inf:PASSED:fsubs(-1.125000 , -0x1p-3 ) = -0x1.000004p+0
+--inf:PASSED:fsubs(-1.125000 , -0x1.000002p-3) = -0x1.000004p+0
+--inf:PASSED:fsubs(-1.125000 , -0x1.000004p-3) = -0x1.000004p+0
+--inf:PASSED:fsubs(-1.125000 , -0x1.000006p-3) = -0x1.000004p+0
+--inf:PASSED:fsubs(-1.125000 , -0x1.000008p-3) = -0x1.000004p+0
+--inf:PASSED:fsubs(-1.125000 , -0x1.00000ap-3) = -0x1.000004p+0
+--inf:PASSED:fsubs(-1.125000 , -0x1.00000cp-3) = -0x1.000004p+0
+--inf:PASSED:fsubs(-1.125000 , -0x1.00000ep-3) = -0x1.000004p+0
+--inf:PASSED:fsubs(-1.125000 , -0x1.00001p-3) = -0x1.000002p+0
+--inf:PASSED:fsubs(-1.125000 , -0x1.000012p-3) = -0x1.000002p+0
+--inf:PASSED:fsubs(-1.125000 , -0x1.000014p-3) = -0x1.000002p+0
+--inf:PASSED:fsubs(-1.125000 , -0x1.000016p-3) = -0x1.000002p+0
+--inf:PASSED:fsubs(-1.125000 , -0x1.000018p-3) = -0x1.000002p+0
+--inf:PASSED:fsubs(-1.125000 , -0x1.00001ap-3) = -0x1.000002p+0
+--inf:PASSED:fsubs(-1.125000 , -0x1.00001cp-3) = -0x1.000002p+0
+--inf:PASSED:fsubs(-1.125000 , -0x1.00001ep-3) = -0x1.000002p+0
+++inf:PASSED:fsubs(1.125001 , 0x1p-3 ) = 0x1.000004p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.000002p-3) = 0x1.000004p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.000004p-3) = 0x1.000004p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.000006p-3) = 0x1.000004p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.000008p-3) = 0x1.000004p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.00000ap-3) = 0x1.000004p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.00000cp-3) = 0x1.000004p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.00000ep-3) = 0x1.000004p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.00001p-3 ) = 0x1.000002p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.000012p-3) = 0x1.000002p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.000014p-3) = 0x1.000002p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.000016p-3) = 0x1.000002p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.000018p-3) = 0x1.000002p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.00001ap-3) = 0x1.000002p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.00001cp-3) = 0x1.000002p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.00001ep-3) = 0x1.000002p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1p-3 ) = -0x1.000004p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.000002p-3) = -0x1.000004p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.000004p-3) = -0x1.000004p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.000006p-3) = -0x1.000004p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.000008p-3) = -0x1.000004p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.00000ap-3) = -0x1.000004p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.00000cp-3) = -0x1.000004p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.00000ep-3) = -0x1.000004p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.00001p-3) = -0x1.000002p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.000012p-3) = -0x1.000002p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.000014p-3) = -0x1.000002p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.000016p-3) = -0x1.000002p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.000018p-3) = -0x1.000002p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.00001ap-3) = -0x1.000002p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.00001cp-3) = -0x1.000002p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.00001ep-3) = -0x1.000002p+0
+ -inf:PASSED:fsubs(1.125000 , 0x1p-3 ) = 0x1.000004p+0
+ -inf:PASSED:fsubs(1.125000 , 0x1.000002p-3) = 0x1.000002p+0
+ -inf:PASSED:fsubs(1.125000 , 0x1.000004p-3) = 0x1.000002p+0
+@@ -409,78 +409,78 @@ zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200002p+0
+ zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200004p+0
+ zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200006p+0
+ zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200008p+0
+-zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000ap+0
+-zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000cp+0
+-zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000ep+0
+-zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200012p+0
++zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ap+0
++zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000cp+0
++zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ep+0
++zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200012p+0
+ zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200014p+0
+ zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200016p+0
+ zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200018p+0
+ zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ap+0
+-zero:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001cp+0
+-zero:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001ep+0
+-zero:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20002p+0
++zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001cp+0
++zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ep+0
++zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20002p+0
+ zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.2p+0
+ zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200002p+0
+ zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200004p+0
+ zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200006p+0
+ zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200008p+0
+-zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000ap+0
+-zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000cp+0
+-zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000ep+0
+-zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200012p+0
++zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ap+0
++zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000cp+0
++zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ep+0
++zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200012p+0
+ zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200014p+0
+ zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200016p+0
+ zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200018p+0
+ zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ap+0
+-zero:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001cp+0
+-zero:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001ep+0
+-zero:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20002p+0
++zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001cp+0
++zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ep+0
++zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20002p+0
+ +inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.2p+0
+ +inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200002p+0
+ +inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200004p+0
+ +inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200006p+0
+ +inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200008p+0
+-+inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000ap+0
+-+inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000cp+0
+-+inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000ep+0
+-+inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200012p+0
+++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ap+0
+++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000cp+0
+++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ep+0
+++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200012p+0
+ +inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200014p+0
+ +inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200016p+0
+ +inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200018p+0
+ +inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ap+0
+-+inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001cp+0
+-+inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001ep+0
+-+inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20002p+0
+++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001cp+0
+++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ep+0
+++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20002p+0
+ +inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.2p+0
+-+inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200004p+0
+-+inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200006p+0
+-+inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200008p+0
+-+inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ap+0
+++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200004p+0
+++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200006p+0
+++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200008p+0
+++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000ap+0
+ +inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000cp+0
+ +inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000ep+0
+ +inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001p+0
+ +inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200012p+0
+-+inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200016p+0
+-+inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200018p+0
+-+inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ap+0
+-+inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001cp+0
+++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.200016p+0
+++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.200018p+0
+++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001ap+0
+++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001cp+0
+ +inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001ep+0
+ +inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20002p+0
+ +inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.200022p+0
+ -inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.2p+0
+--inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200004p+0
+--inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200006p+0
+--inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200008p+0
+--inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ap+0
++-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200004p+0
++-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200006p+0
++-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200008p+0
++-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000ap+0
+ -inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000cp+0
+ -inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000ep+0
+ -inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001p+0
+ -inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200012p+0
+--inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200016p+0
+--inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200018p+0
+--inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ap+0
+--inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001cp+0
++-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.200016p+0
++-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.200018p+0
++-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001ap+0
++-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001cp+0
+ -inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001ep+0
+ -inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20002p+0
+ -inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.200022p+0
+@@ -489,17 +489,17 @@ zero:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20002p+0
+ -inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200004p+0
+ -inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200006p+0
+ -inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200008p+0
+--inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000ap+0
+--inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000cp+0
+--inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000ep+0
+--inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200012p+0
++-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ap+0
++-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000cp+0
++-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ep+0
++-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200012p+0
+ -inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200014p+0
+ -inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200016p+0
+ -inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200018p+0
+ -inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ap+0
+--inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001cp+0
+--inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001ep+0
+--inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20002p+0
++-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001cp+0
++-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ep+0
++-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20002p+0
+ near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
+ near:PASSED:fdivs(-100.000000 , 0x1.c8p+5 ) = -0x1.c11f7p+0
+ near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
+@@ -566,35 +566,35 @@ zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
+ zero:PASSED:fdivs(101.000000 , 0x1.ap+5 ) = 0x1.f13b12p+0
+ +inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
+ +inf:PASSED:fdivs(-100.000000 , 0x1.c8p+5 ) = -0x1.c11f7p+0
+-+inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
+++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x0p+0
+ +inf:PASSED:fdivs(-100.000000 , 0x1.ap+5 ) = -0x1.ec4ec4p+0
+-+inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
+++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x0p+0
+ +inf:PASSED:fdivs(-100.000000 , 0x1.b8p+5 ) = -0x1.d1745cp+0
+-+inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
+++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x0p+0
+ +inf:PASSED:fdivs(-100.000000 , 0x1.98p+5 ) = -0x1.f5f5f4p+0
+-+inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
+++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x1p-149
+ +inf:PASSED:fdivs(-100.000000 , 0x1.cp+5 ) = -0x1.c92492p+0
+-+inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
+++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x1p-149
+ +inf:PASSED:fdivs(-100.000000 , 0x1.bp+5 ) = -0x1.da12f6p+0
+-+inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
+++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x1p-149
+ +inf:PASSED:fdivs(-100.000000 , 0x1.d8p+5 ) = -0x1.b1e5f6p+0
+-+inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
+++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x1p-149
+ +inf:PASSED:fdivs(-101.000000 , 0x1.ap+5 ) = -0x1.f13b12p+0
+ +inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
+ +inf:PASSED:fdivs(100.000000 , 0x1.c8p+5 ) = 0x1.c11f72p+0
+-+inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
+++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-149
+ +inf:PASSED:fdivs(100.000000 , 0x1.ap+5 ) = 0x1.ec4ec6p+0
+-+inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
+++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-149
+ +inf:PASSED:fdivs(100.000000 , 0x1.b8p+5 ) = 0x1.d1745ep+0
+-+inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
+++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-149
+ +inf:PASSED:fdivs(100.000000 , 0x1.98p+5 ) = 0x1.f5f5f6p+0
+-+inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
+++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-149
+ +inf:PASSED:fdivs(100.000000 , 0x1.cp+5 ) = 0x1.c92494p+0
+-+inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-148
+++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-148
+ +inf:PASSED:fdivs(100.000000 , 0x1.bp+5 ) = 0x1.da12f8p+0
+-+inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-148
+++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-148
+ +inf:PASSED:fdivs(100.000000 , 0x1.d8p+5 ) = 0x1.b1e5f8p+0
+-+inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-148
+++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-148
+ +inf:PASSED:fdivs(101.000000 , 0x1.ap+5 ) = 0x1.f13b14p+0
+ -inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
+ -inf:PASSED:fdivs(-100.000000 , 0x1.c8p+5 ) = -0x1.c11f72p+0
+@@ -665,78 +665,78 @@ zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+
+ zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
+ zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
+ zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
+-zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
+-zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
+-zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
+-zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
++zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
++zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
++zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
++zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
+ zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
+ zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
+ zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
+ zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
+-zero:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
+-zero:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
+-zero:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
++zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
++zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
++zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
+ zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0
+ zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0
+ zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
+ zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
+ zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
+-zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
+-zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
+-zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
+-zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
++zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
++zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
++zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
++zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
+ zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
+ zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
+ zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
+ zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
+-zero:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
+-zero:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
+-zero:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
++zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
++zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
++zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
+ +inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0
+ +inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0
+ +inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
+ +inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
+ +inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
+-+inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
+-+inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
+-+inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
+-+inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
+++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
+++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
+++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
+++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
+ +inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
+ +inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
+ +inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
+ +inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
+-+inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
+-+inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
+-+inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
+++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
+++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
+++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
+ +inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0
+-+inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
+-+inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
+-+inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00008p+0
+-+inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
+++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
+++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
+++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00008p+0
+++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
+ +inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
+ +inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
+ +inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
+ +inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
+-+inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
+-+inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
+-+inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ap+0
+-+inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
+++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
+++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
+++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ap+0
+++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
+ +inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
+ +inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
+ +inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00024p+0
+ -inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0
+--inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
+--inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
+--inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00008p+0
+--inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
++-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
++-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
++-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00008p+0
++-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
+ -inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
+ -inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
+ -inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
+ -inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
+--inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
+--inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
+--inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ap+0
+--inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
++-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
++-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
++-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ap+0
++-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
+ -inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
+ -inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
+ -inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00024p+0
+@@ -745,17 +745,17 @@ zero:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
+ -inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
+ -inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
+ -inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
+--inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
+--inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
+--inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
+--inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
++-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
++-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
++-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
++-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
+ -inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
+ -inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
+ -inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
+ -inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
+--inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
+--inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
+--inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
++-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
++-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
++-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
+ near:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0
+ near:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
+ near:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
+@@ -793,78 +793,78 @@ zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0
+ zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
+ zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
+ zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
+-zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
+-zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
+-zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
+-zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
++zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
++zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
++zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
++zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
+ zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
+ zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
+ zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
+ zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
+-zero:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
+-zero:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
+-zero:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
++zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
++zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
++zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
+ zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0
+ zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0
+ zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
+ zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
+ zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
+-zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
+-zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
+-zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
+-zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
++zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
++zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
++zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
++zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
+ zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
+ zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
+ zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
+ zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
+-zero:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
+-zero:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
+-zero:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
++zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
++zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
++zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
+ +inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0
+ +inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0
+ +inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
+ +inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
+ +inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
+-+inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
+-+inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
+-+inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
+-+inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
+++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
+++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
+++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
+++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
+ +inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
+ +inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
+ +inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
+ +inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
+-+inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
+-+inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
+-+inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
+++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
+++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
+++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
+ +inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0
+-+inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
+-+inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
+-+inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00008p+0
+-+inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
+++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
+++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
+++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00008p+0
+++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
+ +inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
+ +inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
+ +inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
+ +inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
+-+inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
+-+inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
+-+inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ap+0
+-+inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
+++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
+++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
+++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ap+0
+++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
+ +inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
+ +inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
+ +inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00024p+0
+ -inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0
+--inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
+--inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
+--inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00008p+0
+--inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
++-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
++-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
++-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00008p+0
++-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
+ -inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
+ -inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
+ -inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
+ -inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
+--inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
+--inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
+--inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ap+0
+--inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
++-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
++-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
++-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ap+0
++-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
+ -inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
+ -inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
+ -inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00024p+0
+@@ -873,17 +873,17 @@ zero:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
+ -inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
+ -inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
+ -inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
+--inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
+--inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
+--inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
+--inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
++-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
++-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
++-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
++-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
+ -inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
+ -inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
+ -inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
+ -inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
+--inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
+--inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
+--inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
++-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
++-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
++-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
+ near:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0
+ near:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
+ near:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
+@@ -921,78 +921,78 @@ zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+
+ zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
+ zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
+ zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
+-zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
+-zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
+-zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
+-zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
++zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
++zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
++zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
++zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
+ zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
+ zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
+ zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
+ zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
+-zero:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
+-zero:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
+-zero:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
++zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
++zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
++zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
+ zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0
+ zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0
+ zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
+ zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
+ zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
+-zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
+-zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
+-zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
+-zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
++zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
++zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
++zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
++zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
+ zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
+ zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
+ zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
+ zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
+-zero:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
+-zero:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
+-zero:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
++zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
++zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
++zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
+ +inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0
+ +inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0
+ +inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
+ +inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
+ +inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
+-+inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
+-+inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
+-+inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
+-+inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
+++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
+++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
+++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
+++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
+ +inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
+ +inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
+ +inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
+ +inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
+-+inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
+-+inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
+-+inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
+++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
+++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
+++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
+ +inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0
+-+inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
+-+inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
+-+inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00008p+0
+-+inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
+++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
+++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
+++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00008p+0
+++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
+ +inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
+ +inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
+ +inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
+ +inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
+-+inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
+-+inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
+-+inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ap+0
+-+inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
+++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
+++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
+++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ap+0
+++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
+ +inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
+ +inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
+ +inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00024p+0
+ -inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0
+--inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
+--inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
+--inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00008p+0
+--inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
++-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
++-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
++-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00008p+0
++-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
+ -inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
+ -inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
+ -inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
+ -inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
+--inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
+--inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
+--inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ap+0
+--inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
++-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
++-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
++-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ap+0
++-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
+ -inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
+ -inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
+ -inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00024p+0
+@@ -1001,17 +1001,17 @@ zero:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+
+ -inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
+ -inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
+ -inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
+--inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
+--inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
+--inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
+--inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
++-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
++-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
++-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
++-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
+ -inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
+ -inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
+ -inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
+ -inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
+--inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
+--inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
+--inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
++-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
++-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
++-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
+ near:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0
+ near:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
+ near:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
+@@ -1049,78 +1049,78 @@ zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0
+ zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
+ zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
+ zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
+-zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
+-zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
+-zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
+-zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
++zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
++zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
++zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
++zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
+ zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
+ zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
+ zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
+ zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
+-zero:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
+-zero:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
+-zero:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
++zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
++zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
++zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
+ zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0
+ zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0
+ zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
+ zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
+ zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
+-zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
+-zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
+-zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
+-zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
++zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
++zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
++zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
++zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
+ zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
+ zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
+ zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
+ zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
+-zero:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
+-zero:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
+-zero:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
++zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
++zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
++zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
+ +inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0
+ +inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0
+ +inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
+ +inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
+ +inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
+-+inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
+-+inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
+-+inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
+-+inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
+++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
+++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
+++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
+++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
+ +inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
+ +inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
+ +inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
+ +inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
+-+inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
+-+inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
+-+inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
+++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
+++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
+++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
+ +inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0
+-+inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
+-+inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
+-+inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00008p+0
+-+inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
+++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
+++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
+++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00008p+0
+++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
+ +inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
+ +inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
+ +inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
+ +inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
+-+inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
+-+inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
+-+inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ap+0
+-+inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
+++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
+++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
+++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ap+0
+++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
+ +inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
+ +inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
+ +inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00024p+0
+ -inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0
+--inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
+--inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
+--inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00008p+0
+--inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
++-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
++-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
++-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00008p+0
++-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
+ -inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
+ -inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
+ -inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
+ -inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
+--inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
+--inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
+--inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ap+0
+--inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
++-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
++-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
++-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ap+0
++-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
+ -inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
+ -inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
+ -inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00024p+0
+@@ -1129,17 +1129,17 @@ zero:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p
+ -inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
+ -inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
+ -inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
+--inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
+--inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
+--inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
+--inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
++-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
++-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
++-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
++-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
+ -inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
+ -inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
+ -inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
+ -inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
+--inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
+--inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
+--inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
++-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
++-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
++-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
+ -------------------------- test rounding of double operators with guard bits --------------------------
+ near:PASSED:fadd(-0x1p+0 , -0x1p-3 ) = -0x1.2p+0
+ near:PASSED:fadd(-0x1p+0 , -0x1.0000000000001p-3) = -0x1.2p+0
+diff --git a/none/tests/ppc32/round.stdout.exp-RM-fix b/none/tests/ppc32/round.stdout.exp-RM-fix
+new file mode 100644
+index 0000000..18efe48
+--- /dev/null
++++ b/none/tests/ppc32/round.stdout.exp-RM-fix
+@@ -0,0 +1,2335 @@
++-------------------------- test denormalized convert --------------------------
++near:PASSED:(double)(0x1p-148 ) = 0x1.cp-149
++near:PASSED:(double)(0x1p-149 ) = 0x1.4p-149
++zero:PASSED:(double)(0x1p-149 ) = 0x1.cp-149
++zero:PASSED:(double)(0x1p-149 ) = 0x1.4p-149
+++inf:PASSED:(double)(0x1p-148 ) = 0x1.cp-149
+++inf:PASSED:(double)(0x1p-148 ) = 0x1.4p-149
++-inf:PASSED:(double)(0x1p-149 ) = 0x1.cp-149
++-inf:PASSED:(double)(0x1p-149 ) = 0x1.4p-149
++-------------------------- test normalized convert --------------------------
++near:PASSED:(double)(0x1.000004p-126 ) = 0x1.0000038p-126
++near:PASSED:(double)(0x1.000002p-126 ) = 0x1.0000028p-126
++zero:PASSED:(double)(0x1.000002p-126 ) = 0x1.0000038p-126
++zero:PASSED:(double)(0x1.000002p-126 ) = 0x1.0000028p-126
+++inf:PASSED:(double)(0x1.000004p-126 ) = 0x1.0000038p-126
+++inf:PASSED:(double)(0x1.000004p-126 ) = 0x1.0000028p-126
++-inf:PASSED:(double)(0x1.000002p-126 ) = 0x1.0000038p-126
++-inf:PASSED:(double)(0x1.000002p-126 ) = 0x1.0000028p-126
++-------------------------- test (float)int convert --------------------------
++near:PASSED:(float)( int) 67047421 = 67047420.0
++near:PASSED:(float)( int) 67047423 = 67047424.0
++zero:PASSED:(float)( int) 67047421 = 67047420.0
++zero:PASSED:(float)( int) 67047423 = 67047420.0
+++inf:PASSED:(float)( int) 67047421 = 67047424.0
+++inf:PASSED:(float)( int) 67047423 = 67047424.0
++-inf:PASSED:(float)( int) 67047421 = 67047420.0
++-inf:PASSED:(float)( int) 67047423 = 67047420.0
++near:PASSED:(float)( int)-67047421 = -67047420.0
++near:PASSED:(float)( int)-67047423 = -67047424.0
++zero:PASSED:(float)( int)-67047421 = -67047420.0
++zero:PASSED:(float)( int)-67047423 = -67047420.0
+++inf:PASSED:(float)( int)-67047421 = -67047420.0
+++inf:PASSED:(float)( int)-67047423 = -67047420.0
++-inf:PASSED:(float)( int)-67047421 = -67047424.0
++-inf:PASSED:(float)( int)-67047423 = -67047424.0
++-------------------------- test (float)int convert --------------------------
++near:PASSED:(float)( int) 67047421 = 67047420.0
++near:PASSED:(float)( int) 67047423 = 67047424.0
++zero:PASSED:(float)( int) 67047421 = 67047420.0
++zero:PASSED:(float)( int) 67047423 = 67047420.0
+++inf:PASSED:(float)( int) 67047421 = 67047424.0
+++inf:PASSED:(float)( int) 67047423 = 67047424.0
++-inf:PASSED:(float)( int) 67047421 = 67047420.0
++-inf:PASSED:(float)( int) 67047423 = 67047420.0
++near:PASSED:(float)( int)-67047421 = -67047420.0
++near:PASSED:(float)( int)-67047423 = -67047424.0
++zero:PASSED:(float)( int)-67047421 = -67047420.0
++zero:PASSED:(float)( int)-67047423 = -67047420.0
+++inf:PASSED:(float)( int)-67047421 = -67047420.0
+++inf:PASSED:(float)( int)-67047423 = -67047420.0
++-inf:PASSED:(float)( int)-67047421 = -67047424.0
++-inf:PASSED:(float)( int)-67047423 = -67047424.0
++-------------------------- test rounding of float operators without guard bits --------------------------
++near:PASSED:fadds(-0x1p-149 , -0x1p-151 ) = -0x1p-149
++near:PASSED:fadds(-0x1p-149 , -0x1.8p-150 ) = -0x1p-148
++near:PASSED:fadds(0x1p-149 , 0x1p-151 ) = 0x1p-149
++near:PASSED:fadds(0x1p-149 , 0x1.8p-150 ) = 0x1p-148
++zero:PASSED:fadds(-0x1p-149 , -0x1p-151 ) = -0x1p-149
++zero:PASSED:fadds(-0x1p-149 , -0x1.8p-150 ) = -0x1p-149
++zero:PASSED:fadds(0x1p-149 , 0x1p-151 ) = 0x1p-149
++zero:PASSED:fadds(0x1p-149 , 0x1.8p-150 ) = 0x1p-149
+++inf:PASSED:fadds(-0x1p-149 , -0x1p-151 ) = -0x1p-149
+++inf:PASSED:fadds(-0x1p-149 , -0x1.8p-150 ) = -0x1p-149
+++inf:PASSED:fadds(0x1p-149 , 0x1p-151 ) = 0x1p-148
+++inf:PASSED:fadds(0x1p-149 , 0x1.8p-150 ) = 0x1p-148
++-inf:PASSED:fadds(-0x1p-149 , -0x1p-151 ) = -0x1p-148
++-inf:PASSED:fadds(-0x1p-149 , -0x1.8p-150 ) = -0x1p-148
++-inf:PASSED:fadds(0x1p-149 , 0x1p-151 ) = 0x1p-149
++-inf:PASSED:fadds(0x1p-149 , 0x1.8p-150 ) = 0x1p-149
++near:PASSED:fsubs(-0x1p-148 , -0x1.8p-150 ) = -0x1p-149
++near:PASSED:fsubs(-0x1p-148 , -0x1p-151 ) = -0x1p-148
++near:PASSED:fsubs(0x1p-148 , 0x1.8p-150 ) = 0x1p-149
++near:PASSED:fsubs(0x1p-148 , 0x1p-151 ) = 0x1p-148
++zero:PASSED:fsubs(-0x1p-148 , -0x1.8p-150 ) = -0x1p-149
++zero:PASSED:fsubs(-0x1p-148 , -0x1p-151 ) = -0x1p-149
++zero:PASSED:fsubs(0x1p-148 , 0x1.8p-150 ) = 0x1p-149
++zero:PASSED:fsubs(0x1p-148 , 0x1p-151 ) = 0x1p-149
+++inf:PASSED:fsubs(-0x1p-148 , -0x1.8p-150 ) = -0x1p-149
+++inf:PASSED:fsubs(-0x1p-148 , -0x1p-151 ) = -0x1p-149
+++inf:PASSED:fsubs(0x1p-148 , 0x1.8p-150 ) = 0x1p-148
+++inf:PASSED:fsubs(0x1p-148 , 0x1p-151 ) = 0x1p-148
++-inf:PASSED:fsubs(-0x1p-148 , -0x1.8p-150 ) = -0x1p-148
++-inf:PASSED:fsubs(-0x1p-148 , -0x1p-151 ) = -0x1p-148
++-inf:PASSED:fsubs(0x1p-148 , 0x1.8p-150 ) = 0x1p-149
++-inf:PASSED:fsubs(0x1p-148 , 0x1p-151 ) = 0x1p-149
++near:PASSED:fmuls(0x1p-1 , -0x1.4p-148 ) = -0x1p-149
++near:PASSED:fmuls(0x1p-1 , -0x1.cp-148 ) = -0x1p-148
++near:PASSED:fmuls(0x1p-1 , 0x1.4p-148 ) = 0x1p-149
++near:PASSED:fmuls(0x1p-1 , 0x1.cp-148 ) = 0x1p-148
++zero:PASSED:fmuls(0x1p-1 , -0x1.4p-148 ) = -0x1p-149
++zero:PASSED:fmuls(0x1p-1 , -0x1.cp-148 ) = -0x1p-149
++zero:PASSED:fmuls(0x1p-1 , 0x1.4p-148 ) = 0x1p-149
++zero:PASSED:fmuls(0x1p-1 , 0x1.cp-148 ) = 0x1p-149
+++inf:PASSED:fmuls(0x1p-1 , -0x1.4p-148 ) = -0x1p-149
+++inf:PASSED:fmuls(0x1p-1 , -0x1.cp-148 ) = -0x1p-149
+++inf:PASSED:fmuls(0x1p-1 , 0x1.4p-148 ) = 0x1p-148
+++inf:PASSED:fmuls(0x1p-1 , 0x1.cp-148 ) = 0x1p-148
++-inf:PASSED:fmuls(0x1p-1 , -0x1.4p-148 ) = -0x1p-148
++-inf:PASSED:fmuls(0x1p-1 , -0x1.cp-148 ) = -0x1p-148
++-inf:PASSED:fmuls(0x1p-1 , 0x1.4p-148 ) = 0x1p-149
++-inf:PASSED:fmuls(0x1p-1 , 0x1.cp-148 ) = 0x1p-149
++near:PASSED:fdivs(-0x1.4p-148 , 0x1p+1 ) = -0x1p-149
++near:PASSED:fdivs(-0x1.cp-148 , 0x1p+1 ) = -0x1p-148
++near:PASSED:fdivs(0x1.4p-148 , 0x1p+1 ) = 0x1p-149
++near:PASSED:fdivs(0x1.cp-148 , 0x1p+1 ) = 0x1p-148
++zero:PASSED:fdivs(-0x1.4p-148 , 0x1p+1 ) = -0x1p-149
++zero:PASSED:fdivs(-0x1.cp-148 , 0x1p+1 ) = -0x1p-149
++zero:PASSED:fdivs(0x1.4p-148 , 0x1p+1 ) = 0x1p-149
++zero:PASSED:fdivs(0x1.cp-148 , 0x1p+1 ) = 0x1p-149
+++inf:PASSED:fdivs(-0x1.4p-148 , 0x1p+1 ) = -0x1p-149
+++inf:PASSED:fdivs(-0x1.cp-148 , 0x1p+1 ) = -0x1p-149
+++inf:PASSED:fdivs(0x1.4p-148 , 0x1p+1 ) = 0x1p-148
+++inf:PASSED:fdivs(0x1.cp-148 , 0x1p+1 ) = 0x1p-148
++-inf:PASSED:fdivs(-0x1.4p-148 , 0x1p+1 ) = -0x1p-148
++-inf:PASSED:fdivs(-0x1.cp-148 , 0x1p+1 ) = -0x1p-148
++-inf:PASSED:fdivs(0x1.4p-148 , 0x1p+1 ) = 0x1p-149
++-inf:PASSED:fdivs(0x1.cp-148 , 0x1p+1 ) = 0x1p-149
++-------------------------- test rounding of float operators with guard bits --------------------------
++near:PASSED:fadds(-1.000000 , -0x1p-3 ) = -0x1.2p+0
++near:PASSED:fadds(-1.000000 , -0x1.000002p-3) = -0x1.2p+0
++near:PASSED:fadds(-1.000000 , -0x1.000004p-3) = -0x1.2p+0
++near:PASSED:fadds(-1.000000 , -0x1.000006p-3) = -0x1.2p+0
++near:PASSED:fadds(-1.000000 , -0x1.000008p-3) = -0x1.2p+0
++near:PASSED:fadds(-1.000000 , -0x1.00000ap-3) = -0x1.200002p+0
++near:PASSED:fadds(-1.000000 , -0x1.00000cp-3) = -0x1.200002p+0
++near:PASSED:fadds(-1.000000 , -0x1.00000ep-3) = -0x1.200002p+0
++near:PASSED:fadds(-1.000000 , -0x1.00001p-3) = -0x1.200002p+0
++near:PASSED:fadds(-1.000000 , -0x1.000012p-3) = -0x1.200002p+0
++near:PASSED:fadds(-1.000000 , -0x1.000014p-3) = -0x1.200002p+0
++near:PASSED:fadds(-1.000000 , -0x1.000016p-3) = -0x1.200002p+0
++near:PASSED:fadds(-1.000000 , -0x1.000018p-3) = -0x1.200004p+0
++near:PASSED:fadds(-1.000000 , -0x1.00001ap-3) = -0x1.200004p+0
++near:PASSED:fadds(-1.000000 , -0x1.00001cp-3) = -0x1.200004p+0
++near:PASSED:fadds(-1.000000 , -0x1.00001ep-3) = -0x1.200004p+0
++near:PASSED:fadds(1.000000 , 0x1p-3 ) = 0x1.2p+0
++near:PASSED:fadds(1.000000 , 0x1.000002p-3) = 0x1.2p+0
++near:PASSED:fadds(1.000000 , 0x1.000004p-3) = 0x1.2p+0
++near:PASSED:fadds(1.000000 , 0x1.000006p-3) = 0x1.2p+0
++near:PASSED:fadds(1.000000 , 0x1.000008p-3) = 0x1.2p+0
++near:PASSED:fadds(1.000000 , 0x1.00000ap-3) = 0x1.200002p+0
++near:PASSED:fadds(1.000000 , 0x1.00000cp-3) = 0x1.200002p+0
++near:PASSED:fadds(1.000000 , 0x1.00000ep-3) = 0x1.200002p+0
++near:PASSED:fadds(1.000000 , 0x1.00001p-3 ) = 0x1.200002p+0
++near:PASSED:fadds(1.000000 , 0x1.000012p-3) = 0x1.200002p+0
++near:PASSED:fadds(1.000000 , 0x1.000014p-3) = 0x1.200002p+0
++near:PASSED:fadds(1.000000 , 0x1.000016p-3) = 0x1.200002p+0
++near:PASSED:fadds(1.000000 , 0x1.000018p-3) = 0x1.200004p+0
++near:PASSED:fadds(1.000000 , 0x1.00001ap-3) = 0x1.200004p+0
++near:PASSED:fadds(1.000000 , 0x1.00001cp-3) = 0x1.200004p+0
++near:PASSED:fadds(1.000000 , 0x1.00001ep-3) = 0x1.200004p+0
++zero:PASSED:fadds(-1.000000 , -0x1p-3 ) = -0x1.2p+0
++zero:PASSED:fadds(-1.000000 , -0x1.000002p-3) = -0x1.2p+0
++zero:PASSED:fadds(-1.000000 , -0x1.000004p-3) = -0x1.2p+0
++zero:PASSED:fadds(-1.000000 , -0x1.000006p-3) = -0x1.2p+0
++zero:PASSED:fadds(-1.000000 , -0x1.000008p-3) = -0x1.2p+0
++zero:PASSED:fadds(-1.000000 , -0x1.00000ap-3) = -0x1.2p+0
++zero:PASSED:fadds(-1.000000 , -0x1.00000cp-3) = -0x1.2p+0
++zero:PASSED:fadds(-1.000000 , -0x1.00000ep-3) = -0x1.2p+0
++zero:PASSED:fadds(-1.000000 , -0x1.00001p-3) = -0x1.200002p+0
++zero:PASSED:fadds(-1.000000 , -0x1.000012p-3) = -0x1.200002p+0
++zero:PASSED:fadds(-1.000000 , -0x1.000014p-3) = -0x1.200002p+0
++zero:PASSED:fadds(-1.000000 , -0x1.000016p-3) = -0x1.200002p+0
++zero:PASSED:fadds(-1.000000 , -0x1.000018p-3) = -0x1.200002p+0
++zero:PASSED:fadds(-1.000000 , -0x1.00001ap-3) = -0x1.200002p+0
++zero:PASSED:fadds(-1.000000 , -0x1.00001cp-3) = -0x1.200002p+0
++zero:PASSED:fadds(-1.000000 , -0x1.00001ep-3) = -0x1.200002p+0
++zero:PASSED:fadds(1.000000 , 0x1p-3 ) = 0x1.2p+0
++zero:PASSED:fadds(1.000000 , 0x1.000002p-3) = 0x1.2p+0
++zero:PASSED:fadds(1.000000 , 0x1.000004p-3) = 0x1.2p+0
++zero:PASSED:fadds(1.000000 , 0x1.000006p-3) = 0x1.2p+0
++zero:PASSED:fadds(1.000000 , 0x1.000008p-3) = 0x1.2p+0
++zero:PASSED:fadds(1.000000 , 0x1.00000ap-3) = 0x1.2p+0
++zero:PASSED:fadds(1.000000 , 0x1.00000cp-3) = 0x1.2p+0
++zero:PASSED:fadds(1.000000 , 0x1.00000ep-3) = 0x1.2p+0
++zero:PASSED:fadds(1.000000 , 0x1.00001p-3 ) = 0x1.200002p+0
++zero:PASSED:fadds(1.000000 , 0x1.000012p-3) = 0x1.200002p+0
++zero:PASSED:fadds(1.000000 , 0x1.000014p-3) = 0x1.200002p+0
++zero:PASSED:fadds(1.000000 , 0x1.000016p-3) = 0x1.200002p+0
++zero:PASSED:fadds(1.000000 , 0x1.000018p-3) = 0x1.200002p+0
++zero:PASSED:fadds(1.000000 , 0x1.00001ap-3) = 0x1.200002p+0
++zero:PASSED:fadds(1.000000 , 0x1.00001cp-3) = 0x1.200002p+0
++zero:PASSED:fadds(1.000000 , 0x1.00001ep-3) = 0x1.200002p+0
+++inf:PASSED:fadds(-1.000000 , -0x1p-3 ) = -0x1.2p+0
+++inf:PASSED:fadds(-1.000000 , -0x1.000002p-3) = -0x1.2p+0
+++inf:PASSED:fadds(-1.000000 , -0x1.000004p-3) = -0x1.2p+0
+++inf:PASSED:fadds(-1.000000 , -0x1.000006p-3) = -0x1.2p+0
+++inf:PASSED:fadds(-1.000000 , -0x1.000008p-3) = -0x1.2p+0
+++inf:PASSED:fadds(-1.000000 , -0x1.00000ap-3) = -0x1.2p+0
+++inf:PASSED:fadds(-1.000000 , -0x1.00000cp-3) = -0x1.2p+0
+++inf:PASSED:fadds(-1.000000 , -0x1.00000ep-3) = -0x1.2p+0
+++inf:PASSED:fadds(-1.000000 , -0x1.00001p-3) = -0x1.200002p+0
+++inf:PASSED:fadds(-1.000000 , -0x1.000012p-3) = -0x1.200002p+0
+++inf:PASSED:fadds(-1.000000 , -0x1.000014p-3) = -0x1.200002p+0
+++inf:PASSED:fadds(-1.000000 , -0x1.000016p-3) = -0x1.200002p+0
+++inf:PASSED:fadds(-1.000000 , -0x1.000018p-3) = -0x1.200002p+0
+++inf:PASSED:fadds(-1.000000 , -0x1.00001ap-3) = -0x1.200002p+0
+++inf:PASSED:fadds(-1.000000 , -0x1.00001cp-3) = -0x1.200002p+0
+++inf:PASSED:fadds(-1.000000 , -0x1.00001ep-3) = -0x1.200002p+0
+++inf:PASSED:fadds(1.000000 , 0x1p-3 ) = 0x1.2p+0
+++inf:PASSED:fadds(1.000000 , 0x1.000002p-3) = 0x1.200002p+0
+++inf:PASSED:fadds(1.000000 , 0x1.000004p-3) = 0x1.200002p+0
+++inf:PASSED:fadds(1.000000 , 0x1.000006p-3) = 0x1.200002p+0
+++inf:PASSED:fadds(1.000000 , 0x1.000008p-3) = 0x1.200002p+0
+++inf:PASSED:fadds(1.000000 , 0x1.00000ap-3) = 0x1.200002p+0
+++inf:PASSED:fadds(1.000000 , 0x1.00000cp-3) = 0x1.200002p+0
+++inf:PASSED:fadds(1.000000 , 0x1.00000ep-3) = 0x1.200002p+0
+++inf:PASSED:fadds(1.000000 , 0x1.00001p-3 ) = 0x1.200002p+0
+++inf:PASSED:fadds(1.000000 , 0x1.000012p-3) = 0x1.200004p+0
+++inf:PASSED:fadds(1.000000 , 0x1.000014p-3) = 0x1.200004p+0
+++inf:PASSED:fadds(1.000000 , 0x1.000016p-3) = 0x1.200004p+0
+++inf:PASSED:fadds(1.000000 , 0x1.000018p-3) = 0x1.200004p+0
+++inf:PASSED:fadds(1.000000 , 0x1.00001ap-3) = 0x1.200004p+0
+++inf:PASSED:fadds(1.000000 , 0x1.00001cp-3) = 0x1.200004p+0
+++inf:PASSED:fadds(1.000000 , 0x1.00001ep-3) = 0x1.200004p+0
++-inf:PASSED:fadds(-1.000000 , -0x1p-3 ) = -0x1.2p+0
++-inf:PASSED:fadds(-1.000000 , -0x1.000002p-3) = -0x1.200002p+0
++-inf:PASSED:fadds(-1.000000 , -0x1.000004p-3) = -0x1.200002p+0
++-inf:PASSED:fadds(-1.000000 , -0x1.000006p-3) = -0x1.200002p+0
++-inf:PASSED:fadds(-1.000000 , -0x1.000008p-3) = -0x1.200002p+0
++-inf:PASSED:fadds(-1.000000 , -0x1.00000ap-3) = -0x1.200002p+0
++-inf:PASSED:fadds(-1.000000 , -0x1.00000cp-3) = -0x1.200002p+0
++-inf:PASSED:fadds(-1.000000 , -0x1.00000ep-3) = -0x1.200002p+0
++-inf:PASSED:fadds(-1.000000 , -0x1.00001p-3) = -0x1.200002p+0
++-inf:PASSED:fadds(-1.000000 , -0x1.000012p-3) = -0x1.200004p+0
++-inf:PASSED:fadds(-1.000000 , -0x1.000014p-3) = -0x1.200004p+0
++-inf:PASSED:fadds(-1.000000 , -0x1.000016p-3) = -0x1.200004p+0
++-inf:PASSED:fadds(-1.000000 , -0x1.000018p-3) = -0x1.200004p+0
++-inf:PASSED:fadds(-1.000000 , -0x1.00001ap-3) = -0x1.200004p+0
++-inf:PASSED:fadds(-1.000000 , -0x1.00001cp-3) = -0x1.200004p+0
++-inf:PASSED:fadds(-1.000000 , -0x1.00001ep-3) = -0x1.200004p+0
++-inf:PASSED:fadds(1.000000 , 0x1p-3 ) = 0x1.2p+0
++-inf:PASSED:fadds(1.000000 , 0x1.000002p-3) = 0x1.2p+0
++-inf:PASSED:fadds(1.000000 , 0x1.000004p-3) = 0x1.2p+0
++-inf:PASSED:fadds(1.000000 , 0x1.000006p-3) = 0x1.2p+0
++-inf:PASSED:fadds(1.000000 , 0x1.000008p-3) = 0x1.2p+0
++-inf:PASSED:fadds(1.000000 , 0x1.00000ap-3) = 0x1.2p+0
++-inf:PASSED:fadds(1.000000 , 0x1.00000cp-3) = 0x1.2p+0
++-inf:PASSED:fadds(1.000000 , 0x1.00000ep-3) = 0x1.2p+0
++-inf:PASSED:fadds(1.000000 , 0x1.00001p-3 ) = 0x1.200002p+0
++-inf:PASSED:fadds(1.000000 , 0x1.000012p-3) = 0x1.200002p+0
++-inf:PASSED:fadds(1.000000 , 0x1.000014p-3) = 0x1.200002p+0
++-inf:PASSED:fadds(1.000000 , 0x1.000016p-3) = 0x1.200002p+0
++-inf:PASSED:fadds(1.000000 , 0x1.000018p-3) = 0x1.200002p+0
++-inf:PASSED:fadds(1.000000 , 0x1.00001ap-3) = 0x1.200002p+0
++-inf:PASSED:fadds(1.000000 , 0x1.00001cp-3) = 0x1.200002p+0
++-inf:PASSED:fadds(1.000000 , 0x1.00001ep-3) = 0x1.200002p+0
++near:PASSED:fsubs(-1.125000 , -0x1p-3 ) = -0x1.000004p+0
++near:PASSED:fsubs(-1.125000 , -0x1.000002p-3) = -0x1.000004p+0
++near:PASSED:fsubs(-1.125000 , -0x1.000004p-3) = -0x1.000004p+0
++near:PASSED:fsubs(-1.125000 , -0x1.000006p-3) = -0x1.000004p+0
++near:PASSED:fsubs(-1.125000 , -0x1.000008p-3) = -0x1.000004p+0
++near:PASSED:fsubs(-1.125000 , -0x1.00000ap-3) = -0x1.000002p+0
++near:PASSED:fsubs(-1.125000 , -0x1.00000cp-3) = -0x1.000002p+0
++near:PASSED:fsubs(-1.125000 , -0x1.00000ep-3) = -0x1.000002p+0
++near:PASSED:fsubs(-1.125000 , -0x1.00001p-3) = -0x1.000002p+0
++near:PASSED:fsubs(-1.125000 , -0x1.000012p-3) = -0x1.000002p+0
++near:PASSED:fsubs(-1.125000 , -0x1.000014p-3) = -0x1.000002p+0
++near:PASSED:fsubs(-1.125000 , -0x1.000016p-3) = -0x1.000002p+0
++near:PASSED:fsubs(-1.125000 , -0x1.000018p-3) = -0x1p+0
++near:PASSED:fsubs(-1.125000 , -0x1.00001ap-3) = -0x1p+0
++near:PASSED:fsubs(-1.125000 , -0x1.00001cp-3) = -0x1p+0
++near:PASSED:fsubs(-1.125000 , -0x1.00001ep-3) = -0x1p+0
++near:PASSED:fsubs(1.125000 , 0x1p-3 ) = 0x1.000004p+0
++near:PASSED:fsubs(1.125000 , 0x1.000002p-3) = 0x1.000004p+0
++near:PASSED:fsubs(1.125000 , 0x1.000004p-3) = 0x1.000004p+0
++near:PASSED:fsubs(1.125000 , 0x1.000006p-3) = 0x1.000004p+0
++near:PASSED:fsubs(1.125000 , 0x1.000008p-3) = 0x1.000004p+0
++near:PASSED:fsubs(1.125000 , 0x1.00000ap-3) = 0x1.000002p+0
++near:PASSED:fsubs(1.125000 , 0x1.00000cp-3) = 0x1.000002p+0
++near:PASSED:fsubs(1.125000 , 0x1.00000ep-3) = 0x1.000002p+0
++near:PASSED:fsubs(1.125000 , 0x1.00001p-3 ) = 0x1.000002p+0
++near:PASSED:fsubs(1.125000 , 0x1.000012p-3) = 0x1.000002p+0
++near:PASSED:fsubs(1.125000 , 0x1.000014p-3) = 0x1.000002p+0
++near:PASSED:fsubs(1.125000 , 0x1.000016p-3) = 0x1.000002p+0
++near:PASSED:fsubs(1.125000 , 0x1.000018p-3) = 0x1p+0
++near:PASSED:fsubs(1.125000 , 0x1.00001ap-3) = 0x1p+0
++near:PASSED:fsubs(1.125000 , 0x1.00001cp-3) = 0x1p+0
++near:PASSED:fsubs(1.125000 , 0x1.00001ep-3) = 0x1p+0
++zero:PASSED:fsubs(-1.125000 , -0x1p-3 ) = -0x1.000004p+0
++zero:PASSED:fsubs(-1.125000 , -0x1.000002p-3) = -0x1.000002p+0
++zero:PASSED:fsubs(-1.125000 , -0x1.000004p-3) = -0x1.000002p+0
++zero:PASSED:fsubs(-1.125000 , -0x1.000006p-3) = -0x1.000002p+0
++zero:PASSED:fsubs(-1.125000 , -0x1.000008p-3) = -0x1.000002p+0
++zero:PASSED:fsubs(-1.125000 , -0x1.00000ap-3) = -0x1.000002p+0
++zero:PASSED:fsubs(-1.125000 , -0x1.00000cp-3) = -0x1.000002p+0
++zero:PASSED:fsubs(-1.125000 , -0x1.00000ep-3) = -0x1.000002p+0
++zero:PASSED:fsubs(-1.125000 , -0x1.00001p-3) = -0x1.000002p+0
++zero:PASSED:fsubs(-1.125000 , -0x1.000012p-3) = -0x1p+0
++zero:PASSED:fsubs(-1.125000 , -0x1.000014p-3) = -0x1p+0
++zero:PASSED:fsubs(-1.125000 , -0x1.000016p-3) = -0x1p+0
++zero:PASSED:fsubs(-1.125000 , -0x1.000018p-3) = -0x1p+0
++zero:PASSED:fsubs(-1.125000 , -0x1.00001ap-3) = -0x1p+0
++zero:PASSED:fsubs(-1.125000 , -0x1.00001cp-3) = -0x1p+0
++zero:PASSED:fsubs(-1.125000 , -0x1.00001ep-3) = -0x1p+0
++zero:PASSED:fsubs(1.125000 , 0x1p-3 ) = 0x1.000004p+0
++zero:PASSED:fsubs(1.125000 , 0x1.000002p-3) = 0x1.000002p+0
++zero:PASSED:fsubs(1.125000 , 0x1.000004p-3) = 0x1.000002p+0
++zero:PASSED:fsubs(1.125000 , 0x1.000006p-3) = 0x1.000002p+0
++zero:PASSED:fsubs(1.125000 , 0x1.000008p-3) = 0x1.000002p+0
++zero:PASSED:fsubs(1.125000 , 0x1.00000ap-3) = 0x1.000002p+0
++zero:PASSED:fsubs(1.125000 , 0x1.00000cp-3) = 0x1.000002p+0
++zero:PASSED:fsubs(1.125000 , 0x1.00000ep-3) = 0x1.000002p+0
++zero:PASSED:fsubs(1.125000 , 0x1.00001p-3 ) = 0x1.000002p+0
++zero:PASSED:fsubs(1.125000 , 0x1.000012p-3) = 0x1p+0
++zero:PASSED:fsubs(1.125000 , 0x1.000014p-3) = 0x1p+0
++zero:PASSED:fsubs(1.125000 , 0x1.000016p-3) = 0x1p+0
++zero:PASSED:fsubs(1.125000 , 0x1.000018p-3) = 0x1p+0
++zero:PASSED:fsubs(1.125000 , 0x1.00001ap-3) = 0x1p+0
++zero:PASSED:fsubs(1.125000 , 0x1.00001cp-3) = 0x1p+0
++zero:PASSED:fsubs(1.125000 , 0x1.00001ep-3) = 0x1p+0
+++inf:PASSED:fsubs(-1.125000 , -0x1p-3 ) = -0x1.000004p+0
+++inf:PASSED:fsubs(-1.125000 , -0x1.000002p-3) = -0x1.000002p+0
+++inf:PASSED:fsubs(-1.125000 , -0x1.000004p-3) = -0x1.000002p+0
+++inf:PASSED:fsubs(-1.125000 , -0x1.000006p-3) = -0x1.000002p+0
+++inf:PASSED:fsubs(-1.125000 , -0x1.000008p-3) = -0x1.000002p+0
+++inf:PASSED:fsubs(-1.125000 , -0x1.00000ap-3) = -0x1.000002p+0
+++inf:PASSED:fsubs(-1.125000 , -0x1.00000cp-3) = -0x1.000002p+0
+++inf:PASSED:fsubs(-1.125000 , -0x1.00000ep-3) = -0x1.000002p+0
+++inf:PASSED:fsubs(-1.125000 , -0x1.00001p-3) = -0x1.000002p+0
+++inf:PASSED:fsubs(-1.125000 , -0x1.000012p-3) = -0x1p+0
+++inf:PASSED:fsubs(-1.125000 , -0x1.000014p-3) = -0x1p+0
+++inf:PASSED:fsubs(-1.125000 , -0x1.000016p-3) = -0x1p+0
+++inf:PASSED:fsubs(-1.125000 , -0x1.000018p-3) = -0x1p+0
+++inf:PASSED:fsubs(-1.125000 , -0x1.00001ap-3) = -0x1p+0
+++inf:PASSED:fsubs(-1.125000 , -0x1.00001cp-3) = -0x1p+0
+++inf:PASSED:fsubs(-1.125000 , -0x1.00001ep-3) = -0x1p+0
+++inf:PASSED:fsubs(1.125001 , 0x1p-3 ) = 0x1.000004p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.000002p-3) = 0x1.000004p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.000004p-3) = 0x1.000004p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.000006p-3) = 0x1.000004p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.000008p-3) = 0x1.000004p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.00000ap-3) = 0x1.000004p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.00000cp-3) = 0x1.000004p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.00000ep-3) = 0x1.000004p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.00001p-3 ) = 0x1.000002p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.000012p-3) = 0x1.000002p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.000014p-3) = 0x1.000002p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.000016p-3) = 0x1.000002p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.000018p-3) = 0x1.000002p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.00001ap-3) = 0x1.000002p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.00001cp-3) = 0x1.000002p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.00001ep-3) = 0x1.000002p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1p-3 ) = -0x1.000004p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.000002p-3) = -0x1.000004p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.000004p-3) = -0x1.000004p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.000006p-3) = -0x1.000004p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.000008p-3) = -0x1.000004p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.00000ap-3) = -0x1.000004p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.00000cp-3) = -0x1.000004p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.00000ep-3) = -0x1.000004p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.00001p-3) = -0x1.000002p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.000012p-3) = -0x1.000002p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.000014p-3) = -0x1.000002p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.000016p-3) = -0x1.000002p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.000018p-3) = -0x1.000002p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.00001ap-3) = -0x1.000002p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.00001cp-3) = -0x1.000002p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.00001ep-3) = -0x1.000002p+0
++-inf:PASSED:fsubs(1.125000 , 0x1p-3 ) = 0x1.000004p+0
++-inf:PASSED:fsubs(1.125000 , 0x1.000002p-3) = 0x1.000002p+0
++-inf:PASSED:fsubs(1.125000 , 0x1.000004p-3) = 0x1.000002p+0
++-inf:PASSED:fsubs(1.125000 , 0x1.000006p-3) = 0x1.000002p+0
++-inf:PASSED:fsubs(1.125000 , 0x1.000008p-3) = 0x1.000002p+0
++-inf:PASSED:fsubs(1.125000 , 0x1.00000ap-3) = 0x1.000002p+0
++-inf:PASSED:fsubs(1.125000 , 0x1.00000cp-3) = 0x1.000002p+0
++-inf:PASSED:fsubs(1.125000 , 0x1.00000ep-3) = 0x1.000002p+0
++-inf:PASSED:fsubs(1.125000 , 0x1.00001p-3 ) = 0x1.000002p+0
++-inf:PASSED:fsubs(1.125000 , 0x1.000012p-3) = 0x1p+0
++-inf:PASSED:fsubs(1.125000 , 0x1.000014p-3) = 0x1p+0
++-inf:PASSED:fsubs(1.125000 , 0x1.000016p-3) = 0x1p+0
++-inf:PASSED:fsubs(1.125000 , 0x1.000018p-3) = 0x1p+0
++-inf:PASSED:fsubs(1.125000 , 0x1.00001ap-3) = 0x1p+0
++-inf:PASSED:fsubs(1.125000 , 0x1.00001cp-3) = 0x1p+0
++-inf:PASSED:fsubs(1.125000 , 0x1.00001ep-3) = 0x1p+0
++near:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.2p+0
++near:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200002p+0
++near:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200004p+0
++near:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200006p+0
++near:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200008p+0
++near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000cp+0
++near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000ep+0
++near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001p+0
++near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200012p+0
++near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200014p+0
++near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200016p+0
++near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200018p+0
++near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001cp+0
++near:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001ep+0
++near:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20002p+0
++near:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.200022p+0
++near:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.2p+0
++near:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200002p+0
++near:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200004p+0
++near:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200006p+0
++near:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200008p+0
++near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000cp+0
++near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000ep+0
++near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001p+0
++near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200012p+0
++near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200014p+0
++near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200016p+0
++near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200018p+0
++near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001cp+0
++near:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001ep+0
++near:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20002p+0
++near:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.200022p+0
++zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.2p+0
++zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200002p+0
++zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200004p+0
++zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200006p+0
++zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200008p+0
++zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ap+0
++zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000cp+0
++zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ep+0
++zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200012p+0
++zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200014p+0
++zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200016p+0
++zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200018p+0
++zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ap+0
++zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001cp+0
++zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ep+0
++zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20002p+0
++zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.2p+0
++zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200002p+0
++zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200004p+0
++zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200006p+0
++zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200008p+0
++zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ap+0
++zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000cp+0
++zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ep+0
++zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200012p+0
++zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200014p+0
++zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200016p+0
++zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200018p+0
++zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ap+0
++zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001cp+0
++zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ep+0
++zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20002p+0
+++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.2p+0
+++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200002p+0
+++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200004p+0
+++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200006p+0
+++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200008p+0
+++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ap+0
+++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000cp+0
+++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ep+0
+++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200012p+0
+++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200014p+0
+++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200016p+0
+++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200018p+0
+++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ap+0
+++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001cp+0
+++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ep+0
+++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20002p+0
+++inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.2p+0
+++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200004p+0
+++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200006p+0
+++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200008p+0
+++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000ap+0
+++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000cp+0
+++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000ep+0
+++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001p+0
+++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200012p+0
+++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.200016p+0
+++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.200018p+0
+++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001ap+0
+++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001cp+0
+++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001ep+0
+++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20002p+0
+++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.200022p+0
++-inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.2p+0
++-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200004p+0
++-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200006p+0
++-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200008p+0
++-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000ap+0
++-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000cp+0
++-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000ep+0
++-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001p+0
++-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200012p+0
++-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.200016p+0
++-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.200018p+0
++-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001ap+0
++-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001cp+0
++-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001ep+0
++-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20002p+0
++-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.200022p+0
++-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.2p+0
++-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200002p+0
++-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200004p+0
++-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200006p+0
++-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200008p+0
++-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ap+0
++-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000cp+0
++-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ep+0
++-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200012p+0
++-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200014p+0
++-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200016p+0
++-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200018p+0
++-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ap+0
++-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001cp+0
++-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ep+0
++-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20002p+0
++near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
++near:PASSED:fdivs(-100.000000 , 0x1.c8p+5 ) = -0x1.c11f7p+0
++near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
++near:PASSED:fdivs(-100.000000 , 0x1.ap+5 ) = -0x1.ec4ec4p+0
++near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
++near:PASSED:fdivs(-100.000000 , 0x1.b8p+5 ) = -0x1.d1745ep+0
++near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
++near:PASSED:fdivs(-100.000000 , 0x1.98p+5 ) = -0x1.f5f5f6p+0
++near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
++near:PASSED:fdivs(-100.000000 , 0x1.cp+5 ) = -0x1.c92492p+0
++near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
++near:PASSED:fdivs(-100.000000 , 0x1.bp+5 ) = -0x1.da12f6p+0
++near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-148
++near:PASSED:fdivs(-100.000000 , 0x1.d8p+5 ) = -0x1.b1e5f8p+0
++near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-148
++near:PASSED:fdivs(-101.000000 , 0x1.ap+5 ) = -0x1.f13b14p+0
++near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
++near:PASSED:fdivs(100.000000 , 0x1.c8p+5 ) = 0x1.c11f7p+0
++near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
++near:PASSED:fdivs(100.000000 , 0x1.ap+5 ) = 0x1.ec4ec4p+0
++near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
++near:PASSED:fdivs(100.000000 , 0x1.b8p+5 ) = 0x1.d1745ep+0
++near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
++near:PASSED:fdivs(100.000000 , 0x1.98p+5 ) = 0x1.f5f5f6p+0
++near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
++near:PASSED:fdivs(100.000000 , 0x1.cp+5 ) = 0x1.c92492p+0
++near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
++near:PASSED:fdivs(100.000000 , 0x1.bp+5 ) = 0x1.da12f6p+0
++near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-148
++near:PASSED:fdivs(100.000000 , 0x1.d8p+5 ) = 0x1.b1e5f8p+0
++near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-148
++near:PASSED:fdivs(101.000000 , 0x1.ap+5 ) = 0x1.f13b14p+0
++zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
++zero:PASSED:fdivs(-100.000000 , 0x1.c8p+5 ) = -0x1.c11f7p+0
++zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
++zero:PASSED:fdivs(-100.000000 , 0x1.ap+5 ) = -0x1.ec4ec4p+0
++zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
++zero:PASSED:fdivs(-100.000000 , 0x1.b8p+5 ) = -0x1.d1745cp+0
++zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
++zero:PASSED:fdivs(-100.000000 , 0x1.98p+5 ) = -0x1.f5f5f4p+0
++zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
++zero:PASSED:fdivs(-100.000000 , 0x1.cp+5 ) = -0x1.c92492p+0
++zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
++zero:PASSED:fdivs(-100.000000 , 0x1.bp+5 ) = -0x1.da12f6p+0
++zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
++zero:PASSED:fdivs(-100.000000 , 0x1.d8p+5 ) = -0x1.b1e5f6p+0
++zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
++zero:PASSED:fdivs(-101.000000 , 0x1.ap+5 ) = -0x1.f13b12p+0
++zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
++zero:PASSED:fdivs(100.000000 , 0x1.c8p+5 ) = 0x1.c11f7p+0
++zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
++zero:PASSED:fdivs(100.000000 , 0x1.ap+5 ) = 0x1.ec4ec4p+0
++zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
++zero:PASSED:fdivs(100.000000 , 0x1.b8p+5 ) = 0x1.d1745cp+0
++zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
++zero:PASSED:fdivs(100.000000 , 0x1.98p+5 ) = 0x1.f5f5f4p+0
++zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
++zero:PASSED:fdivs(100.000000 , 0x1.cp+5 ) = 0x1.c92492p+0
++zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
++zero:PASSED:fdivs(100.000000 , 0x1.bp+5 ) = 0x1.da12f6p+0
++zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
++zero:PASSED:fdivs(100.000000 , 0x1.d8p+5 ) = 0x1.b1e5f6p+0
++zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
++zero:PASSED:fdivs(101.000000 , 0x1.ap+5 ) = 0x1.f13b12p+0
+++inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
+++inf:PASSED:fdivs(-100.000000 , 0x1.c8p+5 ) = -0x1.c11f7p+0
+++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x0p+0
+++inf:PASSED:fdivs(-100.000000 , 0x1.ap+5 ) = -0x1.ec4ec4p+0
+++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x0p+0
+++inf:PASSED:fdivs(-100.000000 , 0x1.b8p+5 ) = -0x1.d1745cp+0
+++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x0p+0
+++inf:PASSED:fdivs(-100.000000 , 0x1.98p+5 ) = -0x1.f5f5f4p+0
+++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x1p-149
+++inf:PASSED:fdivs(-100.000000 , 0x1.cp+5 ) = -0x1.c92492p+0
+++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x1p-149
+++inf:PASSED:fdivs(-100.000000 , 0x1.bp+5 ) = -0x1.da12f6p+0
+++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x1p-149
+++inf:PASSED:fdivs(-100.000000 , 0x1.d8p+5 ) = -0x1.b1e5f6p+0
+++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x1p-149
+++inf:PASSED:fdivs(-101.000000 , 0x1.ap+5 ) = -0x1.f13b12p+0
+++inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
+++inf:PASSED:fdivs(100.000000 , 0x1.c8p+5 ) = 0x1.c11f72p+0
+++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-149
+++inf:PASSED:fdivs(100.000000 , 0x1.ap+5 ) = 0x1.ec4ec6p+0
+++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-149
+++inf:PASSED:fdivs(100.000000 , 0x1.b8p+5 ) = 0x1.d1745ep+0
+++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-149
+++inf:PASSED:fdivs(100.000000 , 0x1.98p+5 ) = 0x1.f5f5f6p+0
+++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-149
+++inf:PASSED:fdivs(100.000000 , 0x1.cp+5 ) = 0x1.c92494p+0
+++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-148
+++inf:PASSED:fdivs(100.000000 , 0x1.bp+5 ) = 0x1.da12f8p+0
+++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-148
+++inf:PASSED:fdivs(100.000000 , 0x1.d8p+5 ) = 0x1.b1e5f8p+0
+++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-148
+++inf:PASSED:fdivs(101.000000 , 0x1.ap+5 ) = 0x1.f13b14p+0
++-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
++-inf:PASSED:fdivs(-100.000000 , 0x1.c8p+5 ) = -0x1.c11f72p+0
++-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
++-inf:PASSED:fdivs(-100.000000 , 0x1.ap+5 ) = -0x1.ec4ec6p+0
++-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
++-inf:PASSED:fdivs(-100.000000 , 0x1.b8p+5 ) = -0x1.d1745ep+0
++-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
++-inf:PASSED:fdivs(-100.000000 , 0x1.98p+5 ) = -0x1.f5f5f6p+0
++-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
++-inf:PASSED:fdivs(-100.000000 , 0x1.cp+5 ) = -0x1.c92494p+0
++-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-148
++-inf:PASSED:fdivs(-100.000000 , 0x1.bp+5 ) = -0x1.da12f8p+0
++-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-148
++-inf:PASSED:fdivs(-100.000000 , 0x1.d8p+5 ) = -0x1.b1e5f8p+0
++-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-148
++-inf:PASSED:fdivs(-101.000000 , 0x1.ap+5 ) = -0x1.f13b14p+0
++-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
++-inf:PASSED:fdivs(100.000000 , 0x1.c8p+5 ) = 0x1.c11f7p+0
++-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
++-inf:PASSED:fdivs(100.000000 , 0x1.ap+5 ) = 0x1.ec4ec4p+0
++-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
++-inf:PASSED:fdivs(100.000000 , 0x1.b8p+5 ) = 0x1.d1745cp+0
++-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
++-inf:PASSED:fdivs(100.000000 , 0x1.98p+5 ) = 0x1.f5f5f4p+0
++-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
++-inf:PASSED:fdivs(100.000000 , 0x1.cp+5 ) = 0x1.c92492p+0
++-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
++-inf:PASSED:fdivs(100.000000 , 0x1.bp+5 ) = 0x1.da12f6p+0
++-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
++-inf:PASSED:fdivs(100.000000 , 0x1.d8p+5 ) = 0x1.b1e5f6p+0
++-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
++-inf:PASSED:fdivs(101.000000 , 0x1.ap+5 ) = 0x1.f13b12p+0
++near:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0
++near:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
++near:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
++near:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00008p+0
++near:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
++near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
++near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
++near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
++near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
++near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
++near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
++near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ap+0
++near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
++near:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
++near:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
++near:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
++near:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0
++near:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
++near:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
++near:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00008p+0
++near:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
++near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
++near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
++near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
++near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
++near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
++near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
++near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ap+0
++near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
++near:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
++near:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
++near:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
++zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0
++zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0
++zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
++zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
++zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
++zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
++zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
++zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
++zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
++zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
++zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
++zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
++zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
++zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
++zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
++zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
++zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0
++zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0
++zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
++zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
++zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
++zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
++zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
++zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
++zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
++zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
++zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
++zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
++zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
++zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
++zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
++zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
+++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0
+++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0
+++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
+++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
+++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
+++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
+++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
+++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
+++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
+++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
+++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
+++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
+++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
+++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
+++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
+++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
+++inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0
+++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
+++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
+++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00008p+0
+++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
+++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
+++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
+++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
+++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
+++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
+++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
+++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ap+0
+++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
+++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
+++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
+++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00024p+0
++-inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0
++-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
++-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
++-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00008p+0
++-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
++-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
++-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
++-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
++-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
++-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
++-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
++-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ap+0
++-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
++-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
++-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
++-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00024p+0
++-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0
++-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0
++-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
++-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
++-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
++-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
++-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
++-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
++-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
++-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
++-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
++-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
++-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
++-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
++-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
++-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
++near:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0
++near:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
++near:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
++near:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00008p+0
++near:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
++near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
++near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
++near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
++near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
++near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
++near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
++near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ap+0
++near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
++near:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
++near:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
++near:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
++near:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0
++near:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
++near:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
++near:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00008p+0
++near:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
++near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
++near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
++near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
++near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
++near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
++near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
++near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ap+0
++near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
++near:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
++near:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
++near:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
++zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0
++zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0
++zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
++zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
++zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
++zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
++zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
++zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
++zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
++zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
++zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
++zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
++zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
++zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
++zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
++zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
++zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0
++zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0
++zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
++zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
++zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
++zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
++zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
++zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
++zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
++zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
++zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
++zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
++zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
++zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
++zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
++zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
+++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0
+++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0
+++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
+++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
+++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
+++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
+++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
+++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
+++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
+++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
+++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
+++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
+++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
+++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
+++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
+++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
+++inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0
+++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
+++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
+++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00008p+0
+++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
+++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
+++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
+++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
+++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
+++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
+++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
+++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ap+0
+++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
+++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
+++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
+++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00024p+0
++-inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0
++-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
++-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
++-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00008p+0
++-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
++-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
++-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
++-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
++-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
++-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
++-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
++-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ap+0
++-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
++-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
++-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
++-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00024p+0
++-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0
++-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0
++-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
++-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
++-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
++-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
++-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
++-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
++-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
++-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
++-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
++-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
++-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
++-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
++-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
++-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
++near:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0
++near:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
++near:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
++near:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00008p+0
++near:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
++near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
++near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
++near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
++near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
++near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
++near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
++near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ap+0
++near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
++near:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
++near:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
++near:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
++near:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0
++near:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
++near:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
++near:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00008p+0
++near:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
++near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
++near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
++near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
++near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
++near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
++near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
++near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ap+0
++near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
++near:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
++near:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
++near:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
++zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0
++zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0
++zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
++zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
++zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
++zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
++zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
++zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
++zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
++zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
++zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
++zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
++zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
++zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
++zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
++zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
++zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0
++zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0
++zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
++zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
++zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
++zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
++zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
++zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
++zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
++zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
++zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
++zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
++zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
++zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
++zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
++zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
+++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0
+++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0
+++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
+++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
+++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
+++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
+++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
+++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
+++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
+++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
+++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
+++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
+++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
+++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
+++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
+++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
+++inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0
+++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
+++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
+++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00008p+0
+++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
+++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
+++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
+++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
+++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
+++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
+++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
+++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ap+0
+++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
+++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
+++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
+++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00024p+0
++-inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0
++-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
++-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
++-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00008p+0
++-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
++-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
++-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
++-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
++-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
++-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
++-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
++-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ap+0
++-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
++-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
++-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
++-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00024p+0
++-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0
++-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0
++-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
++-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
++-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
++-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
++-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
++-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
++-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
++-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
++-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
++-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
++-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
++-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
++-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
++-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
++near:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0
++near:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
++near:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
++near:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00008p+0
++near:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
++near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
++near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
++near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
++near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
++near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
++near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
++near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ap+0
++near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
++near:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
++near:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
++near:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
++near:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0
++near:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
++near:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
++near:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00008p+0
++near:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
++near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
++near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
++near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
++near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
++near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
++near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
++near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ap+0
++near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
++near:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
++near:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
++near:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
++zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0
++zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0
++zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
++zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
++zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
++zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
++zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
++zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
++zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
++zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
++zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
++zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
++zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
++zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
++zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
++zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
++zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0
++zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0
++zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
++zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
++zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
++zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
++zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
++zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
++zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
++zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
++zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
++zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
++zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
++zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
++zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
++zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
+++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0
+++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0
+++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
+++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
+++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
+++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
+++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
+++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
+++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
+++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
+++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
+++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
+++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
+++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
+++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
+++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
+++inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0
+++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
+++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
+++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00008p+0
+++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
+++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
+++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
+++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
+++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
+++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
+++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
+++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ap+0
+++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
+++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
+++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
+++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00024p+0
++-inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0
++-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
++-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
++-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00008p+0
++-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
++-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
++-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
++-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
++-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
++-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
++-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
++-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ap+0
++-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
++-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
++-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
++-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00024p+0
++-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0
++-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0
++-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
++-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
++-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
++-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
++-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
++-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
++-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
++-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
++-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
++-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
++-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
++-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
++-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
++-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
++-------------------------- test rounding of double operators with guard bits --------------------------
++near:PASSED:fadd(-0x1p+0 , -0x1p-3 ) = -0x1.2p+0
++near:PASSED:fadd(-0x1p+0 , -0x1.0000000000001p-3) = -0x1.2p+0
++near:PASSED:fadd(-0x1p+0 , -0x1.0000000000002p-3) = -0x1.2p+0
++near:PASSED:fadd(-0x1p+0 , -0x1.0000000000003p-3) = -0x1.2p+0
++near:PASSED:fadd(-0x1p+0 , -0x1.0000000000004p-3) = -0x1.2p+0
++near:PASSED:fadd(-0x1p+0 , -0x1.0000000000005p-3) = -0x1.2000000000001p+0
++near:PASSED:fadd(-0x1p+0 , -0x1.0000000000006p-3) = -0x1.2000000000001p+0
++near:PASSED:fadd(-0x1p+0 , -0x1.0000000000007p-3) = -0x1.2000000000001p+0
++near:PASSED:fadd(-0x1p+0 , -0x1.0000000000008p-3) = -0x1.2000000000001p+0
++near:PASSED:fadd(-0x1p+0 , -0x1.0000000000009p-3) = -0x1.2000000000001p+0
++near:PASSED:fadd(-0x1p+0 , -0x1.000000000000ap-3) = -0x1.2000000000001p+0
++near:PASSED:fadd(-0x1p+0 , -0x1.000000000000bp-3) = -0x1.2000000000001p+0
++near:PASSED:fadd(-0x1p+0 , -0x1.000000000000cp-3) = -0x1.2000000000002p+0
++near:PASSED:fadd(-0x1p+0 , -0x1.000000000000dp-3) = -0x1.2000000000002p+0
++near:PASSED:fadd(-0x1p+0 , -0x1.000000000000ep-3) = -0x1.2000000000002p+0
++near:PASSED:fadd(-0x1p+0 , -0x1.000000000000fp-3) = -0x1.2000000000002p+0
++near:PASSED:fadd(0x1p+0 , 0x1p-3 ) = 0x1.2p+0
++near:PASSED:fadd(0x1p+0 , 0x1.0000000000001p-3) = 0x1.2p+0
++near:PASSED:fadd(0x1p+0 , 0x1.0000000000002p-3) = 0x1.2p+0
++near:PASSED:fadd(0x1p+0 , 0x1.0000000000003p-3) = 0x1.2p+0
++near:PASSED:fadd(0x1p+0 , 0x1.0000000000004p-3) = 0x1.2p+0
++near:PASSED:fadd(0x1p+0 , 0x1.0000000000005p-3) = 0x1.2000000000001p+0
++near:PASSED:fadd(0x1p+0 , 0x1.0000000000006p-3) = 0x1.2000000000001p+0
++near:PASSED:fadd(0x1p+0 , 0x1.0000000000007p-3) = 0x1.2000000000001p+0
++near:PASSED:fadd(0x1p+0 , 0x1.0000000000008p-3) = 0x1.2000000000001p+0
++near:PASSED:fadd(0x1p+0 , 0x1.0000000000009p-3) = 0x1.2000000000001p+0
++near:PASSED:fadd(0x1p+0 , 0x1.000000000000ap-3) = 0x1.2000000000001p+0
++near:PASSED:fadd(0x1p+0 , 0x1.000000000000bp-3) = 0x1.2000000000001p+0
++near:PASSED:fadd(0x1p+0 , 0x1.000000000000cp-3) = 0x1.2000000000002p+0
++near:PASSED:fadd(0x1p+0 , 0x1.000000000000dp-3) = 0x1.2000000000002p+0
++near:PASSED:fadd(0x1p+0 , 0x1.000000000000ep-3) = 0x1.2000000000002p+0
++near:PASSED:fadd(0x1p+0 , 0x1.000000000000fp-3) = 0x1.2000000000002p+0
++zero:PASSED:fadd(-0x1p+0 , -0x1p-3 ) = -0x1.2p+0
++zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000001p-3) = -0x1.2p+0
++zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000002p-3) = -0x1.2p+0
++zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000003p-3) = -0x1.2p+0
++zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000004p-3) = -0x1.2p+0
++zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000005p-3) = -0x1.2p+0
++zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000006p-3) = -0x1.2p+0
++zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000007p-3) = -0x1.2p+0
++zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000008p-3) = -0x1.2000000000001p+0
++zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000009p-3) = -0x1.2000000000001p+0
++zero:PASSED:fadd(-0x1p+0 , -0x1.000000000000ap-3) = -0x1.2000000000001p+0
++zero:PASSED:fadd(-0x1p+0 , -0x1.000000000000bp-3) = -0x1.2000000000001p+0
++zero:PASSED:fadd(-0x1p+0 , -0x1.000000000000cp-3) = -0x1.2000000000001p+0
++zero:PASSED:fadd(-0x1p+0 , -0x1.000000000000dp-3) = -0x1.2000000000001p+0
++zero:PASSED:fadd(-0x1p+0 , -0x1.000000000000ep-3) = -0x1.2000000000001p+0
++zero:PASSED:fadd(-0x1p+0 , -0x1.000000000000fp-3) = -0x1.2000000000001p+0
++zero:PASSED:fadd(0x1p+0 , 0x1p-3 ) = 0x1.2p+0
++zero:PASSED:fadd(0x1p+0 , 0x1.0000000000001p-3) = 0x1.2p+0
++zero:PASSED:fadd(0x1p+0 , 0x1.0000000000002p-3) = 0x1.2p+0
++zero:PASSED:fadd(0x1p+0 , 0x1.0000000000003p-3) = 0x1.2p+0
++zero:PASSED:fadd(0x1p+0 , 0x1.0000000000004p-3) = 0x1.2p+0
++zero:PASSED:fadd(0x1p+0 , 0x1.0000000000005p-3) = 0x1.2p+0
++zero:PASSED:fadd(0x1p+0 , 0x1.0000000000006p-3) = 0x1.2p+0
++zero:PASSED:fadd(0x1p+0 , 0x1.0000000000007p-3) = 0x1.2p+0
++zero:PASSED:fadd(0x1p+0 , 0x1.0000000000008p-3) = 0x1.2000000000001p+0
++zero:PASSED:fadd(0x1p+0 , 0x1.0000000000009p-3) = 0x1.2000000000001p+0
++zero:PASSED:fadd(0x1p+0 , 0x1.000000000000ap-3) = 0x1.2000000000001p+0
++zero:PASSED:fadd(0x1p+0 , 0x1.000000000000bp-3) = 0x1.2000000000001p+0
++zero:PASSED:fadd(0x1p+0 , 0x1.000000000000cp-3) = 0x1.2000000000001p+0
++zero:PASSED:fadd(0x1p+0 , 0x1.000000000000dp-3) = 0x1.2000000000001p+0
++zero:PASSED:fadd(0x1p+0 , 0x1.000000000000ep-3) = 0x1.2000000000001p+0
++zero:PASSED:fadd(0x1p+0 , 0x1.000000000000fp-3) = 0x1.2000000000001p+0
+++inf:PASSED:fadd(-0x1p+0 , -0x1p-3 ) = -0x1.2p+0
+++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000001p-3) = -0x1.2p+0
+++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000002p-3) = -0x1.2p+0
+++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000003p-3) = -0x1.2p+0
+++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000004p-3) = -0x1.2p+0
+++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000005p-3) = -0x1.2p+0
+++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000006p-3) = -0x1.2p+0
+++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000007p-3) = -0x1.2p+0
+++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000008p-3) = -0x1.2000000000001p+0
+++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000009p-3) = -0x1.2000000000001p+0
+++inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000ap-3) = -0x1.2000000000001p+0
+++inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000bp-3) = -0x1.2000000000001p+0
+++inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000cp-3) = -0x1.2000000000001p+0
+++inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000dp-3) = -0x1.2000000000001p+0
+++inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000ep-3) = -0x1.2000000000001p+0
+++inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000fp-3) = -0x1.2000000000001p+0
+++inf:PASSED:fadd(0x1p+0 , 0x1p-3 ) = 0x1.2p+0
+++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000001p-3) = 0x1.2000000000001p+0
+++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000002p-3) = 0x1.2000000000001p+0
+++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000003p-3) = 0x1.2000000000001p+0
+++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000004p-3) = 0x1.2000000000001p+0
+++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000005p-3) = 0x1.2000000000001p+0
+++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000006p-3) = 0x1.2000000000001p+0
+++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000007p-3) = 0x1.2000000000001p+0
+++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000008p-3) = 0x1.2000000000001p+0
+++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000009p-3) = 0x1.2000000000002p+0
+++inf:PASSED:fadd(0x1p+0 , 0x1.000000000000ap-3) = 0x1.2000000000002p+0
+++inf:PASSED:fadd(0x1p+0 , 0x1.000000000000bp-3) = 0x1.2000000000002p+0
+++inf:PASSED:fadd(0x1p+0 , 0x1.000000000000cp-3) = 0x1.2000000000002p+0
+++inf:PASSED:fadd(0x1p+0 , 0x1.000000000000dp-3) = 0x1.2000000000002p+0
+++inf:PASSED:fadd(0x1p+0 , 0x1.000000000000ep-3) = 0x1.2000000000002p+0
+++inf:PASSED:fadd(0x1p+0 , 0x1.000000000000fp-3) = 0x1.2000000000002p+0
++-inf:PASSED:fadd(-0x1p+0 , -0x1p-3 ) = -0x1.2p+0
++-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000001p-3) = -0x1.2000000000001p+0
++-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000002p-3) = -0x1.2000000000001p+0
++-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000003p-3) = -0x1.2000000000001p+0
++-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000004p-3) = -0x1.2000000000001p+0
++-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000005p-3) = -0x1.2000000000001p+0
++-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000006p-3) = -0x1.2000000000001p+0
++-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000007p-3) = -0x1.2000000000001p+0
++-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000008p-3) = -0x1.2000000000001p+0
++-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000009p-3) = -0x1.2000000000002p+0
++-inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000ap-3) = -0x1.2000000000002p+0
++-inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000bp-3) = -0x1.2000000000002p+0
++-inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000cp-3) = -0x1.2000000000002p+0
++-inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000dp-3) = -0x1.2000000000002p+0
++-inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000ep-3) = -0x1.2000000000002p+0
++-inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000fp-3) = -0x1.2000000000002p+0
++-inf:PASSED:fadd(0x1p+0 , 0x1p-3 ) = 0x1.2p+0
++-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000001p-3) = 0x1.2p+0
++-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000002p-3) = 0x1.2p+0
++-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000003p-3) = 0x1.2p+0
++-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000004p-3) = 0x1.2p+0
++-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000005p-3) = 0x1.2p+0
++-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000006p-3) = 0x1.2p+0
++-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000007p-3) = 0x1.2p+0
++-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000008p-3) = 0x1.2000000000001p+0
++-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000009p-3) = 0x1.2000000000001p+0
++-inf:PASSED:fadd(0x1p+0 , 0x1.000000000000ap-3) = 0x1.2000000000001p+0
++-inf:PASSED:fadd(0x1p+0 , 0x1.000000000000bp-3) = 0x1.2000000000001p+0
++-inf:PASSED:fadd(0x1p+0 , 0x1.000000000000cp-3) = 0x1.2000000000001p+0
++-inf:PASSED:fadd(0x1p+0 , 0x1.000000000000dp-3) = 0x1.2000000000001p+0
++-inf:PASSED:fadd(0x1p+0 , 0x1.000000000000ep-3) = 0x1.2000000000001p+0
++-inf:PASSED:fadd(0x1p+0 , 0x1.000000000000fp-3) = 0x1.2000000000001p+0
++near:PASSED:fsub(-0x1.2000000000002p+0, -0x1p-3 ) = -0x1.0000000000002p+0
++near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000001p-3) = -0x1.0000000000002p+0
++near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000002p-3) = -0x1.0000000000002p+0
++near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000003p-3) = -0x1.0000000000002p+0
++near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000004p-3) = -0x1.0000000000002p+0
++near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000005p-3) = -0x1.0000000000001p+0
++near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000006p-3) = -0x1.0000000000001p+0
++near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000007p-3) = -0x1.0000000000001p+0
++near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000008p-3) = -0x1.0000000000001p+0
++near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000009p-3) = -0x1.0000000000001p+0
++near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ap-3) = -0x1.0000000000001p+0
++near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000bp-3) = -0x1.0000000000001p+0
++near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000cp-3) = -0x1p+0
++near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000dp-3) = -0x1p+0
++near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ep-3) = -0x1p+0
++near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000fp-3) = -0x1p+0
++near:PASSED:fsub(0x1.2000000000002p+0, 0x1p-3 ) = 0x1.0000000000002p+0
++near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000001p-3) = 0x1.0000000000002p+0
++near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000002p-3) = 0x1.0000000000002p+0
++near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000003p-3) = 0x1.0000000000002p+0
++near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000004p-3) = 0x1.0000000000002p+0
++near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000005p-3) = 0x1.0000000000001p+0
++near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000006p-3) = 0x1.0000000000001p+0
++near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000007p-3) = 0x1.0000000000001p+0
++near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000008p-3) = 0x1.0000000000001p+0
++near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000009p-3) = 0x1.0000000000001p+0
++near:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ap-3) = 0x1.0000000000001p+0
++near:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000bp-3) = 0x1.0000000000001p+0
++near:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000cp-3) = 0x1p+0
++near:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000dp-3) = 0x1p+0
++near:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ep-3) = 0x1p+0
++near:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000fp-3) = 0x1p+0
++zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1p-3 ) = -0x1.0000000000002p+0
++zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000001p-3) = -0x1.0000000000001p+0
++zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000002p-3) = -0x1.0000000000001p+0
++zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000003p-3) = -0x1.0000000000001p+0
++zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000004p-3) = -0x1.0000000000001p+0
++zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000005p-3) = -0x1.0000000000001p+0
++zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000006p-3) = -0x1.0000000000001p+0
++zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000007p-3) = -0x1.0000000000001p+0
++zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000008p-3) = -0x1.0000000000001p+0
++zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000009p-3) = -0x1p+0
++zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ap-3) = -0x1p+0
++zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000bp-3) = -0x1p+0
++zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000cp-3) = -0x1p+0
++zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000dp-3) = -0x1p+0
++zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ep-3) = -0x1p+0
++zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000fp-3) = -0x1p+0
++zero:PASSED:fsub(0x1.2000000000002p+0, 0x1p-3 ) = 0x1.0000000000002p+0
++zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000001p-3) = 0x1.0000000000001p+0
++zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000002p-3) = 0x1.0000000000001p+0
++zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000003p-3) = 0x1.0000000000001p+0
++zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000004p-3) = 0x1.0000000000001p+0
++zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000005p-3) = 0x1.0000000000001p+0
++zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000006p-3) = 0x1.0000000000001p+0
++zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000007p-3) = 0x1.0000000000001p+0
++zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000008p-3) = 0x1.0000000000001p+0
++zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000009p-3) = 0x1p+0
++zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ap-3) = 0x1p+0
++zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000bp-3) = 0x1p+0
++zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000cp-3) = 0x1p+0
++zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000dp-3) = 0x1p+0
++zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ep-3) = 0x1p+0
++zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000fp-3) = 0x1p+0
+++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1p-3 ) = -0x1.0000000000002p+0
+++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000001p-3) = -0x1.0000000000001p+0
+++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000002p-3) = -0x1.0000000000001p+0
+++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000003p-3) = -0x1.0000000000001p+0
+++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000004p-3) = -0x1.0000000000001p+0
+++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000005p-3) = -0x1.0000000000001p+0
+++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000006p-3) = -0x1.0000000000001p+0
+++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000007p-3) = -0x1.0000000000001p+0
+++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000008p-3) = -0x1.0000000000001p+0
+++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000009p-3) = -0x1p+0
+++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ap-3) = -0x1p+0
+++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000bp-3) = -0x1p+0
+++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000cp-3) = -0x1p+0
+++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000dp-3) = -0x1p+0
+++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ep-3) = -0x1p+0
+++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000fp-3) = -0x1p+0
+++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1p-3 ) = 0x1.0000000000002p+0
+++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000001p-3) = 0x1.0000000000002p+0
+++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000002p-3) = 0x1.0000000000002p+0
+++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000003p-3) = 0x1.0000000000002p+0
+++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000004p-3) = 0x1.0000000000002p+0
+++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000005p-3) = 0x1.0000000000002p+0
+++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000006p-3) = 0x1.0000000000002p+0
+++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000007p-3) = 0x1.0000000000002p+0
+++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000008p-3) = 0x1.0000000000001p+0
+++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000009p-3) = 0x1.0000000000001p+0
+++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ap-3) = 0x1.0000000000001p+0
+++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000bp-3) = 0x1.0000000000001p+0
+++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000cp-3) = 0x1.0000000000001p+0
+++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000dp-3) = 0x1.0000000000001p+0
+++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ep-3) = 0x1.0000000000001p+0
+++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000fp-3) = 0x1.0000000000001p+0
++-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1p-3 ) = -0x1.0000000000002p+0
++-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000001p-3) = -0x1.0000000000002p+0
++-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000002p-3) = -0x1.0000000000002p+0
++-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000003p-3) = -0x1.0000000000002p+0
++-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000004p-3) = -0x1.0000000000002p+0
++-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000005p-3) = -0x1.0000000000002p+0
++-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000006p-3) = -0x1.0000000000002p+0
++-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000007p-3) = -0x1.0000000000002p+0
++-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000008p-3) = -0x1.0000000000001p+0
++-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000009p-3) = -0x1.0000000000001p+0
++-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ap-3) = -0x1.0000000000001p+0
++-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000bp-3) = -0x1.0000000000001p+0
++-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000cp-3) = -0x1.0000000000001p+0
++-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000dp-3) = -0x1.0000000000001p+0
++-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ep-3) = -0x1.0000000000001p+0
++-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000fp-3) = -0x1.0000000000001p+0
++-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1p-3 ) = 0x1.0000000000002p+0
++-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000001p-3) = 0x1.0000000000001p+0
++-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000002p-3) = 0x1.0000000000001p+0
++-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000003p-3) = 0x1.0000000000001p+0
++-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000004p-3) = 0x1.0000000000001p+0
++-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000005p-3) = 0x1.0000000000001p+0
++-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000006p-3) = 0x1.0000000000001p+0
++-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000007p-3) = 0x1.0000000000001p+0
++-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000008p-3) = 0x1.0000000000001p+0
++-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000009p-3) = 0x1p+0
++-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ap-3) = 0x1p+0
++-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000bp-3) = 0x1p+0
++-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000cp-3) = 0x1p+0
++-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000dp-3) = 0x1p+0
++-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ep-3) = 0x1p+0
++-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000fp-3) = 0x1p+0
++near:PASSED:fmul(-0x1p+0 , 0x1.2p+0 ) = -0x1.2p+0
++near:PASSED:fmul(-0x1.0000000000001p+0, 0x1.2p+0 ) = -0x1.2000000000001p+0
++near:PASSED:fmul(-0x1.0000000000002p+0, 0x1.2p+0 ) = -0x1.2000000000002p+0
++near:PASSED:fmul(-0x1.0000000000003p+0, 0x1.2p+0 ) = -0x1.2000000000003p+0
++near:PASSED:fmul(-0x1.0000000000004p+0, 0x1.2p+0 ) = -0x1.2000000000004p+0
++near:PASSED:fmul(-0x1.0000000000005p+0, 0x1.2p+0 ) = -0x1.2000000000006p+0
++near:PASSED:fmul(-0x1.0000000000006p+0, 0x1.2p+0 ) = -0x1.2000000000007p+0
++near:PASSED:fmul(-0x1.0000000000007p+0, 0x1.2p+0 ) = -0x1.2000000000008p+0
++near:PASSED:fmul(-0x1.0000000000008p+0, 0x1.2p+0 ) = -0x1.2000000000009p+0
++near:PASSED:fmul(-0x1.0000000000009p+0, 0x1.2p+0 ) = -0x1.200000000000ap+0
++near:PASSED:fmul(-0x1.000000000000ap+0, 0x1.2p+0 ) = -0x1.200000000000bp+0
++near:PASSED:fmul(-0x1.000000000000bp+0, 0x1.2p+0 ) = -0x1.200000000000cp+0
++near:PASSED:fmul(-0x1.000000000000cp+0, 0x1.2p+0 ) = -0x1.200000000000ep+0
++near:PASSED:fmul(-0x1.000000000000dp+0, 0x1.2p+0 ) = -0x1.200000000000fp+0
++near:PASSED:fmul(-0x1.000000000000ep+0, 0x1.2p+0 ) = -0x1.200000000001p+0
++near:PASSED:fmul(-0x1.000000000000fp+0, 0x1.2p+0 ) = -0x1.2000000000011p+0
++near:PASSED:fmul(0x1p+0 , 0x1.2p+0 ) = 0x1.2p+0
++near:PASSED:fmul(0x1.0000000000001p+0, 0x1.2p+0 ) = 0x1.2000000000001p+0
++near:PASSED:fmul(0x1.0000000000002p+0, 0x1.2p+0 ) = 0x1.2000000000002p+0
++near:PASSED:fmul(0x1.0000000000003p+0, 0x1.2p+0 ) = 0x1.2000000000003p+0
++near:PASSED:fmul(0x1.0000000000004p+0, 0x1.2p+0 ) = 0x1.2000000000004p+0
++near:PASSED:fmul(0x1.0000000000005p+0, 0x1.2p+0 ) = 0x1.2000000000006p+0
++near:PASSED:fmul(0x1.0000000000006p+0, 0x1.2p+0 ) = 0x1.2000000000007p+0
++near:PASSED:fmul(0x1.0000000000007p+0, 0x1.2p+0 ) = 0x1.2000000000008p+0
++near:PASSED:fmul(0x1.0000000000008p+0, 0x1.2p+0 ) = 0x1.2000000000009p+0
++near:PASSED:fmul(0x1.0000000000009p+0, 0x1.2p+0 ) = 0x1.200000000000ap+0
++near:PASSED:fmul(0x1.000000000000ap+0, 0x1.2p+0 ) = 0x1.200000000000bp+0
++near:PASSED:fmul(0x1.000000000000bp+0, 0x1.2p+0 ) = 0x1.200000000000cp+0
++near:PASSED:fmul(0x1.000000000000cp+0, 0x1.2p+0 ) = 0x1.200000000000ep+0
++near:PASSED:fmul(0x1.000000000000dp+0, 0x1.2p+0 ) = 0x1.200000000000fp+0
++near:PASSED:fmul(0x1.000000000000ep+0, 0x1.2p+0 ) = 0x1.200000000001p+0
++near:PASSED:fmul(0x1.000000000000fp+0, 0x1.2p+0 ) = 0x1.2000000000011p+0
++zero:PASSED:fmul(-0x1p+0 , 0x1.2p+0 ) = -0x1.2p+0
++zero:PASSED:fmul(-0x1.0000000000001p+0, 0x1.2p+0 ) = -0x1.2000000000001p+0
++zero:PASSED:fmul(-0x1.0000000000002p+0, 0x1.2p+0 ) = -0x1.2000000000002p+0
++zero:PASSED:fmul(-0x1.0000000000003p+0, 0x1.2p+0 ) = -0x1.2000000000003p+0
++zero:PASSED:fmul(-0x1.0000000000004p+0, 0x1.2p+0 ) = -0x1.2000000000004p+0
++zero:PASSED:fmul(-0x1.0000000000005p+0, 0x1.2p+0 ) = -0x1.2000000000005p+0
++zero:PASSED:fmul(-0x1.0000000000006p+0, 0x1.2p+0 ) = -0x1.2000000000006p+0
++zero:PASSED:fmul(-0x1.0000000000007p+0, 0x1.2p+0 ) = -0x1.2000000000007p+0
++zero:PASSED:fmul(-0x1.0000000000008p+0, 0x1.2p+0 ) = -0x1.2000000000009p+0
++zero:PASSED:fmul(-0x1.0000000000009p+0, 0x1.2p+0 ) = -0x1.200000000000ap+0
++zero:PASSED:fmul(-0x1.000000000000ap+0, 0x1.2p+0 ) = -0x1.200000000000bp+0
++zero:PASSED:fmul(-0x1.000000000000bp+0, 0x1.2p+0 ) = -0x1.200000000000cp+0
++zero:PASSED:fmul(-0x1.000000000000cp+0, 0x1.2p+0 ) = -0x1.200000000000dp+0
++zero:PASSED:fmul(-0x1.000000000000dp+0, 0x1.2p+0 ) = -0x1.200000000000ep+0
++zero:PASSED:fmul(-0x1.000000000000ep+0, 0x1.2p+0 ) = -0x1.200000000000fp+0
++zero:PASSED:fmul(-0x1.000000000000fp+0, 0x1.2p+0 ) = -0x1.200000000001p+0
++zero:PASSED:fmul(0x1p+0 , 0x1.2p+0 ) = 0x1.2p+0
++zero:PASSED:fmul(0x1.0000000000001p+0, 0x1.2p+0 ) = 0x1.2000000000001p+0
++zero:PASSED:fmul(0x1.0000000000002p+0, 0x1.2p+0 ) = 0x1.2000000000002p+0
++zero:PASSED:fmul(0x1.0000000000003p+0, 0x1.2p+0 ) = 0x1.2000000000003p+0
++zero:PASSED:fmul(0x1.0000000000004p+0, 0x1.2p+0 ) = 0x1.2000000000004p+0
++zero:PASSED:fmul(0x1.0000000000005p+0, 0x1.2p+0 ) = 0x1.2000000000005p+0
++zero:PASSED:fmul(0x1.0000000000006p+0, 0x1.2p+0 ) = 0x1.2000000000006p+0
++zero:PASSED:fmul(0x1.0000000000007p+0, 0x1.2p+0 ) = 0x1.2000000000007p+0
++zero:PASSED:fmul(0x1.0000000000008p+0, 0x1.2p+0 ) = 0x1.2000000000009p+0
++zero:PASSED:fmul(0x1.0000000000009p+0, 0x1.2p+0 ) = 0x1.200000000000ap+0
++zero:PASSED:fmul(0x1.000000000000ap+0, 0x1.2p+0 ) = 0x1.200000000000bp+0
++zero:PASSED:fmul(0x1.000000000000bp+0, 0x1.2p+0 ) = 0x1.200000000000cp+0
++zero:PASSED:fmul(0x1.000000000000cp+0, 0x1.2p+0 ) = 0x1.200000000000dp+0
++zero:PASSED:fmul(0x1.000000000000dp+0, 0x1.2p+0 ) = 0x1.200000000000ep+0
++zero:PASSED:fmul(0x1.000000000000ep+0, 0x1.2p+0 ) = 0x1.200000000000fp+0
++zero:PASSED:fmul(0x1.000000000000fp+0, 0x1.2p+0 ) = 0x1.200000000001p+0
+++inf:PASSED:fmul(-0x1p+0 , 0x1.2p+0 ) = -0x1.2p+0
+++inf:PASSED:fmul(-0x1.0000000000001p+0, 0x1.2p+0 ) = -0x1.2000000000001p+0
+++inf:PASSED:fmul(-0x1.0000000000002p+0, 0x1.2p+0 ) = -0x1.2000000000002p+0
+++inf:PASSED:fmul(-0x1.0000000000003p+0, 0x1.2p+0 ) = -0x1.2000000000003p+0
+++inf:PASSED:fmul(-0x1.0000000000004p+0, 0x1.2p+0 ) = -0x1.2000000000004p+0
+++inf:PASSED:fmul(-0x1.0000000000005p+0, 0x1.2p+0 ) = -0x1.2000000000005p+0
+++inf:PASSED:fmul(-0x1.0000000000006p+0, 0x1.2p+0 ) = -0x1.2000000000006p+0
+++inf:PASSED:fmul(-0x1.0000000000007p+0, 0x1.2p+0 ) = -0x1.2000000000007p+0
+++inf:PASSED:fmul(-0x1.0000000000008p+0, 0x1.2p+0 ) = -0x1.2000000000009p+0
+++inf:PASSED:fmul(-0x1.0000000000009p+0, 0x1.2p+0 ) = -0x1.200000000000ap+0
+++inf:PASSED:fmul(-0x1.000000000000ap+0, 0x1.2p+0 ) = -0x1.200000000000bp+0
+++inf:PASSED:fmul(-0x1.000000000000bp+0, 0x1.2p+0 ) = -0x1.200000000000cp+0
+++inf:PASSED:fmul(-0x1.000000000000cp+0, 0x1.2p+0 ) = -0x1.200000000000dp+0
+++inf:PASSED:fmul(-0x1.000000000000dp+0, 0x1.2p+0 ) = -0x1.200000000000ep+0
+++inf:PASSED:fmul(-0x1.000000000000ep+0, 0x1.2p+0 ) = -0x1.200000000000fp+0
+++inf:PASSED:fmul(-0x1.000000000000fp+0, 0x1.2p+0 ) = -0x1.200000000001p+0
+++inf:PASSED:fmul(0x1p+0 , 0x1.2p+0 ) = 0x1.2p+0
+++inf:PASSED:fmul(0x1.0000000000001p+0, 0x1.2p+0 ) = 0x1.2000000000002p+0
+++inf:PASSED:fmul(0x1.0000000000002p+0, 0x1.2p+0 ) = 0x1.2000000000003p+0
+++inf:PASSED:fmul(0x1.0000000000003p+0, 0x1.2p+0 ) = 0x1.2000000000004p+0
+++inf:PASSED:fmul(0x1.0000000000004p+0, 0x1.2p+0 ) = 0x1.2000000000005p+0
+++inf:PASSED:fmul(0x1.0000000000005p+0, 0x1.2p+0 ) = 0x1.2000000000006p+0
+++inf:PASSED:fmul(0x1.0000000000006p+0, 0x1.2p+0 ) = 0x1.2000000000007p+0
+++inf:PASSED:fmul(0x1.0000000000007p+0, 0x1.2p+0 ) = 0x1.2000000000008p+0
+++inf:PASSED:fmul(0x1.0000000000008p+0, 0x1.2p+0 ) = 0x1.2000000000009p+0
+++inf:PASSED:fmul(0x1.0000000000009p+0, 0x1.2p+0 ) = 0x1.200000000000bp+0
+++inf:PASSED:fmul(0x1.000000000000ap+0, 0x1.2p+0 ) = 0x1.200000000000cp+0
+++inf:PASSED:fmul(0x1.000000000000bp+0, 0x1.2p+0 ) = 0x1.200000000000dp+0
+++inf:PASSED:fmul(0x1.000000000000cp+0, 0x1.2p+0 ) = 0x1.200000000000ep+0
+++inf:PASSED:fmul(0x1.000000000000dp+0, 0x1.2p+0 ) = 0x1.200000000000fp+0
+++inf:PASSED:fmul(0x1.000000000000ep+0, 0x1.2p+0 ) = 0x1.200000000001p+0
+++inf:PASSED:fmul(0x1.000000000000fp+0, 0x1.2p+0 ) = 0x1.2000000000011p+0
++-inf:PASSED:fmul(-0x1p+0 , 0x1.2p+0 ) = -0x1.2p+0
++-inf:PASSED:fmul(-0x1.0000000000001p+0, 0x1.2p+0 ) = -0x1.2000000000002p+0
++-inf:PASSED:fmul(-0x1.0000000000002p+0, 0x1.2p+0 ) = -0x1.2000000000003p+0
++-inf:PASSED:fmul(-0x1.0000000000003p+0, 0x1.2p+0 ) = -0x1.2000000000004p+0
++-inf:PASSED:fmul(-0x1.0000000000004p+0, 0x1.2p+0 ) = -0x1.2000000000005p+0
++-inf:PASSED:fmul(-0x1.0000000000005p+0, 0x1.2p+0 ) = -0x1.2000000000006p+0
++-inf:PASSED:fmul(-0x1.0000000000006p+0, 0x1.2p+0 ) = -0x1.2000000000007p+0
++-inf:PASSED:fmul(-0x1.0000000000007p+0, 0x1.2p+0 ) = -0x1.2000000000008p+0
++-inf:PASSED:fmul(-0x1.0000000000008p+0, 0x1.2p+0 ) = -0x1.2000000000009p+0
++-inf:PASSED:fmul(-0x1.0000000000009p+0, 0x1.2p+0 ) = -0x1.200000000000bp+0
++-inf:PASSED:fmul(-0x1.000000000000ap+0, 0x1.2p+0 ) = -0x1.200000000000cp+0
++-inf:PASSED:fmul(-0x1.000000000000bp+0, 0x1.2p+0 ) = -0x1.200000000000dp+0
++-inf:PASSED:fmul(-0x1.000000000000cp+0, 0x1.2p+0 ) = -0x1.200000000000ep+0
++-inf:PASSED:fmul(-0x1.000000000000dp+0, 0x1.2p+0 ) = -0x1.200000000000fp+0
++-inf:PASSED:fmul(-0x1.000000000000ep+0, 0x1.2p+0 ) = -0x1.200000000001p+0
++-inf:PASSED:fmul(-0x1.000000000000fp+0, 0x1.2p+0 ) = -0x1.2000000000011p+0
++-inf:PASSED:fmul(0x1p+0 , 0x1.2p+0 ) = 0x1.2p+0
++-inf:PASSED:fmul(0x1.0000000000001p+0, 0x1.2p+0 ) = 0x1.2000000000001p+0
++-inf:PASSED:fmul(0x1.0000000000002p+0, 0x1.2p+0 ) = 0x1.2000000000002p+0
++-inf:PASSED:fmul(0x1.0000000000003p+0, 0x1.2p+0 ) = 0x1.2000000000003p+0
++-inf:PASSED:fmul(0x1.0000000000004p+0, 0x1.2p+0 ) = 0x1.2000000000004p+0
++-inf:PASSED:fmul(0x1.0000000000005p+0, 0x1.2p+0 ) = 0x1.2000000000005p+0
++-inf:PASSED:fmul(0x1.0000000000006p+0, 0x1.2p+0 ) = 0x1.2000000000006p+0
++-inf:PASSED:fmul(0x1.0000000000007p+0, 0x1.2p+0 ) = 0x1.2000000000007p+0
++-inf:PASSED:fmul(0x1.0000000000008p+0, 0x1.2p+0 ) = 0x1.2000000000009p+0
++-inf:PASSED:fmul(0x1.0000000000009p+0, 0x1.2p+0 ) = 0x1.200000000000ap+0
++-inf:PASSED:fmul(0x1.000000000000ap+0, 0x1.2p+0 ) = 0x1.200000000000bp+0
++-inf:PASSED:fmul(0x1.000000000000bp+0, 0x1.2p+0 ) = 0x1.200000000000cp+0
++-inf:PASSED:fmul(0x1.000000000000cp+0, 0x1.2p+0 ) = 0x1.200000000000dp+0
++-inf:PASSED:fmul(0x1.000000000000dp+0, 0x1.2p+0 ) = 0x1.200000000000ep+0
++-inf:PASSED:fmul(0x1.000000000000ep+0, 0x1.2p+0 ) = 0x1.200000000000fp+0
++-inf:PASSED:fmul(0x1.000000000000fp+0, 0x1.2p+0 ) = 0x1.200000000001p+0
++-62/62
++near:PASSED:fdiv(-0x1.fp+5 , 0x1.fp+5 ) = -0x1p+0
++-64/62
++near:PASSED:fdiv(-0x1p+6 , 0x1.fp+5 ) = -0x1.0842108421084p+0
++-66/62
++near:PASSED:fdiv(-0x1.08p+6 , 0x1.fp+5 ) = -0x1.1084210842108p+0
++-100/62
++near:PASSED:fdiv(-0x1.9p+6 , 0x1.fp+5 ) = -0x1.9ce739ce739cep+0
++near:PASSED:fdiv(0x0.0000000000001p-1022, -0x1p+1 ) = -0x0p+0
++-102/62
++near:PASSED:fdiv(-0x1.98p+6 , 0x1.fp+5 ) = -0x1.a5294a5294a53p+0
++-106/62
++near:PASSED:fdiv(-0x1.a8p+6 , 0x1.fp+5 ) = -0x1.b5ad6b5ad6b5bp+0
++-108/62
++near:PASSED:fdiv(-0x1.bp+6 , 0x1.fp+5 ) = -0x1.bdef7bdef7bdfp+0
++-108/108
++near:PASSED:fdiv(-0x1.bp+6 , 0x1.bp+6 ) = -0x1p+0
++-112/62
++near:PASSED:fdiv(-0x1.cp+6 , 0x1.fp+5 ) = -0x1.ce739ce739ce7p+0
++-114/62
++near:PASSED:fdiv(-0x1.c8p+6 , 0x1.fp+5 ) = -0x1.d6b5ad6b5ad6bp+0
++-116/62
++near:PASSED:fdiv(-0x1.dp+6 , 0x1.fp+5 ) = -0x1.def7bdef7bdefp+0
++near:PASSED:fdiv(0x0.0000000000003p-1022, -0x1p+1 ) = -0x0.0000000000002p-1022
++-118/62
++near:PASSED:fdiv(-0x1.d8p+6 , 0x1.fp+5 ) = -0x1.e739ce739ce74p+0
++-90/62
++near:PASSED:fdiv(-0x1.68p+6 , 0x1.fp+5 ) = -0x1.739ce739ce73ap+0
++-92/62
++near:PASSED:fdiv(-0x1.7p+6 , 0x1.fp+5 ) = -0x1.7bdef7bdef7bep+0
++62/62
++near:PASSED:fdiv(0x1.fp+5 , 0x1.fp+5 ) = 0x1p+0
++64/62
++near:PASSED:fdiv(0x1p+6 , 0x1.fp+5 ) = 0x1.0842108421084p+0
++66/62
++near:PASSED:fdiv(0x1.08p+6 , 0x1.fp+5 ) = 0x1.1084210842108p+0
++100/62
++near:PASSED:fdiv(0x1.9p+6 , 0x1.fp+5 ) = 0x1.9ce739ce739cep+0
++near:PASSED:fdiv(0x0.0000000000001p-1022, 0x1p+1 ) = 0x0p+0
++102/62
++near:PASSED:fdiv(0x1.98p+6 , 0x1.fp+5 ) = 0x1.a5294a5294a53p+0
++106/62
++near:PASSED:fdiv(0x1.a8p+6 , 0x1.fp+5 ) = 0x1.b5ad6b5ad6b5bp+0
++108/62
++near:PASSED:fdiv(0x1.bp+6 , 0x1.fp+5 ) = 0x1.bdef7bdef7bdfp+0
++108/108
++near:PASSED:fdiv(0x1.bp+6 , 0x1.bp+6 ) = 0x1p+0
++112/62
++near:PASSED:fdiv(0x1.cp+6 , 0x1.fp+5 ) = 0x1.ce739ce739ce7p+0
++114/62
++near:PASSED:fdiv(0x1.c8p+6 , 0x1.fp+5 ) = 0x1.d6b5ad6b5ad6bp+0
++116/62
++near:PASSED:fdiv(0x1.dp+6 , 0x1.fp+5 ) = 0x1.def7bdef7bdefp+0
++near:PASSED:fdiv(0x0.0000000000003p-1022, 0x1p+1 ) = 0x0.0000000000002p-1022
++118/62
++near:PASSED:fdiv(0x1.d8p+6 , 0x1.fp+5 ) = 0x1.e739ce739ce74p+0
++90/62
++near:PASSED:fdiv(0x1.68p+6 , 0x1.fp+5 ) = 0x1.739ce739ce73ap+0
++92/62
++near:PASSED:fdiv(0x1.7p+6 , 0x1.fp+5 ) = 0x1.7bdef7bdef7bep+0
++-62/62
++zero:PASSED:fdiv(-0x1.fp+5 , 0x1.fp+5 ) = -0x1p+0
++-64/62
++zero:PASSED:fdiv(-0x1p+6 , 0x1.fp+5 ) = -0x1.0842108421084p+0
++-66/62
++zero:PASSED:fdiv(-0x1.08p+6 , 0x1.fp+5 ) = -0x1.1084210842108p+0
++-100/62
++zero:PASSED:fdiv(-0x1.9p+6 , 0x1.fp+5 ) = -0x1.9ce739ce739cep+0
++zero:PASSED:fdiv(0x0.0000000000001p-1022, -0x1p+1 ) = -0x0p+0
++-102/62
++zero:PASSED:fdiv(-0x1.98p+6 , 0x1.fp+5 ) = -0x1.a5294a5294a52p+0
++-106/62
++zero:PASSED:fdiv(-0x1.a8p+6 , 0x1.fp+5 ) = -0x1.b5ad6b5ad6b5ap+0
++-108/62
++zero:PASSED:fdiv(-0x1.bp+6 , 0x1.fp+5 ) = -0x1.bdef7bdef7bdep+0
++-108/108
++zero:PASSED:fdiv(-0x1.bp+6 , 0x1.bp+6 ) = -0x1p+0
++-112/62
++zero:PASSED:fdiv(-0x1.cp+6 , 0x1.fp+5 ) = -0x1.ce739ce739ce7p+0
++-114/62
++zero:PASSED:fdiv(-0x1.c8p+6 , 0x1.fp+5 ) = -0x1.d6b5ad6b5ad6bp+0
++-116/62
++zero:PASSED:fdiv(-0x1.dp+6 , 0x1.fp+5 ) = -0x1.def7bdef7bdefp+0
++zero:PASSED:fdiv(0x0.0000000000003p-1022, -0x1p+1 ) = -0x0.0000000000001p-1022
++-118/62
++zero:PASSED:fdiv(-0x1.d8p+6 , 0x1.fp+5 ) = -0x1.e739ce739ce73p+0
++-90/62
++zero:PASSED:fdiv(-0x1.68p+6 , 0x1.fp+5 ) = -0x1.739ce739ce739p+0
++-92/62
++zero:PASSED:fdiv(-0x1.7p+6 , 0x1.fp+5 ) = -0x1.7bdef7bdef7bdp+0
++62/62
++zero:PASSED:fdiv(0x1.fp+5 , 0x1.fp+5 ) = 0x1p+0
++64/62
++zero:PASSED:fdiv(0x1p+6 , 0x1.fp+5 ) = 0x1.0842108421084p+0
++66/62
++zero:PASSED:fdiv(0x1.08p+6 , 0x1.fp+5 ) = 0x1.1084210842108p+0
++100/62
++zero:PASSED:fdiv(0x1.9p+6 , 0x1.fp+5 ) = 0x1.9ce739ce739cep+0
++zero:PASSED:fdiv(0x0.0000000000001p-1022, 0x1p+1 ) = 0x0p+0
++102/62
++zero:PASSED:fdiv(0x1.98p+6 , 0x1.fp+5 ) = 0x1.a5294a5294a52p+0
++106/62
++zero:PASSED:fdiv(0x1.a8p+6 , 0x1.fp+5 ) = 0x1.b5ad6b5ad6b5ap+0
++108/62
++zero:PASSED:fdiv(0x1.bp+6 , 0x1.fp+5 ) = 0x1.bdef7bdef7bdep+0
++108/108
++zero:PASSED:fdiv(0x1.bp+6 , 0x1.bp+6 ) = 0x1p+0
++112/62
++zero:PASSED:fdiv(0x1.cp+6 , 0x1.fp+5 ) = 0x1.ce739ce739ce7p+0
++114/62
++zero:PASSED:fdiv(0x1.c8p+6 , 0x1.fp+5 ) = 0x1.d6b5ad6b5ad6bp+0
++116/62
++zero:PASSED:fdiv(0x1.dp+6 , 0x1.fp+5 ) = 0x1.def7bdef7bdefp+0
++zero:PASSED:fdiv(0x0.0000000000003p-1022, 0x1p+1 ) = 0x0.0000000000001p-1022
++118/62
++zero:PASSED:fdiv(0x1.d8p+6 , 0x1.fp+5 ) = 0x1.e739ce739ce73p+0
++90/62
++zero:PASSED:fdiv(0x1.68p+6 , 0x1.fp+5 ) = 0x1.739ce739ce739p+0
++92/62
++zero:PASSED:fdiv(0x1.7p+6 , 0x1.fp+5 ) = 0x1.7bdef7bdef7bdp+0
++-62/62
+++inf:PASSED:fdiv(-0x1.fp+5 , 0x1.fp+5 ) = -0x1p+0
++-64/62
+++inf:PASSED:fdiv(-0x1p+6 , 0x1.fp+5 ) = -0x1.0842108421084p+0
++-66/62
+++inf:PASSED:fdiv(-0x1.08p+6 , 0x1.fp+5 ) = -0x1.1084210842108p+0
++-100/62
+++inf:PASSED:fdiv(-0x1.9p+6 , 0x1.fp+5 ) = -0x1.9ce739ce739cep+0
+++inf:PASSED:fdiv(0x0.0000000000001p-1022, -0x1p+1 ) = -0x0p+0
++-102/62
+++inf:PASSED:fdiv(-0x1.98p+6 , 0x1.fp+5 ) = -0x1.a5294a5294a52p+0
++-106/62
+++inf:PASSED:fdiv(-0x1.a8p+6 , 0x1.fp+5 ) = -0x1.b5ad6b5ad6b5ap+0
++-108/62
+++inf:PASSED:fdiv(-0x1.bp+6 , 0x1.fp+5 ) = -0x1.bdef7bdef7bdep+0
++-108/108
+++inf:PASSED:fdiv(-0x1.bp+6 , 0x1.bp+6 ) = -0x1p+0
++-112/62
+++inf:PASSED:fdiv(-0x1.cp+6 , 0x1.fp+5 ) = -0x1.ce739ce739ce7p+0
++-114/62
+++inf:PASSED:fdiv(-0x1.c8p+6 , 0x1.fp+5 ) = -0x1.d6b5ad6b5ad6bp+0
++-116/62
+++inf:PASSED:fdiv(-0x1.dp+6 , 0x1.fp+5 ) = -0x1.def7bdef7bdefp+0
+++inf:PASSED:fdiv(0x0.0000000000003p-1022, -0x1p+1 ) = -0x0.0000000000001p-1022
++-118/62
+++inf:PASSED:fdiv(-0x1.d8p+6 , 0x1.fp+5 ) = -0x1.e739ce739ce73p+0
++-90/62
+++inf:PASSED:fdiv(-0x1.68p+6 , 0x1.fp+5 ) = -0x1.739ce739ce739p+0
++-92/62
+++inf:PASSED:fdiv(-0x1.7p+6 , 0x1.fp+5 ) = -0x1.7bdef7bdef7bdp+0
++62/62
+++inf:PASSED:fdiv(0x1.fp+5 , 0x1.fp+5 ) = 0x1p+0
++64/62
+++inf:PASSED:fdiv(0x1p+6 , 0x1.fp+5 ) = 0x1.0842108421085p+0
++66/62
+++inf:PASSED:fdiv(0x1.08p+6 , 0x1.fp+5 ) = 0x1.1084210842109p+0
++100/62
+++inf:PASSED:fdiv(0x1.9p+6 , 0x1.fp+5 ) = 0x1.9ce739ce739cfp+0
+++inf:PASSED:fdiv(0x0.0000000000001p-1022, 0x1p+1 ) = 0x0.0000000000001p-1022
++102/62
+++inf:PASSED:fdiv(0x1.98p+6 , 0x1.fp+5 ) = 0x1.a5294a5294a53p+0
++106/62
+++inf:PASSED:fdiv(0x1.a8p+6 , 0x1.fp+5 ) = 0x1.b5ad6b5ad6b5bp+0
++108/62
+++inf:PASSED:fdiv(0x1.bp+6 , 0x1.fp+5 ) = 0x1.bdef7bdef7bdfp+0
++108/108
+++inf:PASSED:fdiv(0x1.bp+6 , 0x1.bp+6 ) = 0x1p+0
++112/62
+++inf:PASSED:fdiv(0x1.cp+6 , 0x1.fp+5 ) = 0x1.ce739ce739ce8p+0
++114/62
+++inf:PASSED:fdiv(0x1.c8p+6 , 0x1.fp+5 ) = 0x1.d6b5ad6b5ad6cp+0
++116/62
+++inf:PASSED:fdiv(0x1.dp+6 , 0x1.fp+5 ) = 0x1.def7bdef7bdfp+0
+++inf:PASSED:fdiv(0x0.0000000000003p-1022, 0x1p+1 ) = 0x0.0000000000002p-1022
++118/62
+++inf:PASSED:fdiv(0x1.d8p+6 , 0x1.fp+5 ) = 0x1.e739ce739ce74p+0
++90/62
+++inf:PASSED:fdiv(0x1.68p+6 , 0x1.fp+5 ) = 0x1.739ce739ce73ap+0
++92/62
+++inf:PASSED:fdiv(0x1.7p+6 , 0x1.fp+5 ) = 0x1.7bdef7bdef7bep+0
++-62/62
++-inf:PASSED:fdiv(-0x1.fp+5 , 0x1.fp+5 ) = -0x1p+0
++-64/62
++-inf:PASSED:fdiv(-0x1p+6 , 0x1.fp+5 ) = -0x1.0842108421085p+0
++-66/62
++-inf:PASSED:fdiv(-0x1.08p+6 , 0x1.fp+5 ) = -0x1.1084210842109p+0
++-100/62
++-inf:PASSED:fdiv(-0x1.9p+6 , 0x1.fp+5 ) = -0x1.9ce739ce739cfp+0
++-inf:PASSED:fdiv(0x0.0000000000001p-1022, -0x1p+1 ) = -0x0.0000000000001p-1022
++-102/62
++-inf:PASSED:fdiv(-0x1.98p+6 , 0x1.fp+5 ) = -0x1.a5294a5294a53p+0
++-106/62
++-inf:PASSED:fdiv(-0x1.a8p+6 , 0x1.fp+5 ) = -0x1.b5ad6b5ad6b5bp+0
++-108/62
++-inf:PASSED:fdiv(-0x1.bp+6 , 0x1.fp+5 ) = -0x1.bdef7bdef7bdfp+0
++-108/108
++-inf:PASSED:fdiv(-0x1.bp+6 , 0x1.bp+6 ) = -0x1p+0
++-112/62
++-inf:PASSED:fdiv(-0x1.cp+6 , 0x1.fp+5 ) = -0x1.ce739ce739ce8p+0
++-114/62
++-inf:PASSED:fdiv(-0x1.c8p+6 , 0x1.fp+5 ) = -0x1.d6b5ad6b5ad6cp+0
++-116/62
++-inf:PASSED:fdiv(-0x1.dp+6 , 0x1.fp+5 ) = -0x1.def7bdef7bdfp+0
++-inf:PASSED:fdiv(0x0.0000000000003p-1022, -0x1p+1 ) = -0x0.0000000000002p-1022
++-118/62
++-inf:PASSED:fdiv(-0x1.d8p+6 , 0x1.fp+5 ) = -0x1.e739ce739ce74p+0
++-90/62
++-inf:PASSED:fdiv(-0x1.68p+6 , 0x1.fp+5 ) = -0x1.739ce739ce73ap+0
++-92/62
++-inf:PASSED:fdiv(-0x1.7p+6 , 0x1.fp+5 ) = -0x1.7bdef7bdef7bep+0
++62/62
++-inf:PASSED:fdiv(0x1.fp+5 , 0x1.fp+5 ) = 0x1p+0
++64/62
++-inf:PASSED:fdiv(0x1p+6 , 0x1.fp+5 ) = 0x1.0842108421084p+0
++66/62
++-inf:PASSED:fdiv(0x1.08p+6 , 0x1.fp+5 ) = 0x1.1084210842108p+0
++100/62
++-inf:PASSED:fdiv(0x1.9p+6 , 0x1.fp+5 ) = 0x1.9ce739ce739cep+0
++-inf:PASSED:fdiv(0x0.0000000000001p-1022, 0x1p+1 ) = 0x0p+0
++102/62
++-inf:PASSED:fdiv(0x1.98p+6 , 0x1.fp+5 ) = 0x1.a5294a5294a52p+0
++106/62
++-inf:PASSED:fdiv(0x1.a8p+6 , 0x1.fp+5 ) = 0x1.b5ad6b5ad6b5ap+0
++108/62
++-inf:PASSED:fdiv(0x1.bp+6 , 0x1.fp+5 ) = 0x1.bdef7bdef7bdep+0
++108/108
++-inf:PASSED:fdiv(0x1.bp+6 , 0x1.bp+6 ) = 0x1p+0
++112/62
++-inf:PASSED:fdiv(0x1.cp+6 , 0x1.fp+5 ) = 0x1.ce739ce739ce7p+0
++114/62
++-inf:PASSED:fdiv(0x1.c8p+6 , 0x1.fp+5 ) = 0x1.d6b5ad6b5ad6bp+0
++116/62
++-inf:PASSED:fdiv(0x1.dp+6 , 0x1.fp+5 ) = 0x1.def7bdef7bdefp+0
++-inf:PASSED:fdiv(0x0.0000000000003p-1022, 0x1p+1 ) = 0x0.0000000000001p-1022
++118/62
++-inf:PASSED:fdiv(0x1.d8p+6 , 0x1.fp+5 ) = 0x1.e739ce739ce73p+0
++90/62
++-inf:PASSED:fdiv(0x1.68p+6 , 0x1.fp+5 ) = 0x1.739ce739ce739p+0
++92/62
++-inf:PASSED:fdiv(0x1.7p+6 , 0x1.fp+5 ) = 0x1.7bdef7bdef7bdp+0
++near:PASSED:fmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.ap+0
++near:PASSED:fmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0
++near:PASSED:fmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0
++near:PASSED:fmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000004p+0
++near:PASSED:fmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0
++near:PASSED:fmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000006p+0
++near:PASSED:fmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0
++near:PASSED:fmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0
++near:PASSED:fmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0
++near:PASSED:fmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0
++near:PASSED:fmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0
++near:PASSED:fmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000dp+0
++near:PASSED:fmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0
++near:PASSED:fmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000fp+0
++near:PASSED:fmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0
++near:PASSED:fmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0
++near:PASSED:fmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.ap+0
++near:PASSED:fmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0
++near:PASSED:fmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0
++near:PASSED:fmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000004p+0
++near:PASSED:fmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0
++near:PASSED:fmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000006p+0
++near:PASSED:fmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0
++near:PASSED:fmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0
++near:PASSED:fmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0
++near:PASSED:fmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0
++near:PASSED:fmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0
++near:PASSED:fmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000dp+0
++near:PASSED:fmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0
++near:PASSED:fmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000fp+0
++near:PASSED:fmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0
++near:PASSED:fmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0
++zero:PASSED:fmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.ap+0
++zero:PASSED:fmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000001p+0
++zero:PASSED:fmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0
++zero:PASSED:fmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0
++zero:PASSED:fmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0
++zero:PASSED:fmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000006p+0
++zero:PASSED:fmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0
++zero:PASSED:fmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0
++zero:PASSED:fmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000009p+0
++zero:PASSED:fmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0
++zero:PASSED:fmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0
++zero:PASSED:fmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0
++zero:PASSED:fmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0
++zero:PASSED:fmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000fp+0
++zero:PASSED:fmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0
++zero:PASSED:fmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0
++zero:PASSED:fmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.ap+0
++zero:PASSED:fmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000001p+0
++zero:PASSED:fmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0
++zero:PASSED:fmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0
++zero:PASSED:fmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0
++zero:PASSED:fmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000006p+0
++zero:PASSED:fmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0
++zero:PASSED:fmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0
++zero:PASSED:fmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000009p+0
++zero:PASSED:fmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0
++zero:PASSED:fmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0
++zero:PASSED:fmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0
++zero:PASSED:fmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0
++zero:PASSED:fmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000fp+0
++zero:PASSED:fmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0
++zero:PASSED:fmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0
+++inf:PASSED:fmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.ap+0
+++inf:PASSED:fmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000001p+0
+++inf:PASSED:fmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0
+++inf:PASSED:fmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0
+++inf:PASSED:fmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0
+++inf:PASSED:fmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000006p+0
+++inf:PASSED:fmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0
+++inf:PASSED:fmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0
+++inf:PASSED:fmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000009p+0
+++inf:PASSED:fmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0
+++inf:PASSED:fmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0
+++inf:PASSED:fmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0
+++inf:PASSED:fmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0
+++inf:PASSED:fmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000fp+0
+++inf:PASSED:fmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0
+++inf:PASSED:fmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0
+++inf:PASSED:fmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000001p+0
+++inf:PASSED:fmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0
+++inf:PASSED:fmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0
+++inf:PASSED:fmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000004p+0
+++inf:PASSED:fmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0
+++inf:PASSED:fmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0
+++inf:PASSED:fmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0
+++inf:PASSED:fmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000009p+0
+++inf:PASSED:fmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0
+++inf:PASSED:fmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0
+++inf:PASSED:fmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0
+++inf:PASSED:fmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000dp+0
+++inf:PASSED:fmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0
+++inf:PASSED:fmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0
+++inf:PASSED:fmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0
+++inf:PASSED:fmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000012p+0
++-inf:PASSED:fmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000001p+0
++-inf:PASSED:fmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0
++-inf:PASSED:fmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0
++-inf:PASSED:fmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000004p+0
++-inf:PASSED:fmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0
++-inf:PASSED:fmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0
++-inf:PASSED:fmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0
++-inf:PASSED:fmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000009p+0
++-inf:PASSED:fmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0
++-inf:PASSED:fmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0
++-inf:PASSED:fmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0
++-inf:PASSED:fmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000dp+0
++-inf:PASSED:fmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0
++-inf:PASSED:fmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0
++-inf:PASSED:fmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0
++-inf:PASSED:fmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000012p+0
++-inf:PASSED:fmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.ap+0
++-inf:PASSED:fmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000001p+0
++-inf:PASSED:fmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0
++-inf:PASSED:fmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0
++-inf:PASSED:fmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0
++-inf:PASSED:fmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000006p+0
++-inf:PASSED:fmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0
++-inf:PASSED:fmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0
++-inf:PASSED:fmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000009p+0
++-inf:PASSED:fmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0
++-inf:PASSED:fmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0
++-inf:PASSED:fmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0
++-inf:PASSED:fmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0
++-inf:PASSED:fmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000fp+0
++-inf:PASSED:fmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0
++-inf:PASSED:fmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0
++near:PASSED:fmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.ap+0
++near:PASSED:fmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0
++near:PASSED:fmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0
++near:PASSED:fmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000004p+0
++near:PASSED:fmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0
++near:PASSED:fmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000006p+0
++near:PASSED:fmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0
++near:PASSED:fmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0
++near:PASSED:fmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0
++near:PASSED:fmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0
++near:PASSED:fmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0
++near:PASSED:fmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000dp+0
++near:PASSED:fmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0
++near:PASSED:fmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000fp+0
++near:PASSED:fmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0
++near:PASSED:fmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0
++near:PASSED:fmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.ap+0
++near:PASSED:fmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0
++near:PASSED:fmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0
++near:PASSED:fmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000004p+0
++near:PASSED:fmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0
++near:PASSED:fmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000006p+0
++near:PASSED:fmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0
++near:PASSED:fmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0
++near:PASSED:fmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0
++near:PASSED:fmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0
++near:PASSED:fmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0
++near:PASSED:fmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000dp+0
++near:PASSED:fmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0
++near:PASSED:fmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000fp+0
++near:PASSED:fmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0
++near:PASSED:fmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0
++zero:PASSED:fmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.ap+0
++zero:PASSED:fmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000001p+0
++zero:PASSED:fmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0
++zero:PASSED:fmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0
++zero:PASSED:fmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0
++zero:PASSED:fmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000006p+0
++zero:PASSED:fmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0
++zero:PASSED:fmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0
++zero:PASSED:fmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000009p+0
++zero:PASSED:fmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0
++zero:PASSED:fmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0
++zero:PASSED:fmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0
++zero:PASSED:fmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0
++zero:PASSED:fmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000fp+0
++zero:PASSED:fmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0
++zero:PASSED:fmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0
++zero:PASSED:fmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.ap+0
++zero:PASSED:fmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000001p+0
++zero:PASSED:fmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0
++zero:PASSED:fmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0
++zero:PASSED:fmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0
++zero:PASSED:fmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000006p+0
++zero:PASSED:fmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0
++zero:PASSED:fmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0
++zero:PASSED:fmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000009p+0
++zero:PASSED:fmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0
++zero:PASSED:fmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0
++zero:PASSED:fmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0
++zero:PASSED:fmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0
++zero:PASSED:fmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000fp+0
++zero:PASSED:fmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0
++zero:PASSED:fmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0
+++inf:PASSED:fmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.ap+0
+++inf:PASSED:fmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000001p+0
+++inf:PASSED:fmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0
+++inf:PASSED:fmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0
+++inf:PASSED:fmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0
+++inf:PASSED:fmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000006p+0
+++inf:PASSED:fmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0
+++inf:PASSED:fmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0
+++inf:PASSED:fmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000009p+0
+++inf:PASSED:fmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0
+++inf:PASSED:fmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0
+++inf:PASSED:fmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0
+++inf:PASSED:fmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0
+++inf:PASSED:fmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000fp+0
+++inf:PASSED:fmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0
+++inf:PASSED:fmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0
+++inf:PASSED:fmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000001p+0
+++inf:PASSED:fmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0
+++inf:PASSED:fmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0
+++inf:PASSED:fmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000004p+0
+++inf:PASSED:fmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0
+++inf:PASSED:fmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0
+++inf:PASSED:fmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0
+++inf:PASSED:fmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000009p+0
+++inf:PASSED:fmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0
+++inf:PASSED:fmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0
+++inf:PASSED:fmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0
+++inf:PASSED:fmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000dp+0
+++inf:PASSED:fmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0
+++inf:PASSED:fmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0
+++inf:PASSED:fmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0
+++inf:PASSED:fmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000012p+0
++-inf:PASSED:fmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000001p+0
++-inf:PASSED:fmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0
++-inf:PASSED:fmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0
++-inf:PASSED:fmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000004p+0
++-inf:PASSED:fmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0
++-inf:PASSED:fmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0
++-inf:PASSED:fmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0
++-inf:PASSED:fmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000009p+0
++-inf:PASSED:fmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0
++-inf:PASSED:fmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0
++-inf:PASSED:fmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0
++-inf:PASSED:fmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000dp+0
++-inf:PASSED:fmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0
++-inf:PASSED:fmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0
++-inf:PASSED:fmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0
++-inf:PASSED:fmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000012p+0
++-inf:PASSED:fmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.ap+0
++-inf:PASSED:fmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000001p+0
++-inf:PASSED:fmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0
++-inf:PASSED:fmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0
++-inf:PASSED:fmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0
++-inf:PASSED:fmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000006p+0
++-inf:PASSED:fmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0
++-inf:PASSED:fmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0
++-inf:PASSED:fmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000009p+0
++-inf:PASSED:fmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0
++-inf:PASSED:fmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0
++-inf:PASSED:fmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0
++-inf:PASSED:fmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0
++-inf:PASSED:fmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000fp+0
++-inf:PASSED:fmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0
++-inf:PASSED:fmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0
++near:PASSED:fnmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.ap+0
++near:PASSED:fnmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0
++near:PASSED:fnmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0
++near:PASSED:fnmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000004p+0
++near:PASSED:fnmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0
++near:PASSED:fnmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000006p+0
++near:PASSED:fnmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0
++near:PASSED:fnmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0
++near:PASSED:fnmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0
++near:PASSED:fnmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0
++near:PASSED:fnmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0
++near:PASSED:fnmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000dp+0
++near:PASSED:fnmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0
++near:PASSED:fnmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000fp+0
++near:PASSED:fnmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0
++near:PASSED:fnmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0
++near:PASSED:fnmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.ap+0
++near:PASSED:fnmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0
++near:PASSED:fnmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0
++near:PASSED:fnmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000004p+0
++near:PASSED:fnmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0
++near:PASSED:fnmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000006p+0
++near:PASSED:fnmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0
++near:PASSED:fnmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0
++near:PASSED:fnmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0
++near:PASSED:fnmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0
++near:PASSED:fnmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0
++near:PASSED:fnmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000dp+0
++near:PASSED:fnmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0
++near:PASSED:fnmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000fp+0
++near:PASSED:fnmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0
++near:PASSED:fnmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0
++zero:PASSED:fnmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.ap+0
++zero:PASSED:fnmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000001p+0
++zero:PASSED:fnmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0
++zero:PASSED:fnmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0
++zero:PASSED:fnmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0
++zero:PASSED:fnmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000006p+0
++zero:PASSED:fnmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0
++zero:PASSED:fnmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0
++zero:PASSED:fnmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000009p+0
++zero:PASSED:fnmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0
++zero:PASSED:fnmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0
++zero:PASSED:fnmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0
++zero:PASSED:fnmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0
++zero:PASSED:fnmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000fp+0
++zero:PASSED:fnmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0
++zero:PASSED:fnmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0
++zero:PASSED:fnmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.ap+0
++zero:PASSED:fnmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000001p+0
++zero:PASSED:fnmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0
++zero:PASSED:fnmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0
++zero:PASSED:fnmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0
++zero:PASSED:fnmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000006p+0
++zero:PASSED:fnmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0
++zero:PASSED:fnmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0
++zero:PASSED:fnmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000009p+0
++zero:PASSED:fnmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0
++zero:PASSED:fnmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0
++zero:PASSED:fnmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0
++zero:PASSED:fnmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0
++zero:PASSED:fnmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000fp+0
++zero:PASSED:fnmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0
++zero:PASSED:fnmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0
+++inf:PASSED:fnmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.ap+0
+++inf:PASSED:fnmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000001p+0
+++inf:PASSED:fnmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0
+++inf:PASSED:fnmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0
+++inf:PASSED:fnmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0
+++inf:PASSED:fnmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000006p+0
+++inf:PASSED:fnmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0
+++inf:PASSED:fnmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0
+++inf:PASSED:fnmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000009p+0
+++inf:PASSED:fnmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0
+++inf:PASSED:fnmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0
+++inf:PASSED:fnmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0
+++inf:PASSED:fnmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0
+++inf:PASSED:fnmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000fp+0
+++inf:PASSED:fnmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0
+++inf:PASSED:fnmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0
+++inf:PASSED:fnmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000001p+0
+++inf:PASSED:fnmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0
+++inf:PASSED:fnmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0
+++inf:PASSED:fnmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000004p+0
+++inf:PASSED:fnmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0
+++inf:PASSED:fnmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0
+++inf:PASSED:fnmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0
+++inf:PASSED:fnmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000009p+0
+++inf:PASSED:fnmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0
+++inf:PASSED:fnmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0
+++inf:PASSED:fnmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0
+++inf:PASSED:fnmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000dp+0
+++inf:PASSED:fnmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0
+++inf:PASSED:fnmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0
+++inf:PASSED:fnmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0
+++inf:PASSED:fnmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000012p+0
++-inf:PASSED:fnmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000001p+0
++-inf:PASSED:fnmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0
++-inf:PASSED:fnmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0
++-inf:PASSED:fnmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000004p+0
++-inf:PASSED:fnmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0
++-inf:PASSED:fnmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0
++-inf:PASSED:fnmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0
++-inf:PASSED:fnmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000009p+0
++-inf:PASSED:fnmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0
++-inf:PASSED:fnmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0
++-inf:PASSED:fnmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0
++-inf:PASSED:fnmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000dp+0
++-inf:PASSED:fnmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0
++-inf:PASSED:fnmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0
++-inf:PASSED:fnmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0
++-inf:PASSED:fnmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000012p+0
++-inf:PASSED:fnmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.ap+0
++-inf:PASSED:fnmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000001p+0
++-inf:PASSED:fnmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0
++-inf:PASSED:fnmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0
++-inf:PASSED:fnmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0
++-inf:PASSED:fnmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000006p+0
++-inf:PASSED:fnmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0
++-inf:PASSED:fnmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0
++-inf:PASSED:fnmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000009p+0
++-inf:PASSED:fnmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0
++-inf:PASSED:fnmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0
++-inf:PASSED:fnmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0
++-inf:PASSED:fnmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0
++-inf:PASSED:fnmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000fp+0
++-inf:PASSED:fnmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0
++-inf:PASSED:fnmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0
++near:PASSED:fnmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.ap+0
++near:PASSED:fnmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0
++near:PASSED:fnmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0
++near:PASSED:fnmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000004p+0
++near:PASSED:fnmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0
++near:PASSED:fnmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000006p+0
++near:PASSED:fnmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0
++near:PASSED:fnmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0
++near:PASSED:fnmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0
++near:PASSED:fnmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0
++near:PASSED:fnmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0
++near:PASSED:fnmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000dp+0
++near:PASSED:fnmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0
++near:PASSED:fnmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000fp+0
++near:PASSED:fnmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0
++near:PASSED:fnmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0
++near:PASSED:fnmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.ap+0
++near:PASSED:fnmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0
++near:PASSED:fnmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0
++near:PASSED:fnmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000004p+0
++near:PASSED:fnmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0
++near:PASSED:fnmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000006p+0
++near:PASSED:fnmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0
++near:PASSED:fnmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0
++near:PASSED:fnmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0
++near:PASSED:fnmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0
++near:PASSED:fnmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0
++near:PASSED:fnmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000dp+0
++near:PASSED:fnmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0
++near:PASSED:fnmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000fp+0
++near:PASSED:fnmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0
++near:PASSED:fnmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0
++zero:PASSED:fnmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.ap+0
++zero:PASSED:fnmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000001p+0
++zero:PASSED:fnmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0
++zero:PASSED:fnmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0
++zero:PASSED:fnmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0
++zero:PASSED:fnmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000006p+0
++zero:PASSED:fnmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0
++zero:PASSED:fnmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0
++zero:PASSED:fnmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000009p+0
++zero:PASSED:fnmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0
++zero:PASSED:fnmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0
++zero:PASSED:fnmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0
++zero:PASSED:fnmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0
++zero:PASSED:fnmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000fp+0
++zero:PASSED:fnmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0
++zero:PASSED:fnmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0
++zero:PASSED:fnmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.ap+0
++zero:PASSED:fnmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000001p+0
++zero:PASSED:fnmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0
++zero:PASSED:fnmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0
++zero:PASSED:fnmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0
++zero:PASSED:fnmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000006p+0
++zero:PASSED:fnmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0
++zero:PASSED:fnmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0
++zero:PASSED:fnmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000009p+0
++zero:PASSED:fnmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0
++zero:PASSED:fnmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0
++zero:PASSED:fnmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0
++zero:PASSED:fnmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0
++zero:PASSED:fnmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000fp+0
++zero:PASSED:fnmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0
++zero:PASSED:fnmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0
+++inf:PASSED:fnmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.ap+0
+++inf:PASSED:fnmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000001p+0
+++inf:PASSED:fnmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0
+++inf:PASSED:fnmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0
+++inf:PASSED:fnmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0
+++inf:PASSED:fnmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000006p+0
+++inf:PASSED:fnmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0
+++inf:PASSED:fnmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0
+++inf:PASSED:fnmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000009p+0
+++inf:PASSED:fnmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0
+++inf:PASSED:fnmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0
+++inf:PASSED:fnmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0
+++inf:PASSED:fnmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0
+++inf:PASSED:fnmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000fp+0
+++inf:PASSED:fnmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0
+++inf:PASSED:fnmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0
+++inf:PASSED:fnmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000001p+0
+++inf:PASSED:fnmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0
+++inf:PASSED:fnmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0
+++inf:PASSED:fnmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000004p+0
+++inf:PASSED:fnmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0
+++inf:PASSED:fnmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0
+++inf:PASSED:fnmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0
+++inf:PASSED:fnmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000009p+0
+++inf:PASSED:fnmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0
+++inf:PASSED:fnmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0
+++inf:PASSED:fnmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0
+++inf:PASSED:fnmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000dp+0
+++inf:PASSED:fnmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0
+++inf:PASSED:fnmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0
+++inf:PASSED:fnmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0
+++inf:PASSED:fnmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000012p+0
++-inf:PASSED:fnmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000001p+0
++-inf:PASSED:fnmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0
++-inf:PASSED:fnmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0
++-inf:PASSED:fnmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000004p+0
++-inf:PASSED:fnmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0
++-inf:PASSED:fnmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0
++-inf:PASSED:fnmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0
++-inf:PASSED:fnmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000009p+0
++-inf:PASSED:fnmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0
++-inf:PASSED:fnmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0
++-inf:PASSED:fnmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0
++-inf:PASSED:fnmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000dp+0
++-inf:PASSED:fnmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0
++-inf:PASSED:fnmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0
++-inf:PASSED:fnmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0
++-inf:PASSED:fnmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000012p+0
++-inf:PASSED:fnmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.ap+0
++-inf:PASSED:fnmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000001p+0
++-inf:PASSED:fnmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0
++-inf:PASSED:fnmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0
++-inf:PASSED:fnmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0
++-inf:PASSED:fnmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000006p+0
++-inf:PASSED:fnmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0
++-inf:PASSED:fnmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0
++-inf:PASSED:fnmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000009p+0
++-inf:PASSED:fnmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0
++-inf:PASSED:fnmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0
++-inf:PASSED:fnmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0
++-inf:PASSED:fnmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0
++-inf:PASSED:fnmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000fp+0
++-inf:PASSED:fnmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0
++-inf:PASSED:fnmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0
++near:PASSED:fsqrt(0x1.a44p-1 ) = 0x1.cfdcaf353049ep-1
++near:PASSED:fsqrt(0x1.a822p+0 ) = 0x1.498302b49cd6dp+0
++near:PASSED:fsqrt(0x1.05a2p+0 ) = 0x1.02cd13b44f3bfp+0
++near:PASSED:fsqrt(0x1.9504p-1 ) = 0x1.c76073cec0937p-1
++near:PASSED:fsqrt(0x1.dca2p+0 ) = 0x1.5d4f8d4e4c2b2p+0
++near:PASSED:fsqrt(0x1.02c8p+0 ) = 0x1.016309cde7483p+0
++near:PASSED:fsqrt(0x1.b9p-1 ) = 0x1.db2cfe686fe7cp-1
++near:PASSED:fsqrt(0x1.1d02p+0 ) = 0x1.0e1d62e78ed9ep+0
++near:PASSED:fsqrt(0x1.c39p-1 ) = 0x1.e0d526020fb6cp-1
++near:PASSED:fsqrt(0x1.9p-1 ) = 0x1.c48c6001f0acp-1
++near:PASSED:fsqrt(0x1.4852p+0 ) = 0x1.21e9ed813e2e3p+0
++near:PASSED:fsqrt(0x1.e984p-1 ) = 0x1.f4a1b09bbf0b1p-1
++near:PASSED:fsqrt(0x1.9a1p-1 ) = 0x1.ca34879b907afp-1
++near:PASSED:fsqrt(0x1.76b2p+0 ) = 0x1.35b6781aed828p+0
++zero:PASSED:fsqrt(0x1.a44p-1 ) = 0x1.cfdcaf353049ep-1
++zero:PASSED:fsqrt(0x1.a822p+0 ) = 0x1.498302b49cd6dp+0
++zero:PASSED:fsqrt(0x1.05a2p+0 ) = 0x1.02cd13b44f3bfp+0
++zero:PASSED:fsqrt(0x1.9504p-1 ) = 0x1.c76073cec0937p-1
++zero:PASSED:fsqrt(0x1.dca2p+0 ) = 0x1.5d4f8d4e4c2b2p+0
++zero:PASSED:fsqrt(0x1.02c8p+0 ) = 0x1.016309cde7483p+0
++zero:PASSED:fsqrt(0x1.b9p-1 ) = 0x1.db2cfe686fe7cp-1
++zero:PASSED:fsqrt(0x1.1d02p+0 ) = 0x1.0e1d62e78ed9dp+0
++zero:PASSED:fsqrt(0x1.c39p-1 ) = 0x1.e0d526020fb6bp-1
++zero:PASSED:fsqrt(0x1.9p-1 ) = 0x1.c48c6001f0abfp-1
++zero:PASSED:fsqrt(0x1.4852p+0 ) = 0x1.21e9ed813e2e2p+0
++zero:PASSED:fsqrt(0x1.e984p-1 ) = 0x1.f4a1b09bbf0bp-1
++zero:PASSED:fsqrt(0x1.9a1p-1 ) = 0x1.ca34879b907aep-1
++zero:PASSED:fsqrt(0x1.76b2p+0 ) = 0x1.35b6781aed827p+0
+++inf:PASSED:fsqrt(0x1.a44p-1 ) = 0x1.cfdcaf353049fp-1
+++inf:PASSED:fsqrt(0x1.a822p+0 ) = 0x1.498302b49cd6ep+0
+++inf:PASSED:fsqrt(0x1.05a2p+0 ) = 0x1.02cd13b44f3cp+0
+++inf:PASSED:fsqrt(0x1.9504p-1 ) = 0x1.c76073cec0938p-1
+++inf:PASSED:fsqrt(0x1.dca2p+0 ) = 0x1.5d4f8d4e4c2b3p+0
+++inf:PASSED:fsqrt(0x1.02c8p+0 ) = 0x1.016309cde7484p+0
+++inf:PASSED:fsqrt(0x1.b9p-1 ) = 0x1.db2cfe686fe7dp-1
+++inf:PASSED:fsqrt(0x1.1d02p+0 ) = 0x1.0e1d62e78ed9ep+0
+++inf:PASSED:fsqrt(0x1.c39p-1 ) = 0x1.e0d526020fb6cp-1
+++inf:PASSED:fsqrt(0x1.9p-1 ) = 0x1.c48c6001f0acp-1
+++inf:PASSED:fsqrt(0x1.4852p+0 ) = 0x1.21e9ed813e2e3p+0
+++inf:PASSED:fsqrt(0x1.e984p-1 ) = 0x1.f4a1b09bbf0b1p-1
+++inf:PASSED:fsqrt(0x1.9a1p-1 ) = 0x1.ca34879b907afp-1
+++inf:PASSED:fsqrt(0x1.76b2p+0 ) = 0x1.35b6781aed828p+0
++-inf:PASSED:fsqrt(0x1.a44p-1 ) = 0x1.cfdcaf353049ep-1
++-inf:PASSED:fsqrt(0x1.a822p+0 ) = 0x1.498302b49cd6dp+0
++-inf:PASSED:fsqrt(0x1.05a2p+0 ) = 0x1.02cd13b44f3bfp+0
++-inf:PASSED:fsqrt(0x1.9504p-1 ) = 0x1.c76073cec0937p-1
++-inf:PASSED:fsqrt(0x1.dca2p+0 ) = 0x1.5d4f8d4e4c2b2p+0
++-inf:PASSED:fsqrt(0x1.02c8p+0 ) = 0x1.016309cde7483p+0
++-inf:PASSED:fsqrt(0x1.b9p-1 ) = 0x1.db2cfe686fe7cp-1
++-inf:PASSED:fsqrt(0x1.1d02p+0 ) = 0x1.0e1d62e78ed9dp+0
++-inf:PASSED:fsqrt(0x1.c39p-1 ) = 0x1.e0d526020fb6bp-1
++-inf:PASSED:fsqrt(0x1.9p-1 ) = 0x1.c48c6001f0abfp-1
++-inf:PASSED:fsqrt(0x1.4852p+0 ) = 0x1.21e9ed813e2e2p+0
++-inf:PASSED:fsqrt(0x1.e984p-1 ) = 0x1.f4a1b09bbf0bp-1
++-inf:PASSED:fsqrt(0x1.9a1p-1 ) = 0x1.ca34879b907aep-1
++-inf:PASSED:fsqrt(0x1.76b2p+0 ) = 0x1.35b6781aed827p+0
+diff --git a/none/tests/ppc32/test_dfp4.c b/none/tests/ppc32/test_dfp4.c
+index 7cd8721..ebd3963 100644
+--- a/none/tests/ppc32/test_dfp4.c
++++ b/none/tests/ppc32/test_dfp4.c
+@@ -31,8 +31,13 @@ typedef union stuff {
+ _Decimal128 dec_val128;
+ unsigned long long u64_val;
+ struct {
++#if defined(VGP_ppc64le_linux)
++ unsigned long long vall;
++ unsigned long long valu;
++#else
+ unsigned long long valu;
+ unsigned long long vall;
++#endif
+ } u128;
+ } dfp_val_t;
+
+@@ -495,7 +500,6 @@ static void test_dfp_ClassAndGroupTest_ops(void)
+ test_val.u64_val = dfp64_vals[i];
+ } else {
+ test_val.u128.valu = dfp128_vals[i * 2];
+- test_val.u64_val = test_val.u128.valu;
+ test_val.u128.vall = dfp128_vals[(i * 2) + 1];
+ }
+
+@@ -509,11 +513,15 @@ again:
+ GET_CR(flags);
+
+ condreg = ((flags >> (4 * (7-BF)))) & 0xf;
+- printf("%s (DC/DG=%d) %s%016llx", test_def.name, data_class_OR_group,
+- test_def.op, test_val.u64_val);
++ printf("%s (DC/DG=%d) %s", test_def.name, data_class_OR_group,
++ test_def.op);
+ if (test_def.precision == QUAD_TEST) {
+- printf(" %016llx", test_val.u128.vall);
++ printf("%016llx %016llx", test_val.u128.valu, test_val.u128.vall);
++ } else {
++ printf("%016llx", test_val.u64_val);
+ }
++
++ //%016llx
+ printf(" => %x (BF=%d)\n", condreg, BF);
+ }
+ if (repeat) {
+@@ -562,10 +570,8 @@ again:
+ test_val2.u64_val = dfp64_vals[test_def.targs[i].frb_idx];
+ } else {
+ test_val1.u128.valu = dfp128_vals[test_def.targs[i].fra_idx * 2];
+- test_val1.u64_val = test_val1.u128.valu;
+ test_val1.u128.vall = dfp128_vals[(test_def.targs[i].fra_idx * 2) + 1];
+ test_val2.u128.valu = dfp128_vals[test_def.targs[i].frb_idx * 2];
+- test_val2.u64_val = test_val2.u128.valu;
+ test_val2.u128.vall = dfp128_vals[(test_def.targs[i].frb_idx * 2) + 1];
+ }
+
+@@ -575,13 +581,13 @@ again:
+ GET_CR(flags);
+
+ condreg = ((flags >> (4 * (7-BF)))) & 0xf;
+- printf("%s %016llx", test_def.name, test_val1.u64_val);
++ printf("%s ", test_def.name);
+ if (test_def.precision == LONG_TEST) {
+- printf(" %s %016llx ",
+- test_def.op, test_val2.u64_val);
++ printf("%016llx %s %016llx ",
++ test_val1.u64_val, test_def.op, test_val2.u64_val);
+ } else {
+- printf(" %016llx %s %016llx %016llx ",
+- test_val1.u128.vall, test_def.op, test_val2.u128.valu, test_val2.u128.vall);
++ printf("%016llx %016llx %s %016llx %016llx ",
++ test_val1.u128.valu, test_val1.u128.vall, test_def.op, test_val2.u128.valu, test_val2.u128.vall);
+ }
+ printf(" => %x (BF=%d)\n", condreg, BF);
+ }
+diff --git a/none/tests/ppc32/test_dfp5.c b/none/tests/ppc32/test_dfp5.c
+index 64008b6..d8122d8 100644
+--- a/none/tests/ppc32/test_dfp5.c
++++ b/none/tests/ppc32/test_dfp5.c
+@@ -31,8 +31,13 @@ typedef union stuff {
+ _Decimal128 dec_val128;
+ unsigned long long u64_val;
+ struct {
++#if defined(VGP_ppc64le_linux)
++ unsigned long long vall;
++ unsigned long long valu;
++#else
+ unsigned long long valu;
+ unsigned long long vall;
++#endif
+ } u128;
+ } dfp_val_t;
+
+@@ -418,22 +423,20 @@ static void test_dfp_ddedpd_ops(void)
+ test_val.u64_val = dfp64_vals[i];
+ } else {
+ test_val.u128.valu = dfp128_vals[i * 2];
+- test_val.u64_val = test_val.u128.valu;
+ test_val.u128.vall = dfp128_vals[(i * 2) + 1];
+ }
+
+ for (SP = 0; SP < 4; SP++) {
+ dfp_val_t result;
+ result = (*func)(SP, test_val);
+- printf("%s (SP=%d) %s%016llx", test_def.name, SP,
+- test_def.op, test_val.u64_val);
+- if (test_def.precision == QUAD_TEST) {
+- printf(" %016llx", test_val.u128.vall);
++ printf("%s (SP=%d) %s", test_def.name, SP, test_def.op);
++ if (test_def.precision == LONG_TEST) {
++ printf("%016llx ==> %016llx\n", test_val.u64_val, result.u64_val);
++ } else {
++ printf("%016llx %016llx ==> %016llx %016llx\n",
++ test_val.u128.valu, test_val.u128.vall,
++ result.u128.valu, result.u128.vall);
+ }
+- if (test_def.precision == LONG_TEST)
+- printf(" ==> %016llx\n", result.u64_val);
+- else
+- printf(" ==> %016llx %016llx\n", result.u128.valu, result.u128.vall);
+ }
+ }
+ k++;
+@@ -484,20 +487,18 @@ static void test_dfp_denbcd_ops(void)
+ test_val.u64_val = bcd64_vals[i];
+ } else {
+ test_val.u128.valu = bcd128_vals[i * 2];
+- test_val.u64_val = test_val.u128.valu;
+ test_val.u128.vall = bcd128_vals[(i * 2) + 1];
+ }
+
+ result = (*func)(S, test_val);
+- printf("%s (S=%d) %s%016llx", test_def.name, S,
+- test_def.op, test_val.u64_val);
+- if (test_def.precision == QUAD_TEST) {
+- printf(" %016llx", test_val.u128.vall);
++ printf("%s (S=%d) %s", test_def.name, S, test_def.op);
++ if (test_def.precision == LONG_TEST) {
++ printf("%016llx ==> %016llx\n", test_val.u64_val, result.u64_val);
++ } else {
++ printf("%016llx %016llx ==> %016llx %016llx\n",
++ test_val.u128.valu, test_val.u128.vall,
++ result.u128.valu, result.u128.vall);
+ }
+- if (test_def.precision == LONG_TEST)
+- printf(" ==> %016llx\n", result.u64_val);
+- else
+- printf(" ==> %016llx %016llx\n", result.u128.valu, result.u128.vall);
+ }
+ }
+ k++;
+@@ -532,7 +533,6 @@ static void test_dfp_test_significance_ops(void)
+ test_valB.u64_val = dfp64_vals[i];
+ } else {
+ test_valB.u128.valu = dfp128_vals[i * 2];
+- test_valB.u64_val = test_valB.u128.valu;
+ test_valB.u128.vall = dfp128_vals[(i * 2) + 1];
+ }
+
+@@ -549,10 +549,11 @@ static void test_dfp_test_significance_ops(void)
+ GET_CR(flags);
+
+ condreg = ((flags >> (4 * (7-BF)))) & 0xf;
+- printf("%s (ref_sig=%d) %s%016llx", test_def.name, reference_sig,
+- test_def.op, test_valB.u64_val);
+- if (test_def.precision == QUAD_TEST) {
+- printf(" %016llx", test_valB.u128.vall);
++ printf("%s (ref_sig=%d) %s", test_def.name, reference_sig, test_def.op);
++ if (test_def.precision == LONG_TEST) {
++ printf("%016llx", test_valB.u64_val);
++ } else {
++ printf("%016llx %016llx", test_valB.u128.valu, test_valB.u128.vall);
+ }
+ printf(" => %x (BF=%d)\n", condreg, BF);
+ }
+diff --git a/none/tests/ppc32/test_isa_2_06_part1.c b/none/tests/ppc32/test_isa_2_06_part1.c
+index db28aa1..7cd4930 100644
+--- a/none/tests/ppc32/test_isa_2_06_part1.c
++++ b/none/tests/ppc32/test_isa_2_06_part1.c
+@@ -35,7 +35,12 @@ typedef uint32_t HWord_t;
+ typedef uint64_t HWord_t;
+ #endif /* __powerpc64__ */
+
+-static int errors;
++#ifdef VGP_ppc64le_linux
++#define isLE 1
++#else
++#define isLE 0
++#endif
++
+ register HWord_t r14 __asm__ ("r14");
+ register HWord_t r15 __asm__ ("r15");
+ register HWord_t r16 __asm__ ("r16");
+@@ -193,74 +198,14 @@ static void build_fargs_table(void)
+ }
+
+
+-typedef struct ftdiv_test {
+- int fra_idx;
+- int frb_idx;
+- int cr_flags;
+-} ftdiv_test_args_t;
+-
+ typedef struct fp_test_args {
+ int fra_idx;
+ int frb_idx;
+ int cr_flags;
+- unsigned long long dp_bin_result;
+ } fp_test_args_t;
+
+-unsigned long long xscvuxddp_results[] = {
+- 0x43cfec0000000000ULL,
+- 0x43d013c000000000ULL,
+- 0x4338000000b77501ULL,
+- 0x43dffa0000000001ULL,
+- 0x4372321456990000ULL,
+- 0x0000000000000000ULL,
+- 0x43e0000000000000ULL,
+- 0x43dffc0000000000ULL,
+- 0x43effe0000000000ULL,
+- 0x43dffe0000000000ULL,
+- 0x43efff0000000000ULL,
+- 0x43dffe0000000000ULL,
+- 0x43efff0000000000ULL,
+- 0x43e00106800000f0ULL,
+- 0x43e81a0ca1eb40f6ULL
+-};
+-
+-unsigned long long xscvsxddp_results[] = {
+- 0x43cfec0000000000ULL,
+- 0x43d013c000000000ULL,
+- 0x4338000000b77501ULL,
+- 0x43dffa0000000001ULL,
+- 0x4372321456990000ULL,
+- 0x0000000000000000ULL,
+- 0xc3e0000000000000ULL,
+- 0x43dffc0000000000ULL,
+- 0xc330000000000000ULL,
+- 0x43dffe0000000000ULL,
+- 0xc320000000000002ULL,
+- 0x43dffe0000000000ULL,
+- 0xc320000000000000ULL,
+- 0xc3dffdf2fffffe20ULL,
+- 0xc3cf97cd7852fc26ULL,
+-};
+-
+-unsigned long long xscvdpsxds_results[] = {
+- 0x0000000000000000ULL,
+- 0x000000000000003eULL,
+- 0x0000000000000000ULL,
+- 0x7fffffffffffffffULL,
+- 0x0000000000000000ULL,
+- 0x0000000000000000ULL,
+- 0x0000000000000000ULL,
+- 0x7fffffffffffffffULL,
+- 0x8000000000000000ULL,
+- 0x8000000000000000ULL,
+- 0x8000000000000000ULL,
+- 0x8000000000000000ULL,
+- 0x8000000000000000ULL,
+- 0x0000000000000000ULL,
+- 0xffffffffffffbe6cULL
+-};
+
+-ftdiv_test_args_t ftdiv_tests[] = {
++fp_test_args_t ftdiv_tests[] = {
+ {0, 1, 0x8},
+ {9, 1, 0xa},
+ {1, 12, 0xa},
+@@ -278,539 +223,539 @@ ftdiv_test_args_t ftdiv_tests[] = {
+ };
+
+ fp_test_args_t xscmpX_tests[] = {
+- {8, 8, 0x2, 0ULL},
+- {8, 14, 0x8, 0ULL},
+- {8, 6, 0x8, 0ULL},
+- {8, 5, 0x8, 0ULL},
+- {8, 4, 0x8, 0ULL},
+- {8, 7, 0x8, 0ULL},
+- {8, 9, 0x1, 0ULL},
+- {8, 11, 0x1, 0ULL},
+- {14, 8, 0x4, 0ULL},
+- {14, 14, 0x2, 0ULL},
+- {14, 6, 0x8, 0ULL},
+- {14, 5, 0x8, 0ULL},
+- {14, 4, 0x8, 0ULL},
+- {14, 7, 0x8, 0ULL},
+- {14, 9, 0x1, 0ULL},
+- {14, 11, 0x1, 0ULL},
+- {6, 8, 0x4, 0ULL},
+- {6, 14, 0x4, 0ULL},
+- {6, 6, 0x2, 0ULL},
+- {6, 5, 0x2, 0ULL},
+- {6, 4, 0x8, 0ULL},
+- {6, 7, 0x8, 0ULL},
+- {6, 9, 0x1, 0ULL},
+- {6, 11, 0x1, 0ULL},
+- {5, 8, 0x4, 0ULL},
+- {5, 14, 0x4, 0ULL},
+- {5, 6, 0x2, 0ULL},
+- {5, 5, 0x2, 0ULL},
+- {5, 4, 0x8, 0ULL},
+- {5, 7, 0x8, 0ULL},
+- {5, 9, 0x1, 0ULL},
+- {5, 11, 0x1, 0ULL},
+- {4, 8, 0x4, 0ULL},
+- {4, 14, 0x4, 0ULL},
+- {4, 6, 0x4, 0ULL},
+- {4, 5, 0x4, 0ULL},
+- {4, 1, 0x8, 0ULL},
+- {4, 7, 0x8, 0ULL},
+- {4, 9, 0x1, 0ULL},
+- {4, 11, 0x1, 0ULL},
+- {7, 8, 0x4, 0ULL},
+- {7, 14, 0x4, 0ULL},
+- {7, 6, 0x4, 0ULL},
+- {7, 5, 0x4, 0ULL},
+- {7, 4, 0x4, 0ULL},
+- {7, 7, 0x2, 0ULL},
+- {7, 9, 0x1, 0ULL},
+- {7, 11, 0x1, 0ULL},
+- {10, 8, 0x1, 0ULL},
+- {10, 14, 0x1, 0ULL},
+- {10, 6, 0x1, 0ULL},
+- {10, 5, 0x1, 0ULL},
+- {10, 4, 0x1, 0ULL},
+- {10, 7, 0x1, 0ULL},
+- {10, 9, 0x1, 0ULL},
+- {10, 11, 0x1, 0ULL},
+- {12, 8, 0x1, 0ULL},
+- {12, 14, 0x1, 0ULL},
+- {12, 6, 0x1, 0ULL},
+- {12, 5, 0x1, 0ULL},
+- {12, 4, 0x1, 0ULL},
+- {12, 7, 0x1, 0ULL},
+- {12, 9, 0x1, 0ULL},
+- {12, 11, 0x1, 0ULL},
++ {8, 8, 0x2},
++ {8, 14, 0x8},
++ {8, 6, 0x8},
++ {8, 5, 0x8},
++ {8, 4, 0x8},
++ {8, 7, 0x8},
++ {8, 9, 0x1},
++ {8, 11, 0x1},
++ {14, 8, 0x4},
++ {14, 14, 0x2},
++ {14, 6, 0x8},
++ {14, 5, 0x8},
++ {14, 4, 0x8},
++ {14, 7, 0x8},
++ {14, 9, 0x1},
++ {14, 11, 0x1},
++ {6, 8, 0x4},
++ {6, 14, 0x4},
++ {6, 6, 0x2},
++ {6, 5, 0x2},
++ {6, 4, 0x8},
++ {6, 7, 0x8},
++ {6, 9, 0x1},
++ {6, 11, 0x1},
++ {5, 8, 0x4},
++ {5, 14, 0x4},
++ {5, 6, 0x2},
++ {5, 5, 0x2},
++ {5, 4, 0x8},
++ {5, 7, 0x8},
++ {5, 9, 0x1},
++ {5, 11, 0x1},
++ {4, 8, 0x4},
++ {4, 14, 0x4},
++ {4, 6, 0x4},
++ {4, 5, 0x4},
++ {4, 1, 0x8},
++ {4, 7, 0x8},
++ {4, 9, 0x1},
++ {4, 11, 0x1},
++ {7, 8, 0x4},
++ {7, 14, 0x4},
++ {7, 6, 0x4},
++ {7, 5, 0x4},
++ {7, 4, 0x4},
++ {7, 7, 0x2},
++ {7, 9, 0x1},
++ {7, 11, 0x1},
++ {10, 8, 0x1},
++ {10, 14, 0x1},
++ {10, 6, 0x1},
++ {10, 5, 0x1},
++ {10, 4, 0x1},
++ {10, 7, 0x1},
++ {10, 9, 0x1},
++ {10, 11, 0x1},
++ {12, 8, 0x1},
++ {12, 14, 0x1},
++ {12, 6, 0x1},
++ {12, 5, 0x1},
++ {12, 4, 0x1},
++ {12, 7, 0x1},
++ {12, 9, 0x1},
++ {12, 11, 0x1},
+ };
+
+ fp_test_args_t xsadddp_tests[] = {
+- {8, 8, 0x0, 0xfff0000000000000ULL},
+- {8, 14, 0x0, 0xfff0000000000000ULL},
+- {8, 6, 0x0, 0xfff0000000000000ULL},
+- {8, 5, 0x0, 0xfff0000000000000ULL},
+- {8, 4, 0x0, 0xfff0000000000000ULL},
+- {8, 7, 0x0, 0x7ff8000000000000ULL},
+- {8, 9, 0x0, 0x7fffffffffffffffULL},
+- {8, 11, 0x0, 0x7ff8000000000000ULL},
+- {14, 8, 0x0, 0xfff0000000000000ULL},
+- {14, 14, 0x0, 0xc0e0650f5a07b353ULL},
+- {14, 6, 0x0, 0xc0d0650f5a07b353ULL},
+- {14, 5, 0x0, 0xc0d0650f5a07b353ULL},
+- {14, 4, 0x0, 0xc0d0650f5a07b353ULL},
+- {14, 7, 0x0, 0x7ff0000000000000ULL},
+- {14, 9, 0x0, 0x7fffffffffffffffULL},
+- {14, 11, 0x0, 0x7ff8000000000000ULL},
+- {6, 8, 0x0, 0xfff0000000000000ULL},
+- {6, 14, 0x0, 0xc0d0650f5a07b353ULL},
+- {6, 6, 0x0, 0x8000000000000000ULL},
+- {6, 5, 0x0, 0x0000000000000000ULL},
+- {6, 4, 0x0, 0x0123214569900000ULL},
+- {6, 7, 0x0, 0x7ff0000000000000ULL},
+- {6, 9, 0x0, 0x7fffffffffffffffULL},
+- {6, 11, 0x0, 0x7ff8000000000000ULL},
+- {5, 8, 0x0, 0xfff0000000000000ULL},
+- {5, 14, 0x0, 0xc0d0650f5a07b353ULL},
+- {5, 6, 0x0, 0x0000000000000000ULL},
+- {5, 5, 0x0, 0x0000000000000000ULL},
+- {5, 4, 0x0, 0x0123214569900000ULL},
+- {5, 7, 0x0, 0x7ff0000000000000ULL},
+- {5, 9, 0x0, 0x7fffffffffffffffULL},
+- {5, 11, 0x0, 0x7ff8000000000000ULL},
+- {4, 8, 0x0, 0xfff0000000000000ULL},
+- {4, 14, 0x0, 0xc0d0650f5a07b353ULL},
+- {4, 6, 0x0, 0x0123214569900000ULL},
+- {4, 5, 0x0, 0x0123214569900000ULL},
+- {4, 1, 0x0, 0x404f000000000000ULL},
+- {4, 7, 0x0, 0x7ff0000000000000ULL},
+- {4, 9, 0x0, 0x7fffffffffffffffULL},
+- {4, 11, 0x0, 0x7ff8000000000000ULL},
+- {7, 8, 0x0, 0x7ff8000000000000ULL},
+- {7, 14, 0x0, 0x7ff0000000000000ULL},
+- {7, 6, 0x0, 0x7ff0000000000000ULL},
+- {7, 5, 0x0, 0x7ff0000000000000ULL},
+- {7, 4, 0x0, 0x7ff0000000000000ULL},
+- {7, 7, 0x0, 0x7ff0000000000000ULL},
+- {7, 9, 0x0, 0x7fffffffffffffffULL},
+- {7, 11, 0x0, 0x7ff8000000000000ULL},
+- {10, 8, 0x0, 0xffffffffffffffffULL},
+- {10, 14, 0x0, 0xffffffffffffffffULL},
+- {10, 6, 0x0, 0xffffffffffffffffULL},
+- {10, 5, 0x0, 0xffffffffffffffffULL},
+- {10, 4, 0x0, 0xffffffffffffffffULL},
+- {10, 7, 0x0, 0xffffffffffffffffULL},
+- {10, 9, 0x0, 0xffffffffffffffffULL},
+- {10, 11, 0x0, 0xffffffffffffffffULL},
+- {12, 8, 0x0, 0xfff8000000000000ULL},
+- {12, 14, 0x0, 0xfff8000000000000ULL},
+- {12, 6, 0x0, 0xfff8000000000000ULL},
+- {12, 5, 0x0, 0xfff8000000000000ULL},
+- {12, 4, 0x0, 0xfff8000000000000ULL},
+- {12, 7, 0x0, 0xfff8000000000000ULL},
+- {12, 9, 0x0, 0xfff8000000000000ULL},
+- {12, 11, 0x0, 0xfff8000000000000ULL},
++ {8, 8, 0x0},
++ {8, 14, 0x0},
++ {8, 6, 0x0},
++ {8, 5, 0x0},
++ {8, 4, 0x0},
++ {8, 7, 0x0},
++ {8, 9, 0x0},
++ {8, 11, 0x0},
++ {14, 8, 0x0},
++ {14, 14, 0x0},
++ {14, 6, 0x0},
++ {14, 5, 0x0},
++ {14, 4, 0x0},
++ {14, 7, 0x0},
++ {14, 9, 0x0},
++ {14, 11, 0x0},
++ {6, 8, 0x0},
++ {6, 14, 0x0},
++ {6, 6, 0x0},
++ {6, 5, 0x0},
++ {6, 4, 0x0},
++ {6, 7, 0x0},
++ {6, 9, 0x0},
++ {6, 11, 0x0},
++ {5, 8, 0x0},
++ {5, 14, 0x0},
++ {5, 6, 0x0},
++ {5, 5, 0x0},
++ {5, 4, 0x0},
++ {5, 7, 0x0},
++ {5, 9, 0x0},
++ {5, 11, 0x0},
++ {4, 8, 0x0},
++ {4, 14, 0x0},
++ {4, 6, 0x0},
++ {4, 5, 0x0},
++ {4, 1, 0x0},
++ {4, 7, 0x0},
++ {4, 9, 0x0},
++ {4, 11, 0x0},
++ {7, 8, 0x0},
++ {7, 14, 0x0},
++ {7, 6, 0x0},
++ {7, 5, 0x0},
++ {7, 4, 0x0},
++ {7, 7, 0x0},
++ {7, 9, 0x0},
++ {7, 11, 0x0},
++ {10, 8, 0x0},
++ {10, 14, 0x0},
++ {10, 6, 0x0},
++ {10, 5, 0x0},
++ {10, 4, 0x0},
++ {10, 7, 0x0},
++ {10, 9, 0x0},
++ {10, 11, 0x0},
++ {12, 8, 0x0},
++ {12, 14, 0x0},
++ {12, 6, 0x0},
++ {12, 5, 0x0},
++ {12, 4, 0x0},
++ {12, 7, 0x0},
++ {12, 9, 0x0},
++ {12, 11, 0x0},
+ };
+
+ fp_test_args_t xsdivdp_tests[] = {
+- {8, 8, 0x0, 0x7ff8000000000000ULL},
+- {8, 14, 0x0, 0x7ff0000000000000ULL},
+- {8, 6, 0x0, 0x7ff0000000000000ULL},
+- {8, 5, 0x0, 0xfff0000000000000ULL},
+- {8, 4, 0x0, 0xfff0000000000000ULL},
+- {8, 7, 0x0, 0x7ff8000000000000ULL},
+- {8, 9, 0x0, 0x7fffffffffffffffULL},
+- {8, 11, 0x0, 0x7ff8000000000000ULL},
+- {14, 8, 0x0, 0x0000000000000000ULL},
+- {14, 14, 0x0, 0x3ff0000000000000ULL},
+- {14, 6, 0x0, 0x7ff0000000000000ULL},
+- {14, 5, 0x0, 0xfff0000000000000ULL},
+- {14, 4, 0x0, 0xff9b6cb57ca13c00ULL},
+- {14, 7, 0x0, 0x8000000000000000ULL},
+- {14, 9, 0x0, 0x7fffffffffffffffULL},
+- {14, 11, 0x0, 0x7ff8000000000000ULL},
+- {6, 8, 0x0, 0x0000000000000000ULL},
+- {6, 14, 0x0, 0x0000000000000000ULL},
+- {6, 6, 0x0, 0x7ff8000000000000ULL},
+- {6, 5, 0x0, 0x7ff8000000000000ULL},
+- {6, 4, 0x0, 0x8000000000000000ULL},
+- {6, 7, 0x0, 0x8000000000000000ULL},
+- {6, 9, 0x0, 0x7fffffffffffffffULL},
+- {6, 11, 0x0, 0x7ff8000000000000ULL},
+- {5, 8, 0x0, 0x8000000000000000ULL},
+- {5, 14, 0x0, 0x8000000000000000ULL},
+- {5, 6, 0x0, 0x7ff8000000000000ULL},
+- {5, 5, 0x0, 0x7ff8000000000000ULL},
+- {5, 4, 0x0, 0x0000000000000000ULL},
+- {5, 7, 0x0, 0x0000000000000000ULL},
+- {5, 9, 0x0, 0x7fffffffffffffffULL},
+- {5, 11, 0x0, 0x7ff8000000000000ULL},
+- {4, 8, 0x0, 0x8000000000000000ULL},
+- {4, 14, 0x0, 0x8042ab59d8b6ec87ULL},
+- {4, 6, 0x0, 0xfff0000000000000ULL},
+- {4, 5, 0x0, 0x7ff0000000000000ULL},
+- {4, 1, 0x0, 0x00c3bf3f64b5ad6bULL},
+- {4, 7, 0x0, 0x0000000000000000ULL},
+- {4, 9, 0x0, 0x7fffffffffffffffULL},
+- {4, 11, 0x0, 0x7ff8000000000000ULL},
+- {7, 8, 0x0, 0x7ff8000000000000ULL},
+- {7, 14, 0x0, 0xfff0000000000000ULL},
+- {7, 6, 0x0, 0xfff0000000000000ULL},
+- {7, 5, 0x0, 0x7ff0000000000000ULL},
+- {7, 4, 0x0, 0x7ff0000000000000ULL},
+- {7, 7, 0x0, 0x7ff8000000000000ULL},
+- {7, 9, 0x0, 0x7fffffffffffffffULL},
+- {7, 11, 0x0, 0x7ff8000000000000ULL},
+- {10, 8, 0x0, 0xffffffffffffffffULL},
+- {10, 14, 0x0, 0xffffffffffffffffULL},
+- {10, 6, 0x0, 0xffffffffffffffffULL},
+- {10, 5, 0x0, 0xffffffffffffffffULL},
+- {10, 4, 0x0, 0xffffffffffffffffULL},
+- {10, 7, 0x0, 0xffffffffffffffffULL},
+- {10, 9, 0x0, 0xffffffffffffffffULL},
+- {10, 11, 0x0, 0xffffffffffffffffULL},
+- {12, 8, 0x0, 0xfff8000000000000ULL},
+- {12, 14, 0x0, 0xfff8000000000000ULL},
+- {12, 6, 0x0, 0xfff8000000000000ULL},
+- {12, 5, 0x0, 0xfff8000000000000ULL},
+- {12, 4, 0x0, 0xfff8000000000000ULL},
+- {12, 7, 0x0, 0xfff8000000000000ULL},
+- {12, 9, 0x0, 0xfff8000000000000ULL},
+- {12, 11, 0x0, 0xfff8000000000000ULL},
++ {8, 8, 0x0},
++ {8, 14, 0x0},
++ {8, 6, 0x0},
++ {8, 5, 0x0},
++ {8, 4, 0x0},
++ {8, 7, 0x0},
++ {8, 9, 0x0},
++ {8, 11, 0x0},
++ {14, 8, 0x0},
++ {14, 14, 0x0},
++ {14, 6, 0x0},
++ {14, 5, 0x0},
++ {14, 4, 0x0},
++ {14, 7, 0x0},
++ {14, 9, 0x0},
++ {14, 11, 0x0},
++ {6, 8, 0x0},
++ {6, 14, 0x0},
++ {6, 6, 0x0},
++ {6, 5, 0x0},
++ {6, 4, 0x0},
++ {6, 7, 0x0},
++ {6, 9, 0x0},
++ {6, 11, 0x0},
++ {5, 8, 0x0},
++ {5, 14, 0x0},
++ {5, 6, 0x0},
++ {5, 5, 0x0},
++ {5, 4, 0x0},
++ {5, 7, 0x0},
++ {5, 9, 0x0},
++ {5, 11, 0x0},
++ {4, 8, 0x0},
++ {4, 14, 0x0},
++ {4, 6, 0x0},
++ {4, 5, 0x0},
++ {4, 1, 0x0},
++ {4, 7, 0x0},
++ {4, 9, 0x0},
++ {4, 11, 0x0},
++ {7, 8, 0x0},
++ {7, 14, 0x0},
++ {7, 6, 0x0},
++ {7, 5, 0x0},
++ {7, 4, 0x0},
++ {7, 7, 0x0},
++ {7, 9, 0x0},
++ {7, 11, 0x0},
++ {10, 8, 0x0},
++ {10, 14, 0x0},
++ {10, 6, 0x0},
++ {10, 5, 0x0},
++ {10, 4, 0x0},
++ {10, 7, 0x0},
++ {10, 9, 0x0},
++ {10, 11, 0x0},
++ {12, 8, 0x0},
++ {12, 14, 0x0},
++ {12, 6, 0x0},
++ {12, 5, 0x0},
++ {12, 4, 0x0},
++ {12, 7, 0x0},
++ {12, 9, 0x0},
++ {12, 11, 0x0},
+ };
+
+ fp_test_args_t xsmaddXdp_tests[] = {
+- {8, 8, 0x0, 0x7ff8000000000000ULL},
+- {8, 14, 0x0, 0xfff0000000000000ULL},
+- {8, 6, 0x0, 0x7ff0000000000000ULL},
+- {8, 5, 0x0, 0xfff0000000000000ULL},
+- {8, 4, 0x0, 0x7ff0000000000000ULL},
+- {8, 7, 0x0, 0x7ff8000000000000ULL},
+- {8, 9, 0x0, 0x7fffffffffffffffULL},
+- {8, 11, 0x0, 0x7ff8000000000000ULL},
+- {14, 8, 0x0, 0xfff0000000000000ULL},
+- {14, 14, 0x0, 0xc0d0650f5a07b353ULL},
+- {14, 6, 0x0, 0x41b0cc9d05eec2a7ULL},
+- {14, 5, 0x0, 0x82039a19ca8fcb5fULL},
+- {14, 4, 0x0, 0x41b0cc9d05eec2a7ULL},
+- {14, 7, 0x0, 0x7ff0000000000000ULL},
+- {14, 9, 0x0, 0x7fffffffffffffffULL},
+- {14, 11, 0x0, 0x7ff8000000000000ULL},
+- {6, 8, 0x0, 0xfff0000000000000ULL},
+- {6, 14, 0x0, 0xc0d0650f5a07b353ULL},
+- {6, 6, 0x0, 0x0000000000000000ULL},
+- {6, 5, 0x0, 0x0000000000000000ULL},
+- {6, 4, 0x0, 0x0123214569900000ULL},
+- {6, 7, 0x0, 0x7ff0000000000000ULL},
+- {6, 9, 0x0, 0x7fffffffffffffffULL},
+- {6, 11, 0x0, 0x7ff8000000000000ULL},
+- {5, 8, 0x0, 0xfff0000000000000ULL},
+- {5, 14, 0x0, 0xc0d0650f5a07b353ULL},
+- {5, 6, 0x0, 0x8000000000000000ULL},
+- {5, 5, 0x0, 0x0000000000000000ULL},
+- {5, 4, 0x0, 0x0123214569900000ULL},
+- {5, 7, 0x0, 0x7ff0000000000000ULL},
+- {5, 9, 0x0, 0x7fffffffffffffffULL},
+- {5, 11, 0x0, 0x7ff8000000000000ULL},
+- {4, 8, 0x0, 0xfff0000000000000ULL},
+- {4, 14, 0x0, 0xc0d0650f5a07b353ULL},
+- {4, 6, 0x0, 0x82039a19ca8fcb5fULL},
+- {4, 5, 0x0, 0x0000000000000000ULL},
+- {4, 1, 0x0, 0x404f000000000000ULL},
+- {4, 7, 0x0, 0x7ff0000000000000ULL},
+- {4, 9, 0x0, 0x7fffffffffffffffULL},
+- {4, 11, 0x0, 0x7ff8000000000000ULL},
+- {7, 8, 0x0, 0xfff0000000000000ULL},
+- {7, 14, 0x0, 0x7ff0000000000000ULL},
+- {7, 6, 0x0, 0xfff0000000000000ULL},
+- {7, 5, 0x0, 0x7ff0000000000000ULL},
+- {7, 4, 0x0, 0xfff0000000000000ULL},
+- {7, 7, 0x0, 0x7ff0000000000000ULL},
+- {7, 9, 0x0, 0x7fffffffffffffffULL},
+- {7, 11, 0x0, 0x7ff8000000000000ULL},
+- {10, 8, 0x0, 0xffffffffffffffffULL},
+- {10, 14, 0x0, 0xffffffffffffffffULL},
+- {10, 6, 0x0, 0xffffffffffffffffULL},
+- {10, 5, 0x0, 0xffffffffffffffffULL},
+- {10, 4, 0x0, 0xffffffffffffffffULL},
+- {10, 7, 0x0, 0xffffffffffffffffULL},
+- {10, 9, 0x0, 0xffffffffffffffffULL},
+- {10, 11, 0x0, 0xffffffffffffffffULL},
+- {12, 8, 0x0, 0xfff8000000000000ULL},
+- {12, 14, 0x0, 0xfff8000000000000ULL},
+- {12, 6, 0x0, 0xfff8000000000000ULL},
+- {12, 5, 0x0, 0xfff8000000000000ULL},
+- {12, 4, 0x0, 0xfff8000000000000ULL},
+- {12, 7, 0x0, 0xfff8000000000000ULL},
+- {12, 9, 0x0, 0xfff8000000000000ULL},
+- {12, 11, 0x0, 0xfff8000000000000ULL},
++ {8, 8, 0x0},
++ {8, 14, 0x0},
++ {8, 6, 0x0},
++ {8, 5, 0x0},
++ {8, 4, 0x0},
++ {8, 7, 0x0},
++ {8, 9, 0x0},
++ {8, 11, 0x0},
++ {14, 8, 0x0},
++ {14, 14, 0x0},
++ {14, 6, 0x0},
++ {14, 5, 0x0},
++ {14, 4, 0x0},
++ {14, 7, 0x0},
++ {14, 9, 0x0},
++ {14, 11, 0x0},
++ {6, 8, 0x0},
++ {6, 14, 0x0},
++ {6, 6, 0x0},
++ {6, 5, 0x0},
++ {6, 4, 0x0},
++ {6, 7, 0x0},
++ {6, 9, 0x0},
++ {6, 11, 0x0},
++ {5, 8, 0x0},
++ {5, 14, 0x0},
++ {5, 6, 0x0},
++ {5, 5, 0x0},
++ {5, 4, 0x0},
++ {5, 7, 0x0},
++ {5, 9, 0x0},
++ {5, 11, 0x0},
++ {4, 8, 0x0},
++ {4, 14, 0x0},
++ {4, 6, 0x0},
++ {4, 5, 0x0},
++ {4, 1, 0x0},
++ {4, 7, 0x0},
++ {4, 9, 0x0},
++ {4, 11, 0x0},
++ {7, 8, 0x0},
++ {7, 14, 0x0},
++ {7, 6, 0x0},
++ {7, 5, 0x0},
++ {7, 4, 0x0},
++ {7, 7, 0x0},
++ {7, 9, 0x0},
++ {7, 11, 0x0},
++ {10, 8, 0x0},
++ {10, 14, 0x0},
++ {10, 6, 0x0},
++ {10, 5, 0x0},
++ {10, 4, 0x0},
++ {10, 7, 0x0},
++ {10, 9, 0x0},
++ {10, 11, 0x0},
++ {12, 8, 0x0},
++ {12, 14, 0x0},
++ {12, 6, 0x0},
++ {12, 5, 0x0},
++ {12, 4, 0x0},
++ {12, 7, 0x0},
++ {12, 9, 0x0},
++ {12, 11, 0x0},
+ };
+
+ fp_test_args_t xsmsubXdp_tests[] = {
+- {8, 8, 0x0, 0x7ff0000000000000ULL},
+- {8, 14, 0x0, 0xfff0000000000000ULL},
+- {8, 6, 0x0, 0x7ff0000000000000ULL},
+- {8, 5, 0x0, 0xfff0000000000000ULL},
+- {8, 4, 0x0, 0x7ff0000000000000ULL},
+- {8, 7, 0x0, 0xfff0000000000000ULL},
+- {8, 9, 0x0, 0x7fffffffffffffffULL},
+- {8, 11, 0x0, 0x7ff8000000000000ULL},
+- {14, 8, 0x0, 0x7ff0000000000000ULL},
+- {14, 14, 0x0, 0x40d0650f5a07b353ULL},
+- {14, 6, 0x0, 0x41b0cc9d05eec2a7ULL},
+- {14, 5, 0x0, 0x82039a19ca8fcb5fULL},
+- {14, 4, 0x0, 0x41b0cc9d05eec2a7ULL},
+- {14, 7, 0x0, 0xfff0000000000000ULL},
+- {14, 9, 0x0, 0x7fffffffffffffffULL},
+- {14, 11, 0x0, 0x7ff8000000000000ULL},
+- {6, 8, 0x0, 0x7ff0000000000000ULL},
+- {6, 14, 0x0, 0x40d0650f5a07b353ULL},
+- {6, 6, 0x0, 0x0000000000000000ULL},
+- {6, 5, 0x0, 0x8000000000000000ULL},
+- {6, 4, 0x0, 0x8123214569900000ULL},
+- {6, 7, 0x0, 0xfff0000000000000ULL},
+- {6, 9, 0x0, 0x7fffffffffffffffULL},
+- {6, 11, 0x0, 0x7ff8000000000000ULL},
+- {5, 8, 0x0, 0x7ff0000000000000ULL},
+- {5, 14, 0x0, 0x40d0650f5a07b353ULL},
+- {5, 6, 0x0, 0x0000000000000000ULL},
+- {5, 5, 0x0, 0x0000000000000000ULL},
+- {5, 4, 0x0, 0x8123214569900000ULL},
+- {5, 7, 0x0, 0xfff0000000000000ULL},
+- {5, 9, 0x0, 0x7fffffffffffffffULL},
+- {5, 11, 0x0, 0x7ff8000000000000ULL},
+- {4, 8, 0x0, 0x7ff0000000000000ULL},
+- {4, 14, 0x0, 0x40d0650f5a07b353ULL},
+- {4, 6, 0x0, 0x82039a19ca8fcb5fULL},
+- {4, 5, 0x0, 0x0000000000000000ULL},
+- {4, 1, 0x0, 0xc04f000000000000ULL},
+- {4, 7, 0x0, 0xfff0000000000000ULL},
+- {4, 9, 0x0, 0x7fffffffffffffffULL},
+- {4, 11, 0x0, 0x7ff8000000000000ULL},
+- {7, 8, 0x0, 0x7ff8000000000000ULL},
+- {7, 14, 0x0, 0x7ff0000000000000ULL},
+- {7, 6, 0x0, 0xfff0000000000000ULL},
+- {7, 5, 0x0, 0x7ff0000000000000ULL},
+- {7, 4, 0x0, 0xfff0000000000000ULL},
+- {7, 7, 0x0, 0x7ff8000000000000ULL},
+- {7, 9, 0x0, 0x7fffffffffffffffULL},
+- {7, 11, 0x0, 0x7ff8000000000000ULL},
+- {10, 8, 0x0, 0xffffffffffffffffULL},
+- {10, 14, 0x0, 0xffffffffffffffffULL},
+- {10, 6, 0x0, 0xffffffffffffffffULL},
+- {10, 5, 0x0, 0xffffffffffffffffULL},
+- {10, 4, 0x0, 0xffffffffffffffffULL},
+- {10, 7, 0x0, 0xffffffffffffffffULL},
+- {10, 9, 0x0, 0xffffffffffffffffULL},
+- {10, 11, 0x0, 0xffffffffffffffffULL},
+- {12, 8, 0x0, 0xfff8000000000000ULL},
+- {12, 14, 0x0, 0xfff8000000000000ULL},
+- {12, 6, 0x0, 0xfff8000000000000ULL},
+- {12, 5, 0x0, 0xfff8000000000000ULL},
+- {12, 4, 0x0, 0xfff8000000000000ULL},
+- {12, 7, 0x0, 0xfff8000000000000ULL},
+- {12, 9, 0x0, 0xfff8000000000000ULL},
+- {12, 11, 0x0, 0xfff8000000000000ULL},
++ {8, 8, 0x0},
++ {8, 14, 0x0},
++ {8, 6, 0x0},
++ {8, 5, 0x0},
++ {8, 4, 0x0},
++ {8, 7, 0x0},
++ {8, 9, 0x0},
++ {8, 11, 0x0},
++ {14, 8, 0x0},
++ {14, 14, 0x0},
++ {14, 6, 0x0},
++ {14, 5, 0x0},
++ {14, 4, 0x0},
++ {14, 7, 0x0},
++ {14, 9, 0x0},
++ {14, 11, 0x0},
++ {6, 8, 0x0},
++ {6, 14, 0x0},
++ {6, 6, 0x0},
++ {6, 5, 0x0},
++ {6, 4, 0x0},
++ {6, 7, 0x0},
++ {6, 9, 0x0},
++ {6, 11, 0x0},
++ {5, 8, 0x0},
++ {5, 14, 0x0},
++ {5, 6, 0x0},
++ {5, 5, 0x0},
++ {5, 4, 0x0},
++ {5, 7, 0x0},
++ {5, 9, 0x0},
++ {5, 11, 0x0},
++ {4, 8, 0x0},
++ {4, 14, 0x0},
++ {4, 6, 0x0},
++ {4, 5, 0x0},
++ {4, 1, 0x0},
++ {4, 7, 0x0},
++ {4, 9, 0x0},
++ {4, 11, 0x0},
++ {7, 8, 0x0},
++ {7, 14, 0x0},
++ {7, 6, 0x0},
++ {7, 5, 0x0},
++ {7, 4, 0x0},
++ {7, 7, 0x0},
++ {7, 9, 0x0},
++ {7, 11, 0x0},
++ {10, 8, 0x0},
++ {10, 14, 0x0},
++ {10, 6, 0x0},
++ {10, 5, 0x0},
++ {10, 4, 0x0},
++ {10, 7, 0x0},
++ {10, 9, 0x0},
++ {10, 11, 0x0},
++ {12, 8, 0x0},
++ {12, 14, 0x0},
++ {12, 6, 0x0},
++ {12, 5, 0x0},
++ {12, 4, 0x0},
++ {12, 7, 0x0},
++ {12, 9, 0x0},
++ {12, 11, 0x0},
+ };
+
+ fp_test_args_t xsnmaddXdp_tests[] = {
+- {8, 8, 0x0, 0x7ff8000000000000ULL},
+- {8, 14, 0x0, 0x7ff0000000000000ULL},
+- {8, 6, 0x0, 0xfff0000000000000ULL},
+- {8, 5, 0x0, 0x7ff0000000000000ULL},
+- {8, 4, 0x0, 0xfff0000000000000ULL},
+- {8, 7, 0x0, 0x7ff8000000000000ULL},
+- {8, 9, 0x0, 0x7fffffffffffffffULL},
+- {8, 11, 0x0, 0x7ff8000000000000ULL},
+- {14, 8, 0x0, 0x7ff0000000000000ULL},
+- {14, 14, 0x0, 0x40d0650f5a07b353ULL},
+- {14, 6, 0x0, 0xc1b0cc9d05eec2a7ULL},
+- {14, 5, 0x0, 0x02039a19ca8fcb5fULL},
+- {14, 4, 0x0, 0xc1b0cc9d05eec2a7ULL},
+- {14, 7, 0x0, 0xfff0000000000000ULL},
+- {14, 9, 0x0, 0x7fffffffffffffffULL},
+- {14, 11, 0x0, 0x7ff8000000000000ULL},
+- {6, 8, 0x0, 0x7ff0000000000000ULL},
+- {6, 14, 0x0, 0x40d0650f5a07b353ULL},
+- {6, 6, 0x0, 0x8000000000000000ULL},
+- {6, 5, 0x0, 0x8000000000000000ULL},
+- {6, 4, 0x0, 0x8123214569900000ULL},
+- {6, 7, 0x0, 0xfff0000000000000ULL},
+- {6, 9, 0x0, 0x7fffffffffffffffULL},
+- {6, 11, 0x0, 0x7ff8000000000000ULL},
+- {5, 8, 0x0, 0x7ff0000000000000ULL},
+- {5, 14, 0x0, 0x40d0650f5a07b353ULL},
+- {5, 6, 0x0, 0x0000000000000000ULL},
+- {5, 5, 0x0, 0x8000000000000000ULL},
+- {5, 4, 0x0, 0x8123214569900000ULL},
+- {5, 7, 0x0, 0xfff0000000000000ULL},
+- {5, 9, 0x0, 0x7fffffffffffffffULL},
+- {5, 11, 0x0, 0x7ff8000000000000ULL},
+- {4, 8, 0x0, 0x7ff0000000000000ULL},
+- {4, 14, 0x0, 0x40d0650f5a07b353ULL},
+- {4, 6, 0x0, 0x02039a19ca8fcb5fULL},
+- {4, 5, 0x0, 0x8000000000000000ULL},
+- {4, 1, 0x0, 0xc04f000000000000ULL},
+- {4, 7, 0x0, 0xfff0000000000000ULL},
+- {4, 9, 0x0, 0x7fffffffffffffffULL},
+- {4, 11, 0x0, 0x7ff8000000000000ULL},
+- {7, 8, 0x0, 0x7ff0000000000000ULL},
+- {7, 14, 0x0, 0xfff0000000000000ULL},
+- {7, 6, 0x0, 0x7ff0000000000000ULL},
+- {7, 5, 0x0, 0xfff0000000000000ULL},
+- {7, 4, 0x0, 0x7ff0000000000000ULL},
+- {7, 7, 0x0, 0xfff0000000000000ULL},
+- {7, 9, 0x0, 0x7fffffffffffffffULL},
+- {7, 11, 0x0, 0x7ff8000000000000ULL},
+- {10, 8, 0x0, 0xffffffffffffffffULL},
+- {10, 14, 0x0, 0xffffffffffffffffULL},
+- {10, 6, 0x0, 0xffffffffffffffffULL},
+- {10, 5, 0x0, 0xffffffffffffffffULL},
+- {10, 4, 0x0, 0xffffffffffffffffULL},
+- {10, 7, 0x0, 0xffffffffffffffffULL},
+- {10, 9, 0x0, 0xffffffffffffffffULL},
+- {10, 11, 0x0, 0xffffffffffffffffULL},
+- {12, 8, 0x0, 0xfff8000000000000ULL},
+- {12, 14, 0x0, 0xfff8000000000000ULL},
+- {12, 6, 0x0, 0xfff8000000000000ULL},
+- {12, 5, 0x0, 0xfff8000000000000ULL},
+- {12, 4, 0x0, 0xfff8000000000000ULL},
+- {12, 7, 0x0, 0xfff8000000000000ULL},
+- {12, 9, 0x0, 0xfff8000000000000ULL},
+- {12, 11, 0x0, 0xfff8000000000000ULL},
++ {8, 8, 0x0},
++ {8, 14, 0x0},
++ {8, 6, 0x0},
++ {8, 5, 0x0},
++ {8, 4, 0x0},
++ {8, 7, 0x0},
++ {8, 9, 0x0},
++ {8, 11, 0x0},
++ {14, 8, 0x0},
++ {14, 14, 0x0},
++ {14, 6, 0x0},
++ {14, 5, 0x0},
++ {14, 4, 0x0},
++ {14, 7, 0x0},
++ {14, 9, 0x0},
++ {14, 11, 0x0},
++ {6, 8, 0x0},
++ {6, 14, 0x0},
++ {6, 6, 0x0},
++ {6, 5, 0x0},
++ {6, 4, 0x0},
++ {6, 7, 0x0},
++ {6, 9, 0x0},
++ {6, 11, 0x0},
++ {5, 8, 0x0},
++ {5, 14, 0x0},
++ {5, 6, 0x0},
++ {5, 5, 0x0},
++ {5, 4, 0x0},
++ {5, 7, 0x0},
++ {5, 9, 0x0},
++ {5, 11, 0x0},
++ {4, 8, 0x0},
++ {4, 14, 0x0},
++ {4, 6, 0x0},
++ {4, 5, 0x0},
++ {4, 1, 0x0},
++ {4, 7, 0x0},
++ {4, 9, 0x0},
++ {4, 11, 0x0},
++ {7, 8, 0x0},
++ {7, 14, 0x0},
++ {7, 6, 0x0},
++ {7, 5, 0x0},
++ {7, 4, 0x0},
++ {7, 7, 0x0},
++ {7, 9, 0x0},
++ {7, 11, 0x0},
++ {10, 8, 0x0},
++ {10, 14, 0x0},
++ {10, 6, 0x0},
++ {10, 5, 0x0},
++ {10, 4, 0x0},
++ {10, 7, 0x0},
++ {10, 9, 0x0},
++ {10, 11, 0x0},
++ {12, 8, 0x0},
++ {12, 14, 0x0},
++ {12, 6, 0x0},
++ {12, 5, 0x0},
++ {12, 4, 0x0},
++ {12, 7, 0x0},
++ {12, 9, 0x0},
++ {12, 11, 0x0},
+ };
+
+ fp_test_args_t xsmuldp_tests[] = {
+- {8, 8, 0x0, 0x7ff0000000000000ULL},
+- {8, 14, 0x0, 0x7ff0000000000000ULL},
+- {8, 6, 0x0, 0x7ff8000000000000ULL},
+- {8, 5, 0x0, 0x7ff8000000000000ULL},
+- {8, 4, 0x0, 0xfff0000000000000ULL},
+- {8, 7, 0x0, 0xfff0000000000000ULL},
+- {8, 9, 0x0, 0x7fffffffffffffffULL},
+- {8, 11, 0x0, 0x7ff8000000000000ULL},
+- {14, 8, 0x0, 0x7ff0000000000000ULL},
+- {14, 14, 0x0, 0x41b0cc9d05eec2a7ULL},
+- {14, 6, 0x0, 0x0000000000000000ULL},
+- {14, 5, 0x0, 0x8000000000000000ULL},
+- {14, 4, 0x0, 0x82039a19ca8fcb5fULL},
+- {14, 7, 0x0, 0xfff0000000000000ULL},
+- {14, 9, 0x0, 0x7fffffffffffffffULL},
+- {14, 11, 0x0, 0x7ff8000000000000ULL},
+- {6, 8, 0x0, 0x7ff8000000000000ULL},
+- {6, 14, 0x0, 0x0000000000000000ULL},
+- {6, 6, 0x0, 0x0000000000000000ULL},
+- {6, 5, 0x0, 0x8000000000000000ULL},
+- {6, 4, 0x0, 0x8000000000000000ULL},
+- {6, 7, 0x0, 0x7ff8000000000000ULL},
+- {6, 9, 0x0, 0x7fffffffffffffffULL},
+- {6, 11, 0x0, 0x7ff8000000000000ULL},
+- {5, 8, 0x0, 0x7ff8000000000000ULL},
+- {5, 14, 0x0, 0x8000000000000000ULL},
+- {5, 6, 0x0, 0x8000000000000000ULL},
+- {5, 5, 0x0, 0x0000000000000000ULL},
+- {5, 4, 0x0, 0x0000000000000000ULL},
+- {5, 7, 0x0, 0x7ff8000000000000ULL},
+- {5, 9, 0x0, 0x7fffffffffffffffULL},
+- {5, 11, 0x0, 0x7ff8000000000000ULL},
+- {4, 8, 0x0, 0xfff0000000000000ULL},
+- {4, 14, 0x0, 0x82039a19ca8fcb5fULL},
+- {4, 6, 0x0, 0x8000000000000000ULL},
+- {4, 5, 0x0, 0x0000000000000000ULL},
+- {4, 1, 0x0, 0x0182883b3e438000ULL},
+- {4, 7, 0x0, 0x7ff0000000000000ULL},
+- {4, 9, 0x0, 0x7fffffffffffffffULL},
+- {4, 11, 0x0, 0x7ff8000000000000ULL},
+- {7, 8, 0x0, 0xfff0000000000000ULL},
+- {7, 14, 0x0, 0xfff0000000000000ULL},
+- {7, 6, 0x0, 0x7ff8000000000000ULL},
+- {7, 5, 0x0, 0x7ff8000000000000ULL},
+- {7, 4, 0x0, 0x7ff0000000000000ULL},
+- {7, 7, 0x0, 0x7ff0000000000000ULL},
+- {7, 9, 0x0, 0x7fffffffffffffffULL},
+- {7, 11, 0x0, 0x7ff8000000000000ULL},
+- {10, 8, 0x0, 0xffffffffffffffffULL},
+- {10, 14, 0x0, 0xffffffffffffffffULL},
+- {10, 6, 0x0, 0xffffffffffffffffULL},
+- {10, 5, 0x0, 0xffffffffffffffffULL},
+- {10, 4, 0x0, 0xffffffffffffffffULL},
+- {10, 7, 0x0, 0xffffffffffffffffULL},
+- {10, 9, 0x0, 0xffffffffffffffffULL},
+- {10, 11, 0x0, 0xffffffffffffffffULL},
+- {12, 8, 0x0, 0xfff8000000000000ULL},
+- {12, 14, 0x0, 0xfff8000000000000ULL},
+- {12, 6, 0x0, 0xfff8000000000000ULL},
+- {12, 5, 0x0, 0xfff8000000000000ULL},
+- {12, 4, 0x0, 0xfff8000000000000ULL},
+- {12, 7, 0x0, 0xfff8000000000000ULL},
+- {12, 9, 0x0, 0xfff8000000000000ULL},
+- {12, 11, 0x0, 0xfff8000000000000ULL},
++ {8, 8, 0x0},
++ {8, 14, 0x0},
++ {8, 6, 0x0},
++ {8, 5, 0x0},
++ {8, 4, 0x0},
++ {8, 7, 0x0},
++ {8, 9, 0x0},
++ {8, 11, 0x0},
++ {14, 8, 0x0},
++ {14, 14, 0x0},
++ {14, 6, 0x0},
++ {14, 5, 0x0},
++ {14, 4, 0x0},
++ {14, 7, 0x0},
++ {14, 9, 0x0},
++ {14, 11, 0x0},
++ {6, 8, 0x0},
++ {6, 14, 0x0},
++ {6, 6, 0x0},
++ {6, 5, 0x0},
++ {6, 4, 0x0},
++ {6, 7, 0x0},
++ {6, 9, 0x0},
++ {6, 11, 0x0},
++ {5, 8, 0x0},
++ {5, 14, 0x0},
++ {5, 6, 0x0},
++ {5, 5, 0x0},
++ {5, 4, 0x0},
++ {5, 7, 0x0},
++ {5, 9, 0x0},
++ {5, 11, 0x0},
++ {4, 8, 0x0},
++ {4, 14, 0x0},
++ {4, 6, 0x0},
++ {4, 5, 0x0},
++ {4, 1, 0x0},
++ {4, 7, 0x0},
++ {4, 9, 0x0},
++ {4, 11, 0x0},
++ {7, 8, 0x0},
++ {7, 14, 0x0},
++ {7, 6, 0x0},
++ {7, 5, 0x0},
++ {7, 4, 0x0},
++ {7, 7, 0x0},
++ {7, 9, 0x0},
++ {7, 11, 0x0},
++ {10, 8, 0x0},
++ {10, 14, 0x0},
++ {10, 6, 0x0},
++ {10, 5, 0x0},
++ {10, 4, 0x0},
++ {10, 7, 0x0},
++ {10, 9, 0x0},
++ {10, 11, 0x0},
++ {12, 8, 0x0},
++ {12, 14, 0x0},
++ {12, 6, 0x0},
++ {12, 5, 0x0},
++ {12, 4, 0x0},
++ {12, 7, 0x0},
++ {12, 9, 0x0},
++ {12, 11, 0x0},
+ };
+
+ fp_test_args_t xssubdp_tests[] = {
+- {8, 8, 0x0, 0x7ff8000000000000ULL},
+- {8, 14, 0x0, 0xfff0000000000000ULL},
+- {8, 6, 0x0, 0xfff0000000000000ULL},
+- {8, 5, 0x0, 0xfff0000000000000ULL},
+- {8, 4, 0x0, 0xfff0000000000000ULL},
+- {8, 7, 0x0, 0xfff0000000000000ULL},
+- {8, 9, 0x0, 0x7fffffffffffffffULL},
+- {8, 11, 0x0, 0x7ff8000000000000ULL},
+- {14, 8, 0x0, 0x7ff0000000000000ULL},
+- {14, 14, 0x0, 0x0000000000000000ULL},
+- {14, 6, 0x0, 0xc0d0650f5a07b353ULL},
+- {14, 5, 0x0, 0xc0d0650f5a07b353ULL},
+- {14, 4, 0x0, 0xc0d0650f5a07b353ULL},
+- {14, 7, 0x0, 0xfff0000000000000ULL},
+- {14, 9, 0x0, 0x7fffffffffffffffULL},
+- {14, 11, 0x0, 0x7ff8000000000000ULL},
+- {6, 8, 0x0, 0x7ff0000000000000ULL},
+- {6, 14, 0x0, 0x40d0650f5a07b353ULL},
+- {6, 6, 0x0, 0x0000000000000000ULL},
+- {6, 5, 0x0, 0x8000000000000000ULL},
+- {6, 4, 0x0, 0x8123214569900000ULL},
+- {6, 7, 0x0, 0xfff0000000000000ULL},
+- {6, 9, 0x0, 0x7fffffffffffffffULL},
+- {6, 11, 0x0, 0x7ff8000000000000ULL},
+- {5, 8, 0x0, 0x7ff0000000000000ULL},
+- {5, 14, 0x0, 0x40d0650f5a07b353ULL},
+- {5, 6, 0x0, 0x0000000000000000ULL},
+- {5, 5, 0x0, 0x0000000000000000ULL},
+- {5, 4, 0x0, 0x8123214569900000ULL},
+- {5, 7, 0x0, 0xfff0000000000000ULL},
+- {5, 9, 0x0, 0x7fffffffffffffffULL},
+- {5, 11, 0x0, 0x7ff8000000000000ULL},
+- {4, 8, 0x0, 0x7ff0000000000000ULL},
+- {4, 14, 0x0, 0x40d0650f5a07b353ULL},
+- {4, 6, 0x0, 0x0123214569900000ULL},
+- {4, 5, 0x0, 0x0123214569900000ULL},
+- {4, 1, 0x0, 0xc04f000000000000ULL},
+- {4, 7, 0x0, 0xfff0000000000000ULL},
+- {4, 9, 0x0, 0x7fffffffffffffffULL},
+- {4, 11, 0x0, 0x7ff8000000000000ULL},
+- {7, 8, 0x0, 0x7ff0000000000000ULL},
+- {7, 14, 0x0, 0x7ff0000000000000ULL},
+- {7, 6, 0x0, 0x7ff0000000000000ULL},
+- {7, 5, 0x0, 0x7ff0000000000000ULL},
+- {7, 4, 0x0, 0x7ff0000000000000ULL},
+- {7, 7, 0x0, 0x7ff8000000000000ULL},
+- {7, 9, 0x0, 0x7fffffffffffffffULL},
+- {7, 11, 0x0, 0x7ff8000000000000ULL},
+- {10, 8, 0x0, 0xffffffffffffffffULL},
+- {10, 14, 0x0, 0xffffffffffffffffULL},
+- {10, 6, 0x0, 0xffffffffffffffffULL},
+- {10, 5, 0x0, 0xffffffffffffffffULL},
+- {10, 4, 0x0, 0xffffffffffffffffULL},
+- {10, 7, 0x0, 0xffffffffffffffffULL},
+- {10, 9, 0x0, 0xffffffffffffffffULL},
+- {10, 11, 0x0, 0xffffffffffffffffULL},
+- {12, 8, 0x0, 0xfff8000000000000ULL},
+- {12, 14, 0x0, 0xfff8000000000000ULL},
+- {12, 6, 0x0, 0xfff8000000000000ULL},
+- {12, 5, 0x0, 0xfff8000000000000ULL},
+- {12, 4, 0x0, 0xfff8000000000000ULL},
+- {12, 7, 0x0, 0xfff8000000000000ULL},
+- {12, 9, 0x0, 0xfff8000000000000ULL},
+- {12, 11, 0x0, 0xfff8000000000000ULL},
++ {8, 8, 0x0},
++ {8, 14, 0x0},
++ {8, 6, 0x0},
++ {8, 5, 0x0},
++ {8, 4, 0x0},
++ {8, 7, 0x0},
++ {8, 9, 0x0},
++ {8, 11, 0x0},
++ {14, 8, 0x0},
++ {14, 14, 0x0},
++ {14, 6, 0x0},
++ {14, 5, 0x0},
++ {14, 4, 0x0},
++ {14, 7, 0x0},
++ {14, 9, 0x0},
++ {14, 11, 0x0},
++ {6, 8, 0x0},
++ {6, 14, 0x0},
++ {6, 6, 0x0},
++ {6, 5, 0x0},
++ {6, 4, 0x0},
++ {6, 7, 0x0},
++ {6, 9, 0x0},
++ {6, 11, 0x0},
++ {5, 8, 0x0},
++ {5, 14, 0x0},
++ {5, 6, 0x0},
++ {5, 5, 0x0},
++ {5, 4, 0x0},
++ {5, 7, 0x0},
++ {5, 9, 0x0},
++ {5, 11, 0x0},
++ {4, 8, 0x0},
++ {4, 14, 0x0},
++ {4, 6, 0x0},
++ {4, 5, 0x0},
++ {4, 1, 0x0},
++ {4, 7, 0x0},
++ {4, 9, 0x0},
++ {4, 11, 0x0},
++ {7, 8, 0x0},
++ {7, 14, 0x0},
++ {7, 6, 0x0},
++ {7, 5, 0x0},
++ {7, 4, 0x0},
++ {7, 7, 0x0},
++ {7, 9, 0x0},
++ {7, 11, 0x0},
++ {10, 8, 0x0},
++ {10, 14, 0x0},
++ {10, 6, 0x0},
++ {10, 5, 0x0},
++ {10, 4, 0x0},
++ {10, 7, 0x0},
++ {10, 9, 0x0},
++ {10, 11, 0x0},
++ {12, 8, 0x0},
++ {12, 14, 0x0},
++ {12, 6, 0x0},
++ {12, 5, 0x0},
++ {12, 4, 0x0},
++ {12, 7, 0x0},
++ {12, 9, 0x0},
++ {12, 11, 0x0},
+ };
+
+
+@@ -1091,7 +1036,6 @@ struct xs_conv_test
+ {
+ test_func_t test_func;
+ const char *name;
+- unsigned long long * results;
+ int num_tests;
+ };
+
+@@ -1130,8 +1074,6 @@ struct vsx_move_test
+ {
+ test_func_t test_func;
+ const char *name;
+- int xa_idx, xb_idx;
+- unsigned long long expected_result;
+ };
+
+ struct vsx_permute_test
+@@ -1140,7 +1082,6 @@ struct vsx_permute_test
+ const char *name;
+ unsigned int xa[4];
+ unsigned int xb[4];
+- unsigned int expected_output[4];
+ };
+
+ static vector unsigned int vec_out, vec_inA, vec_inB;
+@@ -1402,13 +1343,13 @@ static logic_test_t logic_tests[] = { { &test_xxlxor, "xxlxor", VSX_XOR },
+ { &test_xxlnor, "xxlnor", VSX_NOR },
+ { &test_xxland, "xxland", VSX_AND },
+ { &test_xxlandc, "xxlandc", VSX_ANDC },
+- { NULL, NULL}};
++ { NULL, NULL, 0}};
+
+-static move_test_t move_tests[] = { { &test_xsabsdp, "xsabsdp", 0, 4, 0x0899aabb91929394ULL },
+- { &test_xscpsgndp, "xscpsgndp", 4, 0, 0x8123456789abcdefULL },
+- { &test_xsnabsdp, "xsnabsdp", 7, 3, 0xc45566778899aabbULL, },
+- { &test_xsnegdp, "xsnegdp", 0, 7, 0x31b2b3b4c1c2c3c4ULL, },
+- { NULL, NULL, 0, 0, 0 }
++static move_test_t move_tests[] = { { &test_xsabsdp, "xsabsdp" },
++ { &test_xscpsgndp, "xscpsgndp" },
++ { &test_xsnabsdp, "xsnabsdp" },
++ { &test_xsnegdp, "xsnegdp" },
++ { NULL, NULL }
+
+ };
+
+@@ -1417,62 +1358,50 @@ static permute_test_t permute_tests[] =
+ { &test_xxmrghw, "xxmrghw",
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
+ { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
+- { 0x11111111, 0x55555555, 0x22222222, 0x66666666 } /* XT expected output */
+ },
+ { &test_xxmrghw, "xxmrghw",
+ { 0x00112233, 0x44556677, 0x8899aabb, 0xccddeeff }, /* XA input */
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XB input */
+- { 0x00112233, 0x11111111, 0x44556677, 0x22222222 } /* XT expected output */
+ },
+ { &test_xxmrglw, "xxmrglw",
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
+ { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
+- { 0x33333333, 0x77777777, 0x44444444, 0x88888888 } /* XT expected output */
+ },
+ { &test_xxmrglw, "xxmrglw",
+ { 0x00112233, 0x44556677, 0x8899aabb, 0xccddeeff}, /* XA input */
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444}, /* XB input */
+- { 0x8899aabb, 0x33333333, 0xccddeeff, 0x44444444} /* XT expected output */
+ },
+ { &test_xxpermdi_00, "xxpermdi DM=00",
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
+ { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
+- { 0x11111111, 0x22222222, 0x55555555, 0x66666666 } /* XT expected output */
+ },
+ { &test_xxpermdi_01, "xxpermdi DM=01",
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
+ { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
+- { 0x11111111, 0x22222222, 0x77777777, 0x88888888 } /* XT expected output */
+ },
+ { &test_xxpermdi_10, "xxpermdi DM=10",
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
+ { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
+- { 0x33333333, 0x44444444, 0x55555555, 0x66666666 } /* XT expected output */
+ },
+ { &test_xxpermdi_11, "xxpermdi DM=11",
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
+ { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
+- { 0x33333333, 0x44444444, 0x77777777, 0x88888888 } /* XT expected output */
+ },
+ { &test_xxsldwi_0, "xxsldwi SHW=0",
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
+ { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
+- { 0x11111111, 0x22222222, 0x33333333, 0x44444444 } /* XT expected output */
+ },
+ { &test_xxsldwi_1, "xxsldwi SHW=1",
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
+ { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
+- { 0x22222222, 0x33333333, 0x44444444, 0x55555555 } /* XT expected output */
+ },
+ { &test_xxsldwi_2, "xxsldwi SHW=2",
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
+ { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
+- { 0x33333333, 0x44444444, 0x55555555, 0x66666666 } /* XT expected output */
+ },
+ { &test_xxsldwi_3, "xxsldwi SHW=3",
+ { 0x11111111, 0x22222222, 0x33333333, 0x44444444 }, /* XA input */
+ { 0x55555555, 0x66666666, 0x77777777, 0x88888888 }, /* XB input */
+- { 0x44444444, 0x55555555, 0x66666666, 0x77777777 } /* XT expected output */
+ },
+ { NULL, NULL }
+ };
+@@ -1497,16 +1426,16 @@ static vx_fp_test_t vx_fp_tests[] = {
+ };
+
+ static xs_conv_test_t xs_conv_tests[] = {
+- { &test_xscvdpsxds, "xscvdpsxds", xscvdpsxds_results, 15},
+- { &test_xscvsxddp, "xscvsxddp", xscvsxddp_results, 15},
+- { &test_xscvuxddp, "xscvuxddp", xscvuxddp_results, 15},
+- { NULL, NULL, NULL, 0}
++ { &test_xscvdpsxds, "xscvdpsxds", 15},
++ { &test_xscvsxddp, "xscvsxddp", 15},
++ { &test_xscvuxddp, "xscvuxddp", 15},
++ { NULL, NULL, 0}
+ };
+
+ #ifdef __powerpc64__
+ static void test_ldbrx(void)
+ {
+- int i, equality;
++ int i;
+ HWord_t reg_out;
+ unsigned char * byteIn, * byteOut;
+ r14 = (HWord_t)viargs;
+@@ -1515,13 +1444,12 @@ static void test_ldbrx(void)
+ int j, k;
+ reg_out = 0;
+ r15 = i * 4;
+- equality = 1;
+ __asm__ __volatile__ ("ldbrx %0, %1, %2" : "=r" (reg_out): "b" (r14),"r" (r15));
+ byteIn = ((unsigned char *)(r14 + r15));
+ byteOut = (unsigned char *)®_out;
+
+ printf("ldbrx:");
+- for (k = 0; k < 7; k++) {
++ for (k = 0; k < 8; k++) {
+ printf( " %02x", (byteIn[k]));
+ }
+ printf(" (reverse) =>");
+@@ -1529,13 +1457,6 @@ static void test_ldbrx(void)
+ printf( " %02x", (byteOut[j]));
+ }
+ printf("\n");
+- for (j = 0, k = 7; j < 8; j++, k--) {
+- equality &= (byteIn[k] == byteOut[j]);
+- }
+- if (!equality) {
+- printf("FAILED: load with byte reversal is incorrect\n");
+- errors++;
+- }
+ }
+ printf( "\n" );
+ }
+@@ -1545,18 +1466,9 @@ test_popcntd(void)
+ {
+ uint64_t res;
+ unsigned long long src = 0x9182736405504536ULL;
+- int i, answer = 0;
+ r14 = src;
+ __asm__ __volatile__ ("popcntd %0, %1" : "=r" (res): "r" (r14));
+- for (i = 0; i < 64; i++) {
+- answer += (r14 & 1ULL);
+- r14 = r14 >> 1;
+- }
+ printf("popcntd: 0x%llx => %d\n", src, (int)res);
+- if (res!= answer) {
+- printf("Error: unexpected result from popcntd\n");
+- errors++;
+- }
+ printf( "\n" );
+ }
+ #endif
+@@ -1576,10 +1488,6 @@ test_lfiwzx(void)
+ src = ((unsigned int *)(r14 + r15));
+ printf("lfiwzx: %u => %llu.00\n", *src, (unsigned long long)reg_out);
+
+- if (reg_out > 0xFFFFFFFFULL || *src != (unsigned int)reg_out) {
+- printf("FAILED: integer load to FP register is incorrect\n");
+- errors++;
+- }
+ }
+ printf( "\n" );
+ }
+@@ -1635,6 +1543,9 @@ static void test_vx_fp_ops(void)
+ again:
+ for (i = 0; i < test_group.num_tests; i++) {
+ unsigned int * inA, * inB, * pv;
++ double * dpA = (double *)&vec_inA;
++ double * dpB = (double *)&vec_inB;
++ double * dpT = (double *)&vec_out;
+
+ fp_test_args_t aTest = test_group.targs[i];
+ inA = (unsigned int *)&spec_fargs[aTest.fra_idx];
+@@ -1642,8 +1553,15 @@ again:
+ frap = (unsigned long long *)&spec_fargs[aTest.fra_idx];
+ frbp = (unsigned long long *)&spec_fargs[aTest.frb_idx];
+ // Only need to copy one doubleword into each vector's element 0
+- memcpy(&vec_inA, inA, 8);
+- memcpy(&vec_inB, inB, 8);
++ if (isLE) {
++ // With LE, vector element 0 is the second doubleword from the left
++ memset(dpA, 0, 8);
++ memset(dpB, 0, 8);
++ dpA++;
++ dpB++;
++ }
++ memcpy(dpA, inA, 8);
++ memcpy(dpB, inB, 8);
+
+ switch (test_type) {
+ case VX_FP_CMP:
+@@ -1656,7 +1574,6 @@ again:
+ // printf("\tFRA: %e; FRB: %e\n", spec_fargs[aTest.fra_idx], spec_fargs[aTest.frb_idx]);
+ if ( condreg != aTest.cr_flags) {
+ printf("Error: Expected CR flags 0x%x; actual flags: 0x%x\n", aTest.cr_flags, condreg);
+- errors++;
+ }
+ break;
+ case VX_FP_SMA:
+@@ -1676,7 +1593,7 @@ again:
+ * VSX[XT] -- i.e., vec_out. For the xs<ZZZ>mdp cases, VSX[XT] holds
+ * src3 and VSX[XB] holds src2; for the xs<ZZZ>adp cases, VSX[XT] holds
+ * src2 and VSX[XB] holds src3. The fp_test_args_t that holds the test
+- * data (input args, result) contain only two inputs, so I arbitrarily
++ * data (input args) contain only two inputs, so I arbitrarily
+ * use spec_fargs elements 4 and 14 (alternating) for the third source
+ * argument. We can use the same input data for a given pair of
+ * adp/mdp-type instructions by swapping the src2 and src3 arguments; thus
+@@ -1688,8 +1605,6 @@ again:
+ else
+ extra_arg_idx = 14;
+
+- //memcpy(&vec_out, &spec_fargs[14], 8);
+-
+ if (repeat) {
+ /* We're on the first time through of one of the VX_FP_SMx
+ * test types, meaning we're testing a xs<ZZZ>adp case, thus we
+@@ -1697,28 +1612,30 @@ again:
+ * src2 <= VSX[XT]
+ * src3 <= VSX[XB]
+ */
+- memcpy(&vec_out, inB, 8); // src2
+- memcpy(&vec_inB, &spec_fargs[extra_arg_idx], 8); //src3
++ if (isLE)
++ dpT++;
++ memcpy(dpT, inB, 8); // src2
++ memcpy(dpB, &spec_fargs[extra_arg_idx], 8); //src3
+ frbp = (unsigned long long *)&spec_fargs[extra_arg_idx];
+ } else {
+ // Don't need to init src2, as it's done before the switch()
+- memcpy(&vec_out, &spec_fargs[extra_arg_idx], 8); //src3
++ if (isLE)
++ dpT++;
++ memcpy(dpT, &spec_fargs[extra_arg_idx], 8); //src3
+ }
+- memcpy(&vsr_XT, &vec_out, 8);
++ memcpy(&vsr_XT, dpT, 8);
+ }
+
+ (*func)();
+ dst = (unsigned long long *) &vec_out;
++ if (isLE)
++ dst++;
+ if (test_type == VX_FP_OTHER)
+ printf("#%d: %s %016llx %016llx = %016llx\n", i, test_name, *frap, *frbp, *dst);
+ else
+ printf( "#%d: %s %016llx %016llx %016llx = %016llx\n", i,
+ test_name, vsr_XT, *frap, *frbp, *dst );
+
+- if ( *dst != aTest.dp_bin_result) {
+- printf("Error: Expected result %016llx; actual result %016llx\n", aTest.dp_bin_result, *dst);
+- errors++;
+- }
+ /*
+ {
+ // Debug code. Keep this block commented out except when debugging.
+@@ -1774,6 +1691,11 @@ static void test_xs_conv_ops(void)
+
+ test_func_t func;
+ int k = 0;
++ double * dpB = (double *)&vec_inB;
++ if (isLE) {
++ memset(dpB, 0, 8);
++ dpB++;
++ }
+
+ build_special_fargs_table();
+ while ((func = xs_conv_tests[k].test_func)) {
+@@ -1783,22 +1705,20 @@ static void test_xs_conv_ops(void)
+ for (i = 0; i < test_group.num_tests; i++) {
+ unsigned int * inB, * pv;
+ int idx;
+- unsigned long long exp_result = test_group.results[i];
+ inB = (unsigned int *)&spec_fargs[i];
+ frbp = (unsigned long long *)&spec_fargs[i];
+- memcpy(&vec_inB, inB, 8);
++
++ memcpy(dpB, inB, 8);
+ pv = (unsigned int *)&vec_out;
+ // clear vec_out
+ for (idx = 0; idx < 4; idx++, pv++)
+ *pv = 0;
+ (*func)();
+ dst = (unsigned long long *) &vec_out;
++ if (isLE)
++ dst++;
+ printf("#%d: %s %016llx => %016llx\n", i, test_group.name, *frbp, *dst);
+
+- if ( *dst != exp_result) {
+- printf("Error: Expected result %016llx; actual result %016llx\n", exp_result, *dst);
+- errors++;
+- }
+ }
+ k++;
+ printf("\n");
+@@ -1811,7 +1731,7 @@ static void do_load_test(ldst_test_t loadTest)
+ test_func_t func;
+ unsigned int *src, *dst;
+ int splat = loadTest.type == VSX_LOAD_SPLAT ? 1: 0;
+- int i, j, m, equality;
++ int i, j, m, k;
+ i = j = 0;
+
+ func = loadTest.test_func;
+@@ -1840,20 +1760,19 @@ static void do_load_test(ldst_test_t loadTest)
+ printf( " %08x", src[splat ? m % 2 : m]);
+ }
+ printf( " =>");
+- for (m = 0; m < loadTest.num_words_to_process; m++) {
+- printf( " %08x", dst[m]);
+- }
+- printf("\n");
+- equality = 1;
+- for (m = 0; m < loadTest.num_words_to_process; m++) {
+- equality = equality && (src[splat ? m % 2 : m] == dst[m]);
++ m = 0;
++ k = loadTest.num_words_to_process;
++ if (isLE) {
++ if (loadTest.num_words_to_process == 2) {
++ m = 2;
++ k += 2;
++ }
+ }
+
+- if (!equality) {
+- printf("FAILED: loaded vector is incorrect\n");
+- errors++;
++ for (; m < k; m++) {
++ printf( " %08x", dst[m]);
+ }
+-
++ printf("\n");
+ if (j == 0 && loadTest.offset) {
+ again = 1;
+ j += loadTest.offset;
+@@ -1868,7 +1787,7 @@ do_store_test ( ldst_test_t storeTest )
+ {
+ test_func_t func;
+ unsigned int *src, *dst;
+- int m, equality;
++ int m;
+
+ func = storeTest.test_func;
+ r14 = (HWord_t) storeTest.base_addr;
+@@ -1895,16 +1814,6 @@ do_store_test ( ldst_test_t storeTest )
+ printf( " %08x", dst[m] );
+ }
+ printf( "\n" );
+- equality = 1;
+- for (m = 0; m < storeTest.num_words_to_process; m++) {
+- equality = equality && (src[m] == dst[m]);
+- }
+-
+- if (!equality) {
+- printf( "FAILED: vector store result is incorrect\n" );
+- errors++;
+- }
+-
+ }
+
+
+@@ -1932,7 +1841,7 @@ static void test_ftdiv(void)
+ num_tests = sizeof ftdiv_tests/sizeof ftdiv_tests[0];
+
+ for (i = 0; i < num_tests; i++) {
+- ftdiv_test_args_t aTest = ftdiv_tests[i];
++ fp_test_args_t aTest = ftdiv_tests[i];
+ f14 = spec_fargs[aTest.fra_idx];
+ f15 = spec_fargs[aTest.frb_idx];
+ frap = (unsigned long long *)&spec_fargs[aTest.fra_idx];
+@@ -1946,7 +1855,6 @@ static void test_ftdiv(void)
+ // printf("\tFRA: %e; FRB: %e\n", f14, f15);
+ if ( crx != aTest.cr_flags) {
+ printf("Error: Expected CR flags 0x%x; actual flags: 0x%x\n", aTest.cr_flags, crx);
+- errors++;
+ }
+ }
+ printf( "\n" );
+@@ -1991,7 +1899,7 @@ static void test_vsx_logic(void)
+ {
+ logic_test_t aTest;
+ test_func_t func;
+- int equality, k;
++ int k;
+ k = 0;
+
+ while ((func = logic_tests[k].test_func)) {
+@@ -2021,82 +1929,68 @@ static void test_vsx_logic(void)
+ printf( " %08x %08x %08x %08x", inB[0], inB[1], inB[2], inB[3]);
+ printf(" => %08x %08x %08x %08x\n", dst[0], dst[1], dst[2], dst[3]);
+
+- equality = 1;
+- for (idx = 0; idx < 4; idx++) {
+- switch (aTest.op) {
+- case VSX_AND:
+- equality &= (dst[idx] == (inA[idx] & inB[idx]));
+- break;
+- case VSX_ANDC:
+- equality &= (dst[idx] == (inA[idx] & ~inB[idx]));
+- break;
+- case VSX_NOR:
+- equality &= (dst[idx] == ~(inA[idx] | inB[idx]));
+- break;
+- case VSX_XOR:
+- equality &= (dst[idx] == (inA[idx] ^ inB[idx]));
+- break;
+- case VSX_OR:
+- equality &= (dst[idx] == (inA[idx] | inB[idx]));
+- break;
+- default:
+- fprintf(stderr, "Error in test_vsx_logic(): unknown VSX logical op %d\n", aTest.op);
+- exit(1);
+- }
+- }
+- if (!equality) {
+- printf( "FAILED: vector out is incorrect\n" );
+- errors++;
+- }
+ }
+ k++;
+ }
+ printf( "\n" );
+ }
+
++static vector unsigned long long vec_args[] __attribute__ ((aligned (16))) =
++{
++ { 0x0123456789abcdefULL, 0x0011223344556677ULL},
++ { 0x8899aabb19293942ULL, 0xa1a2a3a4b1b2b3b4ULL},
++ { 0xc1c2c3c4d1d2d3d4ULL, 0x7a6b5d3efc032778ULL}
++};
++#define NUM_VEC_ARGS_LONGS (sizeof vec_args/sizeof vec_args[0])
++
+ static void test_move_ops (void)
+ {
+ move_test_t aTest;
+ test_func_t func;
+- int equality, k;
++ int k;
+ k = 0;
+
+ while ((func = move_tests[k].test_func)) {
+ unsigned int * pv;
+ int startA, startB;
+- unsigned int * inA, * inB, * dst;
+- unsigned long long exp_out;
++ unsigned long long * inA, * inB, * dst;
++ int use_vecA = (strcmp(move_tests[k].name, "xscpsgndp") == 0);
+ int idx;
++ inA = NULL;
+ aTest = move_tests[k];
+- exp_out = aTest.expected_result;
+- startA = aTest.xa_idx;
+- startB = aTest.xb_idx;
+- pv = (unsigned int *)&vec_out;
+- inA = &viargs[startA];
+- inB = &viargs[startB];
+- memcpy(&vec_inA, inA, sizeof(vector unsigned char));
+- memcpy(&vec_inB, inB, sizeof(vector unsigned char));
+- // clear vec_out
+- for (idx = 0; idx < 4; idx++, pv++)
+- *pv = 0;
+-
+- // execute test insn
+- (*func)();
+- dst = (unsigned int*) &vec_out;
++ for (startB = 0; startB < NUM_VEC_ARGS_LONGS; startB++) {
++ inB = (unsigned long long *)&vec_args[startB];
++ memcpy(&vec_inB, inB, sizeof(vector unsigned char));
++ if (isLE)
++ inB++;
++ startA = 0;
++repeat:
++ if (use_vecA) {
++ inA = (unsigned long long *)&vec_args[startA];
++ memcpy(&vec_inA, inA, sizeof(vector unsigned char));
++ startA++;
++ }
++ pv = (unsigned int *)&vec_out;
++ // clear vec_out
++ for (idx = 0; idx < 4; idx++, pv++)
++ *pv = 0;
+
+- printf( "%s:", aTest.name);
+- printf( " %08x %08x %s", inA[0], inA[1], aTest.name);
+- printf( " %08x %08xx", inB[0], inB[1]);
+- printf(" => %08x %08x\n", dst[0], dst[1]);
++ // execute test insn
++ (*func)();
++ dst = (unsigned long long *) &vec_out;
++ if (isLE) {
++ dst++;
++ inA++;
++ }
+
+- equality = 1;
+- pv = (unsigned int *)&exp_out;
+- for (idx = 0; idx < 2; idx++) {
+- equality &= (dst[idx] == pv[idx]);
+- }
+- if (!equality) {
+- printf( "FAILED: vector out is incorrect\n" );
+- errors++;
++ printf( "%s:", aTest.name);
++ if (use_vecA)
++ printf( " X[A]: %016llx ", *inA);
++ printf( " X[B]: %016llx", *inB);
++ printf(" => %016llx\n", *dst);
++
++ if (use_vecA && startA < NUM_VEC_ARGS_LONGS)
++ goto repeat;
+ }
+ k++;
+ printf( "\n" );
+@@ -2126,11 +2020,6 @@ static void test_permute_ops (void)
+ printf( " => XT[%08x,%08x,%08x,%08x]\n",
+ dst[0], dst[1], dst[2], dst[3]);
+
+- if (memcmp (dst, &aTest->expected_output, sizeof(vec_out)))
+- {
+- printf( "FAILED: vector out is incorrect\n" );
+- errors++;
+- }
+ }
+ printf( "\n" );
+ }
+@@ -2177,10 +2066,6 @@ int main(int argc, char *argv[])
+ (*func)();
+ i++;
+ }
+- if (errors)
+- printf("Testcase FAILED with %d errors \n", errors);
+- else
+- printf("Testcase PASSED\n");
+
+ #endif // HAS _VSX
+
+diff --git a/none/tests/ppc32/test_isa_2_06_part1.stdout.exp b/none/tests/ppc32/test_isa_2_06_part1.stdout.exp
+index 80f8564..2137a92 100644
+--- a/none/tests/ppc32/test_isa_2_06_part1.stdout.exp
++++ b/none/tests/ppc32/test_isa_2_06_part1.stdout.exp
+@@ -130,13 +130,27 @@ ftdiv: 0000000000000000 <=> 0000000000000000 ? e (CRx)
+ ftdiv: 0000000000000000 <=> 8000000000000000 ? e (CRx)
+
+ Test VSX move instructions
+-xsabsdp: 01234567 89abcdef xsabsdp 8899aabb 91929394x => 0899aabb 91929394
++xsabsdp: X[B]: 0123456789abcdef => 0123456789abcdef
++xsabsdp: X[B]: 8899aabb19293942 => 0899aabb19293942
++xsabsdp: X[B]: c1c2c3c4d1d2d3d4 => 41c2c3c4d1d2d3d4
+
+-xscpsgndp: 8899aabb 91929394 xscpsgndp 01234567 89abcdefx => 81234567 89abcdef
++xscpsgndp: X[A]: 0123456789abcdef X[B]: 0123456789abcdef => 0123456789abcdef
++xscpsgndp: X[A]: 8899aabb19293942 X[B]: 0123456789abcdef => 8123456789abcdef
++xscpsgndp: X[A]: c1c2c3c4d1d2d3d4 X[B]: 0123456789abcdef => 8123456789abcdef
++xscpsgndp: X[A]: 0123456789abcdef X[B]: 8899aabb19293942 => 0899aabb19293942
++xscpsgndp: X[A]: 8899aabb19293942 X[B]: 8899aabb19293942 => 8899aabb19293942
++xscpsgndp: X[A]: c1c2c3c4d1d2d3d4 X[B]: 8899aabb19293942 => 8899aabb19293942
++xscpsgndp: X[A]: 0123456789abcdef X[B]: c1c2c3c4d1d2d3d4 => 41c2c3c4d1d2d3d4
++xscpsgndp: X[A]: 8899aabb19293942 X[B]: c1c2c3c4d1d2d3d4 => c1c2c3c4d1d2d3d4
++xscpsgndp: X[A]: c1c2c3c4d1d2d3d4 X[B]: c1c2c3c4d1d2d3d4 => c1c2c3c4d1d2d3d4
+
+-xsnabsdp: b1b2b3b4 c1c2c3c4 xsnabsdp 44556677 8899aabbx => c4556677 8899aabb
++xsnabsdp: X[B]: 0123456789abcdef => 8123456789abcdef
++xsnabsdp: X[B]: 8899aabb19293942 => 8899aabb19293942
++xsnabsdp: X[B]: c1c2c3c4d1d2d3d4 => c1c2c3c4d1d2d3d4
+
+-xsnegdp: 01234567 89abcdef xsnegdp b1b2b3b4 c1c2c3c4x => 31b2b3b4 c1c2c3c4
++xsnegdp: X[B]: 0123456789abcdef => 8123456789abcdef
++xsnegdp: X[B]: 8899aabb19293942 => 0899aabb19293942
++xsnegdp: X[B]: c1c2c3c4d1d2d3d4 => 41c2c3c4d1d2d3d4
+
+ Test VSX permute instructions
+ xxmrghw:
+@@ -1020,4 +1034,3 @@ Test VSX scalar integer conversion instructions
+ #14: xscvuxddp c0d0650f5a07b353 => 43e81a0ca1eb40f6
+
+
+-Testcase PASSED
+diff --git a/none/tests/ppc32/test_isa_2_06_part2.c b/none/tests/ppc32/test_isa_2_06_part2.c
+index bb3ec08..b33849a 100644
+--- a/none/tests/ppc32/test_isa_2_06_part2.c
++++ b/none/tests/ppc32/test_isa_2_06_part2.c
+@@ -39,6 +39,13 @@ typedef uint64_t HWord_t;
+ typedef unsigned char Bool;
+ #define True 1
+ #define False 0
++
++#ifdef VGP_ppc64le_linux
++#define isLE 1
++#else
++#define isLE 0
++#endif
++
+ register HWord_t r14 __asm__ ("r14");
+ register HWord_t r15 __asm__ ("r15");
+ register HWord_t r16 __asm__ ("r16");
+@@ -798,8 +805,20 @@ static void test_xxspltw(void)
+ {
+ int uim;
+ unsigned long long * dst = NULL;
+- unsigned long long xb[] = { 0xfedc432124681235ULL, 0xf1e2d3c4e0057708ULL};
+- memcpy(&vec_inB, xb, 16);
++ unsigned int xb[] = { 0xfedc4321, 0x24681235, 0xf1e2d3c4, 0xe0057708};
++ int i;
++ void * vecB_ptr = &vec_inB;
++ if (isLE) {
++ for (i = 3; i >=0; i--) {
++ memcpy(vecB_ptr, &xb[i], 4);
++ vecB_ptr+=4;
++ }
++ } else {
++ for (i = 0; i < 4; i++) {
++ memcpy(vecB_ptr, &xb[i], 4);
++ vecB_ptr+=4;
++ }
++ }
+
+ for (uim = 0; uim < 4; uim++) {
+ switch (uim) {
+@@ -817,7 +836,8 @@ static void test_xxspltw(void)
+ break;
+ }
+ dst = (unsigned long long *) &vec_out;
+- printf("xxspltw 0x%016llx%016llx %d=> 0x%016llx", xb[0], xb[1], uim, *dst);
++ printf("xxspltw 0x%08x%08x%08x%08x %d=> 0x%016llx", xb[0], xb[1],
++ xb[2], xb[3], uim, *dst);
+ dst++;
+ printf("%016llx\n", *dst);
+ }
+@@ -1226,22 +1246,33 @@ static void test_vx_simple_scalar_fp_ops(void)
+ * (e.g. xssqrtdp).
+ */
+ if (test_group.num_tests == nb_special_fargs && !test_group.targs) {
+- void * inB;
++ void * inB, * vec_void_ptr = (void *)&vec_inB;
+ int i;
++ if (isLE)
++ vec_void_ptr += 8;
+ for (i = 0; i < nb_special_fargs; i++) {
+ inB = (void *)&spec_fargs[i];
+ frbp = (unsigned long long *)&spec_fargs[i];
+- memcpy(&vec_inB, inB, 8);
++ memcpy(vec_void_ptr, inB, 8);
+ (*func)();
+ dst = (unsigned long long *) &vec_out;
++ if (isLE)
++ dst++;
+ printf("#%d: %s %016llx => %016llx\n", i, test_group.name, *frbp,
+ convToWord ? (*dst & 0x00000000ffffffffULL) : *dst);
+ }
+ } else {
+- void * inA, * inB;
++ void * inA, * inB, * vecA_void_ptr, * vecB_void_ptr;
+ unsigned int condreg, flags;
+ int isTdiv = (strstr(test_group.name, "xstdivdp") != NULL) ? 1 : 0;
+ int i;
++ if (isLE) {
++ vecA_void_ptr = (void *)&vec_inA + 8;
++ vecB_void_ptr = (void *)&vec_inB + 8;
++ } else {
++ vecA_void_ptr = (void *)&vec_inA;
++ vecB_void_ptr = (void *)&vec_inB;
++ }
+ for (i = 0; i < test_group.num_tests; i++) {
+ fp_test_args_t aTest = test_group.targs[i];
+ inA = (void *)&spec_fargs[aTest.fra_idx];
+@@ -1249,8 +1280,8 @@ static void test_vx_simple_scalar_fp_ops(void)
+ frap = (unsigned long long *)&spec_fargs[aTest.fra_idx];
+ frbp = (unsigned long long *)&spec_fargs[aTest.frb_idx];
+ // Only need to copy one doubleword into each vector's element 0
+- memcpy(&vec_inA, inA, 8);
+- memcpy(&vec_inB, inB, 8);
++ memcpy(vecA_void_ptr, inA, 8);
++ memcpy(vecB_void_ptr, inB, 8);
+ SET_FPSCR_ZERO;
+ SET_CR_XER_ZERO;
+ (*func)();
+@@ -1260,6 +1291,8 @@ static void test_vx_simple_scalar_fp_ops(void)
+ printf("#%d: %s %016llx,%016llx => cr %x\n", i, test_group.name, *frap, *frbp, condreg);
+ } else {
+ dst = (unsigned long long *) &vec_out;
++ if (isLE)
++ dst++;
+ printf("#%d: %s %016llx,%016llx => %016llx\n", i, test_group.name,
+ *frap, *frbp, *dst);
+ }
+@@ -1346,21 +1379,26 @@ again:
+ * src3 <= VSX[XB]
+ */
+ if (scalar) {
++#ifdef VGP_ppc64le_linux
++#define VECTOR_ADDR(_v) ((void *)&_v) + 8
++#else
++#define VECTOR_ADDR(_v) ((void *)&_v)
++#endif
+ // For scalar op, only need to copy one doubleword into each vector's element 0
+ inA = (void *)&spec_fargs[aTest.fra_idx];
+ inB = (void *)&spec_fargs[aTest.frb_idx];
+ frap = (unsigned long long *)&spec_fargs[aTest.fra_idx];
+- memcpy(&vec_inA, inA, 8);
++ memcpy(VECTOR_ADDR(vec_inA), inA, 8);
+ if (repeat) {
+- memcpy(&vec_out, inB, 8); // src2
+- memcpy(&vec_inB, &spec_fargs[fp_idx[0]], 8); //src3
++ memcpy(VECTOR_ADDR(vec_out), inB, 8); // src2
++ memcpy(VECTOR_ADDR(vec_inB), &spec_fargs[fp_idx[0]], 8); //src3
+ frbp = (unsigned long long *)&spec_fargs[fp_idx[0]];
+ } else {
+ frbp = (unsigned long long *)&spec_fargs[aTest.frb_idx];
+- memcpy(&vec_inB, inB, 8); // src2
+- memcpy(&vec_out, &spec_fargs[fp_idx[0]], 8); //src3
++ memcpy(VECTOR_ADDR(vec_inB), inB, 8); // src2
++ memcpy(VECTOR_ADDR(vec_out), &spec_fargs[fp_idx[0]], 8); //src3
+ }
+- memcpy(vsr_XT, &vec_out, 8);
++ memcpy(vsr_XT, VECTOR_ADDR(vec_out), 8);
+ } else {
+ int j, loops = do_dp ? 2 : 4;
+ size_t len = do_dp ? 8 : 4;
+@@ -1382,6 +1420,8 @@ again:
+
+ (*func)();
+ dst = (unsigned long long *) &vec_out;
++ if (isLE)
++ dst++;
+ if (test_type < VX_VECTOR_FP_MULT_AND_OP2)
+ printf( "#%d: %s %s(%016llx,%016llx,%016llx) = %016llx\n", i,
+ test_name, test_group.op, vsr_XT[0], *frap, *frbp, *dst );
+diff --git a/none/tests/ppc32/test_isa_2_06_part3.c b/none/tests/ppc32/test_isa_2_06_part3.c
+index 13a653b..9f9cd79 100644
+--- a/none/tests/ppc32/test_isa_2_06_part3.c
++++ b/none/tests/ppc32/test_isa_2_06_part3.c
+@@ -36,6 +36,12 @@ typedef uint32_t HWord_t;
+ typedef uint64_t HWord_t;
+ #endif /* __powerpc64__ */
+
++#ifdef VGP_ppc64le_linux
++#define isLE 1
++#else
++#define isLE 0
++#endif
++
+ typedef unsigned char Bool;
+ #define True 1
+ #define False 0
+@@ -1116,7 +1122,7 @@ static void test_vsx_one_fp_arg(void)
+
+ for (i = 0; i < test_group.num_tests; i+=stride) {
+ unsigned int * pv;
+- void * inB;
++ void * inB, * vecB_void_ptr = (void *)&vec_inB;
+
+ pv = (unsigned int *)&vec_out;
+ // clear vec_out
+@@ -1129,11 +1135,15 @@ static void test_vsx_one_fp_arg(void)
+ for (j = 0; j < loops; j++) {
+ inB = (void *)&spec_fargs[i + j];
+ // copy double precision FP into vector element i
+- memcpy(((void *)&vec_inB) + (j * 8), inB, 8);
++ if (isLE && is_scalar)
++ vecB_void_ptr += 8;
++ memcpy(vecB_void_ptr + (j * 8), inB, 8);
+ }
+ // execute test insn
+ (*func)();
+ dst_dp = (unsigned long long *) &vec_out;
++ if (isLE && is_scalar)
++ dst_dp++;
+ printf("#%d: %s ", i/stride, test_group.name);
+ for (j = 0; j < loops; j++) {
+ if (j)
+@@ -1141,7 +1151,7 @@ static void test_vsx_one_fp_arg(void)
+ frB_dp = (unsigned long long *)&spec_fargs[i + j];
+ printf("%s(%016llx)", test_group.op, *frB_dp);
+ if (estimate) {
+- Bool res = check_estimate(DOUBLE_TEST, is_sqrt, i + j, j);
++ Bool res = check_estimate(DOUBLE_TEST, is_sqrt, i + j, (isLE && is_scalar) ? 1: j);
+ printf(" ==> %s)", res ? "PASS" : "FAIL");
+ /* For debugging . . .
+ printf(" ==> %s (res=%016llx)", res ? "PASS" : "FAIL", dst_dp[j]);
+@@ -1162,29 +1172,36 @@ static void test_vsx_one_fp_arg(void)
+ }
+ printf("\n");
+ } else {
+- int j, skip_slot;
++ int j;
+ unsigned int * frB_sp, * dst_sp = NULL;
+ unsigned long long * dst_dp = NULL;
+- if (sparse_sp) {
+- skip_slot = 1;
++ if (sparse_sp)
+ loops = 2;
+- } else {
+- skip_slot = 0;
+- }
+ for (j = 0; j < loops; j++) {
+ inB = (void *)&spec_sp_fargs[i + j];
+ // copy single precision FP into vector element i
+- if (skip_slot && j > 0)
+- memcpy(((void *)&vec_inB) + ((j + j) * 4), inB, 4);
+- else
+- memcpy(((void *)&vec_inB) + (j * 4), inB, 4);
++ if (sparse_sp) {
++ if (isLE)
++ memcpy(vecB_void_ptr + ((2 * j * 4) + 4), inB, 4);
++ else
++ memcpy(vecB_void_ptr + ((2 * j * 4) ), inB, 4);
++ } else {
++ if (isLE && is_scalar)
++ vecB_void_ptr += 12;
++ memcpy(vecB_void_ptr + (j * 4), inB, 4);
++ }
+ }
+ // execute test insn
+ (*func)();
+- if (test_group.type == VX_CONV_TO_DOUBLE)
++ if (test_group.type == VX_CONV_TO_DOUBLE) {
+ dst_dp = (unsigned long long *) &vec_out;
+- else
++ if (isLE && is_scalar)
++ dst_dp++;
++ } else {
+ dst_sp = (unsigned int *) &vec_out;
++ if (isLE && is_scalar)
++ dst_sp += 3;
++ }
+ // print result
+ printf("#%d: %s ", i/stride, test_group.name);
+ for (j = 0; j < loops; j++) {
+@@ -1193,7 +1210,7 @@ static void test_vsx_one_fp_arg(void)
+ frB_sp = (unsigned int *)&spec_sp_fargs[i + j];
+ printf("%s(%08x)", test_group.op, *frB_sp);
+ if (estimate) {
+- Bool res = check_estimate(SINGLE_TEST, is_sqrt, i + j, j);
++ Bool res = check_estimate(SINGLE_TEST, is_sqrt, i + j, (isLE && is_scalar) ? 3 : j);
+ printf(" ==> %s)", res ? "PASS" : "FAIL");
+ } else {
+ if (test_group.type == VX_CONV_TO_DOUBLE)
+@@ -1275,23 +1292,24 @@ static void test_int_to_fp_convert(void)
+ }
+ printf("\n");
+ } else {
+- int j, skip_slot;
++ int j;
+ unsigned int * dst_sp = NULL;
+ unsigned int * targs = test_group.targs;
+ unsigned long long * dst_dp = NULL;
+- if (sparse_sp) {
+- skip_slot = 1;
++ void * vecB_void_ptr = (void *)&vec_inB;
++ if (sparse_sp)
+ loops = 2;
+- } else {
+- skip_slot = 0;
+- }
+ for (j = 0; j < loops; j++) {
+ inB = (void *)&targs[i + j];
+ // copy single word into vector element i
+- if (skip_slot && j > 0)
+- memcpy(((void *)&vec_inB) + ((j + j) * 4), inB, 4);
+- else
+- memcpy(((void *)&vec_inB) + (j * 4), inB, 4);
++ if (sparse_sp) {
++ if (isLE)
++ memcpy(vecB_void_ptr + ((2 * j * 4) + 4), inB, 4);
++ else
++ memcpy(vecB_void_ptr + ((2 * j * 4) ), inB, 4);
++ } else {
++ memcpy(vecB_void_ptr + (j * 4), inB, 4);
++ }
+ }
+ // execute test insn
+ (*func)();
+@@ -1441,7 +1459,7 @@ static void test_vx_tdivORtsqrt(void)
+
+ for (i = 0; i < test_group.num_tests; i+=stride) {
+ unsigned int * pv;
+- void * inB;
++ void * inB, * vecB_void_ptr = (void *)&vec_inB;
+
+ pv = (unsigned int *)&vec_out;
+ // clear vec_out
+@@ -1457,7 +1475,9 @@ static void test_vx_tdivORtsqrt(void)
+ for (j = 0; j < loops; j++) {
+ inB = (void *)&spec_fargs[i + j];
+ // copy double precision FP into vector element i
+- memcpy(((void *)&vec_inB) + (j * 8), inB, 8);
++ if (isLE && is_scalar)
++ vecB_void_ptr += 8;
++ memcpy(vecB_void_ptr + (j * 8), inB, 8);
+ }
+ }
+ // execute test insn
+diff --git a/none/tests/ppc32/test_isa_2_07_part2.stdout.exp b/none/tests/ppc32/test_isa_2_07_part2.stdout.exp
+index 6d06bf1..3539405 100644
+--- a/none/tests/ppc32/test_isa_2_07_part2.stdout.exp
++++ b/none/tests/ppc32/test_isa_2_07_part2.stdout.exp
+@@ -651,26 +651,26 @@ Test VSX floating point instructions
+
+
+ Test VSX vector and scalar single argument instructions
+-#0: xscvdpspn conv(3ec00000) = 3ec00000
+-#1: xscvdpspn conv(42780000) = 42780000
+-#2: xscvdpspn conv(00000000) = 00000000
+-#3: xscvdpspn conv(7f800000) = 7f800000
+-#4: xscvdpspn conv(00000000) = 00000000
+-#5: xscvdpspn conv(00000000) = 00000000
+-#6: xscvdpspn conv(80000000) = 80000000
+-#7: xscvdpspn conv(7f800000) = 7f800000
+-#8: xscvdpspn conv(ff800000) = ff800000
+-#9: xscvdpspn conv(7fbfffff) = 7fbfffff
+-#10: xscvdpspn conv(ffbfffff) = ffbfffff
+-#11: xscvdpspn conv(7fc00000) = 7fc00000
+-#12: xscvdpspn conv(ffc00000) = ffc00000
+-#13: xscvdpspn conv(80000000) = 80000000
+-#14: xscvdpspn conv(c683287b) = c683287b
+-#15: xscvdpspn conv(49192c2d) = 49192c2d
+-#16: xscvdpspn conv(49c1288d) = 49c1288d
+-#17: xscvdpspn conv(418977ad) = 418977ad
+-#18: xscvdpspn conv(428a5faf) = 428a5faf
+-#19: xscvdpspn conv(44bb5fcc) = 44bb5fcc
++#0: xscvdpspn conv(3fd8000000000000) = 3ec00000
++#1: xscvdpspn conv(404f000000000000) = 42780000
++#2: xscvdpspn conv(0018000000b77501) = 00000000
++#3: xscvdpspn conv(7fe800000000051b) = 7f800000
++#4: xscvdpspn conv(0123214569900000) = 00000000
++#5: xscvdpspn conv(0000000000000000) = 00000000
++#6: xscvdpspn conv(8000000000000000) = 80000000
++#7: xscvdpspn conv(7ff0000000000000) = 7f800000
++#8: xscvdpspn conv(fff0000000000000) = ff800000
++#9: xscvdpspn conv(7ff7ffffffffffff) = 7fbfffff
++#10: xscvdpspn conv(fff7ffffffffffff) = ffbfffff
++#11: xscvdpspn conv(7ff8000000000000) = 7fc00000
++#12: xscvdpspn conv(fff8000000000000) = ffc00000
++#13: xscvdpspn conv(8008340000078000) = 80000000
++#14: xscvdpspn conv(c0d0650f5a07b353) = c683287b
++#15: xscvdpspn conv(41232585a9900000) = 49192c2d
++#16: xscvdpspn conv(41382511a2000000) = 49c1288d
++#17: xscvdpspn conv(40312ef5a9300000) = 418977ad
++#18: xscvdpspn conv(40514bf5d2300000) = 428a5faf
++#19: xscvdpspn conv(40976bf982440000) = 44bb5fcc
+
+ #0: xscvspdpn conv(3ec00000) = 3fd8000000000000
+ #1: xscvspdpn conv(42780000) = 404f000000000000
+@@ -783,23 +783,15 @@ Test VSX logic instructions
+ #2: xxlnand (80000001 89abcdef 00112233 74556677, 80000001 89abcdef 00112233 74556677) ==> 7ffffffe 76543210 ffeeddcc 8baa9988
+
+ Test VSX scalar integer conversion instructions
+-#0: xscvsxdsp 80000001 => c3e0000000000000
+-#1: xscvsxdsp 89abcdef => c3dd950c80000000
+-#2: xscvsxdsp 00112233 => 4331223380000000
+-#3: xscvsxdsp 74556677 => 43dd1559a0000000
+-#4: xscvsxdsp 00001abb => 42babb89a0000000
+-#5: xscvsxdsp 00000001 => 41f89abce0000000
+-#6: xscvsxdsp 31929394 => 43c8c949c0000000
+-#7: xscvsxdsp a1a2a3a4 => c3d7975720000000
+-
+-#0: xscvuxdsp 80000001 => 43e0000000000000
+-#1: xscvuxdsp 89abcdef => 43e13579c0000000
+-#2: xscvuxdsp 00112233 => 4331223380000000
+-#3: xscvuxdsp 74556677 => 43dd1559a0000000
+-#4: xscvuxdsp 00001abb => 42babb89a0000000
+-#5: xscvuxdsp 00000001 => 41f89abce0000000
+-#6: xscvuxdsp 31929394 => 43c8c949c0000000
+-#7: xscvuxdsp a1a2a3a4 => 43e4345480000000
++#0: xscvsxdsp 0102030405060708 => 4370203040000000
++#1: xscvsxdsp 090a0b0c0e0d0e0f => 43a2141620000000
++#2: xscvsxdsp f1f2f3f4f5f6f7f8 => c3ac1a1820000000
++#3: xscvsxdsp f9fafbfcfefdfeff => c398141000000000
++
++#0: xscvuxdsp 0102030405060708 => 4370203040000000
++#1: xscvuxdsp 090a0b0c0e0d0e0f => 43a2141620000000
++#2: xscvuxdsp f1f2f3f4f5f6f7f8 => 43ee3e5e80000000
++#3: xscvuxdsp f9fafbfcfefdfeff => 43ef3f5f80000000
+
+
+ Test VSX load/store dp to sp instructions
+@@ -812,14 +804,13 @@ stxsspx: 41232585a0000000 ==> 49192c2d
+ stxsspx: 40514bf5e0000000 ==> 428a5faf
+
+
+-stxsiwx: 80000001 ==> 80000001
+-stxsiwx: 89abcdef ==> 89abcdef
+-stxsiwx: 00112233 ==> 00112233
+-stxsiwx: 74556677 ==> 74556677
+-stxsiwx: 00001abb ==> 00001abb
+-stxsiwx: 00000001 ==> 00000001
+-stxsiwx: 31929394 ==> 31929394
+-stxsiwx: a1a2a3a4 ==> a1a2a3a4
++stxsiwx: 3ec00000 ==> 3ec00000
++stxsiwx: 7f800000 ==> 7f800000
++stxsiwx: 80000000 ==> 80000000
++stxsiwx: 7fbfffff ==> 7fbfffff
++stxsiwx: ffc00000 ==> ffc00000
++stxsiwx: 49192c2d ==> 49192c2d
++stxsiwx: 428a5faf ==> 428a5faf
+
+
+ lxsiwax: 80000001 ==> ffffffff80000001
+@@ -832,14 +823,13 @@ lxsiwax: 31929394 ==> 0000000031929394
+ lxsiwax: a1a2a3a4 ==> ffffffffa1a2a3a4
+
+
+-lxsiwzx: 89abcdef ==> 00000000abcdef00
+-lxsiwzx: 00112233 ==> 0000000011223374
+-lxsiwzx: 74556677 ==> 0000000055667700
+-lxsiwzx: 00001abb ==> 00000000001abb00
+-lxsiwzx: 00000001 ==> 0000000000000131
+-lxsiwzx: 31929394 ==> 00000000929394a1
+-lxsiwzx: a1a2a3a4 ==> 00000000a2a3a410
+-lxsiwzx: 10000b08 ==> 00000000000b0810
++lxsiwzx: 89abcdef ==> 0000000089abcdef
++lxsiwzx: 00112233 ==> 0000000000112233
++lxsiwzx: 74556677 ==> 0000000074556677
++lxsiwzx: 00001abb ==> 0000000000001abb
++lxsiwzx: 00000001 ==> 0000000000000001
++lxsiwzx: 31929394 ==> 0000000031929394
++lxsiwzx: a1a2a3a4 ==> 00000000a1a2a3a4
+
+
+ lxsspx: 3ec00000 ==> 3fd8000000000000
+diff --git a/none/tests/ppc64/Makefile.am b/none/tests/ppc64/Makefile.am
+index 20a2ebb..8fd4d6b 100644
+--- a/none/tests/ppc64/Makefile.am
++++ b/none/tests/ppc64/Makefile.am
+@@ -4,20 +4,20 @@ include $(top_srcdir)/Makefile.tool-tests.am
+ dist_noinst_SCRIPTS = filter_stderr
+
+ EXTRA_DIST = \
+- jm-int.stderr.exp jm-int.stdout.exp jm-int.vgtest \
+- jm-fp.stderr.exp jm-fp.stdout.exp jm-fp.vgtest \
+- jm-vmx.stderr.exp jm-vmx.stdout.exp jm-vmx.stdout.exp_Minus_nan \
++ jm-int.stderr.exp jm-int.stdout.exp jm-int.vgtest jm-int.stdout.exp-LE \
++ jm-fp.stderr.exp jm-fp.stdout.exp jm-fp.vgtest jm-fp.stdout.exp-LE jm-fp.stdout.exp-LE2 jm-fp.stdout.exp-BE2 \
++ jm-vmx.stderr.exp jm-vmx.stdout.exp jm-vmx.stdout.exp_Minus_nan jm-vmx.stdout.exp-LE \
+ jm-vmx.vgtest \
+ jm-misc.stderr.exp jm-misc.stdout.exp jm-misc.vgtest \
+ lsw.stderr.exp lsw.stdout.exp lsw.vgtest \
+- std_reg_imm.vgtest std_reg_imm.stderr.exp std_reg_imm.stdout.exp \
+- round.stderr.exp round.stdout.exp round.vgtest \
++ std_reg_imm.vgtest std_reg_imm.stderr.exp std_reg_imm.stdout.exp std_reg_imm.stdout.exp-LE \
++ round.stderr.exp round.stdout.exp round.vgtest round.stdout.exp-RM-fix \
+ twi_tdi.stderr.exp twi_tdi.stdout.exp twi_tdi.vgtest \
+ tw_td.stderr.exp tw_td.stdout.exp tw_td.vgtest \
+ opcodes.h \
+ power6_bcmp.stderr.exp power6_bcmp.stdout.exp power6_bcmp.vgtest \
+ power6_mf_gpr.stderr.exp power6_mf_gpr.stdout.exp power6_mf_gpr.vgtest \
+- test_isa_2_06_part1.stderr.exp test_isa_2_06_part1.stdout.exp test_isa_2_06_part1.vgtest \
++ test_isa_2_06_part1.stderr.exp test_isa_2_06_part1.stdout.exp test_isa_2_06_part1.vgtest test_isa_2_06_part1.stdout.exp-LE \
+ test_isa_2_06_part2.stderr.exp test_isa_2_06_part2.stdout.exp test_isa_2_06_part2.vgtest \
+ test_isa_2_06_part3.stderr.exp test_isa_2_06_part3.stdout.exp test_isa_2_06_part3.vgtest \
+ test_dfp1.stderr.exp test_dfp1.stdout.exp test_dfp1.vgtest \
+@@ -85,33 +85,45 @@ test_isa_2_06_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_
+ test_isa_2_06_part2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) \
+ @FLAG_M64@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX)
+
+-test_isa_2_06_part3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(VSX_FLAG) \
++test_isa_2_06_part3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(VSX_FLAG) \
+ @FLAG_M64@ $(ALTIVEC_FLAG) $(BUILD_FLAG_VSX)
+
+ jm_insns_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames -maltivec \
+ @FLAG_M64@ $(ALTIVEC_FLAG)
+
+-test_dfp1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
++test_dfp1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
+ @FLAG_M64@ $(BUILD_FLAGS_DFP)
+
+-test_dfp2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
++test_dfp2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
+ @FLAG_M64@ $(BUILD_FLAGS_DFP)
+-test_dfp3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
++test_dfp3_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
+ @FLAG_M64@ $(BUILD_FLAGS_DFP)
+
+-test_dfp4_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
++test_dfp4_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
+ @FLAG_M64@ $(BUILD_FLAGS_DFP)
+
+-test_dfp5_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(DFP_FLAG) \
++test_dfp5_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(DFP_FLAG) \
+ @FLAG_M64@ $(BUILD_FLAGS_DFP)
+
+-test_isa_2_07_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \
++test_isa_2_07_part1_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_2_07_FLAG) \
+ @FLAG_M64@ $(BUILD_FLAGS_ISA_2_07)
+
+-test_isa_2_07_part2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \
++test_isa_2_07_part2_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_2_07_FLAG) \
+ @FLAG_M64@ $(BUILD_FLAGS_ISA_2_07)
+
+-test_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \
++test_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_2_07_FLAG) \
+ @FLAG_M64@ $(BUILD_FLAGS_ISA_2_07)
+-test_touch_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -lm -g -mregnames $(ISA_2_07_FLAG) \
++test_touch_tm_CFLAGS = $(AM_CFLAGS) -Winline -Wall -O -g -mregnames $(ISA_2_07_FLAG) \
+ @FLAG_M64@ $(BUILD_FLAGS_ISA_2_07)
++
++test_isa_2_06_part3_LDADD = -lm
++test_dfp1_LDADD = -lm
++test_dfp2_LDADD = -lm
++test_dfp3_LDADD = -lm
++test_dfp4_LDADD = -lm
++test_dfp5_LDADD = -lm
++test_isa_2_07_part1_LDADD = -lm
++test_isa_2_07_part2_LDADD = -lm
++test_tm_LDADD = -lm
++test_touch_tm_LDADD = -lm
++
+diff --git a/none/tests/ppc64/jm-fp.stdout.exp b/none/tests/ppc64/jm-fp.stdout.exp
+index 00bd727..b555430 100644
+--- a/none/tests/ppc64/jm-fp.stdout.exp
++++ b/none/tests/ppc64/jm-fp.stdout.exp
+@@ -692,11 +692,11 @@ PPC floating point compare insns (two args):
+ PPC floating point arith insns with one arg:
+ fres 0010000000000001 => 7ff0000000000000
+ fres 00100094e0000359 => 7ff0000000000000
+- fres 3fe0000000000001 => 4000000000000000
++ fres 3fe0000000000001 => 3ffff00000000000
+ fres 3fe00094e0000359 => 3ffff00000000000
+ fres 8010000000000001 => fff0000000000000
+ fres 80100094e0000359 => fff0000000000000
+- fres bfe0000000000001 => c000000000000000
++ fres bfe0000000000001 => bffff00000000000
+ fres bfe00094e0000359 => bffff00000000000
+ fres 0000000000000000 => 7ff0000000000000
+ fres 8000000000000000 => fff0000000000000
+@@ -915,11 +915,11 @@ PPC floating point arith insns
+ with one arg with flags update:
+ fres. 0010000000000001 => 7ff0000000000000
+ fres. 00100094e0000359 => 7ff0000000000000
+- fres. 3fe0000000000001 => 4000000000000000
++ fres. 3fe0000000000001 => 3ffff00000000000
+ fres. 3fe00094e0000359 => 3ffff00000000000
+ fres. 8010000000000001 => fff0000000000000
+ fres. 80100094e0000359 => fff0000000000000
+- fres. bfe0000000000001 => c000000000000000
++ fres. bfe0000000000001 => bffff00000000000
+ fres. bfe00094e0000359 => bffff00000000000
+ fres. 0000000000000000 => 7ff0000000000000
+ fres. 8000000000000000 => fff0000000000000
+@@ -1122,21 +1122,21 @@ PPC floating point status register manipulation insns
+ with flags update:
+ PPC float load insns
+ with one register + one 16 bits immediate args with flags update:
+- lfs 0010000000000001, -120 => 37e0000000000000, 0
+- lfs 00100094e0000359, -112 => 37e0009400000000, 0
+- lfs 3fe0000000000001, -104 => 3ffc000000000000, 0
+- lfs 3fe00094e0000359, -96 => 3ffc001280000000, 0
+- lfs 8010000000000001, -88 => b7e0000000000000, 0
+- lfs 80100094e0000359, -80 => b7e0009400000000, 0
+- lfs bfe0000000000001, -72 => bffc000000000000, 0
+- lfs bfe00094e0000359, -64 => bffc001280000000, 0
+- lfs 0000000000000000, -56 => 0000000000000000, 0
+- lfs 8000000000000000, -48 => 8000000000000000, 0
+- lfs 7ff0000000000000, -40 => 7ffe000000000000, 0
+- lfs fff0000000000000, -32 => fffe000000000000, 0
+- lfs 7ff7ffffffffffff, -24 => 7ffeffffe0000000, 0
+- lfs fff7ffffffffffff, -16 => fffeffffe0000000, 0
+- lfs 7ff8000000000000, -8 => 7fff000000000000, 0
++ lfs 0010000000000001, 65416 => 37e0000000000000, 0
++ lfs 00100094e0000359, 65424 => 37e0009400000000, 0
++ lfs 3fe0000000000001, 65432 => 3ffc000000000000, 0
++ lfs 3fe00094e0000359, 65440 => 3ffc001280000000, 0
++ lfs 8010000000000001, 65448 => b7e0000000000000, 0
++ lfs 80100094e0000359, 65456 => b7e0009400000000, 0
++ lfs bfe0000000000001, 65464 => bffc000000000000, 0
++ lfs bfe00094e0000359, 65472 => bffc001280000000, 0
++ lfs 0000000000000000, 65480 => 0000000000000000, 0
++ lfs 8000000000000000, 65488 => 8000000000000000, 0
++ lfs 7ff0000000000000, 65496 => 7ffe000000000000, 0
++ lfs fff0000000000000, 65504 => fffe000000000000, 0
++ lfs 7ff7ffffffffffff, 65512 => 7ffeffffe0000000, 0
++ lfs fff7ffffffffffff, 65520 => fffeffffe0000000, 0
++ lfs 7ff8000000000000, 65528 => 7fff000000000000, 0
+ lfs 0010000000000001, 0 => 37e0000000000000, 0
+ lfs 00100094e0000359, 8 => 37e0009400000000, 0
+ lfs 3fe0000000000001, 16 => 3ffc000000000000, 0
+@@ -1154,21 +1154,21 @@ PPC float load insns
+ lfs 7ff8000000000000, 112 => 7fff000000000000, 0
+ lfs fff8000000000000, 120 => ffff000000000000, 0
+
+- lfsu 0010000000000001, -120 => 37e0000000000000, -120
+- lfsu 00100094e0000359, -112 => 37e0009400000000, -112
+- lfsu 3fe0000000000001, -104 => 3ffc000000000000, -104
+- lfsu 3fe00094e0000359, -96 => 3ffc001280000000, -96
+- lfsu 8010000000000001, -88 => b7e0000000000000, -88
+- lfsu 80100094e0000359, -80 => b7e0009400000000, -80
+- lfsu bfe0000000000001, -72 => bffc000000000000, -72
+- lfsu bfe00094e0000359, -64 => bffc001280000000, -64
+- lfsu 0000000000000000, -56 => 0000000000000000, -56
+- lfsu 8000000000000000, -48 => 8000000000000000, -48
+- lfsu 7ff0000000000000, -40 => 7ffe000000000000, -40
+- lfsu fff0000000000000, -32 => fffe000000000000, -32
+- lfsu 7ff7ffffffffffff, -24 => 7ffeffffe0000000, -24
+- lfsu fff7ffffffffffff, -16 => fffeffffe0000000, -16
+- lfsu 7ff8000000000000, -8 => 7fff000000000000, -8
++ lfsu 0010000000000001, 65416 => 37e0000000000000, -120
++ lfsu 00100094e0000359, 65424 => 37e0009400000000, -112
++ lfsu 3fe0000000000001, 65432 => 3ffc000000000000, -104
++ lfsu 3fe00094e0000359, 65440 => 3ffc001280000000, -96
++ lfsu 8010000000000001, 65448 => b7e0000000000000, -88
++ lfsu 80100094e0000359, 65456 => b7e0009400000000, -80
++ lfsu bfe0000000000001, 65464 => bffc000000000000, -72
++ lfsu bfe00094e0000359, 65472 => bffc001280000000, -64
++ lfsu 0000000000000000, 65480 => 0000000000000000, -56
++ lfsu 8000000000000000, 65488 => 8000000000000000, -48
++ lfsu 7ff0000000000000, 65496 => 7ffe000000000000, -40
++ lfsu fff0000000000000, 65504 => fffe000000000000, -32
++ lfsu 7ff7ffffffffffff, 65512 => 7ffeffffe0000000, -24
++ lfsu fff7ffffffffffff, 65520 => fffeffffe0000000, -16
++ lfsu 7ff8000000000000, 65528 => 7fff000000000000, -8
+ lfsu 0010000000000001, 0 => 37e0000000000000, 0
+ lfsu 00100094e0000359, 8 => 37e0009400000000, 8
+ lfsu 3fe0000000000001, 16 => 3ffc000000000000, 16
+@@ -1186,21 +1186,21 @@ PPC float load insns
+ lfsu 7ff8000000000000, 112 => 7fff000000000000, 112
+ lfsu fff8000000000000, 120 => ffff000000000000, 120
+
+- lfd 0010000000000001, -120 => 0010000000000001, 0
+- lfd 00100094e0000359, -112 => 00100094e0000359, 0
+- lfd 3fe0000000000001, -104 => 3fe0000000000001, 0
+- lfd 3fe00094e0000359, -96 => 3fe00094e0000359, 0
+- lfd 8010000000000001, -88 => 8010000000000001, 0
+- lfd 80100094e0000359, -80 => 80100094e0000359, 0
+- lfd bfe0000000000001, -72 => bfe0000000000001, 0
+- lfd bfe00094e0000359, -64 => bfe00094e0000359, 0
+- lfd 0000000000000000, -56 => 0000000000000000, 0
+- lfd 8000000000000000, -48 => 8000000000000000, 0
+- lfd 7ff0000000000000, -40 => 7ff0000000000000, 0
+- lfd fff0000000000000, -32 => fff0000000000000, 0
+- lfd 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, 0
+- lfd fff7ffffffffffff, -16 => fff7ffffffffffff, 0
+- lfd 7ff8000000000000, -8 => 7ff8000000000000, 0
++ lfd 0010000000000001, 65416 => 0010000000000001, 0
++ lfd 00100094e0000359, 65424 => 00100094e0000359, 0
++ lfd 3fe0000000000001, 65432 => 3fe0000000000001, 0
++ lfd 3fe00094e0000359, 65440 => 3fe00094e0000359, 0
++ lfd 8010000000000001, 65448 => 8010000000000001, 0
++ lfd 80100094e0000359, 65456 => 80100094e0000359, 0
++ lfd bfe0000000000001, 65464 => bfe0000000000001, 0
++ lfd bfe00094e0000359, 65472 => bfe00094e0000359, 0
++ lfd 0000000000000000, 65480 => 0000000000000000, 0
++ lfd 8000000000000000, 65488 => 8000000000000000, 0
++ lfd 7ff0000000000000, 65496 => 7ff0000000000000, 0
++ lfd fff0000000000000, 65504 => fff0000000000000, 0
++ lfd 7ff7ffffffffffff, 65512 => 7ff7ffffffffffff, 0
++ lfd fff7ffffffffffff, 65520 => fff7ffffffffffff, 0
++ lfd 7ff8000000000000, 65528 => 7ff8000000000000, 0
+ lfd 0010000000000001, 0 => 0010000000000001, 0
+ lfd 00100094e0000359, 8 => 00100094e0000359, 0
+ lfd 3fe0000000000001, 16 => 3fe0000000000001, 0
+@@ -1218,21 +1218,21 @@ PPC float load insns
+ lfd 7ff8000000000000, 112 => 7ff8000000000000, 0
+ lfd fff8000000000000, 120 => fff8000000000000, 0
+
+- lfdu 0010000000000001, -120 => 0010000000000001, -120
+- lfdu 00100094e0000359, -112 => 00100094e0000359, -112
+- lfdu 3fe0000000000001, -104 => 3fe0000000000001, -104
+- lfdu 3fe00094e0000359, -96 => 3fe00094e0000359, -96
+- lfdu 8010000000000001, -88 => 8010000000000001, -88
+- lfdu 80100094e0000359, -80 => 80100094e0000359, -80
+- lfdu bfe0000000000001, -72 => bfe0000000000001, -72
+- lfdu bfe00094e0000359, -64 => bfe00094e0000359, -64
+- lfdu 0000000000000000, -56 => 0000000000000000, -56
+- lfdu 8000000000000000, -48 => 8000000000000000, -48
+- lfdu 7ff0000000000000, -40 => 7ff0000000000000, -40
+- lfdu fff0000000000000, -32 => fff0000000000000, -32
+- lfdu 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, -24
+- lfdu fff7ffffffffffff, -16 => fff7ffffffffffff, -16
+- lfdu 7ff8000000000000, -8 => 7ff8000000000000, -8
++ lfdu 0010000000000001, 65416 => 0010000000000001, -120
++ lfdu 00100094e0000359, 65424 => 00100094e0000359, -112
++ lfdu 3fe0000000000001, 65432 => 3fe0000000000001, -104
++ lfdu 3fe00094e0000359, 65440 => 3fe00094e0000359, -96
++ lfdu 8010000000000001, 65448 => 8010000000000001, -88
++ lfdu 80100094e0000359, 65456 => 80100094e0000359, -80
++ lfdu bfe0000000000001, 65464 => bfe0000000000001, -72
++ lfdu bfe00094e0000359, 65472 => bfe00094e0000359, -64
++ lfdu 0000000000000000, 65480 => 0000000000000000, -56
++ lfdu 8000000000000000, 65488 => 8000000000000000, -48
++ lfdu 7ff0000000000000, 65496 => 7ff0000000000000, -40
++ lfdu fff0000000000000, 65504 => fff0000000000000, -32
++ lfdu 7ff7ffffffffffff, 65512 => 7ff7ffffffffffff, -24
++ lfdu fff7ffffffffffff, 65520 => fff7ffffffffffff, -16
++ lfdu 7ff8000000000000, 65528 => 7ff8000000000000, -8
+ lfdu 0010000000000001, 0 => 0010000000000001, 0
+ lfdu 00100094e0000359, 8 => 00100094e0000359, 8
+ lfdu 3fe0000000000001, 16 => 3fe0000000000001, 16
+diff --git a/none/tests/ppc64/jm-fp.stdout.exp-BE2 b/none/tests/ppc64/jm-fp.stdout.exp-BE2
+new file mode 100644
+index 0000000..7b83f30
+--- /dev/null
++++ b/none/tests/ppc64/jm-fp.stdout.exp-BE2
+@@ -0,0 +1,1533 @@
++PPC floating point arith insns with three args:
++ fsel 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
++ fsel 0010000000000001, 0010000000000001, bfe00094e0000359 => 0010000000000000
++ fsel 0010000000000001, 80100094e0000359, 0010000000000001 => 80100094e0000300
++ fsel 0010000000000001, 80100094e0000359, bfe00094e0000359 => 80100094e0000300
++ fsel 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0010000000000000
++ fsel 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 0010000000000000
++ fsel 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80100094e0000300
++ fsel 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 80100094e0000300
++ fsel bfe0000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
++ fsel bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fsel bfe0000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
++ fsel bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++
++ fmadd 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
++ fmadd 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fmadd 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
++ fmadd 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++ fmadd 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0018004a70000100
++ fmadd 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fmadd 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0007ff6b1d4b5e00
++ fmadd 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++ fmadd bfe0000000000001, 0010000000000001, 0010000000000001 => 0008000000000000
++ fmadd bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fmadd bfe0000000000001, 80100094e0000359, 0010000000000001 => 0018004a70000100
++ fmadd bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++
++ fmadds 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
++ fmadds 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fmadds 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fmadds 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++ fmadds 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000
++ fmadds 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fmadds 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fmadds 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++ fmadds bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
++ fmadds bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fmadds bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fmadds bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++
++ fmsub 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000
++ fmsub 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fmsub 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000
++ fmsub 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++ fmsub 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8007ffb58ffffe00
++ fmsub 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fmsub 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80180094e2b4a100
++ fmsub 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++ fmsub bfe0000000000001, 0010000000000001, 0010000000000001 => 8018000000000000
++ fmsub bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fmsub bfe0000000000001, 80100094e0000359, 0010000000000001 => 8007ffb58ffffe00
++ fmsub bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++
++ fmsubs 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
++ fmsubs 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fmsubs 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fmsubs 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++ fmsubs 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000
++ fmsubs 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fmsubs 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fmsubs 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++ fmsubs bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
++ fmsubs bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fmsubs bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fmsubs bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++
++ fnmadd 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000
++ fnmadd 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fnmadd 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000
++ fnmadd 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++ fnmadd 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8018004a70000100
++ fnmadd 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fnmadd 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8007ff6b1d4b5e00
++ fnmadd 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++ fnmadd bfe0000000000001, 0010000000000001, 0010000000000001 => 8008000000000000
++ fnmadd bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fnmadd bfe0000000000001, 80100094e0000359, 0010000000000001 => 8018004a70000100
++ fnmadd bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++
++ fnmadds 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
++ fnmadds 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fnmadds 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fnmadds 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++ fnmadds 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000
++ fnmadds 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fnmadds 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fnmadds 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++ fnmadds bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
++ fnmadds bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fnmadds bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fnmadds bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++
++ fnmsub 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
++ fnmsub 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fnmsub 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
++ fnmsub 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++ fnmsub 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0007ffb58ffffe00
++ fnmsub 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fnmsub 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 00180094e2b4a100
++ fnmsub 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++ fnmsub bfe0000000000001, 0010000000000001, 0010000000000001 => 0018000000000000
++ fnmsub bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fnmsub bfe0000000000001, 80100094e0000359, 0010000000000001 => 0007ffb58ffffe00
++ fnmsub bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++
++ fnmsubs 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
++ fnmsubs 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fnmsubs 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fnmsubs 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++ fnmsubs 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000
++ fnmsubs 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fnmsubs 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fnmsubs 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++ fnmsubs bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
++ fnmsubs bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fnmsubs bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fnmsubs bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++
++PPC floating point arith insns
++ with three args with flags update:
++ fsel. 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
++ fsel. 0010000000000001, 0010000000000001, bfe00094e0000359 => 0010000000000000
++ fsel. 0010000000000001, 80100094e0000359, 0010000000000001 => 80100094e0000300
++ fsel. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 80100094e0000300
++ fsel. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0010000000000000
++ fsel. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 0010000000000000
++ fsel. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80100094e0000300
++ fsel. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 80100094e0000300
++ fsel. bfe0000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
++ fsel. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fsel. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
++ fsel. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++
++ fmadd. 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
++ fmadd. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fmadd. 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
++ fmadd. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++ fmadd. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0018004a70000100
++ fmadd. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fmadd. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0007ff6b1d4b5e00
++ fmadd. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++ fmadd. bfe0000000000001, 0010000000000001, 0010000000000001 => 0008000000000000
++ fmadd. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fmadd. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0018004a70000100
++ fmadd. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++
++ fmadds. 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
++ fmadds. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fmadds. 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fmadds. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++ fmadds. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000
++ fmadds. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fmadds. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fmadds. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++ fmadds. bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
++ fmadds. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fmadds. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fmadds. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++
++ fmsub. 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000
++ fmsub. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fmsub. 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000
++ fmsub. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++ fmsub. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8007ffb58ffffe00
++ fmsub. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fmsub. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80180094e2b4a100
++ fmsub. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++ fmsub. bfe0000000000001, 0010000000000001, 0010000000000001 => 8018000000000000
++ fmsub. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fmsub. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8007ffb58ffffe00
++ fmsub. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++
++ fmsubs. 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
++ fmsubs. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fmsubs. 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fmsubs. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++ fmsubs. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000
++ fmsubs. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fmsubs. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fmsubs. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++ fmsubs. bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
++ fmsubs. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fmsubs. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fmsubs. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++
++ fnmadd. 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000
++ fnmadd. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fnmadd. 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000
++ fnmadd. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++ fnmadd. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8018004a70000100
++ fnmadd. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fnmadd. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8007ff6b1d4b5e00
++ fnmadd. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++ fnmadd. bfe0000000000001, 0010000000000001, 0010000000000001 => 8008000000000000
++ fnmadd. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fnmadd. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8018004a70000100
++ fnmadd. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++
++ fnmadds. 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
++ fnmadds. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fnmadds. 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fnmadds. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++ fnmadds. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000
++ fnmadds. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fnmadds. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fnmadds. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++ fnmadds. bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
++ fnmadds. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fnmadds. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fnmadds. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++
++ fnmsub. 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
++ fnmsub. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fnmsub. 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
++ fnmsub. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++ fnmsub. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0007ffb58ffffe00
++ fnmsub. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fnmsub. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 00180094e2b4a100
++ fnmsub. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++ fnmsub. bfe0000000000001, 0010000000000001, 0010000000000001 => 0018000000000000
++ fnmsub. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fnmsub. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0007ffb58ffffe00
++ fnmsub. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++
++ fnmsubs. 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
++ fnmsubs. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fnmsubs. 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fnmsubs. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++ fnmsubs. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000
++ fnmsubs. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fnmsubs. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fnmsubs. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++ fnmsubs. bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
++ fnmsubs. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fnmsubs. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fnmsubs. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++
++PPC floating point arith insns with two args:
++ fadd 0010000000000001, 0010000000000001 => 0020000000000001
++ fadd 0010000000000001, 80100094e0000359 => 80000094e0000358
++ fadd 0010000000000001, 7ff0000000000000 => 7ff0000000000000
++ fadd 0010000000000001, fff8000000000000 => fff8000000000000
++ fadd 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359
++ fadd 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359
++ fadd 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
++ fadd 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fadd bfe0000000000001, 0010000000000001 => bfe0000000000001
++ fadd bfe0000000000001, 80100094e0000359 => bfe0000000000001
++ fadd bfe0000000000001, 7ff0000000000000 => 7ff0000000000000
++ fadd bfe0000000000001, fff8000000000000 => fff8000000000000
++ fadd 8000000000000000, 0010000000000001 => 0010000000000001
++ fadd 8000000000000000, 80100094e0000359 => 80100094e0000359
++ fadd 8000000000000000, 7ff0000000000000 => 7ff0000000000000
++ fadd 8000000000000000, fff8000000000000 => fff8000000000000
++ fadd 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
++ fadd 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
++ fadd 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
++ fadd 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
++ fadd fff8000000000000, 0010000000000001 => fff8000000000000
++ fadd fff8000000000000, 80100094e0000359 => fff8000000000000
++ fadd fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fadd fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fadds 0010000000000001, 0010000000000001 => 0000000000000000
++ fadds 0010000000000001, 80100094e0000359 => 8000000000000000
++ fadds 0010000000000001, 7ff0000000000000 => 7ff0000000000000
++ fadds 0010000000000001, fff8000000000000 => fff8000000000000
++ fadds 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000
++ fadds 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000
++ fadds 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
++ fadds 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fadds bfe0000000000001, 0010000000000001 => bfe0000000000000
++ fadds bfe0000000000001, 80100094e0000359 => bfe0000000000000
++ fadds bfe0000000000001, 7ff0000000000000 => 7ff0000000000000
++ fadds bfe0000000000001, fff8000000000000 => fff8000000000000
++ fadds 8000000000000000, 0010000000000001 => 0000000000000000
++ fadds 8000000000000000, 80100094e0000359 => 8000000000000000
++ fadds 8000000000000000, 7ff0000000000000 => 7ff0000000000000
++ fadds 8000000000000000, fff8000000000000 => fff8000000000000
++ fadds 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
++ fadds 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
++ fadds 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
++ fadds 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
++ fadds fff8000000000000, 0010000000000001 => fff8000000000000
++ fadds fff8000000000000, 80100094e0000359 => fff8000000000000
++ fadds fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fadds fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fsub 0010000000000001, 0010000000000001 => 0000000000000000
++ fsub 0010000000000001, 80100094e0000359 => 0020004a700001ad
++ fsub 0010000000000001, 7ff0000000000000 => fff0000000000000
++ fsub 0010000000000001, fff8000000000000 => fff8000000000000
++ fsub 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359
++ fsub 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359
++ fsub 3fe00094e0000359, 7ff0000000000000 => fff0000000000000
++ fsub 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fsub bfe0000000000001, 0010000000000001 => bfe0000000000001
++ fsub bfe0000000000001, 80100094e0000359 => bfe0000000000001
++ fsub bfe0000000000001, 7ff0000000000000 => fff0000000000000
++ fsub bfe0000000000001, fff8000000000000 => fff8000000000000
++ fsub 8000000000000000, 0010000000000001 => 8010000000000001
++ fsub 8000000000000000, 80100094e0000359 => 00100094e0000359
++ fsub 8000000000000000, 7ff0000000000000 => fff0000000000000
++ fsub 8000000000000000, fff8000000000000 => fff8000000000000
++ fsub 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
++ fsub 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
++ fsub 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
++ fsub 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
++ fsub fff8000000000000, 0010000000000001 => fff8000000000000
++ fsub fff8000000000000, 80100094e0000359 => fff8000000000000
++ fsub fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fsub fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fsubs 0010000000000001, 0010000000000001 => 0000000000000000
++ fsubs 0010000000000001, 80100094e0000359 => 0000000000000000
++ fsubs 0010000000000001, 7ff0000000000000 => fff0000000000000
++ fsubs 0010000000000001, fff8000000000000 => fff8000000000000
++ fsubs 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000
++ fsubs 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000
++ fsubs 3fe00094e0000359, 7ff0000000000000 => fff0000000000000
++ fsubs 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fsubs bfe0000000000001, 0010000000000001 => bfe0000000000000
++ fsubs bfe0000000000001, 80100094e0000359 => bfe0000000000000
++ fsubs bfe0000000000001, 7ff0000000000000 => fff0000000000000
++ fsubs bfe0000000000001, fff8000000000000 => fff8000000000000
++ fsubs 8000000000000000, 0010000000000001 => 8000000000000000
++ fsubs 8000000000000000, 80100094e0000359 => 0000000000000000
++ fsubs 8000000000000000, 7ff0000000000000 => fff0000000000000
++ fsubs 8000000000000000, fff8000000000000 => fff8000000000000
++ fsubs 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
++ fsubs 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
++ fsubs 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
++ fsubs 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
++ fsubs fff8000000000000, 0010000000000001 => fff8000000000000
++ fsubs fff8000000000000, 80100094e0000359 => fff8000000000000
++ fsubs fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fsubs fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fmul 0010000000000001, 0010000000000001 => 0000000000000000
++ fmul 0010000000000001, 80100094e0000359 => 8000000000000000
++ fmul 0010000000000001, 7ff0000000000000 => 7ff0000000000000
++ fmul 0010000000000001, fff8000000000000 => fff8000000000000
++ fmul 3fe00094e0000359, 0010000000000001 => 0008004a700001ad
++ fmul 3fe00094e0000359, 80100094e0000359 => 80080094e2b4a179
++ fmul 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
++ fmul 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fmul bfe0000000000001, 0010000000000001 => 8008000000000001
++ fmul bfe0000000000001, 80100094e0000359 => 0008004a700001ad
++ fmul bfe0000000000001, 7ff0000000000000 => fff0000000000000
++ fmul bfe0000000000001, fff8000000000000 => fff8000000000000
++ fmul 8000000000000000, 0010000000000001 => 8000000000000000
++ fmul 8000000000000000, 80100094e0000359 => 0000000000000000
++ fmul 8000000000000000, 7ff0000000000000 => 7ff8000000000000
++ fmul 8000000000000000, fff8000000000000 => fff8000000000000
++ fmul 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
++ fmul 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
++ fmul 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
++ fmul 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
++ fmul fff8000000000000, 0010000000000001 => fff8000000000000
++ fmul fff8000000000000, 80100094e0000359 => fff8000000000000
++ fmul fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fmul fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fmuls 0010000000000001, 0010000000000001 => 0000000000000000
++ fmuls 0010000000000001, 80100094e0000359 => 8000000000000000
++ fmuls 0010000000000001, 7ff0000000000000 => 7ff0000000000000
++ fmuls 0010000000000001, fff8000000000000 => fff8000000000000
++ fmuls 3fe00094e0000359, 0010000000000001 => 0000000000000000
++ fmuls 3fe00094e0000359, 80100094e0000359 => 8000000000000000
++ fmuls 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
++ fmuls 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fmuls bfe0000000000001, 0010000000000001 => 8000000000000000
++ fmuls bfe0000000000001, 80100094e0000359 => 0000000000000000
++ fmuls bfe0000000000001, 7ff0000000000000 => fff0000000000000
++ fmuls bfe0000000000001, fff8000000000000 => fff8000000000000
++ fmuls 8000000000000000, 0010000000000001 => 8000000000000000
++ fmuls 8000000000000000, 80100094e0000359 => 0000000000000000
++ fmuls 8000000000000000, 7ff0000000000000 => 7ff8000000000000
++ fmuls 8000000000000000, fff8000000000000 => fff8000000000000
++ fmuls 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
++ fmuls 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
++ fmuls 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
++ fmuls 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
++ fmuls fff8000000000000, 0010000000000001 => fff8000000000000
++ fmuls fff8000000000000, 80100094e0000359 => fff8000000000000
++ fmuls fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fmuls fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fdiv 0010000000000001, 0010000000000001 => 3ff0000000000000
++ fdiv 0010000000000001, 80100094e0000359 => bfeffed64ad20d22
++ fdiv 0010000000000001, 7ff0000000000000 => 0000000000000000
++ fdiv 0010000000000001, fff8000000000000 => fff8000000000000
++ fdiv 3fe00094e0000359, 0010000000000001 => 7fc00094e0000358
++ fdiv 3fe00094e0000359, 80100094e0000359 => ffc0000000000000
++ fdiv 3fe00094e0000359, 7ff0000000000000 => 0000000000000000
++ fdiv 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fdiv bfe0000000000001, 0010000000000001 => ffc0000000000000
++ fdiv bfe0000000000001, 80100094e0000359 => 7fbffed64ad20d22
++ fdiv bfe0000000000001, 7ff0000000000000 => 8000000000000000
++ fdiv bfe0000000000001, fff8000000000000 => fff8000000000000
++ fdiv 8000000000000000, 0010000000000001 => 8000000000000000
++ fdiv 8000000000000000, 80100094e0000359 => 0000000000000000
++ fdiv 8000000000000000, 7ff0000000000000 => 8000000000000000
++ fdiv 8000000000000000, fff8000000000000 => fff8000000000000
++ fdiv 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
++ fdiv 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
++ fdiv 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
++ fdiv 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
++ fdiv fff8000000000000, 0010000000000001 => fff8000000000000
++ fdiv fff8000000000000, 80100094e0000359 => fff8000000000000
++ fdiv fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fdiv fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fdivs 0010000000000001, 0010000000000001 => 3ff0000000000000
++ fdivs 0010000000000001, 80100094e0000359 => bfeffed640000000
++ fdivs 0010000000000001, 7ff0000000000000 => 0000000000000000
++ fdivs 0010000000000001, fff8000000000000 => fff8000000000000
++ fdivs 3fe00094e0000359, 0010000000000001 => 7ff0000000000000
++ fdivs 3fe00094e0000359, 80100094e0000359 => fff0000000000000
++ fdivs 3fe00094e0000359, 7ff0000000000000 => 0000000000000000
++ fdivs 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fdivs bfe0000000000001, 0010000000000001 => fff0000000000000
++ fdivs bfe0000000000001, 80100094e0000359 => 7ff0000000000000
++ fdivs bfe0000000000001, 7ff0000000000000 => 8000000000000000
++ fdivs bfe0000000000001, fff8000000000000 => fff8000000000000
++ fdivs 8000000000000000, 0010000000000001 => 8000000000000000
++ fdivs 8000000000000000, 80100094e0000359 => 0000000000000000
++ fdivs 8000000000000000, 7ff0000000000000 => 8000000000000000
++ fdivs 8000000000000000, fff8000000000000 => fff8000000000000
++ fdivs 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
++ fdivs 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
++ fdivs 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
++ fdivs 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
++ fdivs fff8000000000000, 0010000000000001 => fff8000000000000
++ fdivs fff8000000000000, 80100094e0000359 => fff8000000000000
++ fdivs fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fdivs fff8000000000000, fff8000000000000 => fff8000000000000
++
++PPC floating point arith insns
++ with two args with flags update:
++ fadd. 0010000000000001, 0010000000000001 => 0020000000000001
++ fadd. 0010000000000001, 80100094e0000359 => 80000094e0000358
++ fadd. 0010000000000001, 7ff0000000000000 => 7ff0000000000000
++ fadd. 0010000000000001, fff8000000000000 => fff8000000000000
++ fadd. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359
++ fadd. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359
++ fadd. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
++ fadd. 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fadd. bfe0000000000001, 0010000000000001 => bfe0000000000001
++ fadd. bfe0000000000001, 80100094e0000359 => bfe0000000000001
++ fadd. bfe0000000000001, 7ff0000000000000 => 7ff0000000000000
++ fadd. bfe0000000000001, fff8000000000000 => fff8000000000000
++ fadd. 8000000000000000, 0010000000000001 => 0010000000000001
++ fadd. 8000000000000000, 80100094e0000359 => 80100094e0000359
++ fadd. 8000000000000000, 7ff0000000000000 => 7ff0000000000000
++ fadd. 8000000000000000, fff8000000000000 => fff8000000000000
++ fadd. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
++ fadd. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
++ fadd. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
++ fadd. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
++ fadd. fff8000000000000, 0010000000000001 => fff8000000000000
++ fadd. fff8000000000000, 80100094e0000359 => fff8000000000000
++ fadd. fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fadd. fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fadds. 0010000000000001, 0010000000000001 => 0000000000000000
++ fadds. 0010000000000001, 80100094e0000359 => 8000000000000000
++ fadds. 0010000000000001, 7ff0000000000000 => 7ff0000000000000
++ fadds. 0010000000000001, fff8000000000000 => fff8000000000000
++ fadds. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000
++ fadds. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000
++ fadds. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
++ fadds. 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fadds. bfe0000000000001, 0010000000000001 => bfe0000000000000
++ fadds. bfe0000000000001, 80100094e0000359 => bfe0000000000000
++ fadds. bfe0000000000001, 7ff0000000000000 => 7ff0000000000000
++ fadds. bfe0000000000001, fff8000000000000 => fff8000000000000
++ fadds. 8000000000000000, 0010000000000001 => 0000000000000000
++ fadds. 8000000000000000, 80100094e0000359 => 8000000000000000
++ fadds. 8000000000000000, 7ff0000000000000 => 7ff0000000000000
++ fadds. 8000000000000000, fff8000000000000 => fff8000000000000
++ fadds. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
++ fadds. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
++ fadds. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
++ fadds. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
++ fadds. fff8000000000000, 0010000000000001 => fff8000000000000
++ fadds. fff8000000000000, 80100094e0000359 => fff8000000000000
++ fadds. fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fadds. fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fsub. 0010000000000001, 0010000000000001 => 0000000000000000
++ fsub. 0010000000000001, 80100094e0000359 => 0020004a700001ad
++ fsub. 0010000000000001, 7ff0000000000000 => fff0000000000000
++ fsub. 0010000000000001, fff8000000000000 => fff8000000000000
++ fsub. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359
++ fsub. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359
++ fsub. 3fe00094e0000359, 7ff0000000000000 => fff0000000000000
++ fsub. 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fsub. bfe0000000000001, 0010000000000001 => bfe0000000000001
++ fsub. bfe0000000000001, 80100094e0000359 => bfe0000000000001
++ fsub. bfe0000000000001, 7ff0000000000000 => fff0000000000000
++ fsub. bfe0000000000001, fff8000000000000 => fff8000000000000
++ fsub. 8000000000000000, 0010000000000001 => 8010000000000001
++ fsub. 8000000000000000, 80100094e0000359 => 00100094e0000359
++ fsub. 8000000000000000, 7ff0000000000000 => fff0000000000000
++ fsub. 8000000000000000, fff8000000000000 => fff8000000000000
++ fsub. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
++ fsub. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
++ fsub. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
++ fsub. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
++ fsub. fff8000000000000, 0010000000000001 => fff8000000000000
++ fsub. fff8000000000000, 80100094e0000359 => fff8000000000000
++ fsub. fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fsub. fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fsubs. 0010000000000001, 0010000000000001 => 0000000000000000
++ fsubs. 0010000000000001, 80100094e0000359 => 0000000000000000
++ fsubs. 0010000000000001, 7ff0000000000000 => fff0000000000000
++ fsubs. 0010000000000001, fff8000000000000 => fff8000000000000
++ fsubs. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000
++ fsubs. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000
++ fsubs. 3fe00094e0000359, 7ff0000000000000 => fff0000000000000
++ fsubs. 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fsubs. bfe0000000000001, 0010000000000001 => bfe0000000000000
++ fsubs. bfe0000000000001, 80100094e0000359 => bfe0000000000000
++ fsubs. bfe0000000000001, 7ff0000000000000 => fff0000000000000
++ fsubs. bfe0000000000001, fff8000000000000 => fff8000000000000
++ fsubs. 8000000000000000, 0010000000000001 => 8000000000000000
++ fsubs. 8000000000000000, 80100094e0000359 => 0000000000000000
++ fsubs. 8000000000000000, 7ff0000000000000 => fff0000000000000
++ fsubs. 8000000000000000, fff8000000000000 => fff8000000000000
++ fsubs. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
++ fsubs. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
++ fsubs. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
++ fsubs. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
++ fsubs. fff8000000000000, 0010000000000001 => fff8000000000000
++ fsubs. fff8000000000000, 80100094e0000359 => fff8000000000000
++ fsubs. fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fsubs. fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fmul. 0010000000000001, 0010000000000001 => 0000000000000000
++ fmul. 0010000000000001, 80100094e0000359 => 8000000000000000
++ fmul. 0010000000000001, 7ff0000000000000 => 7ff0000000000000
++ fmul. 0010000000000001, fff8000000000000 => fff8000000000000
++ fmul. 3fe00094e0000359, 0010000000000001 => 0008004a700001ad
++ fmul. 3fe00094e0000359, 80100094e0000359 => 80080094e2b4a179
++ fmul. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
++ fmul. 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fmul. bfe0000000000001, 0010000000000001 => 8008000000000001
++ fmul. bfe0000000000001, 80100094e0000359 => 0008004a700001ad
++ fmul. bfe0000000000001, 7ff0000000000000 => fff0000000000000
++ fmul. bfe0000000000001, fff8000000000000 => fff8000000000000
++ fmul. 8000000000000000, 0010000000000001 => 8000000000000000
++ fmul. 8000000000000000, 80100094e0000359 => 0000000000000000
++ fmul. 8000000000000000, 7ff0000000000000 => 7ff8000000000000
++ fmul. 8000000000000000, fff8000000000000 => fff8000000000000
++ fmul. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
++ fmul. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
++ fmul. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
++ fmul. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
++ fmul. fff8000000000000, 0010000000000001 => fff8000000000000
++ fmul. fff8000000000000, 80100094e0000359 => fff8000000000000
++ fmul. fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fmul. fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fmuls. 0010000000000001, 0010000000000001 => 0000000000000000
++ fmuls. 0010000000000001, 80100094e0000359 => 8000000000000000
++ fmuls. 0010000000000001, 7ff0000000000000 => 7ff0000000000000
++ fmuls. 0010000000000001, fff8000000000000 => fff8000000000000
++ fmuls. 3fe00094e0000359, 0010000000000001 => 0000000000000000
++ fmuls. 3fe00094e0000359, 80100094e0000359 => 8000000000000000
++ fmuls. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
++ fmuls. 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fmuls. bfe0000000000001, 0010000000000001 => 8000000000000000
++ fmuls. bfe0000000000001, 80100094e0000359 => 0000000000000000
++ fmuls. bfe0000000000001, 7ff0000000000000 => fff0000000000000
++ fmuls. bfe0000000000001, fff8000000000000 => fff8000000000000
++ fmuls. 8000000000000000, 0010000000000001 => 8000000000000000
++ fmuls. 8000000000000000, 80100094e0000359 => 0000000000000000
++ fmuls. 8000000000000000, 7ff0000000000000 => 7ff8000000000000
++ fmuls. 8000000000000000, fff8000000000000 => fff8000000000000
++ fmuls. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
++ fmuls. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
++ fmuls. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
++ fmuls. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
++ fmuls. fff8000000000000, 0010000000000001 => fff8000000000000
++ fmuls. fff8000000000000, 80100094e0000359 => fff8000000000000
++ fmuls. fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fmuls. fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fdiv. 0010000000000001, 0010000000000001 => 3ff0000000000000
++ fdiv. 0010000000000001, 80100094e0000359 => bfeffed64ad20d22
++ fdiv. 0010000000000001, 7ff0000000000000 => 0000000000000000
++ fdiv. 0010000000000001, fff8000000000000 => fff8000000000000
++ fdiv. 3fe00094e0000359, 0010000000000001 => 7fc00094e0000358
++ fdiv. 3fe00094e0000359, 80100094e0000359 => ffc0000000000000
++ fdiv. 3fe00094e0000359, 7ff0000000000000 => 0000000000000000
++ fdiv. 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fdiv. bfe0000000000001, 0010000000000001 => ffc0000000000000
++ fdiv. bfe0000000000001, 80100094e0000359 => 7fbffed64ad20d22
++ fdiv. bfe0000000000001, 7ff0000000000000 => 8000000000000000
++ fdiv. bfe0000000000001, fff8000000000000 => fff8000000000000
++ fdiv. 8000000000000000, 0010000000000001 => 8000000000000000
++ fdiv. 8000000000000000, 80100094e0000359 => 0000000000000000
++ fdiv. 8000000000000000, 7ff0000000000000 => 8000000000000000
++ fdiv. 8000000000000000, fff8000000000000 => fff8000000000000
++ fdiv. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
++ fdiv. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
++ fdiv. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
++ fdiv. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
++ fdiv. fff8000000000000, 0010000000000001 => fff8000000000000
++ fdiv. fff8000000000000, 80100094e0000359 => fff8000000000000
++ fdiv. fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fdiv. fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fdivs. 0010000000000001, 0010000000000001 => 3ff0000000000000
++ fdivs. 0010000000000001, 80100094e0000359 => bfeffed640000000
++ fdivs. 0010000000000001, 7ff0000000000000 => 0000000000000000
++ fdivs. 0010000000000001, fff8000000000000 => fff8000000000000
++ fdivs. 3fe00094e0000359, 0010000000000001 => 7ff0000000000000
++ fdivs. 3fe00094e0000359, 80100094e0000359 => fff0000000000000
++ fdivs. 3fe00094e0000359, 7ff0000000000000 => 0000000000000000
++ fdivs. 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fdivs. bfe0000000000001, 0010000000000001 => fff0000000000000
++ fdivs. bfe0000000000001, 80100094e0000359 => 7ff0000000000000
++ fdivs. bfe0000000000001, 7ff0000000000000 => 8000000000000000
++ fdivs. bfe0000000000001, fff8000000000000 => fff8000000000000
++ fdivs. 8000000000000000, 0010000000000001 => 8000000000000000
++ fdivs. 8000000000000000, 80100094e0000359 => 0000000000000000
++ fdivs. 8000000000000000, 7ff0000000000000 => 8000000000000000
++ fdivs. 8000000000000000, fff8000000000000 => fff8000000000000
++ fdivs. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
++ fdivs. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
++ fdivs. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
++ fdivs. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
++ fdivs. fff8000000000000, 0010000000000001 => fff8000000000000
++ fdivs. fff8000000000000, 80100094e0000359 => fff8000000000000
++ fdivs. fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fdivs. fff8000000000000, fff8000000000000 => fff8000000000000
++
++PPC floating point compare insns (two args):
++ fcmpo 0010000000000001, 0010000000000001 => fff8000000000000
++ fcmpo 0010000000000001, 80100094e0000359 => fff8000000000000
++ fcmpo 0010000000000001, 7ff0000000000000 => fff8000000000000
++ fcmpo 0010000000000001, fff8000000000000 => fff8000000000000
++ fcmpo 3fe00094e0000359, 0010000000000001 => fff8000000000000
++ fcmpo 3fe00094e0000359, 80100094e0000359 => fff8000000000000
++ fcmpo 3fe00094e0000359, 7ff0000000000000 => fff8000000000000
++ fcmpo 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fcmpo bfe0000000000001, 0010000000000001 => fff8000000000000
++ fcmpo bfe0000000000001, 80100094e0000359 => fff8000000000000
++ fcmpo bfe0000000000001, 7ff0000000000000 => fff8000000000000
++ fcmpo bfe0000000000001, fff8000000000000 => fff8000000000000
++ fcmpo 8000000000000000, 0010000000000001 => fff8000000000000
++ fcmpo 8000000000000000, 80100094e0000359 => fff8000000000000
++ fcmpo 8000000000000000, 7ff0000000000000 => fff8000000000000
++ fcmpo 8000000000000000, fff8000000000000 => fff8000000000000
++ fcmpo 7ff7ffffffffffff, 0010000000000001 => fff8000000000000
++ fcmpo 7ff7ffffffffffff, 80100094e0000359 => fff8000000000000
++ fcmpo 7ff7ffffffffffff, 7ff0000000000000 => fff8000000000000
++ fcmpo 7ff7ffffffffffff, fff8000000000000 => fff8000000000000
++ fcmpo fff8000000000000, 0010000000000001 => fff8000000000000
++ fcmpo fff8000000000000, 80100094e0000359 => fff8000000000000
++ fcmpo fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fcmpo fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fcmpu 0010000000000001, 0010000000000001 => fff8000000000000
++ fcmpu 0010000000000001, 80100094e0000359 => fff8000000000000
++ fcmpu 0010000000000001, 7ff0000000000000 => fff8000000000000
++ fcmpu 0010000000000001, fff8000000000000 => fff8000000000000
++ fcmpu 3fe00094e0000359, 0010000000000001 => fff8000000000000
++ fcmpu 3fe00094e0000359, 80100094e0000359 => fff8000000000000
++ fcmpu 3fe00094e0000359, 7ff0000000000000 => fff8000000000000
++ fcmpu 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fcmpu bfe0000000000001, 0010000000000001 => fff8000000000000
++ fcmpu bfe0000000000001, 80100094e0000359 => fff8000000000000
++ fcmpu bfe0000000000001, 7ff0000000000000 => fff8000000000000
++ fcmpu bfe0000000000001, fff8000000000000 => fff8000000000000
++ fcmpu 8000000000000000, 0010000000000001 => fff8000000000000
++ fcmpu 8000000000000000, 80100094e0000359 => fff8000000000000
++ fcmpu 8000000000000000, 7ff0000000000000 => fff8000000000000
++ fcmpu 8000000000000000, fff8000000000000 => fff8000000000000
++ fcmpu 7ff7ffffffffffff, 0010000000000001 => fff8000000000000
++ fcmpu 7ff7ffffffffffff, 80100094e0000359 => fff8000000000000
++ fcmpu 7ff7ffffffffffff, 7ff0000000000000 => fff8000000000000
++ fcmpu 7ff7ffffffffffff, fff8000000000000 => fff8000000000000
++ fcmpu fff8000000000000, 0010000000000001 => fff8000000000000
++ fcmpu fff8000000000000, 80100094e0000359 => fff8000000000000
++ fcmpu fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fcmpu fff8000000000000, fff8000000000000 => fff8000000000000
++
++PPC floating point arith insns with one arg:
++ fres 0010000000000001 => 7ff0000000000000
++ fres 00100094e0000359 => 7ff0000000000000
++ fres 3fe0000000000001 => 4000000000000000
++ fres 3fe00094e0000359 => 3ffff00000000000
++ fres 8010000000000001 => fff0000000000000
++ fres 80100094e0000359 => fff0000000000000
++ fres bfe0000000000001 => c000000000000000
++ fres bfe00094e0000359 => bffff00000000000
++ fres 0000000000000000 => 7ff0000000000000
++ fres 8000000000000000 => fff0000000000000
++ fres 7ff0000000000000 => 0000000000000000
++ fres fff0000000000000 => 8000000000000000
++ fres 7ff7ffffffffffff => 7ffff00000000000
++ fres fff7ffffffffffff => fffff00000000000
++ fres 7ff8000000000000 => 7ff8000000000000
++ fres fff8000000000000 => fff8000000000000
++
++ frsqrte 0010000000000001 => 5fdf000000000000
++ frsqrte 00100094e0000359 => 5fdf000000000000
++ frsqrte 3fe0000000000001 => 3ff6000000000000
++ frsqrte 3fe00094e0000359 => 3ff6000000000000
++ frsqrte 8010000000000001 => 7ff8000000000000
++ frsqrte 80100094e0000359 => 7ff8000000000000
++ frsqrte bfe0000000000001 => 7ff8000000000000
++ frsqrte bfe00094e0000359 => 7ff8000000000000
++ frsqrte 0000000000000000 => 7ff0000000000000
++ frsqrte 8000000000000000 => fff0000000000000
++ frsqrte 7ff0000000000000 => 0000000000000000
++ frsqrte fff0000000000000 => 7ff8000000000000
++ frsqrte 7ff7ffffffffffff => 7fff000000000000
++ frsqrte fff7ffffffffffff => ffff000000000000
++ frsqrte 7ff8000000000000 => 7ff8000000000000
++ frsqrte fff8000000000000 => fff8000000000000
++
++ frsp 0010000000000001 => 0000000000000000
++ frsp 00100094e0000359 => 0000000000000000
++ frsp 3fe0000000000001 => 3fe0000000000000
++ frsp 3fe00094e0000359 => 3fe00094e0000000
++ frsp 8010000000000001 => 8000000000000000
++ frsp 80100094e0000359 => 8000000000000000
++ frsp bfe0000000000001 => bfe0000000000000
++ frsp bfe00094e0000359 => bfe00094e0000000
++ frsp 0000000000000000 => 0000000000000000
++ frsp 8000000000000000 => 8000000000000000
++ frsp 7ff0000000000000 => 7ff0000000000000
++ frsp fff0000000000000 => fff0000000000000
++ frsp 7ff7ffffffffffff => 7fffffffe0000000
++ frsp fff7ffffffffffff => ffffffffe0000000
++ frsp 7ff8000000000000 => 7ff8000000000000
++ frsp fff8000000000000 => fff8000000000000
++
++ fctiw 0010000000000001 => 0000000000000000
++ fctiw 00100094e0000359 => 0000000000000000
++ fctiw 3fe0000000000001 => 0000000000000001
++ fctiw 3fe00094e0000359 => 0000000000000001
++ fctiw 8010000000000001 => 0000000000000000
++ fctiw 80100094e0000359 => 0000000000000000
++ fctiw bfe0000000000001 => 00000000ffffffff
++ fctiw bfe00094e0000359 => 00000000ffffffff
++ fctiw 0000000000000000 => 0000000000000000
++ fctiw 8000000000000000 => 0000000000000000
++ fctiw 7ff0000000000000 => 000000007fffffff
++ fctiw fff0000000000000 => 0000000080000000
++ fctiw 7ff7ffffffffffff => 0000000080000000
++ fctiw fff7ffffffffffff => 0000000080000000
++ fctiw 7ff8000000000000 => 0000000080000000
++ fctiw fff8000000000000 => 0000000080000000
++
++ fctiwz 0010000000000001 => 0000000000000000
++ fctiwz 00100094e0000359 => 0000000000000000
++ fctiwz 3fe0000000000001 => 0000000000000000
++ fctiwz 3fe00094e0000359 => 0000000000000000
++ fctiwz 8010000000000001 => 0000000000000000
++ fctiwz 80100094e0000359 => 0000000000000000
++ fctiwz bfe0000000000001 => 0000000000000000
++ fctiwz bfe00094e0000359 => 0000000000000000
++ fctiwz 0000000000000000 => 0000000000000000
++ fctiwz 8000000000000000 => 0000000000000000
++ fctiwz 7ff0000000000000 => 000000007fffffff
++ fctiwz fff0000000000000 => 0000000080000000
++ fctiwz 7ff7ffffffffffff => 0000000080000000
++ fctiwz fff7ffffffffffff => 0000000080000000
++ fctiwz 7ff8000000000000 => 0000000080000000
++ fctiwz fff8000000000000 => 0000000080000000
++
++ fmr 0010000000000001 => 0010000000000001
++ fmr 00100094e0000359 => 00100094e0000359
++ fmr 3fe0000000000001 => 3fe0000000000001
++ fmr 3fe00094e0000359 => 3fe00094e0000359
++ fmr 8010000000000001 => 8010000000000001
++ fmr 80100094e0000359 => 80100094e0000359
++ fmr bfe0000000000001 => bfe0000000000001
++ fmr bfe00094e0000359 => bfe00094e0000359
++ fmr 0000000000000000 => 0000000000000000
++ fmr 8000000000000000 => 8000000000000000
++ fmr 7ff0000000000000 => 7ff0000000000000
++ fmr fff0000000000000 => fff0000000000000
++ fmr 7ff7ffffffffffff => 7ff7ffffffffffff
++ fmr fff7ffffffffffff => fff7ffffffffffff
++ fmr 7ff8000000000000 => 7ff8000000000000
++ fmr fff8000000000000 => fff8000000000000
++
++ fneg 0010000000000001 => 8010000000000001
++ fneg 00100094e0000359 => 80100094e0000359
++ fneg 3fe0000000000001 => bfe0000000000001
++ fneg 3fe00094e0000359 => bfe00094e0000359
++ fneg 8010000000000001 => 0010000000000001
++ fneg 80100094e0000359 => 00100094e0000359
++ fneg bfe0000000000001 => 3fe0000000000001
++ fneg bfe00094e0000359 => 3fe00094e0000359
++ fneg 0000000000000000 => 8000000000000000
++ fneg 8000000000000000 => 0000000000000000
++ fneg 7ff0000000000000 => fff0000000000000
++ fneg fff0000000000000 => 7ff0000000000000
++ fneg 7ff7ffffffffffff => fff7ffffffffffff
++ fneg fff7ffffffffffff => 7ff7ffffffffffff
++ fneg 7ff8000000000000 => fff8000000000000
++ fneg fff8000000000000 => 7ff8000000000000
++
++ fabs 0010000000000001 => 0010000000000001
++ fabs 00100094e0000359 => 00100094e0000359
++ fabs 3fe0000000000001 => 3fe0000000000001
++ fabs 3fe00094e0000359 => 3fe00094e0000359
++ fabs 8010000000000001 => 0010000000000001
++ fabs 80100094e0000359 => 00100094e0000359
++ fabs bfe0000000000001 => 3fe0000000000001
++ fabs bfe00094e0000359 => 3fe00094e0000359
++ fabs 0000000000000000 => 0000000000000000
++ fabs 8000000000000000 => 0000000000000000
++ fabs 7ff0000000000000 => 7ff0000000000000
++ fabs fff0000000000000 => 7ff0000000000000
++ fabs 7ff7ffffffffffff => 7ff7ffffffffffff
++ fabs fff7ffffffffffff => 7ff7ffffffffffff
++ fabs 7ff8000000000000 => 7ff8000000000000
++ fabs fff8000000000000 => 7ff8000000000000
++
++ fnabs 0010000000000001 => 8010000000000001
++ fnabs 00100094e0000359 => 80100094e0000359
++ fnabs 3fe0000000000001 => bfe0000000000001
++ fnabs 3fe00094e0000359 => bfe00094e0000359
++ fnabs 8010000000000001 => 8010000000000001
++ fnabs 80100094e0000359 => 80100094e0000359
++ fnabs bfe0000000000001 => bfe0000000000001
++ fnabs bfe00094e0000359 => bfe00094e0000359
++ fnabs 0000000000000000 => 8000000000000000
++ fnabs 8000000000000000 => 8000000000000000
++ fnabs 7ff0000000000000 => fff0000000000000
++ fnabs fff0000000000000 => fff0000000000000
++ fnabs 7ff7ffffffffffff => fff7ffffffffffff
++ fnabs fff7ffffffffffff => fff7ffffffffffff
++ fnabs 7ff8000000000000 => fff8000000000000
++ fnabs fff8000000000000 => fff8000000000000
++
++ fsqrt 0010000000000001 => 2000000000000000
++ fsqrt 00100094e0000359 => 2000004a6f52dd4a
++ fsqrt 3fe0000000000001 => 3fe6a09e667f3bcd
++ fsqrt 3fe00094e0000359 => 3fe6a107aacb50df
++ fsqrt 8010000000000001 => 7ff8000000000000
++ fsqrt 80100094e0000359 => 7ff8000000000000
++ fsqrt bfe0000000000001 => 7ff8000000000000
++ fsqrt bfe00094e0000359 => 7ff8000000000000
++ fsqrt 0000000000000000 => 0000000000000000
++ fsqrt 8000000000000000 => 8000000000000000
++ fsqrt 7ff0000000000000 => 7ff0000000000000
++ fsqrt fff0000000000000 => 7ff8000000000000
++ fsqrt 7ff7ffffffffffff => 7fffffffffffffff
++ fsqrt fff7ffffffffffff => ffffffffffffffff
++ fsqrt 7ff8000000000000 => 7ff8000000000000
++ fsqrt fff8000000000000 => fff8000000000000
++
++ fcfid 0010000000000001 => 4330000000000001
++ fcfid 00100094e0000359 => 43300094e0000359
++ fcfid 3fe0000000000001 => 43cff00000000000
++ fcfid 3fe00094e0000359 => 43cff0004a700002
++ fcfid 8010000000000001 => c3dffc0000000000
++ fcfid 80100094e0000359 => c3dffbffdac7ffff
++ fcfid bfe0000000000001 => c3d0080000000000
++ fcfid bfe00094e0000359 => c3d007ffdac7ffff
++ fcfid 0000000000000000 => 0000000000000000
++ fcfid 8000000000000000 => c3e0000000000000
++ fcfid 7ff0000000000000 => 43dffc0000000000
++ fcfid fff0000000000000 => c330000000000000
++ fcfid 7ff7ffffffffffff => 43dffe0000000000
++ fcfid fff7ffffffffffff => c320000000000002
++ fcfid 7ff8000000000000 => 43dffe0000000000
++ fcfid fff8000000000000 => c320000000000000
++
++ fctid 0010000000000001 => 0000000000000000
++ fctid 00100094e0000359 => 0000000000000000
++ fctid 3fe0000000000001 => 0000000000000001
++ fctid 3fe00094e0000359 => 0000000000000001
++ fctid 8010000000000001 => 0000000000000000
++ fctid 80100094e0000359 => 0000000000000000
++ fctid bfe0000000000001 => ffffffffffffffff
++ fctid bfe00094e0000359 => ffffffffffffffff
++ fctid 0000000000000000 => 0000000000000000
++ fctid 8000000000000000 => 0000000000000000
++ fctid 7ff0000000000000 => 7fffffffffffffff
++ fctid fff0000000000000 => 8000000000000000
++ fctid 7ff7ffffffffffff => 8000000000000000
++ fctid fff7ffffffffffff => 8000000000000000
++ fctid 7ff8000000000000 => 8000000000000000
++ fctid fff8000000000000 => 8000000000000000
++
++ fctidz 0010000000000001 => 0000000000000000
++ fctidz 00100094e0000359 => 0000000000000000
++ fctidz 3fe0000000000001 => 0000000000000000
++ fctidz 3fe00094e0000359 => 0000000000000000
++ fctidz 8010000000000001 => 0000000000000000
++ fctidz 80100094e0000359 => 0000000000000000
++ fctidz bfe0000000000001 => 0000000000000000
++ fctidz bfe00094e0000359 => 0000000000000000
++ fctidz 0000000000000000 => 0000000000000000
++ fctidz 8000000000000000 => 0000000000000000
++ fctidz 7ff0000000000000 => 7fffffffffffffff
++ fctidz fff0000000000000 => 8000000000000000
++ fctidz 7ff7ffffffffffff => 8000000000000000
++ fctidz fff7ffffffffffff => 8000000000000000
++ fctidz 7ff8000000000000 => 8000000000000000
++ fctidz fff8000000000000 => 8000000000000000
++
++PPC floating point arith insns
++ with one arg with flags update:
++ fres. 0010000000000001 => 7ff0000000000000
++ fres. 00100094e0000359 => 7ff0000000000000
++ fres. 3fe0000000000001 => 4000000000000000
++ fres. 3fe00094e0000359 => 3ffff00000000000
++ fres. 8010000000000001 => fff0000000000000
++ fres. 80100094e0000359 => fff0000000000000
++ fres. bfe0000000000001 => c000000000000000
++ fres. bfe00094e0000359 => bffff00000000000
++ fres. 0000000000000000 => 7ff0000000000000
++ fres. 8000000000000000 => fff0000000000000
++ fres. 7ff0000000000000 => 0000000000000000
++ fres. fff0000000000000 => 8000000000000000
++ fres. 7ff7ffffffffffff => 7ffff00000000000
++ fres. fff7ffffffffffff => fffff00000000000
++ fres. 7ff8000000000000 => 7ff8000000000000
++ fres. fff8000000000000 => fff8000000000000
++
++ frsqrte. 0010000000000001 => 5fdf000000000000
++ frsqrte. 00100094e0000359 => 5fdf000000000000
++ frsqrte. 3fe0000000000001 => 3ff6000000000000
++ frsqrte. 3fe00094e0000359 => 3ff6000000000000
++ frsqrte. 8010000000000001 => 7ff8000000000000
++ frsqrte. 80100094e0000359 => 7ff8000000000000
++ frsqrte. bfe0000000000001 => 7ff8000000000000
++ frsqrte. bfe00094e0000359 => 7ff8000000000000
++ frsqrte. 0000000000000000 => 7ff0000000000000
++ frsqrte. 8000000000000000 => fff0000000000000
++ frsqrte. 7ff0000000000000 => 0000000000000000
++ frsqrte. fff0000000000000 => 7ff8000000000000
++ frsqrte. 7ff7ffffffffffff => 7fff000000000000
++ frsqrte. fff7ffffffffffff => ffff000000000000
++ frsqrte. 7ff8000000000000 => 7ff8000000000000
++ frsqrte. fff8000000000000 => fff8000000000000
++
++ frsp. 0010000000000001 => 0000000000000000
++ frsp. 00100094e0000359 => 0000000000000000
++ frsp. 3fe0000000000001 => 3fe0000000000000
++ frsp. 3fe00094e0000359 => 3fe00094e0000000
++ frsp. 8010000000000001 => 8000000000000000
++ frsp. 80100094e0000359 => 8000000000000000
++ frsp. bfe0000000000001 => bfe0000000000000
++ frsp. bfe00094e0000359 => bfe00094e0000000
++ frsp. 0000000000000000 => 0000000000000000
++ frsp. 8000000000000000 => 8000000000000000
++ frsp. 7ff0000000000000 => 7ff0000000000000
++ frsp. fff0000000000000 => fff0000000000000
++ frsp. 7ff7ffffffffffff => 7fffffffe0000000
++ frsp. fff7ffffffffffff => ffffffffe0000000
++ frsp. 7ff8000000000000 => 7ff8000000000000
++ frsp. fff8000000000000 => fff8000000000000
++
++ fctiw. 0010000000000001 => 0000000000000000
++ fctiw. 00100094e0000359 => 0000000000000000
++ fctiw. 3fe0000000000001 => 0000000000000001
++ fctiw. 3fe00094e0000359 => 0000000000000001
++ fctiw. 8010000000000001 => 0000000000000000
++ fctiw. 80100094e0000359 => 0000000000000000
++ fctiw. bfe0000000000001 => 00000000ffffffff
++ fctiw. bfe00094e0000359 => 00000000ffffffff
++ fctiw. 0000000000000000 => 0000000000000000
++ fctiw. 8000000000000000 => 0000000000000000
++ fctiw. 7ff0000000000000 => 000000007fffffff
++ fctiw. fff0000000000000 => 0000000080000000
++ fctiw. 7ff7ffffffffffff => 0000000080000000
++ fctiw. fff7ffffffffffff => 0000000080000000
++ fctiw. 7ff8000000000000 => 0000000080000000
++ fctiw. fff8000000000000 => 0000000080000000
++
++ fctiwz. 0010000000000001 => 0000000000000000
++ fctiwz. 00100094e0000359 => 0000000000000000
++ fctiwz. 3fe0000000000001 => 0000000000000000
++ fctiwz. 3fe00094e0000359 => 0000000000000000
++ fctiwz. 8010000000000001 => 0000000000000000
++ fctiwz. 80100094e0000359 => 0000000000000000
++ fctiwz. bfe0000000000001 => 0000000000000000
++ fctiwz. bfe00094e0000359 => 0000000000000000
++ fctiwz. 0000000000000000 => 0000000000000000
++ fctiwz. 8000000000000000 => 0000000000000000
++ fctiwz. 7ff0000000000000 => 000000007fffffff
++ fctiwz. fff0000000000000 => 0000000080000000
++ fctiwz. 7ff7ffffffffffff => 0000000080000000
++ fctiwz. fff7ffffffffffff => 0000000080000000
++ fctiwz. 7ff8000000000000 => 0000000080000000
++ fctiwz. fff8000000000000 => 0000000080000000
++
++ fmr. 0010000000000001 => 0010000000000001
++ fmr. 00100094e0000359 => 00100094e0000359
++ fmr. 3fe0000000000001 => 3fe0000000000001
++ fmr. 3fe00094e0000359 => 3fe00094e0000359
++ fmr. 8010000000000001 => 8010000000000001
++ fmr. 80100094e0000359 => 80100094e0000359
++ fmr. bfe0000000000001 => bfe0000000000001
++ fmr. bfe00094e0000359 => bfe00094e0000359
++ fmr. 0000000000000000 => 0000000000000000
++ fmr. 8000000000000000 => 8000000000000000
++ fmr. 7ff0000000000000 => 7ff0000000000000
++ fmr. fff0000000000000 => fff0000000000000
++ fmr. 7ff7ffffffffffff => 7ff7ffffffffffff
++ fmr. fff7ffffffffffff => fff7ffffffffffff
++ fmr. 7ff8000000000000 => 7ff8000000000000
++ fmr. fff8000000000000 => fff8000000000000
++
++ fneg. 0010000000000001 => 8010000000000001
++ fneg. 00100094e0000359 => 80100094e0000359
++ fneg. 3fe0000000000001 => bfe0000000000001
++ fneg. 3fe00094e0000359 => bfe00094e0000359
++ fneg. 8010000000000001 => 0010000000000001
++ fneg. 80100094e0000359 => 00100094e0000359
++ fneg. bfe0000000000001 => 3fe0000000000001
++ fneg. bfe00094e0000359 => 3fe00094e0000359
++ fneg. 0000000000000000 => 8000000000000000
++ fneg. 8000000000000000 => 0000000000000000
++ fneg. 7ff0000000000000 => fff0000000000000
++ fneg. fff0000000000000 => 7ff0000000000000
++ fneg. 7ff7ffffffffffff => fff7ffffffffffff
++ fneg. fff7ffffffffffff => 7ff7ffffffffffff
++ fneg. 7ff8000000000000 => fff8000000000000
++ fneg. fff8000000000000 => 7ff8000000000000
++
++ fabs. 0010000000000001 => 0010000000000001
++ fabs. 00100094e0000359 => 00100094e0000359
++ fabs. 3fe0000000000001 => 3fe0000000000001
++ fabs. 3fe00094e0000359 => 3fe00094e0000359
++ fabs. 8010000000000001 => 0010000000000001
++ fabs. 80100094e0000359 => 00100094e0000359
++ fabs. bfe0000000000001 => 3fe0000000000001
++ fabs. bfe00094e0000359 => 3fe00094e0000359
++ fabs. 0000000000000000 => 0000000000000000
++ fabs. 8000000000000000 => 0000000000000000
++ fabs. 7ff0000000000000 => 7ff0000000000000
++ fabs. fff0000000000000 => 7ff0000000000000
++ fabs. 7ff7ffffffffffff => 7ff7ffffffffffff
++ fabs. fff7ffffffffffff => 7ff7ffffffffffff
++ fabs. 7ff8000000000000 => 7ff8000000000000
++ fabs. fff8000000000000 => 7ff8000000000000
++
++ fnabs. 0010000000000001 => 8010000000000001
++ fnabs. 00100094e0000359 => 80100094e0000359
++ fnabs. 3fe0000000000001 => bfe0000000000001
++ fnabs. 3fe00094e0000359 => bfe00094e0000359
++ fnabs. 8010000000000001 => 8010000000000001
++ fnabs. 80100094e0000359 => 80100094e0000359
++ fnabs. bfe0000000000001 => bfe0000000000001
++ fnabs. bfe00094e0000359 => bfe00094e0000359
++ fnabs. 0000000000000000 => 8000000000000000
++ fnabs. 8000000000000000 => 8000000000000000
++ fnabs. 7ff0000000000000 => fff0000000000000
++ fnabs. fff0000000000000 => fff0000000000000
++ fnabs. 7ff7ffffffffffff => fff7ffffffffffff
++ fnabs. fff7ffffffffffff => fff7ffffffffffff
++ fnabs. 7ff8000000000000 => fff8000000000000
++ fnabs. fff8000000000000 => fff8000000000000
++
++ fcfid. 0010000000000001 => 4330000000000001
++ fcfid. 00100094e0000359 => 43300094e0000359
++ fcfid. 3fe0000000000001 => 43cff00000000000
++ fcfid. 3fe00094e0000359 => 43cff0004a700002
++ fcfid. 8010000000000001 => c3dffc0000000000
++ fcfid. 80100094e0000359 => c3dffbffdac7ffff
++ fcfid. bfe0000000000001 => c3d0080000000000
++ fcfid. bfe00094e0000359 => c3d007ffdac7ffff
++ fcfid. 0000000000000000 => 0000000000000000
++ fcfid. 8000000000000000 => c3e0000000000000
++ fcfid. 7ff0000000000000 => 43dffc0000000000
++ fcfid. fff0000000000000 => c330000000000000
++ fcfid. 7ff7ffffffffffff => 43dffe0000000000
++ fcfid. fff7ffffffffffff => c320000000000002
++ fcfid. 7ff8000000000000 => 43dffe0000000000
++ fcfid. fff8000000000000 => c320000000000000
++
++ fctid. 0010000000000001 => 0000000000000000
++ fctid. 00100094e0000359 => 0000000000000000
++ fctid. 3fe0000000000001 => 0000000000000001
++ fctid. 3fe00094e0000359 => 0000000000000001
++ fctid. 8010000000000001 => 0000000000000000
++ fctid. 80100094e0000359 => 0000000000000000
++ fctid. bfe0000000000001 => ffffffffffffffff
++ fctid. bfe00094e0000359 => ffffffffffffffff
++ fctid. 0000000000000000 => 0000000000000000
++ fctid. 8000000000000000 => 0000000000000000
++ fctid. 7ff0000000000000 => 7fffffffffffffff
++ fctid. fff0000000000000 => 8000000000000000
++ fctid. 7ff7ffffffffffff => 8000000000000000
++ fctid. fff7ffffffffffff => 8000000000000000
++ fctid. 7ff8000000000000 => 8000000000000000
++ fctid. fff8000000000000 => 8000000000000000
++
++ fctidz. 0010000000000001 => 0000000000000000
++ fctidz. 00100094e0000359 => 0000000000000000
++ fctidz. 3fe0000000000001 => 0000000000000000
++ fctidz. 3fe00094e0000359 => 0000000000000000
++ fctidz. 8010000000000001 => 0000000000000000
++ fctidz. 80100094e0000359 => 0000000000000000
++ fctidz. bfe0000000000001 => 0000000000000000
++ fctidz. bfe00094e0000359 => 0000000000000000
++ fctidz. 0000000000000000 => 0000000000000000
++ fctidz. 8000000000000000 => 0000000000000000
++ fctidz. 7ff0000000000000 => 7fffffffffffffff
++ fctidz. fff0000000000000 => 8000000000000000
++ fctidz. 7ff7ffffffffffff => 8000000000000000
++ fctidz. fff7ffffffffffff => 8000000000000000
++ fctidz. 7ff8000000000000 => 8000000000000000
++ fctidz. fff8000000000000 => 8000000000000000
++
++PPC floating point status register manipulation insns:
++PPC floating point status register manipulation insns
++ with flags update:
++PPC float load insns
++ with one register + one 16 bits immediate args with flags update:
++ lfs 0010000000000001, 65416 => 37e0000000000000, 0
++ lfs 00100094e0000359, 65424 => 37e0009400000000, 0
++ lfs 3fe0000000000001, 65432 => 3ffc000000000000, 0
++ lfs 3fe00094e0000359, 65440 => 3ffc001280000000, 0
++ lfs 8010000000000001, 65448 => b7e0000000000000, 0
++ lfs 80100094e0000359, 65456 => b7e0009400000000, 0
++ lfs bfe0000000000001, 65464 => bffc000000000000, 0
++ lfs bfe00094e0000359, 65472 => bffc001280000000, 0
++ lfs 0000000000000000, 65480 => 0000000000000000, 0
++ lfs 8000000000000000, 65488 => 8000000000000000, 0
++ lfs 7ff0000000000000, 65496 => 7ffe000000000000, 0
++ lfs fff0000000000000, 65504 => fffe000000000000, 0
++ lfs 7ff7ffffffffffff, 65512 => 7ffeffffe0000000, 0
++ lfs fff7ffffffffffff, 65520 => fffeffffe0000000, 0
++ lfs 7ff8000000000000, 65528 => 7fff000000000000, 0
++ lfs 0010000000000001, 0 => 37e0000000000000, 0
++ lfs 00100094e0000359, 8 => 37e0009400000000, 0
++ lfs 3fe0000000000001, 16 => 3ffc000000000000, 0
++ lfs 3fe00094e0000359, 24 => 3ffc001280000000, 0
++ lfs 8010000000000001, 32 => b7e0000000000000, 0
++ lfs 80100094e0000359, 40 => b7e0009400000000, 0
++ lfs bfe0000000000001, 48 => bffc000000000000, 0
++ lfs bfe00094e0000359, 56 => bffc001280000000, 0
++ lfs 0000000000000000, 64 => 0000000000000000, 0
++ lfs 8000000000000000, 72 => 8000000000000000, 0
++ lfs 7ff0000000000000, 80 => 7ffe000000000000, 0
++ lfs fff0000000000000, 88 => fffe000000000000, 0
++ lfs 7ff7ffffffffffff, 96 => 7ffeffffe0000000, 0
++ lfs fff7ffffffffffff, 104 => fffeffffe0000000, 0
++ lfs 7ff8000000000000, 112 => 7fff000000000000, 0
++ lfs fff8000000000000, 120 => ffff000000000000, 0
++
++ lfsu 0010000000000001, 65416 => 37e0000000000000, -120
++ lfsu 00100094e0000359, 65424 => 37e0009400000000, -112
++ lfsu 3fe0000000000001, 65432 => 3ffc000000000000, -104
++ lfsu 3fe00094e0000359, 65440 => 3ffc001280000000, -96
++ lfsu 8010000000000001, 65448 => b7e0000000000000, -88
++ lfsu 80100094e0000359, 65456 => b7e0009400000000, -80
++ lfsu bfe0000000000001, 65464 => bffc000000000000, -72
++ lfsu bfe00094e0000359, 65472 => bffc001280000000, -64
++ lfsu 0000000000000000, 65480 => 0000000000000000, -56
++ lfsu 8000000000000000, 65488 => 8000000000000000, -48
++ lfsu 7ff0000000000000, 65496 => 7ffe000000000000, -40
++ lfsu fff0000000000000, 65504 => fffe000000000000, -32
++ lfsu 7ff7ffffffffffff, 65512 => 7ffeffffe0000000, -24
++ lfsu fff7ffffffffffff, 65520 => fffeffffe0000000, -16
++ lfsu 7ff8000000000000, 65528 => 7fff000000000000, -8
++ lfsu 0010000000000001, 0 => 37e0000000000000, 0
++ lfsu 00100094e0000359, 8 => 37e0009400000000, 8
++ lfsu 3fe0000000000001, 16 => 3ffc000000000000, 16
++ lfsu 3fe00094e0000359, 24 => 3ffc001280000000, 24
++ lfsu 8010000000000001, 32 => b7e0000000000000, 32
++ lfsu 80100094e0000359, 40 => b7e0009400000000, 40
++ lfsu bfe0000000000001, 48 => bffc000000000000, 48
++ lfsu bfe00094e0000359, 56 => bffc001280000000, 56
++ lfsu 0000000000000000, 64 => 0000000000000000, 64
++ lfsu 8000000000000000, 72 => 8000000000000000, 72
++ lfsu 7ff0000000000000, 80 => 7ffe000000000000, 80
++ lfsu fff0000000000000, 88 => fffe000000000000, 88
++ lfsu 7ff7ffffffffffff, 96 => 7ffeffffe0000000, 96
++ lfsu fff7ffffffffffff, 104 => fffeffffe0000000, 104
++ lfsu 7ff8000000000000, 112 => 7fff000000000000, 112
++ lfsu fff8000000000000, 120 => ffff000000000000, 120
++
++ lfd 0010000000000001, 65416 => 0010000000000001, 0
++ lfd 00100094e0000359, 65424 => 00100094e0000359, 0
++ lfd 3fe0000000000001, 65432 => 3fe0000000000001, 0
++ lfd 3fe00094e0000359, 65440 => 3fe00094e0000359, 0
++ lfd 8010000000000001, 65448 => 8010000000000001, 0
++ lfd 80100094e0000359, 65456 => 80100094e0000359, 0
++ lfd bfe0000000000001, 65464 => bfe0000000000001, 0
++ lfd bfe00094e0000359, 65472 => bfe00094e0000359, 0
++ lfd 0000000000000000, 65480 => 0000000000000000, 0
++ lfd 8000000000000000, 65488 => 8000000000000000, 0
++ lfd 7ff0000000000000, 65496 => 7ff0000000000000, 0
++ lfd fff0000000000000, 65504 => fff0000000000000, 0
++ lfd 7ff7ffffffffffff, 65512 => 7ff7ffffffffffff, 0
++ lfd fff7ffffffffffff, 65520 => fff7ffffffffffff, 0
++ lfd 7ff8000000000000, 65528 => 7ff8000000000000, 0
++ lfd 0010000000000001, 0 => 0010000000000001, 0
++ lfd 00100094e0000359, 8 => 00100094e0000359, 0
++ lfd 3fe0000000000001, 16 => 3fe0000000000001, 0
++ lfd 3fe00094e0000359, 24 => 3fe00094e0000359, 0
++ lfd 8010000000000001, 32 => 8010000000000001, 0
++ lfd 80100094e0000359, 40 => 80100094e0000359, 0
++ lfd bfe0000000000001, 48 => bfe0000000000001, 0
++ lfd bfe00094e0000359, 56 => bfe00094e0000359, 0
++ lfd 0000000000000000, 64 => 0000000000000000, 0
++ lfd 8000000000000000, 72 => 8000000000000000, 0
++ lfd 7ff0000000000000, 80 => 7ff0000000000000, 0
++ lfd fff0000000000000, 88 => fff0000000000000, 0
++ lfd 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0
++ lfd fff7ffffffffffff, 104 => fff7ffffffffffff, 0
++ lfd 7ff8000000000000, 112 => 7ff8000000000000, 0
++ lfd fff8000000000000, 120 => fff8000000000000, 0
++
++ lfdu 0010000000000001, 65416 => 0010000000000001, -120
++ lfdu 00100094e0000359, 65424 => 00100094e0000359, -112
++ lfdu 3fe0000000000001, 65432 => 3fe0000000000001, -104
++ lfdu 3fe00094e0000359, 65440 => 3fe00094e0000359, -96
++ lfdu 8010000000000001, 65448 => 8010000000000001, -88
++ lfdu 80100094e0000359, 65456 => 80100094e0000359, -80
++ lfdu bfe0000000000001, 65464 => bfe0000000000001, -72
++ lfdu bfe00094e0000359, 65472 => bfe00094e0000359, -64
++ lfdu 0000000000000000, 65480 => 0000000000000000, -56
++ lfdu 8000000000000000, 65488 => 8000000000000000, -48
++ lfdu 7ff0000000000000, 65496 => 7ff0000000000000, -40
++ lfdu fff0000000000000, 65504 => fff0000000000000, -32
++ lfdu 7ff7ffffffffffff, 65512 => 7ff7ffffffffffff, -24
++ lfdu fff7ffffffffffff, 65520 => fff7ffffffffffff, -16
++ lfdu 7ff8000000000000, 65528 => 7ff8000000000000, -8
++ lfdu 0010000000000001, 0 => 0010000000000001, 0
++ lfdu 00100094e0000359, 8 => 00100094e0000359, 8
++ lfdu 3fe0000000000001, 16 => 3fe0000000000001, 16
++ lfdu 3fe00094e0000359, 24 => 3fe00094e0000359, 24
++ lfdu 8010000000000001, 32 => 8010000000000001, 32
++ lfdu 80100094e0000359, 40 => 80100094e0000359, 40
++ lfdu bfe0000000000001, 48 => bfe0000000000001, 48
++ lfdu bfe00094e0000359, 56 => bfe00094e0000359, 56
++ lfdu 0000000000000000, 64 => 0000000000000000, 64
++ lfdu 8000000000000000, 72 => 8000000000000000, 72
++ lfdu 7ff0000000000000, 80 => 7ff0000000000000, 80
++ lfdu fff0000000000000, 88 => fff0000000000000, 88
++ lfdu 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96
++ lfdu fff7ffffffffffff, 104 => fff7ffffffffffff, 104
++ lfdu 7ff8000000000000, 112 => 7ff8000000000000, 112
++ lfdu fff8000000000000, 120 => fff8000000000000, 120
++
++PPC float load insns with two register args:
++ lfsx 0010000000000001, -120 => 37e0000000000000, 0
++ lfsx 00100094e0000359, -112 => 37e0009400000000, 0
++ lfsx 3fe0000000000001, -104 => 3ffc000000000000, 0
++ lfsx 3fe00094e0000359, -96 => 3ffc001280000000, 0
++ lfsx 8010000000000001, -88 => b7e0000000000000, 0
++ lfsx 80100094e0000359, -80 => b7e0009400000000, 0
++ lfsx bfe0000000000001, -72 => bffc000000000000, 0
++ lfsx bfe00094e0000359, -64 => bffc001280000000, 0
++ lfsx 0000000000000000, -56 => 0000000000000000, 0
++ lfsx 8000000000000000, -48 => 8000000000000000, 0
++ lfsx 7ff0000000000000, -40 => 7ffe000000000000, 0
++ lfsx fff0000000000000, -32 => fffe000000000000, 0
++ lfsx 7ff7ffffffffffff, -24 => 7ffeffffe0000000, 0
++ lfsx fff7ffffffffffff, -16 => fffeffffe0000000, 0
++ lfsx 7ff8000000000000, -8 => 7fff000000000000, 0
++ lfsx 0010000000000001, 0 => 37e0000000000000, 0
++ lfsx 00100094e0000359, 8 => 37e0009400000000, 0
++ lfsx 3fe0000000000001, 16 => 3ffc000000000000, 0
++ lfsx 3fe00094e0000359, 24 => 3ffc001280000000, 0
++ lfsx 8010000000000001, 32 => b7e0000000000000, 0
++ lfsx 80100094e0000359, 40 => b7e0009400000000, 0
++ lfsx bfe0000000000001, 48 => bffc000000000000, 0
++ lfsx bfe00094e0000359, 56 => bffc001280000000, 0
++ lfsx 0000000000000000, 64 => 0000000000000000, 0
++ lfsx 8000000000000000, 72 => 8000000000000000, 0
++ lfsx 7ff0000000000000, 80 => 7ffe000000000000, 0
++ lfsx fff0000000000000, 88 => fffe000000000000, 0
++ lfsx 7ff7ffffffffffff, 96 => 7ffeffffe0000000, 0
++ lfsx fff7ffffffffffff, 104 => fffeffffe0000000, 0
++ lfsx 7ff8000000000000, 112 => 7fff000000000000, 0
++ lfsx fff8000000000000, 120 => ffff000000000000, 0
++
++ lfsux 0010000000000001, -120 => 37e0000000000000, -120
++ lfsux 00100094e0000359, -112 => 37e0009400000000, -112
++ lfsux 3fe0000000000001, -104 => 3ffc000000000000, -104
++ lfsux 3fe00094e0000359, -96 => 3ffc001280000000, -96
++ lfsux 8010000000000001, -88 => b7e0000000000000, -88
++ lfsux 80100094e0000359, -80 => b7e0009400000000, -80
++ lfsux bfe0000000000001, -72 => bffc000000000000, -72
++ lfsux bfe00094e0000359, -64 => bffc001280000000, -64
++ lfsux 0000000000000000, -56 => 0000000000000000, -56
++ lfsux 8000000000000000, -48 => 8000000000000000, -48
++ lfsux 7ff0000000000000, -40 => 7ffe000000000000, -40
++ lfsux fff0000000000000, -32 => fffe000000000000, -32
++ lfsux 7ff7ffffffffffff, -24 => 7ffeffffe0000000, -24
++ lfsux fff7ffffffffffff, -16 => fffeffffe0000000, -16
++ lfsux 7ff8000000000000, -8 => 7fff000000000000, -8
++ lfsux 0010000000000001, 0 => 37e0000000000000, 0
++ lfsux 00100094e0000359, 8 => 37e0009400000000, 8
++ lfsux 3fe0000000000001, 16 => 3ffc000000000000, 16
++ lfsux 3fe00094e0000359, 24 => 3ffc001280000000, 24
++ lfsux 8010000000000001, 32 => b7e0000000000000, 32
++ lfsux 80100094e0000359, 40 => b7e0009400000000, 40
++ lfsux bfe0000000000001, 48 => bffc000000000000, 48
++ lfsux bfe00094e0000359, 56 => bffc001280000000, 56
++ lfsux 0000000000000000, 64 => 0000000000000000, 64
++ lfsux 8000000000000000, 72 => 8000000000000000, 72
++ lfsux 7ff0000000000000, 80 => 7ffe000000000000, 80
++ lfsux fff0000000000000, 88 => fffe000000000000, 88
++ lfsux 7ff7ffffffffffff, 96 => 7ffeffffe0000000, 96
++ lfsux fff7ffffffffffff, 104 => fffeffffe0000000, 104
++ lfsux 7ff8000000000000, 112 => 7fff000000000000, 112
++ lfsux fff8000000000000, 120 => ffff000000000000, 120
++
++ lfdx 0010000000000001, -120 => 0010000000000001, 0
++ lfdx 00100094e0000359, -112 => 00100094e0000359, 0
++ lfdx 3fe0000000000001, -104 => 3fe0000000000001, 0
++ lfdx 3fe00094e0000359, -96 => 3fe00094e0000359, 0
++ lfdx 8010000000000001, -88 => 8010000000000001, 0
++ lfdx 80100094e0000359, -80 => 80100094e0000359, 0
++ lfdx bfe0000000000001, -72 => bfe0000000000001, 0
++ lfdx bfe00094e0000359, -64 => bfe00094e0000359, 0
++ lfdx 0000000000000000, -56 => 0000000000000000, 0
++ lfdx 8000000000000000, -48 => 8000000000000000, 0
++ lfdx 7ff0000000000000, -40 => 7ff0000000000000, 0
++ lfdx fff0000000000000, -32 => fff0000000000000, 0
++ lfdx 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, 0
++ lfdx fff7ffffffffffff, -16 => fff7ffffffffffff, 0
++ lfdx 7ff8000000000000, -8 => 7ff8000000000000, 0
++ lfdx 0010000000000001, 0 => 0010000000000001, 0
++ lfdx 00100094e0000359, 8 => 00100094e0000359, 0
++ lfdx 3fe0000000000001, 16 => 3fe0000000000001, 0
++ lfdx 3fe00094e0000359, 24 => 3fe00094e0000359, 0
++ lfdx 8010000000000001, 32 => 8010000000000001, 0
++ lfdx 80100094e0000359, 40 => 80100094e0000359, 0
++ lfdx bfe0000000000001, 48 => bfe0000000000001, 0
++ lfdx bfe00094e0000359, 56 => bfe00094e0000359, 0
++ lfdx 0000000000000000, 64 => 0000000000000000, 0
++ lfdx 8000000000000000, 72 => 8000000000000000, 0
++ lfdx 7ff0000000000000, 80 => 7ff0000000000000, 0
++ lfdx fff0000000000000, 88 => fff0000000000000, 0
++ lfdx 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0
++ lfdx fff7ffffffffffff, 104 => fff7ffffffffffff, 0
++ lfdx 7ff8000000000000, 112 => 7ff8000000000000, 0
++ lfdx fff8000000000000, 120 => fff8000000000000, 0
++
++ lfdux 0010000000000001, -120 => 0010000000000001, -120
++ lfdux 00100094e0000359, -112 => 00100094e0000359, -112
++ lfdux 3fe0000000000001, -104 => 3fe0000000000001, -104
++ lfdux 3fe00094e0000359, -96 => 3fe00094e0000359, -96
++ lfdux 8010000000000001, -88 => 8010000000000001, -88
++ lfdux 80100094e0000359, -80 => 80100094e0000359, -80
++ lfdux bfe0000000000001, -72 => bfe0000000000001, -72
++ lfdux bfe00094e0000359, -64 => bfe00094e0000359, -64
++ lfdux 0000000000000000, -56 => 0000000000000000, -56
++ lfdux 8000000000000000, -48 => 8000000000000000, -48
++ lfdux 7ff0000000000000, -40 => 7ff0000000000000, -40
++ lfdux fff0000000000000, -32 => fff0000000000000, -32
++ lfdux 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, -24
++ lfdux fff7ffffffffffff, -16 => fff7ffffffffffff, -16
++ lfdux 7ff8000000000000, -8 => 7ff8000000000000, -8
++ lfdux 0010000000000001, 0 => 0010000000000001, 0
++ lfdux 00100094e0000359, 8 => 00100094e0000359, 8
++ lfdux 3fe0000000000001, 16 => 3fe0000000000001, 16
++ lfdux 3fe00094e0000359, 24 => 3fe00094e0000359, 24
++ lfdux 8010000000000001, 32 => 8010000000000001, 32
++ lfdux 80100094e0000359, 40 => 80100094e0000359, 40
++ lfdux bfe0000000000001, 48 => bfe0000000000001, 48
++ lfdux bfe00094e0000359, 56 => bfe00094e0000359, 56
++ lfdux 0000000000000000, 64 => 0000000000000000, 64
++ lfdux 8000000000000000, 72 => 8000000000000000, 72
++ lfdux 7ff0000000000000, 80 => 7ff0000000000000, 80
++ lfdux fff0000000000000, 88 => fff0000000000000, 88
++ lfdux 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96
++ lfdux fff7ffffffffffff, 104 => fff7ffffffffffff, 104
++ lfdux 7ff8000000000000, 112 => 7ff8000000000000, 112
++ lfdux fff8000000000000, 120 => fff8000000000000, 120
++
++PPC float store insns
++ with one register + one 16 bits immediate args with flags update:
++ stfs 0010000000000001, -56 => 0000000000000000, 0
++ stfs 00100094e0000359, -48 => 0000000000000000, 0
++ stfs 3fe0000000000001, -40 => 3f00000000000000, 0
++ stfs 3fe00094e0000359, -32 => 3f0004a700000000, 0
++ stfs 8010000000000001, -24 => 8000000000000000, 0
++ stfs 80100094e0000359, -16 => 8000000000000000, 0
++ stfs bfe0000000000001, -8 => bf00000000000000, 0
++ stfs 0010000000000001, 0 => 0000000000000000, 0
++ stfs 00100094e0000359, 8 => 0000000000000000, 0
++ stfs 3fe0000000000001, 16 => 3f00000000000000, 0
++ stfs 3fe00094e0000359, 24 => 3f0004a700000000, 0
++ stfs 8010000000000001, 32 => 8000000000000000, 0
++ stfs 80100094e0000359, 40 => 8000000000000000, 0
++ stfs bfe0000000000001, 48 => bf00000000000000, 0
++ stfs bfe00094e0000359, 56 => bf0004a700000000, 0
++
++ stfsu 0010000000000001, -56 => 0000000000000000, -56
++ stfsu 00100094e0000359, -48 => 0000000000000000, -48
++ stfsu 3fe0000000000001, -40 => 3f00000000000000, -40
++ stfsu 3fe00094e0000359, -32 => 3f0004a700000000, -32
++ stfsu 8010000000000001, -24 => 8000000000000000, -24
++ stfsu 80100094e0000359, -16 => 8000000000000000, -16
++ stfsu bfe0000000000001, -8 => bf00000000000000, -8
++ stfsu 0010000000000001, 0 => 0000000000000000, 0
++ stfsu 00100094e0000359, 8 => 0000000000000000, 8
++ stfsu 3fe0000000000001, 16 => 3f00000000000000, 16
++ stfsu 3fe00094e0000359, 24 => 3f0004a700000000, 24
++ stfsu 8010000000000001, 32 => 8000000000000000, 32
++ stfsu 80100094e0000359, 40 => 8000000000000000, 40
++ stfsu bfe0000000000001, 48 => bf00000000000000, 48
++ stfsu bfe00094e0000359, 56 => bf0004a700000000, 56
++
++ stfd 0010000000000001, -120 => 0010000000000001, 0
++ stfd 00100094e0000359, -112 => 00100094e0000359, 0
++ stfd 3fe0000000000001, -104 => 3fe0000000000001, 0
++ stfd 3fe00094e0000359, -96 => 3fe00094e0000359, 0
++ stfd 8010000000000001, -88 => 8010000000000001, 0
++ stfd 80100094e0000359, -80 => 80100094e0000359, 0
++ stfd bfe0000000000001, -72 => bfe0000000000001, 0
++ stfd bfe00094e0000359, -64 => bfe00094e0000359, 0
++ stfd 0000000000000000, -56 => 0000000000000000, 0
++ stfd 8000000000000000, -48 => 8000000000000000, 0
++ stfd 7ff0000000000000, -40 => 7ff0000000000000, 0
++ stfd fff0000000000000, -32 => fff0000000000000, 0
++ stfd 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, 0
++ stfd fff7ffffffffffff, -16 => fff7ffffffffffff, 0
++ stfd 7ff8000000000000, -8 => 7ff8000000000000, 0
++ stfd 0010000000000001, 0 => 0010000000000001, 0
++ stfd 00100094e0000359, 8 => 00100094e0000359, 0
++ stfd 3fe0000000000001, 16 => 3fe0000000000001, 0
++ stfd 3fe00094e0000359, 24 => 3fe00094e0000359, 0
++ stfd 8010000000000001, 32 => 8010000000000001, 0
++ stfd 80100094e0000359, 40 => 80100094e0000359, 0
++ stfd bfe0000000000001, 48 => bfe0000000000001, 0
++ stfd bfe00094e0000359, 56 => bfe00094e0000359, 0
++ stfd 0000000000000000, 64 => 0000000000000000, 0
++ stfd 8000000000000000, 72 => 8000000000000000, 0
++ stfd 7ff0000000000000, 80 => 7ff0000000000000, 0
++ stfd fff0000000000000, 88 => fff0000000000000, 0
++ stfd 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0
++ stfd fff7ffffffffffff, 104 => fff7ffffffffffff, 0
++ stfd 7ff8000000000000, 112 => 7ff8000000000000, 0
++ stfd fff8000000000000, 120 => fff8000000000000, 0
++
++ stfdu 0010000000000001, -120 => 0010000000000001, -120
++ stfdu 00100094e0000359, -112 => 00100094e0000359, -112
++ stfdu 3fe0000000000001, -104 => 3fe0000000000001, -104
++ stfdu 3fe00094e0000359, -96 => 3fe00094e0000359, -96
++ stfdu 8010000000000001, -88 => 8010000000000001, -88
++ stfdu 80100094e0000359, -80 => 80100094e0000359, -80
++ stfdu bfe0000000000001, -72 => bfe0000000000001, -72
++ stfdu bfe00094e0000359, -64 => bfe00094e0000359, -64
++ stfdu 0000000000000000, -56 => 0000000000000000, -56
++ stfdu 8000000000000000, -48 => 8000000000000000, -48
++ stfdu 7ff0000000000000, -40 => 7ff0000000000000, -40
++ stfdu fff0000000000000, -32 => fff0000000000000, -32
++ stfdu 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, -24
++ stfdu fff7ffffffffffff, -16 => fff7ffffffffffff, -16
++ stfdu 7ff8000000000000, -8 => 7ff8000000000000, -8
++ stfdu 0010000000000001, 0 => 0010000000000001, 0
++ stfdu 00100094e0000359, 8 => 00100094e0000359, 8
++ stfdu 3fe0000000000001, 16 => 3fe0000000000001, 16
++ stfdu 3fe00094e0000359, 24 => 3fe00094e0000359, 24
++ stfdu 8010000000000001, 32 => 8010000000000001, 32
++ stfdu 80100094e0000359, 40 => 80100094e0000359, 40
++ stfdu bfe0000000000001, 48 => bfe0000000000001, 48
++ stfdu bfe00094e0000359, 56 => bfe00094e0000359, 56
++ stfdu 0000000000000000, 64 => 0000000000000000, 64
++ stfdu 8000000000000000, 72 => 8000000000000000, 72
++ stfdu 7ff0000000000000, 80 => 7ff0000000000000, 80
++ stfdu fff0000000000000, 88 => fff0000000000000, 88
++ stfdu 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96
++ stfdu fff7ffffffffffff, 104 => fff7ffffffffffff, 104
++ stfdu 7ff8000000000000, 112 => 7ff8000000000000, 112
++ stfdu fff8000000000000, 120 => fff8000000000000, 120
++
++PPC float store insns with three register args:
++ stfsx 0010000000000001, 0 => 0000000000000000, 0
++ stfsx 00100094e0000359, 8 => 0000000000000000, 0
++ stfsx 3fe0000000000001, 16 => 3f00000000000000, 0
++ stfsx 3fe00094e0000359, 24 => 3f0004a700000000, 0
++ stfsx 8010000000000001, 32 => 8000000000000000, 0
++ stfsx 80100094e0000359, 40 => 8000000000000000, 0
++ stfsx bfe0000000000001, 48 => bf00000000000000, 0
++ stfsx bfe00094e0000359, 56 => bf0004a700000000, 0
++
++ stfsux 0010000000000001, 0 => 0000000000000000, 0
++ stfsux 00100094e0000359, 8 => 0000000000000000, 8
++ stfsux 3fe0000000000001, 16 => 3f00000000000000, 16
++ stfsux 3fe00094e0000359, 24 => 3f0004a700000000, 24
++ stfsux 8010000000000001, 32 => 8000000000000000, 32
++ stfsux 80100094e0000359, 40 => 8000000000000000, 40
++ stfsux bfe0000000000001, 48 => bf00000000000000, 48
++ stfsux bfe00094e0000359, 56 => bf0004a700000000, 56
++
++ stfdx 0010000000000001, 0 => 0010000000000001, 0
++ stfdx 00100094e0000359, 8 => 00100094e0000359, 0
++ stfdx 3fe0000000000001, 16 => 3fe0000000000001, 0
++ stfdx 3fe00094e0000359, 24 => 3fe00094e0000359, 0
++ stfdx 8010000000000001, 32 => 8010000000000001, 0
++ stfdx 80100094e0000359, 40 => 80100094e0000359, 0
++ stfdx bfe0000000000001, 48 => bfe0000000000001, 0
++ stfdx bfe00094e0000359, 56 => bfe00094e0000359, 0
++ stfdx 0000000000000000, 64 => 0000000000000000, 0
++ stfdx 8000000000000000, 72 => 8000000000000000, 0
++ stfdx 7ff0000000000000, 80 => 7ff0000000000000, 0
++ stfdx fff0000000000000, 88 => fff0000000000000, 0
++ stfdx 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0
++ stfdx fff7ffffffffffff, 104 => fff7ffffffffffff, 0
++ stfdx 7ff8000000000000, 112 => 7ff8000000000000, 0
++ stfdx fff8000000000000, 120 => fff8000000000000, 0
++
++ stfdux 0010000000000001, 0 => 0010000000000001, 0
++ stfdux 00100094e0000359, 8 => 00100094e0000359, 8
++ stfdux 3fe0000000000001, 16 => 3fe0000000000001, 16
++ stfdux 3fe00094e0000359, 24 => 3fe00094e0000359, 24
++ stfdux 8010000000000001, 32 => 8010000000000001, 32
++ stfdux 80100094e0000359, 40 => 80100094e0000359, 40
++ stfdux bfe0000000000001, 48 => bfe0000000000001, 48
++ stfdux bfe00094e0000359, 56 => bfe00094e0000359, 56
++ stfdux 0000000000000000, 64 => 0000000000000000, 64
++ stfdux 8000000000000000, 72 => 8000000000000000, 72
++ stfdux 7ff0000000000000, 80 => 7ff0000000000000, 80
++ stfdux fff0000000000000, 88 => fff0000000000000, 88
++ stfdux 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96
++ stfdux fff7ffffffffffff, 104 => fff7ffffffffffff, 104
++ stfdux 7ff8000000000000, 112 => 7ff8000000000000, 112
++ stfdux fff8000000000000, 120 => fff8000000000000, 120
++
++All done. Tested 77 different instructions
+diff --git a/none/tests/ppc64/jm-fp.stdout.exp-LE b/none/tests/ppc64/jm-fp.stdout.exp-LE
+new file mode 100644
+index 0000000..578c673
+--- /dev/null
++++ b/none/tests/ppc64/jm-fp.stdout.exp-LE
+@@ -0,0 +1,1533 @@
++PPC floating point arith insns with three args:
++ fsel 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
++ fsel 0010000000000001, 0010000000000001, bfe00094e0000359 => 0010000000000000
++ fsel 0010000000000001, 80100094e0000359, 0010000000000001 => 80100094e0000300
++ fsel 0010000000000001, 80100094e0000359, bfe00094e0000359 => 80100094e0000300
++ fsel 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0010000000000000
++ fsel 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 0010000000000000
++ fsel 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80100094e0000300
++ fsel 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 80100094e0000300
++ fsel bfe0000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
++ fsel bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fsel bfe0000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
++ fsel bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++
++ fmadd 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
++ fmadd 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fmadd 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
++ fmadd 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++ fmadd 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0018004a70000100
++ fmadd 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fmadd 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0007ff6b1d4b5e00
++ fmadd 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++ fmadd bfe0000000000001, 0010000000000001, 0010000000000001 => 0008000000000000
++ fmadd bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fmadd bfe0000000000001, 80100094e0000359, 0010000000000001 => 0018004a70000100
++ fmadd bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++
++ fmadds 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
++ fmadds 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fmadds 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fmadds 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++ fmadds 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000
++ fmadds 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fmadds 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fmadds 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++ fmadds bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
++ fmadds bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fmadds bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fmadds bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++
++ fmsub 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000
++ fmsub 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fmsub 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000
++ fmsub 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++ fmsub 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8007ffb58ffffe00
++ fmsub 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fmsub 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80180094e2b4a100
++ fmsub 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++ fmsub bfe0000000000001, 0010000000000001, 0010000000000001 => 8018000000000000
++ fmsub bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fmsub bfe0000000000001, 80100094e0000359, 0010000000000001 => 8007ffb58ffffe00
++ fmsub bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++
++ fmsubs 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
++ fmsubs 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fmsubs 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fmsubs 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++ fmsubs 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000
++ fmsubs 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fmsubs 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fmsubs 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++ fmsubs bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
++ fmsubs bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fmsubs bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fmsubs bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++
++ fnmadd 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000
++ fnmadd 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fnmadd 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000
++ fnmadd 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++ fnmadd 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8018004a70000100
++ fnmadd 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fnmadd 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8007ff6b1d4b5e00
++ fnmadd 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++ fnmadd bfe0000000000001, 0010000000000001, 0010000000000001 => 8008000000000000
++ fnmadd bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fnmadd bfe0000000000001, 80100094e0000359, 0010000000000001 => 8018004a70000100
++ fnmadd bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++
++ fnmadds 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
++ fnmadds 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fnmadds 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fnmadds 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++ fnmadds 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000
++ fnmadds 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fnmadds 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fnmadds 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++ fnmadds bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
++ fnmadds bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fnmadds bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fnmadds bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++
++ fnmsub 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
++ fnmsub 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fnmsub 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
++ fnmsub 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++ fnmsub 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0007ffb58ffffe00
++ fnmsub 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fnmsub 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 00180094e2b4a100
++ fnmsub 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++ fnmsub bfe0000000000001, 0010000000000001, 0010000000000001 => 0018000000000000
++ fnmsub bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fnmsub bfe0000000000001, 80100094e0000359, 0010000000000001 => 0007ffb58ffffe00
++ fnmsub bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++
++ fnmsubs 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
++ fnmsubs 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fnmsubs 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fnmsubs 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++ fnmsubs 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000
++ fnmsubs 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fnmsubs 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fnmsubs 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++ fnmsubs bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
++ fnmsubs bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fnmsubs bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fnmsubs bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++
++PPC floating point arith insns
++ with three args with flags update:
++ fsel. 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
++ fsel. 0010000000000001, 0010000000000001, bfe00094e0000359 => 0010000000000000
++ fsel. 0010000000000001, 80100094e0000359, 0010000000000001 => 80100094e0000300
++ fsel. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 80100094e0000300
++ fsel. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0010000000000000
++ fsel. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 0010000000000000
++ fsel. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80100094e0000300
++ fsel. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 80100094e0000300
++ fsel. bfe0000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
++ fsel. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fsel. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
++ fsel. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++
++ fmadd. 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
++ fmadd. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fmadd. 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
++ fmadd. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++ fmadd. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0018004a70000100
++ fmadd. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fmadd. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0007ff6b1d4b5e00
++ fmadd. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++ fmadd. bfe0000000000001, 0010000000000001, 0010000000000001 => 0008000000000000
++ fmadd. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fmadd. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0018004a70000100
++ fmadd. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++
++ fmadds. 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
++ fmadds. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fmadds. 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fmadds. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++ fmadds. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000
++ fmadds. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fmadds. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fmadds. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++ fmadds. bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
++ fmadds. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fmadds. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fmadds. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++
++ fmsub. 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000
++ fmsub. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fmsub. 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000
++ fmsub. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++ fmsub. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8007ffb58ffffe00
++ fmsub. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fmsub. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80180094e2b4a100
++ fmsub. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++ fmsub. bfe0000000000001, 0010000000000001, 0010000000000001 => 8018000000000000
++ fmsub. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fmsub. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8007ffb58ffffe00
++ fmsub. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++
++ fmsubs. 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
++ fmsubs. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fmsubs. 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fmsubs. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++ fmsubs. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000
++ fmsubs. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fmsubs. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fmsubs. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++ fmsubs. bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
++ fmsubs. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fmsubs. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fmsubs. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++
++ fnmadd. 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000
++ fnmadd. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fnmadd. 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000
++ fnmadd. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++ fnmadd. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8018004a70000100
++ fnmadd. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fnmadd. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8007ff6b1d4b5e00
++ fnmadd. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++ fnmadd. bfe0000000000001, 0010000000000001, 0010000000000001 => 8008000000000000
++ fnmadd. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fnmadd. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8018004a70000100
++ fnmadd. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++
++ fnmadds. 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
++ fnmadds. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fnmadds. 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fnmadds. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++ fnmadds. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000
++ fnmadds. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fnmadds. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fnmadds. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++ fnmadds. bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
++ fnmadds. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fnmadds. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fnmadds. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++
++ fnmsub. 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
++ fnmsub. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fnmsub. 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
++ fnmsub. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++ fnmsub. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0007ffb58ffffe00
++ fnmsub. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fnmsub. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 00180094e2b4a100
++ fnmsub. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++ fnmsub. bfe0000000000001, 0010000000000001, 0010000000000001 => 0018000000000000
++ fnmsub. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fnmsub. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0007ffb58ffffe00
++ fnmsub. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++
++ fnmsubs. 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
++ fnmsubs. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fnmsubs. 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fnmsubs. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++ fnmsubs. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000
++ fnmsubs. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fnmsubs. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fnmsubs. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++ fnmsubs. bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
++ fnmsubs. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fnmsubs. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fnmsubs. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++
++PPC floating point arith insns with two args:
++ fadd 0010000000000001, 0010000000000001 => 0020000000000001
++ fadd 0010000000000001, 80100094e0000359 => 80000094e0000358
++ fadd 0010000000000001, 7ff0000000000000 => 7ff0000000000000
++ fadd 0010000000000001, fff8000000000000 => fff8000000000000
++ fadd 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359
++ fadd 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359
++ fadd 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
++ fadd 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fadd bfe0000000000001, 0010000000000001 => bfe0000000000001
++ fadd bfe0000000000001, 80100094e0000359 => bfe0000000000001
++ fadd bfe0000000000001, 7ff0000000000000 => 7ff0000000000000
++ fadd bfe0000000000001, fff8000000000000 => fff8000000000000
++ fadd 8000000000000000, 0010000000000001 => 0010000000000001
++ fadd 8000000000000000, 80100094e0000359 => 80100094e0000359
++ fadd 8000000000000000, 7ff0000000000000 => 7ff0000000000000
++ fadd 8000000000000000, fff8000000000000 => fff8000000000000
++ fadd 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
++ fadd 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
++ fadd 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
++ fadd 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
++ fadd fff8000000000000, 0010000000000001 => fff8000000000000
++ fadd fff8000000000000, 80100094e0000359 => fff8000000000000
++ fadd fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fadd fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fadds 0010000000000001, 0010000000000001 => 0000000000000000
++ fadds 0010000000000001, 80100094e0000359 => 8000000000000000
++ fadds 0010000000000001, 7ff0000000000000 => 7ff0000000000000
++ fadds 0010000000000001, fff8000000000000 => fff8000000000000
++ fadds 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000
++ fadds 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000
++ fadds 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
++ fadds 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fadds bfe0000000000001, 0010000000000001 => bfe0000000000000
++ fadds bfe0000000000001, 80100094e0000359 => bfe0000000000000
++ fadds bfe0000000000001, 7ff0000000000000 => 7ff0000000000000
++ fadds bfe0000000000001, fff8000000000000 => fff8000000000000
++ fadds 8000000000000000, 0010000000000001 => 0000000000000000
++ fadds 8000000000000000, 80100094e0000359 => 8000000000000000
++ fadds 8000000000000000, 7ff0000000000000 => 7ff0000000000000
++ fadds 8000000000000000, fff8000000000000 => fff8000000000000
++ fadds 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
++ fadds 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
++ fadds 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
++ fadds 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
++ fadds fff8000000000000, 0010000000000001 => fff8000000000000
++ fadds fff8000000000000, 80100094e0000359 => fff8000000000000
++ fadds fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fadds fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fsub 0010000000000001, 0010000000000001 => 0000000000000000
++ fsub 0010000000000001, 80100094e0000359 => 0020004a700001ad
++ fsub 0010000000000001, 7ff0000000000000 => fff0000000000000
++ fsub 0010000000000001, fff8000000000000 => fff8000000000000
++ fsub 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359
++ fsub 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359
++ fsub 3fe00094e0000359, 7ff0000000000000 => fff0000000000000
++ fsub 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fsub bfe0000000000001, 0010000000000001 => bfe0000000000001
++ fsub bfe0000000000001, 80100094e0000359 => bfe0000000000001
++ fsub bfe0000000000001, 7ff0000000000000 => fff0000000000000
++ fsub bfe0000000000001, fff8000000000000 => fff8000000000000
++ fsub 8000000000000000, 0010000000000001 => 8010000000000001
++ fsub 8000000000000000, 80100094e0000359 => 00100094e0000359
++ fsub 8000000000000000, 7ff0000000000000 => fff0000000000000
++ fsub 8000000000000000, fff8000000000000 => fff8000000000000
++ fsub 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
++ fsub 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
++ fsub 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
++ fsub 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
++ fsub fff8000000000000, 0010000000000001 => fff8000000000000
++ fsub fff8000000000000, 80100094e0000359 => fff8000000000000
++ fsub fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fsub fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fsubs 0010000000000001, 0010000000000001 => 0000000000000000
++ fsubs 0010000000000001, 80100094e0000359 => 0000000000000000
++ fsubs 0010000000000001, 7ff0000000000000 => fff0000000000000
++ fsubs 0010000000000001, fff8000000000000 => fff8000000000000
++ fsubs 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000
++ fsubs 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000
++ fsubs 3fe00094e0000359, 7ff0000000000000 => fff0000000000000
++ fsubs 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fsubs bfe0000000000001, 0010000000000001 => bfe0000000000000
++ fsubs bfe0000000000001, 80100094e0000359 => bfe0000000000000
++ fsubs bfe0000000000001, 7ff0000000000000 => fff0000000000000
++ fsubs bfe0000000000001, fff8000000000000 => fff8000000000000
++ fsubs 8000000000000000, 0010000000000001 => 8000000000000000
++ fsubs 8000000000000000, 80100094e0000359 => 0000000000000000
++ fsubs 8000000000000000, 7ff0000000000000 => fff0000000000000
++ fsubs 8000000000000000, fff8000000000000 => fff8000000000000
++ fsubs 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
++ fsubs 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
++ fsubs 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
++ fsubs 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
++ fsubs fff8000000000000, 0010000000000001 => fff8000000000000
++ fsubs fff8000000000000, 80100094e0000359 => fff8000000000000
++ fsubs fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fsubs fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fmul 0010000000000001, 0010000000000001 => 0000000000000000
++ fmul 0010000000000001, 80100094e0000359 => 8000000000000000
++ fmul 0010000000000001, 7ff0000000000000 => 7ff0000000000000
++ fmul 0010000000000001, fff8000000000000 => fff8000000000000
++ fmul 3fe00094e0000359, 0010000000000001 => 0008004a700001ad
++ fmul 3fe00094e0000359, 80100094e0000359 => 80080094e2b4a179
++ fmul 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
++ fmul 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fmul bfe0000000000001, 0010000000000001 => 8008000000000001
++ fmul bfe0000000000001, 80100094e0000359 => 0008004a700001ad
++ fmul bfe0000000000001, 7ff0000000000000 => fff0000000000000
++ fmul bfe0000000000001, fff8000000000000 => fff8000000000000
++ fmul 8000000000000000, 0010000000000001 => 8000000000000000
++ fmul 8000000000000000, 80100094e0000359 => 0000000000000000
++ fmul 8000000000000000, 7ff0000000000000 => 7ff8000000000000
++ fmul 8000000000000000, fff8000000000000 => fff8000000000000
++ fmul 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
++ fmul 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
++ fmul 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
++ fmul 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
++ fmul fff8000000000000, 0010000000000001 => fff8000000000000
++ fmul fff8000000000000, 80100094e0000359 => fff8000000000000
++ fmul fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fmul fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fmuls 0010000000000001, 0010000000000001 => 0000000000000000
++ fmuls 0010000000000001, 80100094e0000359 => 8000000000000000
++ fmuls 0010000000000001, 7ff0000000000000 => 7ff0000000000000
++ fmuls 0010000000000001, fff8000000000000 => fff8000000000000
++ fmuls 3fe00094e0000359, 0010000000000001 => 0000000000000000
++ fmuls 3fe00094e0000359, 80100094e0000359 => 8000000000000000
++ fmuls 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
++ fmuls 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fmuls bfe0000000000001, 0010000000000001 => 8000000000000000
++ fmuls bfe0000000000001, 80100094e0000359 => 0000000000000000
++ fmuls bfe0000000000001, 7ff0000000000000 => fff0000000000000
++ fmuls bfe0000000000001, fff8000000000000 => fff8000000000000
++ fmuls 8000000000000000, 0010000000000001 => 8000000000000000
++ fmuls 8000000000000000, 80100094e0000359 => 0000000000000000
++ fmuls 8000000000000000, 7ff0000000000000 => 7ff8000000000000
++ fmuls 8000000000000000, fff8000000000000 => fff8000000000000
++ fmuls 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
++ fmuls 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
++ fmuls 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
++ fmuls 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
++ fmuls fff8000000000000, 0010000000000001 => fff8000000000000
++ fmuls fff8000000000000, 80100094e0000359 => fff8000000000000
++ fmuls fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fmuls fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fdiv 0010000000000001, 0010000000000001 => 3ff0000000000000
++ fdiv 0010000000000001, 80100094e0000359 => bfeffed64ad20d22
++ fdiv 0010000000000001, 7ff0000000000000 => 0000000000000000
++ fdiv 0010000000000001, fff8000000000000 => fff8000000000000
++ fdiv 3fe00094e0000359, 0010000000000001 => 7fc00094e0000358
++ fdiv 3fe00094e0000359, 80100094e0000359 => ffc0000000000000
++ fdiv 3fe00094e0000359, 7ff0000000000000 => 0000000000000000
++ fdiv 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fdiv bfe0000000000001, 0010000000000001 => ffc0000000000000
++ fdiv bfe0000000000001, 80100094e0000359 => 7fbffed64ad20d22
++ fdiv bfe0000000000001, 7ff0000000000000 => 8000000000000000
++ fdiv bfe0000000000001, fff8000000000000 => fff8000000000000
++ fdiv 8000000000000000, 0010000000000001 => 8000000000000000
++ fdiv 8000000000000000, 80100094e0000359 => 0000000000000000
++ fdiv 8000000000000000, 7ff0000000000000 => 8000000000000000
++ fdiv 8000000000000000, fff8000000000000 => fff8000000000000
++ fdiv 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
++ fdiv 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
++ fdiv 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
++ fdiv 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
++ fdiv fff8000000000000, 0010000000000001 => fff8000000000000
++ fdiv fff8000000000000, 80100094e0000359 => fff8000000000000
++ fdiv fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fdiv fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fdivs 0010000000000001, 0010000000000001 => 3ff0000000000000
++ fdivs 0010000000000001, 80100094e0000359 => bfeffed640000000
++ fdivs 0010000000000001, 7ff0000000000000 => 0000000000000000
++ fdivs 0010000000000001, fff8000000000000 => fff8000000000000
++ fdivs 3fe00094e0000359, 0010000000000001 => 7ff0000000000000
++ fdivs 3fe00094e0000359, 80100094e0000359 => fff0000000000000
++ fdivs 3fe00094e0000359, 7ff0000000000000 => 0000000000000000
++ fdivs 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fdivs bfe0000000000001, 0010000000000001 => fff0000000000000
++ fdivs bfe0000000000001, 80100094e0000359 => 7ff0000000000000
++ fdivs bfe0000000000001, 7ff0000000000000 => 8000000000000000
++ fdivs bfe0000000000001, fff8000000000000 => fff8000000000000
++ fdivs 8000000000000000, 0010000000000001 => 8000000000000000
++ fdivs 8000000000000000, 80100094e0000359 => 0000000000000000
++ fdivs 8000000000000000, 7ff0000000000000 => 8000000000000000
++ fdivs 8000000000000000, fff8000000000000 => fff8000000000000
++ fdivs 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
++ fdivs 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
++ fdivs 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
++ fdivs 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
++ fdivs fff8000000000000, 0010000000000001 => fff8000000000000
++ fdivs fff8000000000000, 80100094e0000359 => fff8000000000000
++ fdivs fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fdivs fff8000000000000, fff8000000000000 => fff8000000000000
++
++PPC floating point arith insns
++ with two args with flags update:
++ fadd. 0010000000000001, 0010000000000001 => 0020000000000001
++ fadd. 0010000000000001, 80100094e0000359 => 80000094e0000358
++ fadd. 0010000000000001, 7ff0000000000000 => 7ff0000000000000
++ fadd. 0010000000000001, fff8000000000000 => fff8000000000000
++ fadd. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359
++ fadd. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359
++ fadd. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
++ fadd. 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fadd. bfe0000000000001, 0010000000000001 => bfe0000000000001
++ fadd. bfe0000000000001, 80100094e0000359 => bfe0000000000001
++ fadd. bfe0000000000001, 7ff0000000000000 => 7ff0000000000000
++ fadd. bfe0000000000001, fff8000000000000 => fff8000000000000
++ fadd. 8000000000000000, 0010000000000001 => 0010000000000001
++ fadd. 8000000000000000, 80100094e0000359 => 80100094e0000359
++ fadd. 8000000000000000, 7ff0000000000000 => 7ff0000000000000
++ fadd. 8000000000000000, fff8000000000000 => fff8000000000000
++ fadd. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
++ fadd. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
++ fadd. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
++ fadd. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
++ fadd. fff8000000000000, 0010000000000001 => fff8000000000000
++ fadd. fff8000000000000, 80100094e0000359 => fff8000000000000
++ fadd. fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fadd. fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fadds. 0010000000000001, 0010000000000001 => 0000000000000000
++ fadds. 0010000000000001, 80100094e0000359 => 8000000000000000
++ fadds. 0010000000000001, 7ff0000000000000 => 7ff0000000000000
++ fadds. 0010000000000001, fff8000000000000 => fff8000000000000
++ fadds. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000
++ fadds. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000
++ fadds. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
++ fadds. 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fadds. bfe0000000000001, 0010000000000001 => bfe0000000000000
++ fadds. bfe0000000000001, 80100094e0000359 => bfe0000000000000
++ fadds. bfe0000000000001, 7ff0000000000000 => 7ff0000000000000
++ fadds. bfe0000000000001, fff8000000000000 => fff8000000000000
++ fadds. 8000000000000000, 0010000000000001 => 0000000000000000
++ fadds. 8000000000000000, 80100094e0000359 => 8000000000000000
++ fadds. 8000000000000000, 7ff0000000000000 => 7ff0000000000000
++ fadds. 8000000000000000, fff8000000000000 => fff8000000000000
++ fadds. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
++ fadds. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
++ fadds. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
++ fadds. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
++ fadds. fff8000000000000, 0010000000000001 => fff8000000000000
++ fadds. fff8000000000000, 80100094e0000359 => fff8000000000000
++ fadds. fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fadds. fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fsub. 0010000000000001, 0010000000000001 => 0000000000000000
++ fsub. 0010000000000001, 80100094e0000359 => 0020004a700001ad
++ fsub. 0010000000000001, 7ff0000000000000 => fff0000000000000
++ fsub. 0010000000000001, fff8000000000000 => fff8000000000000
++ fsub. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359
++ fsub. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359
++ fsub. 3fe00094e0000359, 7ff0000000000000 => fff0000000000000
++ fsub. 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fsub. bfe0000000000001, 0010000000000001 => bfe0000000000001
++ fsub. bfe0000000000001, 80100094e0000359 => bfe0000000000001
++ fsub. bfe0000000000001, 7ff0000000000000 => fff0000000000000
++ fsub. bfe0000000000001, fff8000000000000 => fff8000000000000
++ fsub. 8000000000000000, 0010000000000001 => 8010000000000001
++ fsub. 8000000000000000, 80100094e0000359 => 00100094e0000359
++ fsub. 8000000000000000, 7ff0000000000000 => fff0000000000000
++ fsub. 8000000000000000, fff8000000000000 => fff8000000000000
++ fsub. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
++ fsub. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
++ fsub. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
++ fsub. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
++ fsub. fff8000000000000, 0010000000000001 => fff8000000000000
++ fsub. fff8000000000000, 80100094e0000359 => fff8000000000000
++ fsub. fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fsub. fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fsubs. 0010000000000001, 0010000000000001 => 0000000000000000
++ fsubs. 0010000000000001, 80100094e0000359 => 0000000000000000
++ fsubs. 0010000000000001, 7ff0000000000000 => fff0000000000000
++ fsubs. 0010000000000001, fff8000000000000 => fff8000000000000
++ fsubs. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000
++ fsubs. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000
++ fsubs. 3fe00094e0000359, 7ff0000000000000 => fff0000000000000
++ fsubs. 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fsubs. bfe0000000000001, 0010000000000001 => bfe0000000000000
++ fsubs. bfe0000000000001, 80100094e0000359 => bfe0000000000000
++ fsubs. bfe0000000000001, 7ff0000000000000 => fff0000000000000
++ fsubs. bfe0000000000001, fff8000000000000 => fff8000000000000
++ fsubs. 8000000000000000, 0010000000000001 => 8000000000000000
++ fsubs. 8000000000000000, 80100094e0000359 => 0000000000000000
++ fsubs. 8000000000000000, 7ff0000000000000 => fff0000000000000
++ fsubs. 8000000000000000, fff8000000000000 => fff8000000000000
++ fsubs. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
++ fsubs. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
++ fsubs. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
++ fsubs. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
++ fsubs. fff8000000000000, 0010000000000001 => fff8000000000000
++ fsubs. fff8000000000000, 80100094e0000359 => fff8000000000000
++ fsubs. fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fsubs. fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fmul. 0010000000000001, 0010000000000001 => 0000000000000000
++ fmul. 0010000000000001, 80100094e0000359 => 8000000000000000
++ fmul. 0010000000000001, 7ff0000000000000 => 7ff0000000000000
++ fmul. 0010000000000001, fff8000000000000 => fff8000000000000
++ fmul. 3fe00094e0000359, 0010000000000001 => 0008004a700001ad
++ fmul. 3fe00094e0000359, 80100094e0000359 => 80080094e2b4a179
++ fmul. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
++ fmul. 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fmul. bfe0000000000001, 0010000000000001 => 8008000000000001
++ fmul. bfe0000000000001, 80100094e0000359 => 0008004a700001ad
++ fmul. bfe0000000000001, 7ff0000000000000 => fff0000000000000
++ fmul. bfe0000000000001, fff8000000000000 => fff8000000000000
++ fmul. 8000000000000000, 0010000000000001 => 8000000000000000
++ fmul. 8000000000000000, 80100094e0000359 => 0000000000000000
++ fmul. 8000000000000000, 7ff0000000000000 => 7ff8000000000000
++ fmul. 8000000000000000, fff8000000000000 => fff8000000000000
++ fmul. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
++ fmul. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
++ fmul. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
++ fmul. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
++ fmul. fff8000000000000, 0010000000000001 => fff8000000000000
++ fmul. fff8000000000000, 80100094e0000359 => fff8000000000000
++ fmul. fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fmul. fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fmuls. 0010000000000001, 0010000000000001 => 0000000000000000
++ fmuls. 0010000000000001, 80100094e0000359 => 8000000000000000
++ fmuls. 0010000000000001, 7ff0000000000000 => 7ff0000000000000
++ fmuls. 0010000000000001, fff8000000000000 => fff8000000000000
++ fmuls. 3fe00094e0000359, 0010000000000001 => 0000000000000000
++ fmuls. 3fe00094e0000359, 80100094e0000359 => 8000000000000000
++ fmuls. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
++ fmuls. 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fmuls. bfe0000000000001, 0010000000000001 => 8000000000000000
++ fmuls. bfe0000000000001, 80100094e0000359 => 0000000000000000
++ fmuls. bfe0000000000001, 7ff0000000000000 => fff0000000000000
++ fmuls. bfe0000000000001, fff8000000000000 => fff8000000000000
++ fmuls. 8000000000000000, 0010000000000001 => 8000000000000000
++ fmuls. 8000000000000000, 80100094e0000359 => 0000000000000000
++ fmuls. 8000000000000000, 7ff0000000000000 => 7ff8000000000000
++ fmuls. 8000000000000000, fff8000000000000 => fff8000000000000
++ fmuls. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
++ fmuls. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
++ fmuls. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
++ fmuls. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
++ fmuls. fff8000000000000, 0010000000000001 => fff8000000000000
++ fmuls. fff8000000000000, 80100094e0000359 => fff8000000000000
++ fmuls. fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fmuls. fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fdiv. 0010000000000001, 0010000000000001 => 3ff0000000000000
++ fdiv. 0010000000000001, 80100094e0000359 => bfeffed64ad20d22
++ fdiv. 0010000000000001, 7ff0000000000000 => 0000000000000000
++ fdiv. 0010000000000001, fff8000000000000 => fff8000000000000
++ fdiv. 3fe00094e0000359, 0010000000000001 => 7fc00094e0000358
++ fdiv. 3fe00094e0000359, 80100094e0000359 => ffc0000000000000
++ fdiv. 3fe00094e0000359, 7ff0000000000000 => 0000000000000000
++ fdiv. 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fdiv. bfe0000000000001, 0010000000000001 => ffc0000000000000
++ fdiv. bfe0000000000001, 80100094e0000359 => 7fbffed64ad20d22
++ fdiv. bfe0000000000001, 7ff0000000000000 => 8000000000000000
++ fdiv. bfe0000000000001, fff8000000000000 => fff8000000000000
++ fdiv. 8000000000000000, 0010000000000001 => 8000000000000000
++ fdiv. 8000000000000000, 80100094e0000359 => 0000000000000000
++ fdiv. 8000000000000000, 7ff0000000000000 => 8000000000000000
++ fdiv. 8000000000000000, fff8000000000000 => fff8000000000000
++ fdiv. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
++ fdiv. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
++ fdiv. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
++ fdiv. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
++ fdiv. fff8000000000000, 0010000000000001 => fff8000000000000
++ fdiv. fff8000000000000, 80100094e0000359 => fff8000000000000
++ fdiv. fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fdiv. fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fdivs. 0010000000000001, 0010000000000001 => 3ff0000000000000
++ fdivs. 0010000000000001, 80100094e0000359 => bfeffed640000000
++ fdivs. 0010000000000001, 7ff0000000000000 => 0000000000000000
++ fdivs. 0010000000000001, fff8000000000000 => fff8000000000000
++ fdivs. 3fe00094e0000359, 0010000000000001 => 7ff0000000000000
++ fdivs. 3fe00094e0000359, 80100094e0000359 => fff0000000000000
++ fdivs. 3fe00094e0000359, 7ff0000000000000 => 0000000000000000
++ fdivs. 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fdivs. bfe0000000000001, 0010000000000001 => fff0000000000000
++ fdivs. bfe0000000000001, 80100094e0000359 => 7ff0000000000000
++ fdivs. bfe0000000000001, 7ff0000000000000 => 8000000000000000
++ fdivs. bfe0000000000001, fff8000000000000 => fff8000000000000
++ fdivs. 8000000000000000, 0010000000000001 => 8000000000000000
++ fdivs. 8000000000000000, 80100094e0000359 => 0000000000000000
++ fdivs. 8000000000000000, 7ff0000000000000 => 8000000000000000
++ fdivs. 8000000000000000, fff8000000000000 => fff8000000000000
++ fdivs. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
++ fdivs. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
++ fdivs. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
++ fdivs. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
++ fdivs. fff8000000000000, 0010000000000001 => fff8000000000000
++ fdivs. fff8000000000000, 80100094e0000359 => fff8000000000000
++ fdivs. fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fdivs. fff8000000000000, fff8000000000000 => fff8000000000000
++
++PPC floating point compare insns (two args):
++ fcmpo 0010000000000001, 0010000000000001 => fff8000000000000
++ fcmpo 0010000000000001, 80100094e0000359 => fff8000000000000
++ fcmpo 0010000000000001, 7ff0000000000000 => fff8000000000000
++ fcmpo 0010000000000001, fff8000000000000 => fff8000000000000
++ fcmpo 3fe00094e0000359, 0010000000000001 => fff8000000000000
++ fcmpo 3fe00094e0000359, 80100094e0000359 => fff8000000000000
++ fcmpo 3fe00094e0000359, 7ff0000000000000 => fff8000000000000
++ fcmpo 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fcmpo bfe0000000000001, 0010000000000001 => fff8000000000000
++ fcmpo bfe0000000000001, 80100094e0000359 => fff8000000000000
++ fcmpo bfe0000000000001, 7ff0000000000000 => fff8000000000000
++ fcmpo bfe0000000000001, fff8000000000000 => fff8000000000000
++ fcmpo 8000000000000000, 0010000000000001 => fff8000000000000
++ fcmpo 8000000000000000, 80100094e0000359 => fff8000000000000
++ fcmpo 8000000000000000, 7ff0000000000000 => fff8000000000000
++ fcmpo 8000000000000000, fff8000000000000 => fff8000000000000
++ fcmpo 7ff7ffffffffffff, 0010000000000001 => fff8000000000000
++ fcmpo 7ff7ffffffffffff, 80100094e0000359 => fff8000000000000
++ fcmpo 7ff7ffffffffffff, 7ff0000000000000 => fff8000000000000
++ fcmpo 7ff7ffffffffffff, fff8000000000000 => fff8000000000000
++ fcmpo fff8000000000000, 0010000000000001 => fff8000000000000
++ fcmpo fff8000000000000, 80100094e0000359 => fff8000000000000
++ fcmpo fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fcmpo fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fcmpu 0010000000000001, 0010000000000001 => fff8000000000000
++ fcmpu 0010000000000001, 80100094e0000359 => fff8000000000000
++ fcmpu 0010000000000001, 7ff0000000000000 => fff8000000000000
++ fcmpu 0010000000000001, fff8000000000000 => fff8000000000000
++ fcmpu 3fe00094e0000359, 0010000000000001 => fff8000000000000
++ fcmpu 3fe00094e0000359, 80100094e0000359 => fff8000000000000
++ fcmpu 3fe00094e0000359, 7ff0000000000000 => fff8000000000000
++ fcmpu 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fcmpu bfe0000000000001, 0010000000000001 => fff8000000000000
++ fcmpu bfe0000000000001, 80100094e0000359 => fff8000000000000
++ fcmpu bfe0000000000001, 7ff0000000000000 => fff8000000000000
++ fcmpu bfe0000000000001, fff8000000000000 => fff8000000000000
++ fcmpu 8000000000000000, 0010000000000001 => fff8000000000000
++ fcmpu 8000000000000000, 80100094e0000359 => fff8000000000000
++ fcmpu 8000000000000000, 7ff0000000000000 => fff8000000000000
++ fcmpu 8000000000000000, fff8000000000000 => fff8000000000000
++ fcmpu 7ff7ffffffffffff, 0010000000000001 => fff8000000000000
++ fcmpu 7ff7ffffffffffff, 80100094e0000359 => fff8000000000000
++ fcmpu 7ff7ffffffffffff, 7ff0000000000000 => fff8000000000000
++ fcmpu 7ff7ffffffffffff, fff8000000000000 => fff8000000000000
++ fcmpu fff8000000000000, 0010000000000001 => fff8000000000000
++ fcmpu fff8000000000000, 80100094e0000359 => fff8000000000000
++ fcmpu fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fcmpu fff8000000000000, fff8000000000000 => fff8000000000000
++
++PPC floating point arith insns with one arg:
++ fres 0010000000000001 => 7ff0000000000000
++ fres 00100094e0000359 => 7ff0000000000000
++ fres 3fe0000000000001 => 3ffff00000000000
++ fres 3fe00094e0000359 => 3ffff00000000000
++ fres 8010000000000001 => fff0000000000000
++ fres 80100094e0000359 => fff0000000000000
++ fres bfe0000000000001 => bffff00000000000
++ fres bfe00094e0000359 => bffff00000000000
++ fres 0000000000000000 => 7ff0000000000000
++ fres 8000000000000000 => fff0000000000000
++ fres 7ff0000000000000 => 0000000000000000
++ fres fff0000000000000 => 8000000000000000
++ fres 7ff7ffffffffffff => 7ffff00000000000
++ fres fff7ffffffffffff => fffff00000000000
++ fres 7ff8000000000000 => 7ff8000000000000
++ fres fff8000000000000 => fff8000000000000
++
++ frsqrte 0010000000000001 => 5fdf000000000000
++ frsqrte 00100094e0000359 => 5fdf000000000000
++ frsqrte 3fe0000000000001 => 3ff6000000000000
++ frsqrte 3fe00094e0000359 => 3ff6000000000000
++ frsqrte 8010000000000001 => 7ff8000000000000
++ frsqrte 80100094e0000359 => 7ff8000000000000
++ frsqrte bfe0000000000001 => 7ff8000000000000
++ frsqrte bfe00094e0000359 => 7ff8000000000000
++ frsqrte 0000000000000000 => 7ff0000000000000
++ frsqrte 8000000000000000 => fff0000000000000
++ frsqrte 7ff0000000000000 => 0000000000000000
++ frsqrte fff0000000000000 => 7ff8000000000000
++ frsqrte 7ff7ffffffffffff => 7fff000000000000
++ frsqrte fff7ffffffffffff => ffff000000000000
++ frsqrte 7ff8000000000000 => 7ff8000000000000
++ frsqrte fff8000000000000 => fff8000000000000
++
++ frsp 0010000000000001 => 0000000000000000
++ frsp 00100094e0000359 => 0000000000000000
++ frsp 3fe0000000000001 => 3fe0000000000000
++ frsp 3fe00094e0000359 => 3fe00094e0000000
++ frsp 8010000000000001 => 8000000000000000
++ frsp 80100094e0000359 => 8000000000000000
++ frsp bfe0000000000001 => bfe0000000000000
++ frsp bfe00094e0000359 => bfe00094e0000000
++ frsp 0000000000000000 => 0000000000000000
++ frsp 8000000000000000 => 8000000000000000
++ frsp 7ff0000000000000 => 7ff0000000000000
++ frsp fff0000000000000 => fff0000000000000
++ frsp 7ff7ffffffffffff => 7fffffffe0000000
++ frsp fff7ffffffffffff => ffffffffe0000000
++ frsp 7ff8000000000000 => 7ff8000000000000
++ frsp fff8000000000000 => fff8000000000000
++
++ fctiw 0010000000000001 => 0000000000000000
++ fctiw 00100094e0000359 => 0000000000000000
++ fctiw 3fe0000000000001 => 0000000000000001
++ fctiw 3fe00094e0000359 => 0000000000000001
++ fctiw 8010000000000001 => 0000000000000000
++ fctiw 80100094e0000359 => 0000000000000000
++ fctiw bfe0000000000001 => 00000000ffffffff
++ fctiw bfe00094e0000359 => 00000000ffffffff
++ fctiw 0000000000000000 => 0000000000000000
++ fctiw 8000000000000000 => 0000000000000000
++ fctiw 7ff0000000000000 => 000000007fffffff
++ fctiw fff0000000000000 => 0000000080000000
++ fctiw 7ff7ffffffffffff => 0000000080000000
++ fctiw fff7ffffffffffff => 0000000080000000
++ fctiw 7ff8000000000000 => 0000000080000000
++ fctiw fff8000000000000 => 0000000080000000
++
++ fctiwz 0010000000000001 => 0000000000000000
++ fctiwz 00100094e0000359 => 0000000000000000
++ fctiwz 3fe0000000000001 => 0000000000000000
++ fctiwz 3fe00094e0000359 => 0000000000000000
++ fctiwz 8010000000000001 => 0000000000000000
++ fctiwz 80100094e0000359 => 0000000000000000
++ fctiwz bfe0000000000001 => 0000000000000000
++ fctiwz bfe00094e0000359 => 0000000000000000
++ fctiwz 0000000000000000 => 0000000000000000
++ fctiwz 8000000000000000 => 0000000000000000
++ fctiwz 7ff0000000000000 => 000000007fffffff
++ fctiwz fff0000000000000 => 0000000080000000
++ fctiwz 7ff7ffffffffffff => 0000000080000000
++ fctiwz fff7ffffffffffff => 0000000080000000
++ fctiwz 7ff8000000000000 => 0000000080000000
++ fctiwz fff8000000000000 => 0000000080000000
++
++ fmr 0010000000000001 => 0010000000000001
++ fmr 00100094e0000359 => 00100094e0000359
++ fmr 3fe0000000000001 => 3fe0000000000001
++ fmr 3fe00094e0000359 => 3fe00094e0000359
++ fmr 8010000000000001 => 8010000000000001
++ fmr 80100094e0000359 => 80100094e0000359
++ fmr bfe0000000000001 => bfe0000000000001
++ fmr bfe00094e0000359 => bfe00094e0000359
++ fmr 0000000000000000 => 0000000000000000
++ fmr 8000000000000000 => 8000000000000000
++ fmr 7ff0000000000000 => 7ff0000000000000
++ fmr fff0000000000000 => fff0000000000000
++ fmr 7ff7ffffffffffff => 7ff7ffffffffffff
++ fmr fff7ffffffffffff => fff7ffffffffffff
++ fmr 7ff8000000000000 => 7ff8000000000000
++ fmr fff8000000000000 => fff8000000000000
++
++ fneg 0010000000000001 => 8010000000000001
++ fneg 00100094e0000359 => 80100094e0000359
++ fneg 3fe0000000000001 => bfe0000000000001
++ fneg 3fe00094e0000359 => bfe00094e0000359
++ fneg 8010000000000001 => 0010000000000001
++ fneg 80100094e0000359 => 00100094e0000359
++ fneg bfe0000000000001 => 3fe0000000000001
++ fneg bfe00094e0000359 => 3fe00094e0000359
++ fneg 0000000000000000 => 8000000000000000
++ fneg 8000000000000000 => 0000000000000000
++ fneg 7ff0000000000000 => fff0000000000000
++ fneg fff0000000000000 => 7ff0000000000000
++ fneg 7ff7ffffffffffff => fff7ffffffffffff
++ fneg fff7ffffffffffff => 7ff7ffffffffffff
++ fneg 7ff8000000000000 => fff8000000000000
++ fneg fff8000000000000 => 7ff8000000000000
++
++ fabs 0010000000000001 => 0010000000000001
++ fabs 00100094e0000359 => 00100094e0000359
++ fabs 3fe0000000000001 => 3fe0000000000001
++ fabs 3fe00094e0000359 => 3fe00094e0000359
++ fabs 8010000000000001 => 0010000000000001
++ fabs 80100094e0000359 => 00100094e0000359
++ fabs bfe0000000000001 => 3fe0000000000001
++ fabs bfe00094e0000359 => 3fe00094e0000359
++ fabs 0000000000000000 => 0000000000000000
++ fabs 8000000000000000 => 0000000000000000
++ fabs 7ff0000000000000 => 7ff0000000000000
++ fabs fff0000000000000 => 7ff0000000000000
++ fabs 7ff7ffffffffffff => 7ff7ffffffffffff
++ fabs fff7ffffffffffff => 7ff7ffffffffffff
++ fabs 7ff8000000000000 => 7ff8000000000000
++ fabs fff8000000000000 => 7ff8000000000000
++
++ fnabs 0010000000000001 => 8010000000000001
++ fnabs 00100094e0000359 => 80100094e0000359
++ fnabs 3fe0000000000001 => bfe0000000000001
++ fnabs 3fe00094e0000359 => bfe00094e0000359
++ fnabs 8010000000000001 => 8010000000000001
++ fnabs 80100094e0000359 => 80100094e0000359
++ fnabs bfe0000000000001 => bfe0000000000001
++ fnabs bfe00094e0000359 => bfe00094e0000359
++ fnabs 0000000000000000 => 8000000000000000
++ fnabs 8000000000000000 => 8000000000000000
++ fnabs 7ff0000000000000 => fff0000000000000
++ fnabs fff0000000000000 => fff0000000000000
++ fnabs 7ff7ffffffffffff => fff7ffffffffffff
++ fnabs fff7ffffffffffff => fff7ffffffffffff
++ fnabs 7ff8000000000000 => fff8000000000000
++ fnabs fff8000000000000 => fff8000000000000
++
++ fsqrt 0010000000000001 => 2000000000000000
++ fsqrt 00100094e0000359 => 2000004a6f52dd4a
++ fsqrt 3fe0000000000001 => 3fe6a09e667f3bcd
++ fsqrt 3fe00094e0000359 => 3fe6a107aacb50df
++ fsqrt 8010000000000001 => 7ff8000000000000
++ fsqrt 80100094e0000359 => 7ff8000000000000
++ fsqrt bfe0000000000001 => 7ff8000000000000
++ fsqrt bfe00094e0000359 => 7ff8000000000000
++ fsqrt 0000000000000000 => 0000000000000000
++ fsqrt 8000000000000000 => 8000000000000000
++ fsqrt 7ff0000000000000 => 7ff0000000000000
++ fsqrt fff0000000000000 => 7ff8000000000000
++ fsqrt 7ff7ffffffffffff => 7fffffffffffffff
++ fsqrt fff7ffffffffffff => ffffffffffffffff
++ fsqrt 7ff8000000000000 => 7ff8000000000000
++ fsqrt fff8000000000000 => fff8000000000000
++
++ fcfid 0010000000000001 => 4330000000000001
++ fcfid 00100094e0000359 => 43300094e0000359
++ fcfid 3fe0000000000001 => 43cff00000000000
++ fcfid 3fe00094e0000359 => 43cff0004a700002
++ fcfid 8010000000000001 => c3dffc0000000000
++ fcfid 80100094e0000359 => c3dffbffdac7ffff
++ fcfid bfe0000000000001 => c3d0080000000000
++ fcfid bfe00094e0000359 => c3d007ffdac7ffff
++ fcfid 0000000000000000 => 0000000000000000
++ fcfid 8000000000000000 => c3e0000000000000
++ fcfid 7ff0000000000000 => 43dffc0000000000
++ fcfid fff0000000000000 => c330000000000000
++ fcfid 7ff7ffffffffffff => 43dffe0000000000
++ fcfid fff7ffffffffffff => c320000000000002
++ fcfid 7ff8000000000000 => 43dffe0000000000
++ fcfid fff8000000000000 => c320000000000000
++
++ fctid 0010000000000001 => 0000000000000000
++ fctid 00100094e0000359 => 0000000000000000
++ fctid 3fe0000000000001 => 0000000000000001
++ fctid 3fe00094e0000359 => 0000000000000001
++ fctid 8010000000000001 => 0000000000000000
++ fctid 80100094e0000359 => 0000000000000000
++ fctid bfe0000000000001 => ffffffffffffffff
++ fctid bfe00094e0000359 => ffffffffffffffff
++ fctid 0000000000000000 => 0000000000000000
++ fctid 8000000000000000 => 0000000000000000
++ fctid 7ff0000000000000 => 7fffffffffffffff
++ fctid fff0000000000000 => 8000000000000000
++ fctid 7ff7ffffffffffff => 8000000000000000
++ fctid fff7ffffffffffff => 8000000000000000
++ fctid 7ff8000000000000 => 8000000000000000
++ fctid fff8000000000000 => 8000000000000000
++
++ fctidz 0010000000000001 => 0000000000000000
++ fctidz 00100094e0000359 => 0000000000000000
++ fctidz 3fe0000000000001 => 0000000000000000
++ fctidz 3fe00094e0000359 => 0000000000000000
++ fctidz 8010000000000001 => 0000000000000000
++ fctidz 80100094e0000359 => 0000000000000000
++ fctidz bfe0000000000001 => 0000000000000000
++ fctidz bfe00094e0000359 => 0000000000000000
++ fctidz 0000000000000000 => 0000000000000000
++ fctidz 8000000000000000 => 0000000000000000
++ fctidz 7ff0000000000000 => 7fffffffffffffff
++ fctidz fff0000000000000 => 8000000000000000
++ fctidz 7ff7ffffffffffff => 8000000000000000
++ fctidz fff7ffffffffffff => 8000000000000000
++ fctidz 7ff8000000000000 => 8000000000000000
++ fctidz fff8000000000000 => 8000000000000000
++
++PPC floating point arith insns
++ with one arg with flags update:
++ fres. 0010000000000001 => 7ff0000000000000
++ fres. 00100094e0000359 => 7ff0000000000000
++ fres. 3fe0000000000001 => 3ffff00000000000
++ fres. 3fe00094e0000359 => 3ffff00000000000
++ fres. 8010000000000001 => fff0000000000000
++ fres. 80100094e0000359 => fff0000000000000
++ fres. bfe0000000000001 => bffff00000000000
++ fres. bfe00094e0000359 => bffff00000000000
++ fres. 0000000000000000 => 7ff0000000000000
++ fres. 8000000000000000 => fff0000000000000
++ fres. 7ff0000000000000 => 0000000000000000
++ fres. fff0000000000000 => 8000000000000000
++ fres. 7ff7ffffffffffff => 7ffff00000000000
++ fres. fff7ffffffffffff => fffff00000000000
++ fres. 7ff8000000000000 => 7ff8000000000000
++ fres. fff8000000000000 => fff8000000000000
++
++ frsqrte. 0010000000000001 => 5fdf000000000000
++ frsqrte. 00100094e0000359 => 5fdf000000000000
++ frsqrte. 3fe0000000000001 => 3ff6000000000000
++ frsqrte. 3fe00094e0000359 => 3ff6000000000000
++ frsqrte. 8010000000000001 => 7ff8000000000000
++ frsqrte. 80100094e0000359 => 7ff8000000000000
++ frsqrte. bfe0000000000001 => 7ff8000000000000
++ frsqrte. bfe00094e0000359 => 7ff8000000000000
++ frsqrte. 0000000000000000 => 7ff0000000000000
++ frsqrte. 8000000000000000 => fff0000000000000
++ frsqrte. 7ff0000000000000 => 0000000000000000
++ frsqrte. fff0000000000000 => 7ff8000000000000
++ frsqrte. 7ff7ffffffffffff => 7fff000000000000
++ frsqrte. fff7ffffffffffff => ffff000000000000
++ frsqrte. 7ff8000000000000 => 7ff8000000000000
++ frsqrte. fff8000000000000 => fff8000000000000
++
++ frsp. 0010000000000001 => 0000000000000000
++ frsp. 00100094e0000359 => 0000000000000000
++ frsp. 3fe0000000000001 => 3fe0000000000000
++ frsp. 3fe00094e0000359 => 3fe00094e0000000
++ frsp. 8010000000000001 => 8000000000000000
++ frsp. 80100094e0000359 => 8000000000000000
++ frsp. bfe0000000000001 => bfe0000000000000
++ frsp. bfe00094e0000359 => bfe00094e0000000
++ frsp. 0000000000000000 => 0000000000000000
++ frsp. 8000000000000000 => 8000000000000000
++ frsp. 7ff0000000000000 => 7ff0000000000000
++ frsp. fff0000000000000 => fff0000000000000
++ frsp. 7ff7ffffffffffff => 7fffffffe0000000
++ frsp. fff7ffffffffffff => ffffffffe0000000
++ frsp. 7ff8000000000000 => 7ff8000000000000
++ frsp. fff8000000000000 => fff8000000000000
++
++ fctiw. 0010000000000001 => 0000000000000000
++ fctiw. 00100094e0000359 => 0000000000000000
++ fctiw. 3fe0000000000001 => 0000000000000001
++ fctiw. 3fe00094e0000359 => 0000000000000001
++ fctiw. 8010000000000001 => 0000000000000000
++ fctiw. 80100094e0000359 => 0000000000000000
++ fctiw. bfe0000000000001 => 00000000ffffffff
++ fctiw. bfe00094e0000359 => 00000000ffffffff
++ fctiw. 0000000000000000 => 0000000000000000
++ fctiw. 8000000000000000 => 0000000000000000
++ fctiw. 7ff0000000000000 => 000000007fffffff
++ fctiw. fff0000000000000 => 0000000080000000
++ fctiw. 7ff7ffffffffffff => 0000000080000000
++ fctiw. fff7ffffffffffff => 0000000080000000
++ fctiw. 7ff8000000000000 => 0000000080000000
++ fctiw. fff8000000000000 => 0000000080000000
++
++ fctiwz. 0010000000000001 => 0000000000000000
++ fctiwz. 00100094e0000359 => 0000000000000000
++ fctiwz. 3fe0000000000001 => 0000000000000000
++ fctiwz. 3fe00094e0000359 => 0000000000000000
++ fctiwz. 8010000000000001 => 0000000000000000
++ fctiwz. 80100094e0000359 => 0000000000000000
++ fctiwz. bfe0000000000001 => 0000000000000000
++ fctiwz. bfe00094e0000359 => 0000000000000000
++ fctiwz. 0000000000000000 => 0000000000000000
++ fctiwz. 8000000000000000 => 0000000000000000
++ fctiwz. 7ff0000000000000 => 000000007fffffff
++ fctiwz. fff0000000000000 => 0000000080000000
++ fctiwz. 7ff7ffffffffffff => 0000000080000000
++ fctiwz. fff7ffffffffffff => 0000000080000000
++ fctiwz. 7ff8000000000000 => 0000000080000000
++ fctiwz. fff8000000000000 => 0000000080000000
++
++ fmr. 0010000000000001 => 0010000000000001
++ fmr. 00100094e0000359 => 00100094e0000359
++ fmr. 3fe0000000000001 => 3fe0000000000001
++ fmr. 3fe00094e0000359 => 3fe00094e0000359
++ fmr. 8010000000000001 => 8010000000000001
++ fmr. 80100094e0000359 => 80100094e0000359
++ fmr. bfe0000000000001 => bfe0000000000001
++ fmr. bfe00094e0000359 => bfe00094e0000359
++ fmr. 0000000000000000 => 0000000000000000
++ fmr. 8000000000000000 => 8000000000000000
++ fmr. 7ff0000000000000 => 7ff0000000000000
++ fmr. fff0000000000000 => fff0000000000000
++ fmr. 7ff7ffffffffffff => 7ff7ffffffffffff
++ fmr. fff7ffffffffffff => fff7ffffffffffff
++ fmr. 7ff8000000000000 => 7ff8000000000000
++ fmr. fff8000000000000 => fff8000000000000
++
++ fneg. 0010000000000001 => 8010000000000001
++ fneg. 00100094e0000359 => 80100094e0000359
++ fneg. 3fe0000000000001 => bfe0000000000001
++ fneg. 3fe00094e0000359 => bfe00094e0000359
++ fneg. 8010000000000001 => 0010000000000001
++ fneg. 80100094e0000359 => 00100094e0000359
++ fneg. bfe0000000000001 => 3fe0000000000001
++ fneg. bfe00094e0000359 => 3fe00094e0000359
++ fneg. 0000000000000000 => 8000000000000000
++ fneg. 8000000000000000 => 0000000000000000
++ fneg. 7ff0000000000000 => fff0000000000000
++ fneg. fff0000000000000 => 7ff0000000000000
++ fneg. 7ff7ffffffffffff => fff7ffffffffffff
++ fneg. fff7ffffffffffff => 7ff7ffffffffffff
++ fneg. 7ff8000000000000 => fff8000000000000
++ fneg. fff8000000000000 => 7ff8000000000000
++
++ fabs. 0010000000000001 => 0010000000000001
++ fabs. 00100094e0000359 => 00100094e0000359
++ fabs. 3fe0000000000001 => 3fe0000000000001
++ fabs. 3fe00094e0000359 => 3fe00094e0000359
++ fabs. 8010000000000001 => 0010000000000001
++ fabs. 80100094e0000359 => 00100094e0000359
++ fabs. bfe0000000000001 => 3fe0000000000001
++ fabs. bfe00094e0000359 => 3fe00094e0000359
++ fabs. 0000000000000000 => 0000000000000000
++ fabs. 8000000000000000 => 0000000000000000
++ fabs. 7ff0000000000000 => 7ff0000000000000
++ fabs. fff0000000000000 => 7ff0000000000000
++ fabs. 7ff7ffffffffffff => 7ff7ffffffffffff
++ fabs. fff7ffffffffffff => 7ff7ffffffffffff
++ fabs. 7ff8000000000000 => 7ff8000000000000
++ fabs. fff8000000000000 => 7ff8000000000000
++
++ fnabs. 0010000000000001 => 8010000000000001
++ fnabs. 00100094e0000359 => 80100094e0000359
++ fnabs. 3fe0000000000001 => bfe0000000000001
++ fnabs. 3fe00094e0000359 => bfe00094e0000359
++ fnabs. 8010000000000001 => 8010000000000001
++ fnabs. 80100094e0000359 => 80100094e0000359
++ fnabs. bfe0000000000001 => bfe0000000000001
++ fnabs. bfe00094e0000359 => bfe00094e0000359
++ fnabs. 0000000000000000 => 8000000000000000
++ fnabs. 8000000000000000 => 8000000000000000
++ fnabs. 7ff0000000000000 => fff0000000000000
++ fnabs. fff0000000000000 => fff0000000000000
++ fnabs. 7ff7ffffffffffff => fff7ffffffffffff
++ fnabs. fff7ffffffffffff => fff7ffffffffffff
++ fnabs. 7ff8000000000000 => fff8000000000000
++ fnabs. fff8000000000000 => fff8000000000000
++
++ fcfid. 0010000000000001 => 4330000000000001
++ fcfid. 00100094e0000359 => 43300094e0000359
++ fcfid. 3fe0000000000001 => 43cff00000000000
++ fcfid. 3fe00094e0000359 => 43cff0004a700002
++ fcfid. 8010000000000001 => c3dffc0000000000
++ fcfid. 80100094e0000359 => c3dffbffdac7ffff
++ fcfid. bfe0000000000001 => c3d0080000000000
++ fcfid. bfe00094e0000359 => c3d007ffdac7ffff
++ fcfid. 0000000000000000 => 0000000000000000
++ fcfid. 8000000000000000 => c3e0000000000000
++ fcfid. 7ff0000000000000 => 43dffc0000000000
++ fcfid. fff0000000000000 => c330000000000000
++ fcfid. 7ff7ffffffffffff => 43dffe0000000000
++ fcfid. fff7ffffffffffff => c320000000000002
++ fcfid. 7ff8000000000000 => 43dffe0000000000
++ fcfid. fff8000000000000 => c320000000000000
++
++ fctid. 0010000000000001 => 0000000000000000
++ fctid. 00100094e0000359 => 0000000000000000
++ fctid. 3fe0000000000001 => 0000000000000001
++ fctid. 3fe00094e0000359 => 0000000000000001
++ fctid. 8010000000000001 => 0000000000000000
++ fctid. 80100094e0000359 => 0000000000000000
++ fctid. bfe0000000000001 => ffffffffffffffff
++ fctid. bfe00094e0000359 => ffffffffffffffff
++ fctid. 0000000000000000 => 0000000000000000
++ fctid. 8000000000000000 => 0000000000000000
++ fctid. 7ff0000000000000 => 7fffffffffffffff
++ fctid. fff0000000000000 => 8000000000000000
++ fctid. 7ff7ffffffffffff => 8000000000000000
++ fctid. fff7ffffffffffff => 8000000000000000
++ fctid. 7ff8000000000000 => 8000000000000000
++ fctid. fff8000000000000 => 8000000000000000
++
++ fctidz. 0010000000000001 => 0000000000000000
++ fctidz. 00100094e0000359 => 0000000000000000
++ fctidz. 3fe0000000000001 => 0000000000000000
++ fctidz. 3fe00094e0000359 => 0000000000000000
++ fctidz. 8010000000000001 => 0000000000000000
++ fctidz. 80100094e0000359 => 0000000000000000
++ fctidz. bfe0000000000001 => 0000000000000000
++ fctidz. bfe00094e0000359 => 0000000000000000
++ fctidz. 0000000000000000 => 0000000000000000
++ fctidz. 8000000000000000 => 0000000000000000
++ fctidz. 7ff0000000000000 => 7fffffffffffffff
++ fctidz. fff0000000000000 => 8000000000000000
++ fctidz. 7ff7ffffffffffff => 8000000000000000
++ fctidz. fff7ffffffffffff => 8000000000000000
++ fctidz. 7ff8000000000000 => 8000000000000000
++ fctidz. fff8000000000000 => 8000000000000000
++
++PPC floating point status register manipulation insns:
++PPC floating point status register manipulation insns
++ with flags update:
++PPC float load insns
++ with one register + one 16 bits immediate args with flags update:
++ lfs 0010000000000001, 65416 => 36a0000000000000, 0
++ lfs 00100094e0000359, 65424 => c400006b20000000, 0
++ lfs 3fe0000000000001, 65432 => 36a0000000000000, 0
++ lfs 3fe00094e0000359, 65440 => c400006b20000000, 0
++ lfs 8010000000000001, 65448 => 36a0000000000000, 0
++ lfs 80100094e0000359, 65456 => c400006b20000000, 0
++ lfs bfe0000000000001, 65464 => 36a0000000000000, 0
++ lfs bfe00094e0000359, 65472 => c400006b20000000, 0
++ lfs 0000000000000000, 65480 => 0000000000000000, 0
++ lfs 8000000000000000, 65488 => 0000000000000000, 0
++ lfs 7ff0000000000000, 65496 => 0000000000000000, 0
++ lfs fff0000000000000, 65504 => 0000000000000000, 0
++ lfs 7ff7ffffffffffff, 65512 => ffffffffe0000000, 0
++ lfs fff7ffffffffffff, 65520 => ffffffffe0000000, 0
++ lfs 7ff8000000000000, 65528 => 0000000000000000, 0
++ lfs 0010000000000001, 0 => 36a0000000000000, 0
++ lfs 00100094e0000359, 8 => c400006b20000000, 0
++ lfs 3fe0000000000001, 16 => 36a0000000000000, 0
++ lfs 3fe00094e0000359, 24 => c400006b20000000, 0
++ lfs 8010000000000001, 32 => 36a0000000000000, 0
++ lfs 80100094e0000359, 40 => c400006b20000000, 0
++ lfs bfe0000000000001, 48 => 36a0000000000000, 0
++ lfs bfe00094e0000359, 56 => c400006b20000000, 0
++ lfs 0000000000000000, 64 => 0000000000000000, 0
++ lfs 8000000000000000, 72 => 0000000000000000, 0
++ lfs 7ff0000000000000, 80 => 0000000000000000, 0
++ lfs fff0000000000000, 88 => 0000000000000000, 0
++ lfs 7ff7ffffffffffff, 96 => ffffffffe0000000, 0
++ lfs fff7ffffffffffff, 104 => ffffffffe0000000, 0
++ lfs 7ff8000000000000, 112 => 0000000000000000, 0
++ lfs fff8000000000000, 120 => 0000000000000000, 0
++
++ lfsu 0010000000000001, 65416 => 36a0000000000000, -120
++ lfsu 00100094e0000359, 65424 => c400006b20000000, -112
++ lfsu 3fe0000000000001, 65432 => 36a0000000000000, -104
++ lfsu 3fe00094e0000359, 65440 => c400006b20000000, -96
++ lfsu 8010000000000001, 65448 => 36a0000000000000, -88
++ lfsu 80100094e0000359, 65456 => c400006b20000000, -80
++ lfsu bfe0000000000001, 65464 => 36a0000000000000, -72
++ lfsu bfe00094e0000359, 65472 => c400006b20000000, -64
++ lfsu 0000000000000000, 65480 => 0000000000000000, -56
++ lfsu 8000000000000000, 65488 => 0000000000000000, -48
++ lfsu 7ff0000000000000, 65496 => 0000000000000000, -40
++ lfsu fff0000000000000, 65504 => 0000000000000000, -32
++ lfsu 7ff7ffffffffffff, 65512 => ffffffffe0000000, -24
++ lfsu fff7ffffffffffff, 65520 => ffffffffe0000000, -16
++ lfsu 7ff8000000000000, 65528 => 0000000000000000, -8
++ lfsu 0010000000000001, 0 => 36a0000000000000, 0
++ lfsu 00100094e0000359, 8 => c400006b20000000, 8
++ lfsu 3fe0000000000001, 16 => 36a0000000000000, 16
++ lfsu 3fe00094e0000359, 24 => c400006b20000000, 24
++ lfsu 8010000000000001, 32 => 36a0000000000000, 32
++ lfsu 80100094e0000359, 40 => c400006b20000000, 40
++ lfsu bfe0000000000001, 48 => 36a0000000000000, 48
++ lfsu bfe00094e0000359, 56 => c400006b20000000, 56
++ lfsu 0000000000000000, 64 => 0000000000000000, 64
++ lfsu 8000000000000000, 72 => 0000000000000000, 72
++ lfsu 7ff0000000000000, 80 => 0000000000000000, 80
++ lfsu fff0000000000000, 88 => 0000000000000000, 88
++ lfsu 7ff7ffffffffffff, 96 => ffffffffe0000000, 96
++ lfsu fff7ffffffffffff, 104 => ffffffffe0000000, 104
++ lfsu 7ff8000000000000, 112 => 0000000000000000, 112
++ lfsu fff8000000000000, 120 => 0000000000000000, 120
++
++ lfd 0010000000000001, 65416 => 0010000000000001, 0
++ lfd 00100094e0000359, 65424 => 00100094e0000359, 0
++ lfd 3fe0000000000001, 65432 => 3fe0000000000001, 0
++ lfd 3fe00094e0000359, 65440 => 3fe00094e0000359, 0
++ lfd 8010000000000001, 65448 => 8010000000000001, 0
++ lfd 80100094e0000359, 65456 => 80100094e0000359, 0
++ lfd bfe0000000000001, 65464 => bfe0000000000001, 0
++ lfd bfe00094e0000359, 65472 => bfe00094e0000359, 0
++ lfd 0000000000000000, 65480 => 0000000000000000, 0
++ lfd 8000000000000000, 65488 => 8000000000000000, 0
++ lfd 7ff0000000000000, 65496 => 7ff0000000000000, 0
++ lfd fff0000000000000, 65504 => fff0000000000000, 0
++ lfd 7ff7ffffffffffff, 65512 => 7ff7ffffffffffff, 0
++ lfd fff7ffffffffffff, 65520 => fff7ffffffffffff, 0
++ lfd 7ff8000000000000, 65528 => 7ff8000000000000, 0
++ lfd 0010000000000001, 0 => 0010000000000001, 0
++ lfd 00100094e0000359, 8 => 00100094e0000359, 0
++ lfd 3fe0000000000001, 16 => 3fe0000000000001, 0
++ lfd 3fe00094e0000359, 24 => 3fe00094e0000359, 0
++ lfd 8010000000000001, 32 => 8010000000000001, 0
++ lfd 80100094e0000359, 40 => 80100094e0000359, 0
++ lfd bfe0000000000001, 48 => bfe0000000000001, 0
++ lfd bfe00094e0000359, 56 => bfe00094e0000359, 0
++ lfd 0000000000000000, 64 => 0000000000000000, 0
++ lfd 8000000000000000, 72 => 8000000000000000, 0
++ lfd 7ff0000000000000, 80 => 7ff0000000000000, 0
++ lfd fff0000000000000, 88 => fff0000000000000, 0
++ lfd 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0
++ lfd fff7ffffffffffff, 104 => fff7ffffffffffff, 0
++ lfd 7ff8000000000000, 112 => 7ff8000000000000, 0
++ lfd fff8000000000000, 120 => fff8000000000000, 0
++
++ lfdu 0010000000000001, 65416 => 0010000000000001, -120
++ lfdu 00100094e0000359, 65424 => 00100094e0000359, -112
++ lfdu 3fe0000000000001, 65432 => 3fe0000000000001, -104
++ lfdu 3fe00094e0000359, 65440 => 3fe00094e0000359, -96
++ lfdu 8010000000000001, 65448 => 8010000000000001, -88
++ lfdu 80100094e0000359, 65456 => 80100094e0000359, -80
++ lfdu bfe0000000000001, 65464 => bfe0000000000001, -72
++ lfdu bfe00094e0000359, 65472 => bfe00094e0000359, -64
++ lfdu 0000000000000000, 65480 => 0000000000000000, -56
++ lfdu 8000000000000000, 65488 => 8000000000000000, -48
++ lfdu 7ff0000000000000, 65496 => 7ff0000000000000, -40
++ lfdu fff0000000000000, 65504 => fff0000000000000, -32
++ lfdu 7ff7ffffffffffff, 65512 => 7ff7ffffffffffff, -24
++ lfdu fff7ffffffffffff, 65520 => fff7ffffffffffff, -16
++ lfdu 7ff8000000000000, 65528 => 7ff8000000000000, -8
++ lfdu 0010000000000001, 0 => 0010000000000001, 0
++ lfdu 00100094e0000359, 8 => 00100094e0000359, 8
++ lfdu 3fe0000000000001, 16 => 3fe0000000000001, 16
++ lfdu 3fe00094e0000359, 24 => 3fe00094e0000359, 24
++ lfdu 8010000000000001, 32 => 8010000000000001, 32
++ lfdu 80100094e0000359, 40 => 80100094e0000359, 40
++ lfdu bfe0000000000001, 48 => bfe0000000000001, 48
++ lfdu bfe00094e0000359, 56 => bfe00094e0000359, 56
++ lfdu 0000000000000000, 64 => 0000000000000000, 64
++ lfdu 8000000000000000, 72 => 8000000000000000, 72
++ lfdu 7ff0000000000000, 80 => 7ff0000000000000, 80
++ lfdu fff0000000000000, 88 => fff0000000000000, 88
++ lfdu 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96
++ lfdu fff7ffffffffffff, 104 => fff7ffffffffffff, 104
++ lfdu 7ff8000000000000, 112 => 7ff8000000000000, 112
++ lfdu fff8000000000000, 120 => fff8000000000000, 120
++
++PPC float load insns with two register args:
++ lfsx 0010000000000001, -120 => 36a0000000000000, 0
++ lfsx 00100094e0000359, -112 => c400006b20000000, 0
++ lfsx 3fe0000000000001, -104 => 36a0000000000000, 0
++ lfsx 3fe00094e0000359, -96 => c400006b20000000, 0
++ lfsx 8010000000000001, -88 => 36a0000000000000, 0
++ lfsx 80100094e0000359, -80 => c400006b20000000, 0
++ lfsx bfe0000000000001, -72 => 36a0000000000000, 0
++ lfsx bfe00094e0000359, -64 => c400006b20000000, 0
++ lfsx 0000000000000000, -56 => 0000000000000000, 0
++ lfsx 8000000000000000, -48 => 0000000000000000, 0
++ lfsx 7ff0000000000000, -40 => 0000000000000000, 0
++ lfsx fff0000000000000, -32 => 0000000000000000, 0
++ lfsx 7ff7ffffffffffff, -24 => ffffffffe0000000, 0
++ lfsx fff7ffffffffffff, -16 => ffffffffe0000000, 0
++ lfsx 7ff8000000000000, -8 => 0000000000000000, 0
++ lfsx 0010000000000001, 0 => 36a0000000000000, 0
++ lfsx 00100094e0000359, 8 => c400006b20000000, 0
++ lfsx 3fe0000000000001, 16 => 36a0000000000000, 0
++ lfsx 3fe00094e0000359, 24 => c400006b20000000, 0
++ lfsx 8010000000000001, 32 => 36a0000000000000, 0
++ lfsx 80100094e0000359, 40 => c400006b20000000, 0
++ lfsx bfe0000000000001, 48 => 36a0000000000000, 0
++ lfsx bfe00094e0000359, 56 => c400006b20000000, 0
++ lfsx 0000000000000000, 64 => 0000000000000000, 0
++ lfsx 8000000000000000, 72 => 0000000000000000, 0
++ lfsx 7ff0000000000000, 80 => 0000000000000000, 0
++ lfsx fff0000000000000, 88 => 0000000000000000, 0
++ lfsx 7ff7ffffffffffff, 96 => ffffffffe0000000, 0
++ lfsx fff7ffffffffffff, 104 => ffffffffe0000000, 0
++ lfsx 7ff8000000000000, 112 => 0000000000000000, 0
++ lfsx fff8000000000000, 120 => 0000000000000000, 0
++
++ lfsux 0010000000000001, -120 => 36a0000000000000, -120
++ lfsux 00100094e0000359, -112 => c400006b20000000, -112
++ lfsux 3fe0000000000001, -104 => 36a0000000000000, -104
++ lfsux 3fe00094e0000359, -96 => c400006b20000000, -96
++ lfsux 8010000000000001, -88 => 36a0000000000000, -88
++ lfsux 80100094e0000359, -80 => c400006b20000000, -80
++ lfsux bfe0000000000001, -72 => 36a0000000000000, -72
++ lfsux bfe00094e0000359, -64 => c400006b20000000, -64
++ lfsux 0000000000000000, -56 => 0000000000000000, -56
++ lfsux 8000000000000000, -48 => 0000000000000000, -48
++ lfsux 7ff0000000000000, -40 => 0000000000000000, -40
++ lfsux fff0000000000000, -32 => 0000000000000000, -32
++ lfsux 7ff7ffffffffffff, -24 => ffffffffe0000000, -24
++ lfsux fff7ffffffffffff, -16 => ffffffffe0000000, -16
++ lfsux 7ff8000000000000, -8 => 0000000000000000, -8
++ lfsux 0010000000000001, 0 => 36a0000000000000, 0
++ lfsux 00100094e0000359, 8 => c400006b20000000, 8
++ lfsux 3fe0000000000001, 16 => 36a0000000000000, 16
++ lfsux 3fe00094e0000359, 24 => c400006b20000000, 24
++ lfsux 8010000000000001, 32 => 36a0000000000000, 32
++ lfsux 80100094e0000359, 40 => c400006b20000000, 40
++ lfsux bfe0000000000001, 48 => 36a0000000000000, 48
++ lfsux bfe00094e0000359, 56 => c400006b20000000, 56
++ lfsux 0000000000000000, 64 => 0000000000000000, 64
++ lfsux 8000000000000000, 72 => 0000000000000000, 72
++ lfsux 7ff0000000000000, 80 => 0000000000000000, 80
++ lfsux fff0000000000000, 88 => 0000000000000000, 88
++ lfsux 7ff7ffffffffffff, 96 => ffffffffe0000000, 96
++ lfsux fff7ffffffffffff, 104 => ffffffffe0000000, 104
++ lfsux 7ff8000000000000, 112 => 0000000000000000, 112
++ lfsux fff8000000000000, 120 => 0000000000000000, 120
++
++ lfdx 0010000000000001, -120 => 0010000000000001, 0
++ lfdx 00100094e0000359, -112 => 00100094e0000359, 0
++ lfdx 3fe0000000000001, -104 => 3fe0000000000001, 0
++ lfdx 3fe00094e0000359, -96 => 3fe00094e0000359, 0
++ lfdx 8010000000000001, -88 => 8010000000000001, 0
++ lfdx 80100094e0000359, -80 => 80100094e0000359, 0
++ lfdx bfe0000000000001, -72 => bfe0000000000001, 0
++ lfdx bfe00094e0000359, -64 => bfe00094e0000359, 0
++ lfdx 0000000000000000, -56 => 0000000000000000, 0
++ lfdx 8000000000000000, -48 => 8000000000000000, 0
++ lfdx 7ff0000000000000, -40 => 7ff0000000000000, 0
++ lfdx fff0000000000000, -32 => fff0000000000000, 0
++ lfdx 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, 0
++ lfdx fff7ffffffffffff, -16 => fff7ffffffffffff, 0
++ lfdx 7ff8000000000000, -8 => 7ff8000000000000, 0
++ lfdx 0010000000000001, 0 => 0010000000000001, 0
++ lfdx 00100094e0000359, 8 => 00100094e0000359, 0
++ lfdx 3fe0000000000001, 16 => 3fe0000000000001, 0
++ lfdx 3fe00094e0000359, 24 => 3fe00094e0000359, 0
++ lfdx 8010000000000001, 32 => 8010000000000001, 0
++ lfdx 80100094e0000359, 40 => 80100094e0000359, 0
++ lfdx bfe0000000000001, 48 => bfe0000000000001, 0
++ lfdx bfe00094e0000359, 56 => bfe00094e0000359, 0
++ lfdx 0000000000000000, 64 => 0000000000000000, 0
++ lfdx 8000000000000000, 72 => 8000000000000000, 0
++ lfdx 7ff0000000000000, 80 => 7ff0000000000000, 0
++ lfdx fff0000000000000, 88 => fff0000000000000, 0
++ lfdx 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0
++ lfdx fff7ffffffffffff, 104 => fff7ffffffffffff, 0
++ lfdx 7ff8000000000000, 112 => 7ff8000000000000, 0
++ lfdx fff8000000000000, 120 => fff8000000000000, 0
++
++ lfdux 0010000000000001, -120 => 0010000000000001, -120
++ lfdux 00100094e0000359, -112 => 00100094e0000359, -112
++ lfdux 3fe0000000000001, -104 => 3fe0000000000001, -104
++ lfdux 3fe00094e0000359, -96 => 3fe00094e0000359, -96
++ lfdux 8010000000000001, -88 => 8010000000000001, -88
++ lfdux 80100094e0000359, -80 => 80100094e0000359, -80
++ lfdux bfe0000000000001, -72 => bfe0000000000001, -72
++ lfdux bfe00094e0000359, -64 => bfe00094e0000359, -64
++ lfdux 0000000000000000, -56 => 0000000000000000, -56
++ lfdux 8000000000000000, -48 => 8000000000000000, -48
++ lfdux 7ff0000000000000, -40 => 7ff0000000000000, -40
++ lfdux fff0000000000000, -32 => fff0000000000000, -32
++ lfdux 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, -24
++ lfdux fff7ffffffffffff, -16 => fff7ffffffffffff, -16
++ lfdux 7ff8000000000000, -8 => 7ff8000000000000, -8
++ lfdux 0010000000000001, 0 => 0010000000000001, 0
++ lfdux 00100094e0000359, 8 => 00100094e0000359, 8
++ lfdux 3fe0000000000001, 16 => 3fe0000000000001, 16
++ lfdux 3fe00094e0000359, 24 => 3fe00094e0000359, 24
++ lfdux 8010000000000001, 32 => 8010000000000001, 32
++ lfdux 80100094e0000359, 40 => 80100094e0000359, 40
++ lfdux bfe0000000000001, 48 => bfe0000000000001, 48
++ lfdux bfe00094e0000359, 56 => bfe00094e0000359, 56
++ lfdux 0000000000000000, 64 => 0000000000000000, 64
++ lfdux 8000000000000000, 72 => 8000000000000000, 72
++ lfdux 7ff0000000000000, 80 => 7ff0000000000000, 80
++ lfdux fff0000000000000, 88 => fff0000000000000, 88
++ lfdux 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96
++ lfdux fff7ffffffffffff, 104 => fff7ffffffffffff, 104
++ lfdux 7ff8000000000000, 112 => 7ff8000000000000, 112
++ lfdux fff8000000000000, 120 => fff8000000000000, 120
++
++PPC float store insns
++ with one register + one 16 bits immediate args with flags update:
++ stfs 0010000000000001, -56 => 0000000000000000, 0
++ stfs 00100094e0000359, -48 => 0000000000000000, 0
++ stfs 3fe0000000000001, -40 => 000000003f000000, 0
++ stfs 3fe00094e0000359, -32 => 000000003f0004a7, 0
++ stfs 8010000000000001, -24 => 0000000080000000, 0
++ stfs 80100094e0000359, -16 => 0000000080000000, 0
++ stfs bfe0000000000001, -8 => 00000000bf000000, 0
++ stfs 0010000000000001, 0 => 0000000000000000, 0
++ stfs 00100094e0000359, 8 => 0000000000000000, 0
++ stfs 3fe0000000000001, 16 => 000000003f000000, 0
++ stfs 3fe00094e0000359, 24 => 000000003f0004a7, 0
++ stfs 8010000000000001, 32 => 0000000080000000, 0
++ stfs 80100094e0000359, 40 => 0000000080000000, 0
++ stfs bfe0000000000001, 48 => 00000000bf000000, 0
++ stfs bfe00094e0000359, 56 => 00000000bf0004a7, 0
++
++ stfsu 0010000000000001, -56 => 0000000000000000, -56
++ stfsu 00100094e0000359, -48 => 0000000000000000, -48
++ stfsu 3fe0000000000001, -40 => 000000003f000000, -40
++ stfsu 3fe00094e0000359, -32 => 000000003f0004a7, -32
++ stfsu 8010000000000001, -24 => 0000000080000000, -24
++ stfsu 80100094e0000359, -16 => 0000000080000000, -16
++ stfsu bfe0000000000001, -8 => 00000000bf000000, -8
++ stfsu 0010000000000001, 0 => 0000000000000000, 0
++ stfsu 00100094e0000359, 8 => 0000000000000000, 8
++ stfsu 3fe0000000000001, 16 => 000000003f000000, 16
++ stfsu 3fe00094e0000359, 24 => 000000003f0004a7, 24
++ stfsu 8010000000000001, 32 => 0000000080000000, 32
++ stfsu 80100094e0000359, 40 => 0000000080000000, 40
++ stfsu bfe0000000000001, 48 => 00000000bf000000, 48
++ stfsu bfe00094e0000359, 56 => 00000000bf0004a7, 56
++
++ stfd 0010000000000001, -120 => 0010000000000001, 0
++ stfd 00100094e0000359, -112 => 00100094e0000359, 0
++ stfd 3fe0000000000001, -104 => 3fe0000000000001, 0
++ stfd 3fe00094e0000359, -96 => 3fe00094e0000359, 0
++ stfd 8010000000000001, -88 => 8010000000000001, 0
++ stfd 80100094e0000359, -80 => 80100094e0000359, 0
++ stfd bfe0000000000001, -72 => bfe0000000000001, 0
++ stfd bfe00094e0000359, -64 => bfe00094e0000359, 0
++ stfd 0000000000000000, -56 => 0000000000000000, 0
++ stfd 8000000000000000, -48 => 8000000000000000, 0
++ stfd 7ff0000000000000, -40 => 7ff0000000000000, 0
++ stfd fff0000000000000, -32 => fff0000000000000, 0
++ stfd 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, 0
++ stfd fff7ffffffffffff, -16 => fff7ffffffffffff, 0
++ stfd 7ff8000000000000, -8 => 7ff8000000000000, 0
++ stfd 0010000000000001, 0 => 0010000000000001, 0
++ stfd 00100094e0000359, 8 => 00100094e0000359, 0
++ stfd 3fe0000000000001, 16 => 3fe0000000000001, 0
++ stfd 3fe00094e0000359, 24 => 3fe00094e0000359, 0
++ stfd 8010000000000001, 32 => 8010000000000001, 0
++ stfd 80100094e0000359, 40 => 80100094e0000359, 0
++ stfd bfe0000000000001, 48 => bfe0000000000001, 0
++ stfd bfe00094e0000359, 56 => bfe00094e0000359, 0
++ stfd 0000000000000000, 64 => 0000000000000000, 0
++ stfd 8000000000000000, 72 => 8000000000000000, 0
++ stfd 7ff0000000000000, 80 => 7ff0000000000000, 0
++ stfd fff0000000000000, 88 => fff0000000000000, 0
++ stfd 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0
++ stfd fff7ffffffffffff, 104 => fff7ffffffffffff, 0
++ stfd 7ff8000000000000, 112 => 7ff8000000000000, 0
++ stfd fff8000000000000, 120 => fff8000000000000, 0
++
++ stfdu 0010000000000001, -120 => 0010000000000001, -120
++ stfdu 00100094e0000359, -112 => 00100094e0000359, -112
++ stfdu 3fe0000000000001, -104 => 3fe0000000000001, -104
++ stfdu 3fe00094e0000359, -96 => 3fe00094e0000359, -96
++ stfdu 8010000000000001, -88 => 8010000000000001, -88
++ stfdu 80100094e0000359, -80 => 80100094e0000359, -80
++ stfdu bfe0000000000001, -72 => bfe0000000000001, -72
++ stfdu bfe00094e0000359, -64 => bfe00094e0000359, -64
++ stfdu 0000000000000000, -56 => 0000000000000000, -56
++ stfdu 8000000000000000, -48 => 8000000000000000, -48
++ stfdu 7ff0000000000000, -40 => 7ff0000000000000, -40
++ stfdu fff0000000000000, -32 => fff0000000000000, -32
++ stfdu 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, -24
++ stfdu fff7ffffffffffff, -16 => fff7ffffffffffff, -16
++ stfdu 7ff8000000000000, -8 => 7ff8000000000000, -8
++ stfdu 0010000000000001, 0 => 0010000000000001, 0
++ stfdu 00100094e0000359, 8 => 00100094e0000359, 8
++ stfdu 3fe0000000000001, 16 => 3fe0000000000001, 16
++ stfdu 3fe00094e0000359, 24 => 3fe00094e0000359, 24
++ stfdu 8010000000000001, 32 => 8010000000000001, 32
++ stfdu 80100094e0000359, 40 => 80100094e0000359, 40
++ stfdu bfe0000000000001, 48 => bfe0000000000001, 48
++ stfdu bfe00094e0000359, 56 => bfe00094e0000359, 56
++ stfdu 0000000000000000, 64 => 0000000000000000, 64
++ stfdu 8000000000000000, 72 => 8000000000000000, 72
++ stfdu 7ff0000000000000, 80 => 7ff0000000000000, 80
++ stfdu fff0000000000000, 88 => fff0000000000000, 88
++ stfdu 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96
++ stfdu fff7ffffffffffff, 104 => fff7ffffffffffff, 104
++ stfdu 7ff8000000000000, 112 => 7ff8000000000000, 112
++ stfdu fff8000000000000, 120 => fff8000000000000, 120
++
++PPC float store insns with three register args:
++ stfsx 0010000000000001, 0 => 0000000000000000, 0
++ stfsx 00100094e0000359, 8 => 0000000000000000, 0
++ stfsx 3fe0000000000001, 16 => 000000003f000000, 0
++ stfsx 3fe00094e0000359, 24 => 000000003f0004a7, 0
++ stfsx 8010000000000001, 32 => 0000000080000000, 0
++ stfsx 80100094e0000359, 40 => 0000000080000000, 0
++ stfsx bfe0000000000001, 48 => 00000000bf000000, 0
++ stfsx bfe00094e0000359, 56 => 00000000bf0004a7, 0
++
++ stfsux 0010000000000001, 0 => 0000000000000000, 0
++ stfsux 00100094e0000359, 8 => 0000000000000000, 8
++ stfsux 3fe0000000000001, 16 => 000000003f000000, 16
++ stfsux 3fe00094e0000359, 24 => 000000003f0004a7, 24
++ stfsux 8010000000000001, 32 => 0000000080000000, 32
++ stfsux 80100094e0000359, 40 => 0000000080000000, 40
++ stfsux bfe0000000000001, 48 => 00000000bf000000, 48
++ stfsux bfe00094e0000359, 56 => 00000000bf0004a7, 56
++
++ stfdx 0010000000000001, 0 => 0010000000000001, 0
++ stfdx 00100094e0000359, 8 => 00100094e0000359, 0
++ stfdx 3fe0000000000001, 16 => 3fe0000000000001, 0
++ stfdx 3fe00094e0000359, 24 => 3fe00094e0000359, 0
++ stfdx 8010000000000001, 32 => 8010000000000001, 0
++ stfdx 80100094e0000359, 40 => 80100094e0000359, 0
++ stfdx bfe0000000000001, 48 => bfe0000000000001, 0
++ stfdx bfe00094e0000359, 56 => bfe00094e0000359, 0
++ stfdx 0000000000000000, 64 => 0000000000000000, 0
++ stfdx 8000000000000000, 72 => 8000000000000000, 0
++ stfdx 7ff0000000000000, 80 => 7ff0000000000000, 0
++ stfdx fff0000000000000, 88 => fff0000000000000, 0
++ stfdx 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0
++ stfdx fff7ffffffffffff, 104 => fff7ffffffffffff, 0
++ stfdx 7ff8000000000000, 112 => 7ff8000000000000, 0
++ stfdx fff8000000000000, 120 => fff8000000000000, 0
++
++ stfdux 0010000000000001, 0 => 0010000000000001, 0
++ stfdux 00100094e0000359, 8 => 00100094e0000359, 8
++ stfdux 3fe0000000000001, 16 => 3fe0000000000001, 16
++ stfdux 3fe00094e0000359, 24 => 3fe00094e0000359, 24
++ stfdux 8010000000000001, 32 => 8010000000000001, 32
++ stfdux 80100094e0000359, 40 => 80100094e0000359, 40
++ stfdux bfe0000000000001, 48 => bfe0000000000001, 48
++ stfdux bfe00094e0000359, 56 => bfe00094e0000359, 56
++ stfdux 0000000000000000, 64 => 0000000000000000, 64
++ stfdux 8000000000000000, 72 => 8000000000000000, 72
++ stfdux 7ff0000000000000, 80 => 7ff0000000000000, 80
++ stfdux fff0000000000000, 88 => fff0000000000000, 88
++ stfdux 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96
++ stfdux fff7ffffffffffff, 104 => fff7ffffffffffff, 104
++ stfdux 7ff8000000000000, 112 => 7ff8000000000000, 112
++ stfdux fff8000000000000, 120 => fff8000000000000, 120
++
++All done. Tested 77 different instructions
+diff --git a/none/tests/ppc64/jm-fp.stdout.exp-LE2 b/none/tests/ppc64/jm-fp.stdout.exp-LE2
+new file mode 100644
+index 0000000..c45786b
+--- /dev/null
++++ b/none/tests/ppc64/jm-fp.stdout.exp-LE2
+@@ -0,0 +1,1533 @@
++PPC floating point arith insns with three args:
++ fsel 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
++ fsel 0010000000000001, 0010000000000001, bfe00094e0000359 => 0010000000000000
++ fsel 0010000000000001, 80100094e0000359, 0010000000000001 => 80100094e0000300
++ fsel 0010000000000001, 80100094e0000359, bfe00094e0000359 => 80100094e0000300
++ fsel 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0010000000000000
++ fsel 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 0010000000000000
++ fsel 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80100094e0000300
++ fsel 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 80100094e0000300
++ fsel bfe0000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
++ fsel bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fsel bfe0000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
++ fsel bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++
++ fmadd 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
++ fmadd 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fmadd 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
++ fmadd 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++ fmadd 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0018004a70000100
++ fmadd 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fmadd 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0007ff6b1d4b5e00
++ fmadd 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++ fmadd bfe0000000000001, 0010000000000001, 0010000000000001 => 0008000000000000
++ fmadd bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fmadd bfe0000000000001, 80100094e0000359, 0010000000000001 => 0018004a70000100
++ fmadd bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++
++ fmadds 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
++ fmadds 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fmadds 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fmadds 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++ fmadds 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000
++ fmadds 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fmadds 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fmadds 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++ fmadds bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
++ fmadds bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fmadds bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fmadds bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++
++ fmsub 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000
++ fmsub 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fmsub 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000
++ fmsub 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++ fmsub 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8007ffb58ffffe00
++ fmsub 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fmsub 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80180094e2b4a100
++ fmsub 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++ fmsub bfe0000000000001, 0010000000000001, 0010000000000001 => 8018000000000000
++ fmsub bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fmsub bfe0000000000001, 80100094e0000359, 0010000000000001 => 8007ffb58ffffe00
++ fmsub bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++
++ fmsubs 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
++ fmsubs 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fmsubs 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fmsubs 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++ fmsubs 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000
++ fmsubs 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fmsubs 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fmsubs 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++ fmsubs bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
++ fmsubs bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fmsubs bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fmsubs bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++
++ fnmadd 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000
++ fnmadd 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fnmadd 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000
++ fnmadd 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++ fnmadd 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8018004a70000100
++ fnmadd 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fnmadd 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8007ff6b1d4b5e00
++ fnmadd 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++ fnmadd bfe0000000000001, 0010000000000001, 0010000000000001 => 8008000000000000
++ fnmadd bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fnmadd bfe0000000000001, 80100094e0000359, 0010000000000001 => 8018004a70000100
++ fnmadd bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++
++ fnmadds 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
++ fnmadds 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fnmadds 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fnmadds 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++ fnmadds 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000
++ fnmadds 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fnmadds 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fnmadds 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++ fnmadds bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
++ fnmadds bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fnmadds bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fnmadds bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++
++ fnmsub 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
++ fnmsub 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fnmsub 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
++ fnmsub 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++ fnmsub 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0007ffb58ffffe00
++ fnmsub 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fnmsub 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 00180094e2b4a100
++ fnmsub 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++ fnmsub bfe0000000000001, 0010000000000001, 0010000000000001 => 0018000000000000
++ fnmsub bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fnmsub bfe0000000000001, 80100094e0000359, 0010000000000001 => 0007ffb58ffffe00
++ fnmsub bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++
++ fnmsubs 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
++ fnmsubs 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fnmsubs 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fnmsubs 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++ fnmsubs 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000
++ fnmsubs 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fnmsubs 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fnmsubs 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++ fnmsubs bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
++ fnmsubs bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fnmsubs bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fnmsubs bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++
++PPC floating point arith insns
++ with three args with flags update:
++ fsel. 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
++ fsel. 0010000000000001, 0010000000000001, bfe00094e0000359 => 0010000000000000
++ fsel. 0010000000000001, 80100094e0000359, 0010000000000001 => 80100094e0000300
++ fsel. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 80100094e0000300
++ fsel. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0010000000000000
++ fsel. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 0010000000000000
++ fsel. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80100094e0000300
++ fsel. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 80100094e0000300
++ fsel. bfe0000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
++ fsel. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fsel. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
++ fsel. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++
++ fmadd. 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
++ fmadd. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fmadd. 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
++ fmadd. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++ fmadd. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0018004a70000100
++ fmadd. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fmadd. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0007ff6b1d4b5e00
++ fmadd. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++ fmadd. bfe0000000000001, 0010000000000001, 0010000000000001 => 0008000000000000
++ fmadd. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fmadd. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0018004a70000100
++ fmadd. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++
++ fmadds. 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
++ fmadds. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fmadds. 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fmadds. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++ fmadds. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000
++ fmadds. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fmadds. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fmadds. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++ fmadds. bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
++ fmadds. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fmadds. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fmadds. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++
++ fmsub. 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000
++ fmsub. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fmsub. 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000
++ fmsub. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++ fmsub. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8007ffb58ffffe00
++ fmsub. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fmsub. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 80180094e2b4a100
++ fmsub. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++ fmsub. bfe0000000000001, 0010000000000001, 0010000000000001 => 8018000000000000
++ fmsub. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fmsub. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8007ffb58ffffe00
++ fmsub. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++
++ fmsubs. 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
++ fmsubs. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fmsubs. 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fmsubs. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++ fmsubs. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000
++ fmsubs. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fmsubs. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fmsubs. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++ fmsubs. bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
++ fmsubs. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fmsubs. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fmsubs. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++
++ fnmadd. 0010000000000001, 0010000000000001, 0010000000000001 => 8010000000000000
++ fnmadd. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fnmadd. 0010000000000001, 80100094e0000359, 0010000000000001 => 8010000000000000
++ fnmadd. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++ fnmadd. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8018004a70000100
++ fnmadd. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fnmadd. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8007ff6b1d4b5e00
++ fnmadd. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++ fnmadd. bfe0000000000001, 0010000000000001, 0010000000000001 => 8008000000000000
++ fnmadd. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000300
++ fnmadd. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8018004a70000100
++ fnmadd. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000300
++
++ fnmadds. 0010000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
++ fnmadds. 0010000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fnmadds. 0010000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fnmadds. 0010000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++ fnmadds. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 8000000000000000
++ fnmadds. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fnmadds. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fnmadds. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++ fnmadds. bfe0000000000001, 0010000000000001, 0010000000000001 => 8000000000000000
++ fnmadds. bfe0000000000001, 0010000000000001, bfe00094e0000359 => 3fe00094e0000000
++ fnmadds. bfe0000000000001, 80100094e0000359, 0010000000000001 => 8000000000000000
++ fnmadds. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => 3fe00094e0000000
++
++ fnmsub. 0010000000000001, 0010000000000001, 0010000000000001 => 0010000000000000
++ fnmsub. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fnmsub. 0010000000000001, 80100094e0000359, 0010000000000001 => 0010000000000000
++ fnmsub. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++ fnmsub. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0007ffb58ffffe00
++ fnmsub. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fnmsub. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 00180094e2b4a100
++ fnmsub. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++ fnmsub. bfe0000000000001, 0010000000000001, 0010000000000001 => 0018000000000000
++ fnmsub. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000300
++ fnmsub. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0007ffb58ffffe00
++ fnmsub. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000300
++
++ fnmsubs. 0010000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
++ fnmsubs. 0010000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fnmsubs. 0010000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fnmsubs. 0010000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++ fnmsubs. 3fe00094e0000359, 0010000000000001, 0010000000000001 => 0000000000000000
++ fnmsubs. 3fe00094e0000359, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fnmsubs. 3fe00094e0000359, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fnmsubs. 3fe00094e0000359, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++ fnmsubs. bfe0000000000001, 0010000000000001, 0010000000000001 => 0000000000000000
++ fnmsubs. bfe0000000000001, 0010000000000001, bfe00094e0000359 => bfe00094e0000000
++ fnmsubs. bfe0000000000001, 80100094e0000359, 0010000000000001 => 0000000000000000
++ fnmsubs. bfe0000000000001, 80100094e0000359, bfe00094e0000359 => bfe00094e0000000
++
++PPC floating point arith insns with two args:
++ fadd 0010000000000001, 0010000000000001 => 0020000000000001
++ fadd 0010000000000001, 80100094e0000359 => 80000094e0000358
++ fadd 0010000000000001, 7ff0000000000000 => 7ff0000000000000
++ fadd 0010000000000001, fff8000000000000 => fff8000000000000
++ fadd 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359
++ fadd 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359
++ fadd 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
++ fadd 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fadd bfe0000000000001, 0010000000000001 => bfe0000000000001
++ fadd bfe0000000000001, 80100094e0000359 => bfe0000000000001
++ fadd bfe0000000000001, 7ff0000000000000 => 7ff0000000000000
++ fadd bfe0000000000001, fff8000000000000 => fff8000000000000
++ fadd 8000000000000000, 0010000000000001 => 0010000000000001
++ fadd 8000000000000000, 80100094e0000359 => 80100094e0000359
++ fadd 8000000000000000, 7ff0000000000000 => 7ff0000000000000
++ fadd 8000000000000000, fff8000000000000 => fff8000000000000
++ fadd 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
++ fadd 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
++ fadd 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
++ fadd 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
++ fadd fff8000000000000, 0010000000000001 => fff8000000000000
++ fadd fff8000000000000, 80100094e0000359 => fff8000000000000
++ fadd fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fadd fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fadds 0010000000000001, 0010000000000001 => 0000000000000000
++ fadds 0010000000000001, 80100094e0000359 => 8000000000000000
++ fadds 0010000000000001, 7ff0000000000000 => 7ff0000000000000
++ fadds 0010000000000001, fff8000000000000 => fff8000000000000
++ fadds 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000
++ fadds 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000
++ fadds 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
++ fadds 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fadds bfe0000000000001, 0010000000000001 => bfe0000000000000
++ fadds bfe0000000000001, 80100094e0000359 => bfe0000000000000
++ fadds bfe0000000000001, 7ff0000000000000 => 7ff0000000000000
++ fadds bfe0000000000001, fff8000000000000 => fff8000000000000
++ fadds 8000000000000000, 0010000000000001 => 0000000000000000
++ fadds 8000000000000000, 80100094e0000359 => 8000000000000000
++ fadds 8000000000000000, 7ff0000000000000 => 7ff0000000000000
++ fadds 8000000000000000, fff8000000000000 => fff8000000000000
++ fadds 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
++ fadds 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
++ fadds 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
++ fadds 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
++ fadds fff8000000000000, 0010000000000001 => fff8000000000000
++ fadds fff8000000000000, 80100094e0000359 => fff8000000000000
++ fadds fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fadds fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fsub 0010000000000001, 0010000000000001 => 0000000000000000
++ fsub 0010000000000001, 80100094e0000359 => 0020004a700001ad
++ fsub 0010000000000001, 7ff0000000000000 => fff0000000000000
++ fsub 0010000000000001, fff8000000000000 => fff8000000000000
++ fsub 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359
++ fsub 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359
++ fsub 3fe00094e0000359, 7ff0000000000000 => fff0000000000000
++ fsub 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fsub bfe0000000000001, 0010000000000001 => bfe0000000000001
++ fsub bfe0000000000001, 80100094e0000359 => bfe0000000000001
++ fsub bfe0000000000001, 7ff0000000000000 => fff0000000000000
++ fsub bfe0000000000001, fff8000000000000 => fff8000000000000
++ fsub 8000000000000000, 0010000000000001 => 8010000000000001
++ fsub 8000000000000000, 80100094e0000359 => 00100094e0000359
++ fsub 8000000000000000, 7ff0000000000000 => fff0000000000000
++ fsub 8000000000000000, fff8000000000000 => fff8000000000000
++ fsub 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
++ fsub 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
++ fsub 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
++ fsub 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
++ fsub fff8000000000000, 0010000000000001 => fff8000000000000
++ fsub fff8000000000000, 80100094e0000359 => fff8000000000000
++ fsub fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fsub fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fsubs 0010000000000001, 0010000000000001 => 0000000000000000
++ fsubs 0010000000000001, 80100094e0000359 => 0000000000000000
++ fsubs 0010000000000001, 7ff0000000000000 => fff0000000000000
++ fsubs 0010000000000001, fff8000000000000 => fff8000000000000
++ fsubs 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000
++ fsubs 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000
++ fsubs 3fe00094e0000359, 7ff0000000000000 => fff0000000000000
++ fsubs 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fsubs bfe0000000000001, 0010000000000001 => bfe0000000000000
++ fsubs bfe0000000000001, 80100094e0000359 => bfe0000000000000
++ fsubs bfe0000000000001, 7ff0000000000000 => fff0000000000000
++ fsubs bfe0000000000001, fff8000000000000 => fff8000000000000
++ fsubs 8000000000000000, 0010000000000001 => 8000000000000000
++ fsubs 8000000000000000, 80100094e0000359 => 0000000000000000
++ fsubs 8000000000000000, 7ff0000000000000 => fff0000000000000
++ fsubs 8000000000000000, fff8000000000000 => fff8000000000000
++ fsubs 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
++ fsubs 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
++ fsubs 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
++ fsubs 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
++ fsubs fff8000000000000, 0010000000000001 => fff8000000000000
++ fsubs fff8000000000000, 80100094e0000359 => fff8000000000000
++ fsubs fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fsubs fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fmul 0010000000000001, 0010000000000001 => 0000000000000000
++ fmul 0010000000000001, 80100094e0000359 => 8000000000000000
++ fmul 0010000000000001, 7ff0000000000000 => 7ff0000000000000
++ fmul 0010000000000001, fff8000000000000 => fff8000000000000
++ fmul 3fe00094e0000359, 0010000000000001 => 0008004a700001ad
++ fmul 3fe00094e0000359, 80100094e0000359 => 80080094e2b4a179
++ fmul 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
++ fmul 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fmul bfe0000000000001, 0010000000000001 => 8008000000000001
++ fmul bfe0000000000001, 80100094e0000359 => 0008004a700001ad
++ fmul bfe0000000000001, 7ff0000000000000 => fff0000000000000
++ fmul bfe0000000000001, fff8000000000000 => fff8000000000000
++ fmul 8000000000000000, 0010000000000001 => 8000000000000000
++ fmul 8000000000000000, 80100094e0000359 => 0000000000000000
++ fmul 8000000000000000, 7ff0000000000000 => 7ff8000000000000
++ fmul 8000000000000000, fff8000000000000 => fff8000000000000
++ fmul 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
++ fmul 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
++ fmul 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
++ fmul 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
++ fmul fff8000000000000, 0010000000000001 => fff8000000000000
++ fmul fff8000000000000, 80100094e0000359 => fff8000000000000
++ fmul fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fmul fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fmuls 0010000000000001, 0010000000000001 => 0000000000000000
++ fmuls 0010000000000001, 80100094e0000359 => 8000000000000000
++ fmuls 0010000000000001, 7ff0000000000000 => 7ff0000000000000
++ fmuls 0010000000000001, fff8000000000000 => fff8000000000000
++ fmuls 3fe00094e0000359, 0010000000000001 => 0000000000000000
++ fmuls 3fe00094e0000359, 80100094e0000359 => 8000000000000000
++ fmuls 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
++ fmuls 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fmuls bfe0000000000001, 0010000000000001 => 8000000000000000
++ fmuls bfe0000000000001, 80100094e0000359 => 0000000000000000
++ fmuls bfe0000000000001, 7ff0000000000000 => fff0000000000000
++ fmuls bfe0000000000001, fff8000000000000 => fff8000000000000
++ fmuls 8000000000000000, 0010000000000001 => 8000000000000000
++ fmuls 8000000000000000, 80100094e0000359 => 0000000000000000
++ fmuls 8000000000000000, 7ff0000000000000 => 7ff8000000000000
++ fmuls 8000000000000000, fff8000000000000 => fff8000000000000
++ fmuls 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
++ fmuls 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
++ fmuls 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
++ fmuls 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
++ fmuls fff8000000000000, 0010000000000001 => fff8000000000000
++ fmuls fff8000000000000, 80100094e0000359 => fff8000000000000
++ fmuls fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fmuls fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fdiv 0010000000000001, 0010000000000001 => 3ff0000000000000
++ fdiv 0010000000000001, 80100094e0000359 => bfeffed64ad20d22
++ fdiv 0010000000000001, 7ff0000000000000 => 0000000000000000
++ fdiv 0010000000000001, fff8000000000000 => fff8000000000000
++ fdiv 3fe00094e0000359, 0010000000000001 => 7fc00094e0000358
++ fdiv 3fe00094e0000359, 80100094e0000359 => ffc0000000000000
++ fdiv 3fe00094e0000359, 7ff0000000000000 => 0000000000000000
++ fdiv 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fdiv bfe0000000000001, 0010000000000001 => ffc0000000000000
++ fdiv bfe0000000000001, 80100094e0000359 => 7fbffed64ad20d22
++ fdiv bfe0000000000001, 7ff0000000000000 => 8000000000000000
++ fdiv bfe0000000000001, fff8000000000000 => fff8000000000000
++ fdiv 8000000000000000, 0010000000000001 => 8000000000000000
++ fdiv 8000000000000000, 80100094e0000359 => 0000000000000000
++ fdiv 8000000000000000, 7ff0000000000000 => 8000000000000000
++ fdiv 8000000000000000, fff8000000000000 => fff8000000000000
++ fdiv 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
++ fdiv 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
++ fdiv 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
++ fdiv 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
++ fdiv fff8000000000000, 0010000000000001 => fff8000000000000
++ fdiv fff8000000000000, 80100094e0000359 => fff8000000000000
++ fdiv fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fdiv fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fdivs 0010000000000001, 0010000000000001 => 3ff0000000000000
++ fdivs 0010000000000001, 80100094e0000359 => bfeffed640000000
++ fdivs 0010000000000001, 7ff0000000000000 => 0000000000000000
++ fdivs 0010000000000001, fff8000000000000 => fff8000000000000
++ fdivs 3fe00094e0000359, 0010000000000001 => 7ff0000000000000
++ fdivs 3fe00094e0000359, 80100094e0000359 => fff0000000000000
++ fdivs 3fe00094e0000359, 7ff0000000000000 => 0000000000000000
++ fdivs 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fdivs bfe0000000000001, 0010000000000001 => fff0000000000000
++ fdivs bfe0000000000001, 80100094e0000359 => 7ff0000000000000
++ fdivs bfe0000000000001, 7ff0000000000000 => 8000000000000000
++ fdivs bfe0000000000001, fff8000000000000 => fff8000000000000
++ fdivs 8000000000000000, 0010000000000001 => 8000000000000000
++ fdivs 8000000000000000, 80100094e0000359 => 0000000000000000
++ fdivs 8000000000000000, 7ff0000000000000 => 8000000000000000
++ fdivs 8000000000000000, fff8000000000000 => fff8000000000000
++ fdivs 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
++ fdivs 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
++ fdivs 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
++ fdivs 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
++ fdivs fff8000000000000, 0010000000000001 => fff8000000000000
++ fdivs fff8000000000000, 80100094e0000359 => fff8000000000000
++ fdivs fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fdivs fff8000000000000, fff8000000000000 => fff8000000000000
++
++PPC floating point arith insns
++ with two args with flags update:
++ fadd. 0010000000000001, 0010000000000001 => 0020000000000001
++ fadd. 0010000000000001, 80100094e0000359 => 80000094e0000358
++ fadd. 0010000000000001, 7ff0000000000000 => 7ff0000000000000
++ fadd. 0010000000000001, fff8000000000000 => fff8000000000000
++ fadd. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359
++ fadd. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359
++ fadd. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
++ fadd. 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fadd. bfe0000000000001, 0010000000000001 => bfe0000000000001
++ fadd. bfe0000000000001, 80100094e0000359 => bfe0000000000001
++ fadd. bfe0000000000001, 7ff0000000000000 => 7ff0000000000000
++ fadd. bfe0000000000001, fff8000000000000 => fff8000000000000
++ fadd. 8000000000000000, 0010000000000001 => 0010000000000001
++ fadd. 8000000000000000, 80100094e0000359 => 80100094e0000359
++ fadd. 8000000000000000, 7ff0000000000000 => 7ff0000000000000
++ fadd. 8000000000000000, fff8000000000000 => fff8000000000000
++ fadd. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
++ fadd. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
++ fadd. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
++ fadd. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
++ fadd. fff8000000000000, 0010000000000001 => fff8000000000000
++ fadd. fff8000000000000, 80100094e0000359 => fff8000000000000
++ fadd. fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fadd. fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fadds. 0010000000000001, 0010000000000001 => 0000000000000000
++ fadds. 0010000000000001, 80100094e0000359 => 8000000000000000
++ fadds. 0010000000000001, 7ff0000000000000 => 7ff0000000000000
++ fadds. 0010000000000001, fff8000000000000 => fff8000000000000
++ fadds. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000
++ fadds. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000
++ fadds. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
++ fadds. 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fadds. bfe0000000000001, 0010000000000001 => bfe0000000000000
++ fadds. bfe0000000000001, 80100094e0000359 => bfe0000000000000
++ fadds. bfe0000000000001, 7ff0000000000000 => 7ff0000000000000
++ fadds. bfe0000000000001, fff8000000000000 => fff8000000000000
++ fadds. 8000000000000000, 0010000000000001 => 0000000000000000
++ fadds. 8000000000000000, 80100094e0000359 => 8000000000000000
++ fadds. 8000000000000000, 7ff0000000000000 => 7ff0000000000000
++ fadds. 8000000000000000, fff8000000000000 => fff8000000000000
++ fadds. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
++ fadds. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
++ fadds. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
++ fadds. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
++ fadds. fff8000000000000, 0010000000000001 => fff8000000000000
++ fadds. fff8000000000000, 80100094e0000359 => fff8000000000000
++ fadds. fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fadds. fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fsub. 0010000000000001, 0010000000000001 => 0000000000000000
++ fsub. 0010000000000001, 80100094e0000359 => 0020004a700001ad
++ fsub. 0010000000000001, 7ff0000000000000 => fff0000000000000
++ fsub. 0010000000000001, fff8000000000000 => fff8000000000000
++ fsub. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000359
++ fsub. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000359
++ fsub. 3fe00094e0000359, 7ff0000000000000 => fff0000000000000
++ fsub. 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fsub. bfe0000000000001, 0010000000000001 => bfe0000000000001
++ fsub. bfe0000000000001, 80100094e0000359 => bfe0000000000001
++ fsub. bfe0000000000001, 7ff0000000000000 => fff0000000000000
++ fsub. bfe0000000000001, fff8000000000000 => fff8000000000000
++ fsub. 8000000000000000, 0010000000000001 => 8010000000000001
++ fsub. 8000000000000000, 80100094e0000359 => 00100094e0000359
++ fsub. 8000000000000000, 7ff0000000000000 => fff0000000000000
++ fsub. 8000000000000000, fff8000000000000 => fff8000000000000
++ fsub. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
++ fsub. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
++ fsub. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
++ fsub. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
++ fsub. fff8000000000000, 0010000000000001 => fff8000000000000
++ fsub. fff8000000000000, 80100094e0000359 => fff8000000000000
++ fsub. fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fsub. fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fsubs. 0010000000000001, 0010000000000001 => 0000000000000000
++ fsubs. 0010000000000001, 80100094e0000359 => 0000000000000000
++ fsubs. 0010000000000001, 7ff0000000000000 => fff0000000000000
++ fsubs. 0010000000000001, fff8000000000000 => fff8000000000000
++ fsubs. 3fe00094e0000359, 0010000000000001 => 3fe00094e0000000
++ fsubs. 3fe00094e0000359, 80100094e0000359 => 3fe00094e0000000
++ fsubs. 3fe00094e0000359, 7ff0000000000000 => fff0000000000000
++ fsubs. 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fsubs. bfe0000000000001, 0010000000000001 => bfe0000000000000
++ fsubs. bfe0000000000001, 80100094e0000359 => bfe0000000000000
++ fsubs. bfe0000000000001, 7ff0000000000000 => fff0000000000000
++ fsubs. bfe0000000000001, fff8000000000000 => fff8000000000000
++ fsubs. 8000000000000000, 0010000000000001 => 8000000000000000
++ fsubs. 8000000000000000, 80100094e0000359 => 0000000000000000
++ fsubs. 8000000000000000, 7ff0000000000000 => fff0000000000000
++ fsubs. 8000000000000000, fff8000000000000 => fff8000000000000
++ fsubs. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
++ fsubs. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
++ fsubs. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
++ fsubs. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
++ fsubs. fff8000000000000, 0010000000000001 => fff8000000000000
++ fsubs. fff8000000000000, 80100094e0000359 => fff8000000000000
++ fsubs. fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fsubs. fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fmul. 0010000000000001, 0010000000000001 => 0000000000000000
++ fmul. 0010000000000001, 80100094e0000359 => 8000000000000000
++ fmul. 0010000000000001, 7ff0000000000000 => 7ff0000000000000
++ fmul. 0010000000000001, fff8000000000000 => fff8000000000000
++ fmul. 3fe00094e0000359, 0010000000000001 => 0008004a700001ad
++ fmul. 3fe00094e0000359, 80100094e0000359 => 80080094e2b4a179
++ fmul. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
++ fmul. 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fmul. bfe0000000000001, 0010000000000001 => 8008000000000001
++ fmul. bfe0000000000001, 80100094e0000359 => 0008004a700001ad
++ fmul. bfe0000000000001, 7ff0000000000000 => fff0000000000000
++ fmul. bfe0000000000001, fff8000000000000 => fff8000000000000
++ fmul. 8000000000000000, 0010000000000001 => 8000000000000000
++ fmul. 8000000000000000, 80100094e0000359 => 0000000000000000
++ fmul. 8000000000000000, 7ff0000000000000 => 7ff8000000000000
++ fmul. 8000000000000000, fff8000000000000 => fff8000000000000
++ fmul. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
++ fmul. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
++ fmul. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
++ fmul. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
++ fmul. fff8000000000000, 0010000000000001 => fff8000000000000
++ fmul. fff8000000000000, 80100094e0000359 => fff8000000000000
++ fmul. fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fmul. fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fmuls. 0010000000000001, 0010000000000001 => 0000000000000000
++ fmuls. 0010000000000001, 80100094e0000359 => 8000000000000000
++ fmuls. 0010000000000001, 7ff0000000000000 => 7ff0000000000000
++ fmuls. 0010000000000001, fff8000000000000 => fff8000000000000
++ fmuls. 3fe00094e0000359, 0010000000000001 => 0000000000000000
++ fmuls. 3fe00094e0000359, 80100094e0000359 => 8000000000000000
++ fmuls. 3fe00094e0000359, 7ff0000000000000 => 7ff0000000000000
++ fmuls. 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fmuls. bfe0000000000001, 0010000000000001 => 8000000000000000
++ fmuls. bfe0000000000001, 80100094e0000359 => 0000000000000000
++ fmuls. bfe0000000000001, 7ff0000000000000 => fff0000000000000
++ fmuls. bfe0000000000001, fff8000000000000 => fff8000000000000
++ fmuls. 8000000000000000, 0010000000000001 => 8000000000000000
++ fmuls. 8000000000000000, 80100094e0000359 => 0000000000000000
++ fmuls. 8000000000000000, 7ff0000000000000 => 7ff8000000000000
++ fmuls. 8000000000000000, fff8000000000000 => fff8000000000000
++ fmuls. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
++ fmuls. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
++ fmuls. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
++ fmuls. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
++ fmuls. fff8000000000000, 0010000000000001 => fff8000000000000
++ fmuls. fff8000000000000, 80100094e0000359 => fff8000000000000
++ fmuls. fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fmuls. fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fdiv. 0010000000000001, 0010000000000001 => 3ff0000000000000
++ fdiv. 0010000000000001, 80100094e0000359 => bfeffed64ad20d22
++ fdiv. 0010000000000001, 7ff0000000000000 => 0000000000000000
++ fdiv. 0010000000000001, fff8000000000000 => fff8000000000000
++ fdiv. 3fe00094e0000359, 0010000000000001 => 7fc00094e0000358
++ fdiv. 3fe00094e0000359, 80100094e0000359 => ffc0000000000000
++ fdiv. 3fe00094e0000359, 7ff0000000000000 => 0000000000000000
++ fdiv. 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fdiv. bfe0000000000001, 0010000000000001 => ffc0000000000000
++ fdiv. bfe0000000000001, 80100094e0000359 => 7fbffed64ad20d22
++ fdiv. bfe0000000000001, 7ff0000000000000 => 8000000000000000
++ fdiv. bfe0000000000001, fff8000000000000 => fff8000000000000
++ fdiv. 8000000000000000, 0010000000000001 => 8000000000000000
++ fdiv. 8000000000000000, 80100094e0000359 => 0000000000000000
++ fdiv. 8000000000000000, 7ff0000000000000 => 8000000000000000
++ fdiv. 8000000000000000, fff8000000000000 => fff8000000000000
++ fdiv. 7ff7ffffffffffff, 0010000000000001 => 7fffffffffffffff
++ fdiv. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffffffffff
++ fdiv. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffffffffff
++ fdiv. 7ff7ffffffffffff, fff8000000000000 => 7fffffffffffffff
++ fdiv. fff8000000000000, 0010000000000001 => fff8000000000000
++ fdiv. fff8000000000000, 80100094e0000359 => fff8000000000000
++ fdiv. fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fdiv. fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fdivs. 0010000000000001, 0010000000000001 => 3ff0000000000000
++ fdivs. 0010000000000001, 80100094e0000359 => bfeffed640000000
++ fdivs. 0010000000000001, 7ff0000000000000 => 0000000000000000
++ fdivs. 0010000000000001, fff8000000000000 => fff8000000000000
++ fdivs. 3fe00094e0000359, 0010000000000001 => 7ff0000000000000
++ fdivs. 3fe00094e0000359, 80100094e0000359 => fff0000000000000
++ fdivs. 3fe00094e0000359, 7ff0000000000000 => 0000000000000000
++ fdivs. 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fdivs. bfe0000000000001, 0010000000000001 => fff0000000000000
++ fdivs. bfe0000000000001, 80100094e0000359 => 7ff0000000000000
++ fdivs. bfe0000000000001, 7ff0000000000000 => 8000000000000000
++ fdivs. bfe0000000000001, fff8000000000000 => fff8000000000000
++ fdivs. 8000000000000000, 0010000000000001 => 8000000000000000
++ fdivs. 8000000000000000, 80100094e0000359 => 0000000000000000
++ fdivs. 8000000000000000, 7ff0000000000000 => 8000000000000000
++ fdivs. 8000000000000000, fff8000000000000 => fff8000000000000
++ fdivs. 7ff7ffffffffffff, 0010000000000001 => 7fffffffe0000000
++ fdivs. 7ff7ffffffffffff, 80100094e0000359 => 7fffffffe0000000
++ fdivs. 7ff7ffffffffffff, 7ff0000000000000 => 7fffffffe0000000
++ fdivs. 7ff7ffffffffffff, fff8000000000000 => 7fffffffe0000000
++ fdivs. fff8000000000000, 0010000000000001 => fff8000000000000
++ fdivs. fff8000000000000, 80100094e0000359 => fff8000000000000
++ fdivs. fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fdivs. fff8000000000000, fff8000000000000 => fff8000000000000
++
++PPC floating point compare insns (two args):
++ fcmpo 0010000000000001, 0010000000000001 => fff8000000000000
++ fcmpo 0010000000000001, 80100094e0000359 => fff8000000000000
++ fcmpo 0010000000000001, 7ff0000000000000 => fff8000000000000
++ fcmpo 0010000000000001, fff8000000000000 => fff8000000000000
++ fcmpo 3fe00094e0000359, 0010000000000001 => fff8000000000000
++ fcmpo 3fe00094e0000359, 80100094e0000359 => fff8000000000000
++ fcmpo 3fe00094e0000359, 7ff0000000000000 => fff8000000000000
++ fcmpo 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fcmpo bfe0000000000001, 0010000000000001 => fff8000000000000
++ fcmpo bfe0000000000001, 80100094e0000359 => fff8000000000000
++ fcmpo bfe0000000000001, 7ff0000000000000 => fff8000000000000
++ fcmpo bfe0000000000001, fff8000000000000 => fff8000000000000
++ fcmpo 8000000000000000, 0010000000000001 => fff8000000000000
++ fcmpo 8000000000000000, 80100094e0000359 => fff8000000000000
++ fcmpo 8000000000000000, 7ff0000000000000 => fff8000000000000
++ fcmpo 8000000000000000, fff8000000000000 => fff8000000000000
++ fcmpo 7ff7ffffffffffff, 0010000000000001 => fff8000000000000
++ fcmpo 7ff7ffffffffffff, 80100094e0000359 => fff8000000000000
++ fcmpo 7ff7ffffffffffff, 7ff0000000000000 => fff8000000000000
++ fcmpo 7ff7ffffffffffff, fff8000000000000 => fff8000000000000
++ fcmpo fff8000000000000, 0010000000000001 => fff8000000000000
++ fcmpo fff8000000000000, 80100094e0000359 => fff8000000000000
++ fcmpo fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fcmpo fff8000000000000, fff8000000000000 => fff8000000000000
++
++ fcmpu 0010000000000001, 0010000000000001 => fff8000000000000
++ fcmpu 0010000000000001, 80100094e0000359 => fff8000000000000
++ fcmpu 0010000000000001, 7ff0000000000000 => fff8000000000000
++ fcmpu 0010000000000001, fff8000000000000 => fff8000000000000
++ fcmpu 3fe00094e0000359, 0010000000000001 => fff8000000000000
++ fcmpu 3fe00094e0000359, 80100094e0000359 => fff8000000000000
++ fcmpu 3fe00094e0000359, 7ff0000000000000 => fff8000000000000
++ fcmpu 3fe00094e0000359, fff8000000000000 => fff8000000000000
++ fcmpu bfe0000000000001, 0010000000000001 => fff8000000000000
++ fcmpu bfe0000000000001, 80100094e0000359 => fff8000000000000
++ fcmpu bfe0000000000001, 7ff0000000000000 => fff8000000000000
++ fcmpu bfe0000000000001, fff8000000000000 => fff8000000000000
++ fcmpu 8000000000000000, 0010000000000001 => fff8000000000000
++ fcmpu 8000000000000000, 80100094e0000359 => fff8000000000000
++ fcmpu 8000000000000000, 7ff0000000000000 => fff8000000000000
++ fcmpu 8000000000000000, fff8000000000000 => fff8000000000000
++ fcmpu 7ff7ffffffffffff, 0010000000000001 => fff8000000000000
++ fcmpu 7ff7ffffffffffff, 80100094e0000359 => fff8000000000000
++ fcmpu 7ff7ffffffffffff, 7ff0000000000000 => fff8000000000000
++ fcmpu 7ff7ffffffffffff, fff8000000000000 => fff8000000000000
++ fcmpu fff8000000000000, 0010000000000001 => fff8000000000000
++ fcmpu fff8000000000000, 80100094e0000359 => fff8000000000000
++ fcmpu fff8000000000000, 7ff0000000000000 => fff8000000000000
++ fcmpu fff8000000000000, fff8000000000000 => fff8000000000000
++
++PPC floating point arith insns with one arg:
++ fres 0010000000000001 => 7ff0000000000000
++ fres 00100094e0000359 => 7ff0000000000000
++ fres 3fe0000000000001 => 4000000000000000
++ fres 3fe00094e0000359 => 3ffff00000000000
++ fres 8010000000000001 => fff0000000000000
++ fres 80100094e0000359 => fff0000000000000
++ fres bfe0000000000001 => c000000000000000
++ fres bfe00094e0000359 => bffff00000000000
++ fres 0000000000000000 => 7ff0000000000000
++ fres 8000000000000000 => fff0000000000000
++ fres 7ff0000000000000 => 0000000000000000
++ fres fff0000000000000 => 8000000000000000
++ fres 7ff7ffffffffffff => 7ffff00000000000
++ fres fff7ffffffffffff => fffff00000000000
++ fres 7ff8000000000000 => 7ff8000000000000
++ fres fff8000000000000 => fff8000000000000
++
++ frsqrte 0010000000000001 => 5fdf000000000000
++ frsqrte 00100094e0000359 => 5fdf000000000000
++ frsqrte 3fe0000000000001 => 3ff6000000000000
++ frsqrte 3fe00094e0000359 => 3ff6000000000000
++ frsqrte 8010000000000001 => 7ff8000000000000
++ frsqrte 80100094e0000359 => 7ff8000000000000
++ frsqrte bfe0000000000001 => 7ff8000000000000
++ frsqrte bfe00094e0000359 => 7ff8000000000000
++ frsqrte 0000000000000000 => 7ff0000000000000
++ frsqrte 8000000000000000 => fff0000000000000
++ frsqrte 7ff0000000000000 => 0000000000000000
++ frsqrte fff0000000000000 => 7ff8000000000000
++ frsqrte 7ff7ffffffffffff => 7fff000000000000
++ frsqrte fff7ffffffffffff => ffff000000000000
++ frsqrte 7ff8000000000000 => 7ff8000000000000
++ frsqrte fff8000000000000 => fff8000000000000
++
++ frsp 0010000000000001 => 0000000000000000
++ frsp 00100094e0000359 => 0000000000000000
++ frsp 3fe0000000000001 => 3fe0000000000000
++ frsp 3fe00094e0000359 => 3fe00094e0000000
++ frsp 8010000000000001 => 8000000000000000
++ frsp 80100094e0000359 => 8000000000000000
++ frsp bfe0000000000001 => bfe0000000000000
++ frsp bfe00094e0000359 => bfe00094e0000000
++ frsp 0000000000000000 => 0000000000000000
++ frsp 8000000000000000 => 8000000000000000
++ frsp 7ff0000000000000 => 7ff0000000000000
++ frsp fff0000000000000 => fff0000000000000
++ frsp 7ff7ffffffffffff => 7fffffffe0000000
++ frsp fff7ffffffffffff => ffffffffe0000000
++ frsp 7ff8000000000000 => 7ff8000000000000
++ frsp fff8000000000000 => fff8000000000000
++
++ fctiw 0010000000000001 => 0000000000000000
++ fctiw 00100094e0000359 => 0000000000000000
++ fctiw 3fe0000000000001 => 0000000000000001
++ fctiw 3fe00094e0000359 => 0000000000000001
++ fctiw 8010000000000001 => 0000000000000000
++ fctiw 80100094e0000359 => 0000000000000000
++ fctiw bfe0000000000001 => 00000000ffffffff
++ fctiw bfe00094e0000359 => 00000000ffffffff
++ fctiw 0000000000000000 => 0000000000000000
++ fctiw 8000000000000000 => 0000000000000000
++ fctiw 7ff0000000000000 => 000000007fffffff
++ fctiw fff0000000000000 => 0000000080000000
++ fctiw 7ff7ffffffffffff => 0000000080000000
++ fctiw fff7ffffffffffff => 0000000080000000
++ fctiw 7ff8000000000000 => 0000000080000000
++ fctiw fff8000000000000 => 0000000080000000
++
++ fctiwz 0010000000000001 => 0000000000000000
++ fctiwz 00100094e0000359 => 0000000000000000
++ fctiwz 3fe0000000000001 => 0000000000000000
++ fctiwz 3fe00094e0000359 => 0000000000000000
++ fctiwz 8010000000000001 => 0000000000000000
++ fctiwz 80100094e0000359 => 0000000000000000
++ fctiwz bfe0000000000001 => 0000000000000000
++ fctiwz bfe00094e0000359 => 0000000000000000
++ fctiwz 0000000000000000 => 0000000000000000
++ fctiwz 8000000000000000 => 0000000000000000
++ fctiwz 7ff0000000000000 => 000000007fffffff
++ fctiwz fff0000000000000 => 0000000080000000
++ fctiwz 7ff7ffffffffffff => 0000000080000000
++ fctiwz fff7ffffffffffff => 0000000080000000
++ fctiwz 7ff8000000000000 => 0000000080000000
++ fctiwz fff8000000000000 => 0000000080000000
++
++ fmr 0010000000000001 => 0010000000000001
++ fmr 00100094e0000359 => 00100094e0000359
++ fmr 3fe0000000000001 => 3fe0000000000001
++ fmr 3fe00094e0000359 => 3fe00094e0000359
++ fmr 8010000000000001 => 8010000000000001
++ fmr 80100094e0000359 => 80100094e0000359
++ fmr bfe0000000000001 => bfe0000000000001
++ fmr bfe00094e0000359 => bfe00094e0000359
++ fmr 0000000000000000 => 0000000000000000
++ fmr 8000000000000000 => 8000000000000000
++ fmr 7ff0000000000000 => 7ff0000000000000
++ fmr fff0000000000000 => fff0000000000000
++ fmr 7ff7ffffffffffff => 7ff7ffffffffffff
++ fmr fff7ffffffffffff => fff7ffffffffffff
++ fmr 7ff8000000000000 => 7ff8000000000000
++ fmr fff8000000000000 => fff8000000000000
++
++ fneg 0010000000000001 => 8010000000000001
++ fneg 00100094e0000359 => 80100094e0000359
++ fneg 3fe0000000000001 => bfe0000000000001
++ fneg 3fe00094e0000359 => bfe00094e0000359
++ fneg 8010000000000001 => 0010000000000001
++ fneg 80100094e0000359 => 00100094e0000359
++ fneg bfe0000000000001 => 3fe0000000000001
++ fneg bfe00094e0000359 => 3fe00094e0000359
++ fneg 0000000000000000 => 8000000000000000
++ fneg 8000000000000000 => 0000000000000000
++ fneg 7ff0000000000000 => fff0000000000000
++ fneg fff0000000000000 => 7ff0000000000000
++ fneg 7ff7ffffffffffff => fff7ffffffffffff
++ fneg fff7ffffffffffff => 7ff7ffffffffffff
++ fneg 7ff8000000000000 => fff8000000000000
++ fneg fff8000000000000 => 7ff8000000000000
++
++ fabs 0010000000000001 => 0010000000000001
++ fabs 00100094e0000359 => 00100094e0000359
++ fabs 3fe0000000000001 => 3fe0000000000001
++ fabs 3fe00094e0000359 => 3fe00094e0000359
++ fabs 8010000000000001 => 0010000000000001
++ fabs 80100094e0000359 => 00100094e0000359
++ fabs bfe0000000000001 => 3fe0000000000001
++ fabs bfe00094e0000359 => 3fe00094e0000359
++ fabs 0000000000000000 => 0000000000000000
++ fabs 8000000000000000 => 0000000000000000
++ fabs 7ff0000000000000 => 7ff0000000000000
++ fabs fff0000000000000 => 7ff0000000000000
++ fabs 7ff7ffffffffffff => 7ff7ffffffffffff
++ fabs fff7ffffffffffff => 7ff7ffffffffffff
++ fabs 7ff8000000000000 => 7ff8000000000000
++ fabs fff8000000000000 => 7ff8000000000000
++
++ fnabs 0010000000000001 => 8010000000000001
++ fnabs 00100094e0000359 => 80100094e0000359
++ fnabs 3fe0000000000001 => bfe0000000000001
++ fnabs 3fe00094e0000359 => bfe00094e0000359
++ fnabs 8010000000000001 => 8010000000000001
++ fnabs 80100094e0000359 => 80100094e0000359
++ fnabs bfe0000000000001 => bfe0000000000001
++ fnabs bfe00094e0000359 => bfe00094e0000359
++ fnabs 0000000000000000 => 8000000000000000
++ fnabs 8000000000000000 => 8000000000000000
++ fnabs 7ff0000000000000 => fff0000000000000
++ fnabs fff0000000000000 => fff0000000000000
++ fnabs 7ff7ffffffffffff => fff7ffffffffffff
++ fnabs fff7ffffffffffff => fff7ffffffffffff
++ fnabs 7ff8000000000000 => fff8000000000000
++ fnabs fff8000000000000 => fff8000000000000
++
++ fsqrt 0010000000000001 => 2000000000000000
++ fsqrt 00100094e0000359 => 2000004a6f52dd4a
++ fsqrt 3fe0000000000001 => 3fe6a09e667f3bcd
++ fsqrt 3fe00094e0000359 => 3fe6a107aacb50df
++ fsqrt 8010000000000001 => 7ff8000000000000
++ fsqrt 80100094e0000359 => 7ff8000000000000
++ fsqrt bfe0000000000001 => 7ff8000000000000
++ fsqrt bfe00094e0000359 => 7ff8000000000000
++ fsqrt 0000000000000000 => 0000000000000000
++ fsqrt 8000000000000000 => 8000000000000000
++ fsqrt 7ff0000000000000 => 7ff0000000000000
++ fsqrt fff0000000000000 => 7ff8000000000000
++ fsqrt 7ff7ffffffffffff => 7fffffffffffffff
++ fsqrt fff7ffffffffffff => ffffffffffffffff
++ fsqrt 7ff8000000000000 => 7ff8000000000000
++ fsqrt fff8000000000000 => fff8000000000000
++
++ fcfid 0010000000000001 => 4330000000000001
++ fcfid 00100094e0000359 => 43300094e0000359
++ fcfid 3fe0000000000001 => 43cff00000000000
++ fcfid 3fe00094e0000359 => 43cff0004a700002
++ fcfid 8010000000000001 => c3dffc0000000000
++ fcfid 80100094e0000359 => c3dffbffdac7ffff
++ fcfid bfe0000000000001 => c3d0080000000000
++ fcfid bfe00094e0000359 => c3d007ffdac7ffff
++ fcfid 0000000000000000 => 0000000000000000
++ fcfid 8000000000000000 => c3e0000000000000
++ fcfid 7ff0000000000000 => 43dffc0000000000
++ fcfid fff0000000000000 => c330000000000000
++ fcfid 7ff7ffffffffffff => 43dffe0000000000
++ fcfid fff7ffffffffffff => c320000000000002
++ fcfid 7ff8000000000000 => 43dffe0000000000
++ fcfid fff8000000000000 => c320000000000000
++
++ fctid 0010000000000001 => 0000000000000000
++ fctid 00100094e0000359 => 0000000000000000
++ fctid 3fe0000000000001 => 0000000000000001
++ fctid 3fe00094e0000359 => 0000000000000001
++ fctid 8010000000000001 => 0000000000000000
++ fctid 80100094e0000359 => 0000000000000000
++ fctid bfe0000000000001 => ffffffffffffffff
++ fctid bfe00094e0000359 => ffffffffffffffff
++ fctid 0000000000000000 => 0000000000000000
++ fctid 8000000000000000 => 0000000000000000
++ fctid 7ff0000000000000 => 7fffffffffffffff
++ fctid fff0000000000000 => 8000000000000000
++ fctid 7ff7ffffffffffff => 8000000000000000
++ fctid fff7ffffffffffff => 8000000000000000
++ fctid 7ff8000000000000 => 8000000000000000
++ fctid fff8000000000000 => 8000000000000000
++
++ fctidz 0010000000000001 => 0000000000000000
++ fctidz 00100094e0000359 => 0000000000000000
++ fctidz 3fe0000000000001 => 0000000000000000
++ fctidz 3fe00094e0000359 => 0000000000000000
++ fctidz 8010000000000001 => 0000000000000000
++ fctidz 80100094e0000359 => 0000000000000000
++ fctidz bfe0000000000001 => 0000000000000000
++ fctidz bfe00094e0000359 => 0000000000000000
++ fctidz 0000000000000000 => 0000000000000000
++ fctidz 8000000000000000 => 0000000000000000
++ fctidz 7ff0000000000000 => 7fffffffffffffff
++ fctidz fff0000000000000 => 8000000000000000
++ fctidz 7ff7ffffffffffff => 8000000000000000
++ fctidz fff7ffffffffffff => 8000000000000000
++ fctidz 7ff8000000000000 => 8000000000000000
++ fctidz fff8000000000000 => 8000000000000000
++
++PPC floating point arith insns
++ with one arg with flags update:
++ fres. 0010000000000001 => 7ff0000000000000
++ fres. 00100094e0000359 => 7ff0000000000000
++ fres. 3fe0000000000001 => 4000000000000000
++ fres. 3fe00094e0000359 => 3ffff00000000000
++ fres. 8010000000000001 => fff0000000000000
++ fres. 80100094e0000359 => fff0000000000000
++ fres. bfe0000000000001 => c000000000000000
++ fres. bfe00094e0000359 => bffff00000000000
++ fres. 0000000000000000 => 7ff0000000000000
++ fres. 8000000000000000 => fff0000000000000
++ fres. 7ff0000000000000 => 0000000000000000
++ fres. fff0000000000000 => 8000000000000000
++ fres. 7ff7ffffffffffff => 7ffff00000000000
++ fres. fff7ffffffffffff => fffff00000000000
++ fres. 7ff8000000000000 => 7ff8000000000000
++ fres. fff8000000000000 => fff8000000000000
++
++ frsqrte. 0010000000000001 => 5fdf000000000000
++ frsqrte. 00100094e0000359 => 5fdf000000000000
++ frsqrte. 3fe0000000000001 => 3ff6000000000000
++ frsqrte. 3fe00094e0000359 => 3ff6000000000000
++ frsqrte. 8010000000000001 => 7ff8000000000000
++ frsqrte. 80100094e0000359 => 7ff8000000000000
++ frsqrte. bfe0000000000001 => 7ff8000000000000
++ frsqrte. bfe00094e0000359 => 7ff8000000000000
++ frsqrte. 0000000000000000 => 7ff0000000000000
++ frsqrte. 8000000000000000 => fff0000000000000
++ frsqrte. 7ff0000000000000 => 0000000000000000
++ frsqrte. fff0000000000000 => 7ff8000000000000
++ frsqrte. 7ff7ffffffffffff => 7fff000000000000
++ frsqrte. fff7ffffffffffff => ffff000000000000
++ frsqrte. 7ff8000000000000 => 7ff8000000000000
++ frsqrte. fff8000000000000 => fff8000000000000
++
++ frsp. 0010000000000001 => 0000000000000000
++ frsp. 00100094e0000359 => 0000000000000000
++ frsp. 3fe0000000000001 => 3fe0000000000000
++ frsp. 3fe00094e0000359 => 3fe00094e0000000
++ frsp. 8010000000000001 => 8000000000000000
++ frsp. 80100094e0000359 => 8000000000000000
++ frsp. bfe0000000000001 => bfe0000000000000
++ frsp. bfe00094e0000359 => bfe00094e0000000
++ frsp. 0000000000000000 => 0000000000000000
++ frsp. 8000000000000000 => 8000000000000000
++ frsp. 7ff0000000000000 => 7ff0000000000000
++ frsp. fff0000000000000 => fff0000000000000
++ frsp. 7ff7ffffffffffff => 7fffffffe0000000
++ frsp. fff7ffffffffffff => ffffffffe0000000
++ frsp. 7ff8000000000000 => 7ff8000000000000
++ frsp. fff8000000000000 => fff8000000000000
++
++ fctiw. 0010000000000001 => 0000000000000000
++ fctiw. 00100094e0000359 => 0000000000000000
++ fctiw. 3fe0000000000001 => 0000000000000001
++ fctiw. 3fe00094e0000359 => 0000000000000001
++ fctiw. 8010000000000001 => 0000000000000000
++ fctiw. 80100094e0000359 => 0000000000000000
++ fctiw. bfe0000000000001 => 00000000ffffffff
++ fctiw. bfe00094e0000359 => 00000000ffffffff
++ fctiw. 0000000000000000 => 0000000000000000
++ fctiw. 8000000000000000 => 0000000000000000
++ fctiw. 7ff0000000000000 => 000000007fffffff
++ fctiw. fff0000000000000 => 0000000080000000
++ fctiw. 7ff7ffffffffffff => 0000000080000000
++ fctiw. fff7ffffffffffff => 0000000080000000
++ fctiw. 7ff8000000000000 => 0000000080000000
++ fctiw. fff8000000000000 => 0000000080000000
++
++ fctiwz. 0010000000000001 => 0000000000000000
++ fctiwz. 00100094e0000359 => 0000000000000000
++ fctiwz. 3fe0000000000001 => 0000000000000000
++ fctiwz. 3fe00094e0000359 => 0000000000000000
++ fctiwz. 8010000000000001 => 0000000000000000
++ fctiwz. 80100094e0000359 => 0000000000000000
++ fctiwz. bfe0000000000001 => 0000000000000000
++ fctiwz. bfe00094e0000359 => 0000000000000000
++ fctiwz. 0000000000000000 => 0000000000000000
++ fctiwz. 8000000000000000 => 0000000000000000
++ fctiwz. 7ff0000000000000 => 000000007fffffff
++ fctiwz. fff0000000000000 => 0000000080000000
++ fctiwz. 7ff7ffffffffffff => 0000000080000000
++ fctiwz. fff7ffffffffffff => 0000000080000000
++ fctiwz. 7ff8000000000000 => 0000000080000000
++ fctiwz. fff8000000000000 => 0000000080000000
++
++ fmr. 0010000000000001 => 0010000000000001
++ fmr. 00100094e0000359 => 00100094e0000359
++ fmr. 3fe0000000000001 => 3fe0000000000001
++ fmr. 3fe00094e0000359 => 3fe00094e0000359
++ fmr. 8010000000000001 => 8010000000000001
++ fmr. 80100094e0000359 => 80100094e0000359
++ fmr. bfe0000000000001 => bfe0000000000001
++ fmr. bfe00094e0000359 => bfe00094e0000359
++ fmr. 0000000000000000 => 0000000000000000
++ fmr. 8000000000000000 => 8000000000000000
++ fmr. 7ff0000000000000 => 7ff0000000000000
++ fmr. fff0000000000000 => fff0000000000000
++ fmr. 7ff7ffffffffffff => 7ff7ffffffffffff
++ fmr. fff7ffffffffffff => fff7ffffffffffff
++ fmr. 7ff8000000000000 => 7ff8000000000000
++ fmr. fff8000000000000 => fff8000000000000
++
++ fneg. 0010000000000001 => 8010000000000001
++ fneg. 00100094e0000359 => 80100094e0000359
++ fneg. 3fe0000000000001 => bfe0000000000001
++ fneg. 3fe00094e0000359 => bfe00094e0000359
++ fneg. 8010000000000001 => 0010000000000001
++ fneg. 80100094e0000359 => 00100094e0000359
++ fneg. bfe0000000000001 => 3fe0000000000001
++ fneg. bfe00094e0000359 => 3fe00094e0000359
++ fneg. 0000000000000000 => 8000000000000000
++ fneg. 8000000000000000 => 0000000000000000
++ fneg. 7ff0000000000000 => fff0000000000000
++ fneg. fff0000000000000 => 7ff0000000000000
++ fneg. 7ff7ffffffffffff => fff7ffffffffffff
++ fneg. fff7ffffffffffff => 7ff7ffffffffffff
++ fneg. 7ff8000000000000 => fff8000000000000
++ fneg. fff8000000000000 => 7ff8000000000000
++
++ fabs. 0010000000000001 => 0010000000000001
++ fabs. 00100094e0000359 => 00100094e0000359
++ fabs. 3fe0000000000001 => 3fe0000000000001
++ fabs. 3fe00094e0000359 => 3fe00094e0000359
++ fabs. 8010000000000001 => 0010000000000001
++ fabs. 80100094e0000359 => 00100094e0000359
++ fabs. bfe0000000000001 => 3fe0000000000001
++ fabs. bfe00094e0000359 => 3fe00094e0000359
++ fabs. 0000000000000000 => 0000000000000000
++ fabs. 8000000000000000 => 0000000000000000
++ fabs. 7ff0000000000000 => 7ff0000000000000
++ fabs. fff0000000000000 => 7ff0000000000000
++ fabs. 7ff7ffffffffffff => 7ff7ffffffffffff
++ fabs. fff7ffffffffffff => 7ff7ffffffffffff
++ fabs. 7ff8000000000000 => 7ff8000000000000
++ fabs. fff8000000000000 => 7ff8000000000000
++
++ fnabs. 0010000000000001 => 8010000000000001
++ fnabs. 00100094e0000359 => 80100094e0000359
++ fnabs. 3fe0000000000001 => bfe0000000000001
++ fnabs. 3fe00094e0000359 => bfe00094e0000359
++ fnabs. 8010000000000001 => 8010000000000001
++ fnabs. 80100094e0000359 => 80100094e0000359
++ fnabs. bfe0000000000001 => bfe0000000000001
++ fnabs. bfe00094e0000359 => bfe00094e0000359
++ fnabs. 0000000000000000 => 8000000000000000
++ fnabs. 8000000000000000 => 8000000000000000
++ fnabs. 7ff0000000000000 => fff0000000000000
++ fnabs. fff0000000000000 => fff0000000000000
++ fnabs. 7ff7ffffffffffff => fff7ffffffffffff
++ fnabs. fff7ffffffffffff => fff7ffffffffffff
++ fnabs. 7ff8000000000000 => fff8000000000000
++ fnabs. fff8000000000000 => fff8000000000000
++
++ fcfid. 0010000000000001 => 4330000000000001
++ fcfid. 00100094e0000359 => 43300094e0000359
++ fcfid. 3fe0000000000001 => 43cff00000000000
++ fcfid. 3fe00094e0000359 => 43cff0004a700002
++ fcfid. 8010000000000001 => c3dffc0000000000
++ fcfid. 80100094e0000359 => c3dffbffdac7ffff
++ fcfid. bfe0000000000001 => c3d0080000000000
++ fcfid. bfe00094e0000359 => c3d007ffdac7ffff
++ fcfid. 0000000000000000 => 0000000000000000
++ fcfid. 8000000000000000 => c3e0000000000000
++ fcfid. 7ff0000000000000 => 43dffc0000000000
++ fcfid. fff0000000000000 => c330000000000000
++ fcfid. 7ff7ffffffffffff => 43dffe0000000000
++ fcfid. fff7ffffffffffff => c320000000000002
++ fcfid. 7ff8000000000000 => 43dffe0000000000
++ fcfid. fff8000000000000 => c320000000000000
++
++ fctid. 0010000000000001 => 0000000000000000
++ fctid. 00100094e0000359 => 0000000000000000
++ fctid. 3fe0000000000001 => 0000000000000001
++ fctid. 3fe00094e0000359 => 0000000000000001
++ fctid. 8010000000000001 => 0000000000000000
++ fctid. 80100094e0000359 => 0000000000000000
++ fctid. bfe0000000000001 => ffffffffffffffff
++ fctid. bfe00094e0000359 => ffffffffffffffff
++ fctid. 0000000000000000 => 0000000000000000
++ fctid. 8000000000000000 => 0000000000000000
++ fctid. 7ff0000000000000 => 7fffffffffffffff
++ fctid. fff0000000000000 => 8000000000000000
++ fctid. 7ff7ffffffffffff => 8000000000000000
++ fctid. fff7ffffffffffff => 8000000000000000
++ fctid. 7ff8000000000000 => 8000000000000000
++ fctid. fff8000000000000 => 8000000000000000
++
++ fctidz. 0010000000000001 => 0000000000000000
++ fctidz. 00100094e0000359 => 0000000000000000
++ fctidz. 3fe0000000000001 => 0000000000000000
++ fctidz. 3fe00094e0000359 => 0000000000000000
++ fctidz. 8010000000000001 => 0000000000000000
++ fctidz. 80100094e0000359 => 0000000000000000
++ fctidz. bfe0000000000001 => 0000000000000000
++ fctidz. bfe00094e0000359 => 0000000000000000
++ fctidz. 0000000000000000 => 0000000000000000
++ fctidz. 8000000000000000 => 0000000000000000
++ fctidz. 7ff0000000000000 => 7fffffffffffffff
++ fctidz. fff0000000000000 => 8000000000000000
++ fctidz. 7ff7ffffffffffff => 8000000000000000
++ fctidz. fff7ffffffffffff => 8000000000000000
++ fctidz. 7ff8000000000000 => 8000000000000000
++ fctidz. fff8000000000000 => 8000000000000000
++
++PPC floating point status register manipulation insns:
++PPC floating point status register manipulation insns
++ with flags update:
++PPC float load insns
++ with one register + one 16 bits immediate args with flags update:
++ lfs 0010000000000001, 65416 => 36a0000000000000, 0
++ lfs 00100094e0000359, 65424 => c400006b20000000, 0
++ lfs 3fe0000000000001, 65432 => 36a0000000000000, 0
++ lfs 3fe00094e0000359, 65440 => c400006b20000000, 0
++ lfs 8010000000000001, 65448 => 36a0000000000000, 0
++ lfs 80100094e0000359, 65456 => c400006b20000000, 0
++ lfs bfe0000000000001, 65464 => 36a0000000000000, 0
++ lfs bfe00094e0000359, 65472 => c400006b20000000, 0
++ lfs 0000000000000000, 65480 => 0000000000000000, 0
++ lfs 8000000000000000, 65488 => 0000000000000000, 0
++ lfs 7ff0000000000000, 65496 => 0000000000000000, 0
++ lfs fff0000000000000, 65504 => 0000000000000000, 0
++ lfs 7ff7ffffffffffff, 65512 => ffffffffe0000000, 0
++ lfs fff7ffffffffffff, 65520 => ffffffffe0000000, 0
++ lfs 7ff8000000000000, 65528 => 0000000000000000, 0
++ lfs 0010000000000001, 0 => 36a0000000000000, 0
++ lfs 00100094e0000359, 8 => c400006b20000000, 0
++ lfs 3fe0000000000001, 16 => 36a0000000000000, 0
++ lfs 3fe00094e0000359, 24 => c400006b20000000, 0
++ lfs 8010000000000001, 32 => 36a0000000000000, 0
++ lfs 80100094e0000359, 40 => c400006b20000000, 0
++ lfs bfe0000000000001, 48 => 36a0000000000000, 0
++ lfs bfe00094e0000359, 56 => c400006b20000000, 0
++ lfs 0000000000000000, 64 => 0000000000000000, 0
++ lfs 8000000000000000, 72 => 0000000000000000, 0
++ lfs 7ff0000000000000, 80 => 0000000000000000, 0
++ lfs fff0000000000000, 88 => 0000000000000000, 0
++ lfs 7ff7ffffffffffff, 96 => ffffffffe0000000, 0
++ lfs fff7ffffffffffff, 104 => ffffffffe0000000, 0
++ lfs 7ff8000000000000, 112 => 0000000000000000, 0
++ lfs fff8000000000000, 120 => 0000000000000000, 0
++
++ lfsu 0010000000000001, 65416 => 36a0000000000000, -120
++ lfsu 00100094e0000359, 65424 => c400006b20000000, -112
++ lfsu 3fe0000000000001, 65432 => 36a0000000000000, -104
++ lfsu 3fe00094e0000359, 65440 => c400006b20000000, -96
++ lfsu 8010000000000001, 65448 => 36a0000000000000, -88
++ lfsu 80100094e0000359, 65456 => c400006b20000000, -80
++ lfsu bfe0000000000001, 65464 => 36a0000000000000, -72
++ lfsu bfe00094e0000359, 65472 => c400006b20000000, -64
++ lfsu 0000000000000000, 65480 => 0000000000000000, -56
++ lfsu 8000000000000000, 65488 => 0000000000000000, -48
++ lfsu 7ff0000000000000, 65496 => 0000000000000000, -40
++ lfsu fff0000000000000, 65504 => 0000000000000000, -32
++ lfsu 7ff7ffffffffffff, 65512 => ffffffffe0000000, -24
++ lfsu fff7ffffffffffff, 65520 => ffffffffe0000000, -16
++ lfsu 7ff8000000000000, 65528 => 0000000000000000, -8
++ lfsu 0010000000000001, 0 => 36a0000000000000, 0
++ lfsu 00100094e0000359, 8 => c400006b20000000, 8
++ lfsu 3fe0000000000001, 16 => 36a0000000000000, 16
++ lfsu 3fe00094e0000359, 24 => c400006b20000000, 24
++ lfsu 8010000000000001, 32 => 36a0000000000000, 32
++ lfsu 80100094e0000359, 40 => c400006b20000000, 40
++ lfsu bfe0000000000001, 48 => 36a0000000000000, 48
++ lfsu bfe00094e0000359, 56 => c400006b20000000, 56
++ lfsu 0000000000000000, 64 => 0000000000000000, 64
++ lfsu 8000000000000000, 72 => 0000000000000000, 72
++ lfsu 7ff0000000000000, 80 => 0000000000000000, 80
++ lfsu fff0000000000000, 88 => 0000000000000000, 88
++ lfsu 7ff7ffffffffffff, 96 => ffffffffe0000000, 96
++ lfsu fff7ffffffffffff, 104 => ffffffffe0000000, 104
++ lfsu 7ff8000000000000, 112 => 0000000000000000, 112
++ lfsu fff8000000000000, 120 => 0000000000000000, 120
++
++ lfd 0010000000000001, 65416 => 0010000000000001, 0
++ lfd 00100094e0000359, 65424 => 00100094e0000359, 0
++ lfd 3fe0000000000001, 65432 => 3fe0000000000001, 0
++ lfd 3fe00094e0000359, 65440 => 3fe00094e0000359, 0
++ lfd 8010000000000001, 65448 => 8010000000000001, 0
++ lfd 80100094e0000359, 65456 => 80100094e0000359, 0
++ lfd bfe0000000000001, 65464 => bfe0000000000001, 0
++ lfd bfe00094e0000359, 65472 => bfe00094e0000359, 0
++ lfd 0000000000000000, 65480 => 0000000000000000, 0
++ lfd 8000000000000000, 65488 => 8000000000000000, 0
++ lfd 7ff0000000000000, 65496 => 7ff0000000000000, 0
++ lfd fff0000000000000, 65504 => fff0000000000000, 0
++ lfd 7ff7ffffffffffff, 65512 => 7ff7ffffffffffff, 0
++ lfd fff7ffffffffffff, 65520 => fff7ffffffffffff, 0
++ lfd 7ff8000000000000, 65528 => 7ff8000000000000, 0
++ lfd 0010000000000001, 0 => 0010000000000001, 0
++ lfd 00100094e0000359, 8 => 00100094e0000359, 0
++ lfd 3fe0000000000001, 16 => 3fe0000000000001, 0
++ lfd 3fe00094e0000359, 24 => 3fe00094e0000359, 0
++ lfd 8010000000000001, 32 => 8010000000000001, 0
++ lfd 80100094e0000359, 40 => 80100094e0000359, 0
++ lfd bfe0000000000001, 48 => bfe0000000000001, 0
++ lfd bfe00094e0000359, 56 => bfe00094e0000359, 0
++ lfd 0000000000000000, 64 => 0000000000000000, 0
++ lfd 8000000000000000, 72 => 8000000000000000, 0
++ lfd 7ff0000000000000, 80 => 7ff0000000000000, 0
++ lfd fff0000000000000, 88 => fff0000000000000, 0
++ lfd 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0
++ lfd fff7ffffffffffff, 104 => fff7ffffffffffff, 0
++ lfd 7ff8000000000000, 112 => 7ff8000000000000, 0
++ lfd fff8000000000000, 120 => fff8000000000000, 0
++
++ lfdu 0010000000000001, 65416 => 0010000000000001, -120
++ lfdu 00100094e0000359, 65424 => 00100094e0000359, -112
++ lfdu 3fe0000000000001, 65432 => 3fe0000000000001, -104
++ lfdu 3fe00094e0000359, 65440 => 3fe00094e0000359, -96
++ lfdu 8010000000000001, 65448 => 8010000000000001, -88
++ lfdu 80100094e0000359, 65456 => 80100094e0000359, -80
++ lfdu bfe0000000000001, 65464 => bfe0000000000001, -72
++ lfdu bfe00094e0000359, 65472 => bfe00094e0000359, -64
++ lfdu 0000000000000000, 65480 => 0000000000000000, -56
++ lfdu 8000000000000000, 65488 => 8000000000000000, -48
++ lfdu 7ff0000000000000, 65496 => 7ff0000000000000, -40
++ lfdu fff0000000000000, 65504 => fff0000000000000, -32
++ lfdu 7ff7ffffffffffff, 65512 => 7ff7ffffffffffff, -24
++ lfdu fff7ffffffffffff, 65520 => fff7ffffffffffff, -16
++ lfdu 7ff8000000000000, 65528 => 7ff8000000000000, -8
++ lfdu 0010000000000001, 0 => 0010000000000001, 0
++ lfdu 00100094e0000359, 8 => 00100094e0000359, 8
++ lfdu 3fe0000000000001, 16 => 3fe0000000000001, 16
++ lfdu 3fe00094e0000359, 24 => 3fe00094e0000359, 24
++ lfdu 8010000000000001, 32 => 8010000000000001, 32
++ lfdu 80100094e0000359, 40 => 80100094e0000359, 40
++ lfdu bfe0000000000001, 48 => bfe0000000000001, 48
++ lfdu bfe00094e0000359, 56 => bfe00094e0000359, 56
++ lfdu 0000000000000000, 64 => 0000000000000000, 64
++ lfdu 8000000000000000, 72 => 8000000000000000, 72
++ lfdu 7ff0000000000000, 80 => 7ff0000000000000, 80
++ lfdu fff0000000000000, 88 => fff0000000000000, 88
++ lfdu 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96
++ lfdu fff7ffffffffffff, 104 => fff7ffffffffffff, 104
++ lfdu 7ff8000000000000, 112 => 7ff8000000000000, 112
++ lfdu fff8000000000000, 120 => fff8000000000000, 120
++
++PPC float load insns with two register args:
++ lfsx 0010000000000001, -120 => 36a0000000000000, 0
++ lfsx 00100094e0000359, -112 => c400006b20000000, 0
++ lfsx 3fe0000000000001, -104 => 36a0000000000000, 0
++ lfsx 3fe00094e0000359, -96 => c400006b20000000, 0
++ lfsx 8010000000000001, -88 => 36a0000000000000, 0
++ lfsx 80100094e0000359, -80 => c400006b20000000, 0
++ lfsx bfe0000000000001, -72 => 36a0000000000000, 0
++ lfsx bfe00094e0000359, -64 => c400006b20000000, 0
++ lfsx 0000000000000000, -56 => 0000000000000000, 0
++ lfsx 8000000000000000, -48 => 0000000000000000, 0
++ lfsx 7ff0000000000000, -40 => 0000000000000000, 0
++ lfsx fff0000000000000, -32 => 0000000000000000, 0
++ lfsx 7ff7ffffffffffff, -24 => ffffffffe0000000, 0
++ lfsx fff7ffffffffffff, -16 => ffffffffe0000000, 0
++ lfsx 7ff8000000000000, -8 => 0000000000000000, 0
++ lfsx 0010000000000001, 0 => 36a0000000000000, 0
++ lfsx 00100094e0000359, 8 => c400006b20000000, 0
++ lfsx 3fe0000000000001, 16 => 36a0000000000000, 0
++ lfsx 3fe00094e0000359, 24 => c400006b20000000, 0
++ lfsx 8010000000000001, 32 => 36a0000000000000, 0
++ lfsx 80100094e0000359, 40 => c400006b20000000, 0
++ lfsx bfe0000000000001, 48 => 36a0000000000000, 0
++ lfsx bfe00094e0000359, 56 => c400006b20000000, 0
++ lfsx 0000000000000000, 64 => 0000000000000000, 0
++ lfsx 8000000000000000, 72 => 0000000000000000, 0
++ lfsx 7ff0000000000000, 80 => 0000000000000000, 0
++ lfsx fff0000000000000, 88 => 0000000000000000, 0
++ lfsx 7ff7ffffffffffff, 96 => ffffffffe0000000, 0
++ lfsx fff7ffffffffffff, 104 => ffffffffe0000000, 0
++ lfsx 7ff8000000000000, 112 => 0000000000000000, 0
++ lfsx fff8000000000000, 120 => 0000000000000000, 0
++
++ lfsux 0010000000000001, -120 => 36a0000000000000, -120
++ lfsux 00100094e0000359, -112 => c400006b20000000, -112
++ lfsux 3fe0000000000001, -104 => 36a0000000000000, -104
++ lfsux 3fe00094e0000359, -96 => c400006b20000000, -96
++ lfsux 8010000000000001, -88 => 36a0000000000000, -88
++ lfsux 80100094e0000359, -80 => c400006b20000000, -80
++ lfsux bfe0000000000001, -72 => 36a0000000000000, -72
++ lfsux bfe00094e0000359, -64 => c400006b20000000, -64
++ lfsux 0000000000000000, -56 => 0000000000000000, -56
++ lfsux 8000000000000000, -48 => 0000000000000000, -48
++ lfsux 7ff0000000000000, -40 => 0000000000000000, -40
++ lfsux fff0000000000000, -32 => 0000000000000000, -32
++ lfsux 7ff7ffffffffffff, -24 => ffffffffe0000000, -24
++ lfsux fff7ffffffffffff, -16 => ffffffffe0000000, -16
++ lfsux 7ff8000000000000, -8 => 0000000000000000, -8
++ lfsux 0010000000000001, 0 => 36a0000000000000, 0
++ lfsux 00100094e0000359, 8 => c400006b20000000, 8
++ lfsux 3fe0000000000001, 16 => 36a0000000000000, 16
++ lfsux 3fe00094e0000359, 24 => c400006b20000000, 24
++ lfsux 8010000000000001, 32 => 36a0000000000000, 32
++ lfsux 80100094e0000359, 40 => c400006b20000000, 40
++ lfsux bfe0000000000001, 48 => 36a0000000000000, 48
++ lfsux bfe00094e0000359, 56 => c400006b20000000, 56
++ lfsux 0000000000000000, 64 => 0000000000000000, 64
++ lfsux 8000000000000000, 72 => 0000000000000000, 72
++ lfsux 7ff0000000000000, 80 => 0000000000000000, 80
++ lfsux fff0000000000000, 88 => 0000000000000000, 88
++ lfsux 7ff7ffffffffffff, 96 => ffffffffe0000000, 96
++ lfsux fff7ffffffffffff, 104 => ffffffffe0000000, 104
++ lfsux 7ff8000000000000, 112 => 0000000000000000, 112
++ lfsux fff8000000000000, 120 => 0000000000000000, 120
++
++ lfdx 0010000000000001, -120 => 0010000000000001, 0
++ lfdx 00100094e0000359, -112 => 00100094e0000359, 0
++ lfdx 3fe0000000000001, -104 => 3fe0000000000001, 0
++ lfdx 3fe00094e0000359, -96 => 3fe00094e0000359, 0
++ lfdx 8010000000000001, -88 => 8010000000000001, 0
++ lfdx 80100094e0000359, -80 => 80100094e0000359, 0
++ lfdx bfe0000000000001, -72 => bfe0000000000001, 0
++ lfdx bfe00094e0000359, -64 => bfe00094e0000359, 0
++ lfdx 0000000000000000, -56 => 0000000000000000, 0
++ lfdx 8000000000000000, -48 => 8000000000000000, 0
++ lfdx 7ff0000000000000, -40 => 7ff0000000000000, 0
++ lfdx fff0000000000000, -32 => fff0000000000000, 0
++ lfdx 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, 0
++ lfdx fff7ffffffffffff, -16 => fff7ffffffffffff, 0
++ lfdx 7ff8000000000000, -8 => 7ff8000000000000, 0
++ lfdx 0010000000000001, 0 => 0010000000000001, 0
++ lfdx 00100094e0000359, 8 => 00100094e0000359, 0
++ lfdx 3fe0000000000001, 16 => 3fe0000000000001, 0
++ lfdx 3fe00094e0000359, 24 => 3fe00094e0000359, 0
++ lfdx 8010000000000001, 32 => 8010000000000001, 0
++ lfdx 80100094e0000359, 40 => 80100094e0000359, 0
++ lfdx bfe0000000000001, 48 => bfe0000000000001, 0
++ lfdx bfe00094e0000359, 56 => bfe00094e0000359, 0
++ lfdx 0000000000000000, 64 => 0000000000000000, 0
++ lfdx 8000000000000000, 72 => 8000000000000000, 0
++ lfdx 7ff0000000000000, 80 => 7ff0000000000000, 0
++ lfdx fff0000000000000, 88 => fff0000000000000, 0
++ lfdx 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0
++ lfdx fff7ffffffffffff, 104 => fff7ffffffffffff, 0
++ lfdx 7ff8000000000000, 112 => 7ff8000000000000, 0
++ lfdx fff8000000000000, 120 => fff8000000000000, 0
++
++ lfdux 0010000000000001, -120 => 0010000000000001, -120
++ lfdux 00100094e0000359, -112 => 00100094e0000359, -112
++ lfdux 3fe0000000000001, -104 => 3fe0000000000001, -104
++ lfdux 3fe00094e0000359, -96 => 3fe00094e0000359, -96
++ lfdux 8010000000000001, -88 => 8010000000000001, -88
++ lfdux 80100094e0000359, -80 => 80100094e0000359, -80
++ lfdux bfe0000000000001, -72 => bfe0000000000001, -72
++ lfdux bfe00094e0000359, -64 => bfe00094e0000359, -64
++ lfdux 0000000000000000, -56 => 0000000000000000, -56
++ lfdux 8000000000000000, -48 => 8000000000000000, -48
++ lfdux 7ff0000000000000, -40 => 7ff0000000000000, -40
++ lfdux fff0000000000000, -32 => fff0000000000000, -32
++ lfdux 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, -24
++ lfdux fff7ffffffffffff, -16 => fff7ffffffffffff, -16
++ lfdux 7ff8000000000000, -8 => 7ff8000000000000, -8
++ lfdux 0010000000000001, 0 => 0010000000000001, 0
++ lfdux 00100094e0000359, 8 => 00100094e0000359, 8
++ lfdux 3fe0000000000001, 16 => 3fe0000000000001, 16
++ lfdux 3fe00094e0000359, 24 => 3fe00094e0000359, 24
++ lfdux 8010000000000001, 32 => 8010000000000001, 32
++ lfdux 80100094e0000359, 40 => 80100094e0000359, 40
++ lfdux bfe0000000000001, 48 => bfe0000000000001, 48
++ lfdux bfe00094e0000359, 56 => bfe00094e0000359, 56
++ lfdux 0000000000000000, 64 => 0000000000000000, 64
++ lfdux 8000000000000000, 72 => 8000000000000000, 72
++ lfdux 7ff0000000000000, 80 => 7ff0000000000000, 80
++ lfdux fff0000000000000, 88 => fff0000000000000, 88
++ lfdux 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96
++ lfdux fff7ffffffffffff, 104 => fff7ffffffffffff, 104
++ lfdux 7ff8000000000000, 112 => 7ff8000000000000, 112
++ lfdux fff8000000000000, 120 => fff8000000000000, 120
++
++PPC float store insns
++ with one register + one 16 bits immediate args with flags update:
++ stfs 0010000000000001, -56 => 0000000000000000, 0
++ stfs 00100094e0000359, -48 => 0000000000000000, 0
++ stfs 3fe0000000000001, -40 => 000000003f000000, 0
++ stfs 3fe00094e0000359, -32 => 000000003f0004a7, 0
++ stfs 8010000000000001, -24 => 0000000080000000, 0
++ stfs 80100094e0000359, -16 => 0000000080000000, 0
++ stfs bfe0000000000001, -8 => 00000000bf000000, 0
++ stfs 0010000000000001, 0 => 0000000000000000, 0
++ stfs 00100094e0000359, 8 => 0000000000000000, 0
++ stfs 3fe0000000000001, 16 => 000000003f000000, 0
++ stfs 3fe00094e0000359, 24 => 000000003f0004a7, 0
++ stfs 8010000000000001, 32 => 0000000080000000, 0
++ stfs 80100094e0000359, 40 => 0000000080000000, 0
++ stfs bfe0000000000001, 48 => 00000000bf000000, 0
++ stfs bfe00094e0000359, 56 => 00000000bf0004a7, 0
++
++ stfsu 0010000000000001, -56 => 0000000000000000, -56
++ stfsu 00100094e0000359, -48 => 0000000000000000, -48
++ stfsu 3fe0000000000001, -40 => 000000003f000000, -40
++ stfsu 3fe00094e0000359, -32 => 000000003f0004a7, -32
++ stfsu 8010000000000001, -24 => 0000000080000000, -24
++ stfsu 80100094e0000359, -16 => 0000000080000000, -16
++ stfsu bfe0000000000001, -8 => 00000000bf000000, -8
++ stfsu 0010000000000001, 0 => 0000000000000000, 0
++ stfsu 00100094e0000359, 8 => 0000000000000000, 8
++ stfsu 3fe0000000000001, 16 => 000000003f000000, 16
++ stfsu 3fe00094e0000359, 24 => 000000003f0004a7, 24
++ stfsu 8010000000000001, 32 => 0000000080000000, 32
++ stfsu 80100094e0000359, 40 => 0000000080000000, 40
++ stfsu bfe0000000000001, 48 => 00000000bf000000, 48
++ stfsu bfe00094e0000359, 56 => 00000000bf0004a7, 56
++
++ stfd 0010000000000001, -120 => 0010000000000001, 0
++ stfd 00100094e0000359, -112 => 00100094e0000359, 0
++ stfd 3fe0000000000001, -104 => 3fe0000000000001, 0
++ stfd 3fe00094e0000359, -96 => 3fe00094e0000359, 0
++ stfd 8010000000000001, -88 => 8010000000000001, 0
++ stfd 80100094e0000359, -80 => 80100094e0000359, 0
++ stfd bfe0000000000001, -72 => bfe0000000000001, 0
++ stfd bfe00094e0000359, -64 => bfe00094e0000359, 0
++ stfd 0000000000000000, -56 => 0000000000000000, 0
++ stfd 8000000000000000, -48 => 8000000000000000, 0
++ stfd 7ff0000000000000, -40 => 7ff0000000000000, 0
++ stfd fff0000000000000, -32 => fff0000000000000, 0
++ stfd 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, 0
++ stfd fff7ffffffffffff, -16 => fff7ffffffffffff, 0
++ stfd 7ff8000000000000, -8 => 7ff8000000000000, 0
++ stfd 0010000000000001, 0 => 0010000000000001, 0
++ stfd 00100094e0000359, 8 => 00100094e0000359, 0
++ stfd 3fe0000000000001, 16 => 3fe0000000000001, 0
++ stfd 3fe00094e0000359, 24 => 3fe00094e0000359, 0
++ stfd 8010000000000001, 32 => 8010000000000001, 0
++ stfd 80100094e0000359, 40 => 80100094e0000359, 0
++ stfd bfe0000000000001, 48 => bfe0000000000001, 0
++ stfd bfe00094e0000359, 56 => bfe00094e0000359, 0
++ stfd 0000000000000000, 64 => 0000000000000000, 0
++ stfd 8000000000000000, 72 => 8000000000000000, 0
++ stfd 7ff0000000000000, 80 => 7ff0000000000000, 0
++ stfd fff0000000000000, 88 => fff0000000000000, 0
++ stfd 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0
++ stfd fff7ffffffffffff, 104 => fff7ffffffffffff, 0
++ stfd 7ff8000000000000, 112 => 7ff8000000000000, 0
++ stfd fff8000000000000, 120 => fff8000000000000, 0
++
++ stfdu 0010000000000001, -120 => 0010000000000001, -120
++ stfdu 00100094e0000359, -112 => 00100094e0000359, -112
++ stfdu 3fe0000000000001, -104 => 3fe0000000000001, -104
++ stfdu 3fe00094e0000359, -96 => 3fe00094e0000359, -96
++ stfdu 8010000000000001, -88 => 8010000000000001, -88
++ stfdu 80100094e0000359, -80 => 80100094e0000359, -80
++ stfdu bfe0000000000001, -72 => bfe0000000000001, -72
++ stfdu bfe00094e0000359, -64 => bfe00094e0000359, -64
++ stfdu 0000000000000000, -56 => 0000000000000000, -56
++ stfdu 8000000000000000, -48 => 8000000000000000, -48
++ stfdu 7ff0000000000000, -40 => 7ff0000000000000, -40
++ stfdu fff0000000000000, -32 => fff0000000000000, -32
++ stfdu 7ff7ffffffffffff, -24 => 7ff7ffffffffffff, -24
++ stfdu fff7ffffffffffff, -16 => fff7ffffffffffff, -16
++ stfdu 7ff8000000000000, -8 => 7ff8000000000000, -8
++ stfdu 0010000000000001, 0 => 0010000000000001, 0
++ stfdu 00100094e0000359, 8 => 00100094e0000359, 8
++ stfdu 3fe0000000000001, 16 => 3fe0000000000001, 16
++ stfdu 3fe00094e0000359, 24 => 3fe00094e0000359, 24
++ stfdu 8010000000000001, 32 => 8010000000000001, 32
++ stfdu 80100094e0000359, 40 => 80100094e0000359, 40
++ stfdu bfe0000000000001, 48 => bfe0000000000001, 48
++ stfdu bfe00094e0000359, 56 => bfe00094e0000359, 56
++ stfdu 0000000000000000, 64 => 0000000000000000, 64
++ stfdu 8000000000000000, 72 => 8000000000000000, 72
++ stfdu 7ff0000000000000, 80 => 7ff0000000000000, 80
++ stfdu fff0000000000000, 88 => fff0000000000000, 88
++ stfdu 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96
++ stfdu fff7ffffffffffff, 104 => fff7ffffffffffff, 104
++ stfdu 7ff8000000000000, 112 => 7ff8000000000000, 112
++ stfdu fff8000000000000, 120 => fff8000000000000, 120
++
++PPC float store insns with three register args:
++ stfsx 0010000000000001, 0 => 0000000000000000, 0
++ stfsx 00100094e0000359, 8 => 0000000000000000, 0
++ stfsx 3fe0000000000001, 16 => 000000003f000000, 0
++ stfsx 3fe00094e0000359, 24 => 000000003f0004a7, 0
++ stfsx 8010000000000001, 32 => 0000000080000000, 0
++ stfsx 80100094e0000359, 40 => 0000000080000000, 0
++ stfsx bfe0000000000001, 48 => 00000000bf000000, 0
++ stfsx bfe00094e0000359, 56 => 00000000bf0004a7, 0
++
++ stfsux 0010000000000001, 0 => 0000000000000000, 0
++ stfsux 00100094e0000359, 8 => 0000000000000000, 8
++ stfsux 3fe0000000000001, 16 => 000000003f000000, 16
++ stfsux 3fe00094e0000359, 24 => 000000003f0004a7, 24
++ stfsux 8010000000000001, 32 => 0000000080000000, 32
++ stfsux 80100094e0000359, 40 => 0000000080000000, 40
++ stfsux bfe0000000000001, 48 => 00000000bf000000, 48
++ stfsux bfe00094e0000359, 56 => 00000000bf0004a7, 56
++
++ stfdx 0010000000000001, 0 => 0010000000000001, 0
++ stfdx 00100094e0000359, 8 => 00100094e0000359, 0
++ stfdx 3fe0000000000001, 16 => 3fe0000000000001, 0
++ stfdx 3fe00094e0000359, 24 => 3fe00094e0000359, 0
++ stfdx 8010000000000001, 32 => 8010000000000001, 0
++ stfdx 80100094e0000359, 40 => 80100094e0000359, 0
++ stfdx bfe0000000000001, 48 => bfe0000000000001, 0
++ stfdx bfe00094e0000359, 56 => bfe00094e0000359, 0
++ stfdx 0000000000000000, 64 => 0000000000000000, 0
++ stfdx 8000000000000000, 72 => 8000000000000000, 0
++ stfdx 7ff0000000000000, 80 => 7ff0000000000000, 0
++ stfdx fff0000000000000, 88 => fff0000000000000, 0
++ stfdx 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 0
++ stfdx fff7ffffffffffff, 104 => fff7ffffffffffff, 0
++ stfdx 7ff8000000000000, 112 => 7ff8000000000000, 0
++ stfdx fff8000000000000, 120 => fff8000000000000, 0
++
++ stfdux 0010000000000001, 0 => 0010000000000001, 0
++ stfdux 00100094e0000359, 8 => 00100094e0000359, 8
++ stfdux 3fe0000000000001, 16 => 3fe0000000000001, 16
++ stfdux 3fe00094e0000359, 24 => 3fe00094e0000359, 24
++ stfdux 8010000000000001, 32 => 8010000000000001, 32
++ stfdux 80100094e0000359, 40 => 80100094e0000359, 40
++ stfdux bfe0000000000001, 48 => bfe0000000000001, 48
++ stfdux bfe00094e0000359, 56 => bfe00094e0000359, 56
++ stfdux 0000000000000000, 64 => 0000000000000000, 64
++ stfdux 8000000000000000, 72 => 8000000000000000, 72
++ stfdux 7ff0000000000000, 80 => 7ff0000000000000, 80
++ stfdux fff0000000000000, 88 => fff0000000000000, 88
++ stfdux 7ff7ffffffffffff, 96 => 7ff7ffffffffffff, 96
++ stfdux fff7ffffffffffff, 104 => fff7ffffffffffff, 104
++ stfdux 7ff8000000000000, 112 => 7ff8000000000000, 112
++ stfdux fff8000000000000, 120 => fff8000000000000, 120
++
++All done. Tested 77 different instructions
+diff --git a/none/tests/ppc64/jm-int.stdout.exp b/none/tests/ppc64/jm-int.stdout.exp
+index e2b5418..060f2ae 100644
+--- a/none/tests/ppc64/jm-int.stdout.exp
++++ b/none/tests/ppc64/jm-int.stdout.exp
+@@ -4549,81 +4549,81 @@ PPC logical insns with special forms with flags update:
+ PPC integer load insns
+ with one register + one 16 bits immediate args with flags update:
+ lbz 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+- lbz 8, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
+- lbz 16, (ffffffffffffffff) => 00000000000000ff, 0 (00000000 00000000)
+- lbz -16, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+- lbz -8, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
+- lbz 0, (ffffffffffffffff) => 00000000000000ff, 0 (00000000 00000000)
++ lbz 7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
++ lbz 15, (ffffffffffffffff) => 00000000000000ef, 0 (00000000 00000000)
++ lbz 1, (00000000ffffffff) => 00000000000000ff, 0 (00000000 00000000)
++ lbz -7, (00000000be991def) => 0000000000000000, 0 (00000000 00000000)
++ lbz -15, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+
+ lbzu 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+- lbzu 8, (0000001cbe991def) => 0000000000000000, 8 (00000000 00000000)
+- lbzu 16, (ffffffffffffffff) => 00000000000000ff, 16 (00000000 00000000)
+- lbzu -16, (0000000000000000) => 0000000000000000, -16 (00000000 00000000)
+- lbzu -8, (0000001cbe991def) => 0000000000000000, -8 (00000000 00000000)
+- lbzu 0, (ffffffffffffffff) => 00000000000000ff, 0 (00000000 00000000)
++ lbzu 7, (0000001cbe991def) => 0000000000000000, 7 (00000000 00000000)
++ lbzu 15, (ffffffffffffffff) => 00000000000000ef, 15 (00000000 00000000)
++ lbzu 1, (00000000ffffffff) => 00000000000000ff, 1 (00000000 00000000)
++ lbzu -7, (00000000be991def) => 0000000000000000, -7 (00000000 00000000)
++ lbzu -15, (0000000000000000) => 0000000000000000, -15 (00000000 00000000)
+
+ lha 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+- lha 8, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
+- lha 16, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
+- lha -16, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+- lha -8, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
+- lha 0, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
++ lha 7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
++ lha 15, (ffffffffffffffff) => ffffffffffffefff, 0 (00000000 00000000)
++ lha 1, (00000000ffffffff) => ffffffffffffffff, 0 (00000000 00000000)
++ lha -7, (00000000be991def) => 0000000000000000, 0 (00000000 00000000)
++ lha -15, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+
+ lhau 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+- lhau 8, (0000001cbe991def) => 0000000000000000, 8 (00000000 00000000)
+- lhau 16, (ffffffffffffffff) => ffffffffffffffff, 16 (00000000 00000000)
+- lhau -16, (0000000000000000) => 0000000000000000, -16 (00000000 00000000)
+- lhau -8, (0000001cbe991def) => 0000000000000000, -8 (00000000 00000000)
+- lhau 0, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
++ lhau 7, (0000001cbe991def) => 0000000000000000, 7 (00000000 00000000)
++ lhau 15, (ffffffffffffffff) => ffffffffffffefff, 15 (00000000 00000000)
++ lhau 1, (00000000ffffffff) => ffffffffffffffff, 1 (00000000 00000000)
++ lhau -7, (00000000be991def) => 0000000000000000, -7 (00000000 00000000)
++ lhau -15, (0000000000000000) => 0000000000000000, -15 (00000000 00000000)
+
+ lhz 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+- lhz 8, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
+- lhz 16, (ffffffffffffffff) => 000000000000ffff, 0 (00000000 00000000)
+- lhz -16, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+- lhz -8, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
+- lhz 0, (ffffffffffffffff) => 000000000000ffff, 0 (00000000 00000000)
++ lhz 7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
++ lhz 15, (ffffffffffffffff) => 000000000000efff, 0 (00000000 00000000)
++ lhz 1, (00000000ffffffff) => 000000000000ffff, 0 (00000000 00000000)
++ lhz -7, (00000000be991def) => 0000000000000000, 0 (00000000 00000000)
++ lhz -15, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+
+ lhzu 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+- lhzu 8, (0000001cbe991def) => 0000000000000000, 8 (00000000 00000000)
+- lhzu 16, (ffffffffffffffff) => 000000000000ffff, 16 (00000000 00000000)
+- lhzu -16, (0000000000000000) => 0000000000000000, -16 (00000000 00000000)
+- lhzu -8, (0000001cbe991def) => 0000000000000000, -8 (00000000 00000000)
+- lhzu 0, (ffffffffffffffff) => 000000000000ffff, 0 (00000000 00000000)
++ lhzu 7, (0000001cbe991def) => 0000000000000000, 7 (00000000 00000000)
++ lhzu 15, (ffffffffffffffff) => 000000000000efff, 15 (00000000 00000000)
++ lhzu 1, (00000000ffffffff) => 000000000000ffff, 1 (00000000 00000000)
++ lhzu -7, (00000000be991def) => 0000000000000000, -7 (00000000 00000000)
++ lhzu -15, (0000000000000000) => 0000000000000000, -15 (00000000 00000000)
+
+ lwz 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+- lwz 8, (0000001cbe991def) => 000000000000001c, 0 (00000000 00000000)
+- lwz 16, (ffffffffffffffff) => 00000000ffffffff, 0 (00000000 00000000)
+- lwz -16, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+- lwz -8, (0000001cbe991def) => 000000000000001c, 0 (00000000 00000000)
+- lwz 0, (ffffffffffffffff) => 00000000ffffffff, 0 (00000000 00000000)
++ lwz 7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
++ lwz 15, (ffffffffffffffff) => 00000000efffffff, 0 (00000000 00000000)
++ lwz 1, (00000000ffffffff) => 00000000ffffffff, 0 (00000000 00000000)
++ lwz -7, (00000000be991def) => 0000000000001cbe, 0 (00000000 00000000)
++ lwz -15, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+
+ lwzu 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+- lwzu 8, (0000001cbe991def) => 000000000000001c, 8 (00000000 00000000)
+- lwzu 16, (ffffffffffffffff) => 00000000ffffffff, 16 (00000000 00000000)
+- lwzu -16, (0000000000000000) => 0000000000000000, -16 (00000000 00000000)
+- lwzu -8, (0000001cbe991def) => 000000000000001c, -8 (00000000 00000000)
+- lwzu 0, (ffffffffffffffff) => 00000000ffffffff, 0 (00000000 00000000)
++ lwzu 7, (0000001cbe991def) => 0000000000000000, 7 (00000000 00000000)
++ lwzu 15, (ffffffffffffffff) => 00000000efffffff, 15 (00000000 00000000)
++ lwzu 1, (00000000ffffffff) => 00000000ffffffff, 1 (00000000 00000000)
++ lwzu -7, (00000000be991def) => 0000000000001cbe, -7 (00000000 00000000)
++ lwzu -15, (0000000000000000) => 0000000000000000, -15 (00000000 00000000)
+
+ ld 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+- ld 8, (0000001cbe991def) => 0000001cbe991def, 0 (00000000 00000000)
+- ld 16, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
+- ld -16, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+- ld -8, (0000001cbe991def) => 0000001cbe991def, 0 (00000000 00000000)
+- ld 0, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
++ ld 7, (0000001cbe991def) => 000000000000001c, 0 (00000000 00000000)
++ ld 15, (ffffffffffffffff) => be991defffffffff, 0 (00000000 00000000)
++ ld 1, (00000000ffffffff) => ffffffffffffffff, 0 (00000000 00000000)
++ ld -7, (00000000be991def) => 0000001cbe991def, -8 (00000000 00000000)
++ ld -15, (0000000000000000) => 0000000000000000, -16 (00000000 00000000)
+
+ ldu 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+- ldu 8, (0000001cbe991def) => 0000001cbe991def, 0 (00000000 00000000)
+- ldu 16, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
+- ldu -16, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+- ldu -8, (0000001cbe991def) => 0000001cbe991def, 0 (00000000 00000000)
+- ldu 0, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
++ ldu 7, (0000001cbe991def) => 000000000000001c, 4 (00000000 00000000)
++ ldu 15, (ffffffffffffffff) => be991defffffffff, 12 (00000000 00000000)
++ ldu 1, (00000000ffffffff) => ffffffffffffffff, 0 (00000000 00000000)
++ ldu -7, (00000000be991def) => 0000001cbe991def, -8 (00000000 00000000)
++ ldu -15, (0000000000000000) => 0000000000000000, -16 (00000000 00000000)
+
+ lwa 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+- lwa 8, (0000001cbe991def) => 000000000000001c, 0 (00000000 00000000)
+- lwa 16, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
+- lwa -16, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+- lwa -8, (0000001cbe991def) => 0000001cbe991def, 0 (00000000 00000000)
+- lwa 0, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
++ lwa 7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
++ lwa 15, (ffffffffffffffff) => ffffffffbe991def, 0 (00000000 00000000)
++ lwa 1, (00000000ffffffff) => ffffffffffffffff, 0 (00000000 00000000)
++ lwa -7, (00000000be991def) => 0000001cbe991def, -8 (00000000 00000000)
++ lwa -15, (0000000000000000) => 0000000000000000, -16 (00000000 00000000)
+
+ PPC integer load insns with two register args:
+ lbzx 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
+diff --git a/none/tests/ppc64/jm-int.stdout.exp-LE b/none/tests/ppc64/jm-int.stdout.exp-LE
+new file mode 100644
+index 0000000..d5f9625
+--- /dev/null
++++ b/none/tests/ppc64/jm-int.stdout.exp-LE
+@@ -0,0 +1,4773 @@
++PPC integer arith insns with two args:
++ add 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ add 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
++ add 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
++ add 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
++ add 0000001cbe991def, 0000001cbe991def => 000000397d323bde (00000000 00000000)
++ add 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (00000000 00000000)
++ add ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
++ add ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (00000000 00000000)
++ add ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (00000000 00000000)
++
++ addo 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ addo 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
++ addo 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
++ addo 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
++ addo 0000001cbe991def, 0000001cbe991def => 000000397d323bde (00000000 00000000)
++ addo 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (00000000 00000000)
++ addo ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
++ addo ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (00000000 00000000)
++ addo ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (00000000 00000000)
++
++ addc 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ addc 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
++ addc 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
++ addc 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
++ addc 0000001cbe991def, 0000001cbe991def => 000000397d323bde (00000000 00000000)
++ addc 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (00000000 20000000)
++ addc ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
++ addc ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (00000000 20000000)
++ addc ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (00000000 20000000)
++
++ addco 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ addco 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
++ addco 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
++ addco 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
++ addco 0000001cbe991def, 0000001cbe991def => 000000397d323bde (00000000 00000000)
++ addco 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (00000000 20000000)
++ addco ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
++ addco ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (00000000 20000000)
++ addco ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (00000000 20000000)
++
++ divw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ divw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++ divw 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000)
++ divw 0000001cbe991def, ffffffffffffffff => 000000004166e211 (00000000 00000000)
++ divw ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ divw ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
++
++ divwo 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ divwo 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++ divwo 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000)
++ divwo 0000001cbe991def, ffffffffffffffff => 000000004166e211 (00000000 00000000)
++ divwo ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ divwo ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
++
++ divwu 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ divwu 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++ divwu 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000)
++ divwu 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++ divwu ffffffffffffffff, 0000001cbe991def => 0000000000000001 (00000000 00000000)
++ divwu ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
++
++ divwuo 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ divwuo 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++ divwuo 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000)
++ divwuo 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++ divwuo ffffffffffffffff, 0000001cbe991def => 0000000000000001 (00000000 00000000)
++ divwuo ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
++
++ mulhw 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ mulhw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ mulhw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++ mulhw 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ mulhw 0000001cbe991def, 0000001cbe991def => 0000000010b56825 (00000000 00000000)
++ mulhw 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++ mulhw ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ mulhw ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ mulhw ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++
++ mulhwu 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ mulhwu 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ mulhwu 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++ mulhwu 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ mulhwu 0000001cbe991def, 0000001cbe991def => 000000008de7a403 (00000000 00000000)
++ mulhwu 0000001cbe991def, ffffffffffffffff => 00000000be991dee (00000000 00000000)
++ mulhwu ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ mulhwu ffffffffffffffff, 0000001cbe991def => 00000000be991dee (00000000 00000000)
++ mulhwu ffffffffffffffff, ffffffffffffffff => 00000000fffffffe (00000000 00000000)
++
++ mullw 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ mullw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ mullw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++ mullw 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ mullw 0000001cbe991def, 0000001cbe991def => 10b568258f2e0521 (00000000 00000000)
++ mullw 0000001cbe991def, ffffffffffffffff => 000000004166e211 (00000000 00000000)
++ mullw ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ mullw ffffffffffffffff, 0000001cbe991def => 000000004166e211 (00000000 00000000)
++ mullw ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
++
++ mullwo 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ mullwo 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ mullwo 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++ mullwo 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ mullwo 0000001cbe991def, 0000001cbe991def => 10b568258f2e0521 (00000000 c0000000)
++ mullwo 0000001cbe991def, ffffffffffffffff => 000000004166e211 (00000000 00000000)
++ mullwo ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ mullwo ffffffffffffffff, 0000001cbe991def => 000000004166e211 (00000000 00000000)
++ mullwo ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
++
++ subf 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ subf 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
++ subf 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
++ subf 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (00000000 00000000)
++ subf 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ subf 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000 00000000)
++ subf ffffffffffffffff, 0000000000000000 => 0000000000000001 (00000000 00000000)
++ subf ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (00000000 00000000)
++ subf ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++
++ subfo 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ subfo 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
++ subfo 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
++ subfo 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (00000000 00000000)
++ subfo 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ subfo 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000 00000000)
++ subfo ffffffffffffffff, 0000000000000000 => 0000000000000001 (00000000 00000000)
++ subfo ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (00000000 00000000)
++ subfo ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++
++ subfc 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 20000000)
++ subfc 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 20000000)
++ subfc 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 20000000)
++ subfc 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (00000000 00000000)
++ subfc 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 20000000)
++ subfc 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000 20000000)
++ subfc ffffffffffffffff, 0000000000000000 => 0000000000000001 (00000000 00000000)
++ subfc ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (00000000 00000000)
++ subfc ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 20000000)
++
++ subfco 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 20000000)
++ subfco 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 20000000)
++ subfco 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 20000000)
++ subfco 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (00000000 00000000)
++ subfco 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 20000000)
++ subfco 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000 20000000)
++ subfco ffffffffffffffff, 0000000000000000 => 0000000000000001 (00000000 00000000)
++ subfco ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (00000000 00000000)
++ subfco ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 20000000)
++
++ mulhd 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ mulhd 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ mulhd 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++ mulhd 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ mulhd 0000001cbe991def, 0000001cbe991def => 000000000000033a (00000000 00000000)
++ mulhd 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
++ mulhd ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ mulhd ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 00000000)
++ mulhd ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++
++ mulhdu 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ mulhdu 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ mulhdu 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++ mulhdu 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ mulhdu 0000001cbe991def, 0000001cbe991def => 000000000000033a (00000000 00000000)
++ mulhdu 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (00000000 00000000)
++ mulhdu ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ mulhdu ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (00000000 00000000)
++ mulhdu ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (00000000 00000000)
++
++ mulld 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ mulld 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ mulld 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++ mulld 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ mulld 0000001cbe991def, 0000001cbe991def => 3f66304b8f2e0521 (00000000 00000000)
++ mulld 0000001cbe991def, ffffffffffffffff => ffffffe34166e211 (00000000 00000000)
++ mulld ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ mulld ffffffffffffffff, 0000001cbe991def => ffffffe34166e211 (00000000 00000000)
++ mulld ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
++
++ mulldo 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ mulldo 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ mulldo 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++ mulldo 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ mulldo 0000001cbe991def, 0000001cbe991def => 3f66304b8f2e0521 (00000000 c0000000)
++ mulldo 0000001cbe991def, ffffffffffffffff => ffffffe34166e211 (00000000 00000000)
++ mulldo ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ mulldo ffffffffffffffff, 0000001cbe991def => ffffffe34166e211 (00000000 00000000)
++ mulldo ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
++
++ divd 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ divd 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ divd 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++ divd 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ divd 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000)
++ divd 0000001cbe991def, ffffffffffffffff => ffffffe34166e211 (00000000 00000000)
++ divd ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ divd ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ divd ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
++
++ divdu 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ divdu 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ divdu 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++ divdu 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ divdu 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000)
++ divdu 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++ divdu ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ divdu ffffffffffffffff, 0000001cbe991def => 0000000008e7f283 (00000000 00000000)
++ divdu ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
++
++ divdo 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 c0000000)
++ divdo 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ divdo 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++ divdo 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 c0000000)
++ divdo 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000)
++ divdo 0000001cbe991def, ffffffffffffffff => ffffffe34166e211 (00000000 00000000)
++ divdo ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 c0000000)
++ divdo ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ divdo ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
++
++ divduo 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 c0000000)
++ divduo 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ divduo 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++ divduo 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 c0000000)
++ divduo 0000001cbe991def, 0000001cbe991def => 0000000000000001 (00000000 00000000)
++ divduo 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++ divduo ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 c0000000)
++ divduo ffffffffffffffff, 0000001cbe991def => 0000000008e7f283 (00000000 00000000)
++ divduo ffffffffffffffff, ffffffffffffffff => 0000000000000001 (00000000 00000000)
++
++PPC integer arith insns with two args with flags update:
++ add. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ add. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
++ add. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
++ add. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
++ add. 0000001cbe991def, 0000001cbe991def => 000000397d323bde (40000000 00000000)
++ add. 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (40000000 00000000)
++ add. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
++ add. ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (40000000 00000000)
++ add. ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (80000000 00000000)
++
++ addo. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ addo. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
++ addo. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
++ addo. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
++ addo. 0000001cbe991def, 0000001cbe991def => 000000397d323bde (40000000 00000000)
++ addo. 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (40000000 00000000)
++ addo. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
++ addo. ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (40000000 00000000)
++ addo. ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (80000000 00000000)
++
++ addc. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ addc. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
++ addc. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
++ addc. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
++ addc. 0000001cbe991def, 0000001cbe991def => 000000397d323bde (40000000 00000000)
++ addc. 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (40000000 20000000)
++ addc. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
++ addc. ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (40000000 20000000)
++ addc. ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (80000000 20000000)
++
++ addco. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ addco. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
++ addco. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
++ addco. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
++ addco. 0000001cbe991def, 0000001cbe991def => 000000397d323bde (40000000 00000000)
++ addco. 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (40000000 20000000)
++ addco. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
++ addco. ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (40000000 20000000)
++ addco. ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (80000000 20000000)
++
++ divw. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ divw. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++ divw. 0000001cbe991def, 0000001cbe991def => 0000000000000001 (40000000 00000000)
++ divw. 0000001cbe991def, ffffffffffffffff => 000000004166e211 (40000000 00000000)
++ divw. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ divw. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000)
++
++ divwo. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ divwo. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++ divwo. 0000001cbe991def, 0000001cbe991def => 0000000000000001 (40000000 00000000)
++ divwo. 0000001cbe991def, ffffffffffffffff => 000000004166e211 (40000000 00000000)
++ divwo. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ divwo. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000)
++
++ divwu. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ divwu. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++ divwu. 0000001cbe991def, 0000001cbe991def => 0000000000000001 (40000000 00000000)
++ divwu. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++ divwu. ffffffffffffffff, 0000001cbe991def => 0000000000000001 (40000000 00000000)
++ divwu. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000)
++
++ divwuo. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ divwuo. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++ divwuo. 0000001cbe991def, 0000001cbe991def => 0000000000000001 (40000000 00000000)
++ divwuo. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++ divwuo. ffffffffffffffff, 0000001cbe991def => 0000000000000001 (40000000 00000000)
++ divwuo. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000)
++
++ mulhw. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ mulhw. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ mulhw. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++ mulhw. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ mulhw. 0000001cbe991def, 0000001cbe991def => 0000000010b56825 (40000000 00000000)
++ mulhw. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++ mulhw. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ mulhw. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ mulhw. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++
++ mulhwu. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ mulhwu. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ mulhwu. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++ mulhwu. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ mulhwu. 0000001cbe991def, 0000001cbe991def => 000000008de7a403 (80000000 00000000)
++ mulhwu. 0000001cbe991def, ffffffffffffffff => 00000000be991dee (80000000 00000000)
++ mulhwu. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ mulhwu. ffffffffffffffff, 0000001cbe991def => 00000000be991dee (80000000 00000000)
++ mulhwu. ffffffffffffffff, ffffffffffffffff => 00000000fffffffe (80000000 00000000)
++
++ mullw. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ mullw. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ mullw. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++ mullw. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ mullw. 0000001cbe991def, 0000001cbe991def => 10b568258f2e0521 (40000000 00000000)
++ mullw. 0000001cbe991def, ffffffffffffffff => 000000004166e211 (40000000 00000000)
++ mullw. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ mullw. ffffffffffffffff, 0000001cbe991def => 000000004166e211 (40000000 00000000)
++ mullw. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000)
++
++ mullwo. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ mullwo. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ mullwo. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++ mullwo. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ mullwo. 0000001cbe991def, 0000001cbe991def => 10b568258f2e0521 (50000000 c0000000)
++ mullwo. 0000001cbe991def, ffffffffffffffff => 000000004166e211 (40000000 00000000)
++ mullwo. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ mullwo. ffffffffffffffff, 0000001cbe991def => 000000004166e211 (40000000 00000000)
++ mullwo. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000)
++
++ subf. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ subf. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
++ subf. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
++ subf. 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (80000000 00000000)
++ subf. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ subf. 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (80000000 00000000)
++ subf. ffffffffffffffff, 0000000000000000 => 0000000000000001 (40000000 00000000)
++ subf. ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (40000000 00000000)
++ subf. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++
++ subfo. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ subfo. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
++ subfo. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
++ subfo. 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (80000000 00000000)
++ subfo. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ subfo. 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (80000000 00000000)
++ subfo. ffffffffffffffff, 0000000000000000 => 0000000000000001 (40000000 00000000)
++ subfo. ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (40000000 00000000)
++ subfo. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++
++ subfc. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 20000000)
++ subfc. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 20000000)
++ subfc. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 20000000)
++ subfc. 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (80000000 00000000)
++ subfc. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 20000000)
++ subfc. 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (80000000 20000000)
++ subfc. ffffffffffffffff, 0000000000000000 => 0000000000000001 (40000000 00000000)
++ subfc. ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (40000000 00000000)
++ subfc. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 20000000)
++
++ subfco. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 20000000)
++ subfco. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 20000000)
++ subfco. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 20000000)
++ subfco. 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (80000000 00000000)
++ subfco. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 20000000)
++ subfco. 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (80000000 20000000)
++ subfco. ffffffffffffffff, 0000000000000000 => 0000000000000001 (40000000 00000000)
++ subfco. ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (40000000 00000000)
++ subfco. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 20000000)
++
++ mulhd. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ mulhd. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ mulhd. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++ mulhd. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ mulhd. 0000001cbe991def, 0000001cbe991def => 000000000000033a (40000000 00000000)
++ mulhd. 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
++ mulhd. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ mulhd. ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (80000000 00000000)
++ mulhd. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++
++ mulhdu. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ mulhdu. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ mulhdu. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++ mulhdu. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ mulhdu. 0000001cbe991def, 0000001cbe991def => 000000000000033a (40000000 00000000)
++ mulhdu. 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (40000000 00000000)
++ mulhdu. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ mulhdu. ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (40000000 00000000)
++ mulhdu. ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (80000000 00000000)
++
++ mulld. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ mulld. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ mulld. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++ mulld. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ mulld. 0000001cbe991def, 0000001cbe991def => 3f66304b8f2e0521 (40000000 00000000)
++ mulld. 0000001cbe991def, ffffffffffffffff => ffffffe34166e211 (80000000 00000000)
++ mulld. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ mulld. ffffffffffffffff, 0000001cbe991def => ffffffe34166e211 (80000000 00000000)
++ mulld. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000)
++
++ mulldo. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ mulldo. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ mulldo. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++ mulldo. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ mulldo. 0000001cbe991def, 0000001cbe991def => 3f66304b8f2e0521 (50000000 c0000000)
++ mulldo. 0000001cbe991def, ffffffffffffffff => ffffffe34166e211 (80000000 00000000)
++ mulldo. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ mulldo. ffffffffffffffff, 0000001cbe991def => ffffffe34166e211 (80000000 00000000)
++ mulldo. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000)
++
++ divd. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ divd. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ divd. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++ divd. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ divd. 0000001cbe991def, 0000001cbe991def => 0000000000000001 (40000000 00000000)
++ divd. 0000001cbe991def, ffffffffffffffff => ffffffe34166e211 (80000000 00000000)
++ divd. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ divd. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ divd. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000)
++
++ divdu. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ divdu. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ divdu. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++ divdu. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ divdu. 0000001cbe991def, 0000001cbe991def => 0000000000000001 (40000000 00000000)
++ divdu. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++ divdu. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ divdu. ffffffffffffffff, 0000001cbe991def => 0000000008e7f283 (40000000 00000000)
++ divdu. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000)
++
++ divdo. 0000000000000000, 0000000000000000 => 0000000000000000 (30000000 c0000000)
++ divdo. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ divdo. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++ divdo. 0000001cbe991def, 0000000000000000 => 0000000000000000 (30000000 c0000000)
++ divdo. 0000001cbe991def, 0000001cbe991def => 0000000000000001 (40000000 00000000)
++ divdo. 0000001cbe991def, ffffffffffffffff => ffffffe34166e211 (80000000 00000000)
++ divdo. ffffffffffffffff, 0000000000000000 => 0000000000000000 (30000000 c0000000)
++ divdo. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ divdo. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000)
++
++ divduo. 0000000000000000, 0000000000000000 => 0000000000000000 (30000000 c0000000)
++ divduo. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ divduo. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++ divduo. 0000001cbe991def, 0000000000000000 => 0000000000000000 (30000000 c0000000)
++ divduo. 0000001cbe991def, 0000001cbe991def => 0000000000000001 (40000000 00000000)
++ divduo. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++ divduo. ffffffffffffffff, 0000000000000000 => 0000000000000000 (30000000 c0000000)
++ divduo. ffffffffffffffff, 0000001cbe991def => 0000000008e7f283 (40000000 00000000)
++ divduo. ffffffffffffffff, ffffffffffffffff => 0000000000000001 (40000000 00000000)
++
++PPC integer arith insns with two args and carry:
++ adde 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ adde 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
++ adde 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
++ adde 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
++ adde 0000001cbe991def, 0000001cbe991def => 000000397d323bde (00000000 00000000)
++ adde 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (00000000 20000000)
++ adde ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
++ adde ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (00000000 20000000)
++ adde ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (00000000 20000000)
++ adde 0000000000000000, 0000000000000000 => 0000000000000001 (00000000 00000000)
++ adde 0000000000000000, 0000001cbe991def => 0000001cbe991df0 (00000000 00000000)
++ adde 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 20000000)
++ adde 0000001cbe991def, 0000000000000000 => 0000001cbe991df0 (00000000 00000000)
++ adde 0000001cbe991def, 0000001cbe991def => 000000397d323bdf (00000000 00000000)
++ adde 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (00000000 20000000)
++ adde ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 20000000)
++ adde ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (00000000 20000000)
++ adde ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 20000000)
++
++ addeo 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ addeo 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
++ addeo 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
++ addeo 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
++ addeo 0000001cbe991def, 0000001cbe991def => 000000397d323bde (00000000 00000000)
++ addeo 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (00000000 20000000)
++ addeo ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
++ addeo ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (00000000 20000000)
++ addeo ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (00000000 20000000)
++ addeo 0000000000000000, 0000000000000000 => 0000000000000001 (00000000 00000000)
++ addeo 0000000000000000, 0000001cbe991def => 0000001cbe991df0 (00000000 00000000)
++ addeo 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 20000000)
++ addeo 0000001cbe991def, 0000000000000000 => 0000001cbe991df0 (00000000 00000000)
++ addeo 0000001cbe991def, 0000001cbe991def => 000000397d323bdf (00000000 00000000)
++ addeo 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (00000000 20000000)
++ addeo ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 20000000)
++ addeo ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (00000000 20000000)
++ addeo ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 20000000)
++
++ subfe 0000000000000000, 0000000000000000 => ffffffffffffffff (00000000 00000000)
++ subfe 0000000000000000, 0000001cbe991def => 0000001cbe991dee (00000000 20000000)
++ subfe 0000000000000000, ffffffffffffffff => fffffffffffffffe (00000000 20000000)
++ subfe 0000001cbe991def, 0000000000000000 => ffffffe34166e210 (00000000 00000000)
++ subfe 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (00000000 00000000)
++ subfe 0000001cbe991def, ffffffffffffffff => ffffffe34166e20f (00000000 20000000)
++ subfe ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ subfe ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
++ subfe ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
++ subfe 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 20000000)
++ subfe 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 20000000)
++ subfe 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 20000000)
++ subfe 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (00000000 00000000)
++ subfe 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 20000000)
++ subfe 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000 20000000)
++ subfe ffffffffffffffff, 0000000000000000 => 0000000000000001 (00000000 00000000)
++ subfe ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (00000000 00000000)
++ subfe ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 20000000)
++
++ subfeo 0000000000000000, 0000000000000000 => ffffffffffffffff (00000000 00000000)
++ subfeo 0000000000000000, 0000001cbe991def => 0000001cbe991dee (00000000 20000000)
++ subfeo 0000000000000000, ffffffffffffffff => fffffffffffffffe (00000000 20000000)
++ subfeo 0000001cbe991def, 0000000000000000 => ffffffe34166e210 (00000000 00000000)
++ subfeo 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (00000000 00000000)
++ subfeo 0000001cbe991def, ffffffffffffffff => ffffffe34166e20f (00000000 20000000)
++ subfeo ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ subfeo ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
++ subfeo ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
++ subfeo 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 20000000)
++ subfeo 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 20000000)
++ subfeo 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 20000000)
++ subfeo 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (00000000 00000000)
++ subfeo 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 20000000)
++ subfeo 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000 20000000)
++ subfeo ffffffffffffffff, 0000000000000000 => 0000000000000001 (00000000 00000000)
++ subfeo ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (00000000 00000000)
++ subfeo ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 20000000)
++
++PPC integer arith insns with two args and carry with flags update:
++ adde. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ adde. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
++ adde. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
++ adde. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
++ adde. 0000001cbe991def, 0000001cbe991def => 000000397d323bde (40000000 00000000)
++ adde. 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (40000000 20000000)
++ adde. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
++ adde. ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (40000000 20000000)
++ adde. ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (80000000 20000000)
++ adde. 0000000000000000, 0000000000000000 => 0000000000000001 (40000000 00000000)
++ adde. 0000000000000000, 0000001cbe991def => 0000001cbe991df0 (40000000 00000000)
++ adde. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 20000000)
++ adde. 0000001cbe991def, 0000000000000000 => 0000001cbe991df0 (40000000 00000000)
++ adde. 0000001cbe991def, 0000001cbe991def => 000000397d323bdf (40000000 00000000)
++ adde. 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (40000000 20000000)
++ adde. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 20000000)
++ adde. ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (40000000 20000000)
++ adde. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 20000000)
++
++ addeo. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ addeo. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
++ addeo. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
++ addeo. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
++ addeo. 0000001cbe991def, 0000001cbe991def => 000000397d323bde (40000000 00000000)
++ addeo. 0000001cbe991def, ffffffffffffffff => 0000001cbe991dee (40000000 20000000)
++ addeo. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
++ addeo. ffffffffffffffff, 0000001cbe991def => 0000001cbe991dee (40000000 20000000)
++ addeo. ffffffffffffffff, ffffffffffffffff => fffffffffffffffe (80000000 20000000)
++ addeo. 0000000000000000, 0000000000000000 => 0000000000000001 (40000000 00000000)
++ addeo. 0000000000000000, 0000001cbe991def => 0000001cbe991df0 (40000000 00000000)
++ addeo. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 20000000)
++ addeo. 0000001cbe991def, 0000000000000000 => 0000001cbe991df0 (40000000 00000000)
++ addeo. 0000001cbe991def, 0000001cbe991def => 000000397d323bdf (40000000 00000000)
++ addeo. 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (40000000 20000000)
++ addeo. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 20000000)
++ addeo. ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (40000000 20000000)
++ addeo. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 20000000)
++
++ subfe. 0000000000000000, 0000000000000000 => ffffffffffffffff (80000000 00000000)
++ subfe. 0000000000000000, 0000001cbe991def => 0000001cbe991dee (40000000 20000000)
++ subfe. 0000000000000000, ffffffffffffffff => fffffffffffffffe (80000000 20000000)
++ subfe. 0000001cbe991def, 0000000000000000 => ffffffe34166e210 (80000000 00000000)
++ subfe. 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (80000000 00000000)
++ subfe. 0000001cbe991def, ffffffffffffffff => ffffffe34166e20f (80000000 20000000)
++ subfe. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ subfe. ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
++ subfe. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
++ subfe. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 20000000)
++ subfe. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 20000000)
++ subfe. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 20000000)
++ subfe. 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (80000000 00000000)
++ subfe. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 20000000)
++ subfe. 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (80000000 20000000)
++ subfe. ffffffffffffffff, 0000000000000000 => 0000000000000001 (40000000 00000000)
++ subfe. ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (40000000 00000000)
++ subfe. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 20000000)
++
++ subfeo. 0000000000000000, 0000000000000000 => ffffffffffffffff (80000000 00000000)
++ subfeo. 0000000000000000, 0000001cbe991def => 0000001cbe991dee (40000000 20000000)
++ subfeo. 0000000000000000, ffffffffffffffff => fffffffffffffffe (80000000 20000000)
++ subfeo. 0000001cbe991def, 0000000000000000 => ffffffe34166e210 (80000000 00000000)
++ subfeo. 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (80000000 00000000)
++ subfeo. 0000001cbe991def, ffffffffffffffff => ffffffe34166e20f (80000000 20000000)
++ subfeo. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ subfeo. ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
++ subfeo. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
++ subfeo. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 20000000)
++ subfeo. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 20000000)
++ subfeo. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 20000000)
++ subfeo. 0000001cbe991def, 0000000000000000 => ffffffe34166e211 (80000000 00000000)
++ subfeo. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 20000000)
++ subfeo. 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (80000000 20000000)
++ subfeo. ffffffffffffffff, 0000000000000000 => 0000000000000001 (40000000 00000000)
++ subfeo. ffffffffffffffff, 0000001cbe991def => 0000001cbe991df0 (40000000 00000000)
++ subfeo. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 20000000)
++
++PPC integer logical insns with two args:
++ and 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ and 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ and 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++ and 0000001cbe991def, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ and 0000001cbe991def, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
++ and 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (00000000 00000000)
++ and ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ and ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
++ and ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
++
++ andc 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ andc 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ andc 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++ andc 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
++ andc 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ andc 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++ andc ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
++ andc ffffffffffffffff, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
++ andc ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++
++ eqv 0000000000000000, 0000000000000000 => ffffffffffffffff (00000000 00000000)
++ eqv 0000000000000000, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
++ eqv 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++ eqv 0000001cbe991def, 0000000000000000 => ffffffe34166e210 (00000000 00000000)
++ eqv 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (00000000 00000000)
++ eqv 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (00000000 00000000)
++ eqv ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ eqv ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
++ eqv ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
++
++ nand 0000000000000000, 0000000000000000 => ffffffffffffffff (00000000 00000000)
++ nand 0000000000000000, 0000001cbe991def => ffffffffffffffff (00000000 00000000)
++ nand 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
++ nand 0000001cbe991def, 0000000000000000 => ffffffffffffffff (00000000 00000000)
++ nand 0000001cbe991def, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
++ nand 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000 00000000)
++ nand ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
++ nand ffffffffffffffff, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
++ nand ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++
++ nor 0000000000000000, 0000000000000000 => ffffffffffffffff (00000000 00000000)
++ nor 0000000000000000, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
++ nor 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++ nor 0000001cbe991def, 0000000000000000 => ffffffe34166e210 (00000000 00000000)
++ nor 0000001cbe991def, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
++ nor 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++ nor ffffffffffffffff, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ nor ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ nor ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++
++ or 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ or 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
++ or 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
++ or 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
++ or 0000001cbe991def, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
++ or 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
++ or ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
++ or ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 00000000)
++ or ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
++
++ orc 0000000000000000, 0000000000000000 => ffffffffffffffff (00000000 00000000)
++ orc 0000000000000000, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
++ orc 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++ orc 0000001cbe991def, 0000000000000000 => ffffffffffffffff (00000000 00000000)
++ orc 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (00000000 00000000)
++ orc 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (00000000 00000000)
++ orc ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
++ orc ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 00000000)
++ orc ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
++
++ xor 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ xor 0000000000000000, 0000001cbe991def => 0000001cbe991def (00000000 00000000)
++ xor 0000000000000000, ffffffffffffffff => ffffffffffffffff (00000000 00000000)
++ xor 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
++ xor 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ xor 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (00000000 00000000)
++ xor ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
++ xor ffffffffffffffff, 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
++ xor ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++
++ slw 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ slw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ slw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++ slw 0000001cbe991def, 0000000000000000 => 00000000be991def (00000000 00000000)
++ slw 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ slw 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++ slw ffffffffffffffff, 0000000000000000 => 00000000ffffffff (00000000 00000000)
++ slw ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ slw ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++
++ sraw 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ sraw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ sraw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++ sraw 0000001cbe991def, 0000000000000000 => ffffffffbe991def (00000000 00000000)
++ sraw 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (00000000 20000000)
++ sraw 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (00000000 20000000)
++ sraw ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
++ sraw ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 20000000)
++ sraw ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 20000000)
++
++ srw 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ srw 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ srw 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++ srw 0000001cbe991def, 0000000000000000 => 00000000be991def (00000000 00000000)
++ srw 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ srw 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++ srw ffffffffffffffff, 0000000000000000 => 00000000ffffffff (00000000 00000000)
++ srw ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ srw ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++
++ sld 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ sld 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ sld 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++ sld 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
++ sld 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ sld 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++ sld ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
++ sld ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ sld ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++
++ srad 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ srad 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ srad 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++ srad 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
++ srad 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ srad 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++ srad ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
++ srad ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (00000000 20000000)
++ srad ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (00000000 20000000)
++
++ srd 0000000000000000, 0000000000000000 => 0000000000000000 (00000000 00000000)
++ srd 0000000000000000, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ srd 0000000000000000, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++ srd 0000001cbe991def, 0000000000000000 => 0000001cbe991def (00000000 00000000)
++ srd 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ srd 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++ srd ffffffffffffffff, 0000000000000000 => ffffffffffffffff (00000000 00000000)
++ srd ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ srd ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00000000 00000000)
++
++PPC integer logical insns with two args with flags update:
++ and. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ and. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ and. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++ and. 0000001cbe991def, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ and. 0000001cbe991def, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
++ and. 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (40000000 00000000)
++ and. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ and. ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
++ and. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
++
++ andc. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ andc. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ andc. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++ andc. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
++ andc. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ andc. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++ andc. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
++ andc. ffffffffffffffff, 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
++ andc. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++
++ eqv. 0000000000000000, 0000000000000000 => ffffffffffffffff (80000000 00000000)
++ eqv. 0000000000000000, 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
++ eqv. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++ eqv. 0000001cbe991def, 0000000000000000 => ffffffe34166e210 (80000000 00000000)
++ eqv. 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (80000000 00000000)
++ eqv. 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (40000000 00000000)
++ eqv. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ eqv. ffffffffffffffff, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
++ eqv. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
++
++ nand. 0000000000000000, 0000000000000000 => ffffffffffffffff (80000000 00000000)
++ nand. 0000000000000000, 0000001cbe991def => ffffffffffffffff (80000000 00000000)
++ nand. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
++ nand. 0000001cbe991def, 0000000000000000 => ffffffffffffffff (80000000 00000000)
++ nand. 0000001cbe991def, 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
++ nand. 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (80000000 00000000)
++ nand. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
++ nand. ffffffffffffffff, 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
++ nand. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++
++ nor. 0000000000000000, 0000000000000000 => ffffffffffffffff (80000000 00000000)
++ nor. 0000000000000000, 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
++ nor. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++ nor. 0000001cbe991def, 0000000000000000 => ffffffe34166e210 (80000000 00000000)
++ nor. 0000001cbe991def, 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
++ nor. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++ nor. ffffffffffffffff, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ nor. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ nor. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++
++ or. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ or. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
++ or. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
++ or. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
++ or. 0000001cbe991def, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
++ or. 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
++ or. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
++ or. ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (80000000 00000000)
++ or. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
++
++ orc. 0000000000000000, 0000000000000000 => ffffffffffffffff (80000000 00000000)
++ orc. 0000000000000000, 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
++ orc. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++ orc. 0000001cbe991def, 0000000000000000 => ffffffffffffffff (80000000 00000000)
++ orc. 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (80000000 00000000)
++ orc. 0000001cbe991def, ffffffffffffffff => 0000001cbe991def (40000000 00000000)
++ orc. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
++ orc. ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (80000000 00000000)
++ orc. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
++
++ xor. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ xor. 0000000000000000, 0000001cbe991def => 0000001cbe991def (40000000 00000000)
++ xor. 0000000000000000, ffffffffffffffff => ffffffffffffffff (80000000 00000000)
++ xor. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
++ xor. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ xor. 0000001cbe991def, ffffffffffffffff => ffffffe34166e210 (80000000 00000000)
++ xor. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
++ xor. ffffffffffffffff, 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
++ xor. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++
++ slw. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ slw. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ slw. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++ slw. 0000001cbe991def, 0000000000000000 => 00000000be991def (40000000 00000000)
++ slw. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ slw. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++ slw. ffffffffffffffff, 0000000000000000 => 00000000ffffffff (40000000 00000000)
++ slw. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ slw. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++
++ sraw. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ sraw. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ sraw. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++ sraw. 0000001cbe991def, 0000000000000000 => ffffffffbe991def (80000000 00000000)
++ sraw. 0000001cbe991def, 0000001cbe991def => ffffffffffffffff (80000000 20000000)
++ sraw. 0000001cbe991def, ffffffffffffffff => ffffffffffffffff (80000000 20000000)
++ sraw. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
++ sraw. ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (80000000 20000000)
++ sraw. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 20000000)
++
++ srw. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ srw. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ srw. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++ srw. 0000001cbe991def, 0000000000000000 => 00000000be991def (40000000 00000000)
++ srw. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ srw. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++ srw. ffffffffffffffff, 0000000000000000 => 00000000ffffffff (40000000 00000000)
++ srw. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ srw. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++
++ sld. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ sld. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ sld. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++ sld. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
++ sld. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ sld. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++ sld. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
++ sld. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ sld. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++
++ srad. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ srad. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ srad. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++ srad. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
++ srad. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ srad. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++ srad. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
++ srad. ffffffffffffffff, 0000001cbe991def => ffffffffffffffff (80000000 20000000)
++ srad. ffffffffffffffff, ffffffffffffffff => ffffffffffffffff (80000000 20000000)
++
++ srd. 0000000000000000, 0000000000000000 => 0000000000000000 (20000000 00000000)
++ srd. 0000000000000000, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ srd. 0000000000000000, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++ srd. 0000001cbe991def, 0000000000000000 => 0000001cbe991def (40000000 00000000)
++ srd. 0000001cbe991def, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ srd. 0000001cbe991def, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++ srd. ffffffffffffffff, 0000000000000000 => ffffffffffffffff (80000000 00000000)
++ srd. ffffffffffffffff, 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ srd. ffffffffffffffff, ffffffffffffffff => 0000000000000000 (20000000 00000000)
++
++PPC integer compare insns (two args):
++ cmpw 0000000000000000, 0000000000000000 => 0000000000000000 (00200000 00000000)
++ cmpw 0000000000000000, 0000001cbe991def => 0000000000000000 (00400000 00000000)
++ cmpw 0000000000000000, ffffffffffffffff => 0000000000000000 (00400000 00000000)
++ cmpw 0000001cbe991def, 0000000000000000 => 0000000000000000 (00800000 00000000)
++ cmpw 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00200000 00000000)
++ cmpw 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00800000 00000000)
++ cmpw ffffffffffffffff, 0000000000000000 => 0000000000000000 (00800000 00000000)
++ cmpw ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00400000 00000000)
++ cmpw ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00200000 00000000)
++
++ cmplw 0000000000000000, 0000000000000000 => 0000000000000000 (00200000 00000000)
++ cmplw 0000000000000000, 0000001cbe991def => 0000000000000000 (00800000 00000000)
++ cmplw 0000000000000000, ffffffffffffffff => 0000000000000000 (00800000 00000000)
++ cmplw 0000001cbe991def, 0000000000000000 => 0000000000000000 (00400000 00000000)
++ cmplw 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00200000 00000000)
++ cmplw 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00800000 00000000)
++ cmplw ffffffffffffffff, 0000000000000000 => 0000000000000000 (00400000 00000000)
++ cmplw ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00400000 00000000)
++ cmplw ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00200000 00000000)
++
++ cmpd 0000000000000000, 0000000000000000 => 0000000000000000 (00200000 00000000)
++ cmpd 0000000000000000, 0000001cbe991def => 0000000000000000 (00800000 00000000)
++ cmpd 0000000000000000, ffffffffffffffff => 0000000000000000 (00400000 00000000)
++ cmpd 0000001cbe991def, 0000000000000000 => 0000000000000000 (00400000 00000000)
++ cmpd 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00200000 00000000)
++ cmpd 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00400000 00000000)
++ cmpd ffffffffffffffff, 0000000000000000 => 0000000000000000 (00800000 00000000)
++ cmpd ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00800000 00000000)
++ cmpd ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00200000 00000000)
++
++ cmpld 0000000000000000, 0000000000000000 => 0000000000000000 (00200000 00000000)
++ cmpld 0000000000000000, 0000001cbe991def => 0000000000000000 (00800000 00000000)
++ cmpld 0000000000000000, ffffffffffffffff => 0000000000000000 (00800000 00000000)
++ cmpld 0000001cbe991def, 0000000000000000 => 0000000000000000 (00400000 00000000)
++ cmpld 0000001cbe991def, 0000001cbe991def => 0000000000000000 (00200000 00000000)
++ cmpld 0000001cbe991def, ffffffffffffffff => 0000000000000000 (00800000 00000000)
++ cmpld ffffffffffffffff, 0000000000000000 => 0000000000000000 (00400000 00000000)
++ cmpld ffffffffffffffff, 0000001cbe991def => 0000000000000000 (00400000 00000000)
++ cmpld ffffffffffffffff, ffffffffffffffff => 0000000000000000 (00200000 00000000)
++
++PPC integer compare with immediate insns (two args):
++ cmpwi 0000000000000000, 00000000 => 0000000000000000 (00200000 00000000)
++ cmpwi 0000000000000000, 000003e7 => 0000000000000000 (00800000 00000000)
++ cmpwi 0000000000000000, 0000ffff => 0000000000000000 (00400000 00000000)
++ cmpwi 0000001cbe991def, 00000000 => 0000000000000000 (00800000 00000000)
++ cmpwi 0000001cbe991def, 000003e7 => 0000000000000000 (00800000 00000000)
++ cmpwi 0000001cbe991def, 0000ffff => 0000000000000000 (00800000 00000000)
++ cmpwi ffffffffffffffff, 00000000 => 0000000000000000 (00800000 00000000)
++ cmpwi ffffffffffffffff, 000003e7 => 0000000000000000 (00800000 00000000)
++ cmpwi ffffffffffffffff, 0000ffff => 0000000000000000 (00200000 00000000)
++
++ cmplwi 0000000000000000, 00000000 => 0000000000000000 (00200000 00000000)
++ cmplwi 0000000000000000, 000003e7 => 0000000000000000 (00800000 00000000)
++ cmplwi 0000000000000000, 0000ffff => 0000000000000000 (00800000 00000000)
++ cmplwi 0000001cbe991def, 00000000 => 0000000000000000 (00400000 00000000)
++ cmplwi 0000001cbe991def, 000003e7 => 0000000000000000 (00400000 00000000)
++ cmplwi 0000001cbe991def, 0000ffff => 0000000000000000 (00400000 00000000)
++ cmplwi ffffffffffffffff, 00000000 => 0000000000000000 (00400000 00000000)
++ cmplwi ffffffffffffffff, 000003e7 => 0000000000000000 (00400000 00000000)
++ cmplwi ffffffffffffffff, 0000ffff => 0000000000000000 (00400000 00000000)
++
++ cmpdi 0000000000000000, 00000000 => 0000000000000000 (00200000 00000000)
++ cmpdi 0000000000000000, 000003e7 => 0000000000000000 (00800000 00000000)
++ cmpdi 0000000000000000, 0000ffff => 0000000000000000 (00400000 00000000)
++ cmpdi 0000001cbe991def, 00000000 => 0000000000000000 (00400000 00000000)
++ cmpdi 0000001cbe991def, 000003e7 => 0000000000000000 (00400000 00000000)
++ cmpdi 0000001cbe991def, 0000ffff => 0000000000000000 (00400000 00000000)
++ cmpdi ffffffffffffffff, 00000000 => 0000000000000000 (00800000 00000000)
++ cmpdi ffffffffffffffff, 000003e7 => 0000000000000000 (00800000 00000000)
++ cmpdi ffffffffffffffff, 0000ffff => 0000000000000000 (00200000 00000000)
++
++ cmpldi 0000000000000000, 00000000 => 0000000000000000 (00200000 00000000)
++ cmpldi 0000000000000000, 000003e7 => 0000000000000000 (00800000 00000000)
++ cmpldi 0000000000000000, 0000ffff => 0000000000000000 (00800000 00000000)
++ cmpldi 0000001cbe991def, 00000000 => 0000000000000000 (00400000 00000000)
++ cmpldi 0000001cbe991def, 000003e7 => 0000000000000000 (00400000 00000000)
++ cmpldi 0000001cbe991def, 0000ffff => 0000000000000000 (00400000 00000000)
++ cmpldi ffffffffffffffff, 00000000 => 0000000000000000 (00400000 00000000)
++ cmpldi ffffffffffffffff, 000003e7 => 0000000000000000 (00400000 00000000)
++ cmpldi ffffffffffffffff, 0000ffff => 0000000000000000 (00400000 00000000)
++
++PPC integer arith insns
++ with one register + one 16 bits immediate args:
++ addi 0000000000000000, 00000000 => 0000000000000000 (00000000 00000000)
++ addi 0000000000000000, 000003e7 => 00000000000003e7 (00000000 00000000)
++ addi 0000000000000000, 0000ffff => ffffffffffffffff (00000000 00000000)
++ addi 0000001cbe991def, 00000000 => 0000001cbe991def (00000000 00000000)
++ addi 0000001cbe991def, 000003e7 => 0000001cbe9921d6 (00000000 00000000)
++ addi 0000001cbe991def, 0000ffff => 0000001cbe991dee (00000000 00000000)
++ addi ffffffffffffffff, 00000000 => ffffffffffffffff (00000000 00000000)
++ addi ffffffffffffffff, 000003e7 => 00000000000003e6 (00000000 00000000)
++ addi ffffffffffffffff, 0000ffff => fffffffffffffffe (00000000 00000000)
++
++ addic 0000000000000000, 00000000 => 0000000000000000 (00000000 00000000)
++ addic 0000000000000000, 000003e7 => 00000000000003e7 (00000000 00000000)
++ addic 0000000000000000, 0000ffff => ffffffffffffffff (00000000 00000000)
++ addic 0000001cbe991def, 00000000 => 0000001cbe991def (00000000 00000000)
++ addic 0000001cbe991def, 000003e7 => 0000001cbe9921d6 (00000000 00000000)
++ addic 0000001cbe991def, 0000ffff => 0000001cbe991dee (00000000 20000000)
++ addic ffffffffffffffff, 00000000 => ffffffffffffffff (00000000 00000000)
++ addic ffffffffffffffff, 000003e7 => 00000000000003e6 (00000000 20000000)
++ addic ffffffffffffffff, 0000ffff => fffffffffffffffe (00000000 20000000)
++
++ addis 0000000000000000, 00000000 => 0000000000000000 (00000000 00000000)
++ addis 0000000000000000, 000003e7 => 0000000003e70000 (00000000 00000000)
++ addis 0000000000000000, 0000ffff => ffffffffffff0000 (00000000 00000000)
++ addis 0000001cbe991def, 00000000 => 0000001cbe991def (00000000 00000000)
++ addis 0000001cbe991def, 000003e7 => 0000001cc2801def (00000000 00000000)
++ addis 0000001cbe991def, 0000ffff => 0000001cbe981def (00000000 00000000)
++ addis ffffffffffffffff, 00000000 => ffffffffffffffff (00000000 00000000)
++ addis ffffffffffffffff, 000003e7 => 0000000003e6ffff (00000000 00000000)
++ addis ffffffffffffffff, 0000ffff => fffffffffffeffff (00000000 00000000)
++
++ mulli 0000000000000000, 00000000 => 0000000000000000 (00000000 00000000)
++ mulli 0000000000000000, 000003e7 => 0000000000000000 (00000000 00000000)
++ mulli 0000000000000000, 0000ffff => 0000000000000000 (00000000 00000000)
++ mulli 0000001cbe991def, 00000000 => 0000000000000000 (00000000 00000000)
++ mulli 0000001cbe991def, 000003e7 => 0000702bc783cfa9 (00000000 00000000)
++ mulli 0000001cbe991def, 0000ffff => ffffffe34166e211 (00000000 00000000)
++ mulli ffffffffffffffff, 00000000 => 0000000000000000 (00000000 00000000)
++ mulli ffffffffffffffff, 000003e7 => fffffffffffffc19 (00000000 00000000)
++ mulli ffffffffffffffff, 0000ffff => 0000000000000001 (00000000 00000000)
++
++ subfic 0000000000000000, 00000000 => 0000000000000000 (00000000 20000000)
++ subfic 0000000000000000, 000003e7 => 00000000000003e7 (00000000 20000000)
++ subfic 0000000000000000, 0000ffff => ffffffffffffffff (00000000 20000000)
++ subfic 0000001cbe991def, 00000000 => ffffffe34166e211 (00000000 00000000)
++ subfic 0000001cbe991def, 000003e7 => ffffffe34166e5f8 (00000000 00000000)
++ subfic 0000001cbe991def, 0000ffff => ffffffe34166e210 (00000000 20000000)
++ subfic ffffffffffffffff, 00000000 => 0000000000000001 (00000000 00000000)
++ subfic ffffffffffffffff, 000003e7 => 00000000000003e8 (00000000 00000000)
++ subfic ffffffffffffffff, 0000ffff => 0000000000000000 (00000000 20000000)
++
++PPC integer arith insns
++ with one register + one 16 bits immediate args with flags update:
++ addic. 0000000000000000, 00000000 => 0000000000000000 (20000000 00000000)
++ addic. 0000000000000000, 000003e7 => 00000000000003e7 (40000000 00000000)
++ addic. 0000000000000000, 0000ffff => ffffffffffffffff (80000000 00000000)
++ addic. 0000001cbe991def, 00000000 => 0000001cbe991def (40000000 00000000)
++ addic. 0000001cbe991def, 000003e7 => 0000001cbe9921d6 (40000000 00000000)
++ addic. 0000001cbe991def, 0000ffff => 0000001cbe991dee (40000000 20000000)
++ addic. ffffffffffffffff, 00000000 => ffffffffffffffff (80000000 00000000)
++ addic. ffffffffffffffff, 000003e7 => 00000000000003e6 (40000000 20000000)
++ addic. ffffffffffffffff, 0000ffff => fffffffffffffffe (80000000 20000000)
++
++PPC integer logical insns
++ with one register + one 16 bits immediate args:
++ ori 0000000000000000, 00000000 => 0000000000000000 (00000000 00000000)
++ ori 0000000000000000, 000003e7 => 00000000000003e7 (00000000 00000000)
++ ori 0000000000000000, 0000ffff => 000000000000ffff (00000000 00000000)
++ ori 0000001cbe991def, 00000000 => 0000001cbe991def (00000000 00000000)
++ ori 0000001cbe991def, 000003e7 => 0000001cbe991fef (00000000 00000000)
++ ori 0000001cbe991def, 0000ffff => 0000001cbe99ffff (00000000 00000000)
++ ori ffffffffffffffff, 00000000 => ffffffffffffffff (00000000 00000000)
++ ori ffffffffffffffff, 000003e7 => ffffffffffffffff (00000000 00000000)
++ ori ffffffffffffffff, 0000ffff => ffffffffffffffff (00000000 00000000)
++
++ oris 0000000000000000, 00000000 => 0000000000000000 (00000000 00000000)
++ oris 0000000000000000, 000003e7 => 0000000003e70000 (00000000 00000000)
++ oris 0000000000000000, 0000ffff => 00000000ffff0000 (00000000 00000000)
++ oris 0000001cbe991def, 00000000 => 0000001cbe991def (00000000 00000000)
++ oris 0000001cbe991def, 000003e7 => 0000001cbfff1def (00000000 00000000)
++ oris 0000001cbe991def, 0000ffff => 0000001cffff1def (00000000 00000000)
++ oris ffffffffffffffff, 00000000 => ffffffffffffffff (00000000 00000000)
++ oris ffffffffffffffff, 000003e7 => ffffffffffffffff (00000000 00000000)
++ oris ffffffffffffffff, 0000ffff => ffffffffffffffff (00000000 00000000)
++
++ xori 0000000000000000, 00000000 => 0000000000000000 (00000000 00000000)
++ xori 0000000000000000, 000003e7 => 00000000000003e7 (00000000 00000000)
++ xori 0000000000000000, 0000ffff => 000000000000ffff (00000000 00000000)
++ xori 0000001cbe991def, 00000000 => 0000001cbe991def (00000000 00000000)
++ xori 0000001cbe991def, 000003e7 => 0000001cbe991e08 (00000000 00000000)
++ xori 0000001cbe991def, 0000ffff => 0000001cbe99e210 (00000000 00000000)
++ xori ffffffffffffffff, 00000000 => ffffffffffffffff (00000000 00000000)
++ xori ffffffffffffffff, 000003e7 => fffffffffffffc18 (00000000 00000000)
++ xori ffffffffffffffff, 0000ffff => ffffffffffff0000 (00000000 00000000)
++
++ xoris 0000000000000000, 00000000 => 0000000000000000 (00000000 00000000)
++ xoris 0000000000000000, 000003e7 => 0000000003e70000 (00000000 00000000)
++ xoris 0000000000000000, 0000ffff => 00000000ffff0000 (00000000 00000000)
++ xoris 0000001cbe991def, 00000000 => 0000001cbe991def (00000000 00000000)
++ xoris 0000001cbe991def, 000003e7 => 0000001cbd7e1def (00000000 00000000)
++ xoris 0000001cbe991def, 0000ffff => 0000001c41661def (00000000 00000000)
++ xoris ffffffffffffffff, 00000000 => ffffffffffffffff (00000000 00000000)
++ xoris ffffffffffffffff, 000003e7 => fffffffffc18ffff (00000000 00000000)
++ xoris ffffffffffffffff, 0000ffff => ffffffff0000ffff (00000000 00000000)
++
++PPC integer logical insns
++ with one register + one 16 bits immediate args with flags update:
++ andi. 0000000000000000, 00000000 => 0000000000000000 (20000000 00000000)
++ andi. 0000000000000000, 000003e7 => 0000000000000000 (20000000 00000000)
++ andi. 0000000000000000, 0000ffff => 0000000000000000 (20000000 00000000)
++ andi. 0000001cbe991def, 00000000 => 0000000000000000 (20000000 00000000)
++ andi. 0000001cbe991def, 000003e7 => 00000000000001e7 (40000000 00000000)
++ andi. 0000001cbe991def, 0000ffff => 0000000000001def (40000000 00000000)
++ andi. ffffffffffffffff, 00000000 => 0000000000000000 (20000000 00000000)
++ andi. ffffffffffffffff, 000003e7 => 00000000000003e7 (40000000 00000000)
++ andi. ffffffffffffffff, 0000ffff => 000000000000ffff (40000000 00000000)
++
++ andis. 0000000000000000, 00000000 => 0000000000000000 (20000000 00000000)
++ andis. 0000000000000000, 000003e7 => 0000000000000000 (20000000 00000000)
++ andis. 0000000000000000, 0000ffff => 0000000000000000 (20000000 00000000)
++ andis. 0000001cbe991def, 00000000 => 0000000000000000 (20000000 00000000)
++ andis. 0000001cbe991def, 000003e7 => 0000000002810000 (40000000 00000000)
++ andis. 0000001cbe991def, 0000ffff => 00000000be990000 (40000000 00000000)
++ andis. ffffffffffffffff, 00000000 => 0000000000000000 (20000000 00000000)
++ andis. ffffffffffffffff, 000003e7 => 0000000003e70000 (40000000 00000000)
++ andis. ffffffffffffffff, 0000ffff => 00000000ffff0000 (40000000 00000000)
++
++PPC condition register logical insns - two operands:
++ crand 0000000000000000, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
++ crand 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
++ crand 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
++ crand 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
++ crand 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
++ crand 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
++ crand ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
++ crand ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
++ crand ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
++
++ crandc 0000000000000000, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
++ crandc 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
++ crandc 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
++ crandc 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
++ crandc 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
++ crandc 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
++ crandc ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
++ crandc ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
++ crandc ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
++
++ creqv 0000000000000000, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
++ creqv 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
++ creqv 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
++ creqv 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
++ creqv 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
++ creqv 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
++ creqv ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
++ creqv ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
++ creqv ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
++
++ crnand 0000000000000000, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
++ crnand 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
++ crnand 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
++ crnand 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
++ crnand 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
++ crnand 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
++ crnand ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
++ crnand ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
++ crnand ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
++
++ crnor 0000000000000000, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
++ crnor 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
++ crnor 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
++ crnor 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
++ crnor 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
++ crnor 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
++ crnor ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
++ crnor ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
++ crnor ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
++
++ cror 0000000000000000, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
++ cror 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
++ cror 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
++ cror 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
++ cror 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
++ cror 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
++ cror ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
++ cror ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
++ cror ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
++
++ crorc 0000000000000000, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
++ crorc 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
++ crorc 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
++ crorc 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
++ crorc 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
++ crorc 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
++ crorc ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00004000 00000000)
++ crorc ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00004000 00000000)
++ crorc ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00004000 00000000)
++
++ crxor 0000000000000000, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
++ crxor 0000000000000000, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
++ crxor 0000000000000000, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
++ crxor 0000001cbe991def, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
++ crxor 0000001cbe991def, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
++ crxor 0000001cbe991def, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
++ crxor ffffffffffffffff, 0000000000000000 => 00000000ffff0000 (00000000 00000000)
++ crxor ffffffffffffffff, 0000001cbe991def => 00000000ffff0000 (00000000 00000000)
++ crxor ffffffffffffffff, ffffffffffffffff => 00000000ffff0000 (00000000 00000000)
++
++PPC integer arith insns with one arg and carry:
++ addme 0000000000000000 => ffffffffffffffff (00000000 00000000)
++ addme 0000001cbe991def => 0000001cbe991dee (00000000 20000000)
++ addme ffffffffffffffff => fffffffffffffffe (00000000 20000000)
++ addme 0000000000000000 => 0000000000000000 (00000000 20000000)
++ addme 0000001cbe991def => 0000001cbe991def (00000000 20000000)
++ addme ffffffffffffffff => ffffffffffffffff (00000000 20000000)
++
++ addmeo 0000000000000000 => ffffffffffffffff (00000000 00000000)
++ addmeo 0000001cbe991def => 0000001cbe991dee (00000000 20000000)
++ addmeo ffffffffffffffff => fffffffffffffffe (00000000 20000000)
++ addmeo 0000000000000000 => 0000000000000000 (00000000 20000000)
++ addmeo 0000001cbe991def => 0000001cbe991def (00000000 20000000)
++ addmeo ffffffffffffffff => ffffffffffffffff (00000000 20000000)
++
++ addze 0000000000000000 => 0000000000000000 (00000000 00000000)
++ addze 0000001cbe991def => 0000001cbe991def (00000000 00000000)
++ addze ffffffffffffffff => ffffffffffffffff (00000000 00000000)
++ addze 0000000000000000 => 0000000000000001 (00000000 00000000)
++ addze 0000001cbe991def => 0000001cbe991df0 (00000000 00000000)
++ addze ffffffffffffffff => 0000000000000000 (00000000 20000000)
++
++ addzeo 0000000000000000 => 0000000000000000 (00000000 00000000)
++ addzeo 0000001cbe991def => 0000001cbe991def (00000000 00000000)
++ addzeo ffffffffffffffff => ffffffffffffffff (00000000 00000000)
++ addzeo 0000000000000000 => 0000000000000001 (00000000 00000000)
++ addzeo 0000001cbe991def => 0000001cbe991df0 (00000000 00000000)
++ addzeo ffffffffffffffff => 0000000000000000 (00000000 20000000)
++
++ subfme 0000000000000000 => fffffffffffffffe (00000000 20000000)
++ subfme 0000001cbe991def => ffffffe34166e20f (00000000 20000000)
++ subfme ffffffffffffffff => ffffffffffffffff (00000000 00000000)
++ subfme 0000000000000000 => ffffffffffffffff (00000000 20000000)
++ subfme 0000001cbe991def => ffffffe34166e210 (00000000 20000000)
++ subfme ffffffffffffffff => 0000000000000000 (00000000 20000000)
++
++ subfmeo 0000000000000000 => fffffffffffffffe (00000000 20000000)
++ subfmeo 0000001cbe991def => ffffffe34166e20f (00000000 20000000)
++ subfmeo ffffffffffffffff => ffffffffffffffff (00000000 00000000)
++ subfmeo 0000000000000000 => ffffffffffffffff (00000000 20000000)
++ subfmeo 0000001cbe991def => ffffffe34166e210 (00000000 20000000)
++ subfmeo ffffffffffffffff => 0000000000000000 (00000000 20000000)
++
++ subfze 0000000000000000 => ffffffffffffffff (00000000 00000000)
++ subfze 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
++ subfze ffffffffffffffff => 0000000000000000 (00000000 00000000)
++ subfze 0000000000000000 => 0000000000000000 (00000000 20000000)
++ subfze 0000001cbe991def => ffffffe34166e211 (00000000 00000000)
++ subfze ffffffffffffffff => 0000000000000001 (00000000 00000000)
++
++ subfzeo 0000000000000000 => ffffffffffffffff (00000000 00000000)
++ subfzeo 0000001cbe991def => ffffffe34166e210 (00000000 00000000)
++ subfzeo ffffffffffffffff => 0000000000000000 (00000000 00000000)
++ subfzeo 0000000000000000 => 0000000000000000 (00000000 20000000)
++ subfzeo 0000001cbe991def => ffffffe34166e211 (00000000 00000000)
++ subfzeo ffffffffffffffff => 0000000000000001 (00000000 00000000)
++
++PPC integer arith insns with one arg and carry with flags update:
++ addme. 0000000000000000 => ffffffffffffffff (80000000 00000000)
++ addme. 0000001cbe991def => 0000001cbe991dee (40000000 20000000)
++ addme. ffffffffffffffff => fffffffffffffffe (80000000 20000000)
++ addme. 0000000000000000 => 0000000000000000 (20000000 20000000)
++ addme. 0000001cbe991def => 0000001cbe991def (40000000 20000000)
++ addme. ffffffffffffffff => ffffffffffffffff (80000000 20000000)
++
++ addmeo. 0000000000000000 => ffffffffffffffff (80000000 00000000)
++ addmeo. 0000001cbe991def => 0000001cbe991dee (40000000 20000000)
++ addmeo. ffffffffffffffff => fffffffffffffffe (80000000 20000000)
++ addmeo. 0000000000000000 => 0000000000000000 (20000000 20000000)
++ addmeo. 0000001cbe991def => 0000001cbe991def (40000000 20000000)
++ addmeo. ffffffffffffffff => ffffffffffffffff (80000000 20000000)
++
++ addze. 0000000000000000 => 0000000000000000 (20000000 00000000)
++ addze. 0000001cbe991def => 0000001cbe991def (40000000 00000000)
++ addze. ffffffffffffffff => ffffffffffffffff (80000000 00000000)
++ addze. 0000000000000000 => 0000000000000001 (40000000 00000000)
++ addze. 0000001cbe991def => 0000001cbe991df0 (40000000 00000000)
++ addze. ffffffffffffffff => 0000000000000000 (20000000 20000000)
++
++ addzeo. 0000000000000000 => 0000000000000000 (20000000 00000000)
++ addzeo. 0000001cbe991def => 0000001cbe991def (40000000 00000000)
++ addzeo. ffffffffffffffff => ffffffffffffffff (80000000 00000000)
++ addzeo. 0000000000000000 => 0000000000000001 (40000000 00000000)
++ addzeo. 0000001cbe991def => 0000001cbe991df0 (40000000 00000000)
++ addzeo. ffffffffffffffff => 0000000000000000 (20000000 20000000)
++
++ subfme. 0000000000000000 => fffffffffffffffe (80000000 20000000)
++ subfme. 0000001cbe991def => ffffffe34166e20f (80000000 20000000)
++ subfme. ffffffffffffffff => ffffffffffffffff (80000000 00000000)
++ subfme. 0000000000000000 => ffffffffffffffff (80000000 20000000)
++ subfme. 0000001cbe991def => ffffffe34166e210 (80000000 20000000)
++ subfme. ffffffffffffffff => 0000000000000000 (20000000 20000000)
++
++ subfmeo. 0000000000000000 => fffffffffffffffe (80000000 20000000)
++ subfmeo. 0000001cbe991def => ffffffe34166e20f (80000000 20000000)
++ subfmeo. ffffffffffffffff => ffffffffffffffff (80000000 00000000)
++ subfmeo. 0000000000000000 => ffffffffffffffff (80000000 20000000)
++ subfmeo. 0000001cbe991def => ffffffe34166e210 (80000000 20000000)
++ subfmeo. ffffffffffffffff => 0000000000000000 (20000000 20000000)
++
++ subfze. 0000000000000000 => ffffffffffffffff (80000000 00000000)
++ subfze. 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
++ subfze. ffffffffffffffff => 0000000000000000 (20000000 00000000)
++ subfze. 0000000000000000 => 0000000000000000 (20000000 20000000)
++ subfze. 0000001cbe991def => ffffffe34166e211 (80000000 00000000)
++ subfze. ffffffffffffffff => 0000000000000001 (40000000 00000000)
++
++ subfzeo. 0000000000000000 => ffffffffffffffff (80000000 00000000)
++ subfzeo. 0000001cbe991def => ffffffe34166e210 (80000000 00000000)
++ subfzeo. ffffffffffffffff => 0000000000000000 (20000000 00000000)
++ subfzeo. 0000000000000000 => 0000000000000000 (20000000 20000000)
++ subfzeo. 0000001cbe991def => ffffffe34166e211 (80000000 00000000)
++ subfzeo. ffffffffffffffff => 0000000000000001 (40000000 00000000)
++
++PPC integer logical insns with one arg:
++ cntlzw 0000000000000000 => 0000000000000020 (00000000 00000000)
++ cntlzw 0000001cbe991def => 0000000000000000 (00000000 00000000)
++ cntlzw ffffffffffffffff => 0000000000000000 (00000000 00000000)
++
++ extsb 0000000000000000 => 0000000000000000 (00000000 00000000)
++ extsb 0000001cbe991def => ffffffffffffffef (00000000 00000000)
++ extsb ffffffffffffffff => ffffffffffffffff (00000000 00000000)
++
++ extsh 0000000000000000 => 0000000000000000 (00000000 00000000)
++ extsh 0000001cbe991def => 0000000000001def (00000000 00000000)
++ extsh ffffffffffffffff => ffffffffffffffff (00000000 00000000)
++
++ neg 0000000000000000 => 0000000000000000 (00000000 00000000)
++ neg 0000001cbe991def => ffffffe34166e211 (00000000 00000000)
++ neg ffffffffffffffff => 0000000000000001 (00000000 00000000)
++
++ nego 0000000000000000 => 0000000000000000 (00000000 00000000)
++ nego 0000001cbe991def => ffffffe34166e211 (00000000 00000000)
++ nego ffffffffffffffff => 0000000000000001 (00000000 00000000)
++
++ cntlzd 0000000000000000 => 0000000000000040 (00000000 00000000)
++ cntlzd 0000001cbe991def => 000000000000001b (00000000 00000000)
++ cntlzd ffffffffffffffff => 0000000000000000 (00000000 00000000)
++
++ extsw 0000000000000000 => 0000000000000000 (00000000 00000000)
++ extsw 0000001cbe991def => ffffffffbe991def (00000000 00000000)
++ extsw ffffffffffffffff => ffffffffffffffff (00000000 00000000)
++
++PPC integer logical insns with one arg with flags update:
++ cntlzw. 0000000000000000 => 0000000000000020 (40000000 00000000)
++ cntlzw. 0000001cbe991def => 0000000000000000 (20000000 00000000)
++ cntlzw. ffffffffffffffff => 0000000000000000 (20000000 00000000)
++
++ extsb. 0000000000000000 => 0000000000000000 (20000000 00000000)
++ extsb. 0000001cbe991def => ffffffffffffffef (80000000 00000000)
++ extsb. ffffffffffffffff => ffffffffffffffff (80000000 00000000)
++
++ extsh. 0000000000000000 => 0000000000000000 (20000000 00000000)
++ extsh. 0000001cbe991def => 0000000000001def (40000000 00000000)
++ extsh. ffffffffffffffff => ffffffffffffffff (80000000 00000000)
++
++ neg. 0000000000000000 => 0000000000000000 (20000000 00000000)
++ neg. 0000001cbe991def => ffffffe34166e211 (80000000 00000000)
++ neg. ffffffffffffffff => 0000000000000001 (40000000 00000000)
++
++ nego. 0000000000000000 => 0000000000000000 (20000000 00000000)
++ nego. 0000001cbe991def => ffffffe34166e211 (80000000 00000000)
++ nego. ffffffffffffffff => 0000000000000001 (40000000 00000000)
++
++ cntlzd. 0000000000000000 => 0000000000000040 (40000000 00000000)
++ cntlzd. 0000001cbe991def => 000000000000001b (40000000 00000000)
++ cntlzd. ffffffffffffffff => 0000000000000000 (20000000 00000000)
++
++ extsw. 0000000000000000 => 0000000000000000 (20000000 00000000)
++ extsw. 0000001cbe991def => ffffffffbe991def (80000000 00000000)
++ extsw. ffffffffffffffff => ffffffffffffffff (80000000 00000000)
++
++PPC logical insns with special forms:
++ rlwimi 0000000000000000, 0, 0, 0 => 0000000000000000 (00000000 00000000)
++ rlwimi 0000000000000000, 0, 0, 31 => 0000000000000000 (00000000 00000000)
++ rlwimi 0000000000000000, 0, 31, 0 => 0000000000000000 (00000000 00000000)
++ rlwimi 0000000000000000, 0, 31, 31 => 0000000000000000 (00000000 00000000)
++ rlwimi 0000000000000000, 31, 0, 0 => 0000000000000000 (00000000 00000000)
++ rlwimi 0000000000000000, 31, 0, 31 => 0000000000000000 (00000000 00000000)
++ rlwimi 0000000000000000, 31, 31, 0 => 0000000000000000 (00000000 00000000)
++ rlwimi 0000000000000000, 31, 31, 31 => 0000000000000000 (00000000 00000000)
++ rlwimi 0000001cbe991def, 0, 0, 0 => 0000000080000000 (00000000 00000000)
++ rlwimi 0000001cbe991def, 0, 0, 31 => 00000000be991def (00000000 00000000)
++ rlwimi 0000001cbe991def, 0, 31, 0 => be991defbe991def (00000000 00000000)
++ rlwimi 0000001cbe991def, 0, 31, 31 => be991defbe991def (00000000 00000000)
++ rlwimi 0000001cbe991def, 31, 0, 0 => be991defbe991def (00000000 00000000)
++ rlwimi 0000001cbe991def, 31, 0, 31 => be991defdf4c8ef7 (00000000 00000000)
++ rlwimi 0000001cbe991def, 31, 31, 0 => df4c8ef7df4c8ef7 (00000000 00000000)
++ rlwimi 0000001cbe991def, 31, 31, 31 => df4c8ef7df4c8ef7 (00000000 00000000)
++ rlwimi ffffffffffffffff, 0, 0, 0 => df4c8ef7df4c8ef7 (00000000 00000000)
++ rlwimi ffffffffffffffff, 0, 0, 31 => df4c8ef7ffffffff (00000000 00000000)
++ rlwimi ffffffffffffffff, 0, 31, 0 => ffffffffffffffff (00000000 00000000)
++ rlwimi ffffffffffffffff, 0, 31, 31 => ffffffffffffffff (00000000 00000000)
++ rlwimi ffffffffffffffff, 31, 0, 0 => ffffffffffffffff (00000000 00000000)
++ rlwimi ffffffffffffffff, 31, 0, 31 => ffffffffffffffff (00000000 00000000)
++ rlwimi ffffffffffffffff, 31, 31, 0 => ffffffffffffffff (00000000 00000000)
++ rlwimi ffffffffffffffff, 31, 31, 31 => ffffffffffffffff (00000000 00000000)
++
++ rlwinm 0000000000000000, 0, 0, 0 => 0000000000000000 (00000000 00000000)
++ rlwinm 0000000000000000, 0, 0, 31 => 0000000000000000 (00000000 00000000)
++ rlwinm 0000000000000000, 0, 31, 0 => 0000000000000000 (00000000 00000000)
++ rlwinm 0000000000000000, 0, 31, 31 => 0000000000000000 (00000000 00000000)
++ rlwinm 0000000000000000, 31, 0, 0 => 0000000000000000 (00000000 00000000)
++ rlwinm 0000000000000000, 31, 0, 31 => 0000000000000000 (00000000 00000000)
++ rlwinm 0000000000000000, 31, 31, 0 => 0000000000000000 (00000000 00000000)
++ rlwinm 0000000000000000, 31, 31, 31 => 0000000000000000 (00000000 00000000)
++ rlwinm 0000001cbe991def, 0, 0, 0 => 0000000080000000 (00000000 00000000)
++ rlwinm 0000001cbe991def, 0, 0, 31 => 00000000be991def (00000000 00000000)
++ rlwinm 0000001cbe991def, 0, 31, 0 => be991def80000001 (00000000 00000000)
++ rlwinm 0000001cbe991def, 0, 31, 31 => 0000000000000001 (00000000 00000000)
++ rlwinm 0000001cbe991def, 31, 0, 0 => 0000000080000000 (00000000 00000000)
++ rlwinm 0000001cbe991def, 31, 0, 31 => 00000000df4c8ef7 (00000000 00000000)
++ rlwinm 0000001cbe991def, 31, 31, 0 => df4c8ef780000001 (00000000 00000000)
++ rlwinm 0000001cbe991def, 31, 31, 31 => 0000000000000001 (00000000 00000000)
++ rlwinm ffffffffffffffff, 0, 0, 0 => 0000000080000000 (00000000 00000000)
++ rlwinm ffffffffffffffff, 0, 0, 31 => 00000000ffffffff (00000000 00000000)
++ rlwinm ffffffffffffffff, 0, 31, 0 => ffffffff80000001 (00000000 00000000)
++ rlwinm ffffffffffffffff, 0, 31, 31 => 0000000000000001 (00000000 00000000)
++ rlwinm ffffffffffffffff, 31, 0, 0 => 0000000080000000 (00000000 00000000)
++ rlwinm ffffffffffffffff, 31, 0, 31 => 00000000ffffffff (00000000 00000000)
++ rlwinm ffffffffffffffff, 31, 31, 0 => ffffffff80000001 (00000000 00000000)
++ rlwinm ffffffffffffffff, 31, 31, 31 => 0000000000000001 (00000000 00000000)
++
++ rlwnm 0000000000000000, 0000000000000000, 0, 0 => 0000000000000000 (00000000 00000000)
++ rlwnm 0000000000000000, 0000000000000000, 0, 31 => 0000000000000000 (00000000 00000000)
++ rlwnm 0000000000000000, 0000000000000000, 31, 0 => 0000000000000000 (00000000 00000000)
++ rlwnm 0000000000000000, 0000000000000000, 31, 31 => 0000000000000000 (00000000 00000000)
++ rlwnm 0000000000000000, 0000001cbe991def, 0, 0 => 0000000000000000 (00000000 00000000)
++ rlwnm 0000000000000000, 0000001cbe991def, 0, 31 => 0000000000000000 (00000000 00000000)
++ rlwnm 0000000000000000, 0000001cbe991def, 31, 0 => 0000000000000000 (00000000 00000000)
++ rlwnm 0000000000000000, 0000001cbe991def, 31, 31 => 0000000000000000 (00000000 00000000)
++ rlwnm 0000000000000000, ffffffffffffffff, 0, 0 => 0000000000000000 (00000000 00000000)
++ rlwnm 0000000000000000, ffffffffffffffff, 0, 31 => 0000000000000000 (00000000 00000000)
++ rlwnm 0000000000000000, ffffffffffffffff, 31, 0 => 0000000000000000 (00000000 00000000)
++ rlwnm 0000000000000000, ffffffffffffffff, 31, 31 => 0000000000000000 (00000000 00000000)
++ rlwnm 0000001cbe991def, 0000000000000000, 0, 0 => 0000000080000000 (00000000 00000000)
++ rlwnm 0000001cbe991def, 0000000000000000, 0, 31 => 00000000be991def (00000000 00000000)
++ rlwnm 0000001cbe991def, 0000000000000000, 31, 0 => be991def80000001 (00000000 00000000)
++ rlwnm 0000001cbe991def, 0000000000000000, 31, 31 => 0000000000000001 (00000000 00000000)
++ rlwnm 0000001cbe991def, 0000001cbe991def, 0, 0 => 0000000080000000 (00000000 00000000)
++ rlwnm 0000001cbe991def, 0000001cbe991def, 0, 31 => 000000008ef7df4c (00000000 00000000)
++ rlwnm 0000001cbe991def, 0000001cbe991def, 31, 0 => 8ef7df4c80000000 (00000000 00000000)
++ rlwnm 0000001cbe991def, 0000001cbe991def, 31, 31 => 0000000000000000 (00000000 00000000)
++ rlwnm 0000001cbe991def, ffffffffffffffff, 0, 0 => 0000000080000000 (00000000 00000000)
++ rlwnm 0000001cbe991def, ffffffffffffffff, 0, 31 => 00000000df4c8ef7 (00000000 00000000)
++ rlwnm 0000001cbe991def, ffffffffffffffff, 31, 0 => df4c8ef780000001 (00000000 00000000)
++ rlwnm 0000001cbe991def, ffffffffffffffff, 31, 31 => 0000000000000001 (00000000 00000000)
++ rlwnm ffffffffffffffff, 0000000000000000, 0, 0 => 0000000080000000 (00000000 00000000)
++ rlwnm ffffffffffffffff, 0000000000000000, 0, 31 => 00000000ffffffff (00000000 00000000)
++ rlwnm ffffffffffffffff, 0000000000000000, 31, 0 => ffffffff80000001 (00000000 00000000)
++ rlwnm ffffffffffffffff, 0000000000000000, 31, 31 => 0000000000000001 (00000000 00000000)
++ rlwnm ffffffffffffffff, 0000001cbe991def, 0, 0 => 0000000080000000 (00000000 00000000)
++ rlwnm ffffffffffffffff, 0000001cbe991def, 0, 31 => 00000000ffffffff (00000000 00000000)
++ rlwnm ffffffffffffffff, 0000001cbe991def, 31, 0 => ffffffff80000001 (00000000 00000000)
++ rlwnm ffffffffffffffff, 0000001cbe991def, 31, 31 => 0000000000000001 (00000000 00000000)
++ rlwnm ffffffffffffffff, ffffffffffffffff, 0, 0 => 0000000080000000 (00000000 00000000)
++ rlwnm ffffffffffffffff, ffffffffffffffff, 0, 31 => 00000000ffffffff (00000000 00000000)
++ rlwnm ffffffffffffffff, ffffffffffffffff, 31, 0 => ffffffff80000001 (00000000 00000000)
++ rlwnm ffffffffffffffff, ffffffffffffffff, 31, 31 => 0000000000000001 (00000000 00000000)
++
++ srawi 0000000000000000, 0 => 0000000000000000 (00000000 00000000)
++ srawi 0000000000000000, 31 => 0000000000000000 (00000000 00000000)
++ srawi 0000001cbe991def, 0 => ffffffffbe991def (00000000 00000000)
++ srawi 0000001cbe991def, 31 => ffffffffffffffff (00000000 20000000)
++ srawi ffffffffffffffff, 0 => ffffffffffffffff (00000000 00000000)
++ srawi ffffffffffffffff, 31 => ffffffffffffffff (00000000 20000000)
++
++ mfcr (0000000000000000) => 0000000000000000 (00000000 00000000)
++ mfcr (0000001cbe991def) => 00000000be991def (be991def 00000000)
++ mfcr (ffffffffffffffff) => 00000000ffffffff (ffffffff 00000000)
++
++ mfspr 1 (00000000) -> mtxer -> mfxer => 0000000000000000
++ mfspr 1 (be991def) -> mtxer -> mfxer => 00000000a000006f
++ mfspr 1 (ffffffff) -> mtxer -> mfxer => 00000000e000007f
++ mfspr 8 (00000000) -> mtlr -> mflr => 0000000000000000
++ mfspr 8 (be991def) -> mtlr -> mflr => ffffffffbe991def
++ mfspr 8 (ffffffff) -> mtlr -> mflr => ffffffffffffffff
++ mfspr 9 (00000000) -> mtctr -> mfctr => 0000000000000000
++ mfspr 9 (be991def) -> mtctr -> mfctr => ffffffffbe991def
++ mfspr 9 (ffffffff) -> mtctr -> mfctr => ffffffffffffffff
++
++
++ rldcl 0000000000000000, 0000000000000000, 0 => 0000000000000000 (00000000 00000000)
++ rldcl 0000000000000000, 0000000000000000, 7 => 0000000000000000 (00000000 00000000)
++ rldcl 0000000000000000, 0000000000000000, 14 => 0000000000000000 (00000000 00000000)
++ rldcl 0000000000000000, 0000000000000000, 21 => 0000000000000000 (00000000 00000000)
++ rldcl 0000000000000000, 0000000000000000, 28 => 0000000000000000 (00000000 00000000)
++ rldcl 0000000000000000, 0000000000000000, 35 => 0000000000000000 (00000000 00000000)
++ rldcl 0000000000000000, 0000000000000000, 42 => 0000000000000000 (00000000 00000000)
++ rldcl 0000000000000000, 0000000000000000, 49 => 0000000000000000 (00000000 00000000)
++ rldcl 0000000000000000, 0000000000000000, 56 => 0000000000000000 (00000000 00000000)
++ rldcl 0000000000000000, 0000000000000000, 63 => 0000000000000000 (00000000 00000000)
++ rldcl 0000000000000000, 0000001cbe991def, 0 => 0000000000000000 (00000000 00000000)
++ rldcl 0000000000000000, 0000001cbe991def, 7 => 0000000000000000 (00000000 00000000)
++ rldcl 0000000000000000, 0000001cbe991def, 14 => 0000000000000000 (00000000 00000000)
++ rldcl 0000000000000000, 0000001cbe991def, 21 => 0000000000000000 (00000000 00000000)
++ rldcl 0000000000000000, 0000001cbe991def, 28 => 0000000000000000 (00000000 00000000)
++ rldcl 0000000000000000, 0000001cbe991def, 35 => 0000000000000000 (00000000 00000000)
++ rldcl 0000000000000000, 0000001cbe991def, 42 => 0000000000000000 (00000000 00000000)
++ rldcl 0000000000000000, 0000001cbe991def, 49 => 0000000000000000 (00000000 00000000)
++ rldcl 0000000000000000, 0000001cbe991def, 56 => 0000000000000000 (00000000 00000000)
++ rldcl 0000000000000000, 0000001cbe991def, 63 => 0000000000000000 (00000000 00000000)
++ rldcl 0000000000000000, ffffffffffffffff, 0 => 0000000000000000 (00000000 00000000)
++ rldcl 0000000000000000, ffffffffffffffff, 7 => 0000000000000000 (00000000 00000000)
++ rldcl 0000000000000000, ffffffffffffffff, 14 => 0000000000000000 (00000000 00000000)
++ rldcl 0000000000000000, ffffffffffffffff, 21 => 0000000000000000 (00000000 00000000)
++ rldcl 0000000000000000, ffffffffffffffff, 28 => 0000000000000000 (00000000 00000000)
++ rldcl 0000000000000000, ffffffffffffffff, 35 => 0000000000000000 (00000000 00000000)
++ rldcl 0000000000000000, ffffffffffffffff, 42 => 0000000000000000 (00000000 00000000)
++ rldcl 0000000000000000, ffffffffffffffff, 49 => 0000000000000000 (00000000 00000000)
++ rldcl 0000000000000000, ffffffffffffffff, 56 => 0000000000000000 (00000000 00000000)
++ rldcl 0000000000000000, ffffffffffffffff, 63 => 0000000000000000 (00000000 00000000)
++ rldcl 0000001cbe991def, 0000000000000000, 0 => 0000001cbe991def (00000000 00000000)
++ rldcl 0000001cbe991def, 0000000000000000, 7 => 0000001cbe991def (00000000 00000000)
++ rldcl 0000001cbe991def, 0000000000000000, 14 => 0000001cbe991def (00000000 00000000)
++ rldcl 0000001cbe991def, 0000000000000000, 21 => 0000001cbe991def (00000000 00000000)
++ rldcl 0000001cbe991def, 0000000000000000, 28 => 0000000cbe991def (00000000 00000000)
++ rldcl 0000001cbe991def, 0000000000000000, 35 => 000000001e991def (00000000 00000000)
++ rldcl 0000001cbe991def, 0000000000000000, 42 => 0000000000191def (00000000 00000000)
++ rldcl 0000001cbe991def, 0000000000000000, 49 => 0000000000001def (00000000 00000000)
++ rldcl 0000001cbe991def, 0000000000000000, 56 => 00000000000000ef (00000000 00000000)
++ rldcl 0000001cbe991def, 0000000000000000, 63 => 0000000000000001 (00000000 00000000)
++ rldcl 0000001cbe991def, 0000001cbe991def, 0 => 8ef78000000e5f4c (00000000 00000000)
++ rldcl 0000001cbe991def, 0000001cbe991def, 7 => 00f78000000e5f4c (00000000 00000000)
++ rldcl 0000001cbe991def, 0000001cbe991def, 14 => 00038000000e5f4c (00000000 00000000)
++ rldcl 0000001cbe991def, 0000001cbe991def, 21 => 00000000000e5f4c (00000000 00000000)
++ rldcl 0000001cbe991def, 0000001cbe991def, 28 => 00000000000e5f4c (00000000 00000000)
++ rldcl 0000001cbe991def, 0000001cbe991def, 35 => 00000000000e5f4c (00000000 00000000)
++ rldcl 0000001cbe991def, 0000001cbe991def, 42 => 00000000000e5f4c (00000000 00000000)
++ rldcl 0000001cbe991def, 0000001cbe991def, 49 => 0000000000005f4c (00000000 00000000)
++ rldcl 0000001cbe991def, 0000001cbe991def, 56 => 000000000000004c (00000000 00000000)
++ rldcl 0000001cbe991def, 0000001cbe991def, 63 => 0000000000000000 (00000000 00000000)
++ rldcl 0000001cbe991def, ffffffffffffffff, 0 => 8000000e5f4c8ef7 (00000000 00000000)
++ rldcl 0000001cbe991def, ffffffffffffffff, 7 => 0000000e5f4c8ef7 (00000000 00000000)
++ rldcl 0000001cbe991def, ffffffffffffffff, 14 => 0000000e5f4c8ef7 (00000000 00000000)
++ rldcl 0000001cbe991def, ffffffffffffffff, 21 => 0000000e5f4c8ef7 (00000000 00000000)
++ rldcl 0000001cbe991def, ffffffffffffffff, 28 => 0000000e5f4c8ef7 (00000000 00000000)
++ rldcl 0000001cbe991def, ffffffffffffffff, 35 => 000000001f4c8ef7 (00000000 00000000)
++ rldcl 0000001cbe991def, ffffffffffffffff, 42 => 00000000000c8ef7 (00000000 00000000)
++ rldcl 0000001cbe991def, ffffffffffffffff, 49 => 0000000000000ef7 (00000000 00000000)
++ rldcl 0000001cbe991def, ffffffffffffffff, 56 => 00000000000000f7 (00000000 00000000)
++ rldcl 0000001cbe991def, ffffffffffffffff, 63 => 0000000000000001 (00000000 00000000)
++ rldcl ffffffffffffffff, 0000000000000000, 0 => ffffffffffffffff (00000000 00000000)
++ rldcl ffffffffffffffff, 0000000000000000, 7 => 01ffffffffffffff (00000000 00000000)
++ rldcl ffffffffffffffff, 0000000000000000, 14 => 0003ffffffffffff (00000000 00000000)
++ rldcl ffffffffffffffff, 0000000000000000, 21 => 000007ffffffffff (00000000 00000000)
++ rldcl ffffffffffffffff, 0000000000000000, 28 => 0000000fffffffff (00000000 00000000)
++ rldcl ffffffffffffffff, 0000000000000000, 35 => 000000001fffffff (00000000 00000000)
++ rldcl ffffffffffffffff, 0000000000000000, 42 => 00000000003fffff (00000000 00000000)
++ rldcl ffffffffffffffff, 0000000000000000, 49 => 0000000000007fff (00000000 00000000)
++ rldcl ffffffffffffffff, 0000000000000000, 56 => 00000000000000ff (00000000 00000000)
++ rldcl ffffffffffffffff, 0000000000000000, 63 => 0000000000000001 (00000000 00000000)
++ rldcl ffffffffffffffff, 0000001cbe991def, 0 => ffffffffffffffff (00000000 00000000)
++ rldcl ffffffffffffffff, 0000001cbe991def, 7 => 01ffffffffffffff (00000000 00000000)
++ rldcl ffffffffffffffff, 0000001cbe991def, 14 => 0003ffffffffffff (00000000 00000000)
++ rldcl ffffffffffffffff, 0000001cbe991def, 21 => 000007ffffffffff (00000000 00000000)
++ rldcl ffffffffffffffff, 0000001cbe991def, 28 => 0000000fffffffff (00000000 00000000)
++ rldcl ffffffffffffffff, 0000001cbe991def, 35 => 000000001fffffff (00000000 00000000)
++ rldcl ffffffffffffffff, 0000001cbe991def, 42 => 00000000003fffff (00000000 00000000)
++ rldcl ffffffffffffffff, 0000001cbe991def, 49 => 0000000000007fff (00000000 00000000)
++ rldcl ffffffffffffffff, 0000001cbe991def, 56 => 00000000000000ff (00000000 00000000)
++ rldcl ffffffffffffffff, 0000001cbe991def, 63 => 0000000000000001 (00000000 00000000)
++ rldcl ffffffffffffffff, ffffffffffffffff, 0 => ffffffffffffffff (00000000 00000000)
++ rldcl ffffffffffffffff, ffffffffffffffff, 7 => 01ffffffffffffff (00000000 00000000)
++ rldcl ffffffffffffffff, ffffffffffffffff, 14 => 0003ffffffffffff (00000000 00000000)
++ rldcl ffffffffffffffff, ffffffffffffffff, 21 => 000007ffffffffff (00000000 00000000)
++ rldcl ffffffffffffffff, ffffffffffffffff, 28 => 0000000fffffffff (00000000 00000000)
++ rldcl ffffffffffffffff, ffffffffffffffff, 35 => 000000001fffffff (00000000 00000000)
++ rldcl ffffffffffffffff, ffffffffffffffff, 42 => 00000000003fffff (00000000 00000000)
++ rldcl ffffffffffffffff, ffffffffffffffff, 49 => 0000000000007fff (00000000 00000000)
++ rldcl ffffffffffffffff, ffffffffffffffff, 56 => 00000000000000ff (00000000 00000000)
++ rldcl ffffffffffffffff, ffffffffffffffff, 63 => 0000000000000001 (00000000 00000000)
++
++ rldcr 0000000000000000, 0000000000000000, 0 => 0000000000000000 (00000000 00000000)
++ rldcr 0000000000000000, 0000000000000000, 7 => 0000000000000000 (00000000 00000000)
++ rldcr 0000000000000000, 0000000000000000, 14 => 0000000000000000 (00000000 00000000)
++ rldcr 0000000000000000, 0000000000000000, 21 => 0000000000000000 (00000000 00000000)
++ rldcr 0000000000000000, 0000000000000000, 28 => 0000000000000000 (00000000 00000000)
++ rldcr 0000000000000000, 0000000000000000, 35 => 0000000000000000 (00000000 00000000)
++ rldcr 0000000000000000, 0000000000000000, 42 => 0000000000000000 (00000000 00000000)
++ rldcr 0000000000000000, 0000000000000000, 49 => 0000000000000000 (00000000 00000000)
++ rldcr 0000000000000000, 0000000000000000, 56 => 0000000000000000 (00000000 00000000)
++ rldcr 0000000000000000, 0000000000000000, 63 => 0000000000000000 (00000000 00000000)
++ rldcr 0000000000000000, 0000001cbe991def, 0 => 0000000000000000 (00000000 00000000)
++ rldcr 0000000000000000, 0000001cbe991def, 7 => 0000000000000000 (00000000 00000000)
++ rldcr 0000000000000000, 0000001cbe991def, 14 => 0000000000000000 (00000000 00000000)
++ rldcr 0000000000000000, 0000001cbe991def, 21 => 0000000000000000 (00000000 00000000)
++ rldcr 0000000000000000, 0000001cbe991def, 28 => 0000000000000000 (00000000 00000000)
++ rldcr 0000000000000000, 0000001cbe991def, 35 => 0000000000000000 (00000000 00000000)
++ rldcr 0000000000000000, 0000001cbe991def, 42 => 0000000000000000 (00000000 00000000)
++ rldcr 0000000000000000, 0000001cbe991def, 49 => 0000000000000000 (00000000 00000000)
++ rldcr 0000000000000000, 0000001cbe991def, 56 => 0000000000000000 (00000000 00000000)
++ rldcr 0000000000000000, 0000001cbe991def, 63 => 0000000000000000 (00000000 00000000)
++ rldcr 0000000000000000, ffffffffffffffff, 0 => 0000000000000000 (00000000 00000000)
++ rldcr 0000000000000000, ffffffffffffffff, 7 => 0000000000000000 (00000000 00000000)
++ rldcr 0000000000000000, ffffffffffffffff, 14 => 0000000000000000 (00000000 00000000)
++ rldcr 0000000000000000, ffffffffffffffff, 21 => 0000000000000000 (00000000 00000000)
++ rldcr 0000000000000000, ffffffffffffffff, 28 => 0000000000000000 (00000000 00000000)
++ rldcr 0000000000000000, ffffffffffffffff, 35 => 0000000000000000 (00000000 00000000)
++ rldcr 0000000000000000, ffffffffffffffff, 42 => 0000000000000000 (00000000 00000000)
++ rldcr 0000000000000000, ffffffffffffffff, 49 => 0000000000000000 (00000000 00000000)
++ rldcr 0000000000000000, ffffffffffffffff, 56 => 0000000000000000 (00000000 00000000)
++ rldcr 0000000000000000, ffffffffffffffff, 63 => 0000000000000000 (00000000 00000000)
++ rldcr 0000001cbe991def, 0000000000000000, 0 => 0000000000000000 (00000000 00000000)
++ rldcr 0000001cbe991def, 0000000000000000, 7 => 0000000000000000 (00000000 00000000)
++ rldcr 0000001cbe991def, 0000000000000000, 14 => 0000000000000000 (00000000 00000000)
++ rldcr 0000001cbe991def, 0000000000000000, 21 => 0000000000000000 (00000000 00000000)
++ rldcr 0000001cbe991def, 0000000000000000, 28 => 0000001800000000 (00000000 00000000)
++ rldcr 0000001cbe991def, 0000000000000000, 35 => 0000001cb0000000 (00000000 00000000)
++ rldcr 0000001cbe991def, 0000000000000000, 42 => 0000001cbe800000 (00000000 00000000)
++ rldcr 0000001cbe991def, 0000000000000000, 49 => 0000001cbe990000 (00000000 00000000)
++ rldcr 0000001cbe991def, 0000000000000000, 56 => 0000001cbe991d80 (00000000 00000000)
++ rldcr 0000001cbe991def, 0000000000000000, 63 => 0000001cbe991def (00000000 00000000)
++ rldcr 0000001cbe991def, 0000001cbe991def, 0 => 8000000000000000 (00000000 00000000)
++ rldcr 0000001cbe991def, 0000001cbe991def, 7 => 8e00000000000000 (00000000 00000000)
++ rldcr 0000001cbe991def, 0000001cbe991def, 14 => 8ef6000000000000 (00000000 00000000)
++ rldcr 0000001cbe991def, 0000001cbe991def, 21 => 8ef7800000000000 (00000000 00000000)
++ rldcr 0000001cbe991def, 0000001cbe991def, 28 => 8ef7800000000000 (00000000 00000000)
++ rldcr 0000001cbe991def, 0000001cbe991def, 35 => 8ef7800000000000 (00000000 00000000)
++ rldcr 0000001cbe991def, 0000001cbe991def, 42 => 8ef7800000000000 (00000000 00000000)
++ rldcr 0000001cbe991def, 0000001cbe991def, 49 => 8ef78000000e4000 (00000000 00000000)
++ rldcr 0000001cbe991def, 0000001cbe991def, 56 => 8ef78000000e5f00 (00000000 00000000)
++ rldcr 0000001cbe991def, 0000001cbe991def, 63 => 8ef78000000e5f4c (00000000 00000000)
++ rldcr 0000001cbe991def, ffffffffffffffff, 0 => 8000000000000000 (00000000 00000000)
++ rldcr 0000001cbe991def, ffffffffffffffff, 7 => 8000000000000000 (00000000 00000000)
++ rldcr 0000001cbe991def, ffffffffffffffff, 14 => 8000000000000000 (00000000 00000000)
++ rldcr 0000001cbe991def, ffffffffffffffff, 21 => 8000000000000000 (00000000 00000000)
++ rldcr 0000001cbe991def, ffffffffffffffff, 28 => 8000000800000000 (00000000 00000000)
++ rldcr 0000001cbe991def, ffffffffffffffff, 35 => 8000000e50000000 (00000000 00000000)
++ rldcr 0000001cbe991def, ffffffffffffffff, 42 => 8000000e5f400000 (00000000 00000000)
++ rldcr 0000001cbe991def, ffffffffffffffff, 49 => 8000000e5f4c8000 (00000000 00000000)
++ rldcr 0000001cbe991def, ffffffffffffffff, 56 => 8000000e5f4c8e80 (00000000 00000000)
++ rldcr 0000001cbe991def, ffffffffffffffff, 63 => 8000000e5f4c8ef7 (00000000 00000000)
++ rldcr ffffffffffffffff, 0000000000000000, 0 => 8000000000000000 (00000000 00000000)
++ rldcr ffffffffffffffff, 0000000000000000, 7 => ff00000000000000 (00000000 00000000)
++ rldcr ffffffffffffffff, 0000000000000000, 14 => fffe000000000000 (00000000 00000000)
++ rldcr ffffffffffffffff, 0000000000000000, 21 => fffffc0000000000 (00000000 00000000)
++ rldcr ffffffffffffffff, 0000000000000000, 28 => fffffff800000000 (00000000 00000000)
++ rldcr ffffffffffffffff, 0000000000000000, 35 => fffffffff0000000 (00000000 00000000)
++ rldcr ffffffffffffffff, 0000000000000000, 42 => ffffffffffe00000 (00000000 00000000)
++ rldcr ffffffffffffffff, 0000000000000000, 49 => ffffffffffffc000 (00000000 00000000)
++ rldcr ffffffffffffffff, 0000000000000000, 56 => ffffffffffffff80 (00000000 00000000)
++ rldcr ffffffffffffffff, 0000000000000000, 63 => ffffffffffffffff (00000000 00000000)
++ rldcr ffffffffffffffff, 0000001cbe991def, 0 => 8000000000000000 (00000000 00000000)
++ rldcr ffffffffffffffff, 0000001cbe991def, 7 => ff00000000000000 (00000000 00000000)
++ rldcr ffffffffffffffff, 0000001cbe991def, 14 => fffe000000000000 (00000000 00000000)
++ rldcr ffffffffffffffff, 0000001cbe991def, 21 => fffffc0000000000 (00000000 00000000)
++ rldcr ffffffffffffffff, 0000001cbe991def, 28 => fffffff800000000 (00000000 00000000)
++ rldcr ffffffffffffffff, 0000001cbe991def, 35 => fffffffff0000000 (00000000 00000000)
++ rldcr ffffffffffffffff, 0000001cbe991def, 42 => ffffffffffe00000 (00000000 00000000)
++ rldcr ffffffffffffffff, 0000001cbe991def, 49 => ffffffffffffc000 (00000000 00000000)
++ rldcr ffffffffffffffff, 0000001cbe991def, 56 => ffffffffffffff80 (00000000 00000000)
++ rldcr ffffffffffffffff, 0000001cbe991def, 63 => ffffffffffffffff (00000000 00000000)
++ rldcr ffffffffffffffff, ffffffffffffffff, 0 => 8000000000000000 (00000000 00000000)
++ rldcr ffffffffffffffff, ffffffffffffffff, 7 => ff00000000000000 (00000000 00000000)
++ rldcr ffffffffffffffff, ffffffffffffffff, 14 => fffe000000000000 (00000000 00000000)
++ rldcr ffffffffffffffff, ffffffffffffffff, 21 => fffffc0000000000 (00000000 00000000)
++ rldcr ffffffffffffffff, ffffffffffffffff, 28 => fffffff800000000 (00000000 00000000)
++ rldcr ffffffffffffffff, ffffffffffffffff, 35 => fffffffff0000000 (00000000 00000000)
++ rldcr ffffffffffffffff, ffffffffffffffff, 42 => ffffffffffe00000 (00000000 00000000)
++ rldcr ffffffffffffffff, ffffffffffffffff, 49 => ffffffffffffc000 (00000000 00000000)
++ rldcr ffffffffffffffff, ffffffffffffffff, 56 => ffffffffffffff80 (00000000 00000000)
++ rldcr ffffffffffffffff, ffffffffffffffff, 63 => ffffffffffffffff (00000000 00000000)
++
++ rldic 0000000000000000, 0, 0 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 0, 7 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 0, 14 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 0, 21 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 0, 28 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 0, 35 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 0, 42 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 0, 49 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 0, 56 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 0, 63 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 7, 0 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 7, 7 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 7, 14 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 7, 21 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 7, 28 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 7, 35 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 7, 42 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 7, 49 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 7, 56 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 7, 63 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 14, 0 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 14, 7 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 14, 14 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 14, 21 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 14, 28 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 14, 35 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 14, 42 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 14, 49 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 14, 56 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 14, 63 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 21, 0 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 21, 7 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 21, 14 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 21, 21 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 21, 28 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 21, 35 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 21, 42 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 21, 49 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 21, 56 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 21, 63 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 28, 0 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 28, 7 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 28, 14 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 28, 21 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 28, 28 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 28, 35 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 28, 42 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 28, 49 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 28, 56 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 28, 63 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 35, 0 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 35, 7 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 35, 14 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 35, 21 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 35, 28 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 35, 35 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 35, 42 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 35, 49 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 35, 56 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 35, 63 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 42, 0 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 42, 7 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 42, 14 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 42, 21 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 42, 28 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 42, 35 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 42, 42 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 42, 49 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 42, 56 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 42, 63 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 49, 0 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 49, 7 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 49, 14 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 49, 21 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 49, 28 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 49, 35 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 49, 42 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 49, 49 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 49, 56 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 49, 63 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 56, 0 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 56, 7 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 56, 14 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 56, 21 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 56, 28 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 56, 35 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 56, 42 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 56, 49 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 56, 56 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 56, 63 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 63, 0 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 63, 7 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 63, 14 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 63, 21 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 63, 28 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 63, 35 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 63, 42 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 63, 49 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 63, 56 => 0000000000000000 (00000000 00000000)
++ rldic 0000000000000000, 63, 63 => 0000000000000000 (00000000 00000000)
++ rldic 0000001cbe991def, 0, 0 => 0000001cbe991def (00000000 00000000)
++ rldic 0000001cbe991def, 0, 7 => 0000001cbe991def (00000000 00000000)
++ rldic 0000001cbe991def, 0, 14 => 0000001cbe991def (00000000 00000000)
++ rldic 0000001cbe991def, 0, 21 => 0000001cbe991def (00000000 00000000)
++ rldic 0000001cbe991def, 0, 28 => 0000000cbe991def (00000000 00000000)
++ rldic 0000001cbe991def, 0, 35 => 000000001e991def (00000000 00000000)
++ rldic 0000001cbe991def, 0, 42 => 0000000000191def (00000000 00000000)
++ rldic 0000001cbe991def, 0, 49 => 0000000000001def (00000000 00000000)
++ rldic 0000001cbe991def, 0, 56 => 00000000000000ef (00000000 00000000)
++ rldic 0000001cbe991def, 0, 63 => 0000000000000001 (00000000 00000000)
++ rldic 0000001cbe991def, 7, 0 => 00000e5f4c8ef780 (00000000 00000000)
++ rldic 0000001cbe991def, 7, 7 => 00000e5f4c8ef780 (00000000 00000000)
++ rldic 0000001cbe991def, 7, 14 => 00000e5f4c8ef780 (00000000 00000000)
++ rldic 0000001cbe991def, 7, 21 => 0000065f4c8ef780 (00000000 00000000)
++ rldic 0000001cbe991def, 7, 28 => 0000000f4c8ef780 (00000000 00000000)
++ rldic 0000001cbe991def, 7, 35 => 000000000c8ef780 (00000000 00000000)
++ rldic 0000001cbe991def, 7, 42 => 00000000000ef780 (00000000 00000000)
++ rldic 0000001cbe991def, 7, 49 => 0000000000007780 (00000000 00000000)
++ rldic 0000001cbe991def, 7, 56 => 0000000000000080 (00000000 00000000)
++ rldic 0000001cbe991def, 7, 63 => 00000e5f4c8ef780 (00000000 00000000)
++ rldic 0000001cbe991def, 14, 0 => 00072fa6477bc000 (00000000 00000000)
++ rldic 0000001cbe991def, 14, 7 => 00072fa6477bc000 (00000000 00000000)
++ rldic 0000001cbe991def, 14, 14 => 00032fa6477bc000 (00000000 00000000)
++ rldic 0000001cbe991def, 14, 21 => 000007a6477bc000 (00000000 00000000)
++ rldic 0000001cbe991def, 14, 28 => 00000006477bc000 (00000000 00000000)
++ rldic 0000001cbe991def, 14, 35 => 00000000077bc000 (00000000 00000000)
++ rldic 0000001cbe991def, 14, 42 => 00000000003bc000 (00000000 00000000)
++ rldic 0000001cbe991def, 14, 49 => 0000000000004000 (00000000 00000000)
++ rldic 0000001cbe991def, 14, 56 => 00072fa6477bc000 (00000000 00000000)
++ rldic 0000001cbe991def, 14, 63 => 00072fa6477bc000 (00000000 00000000)
++ rldic 0000001cbe991def, 21, 0 => 0397d323bde00000 (00000000 00000000)
++ rldic 0000001cbe991def, 21, 7 => 0197d323bde00000 (00000000 00000000)
++ rldic 0000001cbe991def, 21, 14 => 0003d323bde00000 (00000000 00000000)
++ rldic 0000001cbe991def, 21, 21 => 00000323bde00000 (00000000 00000000)
++ rldic 0000001cbe991def, 21, 28 => 00000003bde00000 (00000000 00000000)
++ rldic 0000001cbe991def, 21, 35 => 000000001de00000 (00000000 00000000)
++ rldic 0000001cbe991def, 21, 42 => 0000000000200000 (00000000 00000000)
++ rldic 0000001cbe991def, 21, 49 => 0397d323bde00000 (00000000 00000000)
++ rldic 0000001cbe991def, 21, 56 => 0397d323bde00000 (00000000 00000000)
++ rldic 0000001cbe991def, 21, 63 => 0397d323bde00000 (00000000 00000000)
++ rldic 0000001cbe991def, 28, 0 => cbe991def0000000 (00000000 00000000)
++ rldic 0000001cbe991def, 28, 7 => 01e991def0000000 (00000000 00000000)
++ rldic 0000001cbe991def, 28, 14 => 000191def0000000 (00000000 00000000)
++ rldic 0000001cbe991def, 28, 21 => 000001def0000000 (00000000 00000000)
++ rldic 0000001cbe991def, 28, 28 => 0000000ef0000000 (00000000 00000000)
++ rldic 0000001cbe991def, 28, 35 => 0000000010000000 (00000000 00000000)
++ rldic 0000001cbe991def, 28, 42 => cbe991def0000001 (00000000 00000000)
++ rldic 0000001cbe991def, 28, 49 => cbe991def0000001 (00000000 00000000)
++ rldic 0000001cbe991def, 28, 56 => cbe991def0000001 (00000000 00000000)
++ rldic 0000001cbe991def, 28, 63 => cbe991def0000001 (00000000 00000000)
++ rldic 0000001cbe991def, 35, 0 => f4c8ef7800000000 (00000000 00000000)
++ rldic 0000001cbe991def, 35, 7 => 00c8ef7800000000 (00000000 00000000)
++ rldic 0000001cbe991def, 35, 14 => 0000ef7800000000 (00000000 00000000)
++ rldic 0000001cbe991def, 35, 21 => 0000077800000000 (00000000 00000000)
++ rldic 0000001cbe991def, 35, 28 => 0000000800000000 (00000000 00000000)
++ rldic 0000001cbe991def, 35, 35 => f4c8ef78000000e5 (00000000 00000000)
++ rldic 0000001cbe991def, 35, 42 => f4c8ef78000000e5 (00000000 00000000)
++ rldic 0000001cbe991def, 35, 49 => f4c8ef78000000e5 (00000000 00000000)
++ rldic 0000001cbe991def, 35, 56 => f4c8ef78000000e5 (00000000 00000000)
++ rldic 0000001cbe991def, 35, 63 => f4c8ef7800000001 (00000000 00000000)
++ rldic 0000001cbe991def, 42, 0 => 6477bc0000000000 (00000000 00000000)
++ rldic 0000001cbe991def, 42, 7 => 0077bc0000000000 (00000000 00000000)
++ rldic 0000001cbe991def, 42, 14 => 0003bc0000000000 (00000000 00000000)
++ rldic 0000001cbe991def, 42, 21 => 0000040000000000 (00000000 00000000)
++ rldic 0000001cbe991def, 42, 28 => 6477bc00000072fa (00000000 00000000)
++ rldic 0000001cbe991def, 42, 35 => 6477bc00000072fa (00000000 00000000)
++ rldic 0000001cbe991def, 42, 42 => 6477bc00000072fa (00000000 00000000)
++ rldic 0000001cbe991def, 42, 49 => 6477bc00000072fa (00000000 00000000)
++ rldic 0000001cbe991def, 42, 56 => 6477bc00000000fa (00000000 00000000)
++ rldic 0000001cbe991def, 42, 63 => 6477bc0000000000 (00000000 00000000)
++ rldic 0000001cbe991def, 49, 0 => 3bde000000000000 (00000000 00000000)
++ rldic 0000001cbe991def, 49, 7 => 01de000000000000 (00000000 00000000)
++ rldic 0000001cbe991def, 49, 14 => 0002000000000000 (00000000 00000000)
++ rldic 0000001cbe991def, 49, 21 => 3bde000000397d32 (00000000 00000000)
++ rldic 0000001cbe991def, 49, 28 => 3bde000000397d32 (00000000 00000000)
++ rldic 0000001cbe991def, 49, 35 => 3bde000000397d32 (00000000 00000000)
++ rldic 0000001cbe991def, 49, 42 => 3bde000000397d32 (00000000 00000000)
++ rldic 0000001cbe991def, 49, 49 => 3bde000000007d32 (00000000 00000000)
++ rldic 0000001cbe991def, 49, 56 => 3bde000000000032 (00000000 00000000)
++ rldic 0000001cbe991def, 49, 63 => 3bde000000000000 (00000000 00000000)
++ rldic 0000001cbe991def, 56, 0 => ef00000000000000 (00000000 00000000)
++ rldic 0000001cbe991def, 56, 7 => 0100000000000000 (00000000 00000000)
++ rldic 0000001cbe991def, 56, 14 => ef0000001cbe991d (00000000 00000000)
++ rldic 0000001cbe991def, 56, 21 => ef0000001cbe991d (00000000 00000000)
++ rldic 0000001cbe991def, 56, 28 => ef0000001cbe991d (00000000 00000000)
++ rldic 0000001cbe991def, 56, 35 => ef0000001cbe991d (00000000 00000000)
++ rldic 0000001cbe991def, 56, 42 => ef000000003e991d (00000000 00000000)
++ rldic 0000001cbe991def, 56, 49 => ef0000000000191d (00000000 00000000)
++ rldic 0000001cbe991def, 56, 56 => ef0000000000001d (00000000 00000000)
++ rldic 0000001cbe991def, 56, 63 => ef00000000000001 (00000000 00000000)
++ rldic 0000001cbe991def, 63, 0 => 8000000000000000 (00000000 00000000)
++ rldic 0000001cbe991def, 63, 7 => 8000000e5f4c8ef7 (00000000 00000000)
++ rldic 0000001cbe991def, 63, 14 => 8000000e5f4c8ef7 (00000000 00000000)
++ rldic 0000001cbe991def, 63, 21 => 8000000e5f4c8ef7 (00000000 00000000)
++ rldic 0000001cbe991def, 63, 28 => 8000000e5f4c8ef7 (00000000 00000000)
++ rldic 0000001cbe991def, 63, 35 => 800000001f4c8ef7 (00000000 00000000)
++ rldic 0000001cbe991def, 63, 42 => 80000000000c8ef7 (00000000 00000000)
++ rldic 0000001cbe991def, 63, 49 => 8000000000000ef7 (00000000 00000000)
++ rldic 0000001cbe991def, 63, 56 => 80000000000000f7 (00000000 00000000)
++ rldic 0000001cbe991def, 63, 63 => 8000000000000001 (00000000 00000000)
++ rldic ffffffffffffffff, 0, 0 => ffffffffffffffff (00000000 00000000)
++ rldic ffffffffffffffff, 0, 7 => 01ffffffffffffff (00000000 00000000)
++ rldic ffffffffffffffff, 0, 14 => 0003ffffffffffff (00000000 00000000)
++ rldic ffffffffffffffff, 0, 21 => 000007ffffffffff (00000000 00000000)
++ rldic ffffffffffffffff, 0, 28 => 0000000fffffffff (00000000 00000000)
++ rldic ffffffffffffffff, 0, 35 => 000000001fffffff (00000000 00000000)
++ rldic ffffffffffffffff, 0, 42 => 00000000003fffff (00000000 00000000)
++ rldic ffffffffffffffff, 0, 49 => 0000000000007fff (00000000 00000000)
++ rldic ffffffffffffffff, 0, 56 => 00000000000000ff (00000000 00000000)
++ rldic ffffffffffffffff, 0, 63 => 0000000000000001 (00000000 00000000)
++ rldic ffffffffffffffff, 7, 0 => ffffffffffffff80 (00000000 00000000)
++ rldic ffffffffffffffff, 7, 7 => 01ffffffffffff80 (00000000 00000000)
++ rldic ffffffffffffffff, 7, 14 => 0003ffffffffff80 (00000000 00000000)
++ rldic ffffffffffffffff, 7, 21 => 000007ffffffff80 (00000000 00000000)
++ rldic ffffffffffffffff, 7, 28 => 0000000fffffff80 (00000000 00000000)
++ rldic ffffffffffffffff, 7, 35 => 000000001fffff80 (00000000 00000000)
++ rldic ffffffffffffffff, 7, 42 => 00000000003fff80 (00000000 00000000)
++ rldic ffffffffffffffff, 7, 49 => 0000000000007f80 (00000000 00000000)
++ rldic ffffffffffffffff, 7, 56 => 0000000000000080 (00000000 00000000)
++ rldic ffffffffffffffff, 7, 63 => ffffffffffffff81 (00000000 00000000)
++ rldic ffffffffffffffff, 14, 0 => ffffffffffffc000 (00000000 00000000)
++ rldic ffffffffffffffff, 14, 7 => 01ffffffffffc000 (00000000 00000000)
++ rldic ffffffffffffffff, 14, 14 => 0003ffffffffc000 (00000000 00000000)
++ rldic ffffffffffffffff, 14, 21 => 000007ffffffc000 (00000000 00000000)
++ rldic ffffffffffffffff, 14, 28 => 0000000fffffc000 (00000000 00000000)
++ rldic ffffffffffffffff, 14, 35 => 000000001fffc000 (00000000 00000000)
++ rldic ffffffffffffffff, 14, 42 => 00000000003fc000 (00000000 00000000)
++ rldic ffffffffffffffff, 14, 49 => 0000000000004000 (00000000 00000000)
++ rldic ffffffffffffffff, 14, 56 => ffffffffffffc0ff (00000000 00000000)
++ rldic ffffffffffffffff, 14, 63 => ffffffffffffc001 (00000000 00000000)
++ rldic ffffffffffffffff, 21, 0 => ffffffffffe00000 (00000000 00000000)
++ rldic ffffffffffffffff, 21, 7 => 01ffffffffe00000 (00000000 00000000)
++ rldic ffffffffffffffff, 21, 14 => 0003ffffffe00000 (00000000 00000000)
++ rldic ffffffffffffffff, 21, 21 => 000007ffffe00000 (00000000 00000000)
++ rldic ffffffffffffffff, 21, 28 => 0000000fffe00000 (00000000 00000000)
++ rldic ffffffffffffffff, 21, 35 => 000000001fe00000 (00000000 00000000)
++ rldic ffffffffffffffff, 21, 42 => 0000000000200000 (00000000 00000000)
++ rldic ffffffffffffffff, 21, 49 => ffffffffffe07fff (00000000 00000000)
++ rldic ffffffffffffffff, 21, 56 => ffffffffffe000ff (00000000 00000000)
++ rldic ffffffffffffffff, 21, 63 => ffffffffffe00001 (00000000 00000000)
++ rldic ffffffffffffffff, 28, 0 => fffffffff0000000 (00000000 00000000)
++ rldic ffffffffffffffff, 28, 7 => 01fffffff0000000 (00000000 00000000)
++ rldic ffffffffffffffff, 28, 14 => 0003fffff0000000 (00000000 00000000)
++ rldic ffffffffffffffff, 28, 21 => 000007fff0000000 (00000000 00000000)
++ rldic ffffffffffffffff, 28, 28 => 0000000ff0000000 (00000000 00000000)
++ rldic ffffffffffffffff, 28, 35 => 0000000010000000 (00000000 00000000)
++ rldic ffffffffffffffff, 28, 42 => fffffffff03fffff (00000000 00000000)
++ rldic ffffffffffffffff, 28, 49 => fffffffff0007fff (00000000 00000000)
++ rldic ffffffffffffffff, 28, 56 => fffffffff00000ff (00000000 00000000)
++ rldic ffffffffffffffff, 28, 63 => fffffffff0000001 (00000000 00000000)
++ rldic ffffffffffffffff, 35, 0 => fffffff800000000 (00000000 00000000)
++ rldic ffffffffffffffff, 35, 7 => 01fffff800000000 (00000000 00000000)
++ rldic ffffffffffffffff, 35, 14 => 0003fff800000000 (00000000 00000000)
++ rldic ffffffffffffffff, 35, 21 => 000007f800000000 (00000000 00000000)
++ rldic ffffffffffffffff, 35, 28 => 0000000800000000 (00000000 00000000)
++ rldic ffffffffffffffff, 35, 35 => fffffff81fffffff (00000000 00000000)
++ rldic ffffffffffffffff, 35, 42 => fffffff8003fffff (00000000 00000000)
++ rldic ffffffffffffffff, 35, 49 => fffffff800007fff (00000000 00000000)
++ rldic ffffffffffffffff, 35, 56 => fffffff8000000ff (00000000 00000000)
++ rldic ffffffffffffffff, 35, 63 => fffffff800000001 (00000000 00000000)
++ rldic ffffffffffffffff, 42, 0 => fffffc0000000000 (00000000 00000000)
++ rldic ffffffffffffffff, 42, 7 => 01fffc0000000000 (00000000 00000000)
++ rldic ffffffffffffffff, 42, 14 => 0003fc0000000000 (00000000 00000000)
++ rldic ffffffffffffffff, 42, 21 => 0000040000000000 (00000000 00000000)
++ rldic ffffffffffffffff, 42, 28 => fffffc0fffffffff (00000000 00000000)
++ rldic ffffffffffffffff, 42, 35 => fffffc001fffffff (00000000 00000000)
++ rldic ffffffffffffffff, 42, 42 => fffffc00003fffff (00000000 00000000)
++ rldic ffffffffffffffff, 42, 49 => fffffc0000007fff (00000000 00000000)
++ rldic ffffffffffffffff, 42, 56 => fffffc00000000ff (00000000 00000000)
++ rldic ffffffffffffffff, 42, 63 => fffffc0000000001 (00000000 00000000)
++ rldic ffffffffffffffff, 49, 0 => fffe000000000000 (00000000 00000000)
++ rldic ffffffffffffffff, 49, 7 => 01fe000000000000 (00000000 00000000)
++ rldic ffffffffffffffff, 49, 14 => 0002000000000000 (00000000 00000000)
++ rldic ffffffffffffffff, 49, 21 => fffe07ffffffffff (00000000 00000000)
++ rldic ffffffffffffffff, 49, 28 => fffe000fffffffff (00000000 00000000)
++ rldic ffffffffffffffff, 49, 35 => fffe00001fffffff (00000000 00000000)
++ rldic ffffffffffffffff, 49, 42 => fffe0000003fffff (00000000 00000000)
++ rldic ffffffffffffffff, 49, 49 => fffe000000007fff (00000000 00000000)
++ rldic ffffffffffffffff, 49, 56 => fffe0000000000ff (00000000 00000000)
++ rldic ffffffffffffffff, 49, 63 => fffe000000000001 (00000000 00000000)
++ rldic ffffffffffffffff, 56, 0 => ff00000000000000 (00000000 00000000)
++ rldic ffffffffffffffff, 56, 7 => 0100000000000000 (00000000 00000000)
++ rldic ffffffffffffffff, 56, 14 => ff03ffffffffffff (00000000 00000000)
++ rldic ffffffffffffffff, 56, 21 => ff0007ffffffffff (00000000 00000000)
++ rldic ffffffffffffffff, 56, 28 => ff00000fffffffff (00000000 00000000)
++ rldic ffffffffffffffff, 56, 35 => ff0000001fffffff (00000000 00000000)
++ rldic ffffffffffffffff, 56, 42 => ff000000003fffff (00000000 00000000)
++ rldic ffffffffffffffff, 56, 49 => ff00000000007fff (00000000 00000000)
++ rldic ffffffffffffffff, 56, 56 => ff000000000000ff (00000000 00000000)
++ rldic ffffffffffffffff, 56, 63 => ff00000000000001 (00000000 00000000)
++ rldic ffffffffffffffff, 63, 0 => 8000000000000000 (00000000 00000000)
++ rldic ffffffffffffffff, 63, 7 => 81ffffffffffffff (00000000 00000000)
++ rldic ffffffffffffffff, 63, 14 => 8003ffffffffffff (00000000 00000000)
++ rldic ffffffffffffffff, 63, 21 => 800007ffffffffff (00000000 00000000)
++ rldic ffffffffffffffff, 63, 28 => 8000000fffffffff (00000000 00000000)
++ rldic ffffffffffffffff, 63, 35 => 800000001fffffff (00000000 00000000)
++ rldic ffffffffffffffff, 63, 42 => 80000000003fffff (00000000 00000000)
++ rldic ffffffffffffffff, 63, 49 => 8000000000007fff (00000000 00000000)
++ rldic ffffffffffffffff, 63, 56 => 80000000000000ff (00000000 00000000)
++ rldic ffffffffffffffff, 63, 63 => 8000000000000001 (00000000 00000000)
++
++ rldicl 0000000000000000, 0, 0 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 0, 7 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 0, 14 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 0, 21 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 0, 28 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 0, 35 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 0, 42 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 0, 49 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 0, 56 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 0, 63 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 7, 0 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 7, 7 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 7, 14 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 7, 21 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 7, 28 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 7, 35 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 7, 42 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 7, 49 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 7, 56 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 7, 63 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 14, 0 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 14, 7 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 14, 14 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 14, 21 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 14, 28 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 14, 35 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 14, 42 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 14, 49 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 14, 56 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 14, 63 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 21, 0 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 21, 7 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 21, 14 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 21, 21 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 21, 28 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 21, 35 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 21, 42 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 21, 49 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 21, 56 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 21, 63 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 28, 0 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 28, 7 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 28, 14 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 28, 21 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 28, 28 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 28, 35 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 28, 42 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 28, 49 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 28, 56 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 28, 63 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 35, 0 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 35, 7 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 35, 14 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 35, 21 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 35, 28 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 35, 35 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 35, 42 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 35, 49 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 35, 56 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 35, 63 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 42, 0 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 42, 7 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 42, 14 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 42, 21 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 42, 28 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 42, 35 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 42, 42 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 42, 49 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 42, 56 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 42, 63 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 49, 0 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 49, 7 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 49, 14 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 49, 21 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 49, 28 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 49, 35 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 49, 42 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 49, 49 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 49, 56 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 49, 63 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 56, 0 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 56, 7 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 56, 14 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 56, 21 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 56, 28 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 56, 35 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 56, 42 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 56, 49 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 56, 56 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 56, 63 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 63, 0 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 63, 7 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 63, 14 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 63, 21 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 63, 28 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 63, 35 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 63, 42 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 63, 49 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 63, 56 => 0000000000000000 (00000000 00000000)
++ rldicl 0000000000000000, 63, 63 => 0000000000000000 (00000000 00000000)
++ rldicl 0000001cbe991def, 0, 0 => 0000001cbe991def (00000000 00000000)
++ rldicl 0000001cbe991def, 0, 7 => 0000001cbe991def (00000000 00000000)
++ rldicl 0000001cbe991def, 0, 14 => 0000001cbe991def (00000000 00000000)
++ rldicl 0000001cbe991def, 0, 21 => 0000001cbe991def (00000000 00000000)
++ rldicl 0000001cbe991def, 0, 28 => 0000000cbe991def (00000000 00000000)
++ rldicl 0000001cbe991def, 0, 35 => 000000001e991def (00000000 00000000)
++ rldicl 0000001cbe991def, 0, 42 => 0000000000191def (00000000 00000000)
++ rldicl 0000001cbe991def, 0, 49 => 0000000000001def (00000000 00000000)
++ rldicl 0000001cbe991def, 0, 56 => 00000000000000ef (00000000 00000000)
++ rldicl 0000001cbe991def, 0, 63 => 0000000000000001 (00000000 00000000)
++ rldicl 0000001cbe991def, 7, 0 => 00000e5f4c8ef780 (00000000 00000000)
++ rldicl 0000001cbe991def, 7, 7 => 00000e5f4c8ef780 (00000000 00000000)
++ rldicl 0000001cbe991def, 7, 14 => 00000e5f4c8ef780 (00000000 00000000)
++ rldicl 0000001cbe991def, 7, 21 => 0000065f4c8ef780 (00000000 00000000)
++ rldicl 0000001cbe991def, 7, 28 => 0000000f4c8ef780 (00000000 00000000)
++ rldicl 0000001cbe991def, 7, 35 => 000000000c8ef780 (00000000 00000000)
++ rldicl 0000001cbe991def, 7, 42 => 00000000000ef780 (00000000 00000000)
++ rldicl 0000001cbe991def, 7, 49 => 0000000000007780 (00000000 00000000)
++ rldicl 0000001cbe991def, 7, 56 => 0000000000000080 (00000000 00000000)
++ rldicl 0000001cbe991def, 7, 63 => 0000000000000000 (00000000 00000000)
++ rldicl 0000001cbe991def, 14, 0 => 00072fa6477bc000 (00000000 00000000)
++ rldicl 0000001cbe991def, 14, 7 => 00072fa6477bc000 (00000000 00000000)
++ rldicl 0000001cbe991def, 14, 14 => 00032fa6477bc000 (00000000 00000000)
++ rldicl 0000001cbe991def, 14, 21 => 000007a6477bc000 (00000000 00000000)
++ rldicl 0000001cbe991def, 14, 28 => 00000006477bc000 (00000000 00000000)
++ rldicl 0000001cbe991def, 14, 35 => 00000000077bc000 (00000000 00000000)
++ rldicl 0000001cbe991def, 14, 42 => 00000000003bc000 (00000000 00000000)
++ rldicl 0000001cbe991def, 14, 49 => 0000000000004000 (00000000 00000000)
++ rldicl 0000001cbe991def, 14, 56 => 0000000000000000 (00000000 00000000)
++ rldicl 0000001cbe991def, 14, 63 => 0000000000000000 (00000000 00000000)
++ rldicl 0000001cbe991def, 21, 0 => 0397d323bde00000 (00000000 00000000)
++ rldicl 0000001cbe991def, 21, 7 => 0197d323bde00000 (00000000 00000000)
++ rldicl 0000001cbe991def, 21, 14 => 0003d323bde00000 (00000000 00000000)
++ rldicl 0000001cbe991def, 21, 21 => 00000323bde00000 (00000000 00000000)
++ rldicl 0000001cbe991def, 21, 28 => 00000003bde00000 (00000000 00000000)
++ rldicl 0000001cbe991def, 21, 35 => 000000001de00000 (00000000 00000000)
++ rldicl 0000001cbe991def, 21, 42 => 0000000000200000 (00000000 00000000)
++ rldicl 0000001cbe991def, 21, 49 => 0000000000000000 (00000000 00000000)
++ rldicl 0000001cbe991def, 21, 56 => 0000000000000000 (00000000 00000000)
++ rldicl 0000001cbe991def, 21, 63 => 0000000000000000 (00000000 00000000)
++ rldicl 0000001cbe991def, 28, 0 => cbe991def0000001 (00000000 00000000)
++ rldicl 0000001cbe991def, 28, 7 => 01e991def0000001 (00000000 00000000)
++ rldicl 0000001cbe991def, 28, 14 => 000191def0000001 (00000000 00000000)
++ rldicl 0000001cbe991def, 28, 21 => 000001def0000001 (00000000 00000000)
++ rldicl 0000001cbe991def, 28, 28 => 0000000ef0000001 (00000000 00000000)
++ rldicl 0000001cbe991def, 28, 35 => 0000000010000001 (00000000 00000000)
++ rldicl 0000001cbe991def, 28, 42 => 0000000000000001 (00000000 00000000)
++ rldicl 0000001cbe991def, 28, 49 => 0000000000000001 (00000000 00000000)
++ rldicl 0000001cbe991def, 28, 56 => 0000000000000001 (00000000 00000000)
++ rldicl 0000001cbe991def, 28, 63 => 0000000000000001 (00000000 00000000)
++ rldicl 0000001cbe991def, 35, 0 => f4c8ef78000000e5 (00000000 00000000)
++ rldicl 0000001cbe991def, 35, 7 => 00c8ef78000000e5 (00000000 00000000)
++ rldicl 0000001cbe991def, 35, 14 => 0000ef78000000e5 (00000000 00000000)
++ rldicl 0000001cbe991def, 35, 21 => 00000778000000e5 (00000000 00000000)
++ rldicl 0000001cbe991def, 35, 28 => 00000008000000e5 (00000000 00000000)
++ rldicl 0000001cbe991def, 35, 35 => 00000000000000e5 (00000000 00000000)
++ rldicl 0000001cbe991def, 35, 42 => 00000000000000e5 (00000000 00000000)
++ rldicl 0000001cbe991def, 35, 49 => 00000000000000e5 (00000000 00000000)
++ rldicl 0000001cbe991def, 35, 56 => 00000000000000e5 (00000000 00000000)
++ rldicl 0000001cbe991def, 35, 63 => 0000000000000001 (00000000 00000000)
++ rldicl 0000001cbe991def, 42, 0 => 6477bc00000072fa (00000000 00000000)
++ rldicl 0000001cbe991def, 42, 7 => 0077bc00000072fa (00000000 00000000)
++ rldicl 0000001cbe991def, 42, 14 => 0003bc00000072fa (00000000 00000000)
++ rldicl 0000001cbe991def, 42, 21 => 00000400000072fa (00000000 00000000)
++ rldicl 0000001cbe991def, 42, 28 => 00000000000072fa (00000000 00000000)
++ rldicl 0000001cbe991def, 42, 35 => 00000000000072fa (00000000 00000000)
++ rldicl 0000001cbe991def, 42, 42 => 00000000000072fa (00000000 00000000)
++ rldicl 0000001cbe991def, 42, 49 => 00000000000072fa (00000000 00000000)
++ rldicl 0000001cbe991def, 42, 56 => 00000000000000fa (00000000 00000000)
++ rldicl 0000001cbe991def, 42, 63 => 0000000000000000 (00000000 00000000)
++ rldicl 0000001cbe991def, 49, 0 => 3bde000000397d32 (00000000 00000000)
++ rldicl 0000001cbe991def, 49, 7 => 01de000000397d32 (00000000 00000000)
++ rldicl 0000001cbe991def, 49, 14 => 0002000000397d32 (00000000 00000000)
++ rldicl 0000001cbe991def, 49, 21 => 0000000000397d32 (00000000 00000000)
++ rldicl 0000001cbe991def, 49, 28 => 0000000000397d32 (00000000 00000000)
++ rldicl 0000001cbe991def, 49, 35 => 0000000000397d32 (00000000 00000000)
++ rldicl 0000001cbe991def, 49, 42 => 0000000000397d32 (00000000 00000000)
++ rldicl 0000001cbe991def, 49, 49 => 0000000000007d32 (00000000 00000000)
++ rldicl 0000001cbe991def, 49, 56 => 0000000000000032 (00000000 00000000)
++ rldicl 0000001cbe991def, 49, 63 => 0000000000000000 (00000000 00000000)
++ rldicl 0000001cbe991def, 56, 0 => ef0000001cbe991d (00000000 00000000)
++ rldicl 0000001cbe991def, 56, 7 => 010000001cbe991d (00000000 00000000)
++ rldicl 0000001cbe991def, 56, 14 => 000000001cbe991d (00000000 00000000)
++ rldicl 0000001cbe991def, 56, 21 => 000000001cbe991d (00000000 00000000)
++ rldicl 0000001cbe991def, 56, 28 => 000000001cbe991d (00000000 00000000)
++ rldicl 0000001cbe991def, 56, 35 => 000000001cbe991d (00000000 00000000)
++ rldicl 0000001cbe991def, 56, 42 => 00000000003e991d (00000000 00000000)
++ rldicl 0000001cbe991def, 56, 49 => 000000000000191d (00000000 00000000)
++ rldicl 0000001cbe991def, 56, 56 => 000000000000001d (00000000 00000000)
++ rldicl 0000001cbe991def, 56, 63 => 0000000000000001 (00000000 00000000)
++ rldicl 0000001cbe991def, 63, 0 => 8000000e5f4c8ef7 (00000000 00000000)
++ rldicl 0000001cbe991def, 63, 7 => 0000000e5f4c8ef7 (00000000 00000000)
++ rldicl 0000001cbe991def, 63, 14 => 0000000e5f4c8ef7 (00000000 00000000)
++ rldicl 0000001cbe991def, 63, 21 => 0000000e5f4c8ef7 (00000000 00000000)
++ rldicl 0000001cbe991def, 63, 28 => 0000000e5f4c8ef7 (00000000 00000000)
++ rldicl 0000001cbe991def, 63, 35 => 000000001f4c8ef7 (00000000 00000000)
++ rldicl 0000001cbe991def, 63, 42 => 00000000000c8ef7 (00000000 00000000)
++ rldicl 0000001cbe991def, 63, 49 => 0000000000000ef7 (00000000 00000000)
++ rldicl 0000001cbe991def, 63, 56 => 00000000000000f7 (00000000 00000000)
++ rldicl 0000001cbe991def, 63, 63 => 0000000000000001 (00000000 00000000)
++ rldicl ffffffffffffffff, 0, 0 => ffffffffffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 0, 7 => 01ffffffffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 0, 14 => 0003ffffffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 0, 21 => 000007ffffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 0, 28 => 0000000fffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 0, 35 => 000000001fffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 0, 42 => 00000000003fffff (00000000 00000000)
++ rldicl ffffffffffffffff, 0, 49 => 0000000000007fff (00000000 00000000)
++ rldicl ffffffffffffffff, 0, 56 => 00000000000000ff (00000000 00000000)
++ rldicl ffffffffffffffff, 0, 63 => 0000000000000001 (00000000 00000000)
++ rldicl ffffffffffffffff, 7, 0 => ffffffffffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 7, 7 => 01ffffffffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 7, 14 => 0003ffffffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 7, 21 => 000007ffffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 7, 28 => 0000000fffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 7, 35 => 000000001fffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 7, 42 => 00000000003fffff (00000000 00000000)
++ rldicl ffffffffffffffff, 7, 49 => 0000000000007fff (00000000 00000000)
++ rldicl ffffffffffffffff, 7, 56 => 00000000000000ff (00000000 00000000)
++ rldicl ffffffffffffffff, 7, 63 => 0000000000000001 (00000000 00000000)
++ rldicl ffffffffffffffff, 14, 0 => ffffffffffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 14, 7 => 01ffffffffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 14, 14 => 0003ffffffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 14, 21 => 000007ffffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 14, 28 => 0000000fffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 14, 35 => 000000001fffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 14, 42 => 00000000003fffff (00000000 00000000)
++ rldicl ffffffffffffffff, 14, 49 => 0000000000007fff (00000000 00000000)
++ rldicl ffffffffffffffff, 14, 56 => 00000000000000ff (00000000 00000000)
++ rldicl ffffffffffffffff, 14, 63 => 0000000000000001 (00000000 00000000)
++ rldicl ffffffffffffffff, 21, 0 => ffffffffffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 21, 7 => 01ffffffffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 21, 14 => 0003ffffffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 21, 21 => 000007ffffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 21, 28 => 0000000fffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 21, 35 => 000000001fffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 21, 42 => 00000000003fffff (00000000 00000000)
++ rldicl ffffffffffffffff, 21, 49 => 0000000000007fff (00000000 00000000)
++ rldicl ffffffffffffffff, 21, 56 => 00000000000000ff (00000000 00000000)
++ rldicl ffffffffffffffff, 21, 63 => 0000000000000001 (00000000 00000000)
++ rldicl ffffffffffffffff, 28, 0 => ffffffffffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 28, 7 => 01ffffffffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 28, 14 => 0003ffffffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 28, 21 => 000007ffffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 28, 28 => 0000000fffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 28, 35 => 000000001fffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 28, 42 => 00000000003fffff (00000000 00000000)
++ rldicl ffffffffffffffff, 28, 49 => 0000000000007fff (00000000 00000000)
++ rldicl ffffffffffffffff, 28, 56 => 00000000000000ff (00000000 00000000)
++ rldicl ffffffffffffffff, 28, 63 => 0000000000000001 (00000000 00000000)
++ rldicl ffffffffffffffff, 35, 0 => ffffffffffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 35, 7 => 01ffffffffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 35, 14 => 0003ffffffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 35, 21 => 000007ffffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 35, 28 => 0000000fffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 35, 35 => 000000001fffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 35, 42 => 00000000003fffff (00000000 00000000)
++ rldicl ffffffffffffffff, 35, 49 => 0000000000007fff (00000000 00000000)
++ rldicl ffffffffffffffff, 35, 56 => 00000000000000ff (00000000 00000000)
++ rldicl ffffffffffffffff, 35, 63 => 0000000000000001 (00000000 00000000)
++ rldicl ffffffffffffffff, 42, 0 => ffffffffffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 42, 7 => 01ffffffffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 42, 14 => 0003ffffffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 42, 21 => 000007ffffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 42, 28 => 0000000fffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 42, 35 => 000000001fffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 42, 42 => 00000000003fffff (00000000 00000000)
++ rldicl ffffffffffffffff, 42, 49 => 0000000000007fff (00000000 00000000)
++ rldicl ffffffffffffffff, 42, 56 => 00000000000000ff (00000000 00000000)
++ rldicl ffffffffffffffff, 42, 63 => 0000000000000001 (00000000 00000000)
++ rldicl ffffffffffffffff, 49, 0 => ffffffffffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 49, 7 => 01ffffffffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 49, 14 => 0003ffffffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 49, 21 => 000007ffffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 49, 28 => 0000000fffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 49, 35 => 000000001fffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 49, 42 => 00000000003fffff (00000000 00000000)
++ rldicl ffffffffffffffff, 49, 49 => 0000000000007fff (00000000 00000000)
++ rldicl ffffffffffffffff, 49, 56 => 00000000000000ff (00000000 00000000)
++ rldicl ffffffffffffffff, 49, 63 => 0000000000000001 (00000000 00000000)
++ rldicl ffffffffffffffff, 56, 0 => ffffffffffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 56, 7 => 01ffffffffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 56, 14 => 0003ffffffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 56, 21 => 000007ffffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 56, 28 => 0000000fffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 56, 35 => 000000001fffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 56, 42 => 00000000003fffff (00000000 00000000)
++ rldicl ffffffffffffffff, 56, 49 => 0000000000007fff (00000000 00000000)
++ rldicl ffffffffffffffff, 56, 56 => 00000000000000ff (00000000 00000000)
++ rldicl ffffffffffffffff, 56, 63 => 0000000000000001 (00000000 00000000)
++ rldicl ffffffffffffffff, 63, 0 => ffffffffffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 63, 7 => 01ffffffffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 63, 14 => 0003ffffffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 63, 21 => 000007ffffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 63, 28 => 0000000fffffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 63, 35 => 000000001fffffff (00000000 00000000)
++ rldicl ffffffffffffffff, 63, 42 => 00000000003fffff (00000000 00000000)
++ rldicl ffffffffffffffff, 63, 49 => 0000000000007fff (00000000 00000000)
++ rldicl ffffffffffffffff, 63, 56 => 00000000000000ff (00000000 00000000)
++ rldicl ffffffffffffffff, 63, 63 => 0000000000000001 (00000000 00000000)
++
++ rldicr 0000000000000000, 0, 0 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 0, 7 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 0, 14 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 0, 21 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 0, 28 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 0, 35 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 0, 42 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 0, 49 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 0, 56 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 0, 63 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 7, 0 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 7, 7 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 7, 14 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 7, 21 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 7, 28 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 7, 35 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 7, 42 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 7, 49 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 7, 56 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 7, 63 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 14, 0 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 14, 7 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 14, 14 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 14, 21 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 14, 28 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 14, 35 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 14, 42 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 14, 49 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 14, 56 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 14, 63 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 21, 0 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 21, 7 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 21, 14 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 21, 21 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 21, 28 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 21, 35 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 21, 42 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 21, 49 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 21, 56 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 21, 63 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 28, 0 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 28, 7 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 28, 14 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 28, 21 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 28, 28 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 28, 35 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 28, 42 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 28, 49 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 28, 56 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 28, 63 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 35, 0 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 35, 7 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 35, 14 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 35, 21 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 35, 28 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 35, 35 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 35, 42 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 35, 49 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 35, 56 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 35, 63 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 42, 0 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 42, 7 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 42, 14 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 42, 21 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 42, 28 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 42, 35 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 42, 42 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 42, 49 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 42, 56 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 42, 63 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 49, 0 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 49, 7 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 49, 14 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 49, 21 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 49, 28 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 49, 35 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 49, 42 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 49, 49 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 49, 56 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 49, 63 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 56, 0 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 56, 7 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 56, 14 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 56, 21 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 56, 28 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 56, 35 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 56, 42 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 56, 49 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 56, 56 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 56, 63 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 63, 0 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 63, 7 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 63, 14 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 63, 21 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 63, 28 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 63, 35 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 63, 42 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 63, 49 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 63, 56 => 0000000000000000 (00000000 00000000)
++ rldicr 0000000000000000, 63, 63 => 0000000000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 0, 0 => 0000000000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 0, 7 => 0000000000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 0, 14 => 0000000000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 0, 21 => 0000000000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 0, 28 => 0000001800000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 0, 35 => 0000001cb0000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 0, 42 => 0000001cbe800000 (00000000 00000000)
++ rldicr 0000001cbe991def, 0, 49 => 0000001cbe990000 (00000000 00000000)
++ rldicr 0000001cbe991def, 0, 56 => 0000001cbe991d80 (00000000 00000000)
++ rldicr 0000001cbe991def, 0, 63 => 0000001cbe991def (00000000 00000000)
++ rldicr 0000001cbe991def, 7, 0 => 0000000000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 7, 7 => 0000000000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 7, 14 => 0000000000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 7, 21 => 00000c0000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 7, 28 => 00000e5800000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 7, 35 => 00000e5f40000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 7, 42 => 00000e5f4c800000 (00000000 00000000)
++ rldicr 0000001cbe991def, 7, 49 => 00000e5f4c8ec000 (00000000 00000000)
++ rldicr 0000001cbe991def, 7, 56 => 00000e5f4c8ef780 (00000000 00000000)
++ rldicr 0000001cbe991def, 7, 63 => 00000e5f4c8ef780 (00000000 00000000)
++ rldicr 0000001cbe991def, 14, 0 => 0000000000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 14, 7 => 0000000000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 14, 14 => 0006000000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 14, 21 => 00072c0000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 14, 28 => 00072fa000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 14, 35 => 00072fa640000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 14, 42 => 00072fa647600000 (00000000 00000000)
++ rldicr 0000001cbe991def, 14, 49 => 00072fa6477bc000 (00000000 00000000)
++ rldicr 0000001cbe991def, 14, 56 => 00072fa6477bc000 (00000000 00000000)
++ rldicr 0000001cbe991def, 14, 63 => 00072fa6477bc000 (00000000 00000000)
++ rldicr 0000001cbe991def, 21, 0 => 0000000000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 21, 7 => 0300000000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 21, 14 => 0396000000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 21, 21 => 0397d00000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 21, 28 => 0397d32000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 21, 35 => 0397d323b0000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 21, 42 => 0397d323bde00000 (00000000 00000000)
++ rldicr 0000001cbe991def, 21, 49 => 0397d323bde00000 (00000000 00000000)
++ rldicr 0000001cbe991def, 21, 56 => 0397d323bde00000 (00000000 00000000)
++ rldicr 0000001cbe991def, 21, 63 => 0397d323bde00000 (00000000 00000000)
++ rldicr 0000001cbe991def, 28, 0 => 8000000000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 28, 7 => cb00000000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 28, 14 => cbe8000000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 28, 21 => cbe9900000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 28, 28 => cbe991d800000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 28, 35 => cbe991def0000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 28, 42 => cbe991def0000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 28, 49 => cbe991def0000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 28, 56 => cbe991def0000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 28, 63 => cbe991def0000001 (00000000 00000000)
++ rldicr 0000001cbe991def, 35, 0 => 8000000000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 35, 7 => f400000000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 35, 14 => f4c8000000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 35, 21 => f4c8ec0000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 35, 28 => f4c8ef7800000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 35, 35 => f4c8ef7800000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 35, 42 => f4c8ef7800000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 35, 49 => f4c8ef7800000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 35, 56 => f4c8ef7800000080 (00000000 00000000)
++ rldicr 0000001cbe991def, 35, 63 => f4c8ef78000000e5 (00000000 00000000)
++ rldicr 0000001cbe991def, 42, 0 => 0000000000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 42, 7 => 6400000000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 42, 14 => 6476000000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 42, 21 => 6477bc0000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 42, 28 => 6477bc0000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 42, 35 => 6477bc0000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 42, 42 => 6477bc0000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 42, 49 => 6477bc0000004000 (00000000 00000000)
++ rldicr 0000001cbe991def, 42, 56 => 6477bc0000007280 (00000000 00000000)
++ rldicr 0000001cbe991def, 42, 63 => 6477bc00000072fa (00000000 00000000)
++ rldicr 0000001cbe991def, 49, 0 => 0000000000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 49, 7 => 3b00000000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 49, 14 => 3bde000000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 49, 21 => 3bde000000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 49, 28 => 3bde000000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 49, 35 => 3bde000000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 49, 42 => 3bde000000200000 (00000000 00000000)
++ rldicr 0000001cbe991def, 49, 49 => 3bde000000394000 (00000000 00000000)
++ rldicr 0000001cbe991def, 49, 56 => 3bde000000397d00 (00000000 00000000)
++ rldicr 0000001cbe991def, 49, 63 => 3bde000000397d32 (00000000 00000000)
++ rldicr 0000001cbe991def, 56, 0 => 8000000000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 56, 7 => ef00000000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 56, 14 => ef00000000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 56, 21 => ef00000000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 56, 28 => ef00000000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 56, 35 => ef00000010000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 56, 42 => ef0000001ca00000 (00000000 00000000)
++ rldicr 0000001cbe991def, 56, 49 => ef0000001cbe8000 (00000000 00000000)
++ rldicr 0000001cbe991def, 56, 56 => ef0000001cbe9900 (00000000 00000000)
++ rldicr 0000001cbe991def, 56, 63 => ef0000001cbe991d (00000000 00000000)
++ rldicr 0000001cbe991def, 63, 0 => 8000000000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 63, 7 => 8000000000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 63, 14 => 8000000000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 63, 21 => 8000000000000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 63, 28 => 8000000800000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 63, 35 => 8000000e50000000 (00000000 00000000)
++ rldicr 0000001cbe991def, 63, 42 => 8000000e5f400000 (00000000 00000000)
++ rldicr 0000001cbe991def, 63, 49 => 8000000e5f4c8000 (00000000 00000000)
++ rldicr 0000001cbe991def, 63, 56 => 8000000e5f4c8e80 (00000000 00000000)
++ rldicr 0000001cbe991def, 63, 63 => 8000000e5f4c8ef7 (00000000 00000000)
++ rldicr ffffffffffffffff, 0, 0 => 8000000000000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 0, 7 => ff00000000000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 0, 14 => fffe000000000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 0, 21 => fffffc0000000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 0, 28 => fffffff800000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 0, 35 => fffffffff0000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 0, 42 => ffffffffffe00000 (00000000 00000000)
++ rldicr ffffffffffffffff, 0, 49 => ffffffffffffc000 (00000000 00000000)
++ rldicr ffffffffffffffff, 0, 56 => ffffffffffffff80 (00000000 00000000)
++ rldicr ffffffffffffffff, 0, 63 => ffffffffffffffff (00000000 00000000)
++ rldicr ffffffffffffffff, 7, 0 => 8000000000000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 7, 7 => ff00000000000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 7, 14 => fffe000000000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 7, 21 => fffffc0000000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 7, 28 => fffffff800000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 7, 35 => fffffffff0000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 7, 42 => ffffffffffe00000 (00000000 00000000)
++ rldicr ffffffffffffffff, 7, 49 => ffffffffffffc000 (00000000 00000000)
++ rldicr ffffffffffffffff, 7, 56 => ffffffffffffff80 (00000000 00000000)
++ rldicr ffffffffffffffff, 7, 63 => ffffffffffffffff (00000000 00000000)
++ rldicr ffffffffffffffff, 14, 0 => 8000000000000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 14, 7 => ff00000000000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 14, 14 => fffe000000000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 14, 21 => fffffc0000000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 14, 28 => fffffff800000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 14, 35 => fffffffff0000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 14, 42 => ffffffffffe00000 (00000000 00000000)
++ rldicr ffffffffffffffff, 14, 49 => ffffffffffffc000 (00000000 00000000)
++ rldicr ffffffffffffffff, 14, 56 => ffffffffffffff80 (00000000 00000000)
++ rldicr ffffffffffffffff, 14, 63 => ffffffffffffffff (00000000 00000000)
++ rldicr ffffffffffffffff, 21, 0 => 8000000000000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 21, 7 => ff00000000000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 21, 14 => fffe000000000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 21, 21 => fffffc0000000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 21, 28 => fffffff800000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 21, 35 => fffffffff0000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 21, 42 => ffffffffffe00000 (00000000 00000000)
++ rldicr ffffffffffffffff, 21, 49 => ffffffffffffc000 (00000000 00000000)
++ rldicr ffffffffffffffff, 21, 56 => ffffffffffffff80 (00000000 00000000)
++ rldicr ffffffffffffffff, 21, 63 => ffffffffffffffff (00000000 00000000)
++ rldicr ffffffffffffffff, 28, 0 => 8000000000000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 28, 7 => ff00000000000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 28, 14 => fffe000000000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 28, 21 => fffffc0000000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 28, 28 => fffffff800000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 28, 35 => fffffffff0000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 28, 42 => ffffffffffe00000 (00000000 00000000)
++ rldicr ffffffffffffffff, 28, 49 => ffffffffffffc000 (00000000 00000000)
++ rldicr ffffffffffffffff, 28, 56 => ffffffffffffff80 (00000000 00000000)
++ rldicr ffffffffffffffff, 28, 63 => ffffffffffffffff (00000000 00000000)
++ rldicr ffffffffffffffff, 35, 0 => 8000000000000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 35, 7 => ff00000000000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 35, 14 => fffe000000000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 35, 21 => fffffc0000000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 35, 28 => fffffff800000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 35, 35 => fffffffff0000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 35, 42 => ffffffffffe00000 (00000000 00000000)
++ rldicr ffffffffffffffff, 35, 49 => ffffffffffffc000 (00000000 00000000)
++ rldicr ffffffffffffffff, 35, 56 => ffffffffffffff80 (00000000 00000000)
++ rldicr ffffffffffffffff, 35, 63 => ffffffffffffffff (00000000 00000000)
++ rldicr ffffffffffffffff, 42, 0 => 8000000000000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 42, 7 => ff00000000000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 42, 14 => fffe000000000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 42, 21 => fffffc0000000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 42, 28 => fffffff800000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 42, 35 => fffffffff0000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 42, 42 => ffffffffffe00000 (00000000 00000000)
++ rldicr ffffffffffffffff, 42, 49 => ffffffffffffc000 (00000000 00000000)
++ rldicr ffffffffffffffff, 42, 56 => ffffffffffffff80 (00000000 00000000)
++ rldicr ffffffffffffffff, 42, 63 => ffffffffffffffff (00000000 00000000)
++ rldicr ffffffffffffffff, 49, 0 => 8000000000000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 49, 7 => ff00000000000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 49, 14 => fffe000000000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 49, 21 => fffffc0000000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 49, 28 => fffffff800000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 49, 35 => fffffffff0000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 49, 42 => ffffffffffe00000 (00000000 00000000)
++ rldicr ffffffffffffffff, 49, 49 => ffffffffffffc000 (00000000 00000000)
++ rldicr ffffffffffffffff, 49, 56 => ffffffffffffff80 (00000000 00000000)
++ rldicr ffffffffffffffff, 49, 63 => ffffffffffffffff (00000000 00000000)
++ rldicr ffffffffffffffff, 56, 0 => 8000000000000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 56, 7 => ff00000000000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 56, 14 => fffe000000000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 56, 21 => fffffc0000000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 56, 28 => fffffff800000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 56, 35 => fffffffff0000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 56, 42 => ffffffffffe00000 (00000000 00000000)
++ rldicr ffffffffffffffff, 56, 49 => ffffffffffffc000 (00000000 00000000)
++ rldicr ffffffffffffffff, 56, 56 => ffffffffffffff80 (00000000 00000000)
++ rldicr ffffffffffffffff, 56, 63 => ffffffffffffffff (00000000 00000000)
++ rldicr ffffffffffffffff, 63, 0 => 8000000000000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 63, 7 => ff00000000000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 63, 14 => fffe000000000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 63, 21 => fffffc0000000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 63, 28 => fffffff800000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 63, 35 => fffffffff0000000 (00000000 00000000)
++ rldicr ffffffffffffffff, 63, 42 => ffffffffffe00000 (00000000 00000000)
++ rldicr ffffffffffffffff, 63, 49 => ffffffffffffc000 (00000000 00000000)
++ rldicr ffffffffffffffff, 63, 56 => ffffffffffffff80 (00000000 00000000)
++ rldicr ffffffffffffffff, 63, 63 => ffffffffffffffff (00000000 00000000)
++
++ rldimi 0000000000000000, 0, 0 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 0, 7 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 0, 14 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 0, 21 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 0, 28 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 0, 35 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 0, 42 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 0, 49 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 0, 56 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 0, 63 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 7, 0 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 7, 7 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 7, 14 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 7, 21 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 7, 28 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 7, 35 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 7, 42 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 7, 49 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 7, 56 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 7, 63 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 14, 0 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 14, 7 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 14, 14 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 14, 21 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 14, 28 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 14, 35 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 14, 42 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 14, 49 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 14, 56 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 14, 63 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 21, 0 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 21, 7 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 21, 14 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 21, 21 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 21, 28 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 21, 35 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 21, 42 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 21, 49 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 21, 56 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 21, 63 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 28, 0 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 28, 7 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 28, 14 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 28, 21 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 28, 28 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 28, 35 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 28, 42 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 28, 49 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 28, 56 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 28, 63 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 35, 0 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 35, 7 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 35, 14 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 35, 21 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 35, 28 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 35, 35 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 35, 42 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 35, 49 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 35, 56 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 35, 63 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 42, 0 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 42, 7 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 42, 14 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 42, 21 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 42, 28 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 42, 35 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 42, 42 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 42, 49 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 42, 56 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 42, 63 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 49, 0 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 49, 7 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 49, 14 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 49, 21 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 49, 28 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 49, 35 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 49, 42 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 49, 49 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 49, 56 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 49, 63 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 56, 0 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 56, 7 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 56, 14 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 56, 21 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 56, 28 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 56, 35 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 56, 42 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 56, 49 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 56, 56 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 56, 63 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 63, 0 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 63, 7 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 63, 14 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 63, 21 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 63, 28 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 63, 35 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 63, 42 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 63, 49 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 63, 56 => 0000000000000000 (00000000 00000000)
++ rldimi 0000000000000000, 63, 63 => 0000000000000000 (00000000 00000000)
++ rldimi 0000001cbe991def, 0, 0 => 0000001cbe991def (00000000 00000000)
++ rldimi 0000001cbe991def, 0, 7 => 0000001cbe991def (00000000 00000000)
++ rldimi 0000001cbe991def, 0, 14 => 0000001cbe991def (00000000 00000000)
++ rldimi 0000001cbe991def, 0, 21 => 0000001cbe991def (00000000 00000000)
++ rldimi 0000001cbe991def, 0, 28 => 0000001cbe991def (00000000 00000000)
++ rldimi 0000001cbe991def, 0, 35 => 0000001cbe991def (00000000 00000000)
++ rldimi 0000001cbe991def, 0, 42 => 0000001cbe991def (00000000 00000000)
++ rldimi 0000001cbe991def, 0, 49 => 0000001cbe991def (00000000 00000000)
++ rldimi 0000001cbe991def, 0, 56 => 0000001cbe991def (00000000 00000000)
++ rldimi 0000001cbe991def, 0, 63 => 0000001cbe991def (00000000 00000000)
++ rldimi 0000001cbe991def, 7, 0 => 00000e5f4c8ef7ef (00000000 00000000)
++ rldimi 0000001cbe991def, 7, 7 => 00000e5f4c8ef7ef (00000000 00000000)
++ rldimi 0000001cbe991def, 7, 14 => 00000e5f4c8ef7ef (00000000 00000000)
++ rldimi 0000001cbe991def, 7, 21 => 00000e5f4c8ef7ef (00000000 00000000)
++ rldimi 0000001cbe991def, 7, 28 => 00000e5f4c8ef7ef (00000000 00000000)
++ rldimi 0000001cbe991def, 7, 35 => 00000e5f4c8ef7ef (00000000 00000000)
++ rldimi 0000001cbe991def, 7, 42 => 00000e5f4c8ef7ef (00000000 00000000)
++ rldimi 0000001cbe991def, 7, 49 => 00000e5f4c8ef7ef (00000000 00000000)
++ rldimi 0000001cbe991def, 7, 56 => 00000e5f4c8ef7ef (00000000 00000000)
++ rldimi 0000001cbe991def, 7, 63 => 00000e5f4c8ef7ee (00000000 00000000)
++ rldimi 0000001cbe991def, 14, 0 => 00072fa6477bf7ee (00000000 00000000)
++ rldimi 0000001cbe991def, 14, 7 => 00072fa6477bf7ee (00000000 00000000)
++ rldimi 0000001cbe991def, 14, 14 => 00072fa6477bf7ee (00000000 00000000)
++ rldimi 0000001cbe991def, 14, 21 => 00072fa6477bf7ee (00000000 00000000)
++ rldimi 0000001cbe991def, 14, 28 => 00072fa6477bf7ee (00000000 00000000)
++ rldimi 0000001cbe991def, 14, 35 => 00072fa6477bf7ee (00000000 00000000)
++ rldimi 0000001cbe991def, 14, 42 => 00072fa6477bf7ee (00000000 00000000)
++ rldimi 0000001cbe991def, 14, 49 => 00072fa6477bf7ee (00000000 00000000)
++ rldimi 0000001cbe991def, 14, 56 => 00072fa6477bf700 (00000000 00000000)
++ rldimi 0000001cbe991def, 14, 63 => 00072fa6477bf700 (00000000 00000000)
++ rldimi 0000001cbe991def, 21, 0 => 0397d323bdfbf700 (00000000 00000000)
++ rldimi 0000001cbe991def, 21, 7 => 0397d323bdfbf700 (00000000 00000000)
++ rldimi 0000001cbe991def, 21, 14 => 0397d323bdfbf700 (00000000 00000000)
++ rldimi 0000001cbe991def, 21, 21 => 0397d323bdfbf700 (00000000 00000000)
++ rldimi 0000001cbe991def, 21, 28 => 0397d323bdfbf700 (00000000 00000000)
++ rldimi 0000001cbe991def, 21, 35 => 0397d323bdfbf700 (00000000 00000000)
++ rldimi 0000001cbe991def, 21, 42 => 0397d323bdfbf700 (00000000 00000000)
++ rldimi 0000001cbe991def, 21, 49 => 0397d323bdfb8000 (00000000 00000000)
++ rldimi 0000001cbe991def, 21, 56 => 0397d323bdfb8000 (00000000 00000000)
++ rldimi 0000001cbe991def, 21, 63 => 0397d323bdfb8000 (00000000 00000000)
++ rldimi 0000001cbe991def, 28, 0 => cbe991defdfb8000 (00000000 00000000)
++ rldimi 0000001cbe991def, 28, 7 => cbe991defdfb8000 (00000000 00000000)
++ rldimi 0000001cbe991def, 28, 14 => cbe991defdfb8000 (00000000 00000000)
++ rldimi 0000001cbe991def, 28, 21 => cbe991defdfb8000 (00000000 00000000)
++ rldimi 0000001cbe991def, 28, 28 => cbe991defdfb8000 (00000000 00000000)
++ rldimi 0000001cbe991def, 28, 35 => cbe991defdfb8000 (00000000 00000000)
++ rldimi 0000001cbe991def, 28, 42 => cbe991defdc00001 (00000000 00000000)
++ rldimi 0000001cbe991def, 28, 49 => cbe991defdc00001 (00000000 00000000)
++ rldimi 0000001cbe991def, 28, 56 => cbe991defdc00001 (00000000 00000000)
++ rldimi 0000001cbe991def, 28, 63 => cbe991defdc00001 (00000000 00000000)
++ rldimi 0000001cbe991def, 35, 0 => f4c8ef7efdc00001 (00000000 00000000)
++ rldimi 0000001cbe991def, 35, 7 => f4c8ef7efdc00001 (00000000 00000000)
++ rldimi 0000001cbe991def, 35, 14 => f4c8ef7efdc00001 (00000000 00000000)
++ rldimi 0000001cbe991def, 35, 21 => f4c8ef7efdc00001 (00000000 00000000)
++ rldimi 0000001cbe991def, 35, 28 => f4c8ef7efdc00001 (00000000 00000000)
++ rldimi 0000001cbe991def, 35, 35 => f4c8ef7ee00000e5 (00000000 00000000)
++ rldimi 0000001cbe991def, 35, 42 => f4c8ef7ee00000e5 (00000000 00000000)
++ rldimi 0000001cbe991def, 35, 49 => f4c8ef7ee00000e5 (00000000 00000000)
++ rldimi 0000001cbe991def, 35, 56 => f4c8ef7ee00000e5 (00000000 00000000)
++ rldimi 0000001cbe991def, 35, 63 => f4c8ef7ee00000e5 (00000000 00000000)
++ rldimi 0000001cbe991def, 42, 0 => 6477bf7ee00000e5 (00000000 00000000)
++ rldimi 0000001cbe991def, 42, 7 => 6477bf7ee00000e5 (00000000 00000000)
++ rldimi 0000001cbe991def, 42, 14 => 6477bf7ee00000e5 (00000000 00000000)
++ rldimi 0000001cbe991def, 42, 21 => 6477bf7ee00000e5 (00000000 00000000)
++ rldimi 0000001cbe991def, 42, 28 => 6477bf70000072fa (00000000 00000000)
++ rldimi 0000001cbe991def, 42, 35 => 6477bf70000072fa (00000000 00000000)
++ rldimi 0000001cbe991def, 42, 42 => 6477bf70000072fa (00000000 00000000)
++ rldimi 0000001cbe991def, 42, 49 => 6477bf70000072fa (00000000 00000000)
++ rldimi 0000001cbe991def, 42, 56 => 6477bf70000072fa (00000000 00000000)
++ rldimi 0000001cbe991def, 42, 63 => 6477bf70000072fa (00000000 00000000)
++ rldimi 0000001cbe991def, 49, 0 => 3bdfbf70000072fa (00000000 00000000)
++ rldimi 0000001cbe991def, 49, 7 => 3bdfbf70000072fa (00000000 00000000)
++ rldimi 0000001cbe991def, 49, 14 => 3bdfbf70000072fa (00000000 00000000)
++ rldimi 0000001cbe991def, 49, 21 => 3bdfb80000397d32 (00000000 00000000)
++ rldimi 0000001cbe991def, 49, 28 => 3bdfb80000397d32 (00000000 00000000)
++ rldimi 0000001cbe991def, 49, 35 => 3bdfb80000397d32 (00000000 00000000)
++ rldimi 0000001cbe991def, 49, 42 => 3bdfb80000397d32 (00000000 00000000)
++ rldimi 0000001cbe991def, 49, 49 => 3bdfb80000397d32 (00000000 00000000)
++ rldimi 0000001cbe991def, 49, 56 => 3bdfb80000397d32 (00000000 00000000)
++ rldimi 0000001cbe991def, 49, 63 => 3bdfb80000397d32 (00000000 00000000)
++ rldimi 0000001cbe991def, 56, 0 => efdfb80000397d32 (00000000 00000000)
++ rldimi 0000001cbe991def, 56, 7 => efdfb80000397d32 (00000000 00000000)
++ rldimi 0000001cbe991def, 56, 14 => efdc00001cbe991d (00000000 00000000)
++ rldimi 0000001cbe991def, 56, 21 => efdc00001cbe991d (00000000 00000000)
++ rldimi 0000001cbe991def, 56, 28 => efdc00001cbe991d (00000000 00000000)
++ rldimi 0000001cbe991def, 56, 35 => efdc00001cbe991d (00000000 00000000)
++ rldimi 0000001cbe991def, 56, 42 => efdc00001cbe991d (00000000 00000000)
++ rldimi 0000001cbe991def, 56, 49 => efdc00001cbe991d (00000000 00000000)
++ rldimi 0000001cbe991def, 56, 56 => efdc00001cbe991d (00000000 00000000)
++ rldimi 0000001cbe991def, 56, 63 => efdc00001cbe991d (00000000 00000000)
++ rldimi 0000001cbe991def, 63, 0 => efdc00001cbe991d (00000000 00000000)
++ rldimi 0000001cbe991def, 63, 7 => ee00000e5f4c8ef7 (00000000 00000000)
++ rldimi 0000001cbe991def, 63, 14 => ee00000e5f4c8ef7 (00000000 00000000)
++ rldimi 0000001cbe991def, 63, 21 => ee00000e5f4c8ef7 (00000000 00000000)
++ rldimi 0000001cbe991def, 63, 28 => ee00000e5f4c8ef7 (00000000 00000000)
++ rldimi 0000001cbe991def, 63, 35 => ee00000e5f4c8ef7 (00000000 00000000)
++ rldimi 0000001cbe991def, 63, 42 => ee00000e5f4c8ef7 (00000000 00000000)
++ rldimi 0000001cbe991def, 63, 49 => ee00000e5f4c8ef7 (00000000 00000000)
++ rldimi 0000001cbe991def, 63, 56 => ee00000e5f4c8ef7 (00000000 00000000)
++ rldimi 0000001cbe991def, 63, 63 => ee00000e5f4c8ef7 (00000000 00000000)
++ rldimi ffffffffffffffff, 0, 0 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 0, 7 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 0, 14 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 0, 21 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 0, 28 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 0, 35 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 0, 42 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 0, 49 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 0, 56 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 0, 63 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 7, 0 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 7, 7 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 7, 14 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 7, 21 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 7, 28 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 7, 35 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 7, 42 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 7, 49 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 7, 56 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 7, 63 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 14, 0 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 14, 7 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 14, 14 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 14, 21 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 14, 28 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 14, 35 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 14, 42 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 14, 49 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 14, 56 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 14, 63 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 21, 0 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 21, 7 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 21, 14 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 21, 21 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 21, 28 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 21, 35 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 21, 42 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 21, 49 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 21, 56 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 21, 63 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 28, 0 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 28, 7 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 28, 14 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 28, 21 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 28, 28 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 28, 35 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 28, 42 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 28, 49 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 28, 56 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 28, 63 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 35, 0 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 35, 7 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 35, 14 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 35, 21 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 35, 28 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 35, 35 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 35, 42 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 35, 49 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 35, 56 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 35, 63 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 42, 0 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 42, 7 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 42, 14 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 42, 21 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 42, 28 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 42, 35 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 42, 42 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 42, 49 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 42, 56 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 42, 63 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 49, 0 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 49, 7 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 49, 14 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 49, 21 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 49, 28 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 49, 35 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 49, 42 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 49, 49 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 49, 56 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 49, 63 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 56, 0 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 56, 7 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 56, 14 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 56, 21 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 56, 28 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 56, 35 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 56, 42 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 56, 49 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 56, 56 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 56, 63 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 63, 0 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 63, 7 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 63, 14 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 63, 21 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 63, 28 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 63, 35 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 63, 42 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 63, 49 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 63, 56 => ffffffffffffffff (00000000 00000000)
++ rldimi ffffffffffffffff, 63, 63 => ffffffffffffffff (00000000 00000000)
++
++ sradi 0000000000000000, 0 => 0000000000000000 (00000000 00000000)
++ sradi 0000000000000000, 7 => 0000000000000000 (00000000 00000000)
++ sradi 0000000000000000, 14 => 0000000000000000 (00000000 00000000)
++ sradi 0000000000000000, 21 => 0000000000000000 (00000000 00000000)
++ sradi 0000000000000000, 28 => 0000000000000000 (00000000 00000000)
++ sradi 0000000000000000, 35 => 0000000000000000 (00000000 00000000)
++ sradi 0000000000000000, 42 => 0000000000000000 (00000000 00000000)
++ sradi 0000000000000000, 49 => 0000000000000000 (00000000 00000000)
++ sradi 0000000000000000, 56 => 0000000000000000 (00000000 00000000)
++ sradi 0000000000000000, 63 => 0000000000000000 (00000000 00000000)
++ sradi 0000001cbe991def, 0 => 0000001cbe991def (00000000 00000000)
++ sradi 0000001cbe991def, 7 => 00000000397d323b (00000000 00000000)
++ sradi 0000001cbe991def, 14 => 000000000072fa64 (00000000 00000000)
++ sradi 0000001cbe991def, 21 => 000000000000e5f4 (00000000 00000000)
++ sradi 0000001cbe991def, 28 => 00000000000001cb (00000000 00000000)
++ sradi 0000001cbe991def, 35 => 0000000000000003 (00000000 00000000)
++ sradi 0000001cbe991def, 42 => 0000000000000000 (00000000 00000000)
++ sradi 0000001cbe991def, 49 => 0000000000000000 (00000000 00000000)
++ sradi 0000001cbe991def, 56 => 0000000000000000 (00000000 00000000)
++ sradi 0000001cbe991def, 63 => 0000000000000000 (00000000 00000000)
++ sradi ffffffffffffffff, 0 => ffffffffffffffff (00000000 00000000)
++ sradi ffffffffffffffff, 7 => ffffffffffffffff (00000000 20000000)
++ sradi ffffffffffffffff, 14 => ffffffffffffffff (00000000 20000000)
++ sradi ffffffffffffffff, 21 => ffffffffffffffff (00000000 20000000)
++ sradi ffffffffffffffff, 28 => ffffffffffffffff (00000000 20000000)
++ sradi ffffffffffffffff, 35 => ffffffffffffffff (00000000 20000000)
++ sradi ffffffffffffffff, 42 => ffffffffffffffff (00000000 20000000)
++ sradi ffffffffffffffff, 49 => ffffffffffffffff (00000000 20000000)
++ sradi ffffffffffffffff, 56 => ffffffffffffffff (00000000 20000000)
++ sradi ffffffffffffffff, 63 => ffffffffffffffff (00000000 20000000)
++
++PPC logical insns with special forms with flags update:
++ rlwimi. 0000000000000000, 0, 0, 0 => 0000000000000000 (20000000 00000000)
++ rlwimi. 0000000000000000, 0, 0, 31 => 0000000000000000 (20000000 00000000)
++ rlwimi. 0000000000000000, 0, 31, 0 => 0000000000000000 (20000000 00000000)
++ rlwimi. 0000000000000000, 0, 31, 31 => 0000000000000000 (20000000 00000000)
++ rlwimi. 0000000000000000, 31, 0, 0 => 0000000000000000 (20000000 00000000)
++ rlwimi. 0000000000000000, 31, 0, 31 => 0000000000000000 (20000000 00000000)
++ rlwimi. 0000000000000000, 31, 31, 0 => 0000000000000000 (20000000 00000000)
++ rlwimi. 0000000000000000, 31, 31, 31 => 0000000000000000 (20000000 00000000)
++ rlwimi. 0000001cbe991def, 0, 0, 0 => 0000000080000000 (40000000 00000000)
++ rlwimi. 0000001cbe991def, 0, 0, 31 => 00000000be991def (40000000 00000000)
++ rlwimi. 0000001cbe991def, 0, 31, 0 => be991defbe991def (80000000 00000000)
++ rlwimi. 0000001cbe991def, 0, 31, 31 => be991defbe991def (80000000 00000000)
++ rlwimi. 0000001cbe991def, 31, 0, 0 => be991defbe991def (80000000 00000000)
++ rlwimi. 0000001cbe991def, 31, 0, 31 => be991defdf4c8ef7 (80000000 00000000)
++ rlwimi. 0000001cbe991def, 31, 31, 0 => df4c8ef7df4c8ef7 (80000000 00000000)
++ rlwimi. 0000001cbe991def, 31, 31, 31 => df4c8ef7df4c8ef7 (80000000 00000000)
++ rlwimi. ffffffffffffffff, 0, 0, 0 => df4c8ef7df4c8ef7 (80000000 00000000)
++ rlwimi. ffffffffffffffff, 0, 0, 31 => df4c8ef7ffffffff (80000000 00000000)
++ rlwimi. ffffffffffffffff, 0, 31, 0 => ffffffffffffffff (80000000 00000000)
++ rlwimi. ffffffffffffffff, 0, 31, 31 => ffffffffffffffff (80000000 00000000)
++ rlwimi. ffffffffffffffff, 31, 0, 0 => ffffffffffffffff (80000000 00000000)
++ rlwimi. ffffffffffffffff, 31, 0, 31 => ffffffffffffffff (80000000 00000000)
++ rlwimi. ffffffffffffffff, 31, 31, 0 => ffffffffffffffff (80000000 00000000)
++ rlwimi. ffffffffffffffff, 31, 31, 31 => ffffffffffffffff (80000000 00000000)
++
++ rlwinm. 0000000000000000, 0, 0, 0 => 0000000000000000 (20000000 00000000)
++ rlwinm. 0000000000000000, 0, 0, 31 => 0000000000000000 (20000000 00000000)
++ rlwinm. 0000000000000000, 0, 31, 0 => 0000000000000000 (20000000 00000000)
++ rlwinm. 0000000000000000, 0, 31, 31 => 0000000000000000 (20000000 00000000)
++ rlwinm. 0000000000000000, 31, 0, 0 => 0000000000000000 (20000000 00000000)
++ rlwinm. 0000000000000000, 31, 0, 31 => 0000000000000000 (20000000 00000000)
++ rlwinm. 0000000000000000, 31, 31, 0 => 0000000000000000 (20000000 00000000)
++ rlwinm. 0000000000000000, 31, 31, 31 => 0000000000000000 (20000000 00000000)
++ rlwinm. 0000001cbe991def, 0, 0, 0 => 0000000080000000 (40000000 00000000)
++ rlwinm. 0000001cbe991def, 0, 0, 31 => 00000000be991def (40000000 00000000)
++ rlwinm. 0000001cbe991def, 0, 31, 0 => be991def80000001 (80000000 00000000)
++ rlwinm. 0000001cbe991def, 0, 31, 31 => 0000000000000001 (40000000 00000000)
++ rlwinm. 0000001cbe991def, 31, 0, 0 => 0000000080000000 (40000000 00000000)
++ rlwinm. 0000001cbe991def, 31, 0, 31 => 00000000df4c8ef7 (40000000 00000000)
++ rlwinm. 0000001cbe991def, 31, 31, 0 => df4c8ef780000001 (80000000 00000000)
++ rlwinm. 0000001cbe991def, 31, 31, 31 => 0000000000000001 (40000000 00000000)
++ rlwinm. ffffffffffffffff, 0, 0, 0 => 0000000080000000 (40000000 00000000)
++ rlwinm. ffffffffffffffff, 0, 0, 31 => 00000000ffffffff (40000000 00000000)
++ rlwinm. ffffffffffffffff, 0, 31, 0 => ffffffff80000001 (80000000 00000000)
++ rlwinm. ffffffffffffffff, 0, 31, 31 => 0000000000000001 (40000000 00000000)
++ rlwinm. ffffffffffffffff, 31, 0, 0 => 0000000080000000 (40000000 00000000)
++ rlwinm. ffffffffffffffff, 31, 0, 31 => 00000000ffffffff (40000000 00000000)
++ rlwinm. ffffffffffffffff, 31, 31, 0 => ffffffff80000001 (80000000 00000000)
++ rlwinm. ffffffffffffffff, 31, 31, 31 => 0000000000000001 (40000000 00000000)
++
++ rlwnm. 0000000000000000, 0000000000000000, 0, 0 => 0000000000000000 (20000000 00000000)
++ rlwnm. 0000000000000000, 0000000000000000, 0, 31 => 0000000000000000 (20000000 00000000)
++ rlwnm. 0000000000000000, 0000000000000000, 31, 0 => 0000000000000000 (20000000 00000000)
++ rlwnm. 0000000000000000, 0000000000000000, 31, 31 => 0000000000000000 (20000000 00000000)
++ rlwnm. 0000000000000000, 0000001cbe991def, 0, 0 => 0000000000000000 (20000000 00000000)
++ rlwnm. 0000000000000000, 0000001cbe991def, 0, 31 => 0000000000000000 (20000000 00000000)
++ rlwnm. 0000000000000000, 0000001cbe991def, 31, 0 => 0000000000000000 (20000000 00000000)
++ rlwnm. 0000000000000000, 0000001cbe991def, 31, 31 => 0000000000000000 (20000000 00000000)
++ rlwnm. 0000000000000000, ffffffffffffffff, 0, 0 => 0000000000000000 (20000000 00000000)
++ rlwnm. 0000000000000000, ffffffffffffffff, 0, 31 => 0000000000000000 (20000000 00000000)
++ rlwnm. 0000000000000000, ffffffffffffffff, 31, 0 => 0000000000000000 (20000000 00000000)
++ rlwnm. 0000000000000000, ffffffffffffffff, 31, 31 => 0000000000000000 (20000000 00000000)
++ rlwnm. 0000001cbe991def, 0000000000000000, 0, 0 => 0000000080000000 (40000000 00000000)
++ rlwnm. 0000001cbe991def, 0000000000000000, 0, 31 => 00000000be991def (40000000 00000000)
++ rlwnm. 0000001cbe991def, 0000000000000000, 31, 0 => be991def80000001 (80000000 00000000)
++ rlwnm. 0000001cbe991def, 0000000000000000, 31, 31 => 0000000000000001 (40000000 00000000)
++ rlwnm. 0000001cbe991def, 0000001cbe991def, 0, 0 => 0000000080000000 (40000000 00000000)
++ rlwnm. 0000001cbe991def, 0000001cbe991def, 0, 31 => 000000008ef7df4c (40000000 00000000)
++ rlwnm. 0000001cbe991def, 0000001cbe991def, 31, 0 => 8ef7df4c80000000 (80000000 00000000)
++ rlwnm. 0000001cbe991def, 0000001cbe991def, 31, 31 => 0000000000000000 (20000000 00000000)
++ rlwnm. 0000001cbe991def, ffffffffffffffff, 0, 0 => 0000000080000000 (40000000 00000000)
++ rlwnm. 0000001cbe991def, ffffffffffffffff, 0, 31 => 00000000df4c8ef7 (40000000 00000000)
++ rlwnm. 0000001cbe991def, ffffffffffffffff, 31, 0 => df4c8ef780000001 (80000000 00000000)
++ rlwnm. 0000001cbe991def, ffffffffffffffff, 31, 31 => 0000000000000001 (40000000 00000000)
++ rlwnm. ffffffffffffffff, 0000000000000000, 0, 0 => 0000000080000000 (40000000 00000000)
++ rlwnm. ffffffffffffffff, 0000000000000000, 0, 31 => 00000000ffffffff (40000000 00000000)
++ rlwnm. ffffffffffffffff, 0000000000000000, 31, 0 => ffffffff80000001 (80000000 00000000)
++ rlwnm. ffffffffffffffff, 0000000000000000, 31, 31 => 0000000000000001 (40000000 00000000)
++ rlwnm. ffffffffffffffff, 0000001cbe991def, 0, 0 => 0000000080000000 (40000000 00000000)
++ rlwnm. ffffffffffffffff, 0000001cbe991def, 0, 31 => 00000000ffffffff (40000000 00000000)
++ rlwnm. ffffffffffffffff, 0000001cbe991def, 31, 0 => ffffffff80000001 (80000000 00000000)
++ rlwnm. ffffffffffffffff, 0000001cbe991def, 31, 31 => 0000000000000001 (40000000 00000000)
++ rlwnm. ffffffffffffffff, ffffffffffffffff, 0, 0 => 0000000080000000 (40000000 00000000)
++ rlwnm. ffffffffffffffff, ffffffffffffffff, 0, 31 => 00000000ffffffff (40000000 00000000)
++ rlwnm. ffffffffffffffff, ffffffffffffffff, 31, 0 => ffffffff80000001 (80000000 00000000)
++ rlwnm. ffffffffffffffff, ffffffffffffffff, 31, 31 => 0000000000000001 (40000000 00000000)
++
++ srawi. 0000000000000000, 0 => 0000000000000000 (20000000 00000000)
++ srawi. 0000000000000000, 31 => 0000000000000000 (20000000 00000000)
++ srawi. 0000001cbe991def, 0 => ffffffffbe991def (80000000 00000000)
++ srawi. 0000001cbe991def, 31 => ffffffffffffffff (80000000 20000000)
++ srawi. ffffffffffffffff, 0 => ffffffffffffffff (80000000 00000000)
++ srawi. ffffffffffffffff, 31 => ffffffffffffffff (80000000 20000000)
++
++ mcrf 0, 0 (0000000000000000) => (00000000 00000000)
++ mcrf 0, 7 (0000000000000000) => (00000000 00000000)
++ mcrf 7, 0 (0000000000000000) => (00000000 00000000)
++ mcrf 7, 7 (0000000000000000) => (00000000 00000000)
++ mcrf 0, 0 (0000001cbe991def) => (be991def 00000000)
++ mcrf 0, 7 (0000001cbe991def) => (fe991def 00000000)
++ mcrf 7, 0 (0000001cbe991def) => (be991deb 00000000)
++ mcrf 7, 7 (0000001cbe991def) => (be991def 00000000)
++ mcrf 0, 0 (ffffffffffffffff) => (ffffffff 00000000)
++ mcrf 0, 7 (ffffffffffffffff) => (ffffffff 00000000)
++ mcrf 7, 0 (ffffffffffffffff) => (ffffffff 00000000)
++ mcrf 7, 7 (ffffffffffffffff) => (ffffffff 00000000)
++
++ mcrxr 0 (00000000) => (00000000 00000000)
++ mcrxr 1 (00000000) => (00000000 00000000)
++ mcrxr 2 (00000000) => (00000000 00000000)
++ mcrxr 3 (00000000) => (00000000 00000000)
++ mcrxr 4 (00000000) => (00000000 00000000)
++ mcrxr 5 (00000000) => (00000000 00000000)
++ mcrxr 6 (00000000) => (00000000 00000000)
++ mcrxr 7 (00000000) => (00000000 00000000)
++ mcrxr 0 (10000000) => (00000000 00000000)
++ mcrxr 1 (10000000) => (00000000 00000000)
++ mcrxr 2 (10000000) => (00000000 00000000)
++ mcrxr 3 (10000000) => (00000000 00000000)
++ mcrxr 4 (10000000) => (00000000 00000000)
++ mcrxr 5 (10000000) => (00000000 00000000)
++ mcrxr 6 (10000000) => (00000000 00000000)
++ mcrxr 7 (10000000) => (00000000 00000000)
++ mcrxr 0 (20000000) => (20000000 00000000)
++ mcrxr 1 (20000000) => (02000000 00000000)
++ mcrxr 2 (20000000) => (00200000 00000000)
++ mcrxr 3 (20000000) => (00020000 00000000)
++ mcrxr 4 (20000000) => (00002000 00000000)
++ mcrxr 5 (20000000) => (00000200 00000000)
++ mcrxr 6 (20000000) => (00000020 00000000)
++ mcrxr 7 (20000000) => (00000002 00000000)
++ mcrxr 0 (30000000) => (20000000 00000000)
++ mcrxr 1 (30000000) => (02000000 00000000)
++ mcrxr 2 (30000000) => (00200000 00000000)
++ mcrxr 3 (30000000) => (00020000 00000000)
++ mcrxr 4 (30000000) => (00002000 00000000)
++ mcrxr 5 (30000000) => (00000200 00000000)
++ mcrxr 6 (30000000) => (00000020 00000000)
++ mcrxr 7 (30000000) => (00000002 00000000)
++ mcrxr 0 (40000000) => (40000000 00000000)
++ mcrxr 1 (40000000) => (04000000 00000000)
++ mcrxr 2 (40000000) => (00400000 00000000)
++ mcrxr 3 (40000000) => (00040000 00000000)
++ mcrxr 4 (40000000) => (00004000 00000000)
++ mcrxr 5 (40000000) => (00000400 00000000)
++ mcrxr 6 (40000000) => (00000040 00000000)
++ mcrxr 7 (40000000) => (00000004 00000000)
++ mcrxr 0 (50000000) => (40000000 00000000)
++ mcrxr 1 (50000000) => (04000000 00000000)
++ mcrxr 2 (50000000) => (00400000 00000000)
++ mcrxr 3 (50000000) => (00040000 00000000)
++ mcrxr 4 (50000000) => (00004000 00000000)
++ mcrxr 5 (50000000) => (00000400 00000000)
++ mcrxr 6 (50000000) => (00000040 00000000)
++ mcrxr 7 (50000000) => (00000004 00000000)
++ mcrxr 0 (60000000) => (60000000 00000000)
++ mcrxr 1 (60000000) => (06000000 00000000)
++ mcrxr 2 (60000000) => (00600000 00000000)
++ mcrxr 3 (60000000) => (00060000 00000000)
++ mcrxr 4 (60000000) => (00006000 00000000)
++ mcrxr 5 (60000000) => (00000600 00000000)
++ mcrxr 6 (60000000) => (00000060 00000000)
++ mcrxr 7 (60000000) => (00000006 00000000)
++ mcrxr 0 (70000000) => (60000000 00000000)
++ mcrxr 1 (70000000) => (06000000 00000000)
++ mcrxr 2 (70000000) => (00600000 00000000)
++ mcrxr 3 (70000000) => (00060000 00000000)
++ mcrxr 4 (70000000) => (00006000 00000000)
++ mcrxr 5 (70000000) => (00000600 00000000)
++ mcrxr 6 (70000000) => (00000060 00000000)
++ mcrxr 7 (70000000) => (00000006 00000000)
++ mcrxr 0 (80000000) => (80000000 00000000)
++ mcrxr 1 (80000000) => (08000000 00000000)
++ mcrxr 2 (80000000) => (00800000 00000000)
++ mcrxr 3 (80000000) => (00080000 00000000)
++ mcrxr 4 (80000000) => (00008000 00000000)
++ mcrxr 5 (80000000) => (00000800 00000000)
++ mcrxr 6 (80000000) => (00000080 00000000)
++ mcrxr 7 (80000000) => (00000008 00000000)
++ mcrxr 0 (90000000) => (80000000 00000000)
++ mcrxr 1 (90000000) => (08000000 00000000)
++ mcrxr 2 (90000000) => (00800000 00000000)
++ mcrxr 3 (90000000) => (00080000 00000000)
++ mcrxr 4 (90000000) => (00008000 00000000)
++ mcrxr 5 (90000000) => (00000800 00000000)
++ mcrxr 6 (90000000) => (00000080 00000000)
++ mcrxr 7 (90000000) => (00000008 00000000)
++ mcrxr 0 (a0000000) => (a0000000 00000000)
++ mcrxr 1 (a0000000) => (0a000000 00000000)
++ mcrxr 2 (a0000000) => (00a00000 00000000)
++ mcrxr 3 (a0000000) => (000a0000 00000000)
++ mcrxr 4 (a0000000) => (0000a000 00000000)
++ mcrxr 5 (a0000000) => (00000a00 00000000)
++ mcrxr 6 (a0000000) => (000000a0 00000000)
++ mcrxr 7 (a0000000) => (0000000a 00000000)
++ mcrxr 0 (b0000000) => (a0000000 00000000)
++ mcrxr 1 (b0000000) => (0a000000 00000000)
++ mcrxr 2 (b0000000) => (00a00000 00000000)
++ mcrxr 3 (b0000000) => (000a0000 00000000)
++ mcrxr 4 (b0000000) => (0000a000 00000000)
++ mcrxr 5 (b0000000) => (00000a00 00000000)
++ mcrxr 6 (b0000000) => (000000a0 00000000)
++ mcrxr 7 (b0000000) => (0000000a 00000000)
++ mcrxr 0 (c0000000) => (c0000000 00000000)
++ mcrxr 1 (c0000000) => (0c000000 00000000)
++ mcrxr 2 (c0000000) => (00c00000 00000000)
++ mcrxr 3 (c0000000) => (000c0000 00000000)
++ mcrxr 4 (c0000000) => (0000c000 00000000)
++ mcrxr 5 (c0000000) => (00000c00 00000000)
++ mcrxr 6 (c0000000) => (000000c0 00000000)
++ mcrxr 7 (c0000000) => (0000000c 00000000)
++ mcrxr 0 (d0000000) => (c0000000 00000000)
++ mcrxr 1 (d0000000) => (0c000000 00000000)
++ mcrxr 2 (d0000000) => (00c00000 00000000)
++ mcrxr 3 (d0000000) => (000c0000 00000000)
++ mcrxr 4 (d0000000) => (0000c000 00000000)
++ mcrxr 5 (d0000000) => (00000c00 00000000)
++ mcrxr 6 (d0000000) => (000000c0 00000000)
++ mcrxr 7 (d0000000) => (0000000c 00000000)
++ mcrxr 0 (e0000000) => (e0000000 00000000)
++ mcrxr 1 (e0000000) => (0e000000 00000000)
++ mcrxr 2 (e0000000) => (00e00000 00000000)
++ mcrxr 3 (e0000000) => (000e0000 00000000)
++ mcrxr 4 (e0000000) => (0000e000 00000000)
++ mcrxr 5 (e0000000) => (00000e00 00000000)
++ mcrxr 6 (e0000000) => (000000e0 00000000)
++ mcrxr 7 (e0000000) => (0000000e 00000000)
++ mcrxr 0 (f0000000) => (e0000000 00000000)
++ mcrxr 1 (f0000000) => (0e000000 00000000)
++ mcrxr 2 (f0000000) => (00e00000 00000000)
++ mcrxr 3 (f0000000) => (000e0000 00000000)
++ mcrxr 4 (f0000000) => (0000e000 00000000)
++ mcrxr 5 (f0000000) => (00000e00 00000000)
++ mcrxr 6 (f0000000) => (000000e0 00000000)
++ mcrxr 7 (f0000000) => (0000000e 00000000)
++
++ mtcrf 0, 0000000000000000 => (00000000 00000000)
++ mtcrf 99, 0000000000000000 => (00000000 00000000)
++ mtcrf 198, 0000000000000000 => (00000000 00000000)
++ mtcrf 0, 0000001cbe991def => (00000000 00000000)
++ mtcrf 99, 0000001cbe991def => (0e9000ef 00000000)
++ mtcrf 198, 0000001cbe991def => (be000de0 00000000)
++ mtcrf 0, ffffffffffffffff => (00000000 00000000)
++ mtcrf 99, ffffffffffffffff => (0ff000ff 00000000)
++ mtcrf 198, ffffffffffffffff => (ff000ff0 00000000)
++
++ rldcl. 0000000000000000, 0000000000000000, 0 => 0000000000000000 (20000000 00000000)
++ rldcl. 0000000000000000, 0000000000000000, 7 => 0000000000000000 (20000000 00000000)
++ rldcl. 0000000000000000, 0000000000000000, 14 => 0000000000000000 (20000000 00000000)
++ rldcl. 0000000000000000, 0000000000000000, 21 => 0000000000000000 (20000000 00000000)
++ rldcl. 0000000000000000, 0000000000000000, 28 => 0000000000000000 (20000000 00000000)
++ rldcl. 0000000000000000, 0000000000000000, 35 => 0000000000000000 (20000000 00000000)
++ rldcl. 0000000000000000, 0000000000000000, 42 => 0000000000000000 (20000000 00000000)
++ rldcl. 0000000000000000, 0000000000000000, 49 => 0000000000000000 (20000000 00000000)
++ rldcl. 0000000000000000, 0000000000000000, 56 => 0000000000000000 (20000000 00000000)
++ rldcl. 0000000000000000, 0000000000000000, 63 => 0000000000000000 (20000000 00000000)
++ rldcl. 0000000000000000, 0000001cbe991def, 0 => 0000000000000000 (20000000 00000000)
++ rldcl. 0000000000000000, 0000001cbe991def, 7 => 0000000000000000 (20000000 00000000)
++ rldcl. 0000000000000000, 0000001cbe991def, 14 => 0000000000000000 (20000000 00000000)
++ rldcl. 0000000000000000, 0000001cbe991def, 21 => 0000000000000000 (20000000 00000000)
++ rldcl. 0000000000000000, 0000001cbe991def, 28 => 0000000000000000 (20000000 00000000)
++ rldcl. 0000000000000000, 0000001cbe991def, 35 => 0000000000000000 (20000000 00000000)
++ rldcl. 0000000000000000, 0000001cbe991def, 42 => 0000000000000000 (20000000 00000000)
++ rldcl. 0000000000000000, 0000001cbe991def, 49 => 0000000000000000 (20000000 00000000)
++ rldcl. 0000000000000000, 0000001cbe991def, 56 => 0000000000000000 (20000000 00000000)
++ rldcl. 0000000000000000, 0000001cbe991def, 63 => 0000000000000000 (20000000 00000000)
++ rldcl. 0000000000000000, ffffffffffffffff, 0 => 0000000000000000 (20000000 00000000)
++ rldcl. 0000000000000000, ffffffffffffffff, 7 => 0000000000000000 (20000000 00000000)
++ rldcl. 0000000000000000, ffffffffffffffff, 14 => 0000000000000000 (20000000 00000000)
++ rldcl. 0000000000000000, ffffffffffffffff, 21 => 0000000000000000 (20000000 00000000)
++ rldcl. 0000000000000000, ffffffffffffffff, 28 => 0000000000000000 (20000000 00000000)
++ rldcl. 0000000000000000, ffffffffffffffff, 35 => 0000000000000000 (20000000 00000000)
++ rldcl. 0000000000000000, ffffffffffffffff, 42 => 0000000000000000 (20000000 00000000)
++ rldcl. 0000000000000000, ffffffffffffffff, 49 => 0000000000000000 (20000000 00000000)
++ rldcl. 0000000000000000, ffffffffffffffff, 56 => 0000000000000000 (20000000 00000000)
++ rldcl. 0000000000000000, ffffffffffffffff, 63 => 0000000000000000 (20000000 00000000)
++ rldcl. 0000001cbe991def, 0000000000000000, 0 => 0000001cbe991def (40000000 00000000)
++ rldcl. 0000001cbe991def, 0000000000000000, 7 => 0000001cbe991def (40000000 00000000)
++ rldcl. 0000001cbe991def, 0000000000000000, 14 => 0000001cbe991def (40000000 00000000)
++ rldcl. 0000001cbe991def, 0000000000000000, 21 => 0000001cbe991def (40000000 00000000)
++ rldcl. 0000001cbe991def, 0000000000000000, 28 => 0000000cbe991def (40000000 00000000)
++ rldcl. 0000001cbe991def, 0000000000000000, 35 => 000000001e991def (40000000 00000000)
++ rldcl. 0000001cbe991def, 0000000000000000, 42 => 0000000000191def (40000000 00000000)
++ rldcl. 0000001cbe991def, 0000000000000000, 49 => 0000000000001def (40000000 00000000)
++ rldcl. 0000001cbe991def, 0000000000000000, 56 => 00000000000000ef (40000000 00000000)
++ rldcl. 0000001cbe991def, 0000000000000000, 63 => 0000000000000001 (40000000 00000000)
++ rldcl. 0000001cbe991def, 0000001cbe991def, 0 => 8ef78000000e5f4c (80000000 00000000)
++ rldcl. 0000001cbe991def, 0000001cbe991def, 7 => 00f78000000e5f4c (40000000 00000000)
++ rldcl. 0000001cbe991def, 0000001cbe991def, 14 => 00038000000e5f4c (40000000 00000000)
++ rldcl. 0000001cbe991def, 0000001cbe991def, 21 => 00000000000e5f4c (40000000 00000000)
++ rldcl. 0000001cbe991def, 0000001cbe991def, 28 => 00000000000e5f4c (40000000 00000000)
++ rldcl. 0000001cbe991def, 0000001cbe991def, 35 => 00000000000e5f4c (40000000 00000000)
++ rldcl. 0000001cbe991def, 0000001cbe991def, 42 => 00000000000e5f4c (40000000 00000000)
++ rldcl. 0000001cbe991def, 0000001cbe991def, 49 => 0000000000005f4c (40000000 00000000)
++ rldcl. 0000001cbe991def, 0000001cbe991def, 56 => 000000000000004c (40000000 00000000)
++ rldcl. 0000001cbe991def, 0000001cbe991def, 63 => 0000000000000000 (20000000 00000000)
++ rldcl. 0000001cbe991def, ffffffffffffffff, 0 => 8000000e5f4c8ef7 (80000000 00000000)
++ rldcl. 0000001cbe991def, ffffffffffffffff, 7 => 0000000e5f4c8ef7 (40000000 00000000)
++ rldcl. 0000001cbe991def, ffffffffffffffff, 14 => 0000000e5f4c8ef7 (40000000 00000000)
++ rldcl. 0000001cbe991def, ffffffffffffffff, 21 => 0000000e5f4c8ef7 (40000000 00000000)
++ rldcl. 0000001cbe991def, ffffffffffffffff, 28 => 0000000e5f4c8ef7 (40000000 00000000)
++ rldcl. 0000001cbe991def, ffffffffffffffff, 35 => 000000001f4c8ef7 (40000000 00000000)
++ rldcl. 0000001cbe991def, ffffffffffffffff, 42 => 00000000000c8ef7 (40000000 00000000)
++ rldcl. 0000001cbe991def, ffffffffffffffff, 49 => 0000000000000ef7 (40000000 00000000)
++ rldcl. 0000001cbe991def, ffffffffffffffff, 56 => 00000000000000f7 (40000000 00000000)
++ rldcl. 0000001cbe991def, ffffffffffffffff, 63 => 0000000000000001 (40000000 00000000)
++ rldcl. ffffffffffffffff, 0000000000000000, 0 => ffffffffffffffff (80000000 00000000)
++ rldcl. ffffffffffffffff, 0000000000000000, 7 => 01ffffffffffffff (40000000 00000000)
++ rldcl. ffffffffffffffff, 0000000000000000, 14 => 0003ffffffffffff (40000000 00000000)
++ rldcl. ffffffffffffffff, 0000000000000000, 21 => 000007ffffffffff (40000000 00000000)
++ rldcl. ffffffffffffffff, 0000000000000000, 28 => 0000000fffffffff (40000000 00000000)
++ rldcl. ffffffffffffffff, 0000000000000000, 35 => 000000001fffffff (40000000 00000000)
++ rldcl. ffffffffffffffff, 0000000000000000, 42 => 00000000003fffff (40000000 00000000)
++ rldcl. ffffffffffffffff, 0000000000000000, 49 => 0000000000007fff (40000000 00000000)
++ rldcl. ffffffffffffffff, 0000000000000000, 56 => 00000000000000ff (40000000 00000000)
++ rldcl. ffffffffffffffff, 0000000000000000, 63 => 0000000000000001 (40000000 00000000)
++ rldcl. ffffffffffffffff, 0000001cbe991def, 0 => ffffffffffffffff (80000000 00000000)
++ rldcl. ffffffffffffffff, 0000001cbe991def, 7 => 01ffffffffffffff (40000000 00000000)
++ rldcl. ffffffffffffffff, 0000001cbe991def, 14 => 0003ffffffffffff (40000000 00000000)
++ rldcl. ffffffffffffffff, 0000001cbe991def, 21 => 000007ffffffffff (40000000 00000000)
++ rldcl. ffffffffffffffff, 0000001cbe991def, 28 => 0000000fffffffff (40000000 00000000)
++ rldcl. ffffffffffffffff, 0000001cbe991def, 35 => 000000001fffffff (40000000 00000000)
++ rldcl. ffffffffffffffff, 0000001cbe991def, 42 => 00000000003fffff (40000000 00000000)
++ rldcl. ffffffffffffffff, 0000001cbe991def, 49 => 0000000000007fff (40000000 00000000)
++ rldcl. ffffffffffffffff, 0000001cbe991def, 56 => 00000000000000ff (40000000 00000000)
++ rldcl. ffffffffffffffff, 0000001cbe991def, 63 => 0000000000000001 (40000000 00000000)
++ rldcl. ffffffffffffffff, ffffffffffffffff, 0 => ffffffffffffffff (80000000 00000000)
++ rldcl. ffffffffffffffff, ffffffffffffffff, 7 => 01ffffffffffffff (40000000 00000000)
++ rldcl. ffffffffffffffff, ffffffffffffffff, 14 => 0003ffffffffffff (40000000 00000000)
++ rldcl. ffffffffffffffff, ffffffffffffffff, 21 => 000007ffffffffff (40000000 00000000)
++ rldcl. ffffffffffffffff, ffffffffffffffff, 28 => 0000000fffffffff (40000000 00000000)
++ rldcl. ffffffffffffffff, ffffffffffffffff, 35 => 000000001fffffff (40000000 00000000)
++ rldcl. ffffffffffffffff, ffffffffffffffff, 42 => 00000000003fffff (40000000 00000000)
++ rldcl. ffffffffffffffff, ffffffffffffffff, 49 => 0000000000007fff (40000000 00000000)
++ rldcl. ffffffffffffffff, ffffffffffffffff, 56 => 00000000000000ff (40000000 00000000)
++ rldcl. ffffffffffffffff, ffffffffffffffff, 63 => 0000000000000001 (40000000 00000000)
++
++ rldcr. 0000000000000000, 0000000000000000, 0 => 0000000000000000 (20000000 00000000)
++ rldcr. 0000000000000000, 0000000000000000, 7 => 0000000000000000 (20000000 00000000)
++ rldcr. 0000000000000000, 0000000000000000, 14 => 0000000000000000 (20000000 00000000)
++ rldcr. 0000000000000000, 0000000000000000, 21 => 0000000000000000 (20000000 00000000)
++ rldcr. 0000000000000000, 0000000000000000, 28 => 0000000000000000 (20000000 00000000)
++ rldcr. 0000000000000000, 0000000000000000, 35 => 0000000000000000 (20000000 00000000)
++ rldcr. 0000000000000000, 0000000000000000, 42 => 0000000000000000 (20000000 00000000)
++ rldcr. 0000000000000000, 0000000000000000, 49 => 0000000000000000 (20000000 00000000)
++ rldcr. 0000000000000000, 0000000000000000, 56 => 0000000000000000 (20000000 00000000)
++ rldcr. 0000000000000000, 0000000000000000, 63 => 0000000000000000 (20000000 00000000)
++ rldcr. 0000000000000000, 0000001cbe991def, 0 => 0000000000000000 (20000000 00000000)
++ rldcr. 0000000000000000, 0000001cbe991def, 7 => 0000000000000000 (20000000 00000000)
++ rldcr. 0000000000000000, 0000001cbe991def, 14 => 0000000000000000 (20000000 00000000)
++ rldcr. 0000000000000000, 0000001cbe991def, 21 => 0000000000000000 (20000000 00000000)
++ rldcr. 0000000000000000, 0000001cbe991def, 28 => 0000000000000000 (20000000 00000000)
++ rldcr. 0000000000000000, 0000001cbe991def, 35 => 0000000000000000 (20000000 00000000)
++ rldcr. 0000000000000000, 0000001cbe991def, 42 => 0000000000000000 (20000000 00000000)
++ rldcr. 0000000000000000, 0000001cbe991def, 49 => 0000000000000000 (20000000 00000000)
++ rldcr. 0000000000000000, 0000001cbe991def, 56 => 0000000000000000 (20000000 00000000)
++ rldcr. 0000000000000000, 0000001cbe991def, 63 => 0000000000000000 (20000000 00000000)
++ rldcr. 0000000000000000, ffffffffffffffff, 0 => 0000000000000000 (20000000 00000000)
++ rldcr. 0000000000000000, ffffffffffffffff, 7 => 0000000000000000 (20000000 00000000)
++ rldcr. 0000000000000000, ffffffffffffffff, 14 => 0000000000000000 (20000000 00000000)
++ rldcr. 0000000000000000, ffffffffffffffff, 21 => 0000000000000000 (20000000 00000000)
++ rldcr. 0000000000000000, ffffffffffffffff, 28 => 0000000000000000 (20000000 00000000)
++ rldcr. 0000000000000000, ffffffffffffffff, 35 => 0000000000000000 (20000000 00000000)
++ rldcr. 0000000000000000, ffffffffffffffff, 42 => 0000000000000000 (20000000 00000000)
++ rldcr. 0000000000000000, ffffffffffffffff, 49 => 0000000000000000 (20000000 00000000)
++ rldcr. 0000000000000000, ffffffffffffffff, 56 => 0000000000000000 (20000000 00000000)
++ rldcr. 0000000000000000, ffffffffffffffff, 63 => 0000000000000000 (20000000 00000000)
++ rldcr. 0000001cbe991def, 0000000000000000, 0 => 0000000000000000 (20000000 00000000)
++ rldcr. 0000001cbe991def, 0000000000000000, 7 => 0000000000000000 (20000000 00000000)
++ rldcr. 0000001cbe991def, 0000000000000000, 14 => 0000000000000000 (20000000 00000000)
++ rldcr. 0000001cbe991def, 0000000000000000, 21 => 0000000000000000 (20000000 00000000)
++ rldcr. 0000001cbe991def, 0000000000000000, 28 => 0000001800000000 (40000000 00000000)
++ rldcr. 0000001cbe991def, 0000000000000000, 35 => 0000001cb0000000 (40000000 00000000)
++ rldcr. 0000001cbe991def, 0000000000000000, 42 => 0000001cbe800000 (40000000 00000000)
++ rldcr. 0000001cbe991def, 0000000000000000, 49 => 0000001cbe990000 (40000000 00000000)
++ rldcr. 0000001cbe991def, 0000000000000000, 56 => 0000001cbe991d80 (40000000 00000000)
++ rldcr. 0000001cbe991def, 0000000000000000, 63 => 0000001cbe991def (40000000 00000000)
++ rldcr. 0000001cbe991def, 0000001cbe991def, 0 => 8000000000000000 (80000000 00000000)
++ rldcr. 0000001cbe991def, 0000001cbe991def, 7 => 8e00000000000000 (80000000 00000000)
++ rldcr. 0000001cbe991def, 0000001cbe991def, 14 => 8ef6000000000000 (80000000 00000000)
++ rldcr. 0000001cbe991def, 0000001cbe991def, 21 => 8ef7800000000000 (80000000 00000000)
++ rldcr. 0000001cbe991def, 0000001cbe991def, 28 => 8ef7800000000000 (80000000 00000000)
++ rldcr. 0000001cbe991def, 0000001cbe991def, 35 => 8ef7800000000000 (80000000 00000000)
++ rldcr. 0000001cbe991def, 0000001cbe991def, 42 => 8ef7800000000000 (80000000 00000000)
++ rldcr. 0000001cbe991def, 0000001cbe991def, 49 => 8ef78000000e4000 (80000000 00000000)
++ rldcr. 0000001cbe991def, 0000001cbe991def, 56 => 8ef78000000e5f00 (80000000 00000000)
++ rldcr. 0000001cbe991def, 0000001cbe991def, 63 => 8ef78000000e5f4c (80000000 00000000)
++ rldcr. 0000001cbe991def, ffffffffffffffff, 0 => 8000000000000000 (80000000 00000000)
++ rldcr. 0000001cbe991def, ffffffffffffffff, 7 => 8000000000000000 (80000000 00000000)
++ rldcr. 0000001cbe991def, ffffffffffffffff, 14 => 8000000000000000 (80000000 00000000)
++ rldcr. 0000001cbe991def, ffffffffffffffff, 21 => 8000000000000000 (80000000 00000000)
++ rldcr. 0000001cbe991def, ffffffffffffffff, 28 => 8000000800000000 (80000000 00000000)
++ rldcr. 0000001cbe991def, ffffffffffffffff, 35 => 8000000e50000000 (80000000 00000000)
++ rldcr. 0000001cbe991def, ffffffffffffffff, 42 => 8000000e5f400000 (80000000 00000000)
++ rldcr. 0000001cbe991def, ffffffffffffffff, 49 => 8000000e5f4c8000 (80000000 00000000)
++ rldcr. 0000001cbe991def, ffffffffffffffff, 56 => 8000000e5f4c8e80 (80000000 00000000)
++ rldcr. 0000001cbe991def, ffffffffffffffff, 63 => 8000000e5f4c8ef7 (80000000 00000000)
++ rldcr. ffffffffffffffff, 0000000000000000, 0 => 8000000000000000 (80000000 00000000)
++ rldcr. ffffffffffffffff, 0000000000000000, 7 => ff00000000000000 (80000000 00000000)
++ rldcr. ffffffffffffffff, 0000000000000000, 14 => fffe000000000000 (80000000 00000000)
++ rldcr. ffffffffffffffff, 0000000000000000, 21 => fffffc0000000000 (80000000 00000000)
++ rldcr. ffffffffffffffff, 0000000000000000, 28 => fffffff800000000 (80000000 00000000)
++ rldcr. ffffffffffffffff, 0000000000000000, 35 => fffffffff0000000 (80000000 00000000)
++ rldcr. ffffffffffffffff, 0000000000000000, 42 => ffffffffffe00000 (80000000 00000000)
++ rldcr. ffffffffffffffff, 0000000000000000, 49 => ffffffffffffc000 (80000000 00000000)
++ rldcr. ffffffffffffffff, 0000000000000000, 56 => ffffffffffffff80 (80000000 00000000)
++ rldcr. ffffffffffffffff, 0000000000000000, 63 => ffffffffffffffff (80000000 00000000)
++ rldcr. ffffffffffffffff, 0000001cbe991def, 0 => 8000000000000000 (80000000 00000000)
++ rldcr. ffffffffffffffff, 0000001cbe991def, 7 => ff00000000000000 (80000000 00000000)
++ rldcr. ffffffffffffffff, 0000001cbe991def, 14 => fffe000000000000 (80000000 00000000)
++ rldcr. ffffffffffffffff, 0000001cbe991def, 21 => fffffc0000000000 (80000000 00000000)
++ rldcr. ffffffffffffffff, 0000001cbe991def, 28 => fffffff800000000 (80000000 00000000)
++ rldcr. ffffffffffffffff, 0000001cbe991def, 35 => fffffffff0000000 (80000000 00000000)
++ rldcr. ffffffffffffffff, 0000001cbe991def, 42 => ffffffffffe00000 (80000000 00000000)
++ rldcr. ffffffffffffffff, 0000001cbe991def, 49 => ffffffffffffc000 (80000000 00000000)
++ rldcr. ffffffffffffffff, 0000001cbe991def, 56 => ffffffffffffff80 (80000000 00000000)
++ rldcr. ffffffffffffffff, 0000001cbe991def, 63 => ffffffffffffffff (80000000 00000000)
++ rldcr. ffffffffffffffff, ffffffffffffffff, 0 => 8000000000000000 (80000000 00000000)
++ rldcr. ffffffffffffffff, ffffffffffffffff, 7 => ff00000000000000 (80000000 00000000)
++ rldcr. ffffffffffffffff, ffffffffffffffff, 14 => fffe000000000000 (80000000 00000000)
++ rldcr. ffffffffffffffff, ffffffffffffffff, 21 => fffffc0000000000 (80000000 00000000)
++ rldcr. ffffffffffffffff, ffffffffffffffff, 28 => fffffff800000000 (80000000 00000000)
++ rldcr. ffffffffffffffff, ffffffffffffffff, 35 => fffffffff0000000 (80000000 00000000)
++ rldcr. ffffffffffffffff, ffffffffffffffff, 42 => ffffffffffe00000 (80000000 00000000)
++ rldcr. ffffffffffffffff, ffffffffffffffff, 49 => ffffffffffffc000 (80000000 00000000)
++ rldcr. ffffffffffffffff, ffffffffffffffff, 56 => ffffffffffffff80 (80000000 00000000)
++ rldcr. ffffffffffffffff, ffffffffffffffff, 63 => ffffffffffffffff (80000000 00000000)
++
++ rldic. 0000000000000000, 0, 0 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 0, 7 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 0, 14 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 0, 21 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 0, 28 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 0, 35 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 0, 42 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 0, 49 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 0, 56 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 0, 63 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 7, 0 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 7, 7 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 7, 14 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 7, 21 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 7, 28 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 7, 35 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 7, 42 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 7, 49 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 7, 56 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 7, 63 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 14, 0 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 14, 7 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 14, 14 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 14, 21 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 14, 28 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 14, 35 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 14, 42 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 14, 49 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 14, 56 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 14, 63 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 21, 0 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 21, 7 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 21, 14 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 21, 21 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 21, 28 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 21, 35 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 21, 42 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 21, 49 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 21, 56 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 21, 63 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 28, 0 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 28, 7 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 28, 14 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 28, 21 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 28, 28 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 28, 35 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 28, 42 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 28, 49 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 28, 56 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 28, 63 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 35, 0 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 35, 7 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 35, 14 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 35, 21 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 35, 28 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 35, 35 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 35, 42 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 35, 49 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 35, 56 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 35, 63 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 42, 0 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 42, 7 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 42, 14 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 42, 21 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 42, 28 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 42, 35 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 42, 42 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 42, 49 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 42, 56 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 42, 63 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 49, 0 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 49, 7 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 49, 14 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 49, 21 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 49, 28 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 49, 35 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 49, 42 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 49, 49 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 49, 56 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 49, 63 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 56, 0 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 56, 7 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 56, 14 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 56, 21 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 56, 28 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 56, 35 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 56, 42 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 56, 49 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 56, 56 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 56, 63 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 63, 0 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 63, 7 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 63, 14 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 63, 21 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 63, 28 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 63, 35 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 63, 42 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 63, 49 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 63, 56 => 0000000000000000 (20000000 00000000)
++ rldic. 0000000000000000, 63, 63 => 0000000000000000 (20000000 00000000)
++ rldic. 0000001cbe991def, 0, 0 => 0000001cbe991def (40000000 00000000)
++ rldic. 0000001cbe991def, 0, 7 => 0000001cbe991def (40000000 00000000)
++ rldic. 0000001cbe991def, 0, 14 => 0000001cbe991def (40000000 00000000)
++ rldic. 0000001cbe991def, 0, 21 => 0000001cbe991def (40000000 00000000)
++ rldic. 0000001cbe991def, 0, 28 => 0000000cbe991def (40000000 00000000)
++ rldic. 0000001cbe991def, 0, 35 => 000000001e991def (40000000 00000000)
++ rldic. 0000001cbe991def, 0, 42 => 0000000000191def (40000000 00000000)
++ rldic. 0000001cbe991def, 0, 49 => 0000000000001def (40000000 00000000)
++ rldic. 0000001cbe991def, 0, 56 => 00000000000000ef (40000000 00000000)
++ rldic. 0000001cbe991def, 0, 63 => 0000000000000001 (40000000 00000000)
++ rldic. 0000001cbe991def, 7, 0 => 00000e5f4c8ef780 (40000000 00000000)
++ rldic. 0000001cbe991def, 7, 7 => 00000e5f4c8ef780 (40000000 00000000)
++ rldic. 0000001cbe991def, 7, 14 => 00000e5f4c8ef780 (40000000 00000000)
++ rldic. 0000001cbe991def, 7, 21 => 0000065f4c8ef780 (40000000 00000000)
++ rldic. 0000001cbe991def, 7, 28 => 0000000f4c8ef780 (40000000 00000000)
++ rldic. 0000001cbe991def, 7, 35 => 000000000c8ef780 (40000000 00000000)
++ rldic. 0000001cbe991def, 7, 42 => 00000000000ef780 (40000000 00000000)
++ rldic. 0000001cbe991def, 7, 49 => 0000000000007780 (40000000 00000000)
++ rldic. 0000001cbe991def, 7, 56 => 0000000000000080 (40000000 00000000)
++ rldic. 0000001cbe991def, 7, 63 => 00000e5f4c8ef780 (40000000 00000000)
++ rldic. 0000001cbe991def, 14, 0 => 00072fa6477bc000 (40000000 00000000)
++ rldic. 0000001cbe991def, 14, 7 => 00072fa6477bc000 (40000000 00000000)
++ rldic. 0000001cbe991def, 14, 14 => 00032fa6477bc000 (40000000 00000000)
++ rldic. 0000001cbe991def, 14, 21 => 000007a6477bc000 (40000000 00000000)
++ rldic. 0000001cbe991def, 14, 28 => 00000006477bc000 (40000000 00000000)
++ rldic. 0000001cbe991def, 14, 35 => 00000000077bc000 (40000000 00000000)
++ rldic. 0000001cbe991def, 14, 42 => 00000000003bc000 (40000000 00000000)
++ rldic. 0000001cbe991def, 14, 49 => 0000000000004000 (40000000 00000000)
++ rldic. 0000001cbe991def, 14, 56 => 00072fa6477bc000 (40000000 00000000)
++ rldic. 0000001cbe991def, 14, 63 => 00072fa6477bc000 (40000000 00000000)
++ rldic. 0000001cbe991def, 21, 0 => 0397d323bde00000 (40000000 00000000)
++ rldic. 0000001cbe991def, 21, 7 => 0197d323bde00000 (40000000 00000000)
++ rldic. 0000001cbe991def, 21, 14 => 0003d323bde00000 (40000000 00000000)
++ rldic. 0000001cbe991def, 21, 21 => 00000323bde00000 (40000000 00000000)
++ rldic. 0000001cbe991def, 21, 28 => 00000003bde00000 (40000000 00000000)
++ rldic. 0000001cbe991def, 21, 35 => 000000001de00000 (40000000 00000000)
++ rldic. 0000001cbe991def, 21, 42 => 0000000000200000 (40000000 00000000)
++ rldic. 0000001cbe991def, 21, 49 => 0397d323bde00000 (40000000 00000000)
++ rldic. 0000001cbe991def, 21, 56 => 0397d323bde00000 (40000000 00000000)
++ rldic. 0000001cbe991def, 21, 63 => 0397d323bde00000 (40000000 00000000)
++ rldic. 0000001cbe991def, 28, 0 => cbe991def0000000 (80000000 00000000)
++ rldic. 0000001cbe991def, 28, 7 => 01e991def0000000 (40000000 00000000)
++ rldic. 0000001cbe991def, 28, 14 => 000191def0000000 (40000000 00000000)
++ rldic. 0000001cbe991def, 28, 21 => 000001def0000000 (40000000 00000000)
++ rldic. 0000001cbe991def, 28, 28 => 0000000ef0000000 (40000000 00000000)
++ rldic. 0000001cbe991def, 28, 35 => 0000000010000000 (40000000 00000000)
++ rldic. 0000001cbe991def, 28, 42 => cbe991def0000001 (80000000 00000000)
++ rldic. 0000001cbe991def, 28, 49 => cbe991def0000001 (80000000 00000000)
++ rldic. 0000001cbe991def, 28, 56 => cbe991def0000001 (80000000 00000000)
++ rldic. 0000001cbe991def, 28, 63 => cbe991def0000001 (80000000 00000000)
++ rldic. 0000001cbe991def, 35, 0 => f4c8ef7800000000 (80000000 00000000)
++ rldic. 0000001cbe991def, 35, 7 => 00c8ef7800000000 (40000000 00000000)
++ rldic. 0000001cbe991def, 35, 14 => 0000ef7800000000 (40000000 00000000)
++ rldic. 0000001cbe991def, 35, 21 => 0000077800000000 (40000000 00000000)
++ rldic. 0000001cbe991def, 35, 28 => 0000000800000000 (40000000 00000000)
++ rldic. 0000001cbe991def, 35, 35 => f4c8ef78000000e5 (80000000 00000000)
++ rldic. 0000001cbe991def, 35, 42 => f4c8ef78000000e5 (80000000 00000000)
++ rldic. 0000001cbe991def, 35, 49 => f4c8ef78000000e5 (80000000 00000000)
++ rldic. 0000001cbe991def, 35, 56 => f4c8ef78000000e5 (80000000 00000000)
++ rldic. 0000001cbe991def, 35, 63 => f4c8ef7800000001 (80000000 00000000)
++ rldic. 0000001cbe991def, 42, 0 => 6477bc0000000000 (40000000 00000000)
++ rldic. 0000001cbe991def, 42, 7 => 0077bc0000000000 (40000000 00000000)
++ rldic. 0000001cbe991def, 42, 14 => 0003bc0000000000 (40000000 00000000)
++ rldic. 0000001cbe991def, 42, 21 => 0000040000000000 (40000000 00000000)
++ rldic. 0000001cbe991def, 42, 28 => 6477bc00000072fa (40000000 00000000)
++ rldic. 0000001cbe991def, 42, 35 => 6477bc00000072fa (40000000 00000000)
++ rldic. 0000001cbe991def, 42, 42 => 6477bc00000072fa (40000000 00000000)
++ rldic. 0000001cbe991def, 42, 49 => 6477bc00000072fa (40000000 00000000)
++ rldic. 0000001cbe991def, 42, 56 => 6477bc00000000fa (40000000 00000000)
++ rldic. 0000001cbe991def, 42, 63 => 6477bc0000000000 (40000000 00000000)
++ rldic. 0000001cbe991def, 49, 0 => 3bde000000000000 (40000000 00000000)
++ rldic. 0000001cbe991def, 49, 7 => 01de000000000000 (40000000 00000000)
++ rldic. 0000001cbe991def, 49, 14 => 0002000000000000 (40000000 00000000)
++ rldic. 0000001cbe991def, 49, 21 => 3bde000000397d32 (40000000 00000000)
++ rldic. 0000001cbe991def, 49, 28 => 3bde000000397d32 (40000000 00000000)
++ rldic. 0000001cbe991def, 49, 35 => 3bde000000397d32 (40000000 00000000)
++ rldic. 0000001cbe991def, 49, 42 => 3bde000000397d32 (40000000 00000000)
++ rldic. 0000001cbe991def, 49, 49 => 3bde000000007d32 (40000000 00000000)
++ rldic. 0000001cbe991def, 49, 56 => 3bde000000000032 (40000000 00000000)
++ rldic. 0000001cbe991def, 49, 63 => 3bde000000000000 (40000000 00000000)
++ rldic. 0000001cbe991def, 56, 0 => ef00000000000000 (80000000 00000000)
++ rldic. 0000001cbe991def, 56, 7 => 0100000000000000 (40000000 00000000)
++ rldic. 0000001cbe991def, 56, 14 => ef0000001cbe991d (80000000 00000000)
++ rldic. 0000001cbe991def, 56, 21 => ef0000001cbe991d (80000000 00000000)
++ rldic. 0000001cbe991def, 56, 28 => ef0000001cbe991d (80000000 00000000)
++ rldic. 0000001cbe991def, 56, 35 => ef0000001cbe991d (80000000 00000000)
++ rldic. 0000001cbe991def, 56, 42 => ef000000003e991d (80000000 00000000)
++ rldic. 0000001cbe991def, 56, 49 => ef0000000000191d (80000000 00000000)
++ rldic. 0000001cbe991def, 56, 56 => ef0000000000001d (80000000 00000000)
++ rldic. 0000001cbe991def, 56, 63 => ef00000000000001 (80000000 00000000)
++ rldic. 0000001cbe991def, 63, 0 => 8000000000000000 (80000000 00000000)
++ rldic. 0000001cbe991def, 63, 7 => 8000000e5f4c8ef7 (80000000 00000000)
++ rldic. 0000001cbe991def, 63, 14 => 8000000e5f4c8ef7 (80000000 00000000)
++ rldic. 0000001cbe991def, 63, 21 => 8000000e5f4c8ef7 (80000000 00000000)
++ rldic. 0000001cbe991def, 63, 28 => 8000000e5f4c8ef7 (80000000 00000000)
++ rldic. 0000001cbe991def, 63, 35 => 800000001f4c8ef7 (80000000 00000000)
++ rldic. 0000001cbe991def, 63, 42 => 80000000000c8ef7 (80000000 00000000)
++ rldic. 0000001cbe991def, 63, 49 => 8000000000000ef7 (80000000 00000000)
++ rldic. 0000001cbe991def, 63, 56 => 80000000000000f7 (80000000 00000000)
++ rldic. 0000001cbe991def, 63, 63 => 8000000000000001 (80000000 00000000)
++ rldic. ffffffffffffffff, 0, 0 => ffffffffffffffff (80000000 00000000)
++ rldic. ffffffffffffffff, 0, 7 => 01ffffffffffffff (40000000 00000000)
++ rldic. ffffffffffffffff, 0, 14 => 0003ffffffffffff (40000000 00000000)
++ rldic. ffffffffffffffff, 0, 21 => 000007ffffffffff (40000000 00000000)
++ rldic. ffffffffffffffff, 0, 28 => 0000000fffffffff (40000000 00000000)
++ rldic. ffffffffffffffff, 0, 35 => 000000001fffffff (40000000 00000000)
++ rldic. ffffffffffffffff, 0, 42 => 00000000003fffff (40000000 00000000)
++ rldic. ffffffffffffffff, 0, 49 => 0000000000007fff (40000000 00000000)
++ rldic. ffffffffffffffff, 0, 56 => 00000000000000ff (40000000 00000000)
++ rldic. ffffffffffffffff, 0, 63 => 0000000000000001 (40000000 00000000)
++ rldic. ffffffffffffffff, 7, 0 => ffffffffffffff80 (80000000 00000000)
++ rldic. ffffffffffffffff, 7, 7 => 01ffffffffffff80 (40000000 00000000)
++ rldic. ffffffffffffffff, 7, 14 => 0003ffffffffff80 (40000000 00000000)
++ rldic. ffffffffffffffff, 7, 21 => 000007ffffffff80 (40000000 00000000)
++ rldic. ffffffffffffffff, 7, 28 => 0000000fffffff80 (40000000 00000000)
++ rldic. ffffffffffffffff, 7, 35 => 000000001fffff80 (40000000 00000000)
++ rldic. ffffffffffffffff, 7, 42 => 00000000003fff80 (40000000 00000000)
++ rldic. ffffffffffffffff, 7, 49 => 0000000000007f80 (40000000 00000000)
++ rldic. ffffffffffffffff, 7, 56 => 0000000000000080 (40000000 00000000)
++ rldic. ffffffffffffffff, 7, 63 => ffffffffffffff81 (80000000 00000000)
++ rldic. ffffffffffffffff, 14, 0 => ffffffffffffc000 (80000000 00000000)
++ rldic. ffffffffffffffff, 14, 7 => 01ffffffffffc000 (40000000 00000000)
++ rldic. ffffffffffffffff, 14, 14 => 0003ffffffffc000 (40000000 00000000)
++ rldic. ffffffffffffffff, 14, 21 => 000007ffffffc000 (40000000 00000000)
++ rldic. ffffffffffffffff, 14, 28 => 0000000fffffc000 (40000000 00000000)
++ rldic. ffffffffffffffff, 14, 35 => 000000001fffc000 (40000000 00000000)
++ rldic. ffffffffffffffff, 14, 42 => 00000000003fc000 (40000000 00000000)
++ rldic. ffffffffffffffff, 14, 49 => 0000000000004000 (40000000 00000000)
++ rldic. ffffffffffffffff, 14, 56 => ffffffffffffc0ff (80000000 00000000)
++ rldic. ffffffffffffffff, 14, 63 => ffffffffffffc001 (80000000 00000000)
++ rldic. ffffffffffffffff, 21, 0 => ffffffffffe00000 (80000000 00000000)
++ rldic. ffffffffffffffff, 21, 7 => 01ffffffffe00000 (40000000 00000000)
++ rldic. ffffffffffffffff, 21, 14 => 0003ffffffe00000 (40000000 00000000)
++ rldic. ffffffffffffffff, 21, 21 => 000007ffffe00000 (40000000 00000000)
++ rldic. ffffffffffffffff, 21, 28 => 0000000fffe00000 (40000000 00000000)
++ rldic. ffffffffffffffff, 21, 35 => 000000001fe00000 (40000000 00000000)
++ rldic. ffffffffffffffff, 21, 42 => 0000000000200000 (40000000 00000000)
++ rldic. ffffffffffffffff, 21, 49 => ffffffffffe07fff (80000000 00000000)
++ rldic. ffffffffffffffff, 21, 56 => ffffffffffe000ff (80000000 00000000)
++ rldic. ffffffffffffffff, 21, 63 => ffffffffffe00001 (80000000 00000000)
++ rldic. ffffffffffffffff, 28, 0 => fffffffff0000000 (80000000 00000000)
++ rldic. ffffffffffffffff, 28, 7 => 01fffffff0000000 (40000000 00000000)
++ rldic. ffffffffffffffff, 28, 14 => 0003fffff0000000 (40000000 00000000)
++ rldic. ffffffffffffffff, 28, 21 => 000007fff0000000 (40000000 00000000)
++ rldic. ffffffffffffffff, 28, 28 => 0000000ff0000000 (40000000 00000000)
++ rldic. ffffffffffffffff, 28, 35 => 0000000010000000 (40000000 00000000)
++ rldic. ffffffffffffffff, 28, 42 => fffffffff03fffff (80000000 00000000)
++ rldic. ffffffffffffffff, 28, 49 => fffffffff0007fff (80000000 00000000)
++ rldic. ffffffffffffffff, 28, 56 => fffffffff00000ff (80000000 00000000)
++ rldic. ffffffffffffffff, 28, 63 => fffffffff0000001 (80000000 00000000)
++ rldic. ffffffffffffffff, 35, 0 => fffffff800000000 (80000000 00000000)
++ rldic. ffffffffffffffff, 35, 7 => 01fffff800000000 (40000000 00000000)
++ rldic. ffffffffffffffff, 35, 14 => 0003fff800000000 (40000000 00000000)
++ rldic. ffffffffffffffff, 35, 21 => 000007f800000000 (40000000 00000000)
++ rldic. ffffffffffffffff, 35, 28 => 0000000800000000 (40000000 00000000)
++ rldic. ffffffffffffffff, 35, 35 => fffffff81fffffff (80000000 00000000)
++ rldic. ffffffffffffffff, 35, 42 => fffffff8003fffff (80000000 00000000)
++ rldic. ffffffffffffffff, 35, 49 => fffffff800007fff (80000000 00000000)
++ rldic. ffffffffffffffff, 35, 56 => fffffff8000000ff (80000000 00000000)
++ rldic. ffffffffffffffff, 35, 63 => fffffff800000001 (80000000 00000000)
++ rldic. ffffffffffffffff, 42, 0 => fffffc0000000000 (80000000 00000000)
++ rldic. ffffffffffffffff, 42, 7 => 01fffc0000000000 (40000000 00000000)
++ rldic. ffffffffffffffff, 42, 14 => 0003fc0000000000 (40000000 00000000)
++ rldic. ffffffffffffffff, 42, 21 => 0000040000000000 (40000000 00000000)
++ rldic. ffffffffffffffff, 42, 28 => fffffc0fffffffff (80000000 00000000)
++ rldic. ffffffffffffffff, 42, 35 => fffffc001fffffff (80000000 00000000)
++ rldic. ffffffffffffffff, 42, 42 => fffffc00003fffff (80000000 00000000)
++ rldic. ffffffffffffffff, 42, 49 => fffffc0000007fff (80000000 00000000)
++ rldic. ffffffffffffffff, 42, 56 => fffffc00000000ff (80000000 00000000)
++ rldic. ffffffffffffffff, 42, 63 => fffffc0000000001 (80000000 00000000)
++ rldic. ffffffffffffffff, 49, 0 => fffe000000000000 (80000000 00000000)
++ rldic. ffffffffffffffff, 49, 7 => 01fe000000000000 (40000000 00000000)
++ rldic. ffffffffffffffff, 49, 14 => 0002000000000000 (40000000 00000000)
++ rldic. ffffffffffffffff, 49, 21 => fffe07ffffffffff (80000000 00000000)
++ rldic. ffffffffffffffff, 49, 28 => fffe000fffffffff (80000000 00000000)
++ rldic. ffffffffffffffff, 49, 35 => fffe00001fffffff (80000000 00000000)
++ rldic. ffffffffffffffff, 49, 42 => fffe0000003fffff (80000000 00000000)
++ rldic. ffffffffffffffff, 49, 49 => fffe000000007fff (80000000 00000000)
++ rldic. ffffffffffffffff, 49, 56 => fffe0000000000ff (80000000 00000000)
++ rldic. ffffffffffffffff, 49, 63 => fffe000000000001 (80000000 00000000)
++ rldic. ffffffffffffffff, 56, 0 => ff00000000000000 (80000000 00000000)
++ rldic. ffffffffffffffff, 56, 7 => 0100000000000000 (40000000 00000000)
++ rldic. ffffffffffffffff, 56, 14 => ff03ffffffffffff (80000000 00000000)
++ rldic. ffffffffffffffff, 56, 21 => ff0007ffffffffff (80000000 00000000)
++ rldic. ffffffffffffffff, 56, 28 => ff00000fffffffff (80000000 00000000)
++ rldic. ffffffffffffffff, 56, 35 => ff0000001fffffff (80000000 00000000)
++ rldic. ffffffffffffffff, 56, 42 => ff000000003fffff (80000000 00000000)
++ rldic. ffffffffffffffff, 56, 49 => ff00000000007fff (80000000 00000000)
++ rldic. ffffffffffffffff, 56, 56 => ff000000000000ff (80000000 00000000)
++ rldic. ffffffffffffffff, 56, 63 => ff00000000000001 (80000000 00000000)
++ rldic. ffffffffffffffff, 63, 0 => 8000000000000000 (80000000 00000000)
++ rldic. ffffffffffffffff, 63, 7 => 81ffffffffffffff (80000000 00000000)
++ rldic. ffffffffffffffff, 63, 14 => 8003ffffffffffff (80000000 00000000)
++ rldic. ffffffffffffffff, 63, 21 => 800007ffffffffff (80000000 00000000)
++ rldic. ffffffffffffffff, 63, 28 => 8000000fffffffff (80000000 00000000)
++ rldic. ffffffffffffffff, 63, 35 => 800000001fffffff (80000000 00000000)
++ rldic. ffffffffffffffff, 63, 42 => 80000000003fffff (80000000 00000000)
++ rldic. ffffffffffffffff, 63, 49 => 8000000000007fff (80000000 00000000)
++ rldic. ffffffffffffffff, 63, 56 => 80000000000000ff (80000000 00000000)
++ rldic. ffffffffffffffff, 63, 63 => 8000000000000001 (80000000 00000000)
++
++ rldicl. 0000000000000000, 0, 0 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 0, 7 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 0, 14 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 0, 21 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 0, 28 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 0, 35 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 0, 42 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 0, 49 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 0, 56 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 0, 63 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 7, 0 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 7, 7 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 7, 14 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 7, 21 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 7, 28 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 7, 35 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 7, 42 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 7, 49 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 7, 56 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 7, 63 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 14, 0 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 14, 7 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 14, 14 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 14, 21 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 14, 28 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 14, 35 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 14, 42 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 14, 49 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 14, 56 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 14, 63 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 21, 0 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 21, 7 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 21, 14 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 21, 21 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 21, 28 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 21, 35 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 21, 42 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 21, 49 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 21, 56 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 21, 63 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 28, 0 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 28, 7 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 28, 14 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 28, 21 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 28, 28 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 28, 35 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 28, 42 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 28, 49 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 28, 56 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 28, 63 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 35, 0 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 35, 7 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 35, 14 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 35, 21 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 35, 28 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 35, 35 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 35, 42 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 35, 49 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 35, 56 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 35, 63 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 42, 0 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 42, 7 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 42, 14 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 42, 21 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 42, 28 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 42, 35 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 42, 42 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 42, 49 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 42, 56 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 42, 63 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 49, 0 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 49, 7 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 49, 14 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 49, 21 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 49, 28 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 49, 35 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 49, 42 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 49, 49 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 49, 56 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 49, 63 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 56, 0 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 56, 7 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 56, 14 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 56, 21 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 56, 28 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 56, 35 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 56, 42 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 56, 49 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 56, 56 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 56, 63 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 63, 0 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 63, 7 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 63, 14 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 63, 21 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 63, 28 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 63, 35 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 63, 42 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 63, 49 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 63, 56 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000000000000000, 63, 63 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000001cbe991def, 0, 0 => 0000001cbe991def (40000000 00000000)
++ rldicl. 0000001cbe991def, 0, 7 => 0000001cbe991def (40000000 00000000)
++ rldicl. 0000001cbe991def, 0, 14 => 0000001cbe991def (40000000 00000000)
++ rldicl. 0000001cbe991def, 0, 21 => 0000001cbe991def (40000000 00000000)
++ rldicl. 0000001cbe991def, 0, 28 => 0000000cbe991def (40000000 00000000)
++ rldicl. 0000001cbe991def, 0, 35 => 000000001e991def (40000000 00000000)
++ rldicl. 0000001cbe991def, 0, 42 => 0000000000191def (40000000 00000000)
++ rldicl. 0000001cbe991def, 0, 49 => 0000000000001def (40000000 00000000)
++ rldicl. 0000001cbe991def, 0, 56 => 00000000000000ef (40000000 00000000)
++ rldicl. 0000001cbe991def, 0, 63 => 0000000000000001 (40000000 00000000)
++ rldicl. 0000001cbe991def, 7, 0 => 00000e5f4c8ef780 (40000000 00000000)
++ rldicl. 0000001cbe991def, 7, 7 => 00000e5f4c8ef780 (40000000 00000000)
++ rldicl. 0000001cbe991def, 7, 14 => 00000e5f4c8ef780 (40000000 00000000)
++ rldicl. 0000001cbe991def, 7, 21 => 0000065f4c8ef780 (40000000 00000000)
++ rldicl. 0000001cbe991def, 7, 28 => 0000000f4c8ef780 (40000000 00000000)
++ rldicl. 0000001cbe991def, 7, 35 => 000000000c8ef780 (40000000 00000000)
++ rldicl. 0000001cbe991def, 7, 42 => 00000000000ef780 (40000000 00000000)
++ rldicl. 0000001cbe991def, 7, 49 => 0000000000007780 (40000000 00000000)
++ rldicl. 0000001cbe991def, 7, 56 => 0000000000000080 (40000000 00000000)
++ rldicl. 0000001cbe991def, 7, 63 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000001cbe991def, 14, 0 => 00072fa6477bc000 (40000000 00000000)
++ rldicl. 0000001cbe991def, 14, 7 => 00072fa6477bc000 (40000000 00000000)
++ rldicl. 0000001cbe991def, 14, 14 => 00032fa6477bc000 (40000000 00000000)
++ rldicl. 0000001cbe991def, 14, 21 => 000007a6477bc000 (40000000 00000000)
++ rldicl. 0000001cbe991def, 14, 28 => 00000006477bc000 (40000000 00000000)
++ rldicl. 0000001cbe991def, 14, 35 => 00000000077bc000 (40000000 00000000)
++ rldicl. 0000001cbe991def, 14, 42 => 00000000003bc000 (40000000 00000000)
++ rldicl. 0000001cbe991def, 14, 49 => 0000000000004000 (40000000 00000000)
++ rldicl. 0000001cbe991def, 14, 56 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000001cbe991def, 14, 63 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000001cbe991def, 21, 0 => 0397d323bde00000 (40000000 00000000)
++ rldicl. 0000001cbe991def, 21, 7 => 0197d323bde00000 (40000000 00000000)
++ rldicl. 0000001cbe991def, 21, 14 => 0003d323bde00000 (40000000 00000000)
++ rldicl. 0000001cbe991def, 21, 21 => 00000323bde00000 (40000000 00000000)
++ rldicl. 0000001cbe991def, 21, 28 => 00000003bde00000 (40000000 00000000)
++ rldicl. 0000001cbe991def, 21, 35 => 000000001de00000 (40000000 00000000)
++ rldicl. 0000001cbe991def, 21, 42 => 0000000000200000 (40000000 00000000)
++ rldicl. 0000001cbe991def, 21, 49 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000001cbe991def, 21, 56 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000001cbe991def, 21, 63 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000001cbe991def, 28, 0 => cbe991def0000001 (80000000 00000000)
++ rldicl. 0000001cbe991def, 28, 7 => 01e991def0000001 (40000000 00000000)
++ rldicl. 0000001cbe991def, 28, 14 => 000191def0000001 (40000000 00000000)
++ rldicl. 0000001cbe991def, 28, 21 => 000001def0000001 (40000000 00000000)
++ rldicl. 0000001cbe991def, 28, 28 => 0000000ef0000001 (40000000 00000000)
++ rldicl. 0000001cbe991def, 28, 35 => 0000000010000001 (40000000 00000000)
++ rldicl. 0000001cbe991def, 28, 42 => 0000000000000001 (40000000 00000000)
++ rldicl. 0000001cbe991def, 28, 49 => 0000000000000001 (40000000 00000000)
++ rldicl. 0000001cbe991def, 28, 56 => 0000000000000001 (40000000 00000000)
++ rldicl. 0000001cbe991def, 28, 63 => 0000000000000001 (40000000 00000000)
++ rldicl. 0000001cbe991def, 35, 0 => f4c8ef78000000e5 (80000000 00000000)
++ rldicl. 0000001cbe991def, 35, 7 => 00c8ef78000000e5 (40000000 00000000)
++ rldicl. 0000001cbe991def, 35, 14 => 0000ef78000000e5 (40000000 00000000)
++ rldicl. 0000001cbe991def, 35, 21 => 00000778000000e5 (40000000 00000000)
++ rldicl. 0000001cbe991def, 35, 28 => 00000008000000e5 (40000000 00000000)
++ rldicl. 0000001cbe991def, 35, 35 => 00000000000000e5 (40000000 00000000)
++ rldicl. 0000001cbe991def, 35, 42 => 00000000000000e5 (40000000 00000000)
++ rldicl. 0000001cbe991def, 35, 49 => 00000000000000e5 (40000000 00000000)
++ rldicl. 0000001cbe991def, 35, 56 => 00000000000000e5 (40000000 00000000)
++ rldicl. 0000001cbe991def, 35, 63 => 0000000000000001 (40000000 00000000)
++ rldicl. 0000001cbe991def, 42, 0 => 6477bc00000072fa (40000000 00000000)
++ rldicl. 0000001cbe991def, 42, 7 => 0077bc00000072fa (40000000 00000000)
++ rldicl. 0000001cbe991def, 42, 14 => 0003bc00000072fa (40000000 00000000)
++ rldicl. 0000001cbe991def, 42, 21 => 00000400000072fa (40000000 00000000)
++ rldicl. 0000001cbe991def, 42, 28 => 00000000000072fa (40000000 00000000)
++ rldicl. 0000001cbe991def, 42, 35 => 00000000000072fa (40000000 00000000)
++ rldicl. 0000001cbe991def, 42, 42 => 00000000000072fa (40000000 00000000)
++ rldicl. 0000001cbe991def, 42, 49 => 00000000000072fa (40000000 00000000)
++ rldicl. 0000001cbe991def, 42, 56 => 00000000000000fa (40000000 00000000)
++ rldicl. 0000001cbe991def, 42, 63 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000001cbe991def, 49, 0 => 3bde000000397d32 (40000000 00000000)
++ rldicl. 0000001cbe991def, 49, 7 => 01de000000397d32 (40000000 00000000)
++ rldicl. 0000001cbe991def, 49, 14 => 0002000000397d32 (40000000 00000000)
++ rldicl. 0000001cbe991def, 49, 21 => 0000000000397d32 (40000000 00000000)
++ rldicl. 0000001cbe991def, 49, 28 => 0000000000397d32 (40000000 00000000)
++ rldicl. 0000001cbe991def, 49, 35 => 0000000000397d32 (40000000 00000000)
++ rldicl. 0000001cbe991def, 49, 42 => 0000000000397d32 (40000000 00000000)
++ rldicl. 0000001cbe991def, 49, 49 => 0000000000007d32 (40000000 00000000)
++ rldicl. 0000001cbe991def, 49, 56 => 0000000000000032 (40000000 00000000)
++ rldicl. 0000001cbe991def, 49, 63 => 0000000000000000 (20000000 00000000)
++ rldicl. 0000001cbe991def, 56, 0 => ef0000001cbe991d (80000000 00000000)
++ rldicl. 0000001cbe991def, 56, 7 => 010000001cbe991d (40000000 00000000)
++ rldicl. 0000001cbe991def, 56, 14 => 000000001cbe991d (40000000 00000000)
++ rldicl. 0000001cbe991def, 56, 21 => 000000001cbe991d (40000000 00000000)
++ rldicl. 0000001cbe991def, 56, 28 => 000000001cbe991d (40000000 00000000)
++ rldicl. 0000001cbe991def, 56, 35 => 000000001cbe991d (40000000 00000000)
++ rldicl. 0000001cbe991def, 56, 42 => 00000000003e991d (40000000 00000000)
++ rldicl. 0000001cbe991def, 56, 49 => 000000000000191d (40000000 00000000)
++ rldicl. 0000001cbe991def, 56, 56 => 000000000000001d (40000000 00000000)
++ rldicl. 0000001cbe991def, 56, 63 => 0000000000000001 (40000000 00000000)
++ rldicl. 0000001cbe991def, 63, 0 => 8000000e5f4c8ef7 (80000000 00000000)
++ rldicl. 0000001cbe991def, 63, 7 => 0000000e5f4c8ef7 (40000000 00000000)
++ rldicl. 0000001cbe991def, 63, 14 => 0000000e5f4c8ef7 (40000000 00000000)
++ rldicl. 0000001cbe991def, 63, 21 => 0000000e5f4c8ef7 (40000000 00000000)
++ rldicl. 0000001cbe991def, 63, 28 => 0000000e5f4c8ef7 (40000000 00000000)
++ rldicl. 0000001cbe991def, 63, 35 => 000000001f4c8ef7 (40000000 00000000)
++ rldicl. 0000001cbe991def, 63, 42 => 00000000000c8ef7 (40000000 00000000)
++ rldicl. 0000001cbe991def, 63, 49 => 0000000000000ef7 (40000000 00000000)
++ rldicl. 0000001cbe991def, 63, 56 => 00000000000000f7 (40000000 00000000)
++ rldicl. 0000001cbe991def, 63, 63 => 0000000000000001 (40000000 00000000)
++ rldicl. ffffffffffffffff, 0, 0 => ffffffffffffffff (80000000 00000000)
++ rldicl. ffffffffffffffff, 0, 7 => 01ffffffffffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 0, 14 => 0003ffffffffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 0, 21 => 000007ffffffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 0, 28 => 0000000fffffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 0, 35 => 000000001fffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 0, 42 => 00000000003fffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 0, 49 => 0000000000007fff (40000000 00000000)
++ rldicl. ffffffffffffffff, 0, 56 => 00000000000000ff (40000000 00000000)
++ rldicl. ffffffffffffffff, 0, 63 => 0000000000000001 (40000000 00000000)
++ rldicl. ffffffffffffffff, 7, 0 => ffffffffffffffff (80000000 00000000)
++ rldicl. ffffffffffffffff, 7, 7 => 01ffffffffffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 7, 14 => 0003ffffffffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 7, 21 => 000007ffffffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 7, 28 => 0000000fffffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 7, 35 => 000000001fffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 7, 42 => 00000000003fffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 7, 49 => 0000000000007fff (40000000 00000000)
++ rldicl. ffffffffffffffff, 7, 56 => 00000000000000ff (40000000 00000000)
++ rldicl. ffffffffffffffff, 7, 63 => 0000000000000001 (40000000 00000000)
++ rldicl. ffffffffffffffff, 14, 0 => ffffffffffffffff (80000000 00000000)
++ rldicl. ffffffffffffffff, 14, 7 => 01ffffffffffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 14, 14 => 0003ffffffffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 14, 21 => 000007ffffffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 14, 28 => 0000000fffffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 14, 35 => 000000001fffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 14, 42 => 00000000003fffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 14, 49 => 0000000000007fff (40000000 00000000)
++ rldicl. ffffffffffffffff, 14, 56 => 00000000000000ff (40000000 00000000)
++ rldicl. ffffffffffffffff, 14, 63 => 0000000000000001 (40000000 00000000)
++ rldicl. ffffffffffffffff, 21, 0 => ffffffffffffffff (80000000 00000000)
++ rldicl. ffffffffffffffff, 21, 7 => 01ffffffffffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 21, 14 => 0003ffffffffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 21, 21 => 000007ffffffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 21, 28 => 0000000fffffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 21, 35 => 000000001fffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 21, 42 => 00000000003fffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 21, 49 => 0000000000007fff (40000000 00000000)
++ rldicl. ffffffffffffffff, 21, 56 => 00000000000000ff (40000000 00000000)
++ rldicl. ffffffffffffffff, 21, 63 => 0000000000000001 (40000000 00000000)
++ rldicl. ffffffffffffffff, 28, 0 => ffffffffffffffff (80000000 00000000)
++ rldicl. ffffffffffffffff, 28, 7 => 01ffffffffffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 28, 14 => 0003ffffffffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 28, 21 => 000007ffffffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 28, 28 => 0000000fffffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 28, 35 => 000000001fffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 28, 42 => 00000000003fffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 28, 49 => 0000000000007fff (40000000 00000000)
++ rldicl. ffffffffffffffff, 28, 56 => 00000000000000ff (40000000 00000000)
++ rldicl. ffffffffffffffff, 28, 63 => 0000000000000001 (40000000 00000000)
++ rldicl. ffffffffffffffff, 35, 0 => ffffffffffffffff (80000000 00000000)
++ rldicl. ffffffffffffffff, 35, 7 => 01ffffffffffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 35, 14 => 0003ffffffffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 35, 21 => 000007ffffffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 35, 28 => 0000000fffffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 35, 35 => 000000001fffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 35, 42 => 00000000003fffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 35, 49 => 0000000000007fff (40000000 00000000)
++ rldicl. ffffffffffffffff, 35, 56 => 00000000000000ff (40000000 00000000)
++ rldicl. ffffffffffffffff, 35, 63 => 0000000000000001 (40000000 00000000)
++ rldicl. ffffffffffffffff, 42, 0 => ffffffffffffffff (80000000 00000000)
++ rldicl. ffffffffffffffff, 42, 7 => 01ffffffffffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 42, 14 => 0003ffffffffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 42, 21 => 000007ffffffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 42, 28 => 0000000fffffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 42, 35 => 000000001fffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 42, 42 => 00000000003fffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 42, 49 => 0000000000007fff (40000000 00000000)
++ rldicl. ffffffffffffffff, 42, 56 => 00000000000000ff (40000000 00000000)
++ rldicl. ffffffffffffffff, 42, 63 => 0000000000000001 (40000000 00000000)
++ rldicl. ffffffffffffffff, 49, 0 => ffffffffffffffff (80000000 00000000)
++ rldicl. ffffffffffffffff, 49, 7 => 01ffffffffffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 49, 14 => 0003ffffffffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 49, 21 => 000007ffffffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 49, 28 => 0000000fffffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 49, 35 => 000000001fffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 49, 42 => 00000000003fffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 49, 49 => 0000000000007fff (40000000 00000000)
++ rldicl. ffffffffffffffff, 49, 56 => 00000000000000ff (40000000 00000000)
++ rldicl. ffffffffffffffff, 49, 63 => 0000000000000001 (40000000 00000000)
++ rldicl. ffffffffffffffff, 56, 0 => ffffffffffffffff (80000000 00000000)
++ rldicl. ffffffffffffffff, 56, 7 => 01ffffffffffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 56, 14 => 0003ffffffffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 56, 21 => 000007ffffffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 56, 28 => 0000000fffffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 56, 35 => 000000001fffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 56, 42 => 00000000003fffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 56, 49 => 0000000000007fff (40000000 00000000)
++ rldicl. ffffffffffffffff, 56, 56 => 00000000000000ff (40000000 00000000)
++ rldicl. ffffffffffffffff, 56, 63 => 0000000000000001 (40000000 00000000)
++ rldicl. ffffffffffffffff, 63, 0 => ffffffffffffffff (80000000 00000000)
++ rldicl. ffffffffffffffff, 63, 7 => 01ffffffffffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 63, 14 => 0003ffffffffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 63, 21 => 000007ffffffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 63, 28 => 0000000fffffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 63, 35 => 000000001fffffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 63, 42 => 00000000003fffff (40000000 00000000)
++ rldicl. ffffffffffffffff, 63, 49 => 0000000000007fff (40000000 00000000)
++ rldicl. ffffffffffffffff, 63, 56 => 00000000000000ff (40000000 00000000)
++ rldicl. ffffffffffffffff, 63, 63 => 0000000000000001 (40000000 00000000)
++
++ rldicr. 0000000000000000, 0, 0 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 0, 7 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 0, 14 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 0, 21 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 0, 28 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 0, 35 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 0, 42 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 0, 49 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 0, 56 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 0, 63 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 7, 0 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 7, 7 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 7, 14 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 7, 21 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 7, 28 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 7, 35 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 7, 42 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 7, 49 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 7, 56 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 7, 63 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 14, 0 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 14, 7 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 14, 14 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 14, 21 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 14, 28 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 14, 35 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 14, 42 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 14, 49 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 14, 56 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 14, 63 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 21, 0 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 21, 7 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 21, 14 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 21, 21 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 21, 28 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 21, 35 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 21, 42 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 21, 49 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 21, 56 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 21, 63 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 28, 0 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 28, 7 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 28, 14 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 28, 21 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 28, 28 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 28, 35 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 28, 42 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 28, 49 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 28, 56 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 28, 63 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 35, 0 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 35, 7 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 35, 14 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 35, 21 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 35, 28 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 35, 35 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 35, 42 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 35, 49 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 35, 56 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 35, 63 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 42, 0 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 42, 7 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 42, 14 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 42, 21 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 42, 28 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 42, 35 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 42, 42 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 42, 49 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 42, 56 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 42, 63 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 49, 0 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 49, 7 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 49, 14 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 49, 21 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 49, 28 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 49, 35 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 49, 42 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 49, 49 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 49, 56 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 49, 63 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 56, 0 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 56, 7 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 56, 14 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 56, 21 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 56, 28 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 56, 35 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 56, 42 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 56, 49 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 56, 56 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 56, 63 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 63, 0 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 63, 7 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 63, 14 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 63, 21 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 63, 28 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 63, 35 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 63, 42 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 63, 49 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 63, 56 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000000000000000, 63, 63 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000001cbe991def, 0, 0 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000001cbe991def, 0, 7 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000001cbe991def, 0, 14 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000001cbe991def, 0, 21 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000001cbe991def, 0, 28 => 0000001800000000 (40000000 00000000)
++ rldicr. 0000001cbe991def, 0, 35 => 0000001cb0000000 (40000000 00000000)
++ rldicr. 0000001cbe991def, 0, 42 => 0000001cbe800000 (40000000 00000000)
++ rldicr. 0000001cbe991def, 0, 49 => 0000001cbe990000 (40000000 00000000)
++ rldicr. 0000001cbe991def, 0, 56 => 0000001cbe991d80 (40000000 00000000)
++ rldicr. 0000001cbe991def, 0, 63 => 0000001cbe991def (40000000 00000000)
++ rldicr. 0000001cbe991def, 7, 0 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000001cbe991def, 7, 7 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000001cbe991def, 7, 14 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000001cbe991def, 7, 21 => 00000c0000000000 (40000000 00000000)
++ rldicr. 0000001cbe991def, 7, 28 => 00000e5800000000 (40000000 00000000)
++ rldicr. 0000001cbe991def, 7, 35 => 00000e5f40000000 (40000000 00000000)
++ rldicr. 0000001cbe991def, 7, 42 => 00000e5f4c800000 (40000000 00000000)
++ rldicr. 0000001cbe991def, 7, 49 => 00000e5f4c8ec000 (40000000 00000000)
++ rldicr. 0000001cbe991def, 7, 56 => 00000e5f4c8ef780 (40000000 00000000)
++ rldicr. 0000001cbe991def, 7, 63 => 00000e5f4c8ef780 (40000000 00000000)
++ rldicr. 0000001cbe991def, 14, 0 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000001cbe991def, 14, 7 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000001cbe991def, 14, 14 => 0006000000000000 (40000000 00000000)
++ rldicr. 0000001cbe991def, 14, 21 => 00072c0000000000 (40000000 00000000)
++ rldicr. 0000001cbe991def, 14, 28 => 00072fa000000000 (40000000 00000000)
++ rldicr. 0000001cbe991def, 14, 35 => 00072fa640000000 (40000000 00000000)
++ rldicr. 0000001cbe991def, 14, 42 => 00072fa647600000 (40000000 00000000)
++ rldicr. 0000001cbe991def, 14, 49 => 00072fa6477bc000 (40000000 00000000)
++ rldicr. 0000001cbe991def, 14, 56 => 00072fa6477bc000 (40000000 00000000)
++ rldicr. 0000001cbe991def, 14, 63 => 00072fa6477bc000 (40000000 00000000)
++ rldicr. 0000001cbe991def, 21, 0 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000001cbe991def, 21, 7 => 0300000000000000 (40000000 00000000)
++ rldicr. 0000001cbe991def, 21, 14 => 0396000000000000 (40000000 00000000)
++ rldicr. 0000001cbe991def, 21, 21 => 0397d00000000000 (40000000 00000000)
++ rldicr. 0000001cbe991def, 21, 28 => 0397d32000000000 (40000000 00000000)
++ rldicr. 0000001cbe991def, 21, 35 => 0397d323b0000000 (40000000 00000000)
++ rldicr. 0000001cbe991def, 21, 42 => 0397d323bde00000 (40000000 00000000)
++ rldicr. 0000001cbe991def, 21, 49 => 0397d323bde00000 (40000000 00000000)
++ rldicr. 0000001cbe991def, 21, 56 => 0397d323bde00000 (40000000 00000000)
++ rldicr. 0000001cbe991def, 21, 63 => 0397d323bde00000 (40000000 00000000)
++ rldicr. 0000001cbe991def, 28, 0 => 8000000000000000 (80000000 00000000)
++ rldicr. 0000001cbe991def, 28, 7 => cb00000000000000 (80000000 00000000)
++ rldicr. 0000001cbe991def, 28, 14 => cbe8000000000000 (80000000 00000000)
++ rldicr. 0000001cbe991def, 28, 21 => cbe9900000000000 (80000000 00000000)
++ rldicr. 0000001cbe991def, 28, 28 => cbe991d800000000 (80000000 00000000)
++ rldicr. 0000001cbe991def, 28, 35 => cbe991def0000000 (80000000 00000000)
++ rldicr. 0000001cbe991def, 28, 42 => cbe991def0000000 (80000000 00000000)
++ rldicr. 0000001cbe991def, 28, 49 => cbe991def0000000 (80000000 00000000)
++ rldicr. 0000001cbe991def, 28, 56 => cbe991def0000000 (80000000 00000000)
++ rldicr. 0000001cbe991def, 28, 63 => cbe991def0000001 (80000000 00000000)
++ rldicr. 0000001cbe991def, 35, 0 => 8000000000000000 (80000000 00000000)
++ rldicr. 0000001cbe991def, 35, 7 => f400000000000000 (80000000 00000000)
++ rldicr. 0000001cbe991def, 35, 14 => f4c8000000000000 (80000000 00000000)
++ rldicr. 0000001cbe991def, 35, 21 => f4c8ec0000000000 (80000000 00000000)
++ rldicr. 0000001cbe991def, 35, 28 => f4c8ef7800000000 (80000000 00000000)
++ rldicr. 0000001cbe991def, 35, 35 => f4c8ef7800000000 (80000000 00000000)
++ rldicr. 0000001cbe991def, 35, 42 => f4c8ef7800000000 (80000000 00000000)
++ rldicr. 0000001cbe991def, 35, 49 => f4c8ef7800000000 (80000000 00000000)
++ rldicr. 0000001cbe991def, 35, 56 => f4c8ef7800000080 (80000000 00000000)
++ rldicr. 0000001cbe991def, 35, 63 => f4c8ef78000000e5 (80000000 00000000)
++ rldicr. 0000001cbe991def, 42, 0 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000001cbe991def, 42, 7 => 6400000000000000 (40000000 00000000)
++ rldicr. 0000001cbe991def, 42, 14 => 6476000000000000 (40000000 00000000)
++ rldicr. 0000001cbe991def, 42, 21 => 6477bc0000000000 (40000000 00000000)
++ rldicr. 0000001cbe991def, 42, 28 => 6477bc0000000000 (40000000 00000000)
++ rldicr. 0000001cbe991def, 42, 35 => 6477bc0000000000 (40000000 00000000)
++ rldicr. 0000001cbe991def, 42, 42 => 6477bc0000000000 (40000000 00000000)
++ rldicr. 0000001cbe991def, 42, 49 => 6477bc0000004000 (40000000 00000000)
++ rldicr. 0000001cbe991def, 42, 56 => 6477bc0000007280 (40000000 00000000)
++ rldicr. 0000001cbe991def, 42, 63 => 6477bc00000072fa (40000000 00000000)
++ rldicr. 0000001cbe991def, 49, 0 => 0000000000000000 (20000000 00000000)
++ rldicr. 0000001cbe991def, 49, 7 => 3b00000000000000 (40000000 00000000)
++ rldicr. 0000001cbe991def, 49, 14 => 3bde000000000000 (40000000 00000000)
++ rldicr. 0000001cbe991def, 49, 21 => 3bde000000000000 (40000000 00000000)
++ rldicr. 0000001cbe991def, 49, 28 => 3bde000000000000 (40000000 00000000)
++ rldicr. 0000001cbe991def, 49, 35 => 3bde000000000000 (40000000 00000000)
++ rldicr. 0000001cbe991def, 49, 42 => 3bde000000200000 (40000000 00000000)
++ rldicr. 0000001cbe991def, 49, 49 => 3bde000000394000 (40000000 00000000)
++ rldicr. 0000001cbe991def, 49, 56 => 3bde000000397d00 (40000000 00000000)
++ rldicr. 0000001cbe991def, 49, 63 => 3bde000000397d32 (40000000 00000000)
++ rldicr. 0000001cbe991def, 56, 0 => 8000000000000000 (80000000 00000000)
++ rldicr. 0000001cbe991def, 56, 7 => ef00000000000000 (80000000 00000000)
++ rldicr. 0000001cbe991def, 56, 14 => ef00000000000000 (80000000 00000000)
++ rldicr. 0000001cbe991def, 56, 21 => ef00000000000000 (80000000 00000000)
++ rldicr. 0000001cbe991def, 56, 28 => ef00000000000000 (80000000 00000000)
++ rldicr. 0000001cbe991def, 56, 35 => ef00000010000000 (80000000 00000000)
++ rldicr. 0000001cbe991def, 56, 42 => ef0000001ca00000 (80000000 00000000)
++ rldicr. 0000001cbe991def, 56, 49 => ef0000001cbe8000 (80000000 00000000)
++ rldicr. 0000001cbe991def, 56, 56 => ef0000001cbe9900 (80000000 00000000)
++ rldicr. 0000001cbe991def, 56, 63 => ef0000001cbe991d (80000000 00000000)
++ rldicr. 0000001cbe991def, 63, 0 => 8000000000000000 (80000000 00000000)
++ rldicr. 0000001cbe991def, 63, 7 => 8000000000000000 (80000000 00000000)
++ rldicr. 0000001cbe991def, 63, 14 => 8000000000000000 (80000000 00000000)
++ rldicr. 0000001cbe991def, 63, 21 => 8000000000000000 (80000000 00000000)
++ rldicr. 0000001cbe991def, 63, 28 => 8000000800000000 (80000000 00000000)
++ rldicr. 0000001cbe991def, 63, 35 => 8000000e50000000 (80000000 00000000)
++ rldicr. 0000001cbe991def, 63, 42 => 8000000e5f400000 (80000000 00000000)
++ rldicr. 0000001cbe991def, 63, 49 => 8000000e5f4c8000 (80000000 00000000)
++ rldicr. 0000001cbe991def, 63, 56 => 8000000e5f4c8e80 (80000000 00000000)
++ rldicr. 0000001cbe991def, 63, 63 => 8000000e5f4c8ef7 (80000000 00000000)
++ rldicr. ffffffffffffffff, 0, 0 => 8000000000000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 0, 7 => ff00000000000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 0, 14 => fffe000000000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 0, 21 => fffffc0000000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 0, 28 => fffffff800000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 0, 35 => fffffffff0000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 0, 42 => ffffffffffe00000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 0, 49 => ffffffffffffc000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 0, 56 => ffffffffffffff80 (80000000 00000000)
++ rldicr. ffffffffffffffff, 0, 63 => ffffffffffffffff (80000000 00000000)
++ rldicr. ffffffffffffffff, 7, 0 => 8000000000000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 7, 7 => ff00000000000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 7, 14 => fffe000000000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 7, 21 => fffffc0000000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 7, 28 => fffffff800000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 7, 35 => fffffffff0000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 7, 42 => ffffffffffe00000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 7, 49 => ffffffffffffc000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 7, 56 => ffffffffffffff80 (80000000 00000000)
++ rldicr. ffffffffffffffff, 7, 63 => ffffffffffffffff (80000000 00000000)
++ rldicr. ffffffffffffffff, 14, 0 => 8000000000000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 14, 7 => ff00000000000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 14, 14 => fffe000000000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 14, 21 => fffffc0000000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 14, 28 => fffffff800000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 14, 35 => fffffffff0000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 14, 42 => ffffffffffe00000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 14, 49 => ffffffffffffc000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 14, 56 => ffffffffffffff80 (80000000 00000000)
++ rldicr. ffffffffffffffff, 14, 63 => ffffffffffffffff (80000000 00000000)
++ rldicr. ffffffffffffffff, 21, 0 => 8000000000000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 21, 7 => ff00000000000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 21, 14 => fffe000000000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 21, 21 => fffffc0000000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 21, 28 => fffffff800000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 21, 35 => fffffffff0000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 21, 42 => ffffffffffe00000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 21, 49 => ffffffffffffc000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 21, 56 => ffffffffffffff80 (80000000 00000000)
++ rldicr. ffffffffffffffff, 21, 63 => ffffffffffffffff (80000000 00000000)
++ rldicr. ffffffffffffffff, 28, 0 => 8000000000000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 28, 7 => ff00000000000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 28, 14 => fffe000000000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 28, 21 => fffffc0000000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 28, 28 => fffffff800000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 28, 35 => fffffffff0000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 28, 42 => ffffffffffe00000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 28, 49 => ffffffffffffc000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 28, 56 => ffffffffffffff80 (80000000 00000000)
++ rldicr. ffffffffffffffff, 28, 63 => ffffffffffffffff (80000000 00000000)
++ rldicr. ffffffffffffffff, 35, 0 => 8000000000000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 35, 7 => ff00000000000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 35, 14 => fffe000000000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 35, 21 => fffffc0000000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 35, 28 => fffffff800000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 35, 35 => fffffffff0000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 35, 42 => ffffffffffe00000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 35, 49 => ffffffffffffc000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 35, 56 => ffffffffffffff80 (80000000 00000000)
++ rldicr. ffffffffffffffff, 35, 63 => ffffffffffffffff (80000000 00000000)
++ rldicr. ffffffffffffffff, 42, 0 => 8000000000000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 42, 7 => ff00000000000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 42, 14 => fffe000000000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 42, 21 => fffffc0000000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 42, 28 => fffffff800000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 42, 35 => fffffffff0000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 42, 42 => ffffffffffe00000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 42, 49 => ffffffffffffc000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 42, 56 => ffffffffffffff80 (80000000 00000000)
++ rldicr. ffffffffffffffff, 42, 63 => ffffffffffffffff (80000000 00000000)
++ rldicr. ffffffffffffffff, 49, 0 => 8000000000000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 49, 7 => ff00000000000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 49, 14 => fffe000000000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 49, 21 => fffffc0000000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 49, 28 => fffffff800000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 49, 35 => fffffffff0000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 49, 42 => ffffffffffe00000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 49, 49 => ffffffffffffc000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 49, 56 => ffffffffffffff80 (80000000 00000000)
++ rldicr. ffffffffffffffff, 49, 63 => ffffffffffffffff (80000000 00000000)
++ rldicr. ffffffffffffffff, 56, 0 => 8000000000000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 56, 7 => ff00000000000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 56, 14 => fffe000000000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 56, 21 => fffffc0000000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 56, 28 => fffffff800000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 56, 35 => fffffffff0000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 56, 42 => ffffffffffe00000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 56, 49 => ffffffffffffc000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 56, 56 => ffffffffffffff80 (80000000 00000000)
++ rldicr. ffffffffffffffff, 56, 63 => ffffffffffffffff (80000000 00000000)
++ rldicr. ffffffffffffffff, 63, 0 => 8000000000000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 63, 7 => ff00000000000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 63, 14 => fffe000000000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 63, 21 => fffffc0000000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 63, 28 => fffffff800000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 63, 35 => fffffffff0000000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 63, 42 => ffffffffffe00000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 63, 49 => ffffffffffffc000 (80000000 00000000)
++ rldicr. ffffffffffffffff, 63, 56 => ffffffffffffff80 (80000000 00000000)
++ rldicr. ffffffffffffffff, 63, 63 => ffffffffffffffff (80000000 00000000)
++
++ rldimi. 0000000000000000, 0, 0 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 0, 7 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 0, 14 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 0, 21 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 0, 28 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 0, 35 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 0, 42 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 0, 49 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 0, 56 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 0, 63 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 7, 0 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 7, 7 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 7, 14 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 7, 21 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 7, 28 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 7, 35 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 7, 42 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 7, 49 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 7, 56 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 7, 63 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 14, 0 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 14, 7 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 14, 14 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 14, 21 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 14, 28 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 14, 35 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 14, 42 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 14, 49 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 14, 56 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 14, 63 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 21, 0 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 21, 7 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 21, 14 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 21, 21 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 21, 28 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 21, 35 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 21, 42 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 21, 49 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 21, 56 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 21, 63 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 28, 0 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 28, 7 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 28, 14 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 28, 21 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 28, 28 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 28, 35 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 28, 42 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 28, 49 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 28, 56 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 28, 63 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 35, 0 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 35, 7 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 35, 14 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 35, 21 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 35, 28 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 35, 35 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 35, 42 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 35, 49 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 35, 56 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 35, 63 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 42, 0 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 42, 7 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 42, 14 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 42, 21 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 42, 28 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 42, 35 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 42, 42 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 42, 49 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 42, 56 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 42, 63 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 49, 0 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 49, 7 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 49, 14 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 49, 21 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 49, 28 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 49, 35 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 49, 42 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 49, 49 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 49, 56 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 49, 63 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 56, 0 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 56, 7 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 56, 14 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 56, 21 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 56, 28 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 56, 35 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 56, 42 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 56, 49 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 56, 56 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 56, 63 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 63, 0 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 63, 7 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 63, 14 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 63, 21 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 63, 28 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 63, 35 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 63, 42 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 63, 49 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 63, 56 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000000000000000, 63, 63 => 0000000000000000 (20000000 00000000)
++ rldimi. 0000001cbe991def, 0, 0 => 0000001cbe991def (40000000 00000000)
++ rldimi. 0000001cbe991def, 0, 7 => 0000001cbe991def (40000000 00000000)
++ rldimi. 0000001cbe991def, 0, 14 => 0000001cbe991def (40000000 00000000)
++ rldimi. 0000001cbe991def, 0, 21 => 0000001cbe991def (40000000 00000000)
++ rldimi. 0000001cbe991def, 0, 28 => 0000001cbe991def (40000000 00000000)
++ rldimi. 0000001cbe991def, 0, 35 => 0000001cbe991def (40000000 00000000)
++ rldimi. 0000001cbe991def, 0, 42 => 0000001cbe991def (40000000 00000000)
++ rldimi. 0000001cbe991def, 0, 49 => 0000001cbe991def (40000000 00000000)
++ rldimi. 0000001cbe991def, 0, 56 => 0000001cbe991def (40000000 00000000)
++ rldimi. 0000001cbe991def, 0, 63 => 0000001cbe991def (40000000 00000000)
++ rldimi. 0000001cbe991def, 7, 0 => 00000e5f4c8ef7ef (40000000 00000000)
++ rldimi. 0000001cbe991def, 7, 7 => 00000e5f4c8ef7ef (40000000 00000000)
++ rldimi. 0000001cbe991def, 7, 14 => 00000e5f4c8ef7ef (40000000 00000000)
++ rldimi. 0000001cbe991def, 7, 21 => 00000e5f4c8ef7ef (40000000 00000000)
++ rldimi. 0000001cbe991def, 7, 28 => 00000e5f4c8ef7ef (40000000 00000000)
++ rldimi. 0000001cbe991def, 7, 35 => 00000e5f4c8ef7ef (40000000 00000000)
++ rldimi. 0000001cbe991def, 7, 42 => 00000e5f4c8ef7ef (40000000 00000000)
++ rldimi. 0000001cbe991def, 7, 49 => 00000e5f4c8ef7ef (40000000 00000000)
++ rldimi. 0000001cbe991def, 7, 56 => 00000e5f4c8ef7ef (40000000 00000000)
++ rldimi. 0000001cbe991def, 7, 63 => 00000e5f4c8ef7ee (40000000 00000000)
++ rldimi. 0000001cbe991def, 14, 0 => 00072fa6477bf7ee (40000000 00000000)
++ rldimi. 0000001cbe991def, 14, 7 => 00072fa6477bf7ee (40000000 00000000)
++ rldimi. 0000001cbe991def, 14, 14 => 00072fa6477bf7ee (40000000 00000000)
++ rldimi. 0000001cbe991def, 14, 21 => 00072fa6477bf7ee (40000000 00000000)
++ rldimi. 0000001cbe991def, 14, 28 => 00072fa6477bf7ee (40000000 00000000)
++ rldimi. 0000001cbe991def, 14, 35 => 00072fa6477bf7ee (40000000 00000000)
++ rldimi. 0000001cbe991def, 14, 42 => 00072fa6477bf7ee (40000000 00000000)
++ rldimi. 0000001cbe991def, 14, 49 => 00072fa6477bf7ee (40000000 00000000)
++ rldimi. 0000001cbe991def, 14, 56 => 00072fa6477bf700 (40000000 00000000)
++ rldimi. 0000001cbe991def, 14, 63 => 00072fa6477bf700 (40000000 00000000)
++ rldimi. 0000001cbe991def, 21, 0 => 0397d323bdfbf700 (40000000 00000000)
++ rldimi. 0000001cbe991def, 21, 7 => 0397d323bdfbf700 (40000000 00000000)
++ rldimi. 0000001cbe991def, 21, 14 => 0397d323bdfbf700 (40000000 00000000)
++ rldimi. 0000001cbe991def, 21, 21 => 0397d323bdfbf700 (40000000 00000000)
++ rldimi. 0000001cbe991def, 21, 28 => 0397d323bdfbf700 (40000000 00000000)
++ rldimi. 0000001cbe991def, 21, 35 => 0397d323bdfbf700 (40000000 00000000)
++ rldimi. 0000001cbe991def, 21, 42 => 0397d323bdfbf700 (40000000 00000000)
++ rldimi. 0000001cbe991def, 21, 49 => 0397d323bdfb8000 (40000000 00000000)
++ rldimi. 0000001cbe991def, 21, 56 => 0397d323bdfb8000 (40000000 00000000)
++ rldimi. 0000001cbe991def, 21, 63 => 0397d323bdfb8000 (40000000 00000000)
++ rldimi. 0000001cbe991def, 28, 0 => cbe991defdfb8000 (80000000 00000000)
++ rldimi. 0000001cbe991def, 28, 7 => cbe991defdfb8000 (80000000 00000000)
++ rldimi. 0000001cbe991def, 28, 14 => cbe991defdfb8000 (80000000 00000000)
++ rldimi. 0000001cbe991def, 28, 21 => cbe991defdfb8000 (80000000 00000000)
++ rldimi. 0000001cbe991def, 28, 28 => cbe991defdfb8000 (80000000 00000000)
++ rldimi. 0000001cbe991def, 28, 35 => cbe991defdfb8000 (80000000 00000000)
++ rldimi. 0000001cbe991def, 28, 42 => cbe991defdc00001 (80000000 00000000)
++ rldimi. 0000001cbe991def, 28, 49 => cbe991defdc00001 (80000000 00000000)
++ rldimi. 0000001cbe991def, 28, 56 => cbe991defdc00001 (80000000 00000000)
++ rldimi. 0000001cbe991def, 28, 63 => cbe991defdc00001 (80000000 00000000)
++ rldimi. 0000001cbe991def, 35, 0 => f4c8ef7efdc00001 (80000000 00000000)
++ rldimi. 0000001cbe991def, 35, 7 => f4c8ef7efdc00001 (80000000 00000000)
++ rldimi. 0000001cbe991def, 35, 14 => f4c8ef7efdc00001 (80000000 00000000)
++ rldimi. 0000001cbe991def, 35, 21 => f4c8ef7efdc00001 (80000000 00000000)
++ rldimi. 0000001cbe991def, 35, 28 => f4c8ef7efdc00001 (80000000 00000000)
++ rldimi. 0000001cbe991def, 35, 35 => f4c8ef7ee00000e5 (80000000 00000000)
++ rldimi. 0000001cbe991def, 35, 42 => f4c8ef7ee00000e5 (80000000 00000000)
++ rldimi. 0000001cbe991def, 35, 49 => f4c8ef7ee00000e5 (80000000 00000000)
++ rldimi. 0000001cbe991def, 35, 56 => f4c8ef7ee00000e5 (80000000 00000000)
++ rldimi. 0000001cbe991def, 35, 63 => f4c8ef7ee00000e5 (80000000 00000000)
++ rldimi. 0000001cbe991def, 42, 0 => 6477bf7ee00000e5 (40000000 00000000)
++ rldimi. 0000001cbe991def, 42, 7 => 6477bf7ee00000e5 (40000000 00000000)
++ rldimi. 0000001cbe991def, 42, 14 => 6477bf7ee00000e5 (40000000 00000000)
++ rldimi. 0000001cbe991def, 42, 21 => 6477bf7ee00000e5 (40000000 00000000)
++ rldimi. 0000001cbe991def, 42, 28 => 6477bf70000072fa (40000000 00000000)
++ rldimi. 0000001cbe991def, 42, 35 => 6477bf70000072fa (40000000 00000000)
++ rldimi. 0000001cbe991def, 42, 42 => 6477bf70000072fa (40000000 00000000)
++ rldimi. 0000001cbe991def, 42, 49 => 6477bf70000072fa (40000000 00000000)
++ rldimi. 0000001cbe991def, 42, 56 => 6477bf70000072fa (40000000 00000000)
++ rldimi. 0000001cbe991def, 42, 63 => 6477bf70000072fa (40000000 00000000)
++ rldimi. 0000001cbe991def, 49, 0 => 3bdfbf70000072fa (40000000 00000000)
++ rldimi. 0000001cbe991def, 49, 7 => 3bdfbf70000072fa (40000000 00000000)
++ rldimi. 0000001cbe991def, 49, 14 => 3bdfbf70000072fa (40000000 00000000)
++ rldimi. 0000001cbe991def, 49, 21 => 3bdfb80000397d32 (40000000 00000000)
++ rldimi. 0000001cbe991def, 49, 28 => 3bdfb80000397d32 (40000000 00000000)
++ rldimi. 0000001cbe991def, 49, 35 => 3bdfb80000397d32 (40000000 00000000)
++ rldimi. 0000001cbe991def, 49, 42 => 3bdfb80000397d32 (40000000 00000000)
++ rldimi. 0000001cbe991def, 49, 49 => 3bdfb80000397d32 (40000000 00000000)
++ rldimi. 0000001cbe991def, 49, 56 => 3bdfb80000397d32 (40000000 00000000)
++ rldimi. 0000001cbe991def, 49, 63 => 3bdfb80000397d32 (40000000 00000000)
++ rldimi. 0000001cbe991def, 56, 0 => efdfb80000397d32 (80000000 00000000)
++ rldimi. 0000001cbe991def, 56, 7 => efdfb80000397d32 (80000000 00000000)
++ rldimi. 0000001cbe991def, 56, 14 => efdc00001cbe991d (80000000 00000000)
++ rldimi. 0000001cbe991def, 56, 21 => efdc00001cbe991d (80000000 00000000)
++ rldimi. 0000001cbe991def, 56, 28 => efdc00001cbe991d (80000000 00000000)
++ rldimi. 0000001cbe991def, 56, 35 => efdc00001cbe991d (80000000 00000000)
++ rldimi. 0000001cbe991def, 56, 42 => efdc00001cbe991d (80000000 00000000)
++ rldimi. 0000001cbe991def, 56, 49 => efdc00001cbe991d (80000000 00000000)
++ rldimi. 0000001cbe991def, 56, 56 => efdc00001cbe991d (80000000 00000000)
++ rldimi. 0000001cbe991def, 56, 63 => efdc00001cbe991d (80000000 00000000)
++ rldimi. 0000001cbe991def, 63, 0 => efdc00001cbe991d (80000000 00000000)
++ rldimi. 0000001cbe991def, 63, 7 => ee00000e5f4c8ef7 (80000000 00000000)
++ rldimi. 0000001cbe991def, 63, 14 => ee00000e5f4c8ef7 (80000000 00000000)
++ rldimi. 0000001cbe991def, 63, 21 => ee00000e5f4c8ef7 (80000000 00000000)
++ rldimi. 0000001cbe991def, 63, 28 => ee00000e5f4c8ef7 (80000000 00000000)
++ rldimi. 0000001cbe991def, 63, 35 => ee00000e5f4c8ef7 (80000000 00000000)
++ rldimi. 0000001cbe991def, 63, 42 => ee00000e5f4c8ef7 (80000000 00000000)
++ rldimi. 0000001cbe991def, 63, 49 => ee00000e5f4c8ef7 (80000000 00000000)
++ rldimi. 0000001cbe991def, 63, 56 => ee00000e5f4c8ef7 (80000000 00000000)
++ rldimi. 0000001cbe991def, 63, 63 => ee00000e5f4c8ef7 (80000000 00000000)
++ rldimi. ffffffffffffffff, 0, 0 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 0, 7 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 0, 14 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 0, 21 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 0, 28 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 0, 35 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 0, 42 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 0, 49 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 0, 56 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 0, 63 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 7, 0 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 7, 7 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 7, 14 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 7, 21 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 7, 28 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 7, 35 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 7, 42 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 7, 49 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 7, 56 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 7, 63 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 14, 0 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 14, 7 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 14, 14 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 14, 21 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 14, 28 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 14, 35 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 14, 42 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 14, 49 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 14, 56 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 14, 63 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 21, 0 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 21, 7 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 21, 14 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 21, 21 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 21, 28 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 21, 35 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 21, 42 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 21, 49 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 21, 56 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 21, 63 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 28, 0 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 28, 7 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 28, 14 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 28, 21 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 28, 28 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 28, 35 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 28, 42 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 28, 49 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 28, 56 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 28, 63 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 35, 0 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 35, 7 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 35, 14 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 35, 21 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 35, 28 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 35, 35 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 35, 42 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 35, 49 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 35, 56 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 35, 63 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 42, 0 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 42, 7 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 42, 14 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 42, 21 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 42, 28 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 42, 35 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 42, 42 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 42, 49 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 42, 56 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 42, 63 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 49, 0 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 49, 7 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 49, 14 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 49, 21 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 49, 28 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 49, 35 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 49, 42 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 49, 49 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 49, 56 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 49, 63 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 56, 0 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 56, 7 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 56, 14 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 56, 21 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 56, 28 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 56, 35 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 56, 42 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 56, 49 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 56, 56 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 56, 63 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 63, 0 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 63, 7 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 63, 14 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 63, 21 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 63, 28 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 63, 35 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 63, 42 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 63, 49 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 63, 56 => ffffffffffffffff (80000000 00000000)
++ rldimi. ffffffffffffffff, 63, 63 => ffffffffffffffff (80000000 00000000)
++
++ sradi. 0000000000000000, 0 => 0000000000000000 (20000000 00000000)
++ sradi. 0000000000000000, 7 => 0000000000000000 (20000000 00000000)
++ sradi. 0000000000000000, 14 => 0000000000000000 (20000000 00000000)
++ sradi. 0000000000000000, 21 => 0000000000000000 (20000000 00000000)
++ sradi. 0000000000000000, 28 => 0000000000000000 (20000000 00000000)
++ sradi. 0000000000000000, 35 => 0000000000000000 (20000000 00000000)
++ sradi. 0000000000000000, 42 => 0000000000000000 (20000000 00000000)
++ sradi. 0000000000000000, 49 => 0000000000000000 (20000000 00000000)
++ sradi. 0000000000000000, 56 => 0000000000000000 (20000000 00000000)
++ sradi. 0000000000000000, 63 => 0000000000000000 (20000000 00000000)
++ sradi. 0000001cbe991def, 0 => 0000001cbe991def (40000000 00000000)
++ sradi. 0000001cbe991def, 7 => 00000000397d323b (40000000 00000000)
++ sradi. 0000001cbe991def, 14 => 000000000072fa64 (40000000 00000000)
++ sradi. 0000001cbe991def, 21 => 000000000000e5f4 (40000000 00000000)
++ sradi. 0000001cbe991def, 28 => 00000000000001cb (40000000 00000000)
++ sradi. 0000001cbe991def, 35 => 0000000000000003 (40000000 00000000)
++ sradi. 0000001cbe991def, 42 => 0000000000000000 (20000000 00000000)
++ sradi. 0000001cbe991def, 49 => 0000000000000000 (20000000 00000000)
++ sradi. 0000001cbe991def, 56 => 0000000000000000 (20000000 00000000)
++ sradi. 0000001cbe991def, 63 => 0000000000000000 (20000000 00000000)
++ sradi. ffffffffffffffff, 0 => ffffffffffffffff (80000000 00000000)
++ sradi. ffffffffffffffff, 7 => ffffffffffffffff (80000000 20000000)
++ sradi. ffffffffffffffff, 14 => ffffffffffffffff (80000000 20000000)
++ sradi. ffffffffffffffff, 21 => ffffffffffffffff (80000000 20000000)
++ sradi. ffffffffffffffff, 28 => ffffffffffffffff (80000000 20000000)
++ sradi. ffffffffffffffff, 35 => ffffffffffffffff (80000000 20000000)
++ sradi. ffffffffffffffff, 42 => ffffffffffffffff (80000000 20000000)
++ sradi. ffffffffffffffff, 49 => ffffffffffffffff (80000000 20000000)
++ sradi. ffffffffffffffff, 56 => ffffffffffffffff (80000000 20000000)
++ sradi. ffffffffffffffff, 63 => ffffffffffffffff (80000000 20000000)
++
++PPC integer load insns
++ with one register + one 16 bits immediate args with flags update:
++ lbz 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
++ lbz 7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
++ lbz 15, (ffffffffffffffff) => 0000000000000000, 0 (00000000 00000000)
++ lbz 1, (00000000ffffffff) => 00000000000000ff, 0 (00000000 00000000)
++ lbz -7, (00000000be991def) => 000000000000001d, 0 (00000000 00000000)
++ lbz -15, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
++
++ lbzu 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
++ lbzu 7, (0000001cbe991def) => 0000000000000000, 7 (00000000 00000000)
++ lbzu 15, (ffffffffffffffff) => 0000000000000000, 15 (00000000 00000000)
++ lbzu 1, (00000000ffffffff) => 00000000000000ff, 1 (00000000 00000000)
++ lbzu -7, (00000000be991def) => 000000000000001d, -7 (00000000 00000000)
++ lbzu -15, (0000000000000000) => 0000000000000000, -15 (00000000 00000000)
++
++ lha 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
++ lha 7, (0000001cbe991def) => ffffffffffffef00, 0 (00000000 00000000)
++ lha 15, (ffffffffffffffff) => ffffffffffffff00, 0 (00000000 00000000)
++ lha 1, (00000000ffffffff) => ffffffffffffffff, 0 (00000000 00000000)
++ lha -7, (00000000be991def) => ffffffffffff991d, 0 (00000000 00000000)
++ lha -15, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
++
++ lhau 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
++ lhau 7, (0000001cbe991def) => ffffffffffffef00, 7 (00000000 00000000)
++ lhau 15, (ffffffffffffffff) => ffffffffffffff00, 15 (00000000 00000000)
++ lhau 1, (00000000ffffffff) => ffffffffffffffff, 1 (00000000 00000000)
++ lhau -7, (00000000be991def) => ffffffffffff991d, -7 (00000000 00000000)
++ lhau -15, (0000000000000000) => 0000000000000000, -15 (00000000 00000000)
++
++ lhz 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
++ lhz 7, (0000001cbe991def) => 000000000000ef00, 0 (00000000 00000000)
++ lhz 15, (ffffffffffffffff) => 000000000000ff00, 0 (00000000 00000000)
++ lhz 1, (00000000ffffffff) => 000000000000ffff, 0 (00000000 00000000)
++ lhz -7, (00000000be991def) => 000000000000991d, 0 (00000000 00000000)
++ lhz -15, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
++
++ lhzu 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
++ lhzu 7, (0000001cbe991def) => 000000000000ef00, 7 (00000000 00000000)
++ lhzu 15, (ffffffffffffffff) => 000000000000ff00, 15 (00000000 00000000)
++ lhzu 1, (00000000ffffffff) => 000000000000ffff, 1 (00000000 00000000)
++ lhzu -7, (00000000be991def) => 000000000000991d, -7 (00000000 00000000)
++ lhzu -15, (0000000000000000) => 0000000000000000, -15 (00000000 00000000)
++
++ lwz 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
++ lwz 7, (0000001cbe991def) => 00000000991def00, 0 (00000000 00000000)
++ lwz 15, (ffffffffffffffff) => 00000000ffffff00, 0 (00000000 00000000)
++ lwz 1, (00000000ffffffff) => 00000000ffffffff, 0 (00000000 00000000)
++ lwz -7, (00000000be991def) => 000000001cbe991d, 0 (00000000 00000000)
++ lwz -15, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
++
++ lwzu 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
++ lwzu 7, (0000001cbe991def) => 00000000991def00, 7 (00000000 00000000)
++ lwzu 15, (ffffffffffffffff) => 00000000ffffff00, 15 (00000000 00000000)
++ lwzu 1, (00000000ffffffff) => 00000000ffffffff, 1 (00000000 00000000)
++ lwzu -7, (00000000be991def) => 000000001cbe991d, -7 (00000000 00000000)
++ lwzu -15, (0000000000000000) => 0000000000000000, -15 (00000000 00000000)
++
++ ld 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
++ ld 7, (0000001cbe991def) => be991def00000000, 0 (00000000 00000000)
++ ld 15, (ffffffffffffffff) => ffffffff0000001c, 0 (00000000 00000000)
++ ld 1, (00000000ffffffff) => ffffffffffffffff, 0 (00000000 00000000)
++ ld -7, (00000000be991def) => 0000001cbe991def, -8 (00000000 00000000)
++ ld -15, (0000000000000000) => 0000000000000000, -16 (00000000 00000000)
++
++ ldu 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
++ ldu 7, (0000001cbe991def) => be991def00000000, 4 (00000000 00000000)
++ ldu 15, (ffffffffffffffff) => ffffffff0000001c, 12 (00000000 00000000)
++ ldu 1, (00000000ffffffff) => ffffffffffffffff, 0 (00000000 00000000)
++ ldu -7, (00000000be991def) => 0000001cbe991def, -8 (00000000 00000000)
++ ldu -15, (0000000000000000) => 0000000000000000, -16 (00000000 00000000)
++
++ lwa 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
++ lwa 7, (0000001cbe991def) => 0000000000000000, 0 (00000000 00000000)
++ lwa 15, (ffffffffffffffff) => 000000000000001c, 0 (00000000 00000000)
++ lwa 1, (00000000ffffffff) => ffffffffffffffff, 0 (00000000 00000000)
++ lwa -7, (00000000be991def) => 0000001cbe991def, -8 (00000000 00000000)
++ lwa -15, (0000000000000000) => 0000000000000000, -16 (00000000 00000000)
++
++PPC integer load insns with two register args:
++ lbzx 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
++ lbzx 8, (0000001cbe991def) => 00000000000000ef, 0 (00000000 00000000)
++ lbzx 16, (ffffffffffffffff) => 00000000000000ff, 0 (00000000 00000000)
++
++ lbzux 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
++ lbzux 8, (0000001cbe991def) => 00000000000000ef, 8 (00000000 00000000)
++ lbzux 16, (ffffffffffffffff) => 00000000000000ff, 16 (00000000 00000000)
++
++ lhax 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
++ lhax 8, (0000001cbe991def) => 0000000000001def, 0 (00000000 00000000)
++ lhax 16, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
++
++ lhaux 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
++ lhaux 8, (0000001cbe991def) => 0000000000001def, 8 (00000000 00000000)
++ lhaux 16, (ffffffffffffffff) => ffffffffffffffff, 16 (00000000 00000000)
++
++ lhzx 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
++ lhzx 8, (0000001cbe991def) => 0000000000001def, 0 (00000000 00000000)
++ lhzx 16, (ffffffffffffffff) => 000000000000ffff, 0 (00000000 00000000)
++
++ lhzux 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
++ lhzux 8, (0000001cbe991def) => 0000000000001def, 8 (00000000 00000000)
++ lhzux 16, (ffffffffffffffff) => 000000000000ffff, 16 (00000000 00000000)
++
++ lwzx 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
++ lwzx 8, (0000001cbe991def) => 00000000be991def, 0 (00000000 00000000)
++ lwzx 16, (ffffffffffffffff) => 00000000ffffffff, 0 (00000000 00000000)
++
++ lwzux 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
++ lwzux 8, (0000001cbe991def) => 00000000be991def, 8 (00000000 00000000)
++ lwzux 16, (ffffffffffffffff) => 00000000ffffffff, 16 (00000000 00000000)
++
++ ldx 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
++ ldx 8, (0000001cbe991def) => 0000001cbe991def, 0 (00000000 00000000)
++ ldx 16, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
++
++ ldux 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
++ ldux 8, (0000001cbe991def) => 0000001cbe991def, 8 (00000000 00000000)
++ ldux 16, (ffffffffffffffff) => ffffffffffffffff, 16 (00000000 00000000)
++
++ lwax 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
++ lwax 8, (0000001cbe991def) => ffffffffbe991def, 0 (00000000 00000000)
++ lwax 16, (ffffffffffffffff) => ffffffffffffffff, 0 (00000000 00000000)
++
++ lwaux 0, (0000000000000000) => 0000000000000000, 0 (00000000 00000000)
++ lwaux 8, (0000001cbe991def) => ffffffffbe991def, 8 (00000000 00000000)
++ lwaux 16, (ffffffffffffffff) => ffffffffffffffff, 16 (00000000 00000000)
++
++PPC integer store insns
++ with one register + one 16 bits immediate args with flags update:
++ stb 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
++ stb 0000001cbe991def, 8 => 00000000000000ef, 0 (00000000 00000000)
++ stb ffffffffffffffff, 16 => 00000000000000ff, 0 (00000000 00000000)
++ stb 0000000000000000, -16 => 0000000000000000, 0 (00000000 00000000)
++ stb 0000001cbe991def, -8 => 00000000000000ef, 0 (00000000 00000000)
++ stb ffffffffffffffff, 0 => 00000000000000ff, 0 (00000000 00000000)
++
++ stbu 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
++ stbu 0000001cbe991def, 8 => 00000000000000ef, 8 (00000000 00000000)
++ stbu ffffffffffffffff, 16 => 00000000000000ff, 16 (00000000 00000000)
++ stbu 0000000000000000, -16 => 0000000000000000, -16 (00000000 00000000)
++ stbu 0000001cbe991def, -8 => 00000000000000ef, -8 (00000000 00000000)
++ stbu ffffffffffffffff, 0 => 00000000000000ff, 0 (00000000 00000000)
++
++ sth 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
++ sth 0000001cbe991def, 8 => 0000000000001def, 0 (00000000 00000000)
++ sth ffffffffffffffff, 16 => 000000000000ffff, 0 (00000000 00000000)
++ sth 0000000000000000, -16 => 0000000000000000, 0 (00000000 00000000)
++ sth 0000001cbe991def, -8 => 0000000000001def, 0 (00000000 00000000)
++ sth ffffffffffffffff, 0 => 000000000000ffff, 0 (00000000 00000000)
++
++ sthu 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
++ sthu 0000001cbe991def, 8 => 0000000000001def, 8 (00000000 00000000)
++ sthu ffffffffffffffff, 16 => 000000000000ffff, 16 (00000000 00000000)
++ sthu 0000000000000000, -16 => 0000000000000000, -16 (00000000 00000000)
++ sthu 0000001cbe991def, -8 => 0000000000001def, -8 (00000000 00000000)
++ sthu ffffffffffffffff, 0 => 000000000000ffff, 0 (00000000 00000000)
++
++ stw 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
++ stw 0000001cbe991def, 8 => 00000000be991def, 0 (00000000 00000000)
++ stw ffffffffffffffff, 16 => 00000000ffffffff, 0 (00000000 00000000)
++ stw 0000000000000000, -16 => 0000000000000000, 0 (00000000 00000000)
++ stw 0000001cbe991def, -8 => 00000000be991def, 0 (00000000 00000000)
++ stw ffffffffffffffff, 0 => 00000000ffffffff, 0 (00000000 00000000)
++
++ stwu 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
++ stwu 0000001cbe991def, 8 => 00000000be991def, 8 (00000000 00000000)
++ stwu ffffffffffffffff, 16 => 00000000ffffffff, 16 (00000000 00000000)
++ stwu 0000000000000000, -16 => 0000000000000000, -16 (00000000 00000000)
++ stwu 0000001cbe991def, -8 => 00000000be991def, -8 (00000000 00000000)
++ stwu ffffffffffffffff, 0 => 00000000ffffffff, 0 (00000000 00000000)
++
++ std 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
++ std 0000001cbe991def, 8 => 0000001cbe991def, 0 (00000000 00000000)
++ std ffffffffffffffff, 16 => ffffffffffffffff, 0 (00000000 00000000)
++ std 0000000000000000, -16 => 0000000000000000, 0 (00000000 00000000)
++ std 0000001cbe991def, -8 => 0000001cbe991def, 0 (00000000 00000000)
++ std ffffffffffffffff, 0 => ffffffffffffffff, 0 (00000000 00000000)
++
++ stdu 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
++ stdu 0000001cbe991def, 8 => 0000001cbe991def, 0 (00000000 00000000)
++ stdu ffffffffffffffff, 16 => ffffffffffffffff, 0 (00000000 00000000)
++ stdu 0000000000000000, -16 => 0000000000000000, 0 (00000000 00000000)
++ stdu 0000001cbe991def, -8 => 0000001cbe991def, 0 (00000000 00000000)
++ stdu ffffffffffffffff, 0 => ffffffffffffffff, 0 (00000000 00000000)
++
++PPC integer store insns with three register args:
++ stbx 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
++ stbx 0000001cbe991def, 8 => 00000000000000ef, 0 (00000000 00000000)
++ stbx ffffffffffffffff, 16 => 00000000000000ff, 0 (00000000 00000000)
++
++ stbux 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
++ stbux 0000001cbe991def, 8 => 00000000000000ef, 8 (00000000 00000000)
++ stbux ffffffffffffffff, 16 => 00000000000000ff, 16 (00000000 00000000)
++
++ sthx 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
++ sthx 0000001cbe991def, 8 => 0000000000001def, 0 (00000000 00000000)
++ sthx ffffffffffffffff, 16 => 000000000000ffff, 0 (00000000 00000000)
++
++ sthux 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
++ sthux 0000001cbe991def, 8 => 0000000000001def, 8 (00000000 00000000)
++ sthux ffffffffffffffff, 16 => 000000000000ffff, 16 (00000000 00000000)
++
++ stwx 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
++ stwx 0000001cbe991def, 8 => 00000000be991def, 0 (00000000 00000000)
++ stwx ffffffffffffffff, 16 => 00000000ffffffff, 0 (00000000 00000000)
++
++ stwux 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
++ stwux 0000001cbe991def, 8 => 00000000be991def, 8 (00000000 00000000)
++ stwux ffffffffffffffff, 16 => 00000000ffffffff, 16 (00000000 00000000)
++
++ stdx 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
++ stdx 0000001cbe991def, 8 => 0000001cbe991def, 0 (00000000 00000000)
++ stdx ffffffffffffffff, 16 => ffffffffffffffff, 0 (00000000 00000000)
++
++ stdux 0000000000000000, 0 => 0000000000000000, 0 (00000000 00000000)
++ stdux 0000001cbe991def, 8 => 0000001cbe991def, 8 (00000000 00000000)
++ stdux ffffffffffffffff, 16 => ffffffffffffffff, 16 (00000000 00000000)
++
++PPC integer population count with one register args, no flags:
++ popcntb 0000000000000000 => 0000000000000000 (00000000 00000000)
++ popcntb 0000001cbe991def => 0000000306040407 (00000000 00000000)
++ popcntb ffffffffffffffff => 0808080808080808 (00000000 00000000)
++
++All done. Tested 210 different instructions
+diff --git a/none/tests/ppc64/jm-vmx.stdout.exp b/none/tests/ppc64/jm-vmx.stdout.exp
+index 3e19e63..44fe879 100644
+--- a/none/tests/ppc64/jm-vmx.stdout.exp
++++ b/none/tests/ppc64/jm-vmx.stdout.exp
+@@ -1407,43 +1407,43 @@ Altivec integer special insns:
+ vsldoi: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 14
+ vsldoi: => fefff1f2 f3f4f5f6 f7f8f9fa fbfcfefd] (00000000)
+
+- lvsl -1, 0 => 0f101112 13141516 1718191a 1b1c1d1e (00000000)
+- lvsl 0, 0 => 00010203 04050607 08090a0b 0c0d0e0f (00000000)
+- lvsl 1, 0 => 01020304 05060708 090a0b0c 0d0e0f10 (00000000)
+- lvsl 2, 0 => 02030405 06070809 0a0b0c0d 0e0f1011 (00000000)
+- lvsl 3, 0 => 03040506 0708090a 0b0c0d0e 0f101112 (00000000)
+- lvsl 4, 0 => 04050607 08090a0b 0c0d0e0f 10111213 (00000000)
+- lvsl 5, 0 => 05060708 090a0b0c 0d0e0f10 11121314 (00000000)
+- lvsl 6, 0 => 06070809 0a0b0c0d 0e0f1011 12131415 (00000000)
+- lvsl 7, 0 => 0708090a 0b0c0d0e 0f101112 13141516 (00000000)
+- lvsl 8, 0 => 08090a0b 0c0d0e0f 10111213 14151617 (00000000)
+- lvsl 9, 0 => 090a0b0c 0d0e0f10 11121314 15161718 (00000000)
+- lvsl 10, 0 => 0a0b0c0d 0e0f1011 12131415 16171819 (00000000)
+- lvsl 11, 0 => 0b0c0d0e 0f101112 13141516 1718191a (00000000)
+- lvsl 12, 0 => 0c0d0e0f 10111213 14151617 18191a1b (00000000)
+- lvsl 13, 0 => 0d0e0f10 11121314 15161718 191a1b1c (00000000)
+- lvsl 14, 0 => 0e0f1011 12131415 16171819 1a1b1c1d (00000000)
+- lvsl 15, 0 => 0f101112 13141516 1718191a 1b1c1d1e (00000000)
+- lvsl 16, 0 => 00010203 04050607 08090a0b 0c0d0e0f (00000000)
+-
+- lvsr -1, 0 => 01020304 05060708 090a0b0c 0d0e0f10 (00000000)
+- lvsr 0, 0 => 10111213 14151617 18191a1b 1c1d1e1f (00000000)
+- lvsr 1, 0 => 0f101112 13141516 1718191a 1b1c1d1e (00000000)
+- lvsr 2, 0 => 0e0f1011 12131415 16171819 1a1b1c1d (00000000)
+- lvsr 3, 0 => 0d0e0f10 11121314 15161718 191a1b1c (00000000)
+- lvsr 4, 0 => 0c0d0e0f 10111213 14151617 18191a1b (00000000)
+- lvsr 5, 0 => 0b0c0d0e 0f101112 13141516 1718191a (00000000)
+- lvsr 6, 0 => 0a0b0c0d 0e0f1011 12131415 16171819 (00000000)
+- lvsr 7, 0 => 090a0b0c 0d0e0f10 11121314 15161718 (00000000)
+- lvsr 8, 0 => 08090a0b 0c0d0e0f 10111213 14151617 (00000000)
+- lvsr 9, 0 => 0708090a 0b0c0d0e 0f101112 13141516 (00000000)
+- lvsr 10, 0 => 06070809 0a0b0c0d 0e0f1011 12131415 (00000000)
+- lvsr 11, 0 => 05060708 090a0b0c 0d0e0f10 11121314 (00000000)
+- lvsr 12, 0 => 04050607 08090a0b 0c0d0e0f 10111213 (00000000)
+- lvsr 13, 0 => 03040506 0708090a 0b0c0d0e 0f101112 (00000000)
+- lvsr 14, 0 => 02030405 06070809 0a0b0c0d 0e0f1011 (00000000)
+- lvsr 15, 0 => 01020304 05060708 090a0b0c 0d0e0f10 (00000000)
+- lvsr 16, 0 => 10111213 14151617 18191a1b 1c1d1e1f (00000000)
++ lvsl 7, 0 => 0x0708090a0b0c0d0e 0x0f10111213141516 (00000000)
++ lvsl 8, 0 => 0x08090a0b0c0d0e0f 0x1011121314151617 (00000000)
++ lvsl 9, 0 => 0x090a0b0c0d0e0f10 0x1112131415161718 (00000000)
++ lvsl a, 0 => 0x0a0b0c0d0e0f1011 0x1213141516171819 (00000000)
++ lvsl b, 0 => 0x0b0c0d0e0f101112 0x131415161718191a (00000000)
++ lvsl c, 0 => 0x0c0d0e0f10111213 0x1415161718191a1b (00000000)
++ lvsl d, 0 => 0x0d0e0f1011121314 0x15161718191a1b1c (00000000)
++ lvsl e, 0 => 0x0e0f101112131415 0x161718191a1b1c1d (00000000)
++ lvsl f, 0 => 0x0f10111213141516 0x1718191a1b1c1d1e (00000000)
++ lvsl 0, 0 => 0x0001020304050607 0x08090a0b0c0d0e0f (00000000)
++ lvsl 1, 0 => 0x0102030405060708 0x090a0b0c0d0e0f10 (00000000)
++ lvsl 2, 0 => 0x0203040506070809 0x0a0b0c0d0e0f1011 (00000000)
++ lvsl 3, 0 => 0x030405060708090a 0x0b0c0d0e0f101112 (00000000)
++ lvsl 4, 0 => 0x0405060708090a0b 0x0c0d0e0f10111213 (00000000)
++ lvsl 5, 0 => 0x05060708090a0b0c 0x0d0e0f1011121314 (00000000)
++ lvsl 6, 0 => 0x060708090a0b0c0d 0x0e0f101112131415 (00000000)
++ lvsl 7, 0 => 0x0708090a0b0c0d0e 0x0f10111213141516 (00000000)
++ lvsl 8, 0 => 0x08090a0b0c0d0e0f 0x1011121314151617 (00000000)
++
++ lvsr 7, 0 => 0x090a0b0c0d0e0f10 0x1112131415161718 (00000000)
++ lvsr 8, 0 => 0x08090a0b0c0d0e0f 0x1011121314151617 (00000000)
++ lvsr 9, 0 => 0x0708090a0b0c0d0e 0x0f10111213141516 (00000000)
++ lvsr a, 0 => 0x060708090a0b0c0d 0x0e0f101112131415 (00000000)
++ lvsr b, 0 => 0x05060708090a0b0c 0x0d0e0f1011121314 (00000000)
++ lvsr c, 0 => 0x0405060708090a0b 0x0c0d0e0f10111213 (00000000)
++ lvsr d, 0 => 0x030405060708090a 0x0b0c0d0e0f101112 (00000000)
++ lvsr e, 0 => 0x0203040506070809 0x0a0b0c0d0e0f1011 (00000000)
++ lvsr f, 0 => 0x0102030405060708 0x090a0b0c0d0e0f10 (00000000)
++ lvsr 0, 0 => 0x1011121314151617 0x18191a1b1c1d1e1f (00000000)
++ lvsr 1, 0 => 0x0f10111213141516 0x1718191a1b1c1d1e (00000000)
++ lvsr 2, 0 => 0x0e0f101112131415 0x161718191a1b1c1d (00000000)
++ lvsr 3, 0 => 0x0d0e0f1011121314 0x15161718191a1b1c (00000000)
++ lvsr 4, 0 => 0x0c0d0e0f10111213 0x1415161718191a1b (00000000)
++ lvsr 5, 0 => 0x0b0c0d0e0f101112 0x131415161718191a (00000000)
++ lvsr 6, 0 => 0x0a0b0c0d0e0f1011 0x1213141516171819 (00000000)
++ lvsr 7, 0 => 0x090a0b0c0d0e0f10 0x1112131415161718 (00000000)
++ lvsr 8, 0 => 0x08090a0b0c0d0e0f 0x1011121314151617 (00000000)
+
+ Altivec load insns with two register args:
+ lvebx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01000000 00000000 00000000 00000000 (00000000)
+@@ -3451,18 +3451,18 @@ Altivec float special insns:
+ vcfux: 7fffffff ( nan), 9 => 4a800000 ( 4.194304e+06) (00000000)
+ vcfux: 7fffffff ( nan), 18 => 46000000 ( 8.192000e+03) (00000000)
+ vcfux: 7fffffff ( nan), 27 => 41800000 ( 1.600000e+01) (00000000)
+- vcfux: ffffffff ( nan), 0 => 4f800000 ( 4.294967e+09) (00000000)
+- vcfux: ffffffff ( nan), 9 => 4b000000 ( 8.388608e+06) (00000000)
+- vcfux: ffffffff ( nan), 18 => 46800000 ( 1.638400e+04) (00000000)
+- vcfux: ffffffff ( nan), 27 => 42000000 ( 3.200000e+01) (00000000)
++ vcfux: ffffffff ( -nan), 0 => 4f800000 ( 4.294967e+09) (00000000)
++ vcfux: ffffffff ( -nan), 9 => 4b000000 ( 8.388608e+06) (00000000)
++ vcfux: ffffffff ( -nan), 18 => 46800000 ( 1.638400e+04) (00000000)
++ vcfux: ffffffff ( -nan), 27 => 42000000 ( 3.200000e+01) (00000000)
+ vcfux: 7fbfffff ( nan), 0 => 4eff8000 ( 2.143289e+09) (00000000)
+ vcfux: 7fbfffff ( nan), 9 => 4a7f8000 ( 4.186112e+06) (00000000)
+ vcfux: 7fbfffff ( nan), 18 => 45ff8000 ( 8.176000e+03) (00000000)
+ vcfux: 7fbfffff ( nan), 27 => 417f8000 ( 1.596875e+01) (00000000)
+- vcfux: ffbfffff ( nan), 0 => 4f7fc000 ( 4.290773e+09) (00000000)
+- vcfux: ffbfffff ( nan), 9 => 4affc000 ( 8.380416e+06) (00000000)
+- vcfux: ffbfffff ( nan), 18 => 467fc000 ( 1.636800e+04) (00000000)
+- vcfux: ffbfffff ( nan), 27 => 41ffc000 ( 3.196875e+01) (00000000)
++ vcfux: ffbfffff ( -nan), 0 => 4f7fc000 ( 4.290773e+09) (00000000)
++ vcfux: ffbfffff ( -nan), 9 => 4affc000 ( 8.380416e+06) (00000000)
++ vcfux: ffbfffff ( -nan), 18 => 467fc000 ( 1.636800e+04) (00000000)
++ vcfux: ffbfffff ( -nan), 27 => 41ffc000 ( 3.196875e+01) (00000000)
+
+ vcfsx: 02bfffff ( 2.821186e-37), 0 => 4c300000 ( 4.613734e+07) (00000000)
+ vcfsx: 02bfffff ( 2.821186e-37), 9 => 47b00000 ( 9.011200e+04) (00000000)
+@@ -3500,27 +3500,27 @@ Altivec float special insns:
+ vcfsx: 7fffffff ( nan), 9 => 4a800000 ( 4.194304e+06) (00000000)
+ vcfsx: 7fffffff ( nan), 18 => 46000000 ( 8.192000e+03) (00000000)
+ vcfsx: 7fffffff ( nan), 27 => 41800000 ( 1.600000e+01) (00000000)
+- vcfsx: ffffffff ( nan), 0 => bf800000 (-1.000000e+00) (00000000)
+- vcfsx: ffffffff ( nan), 9 => bb000000 (-1.953125e-03) (00000000)
+- vcfsx: ffffffff ( nan), 18 => b6800000 (-3.814697e-06) (00000000)
+- vcfsx: ffffffff ( nan), 27 => b2000000 (-7.450581e-09) (00000000)
++ vcfsx: ffffffff ( -nan), 0 => bf800000 (-1.000000e+00) (00000000)
++ vcfsx: ffffffff ( -nan), 9 => bb000000 (-1.953125e-03) (00000000)
++ vcfsx: ffffffff ( -nan), 18 => b6800000 (-3.814697e-06) (00000000)
++ vcfsx: ffffffff ( -nan), 27 => b2000000 (-7.450581e-09) (00000000)
+ vcfsx: 7fbfffff ( nan), 0 => 4eff8000 ( 2.143289e+09) (00000000)
+ vcfsx: 7fbfffff ( nan), 9 => 4a7f8000 ( 4.186112e+06) (00000000)
+ vcfsx: 7fbfffff ( nan), 18 => 45ff8000 ( 8.176000e+03) (00000000)
+ vcfsx: 7fbfffff ( nan), 27 => 417f8000 ( 1.596875e+01) (00000000)
+- vcfsx: ffbfffff ( nan), 0 => ca800002 (-4.194305e+06) (00000000)
+- vcfsx: ffbfffff ( nan), 9 => c6000002 (-8.192002e+03) (00000000)
+- vcfsx: ffbfffff ( nan), 18 => c1800002 (-1.600000e+01) (00000000)
+- vcfsx: ffbfffff ( nan), 27 => bd000002 (-3.125001e-02) (00000000)
++ vcfsx: ffbfffff ( -nan), 0 => ca800002 (-4.194305e+06) (00000000)
++ vcfsx: ffbfffff ( -nan), 9 => c6000002 (-8.192002e+03) (00000000)
++ vcfsx: ffbfffff ( -nan), 18 => c1800002 (-1.600000e+01) (00000000)
++ vcfsx: ffbfffff ( -nan), 27 => bd000002 (-3.125001e-02) (00000000)
+
+ vctuxs: 02bfffff ( 2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 02bfffff ( 2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 02bfffff ( 2.821186e-37), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 02bfffff ( 2.821186e-37), 27 => 00000000 ( 0.000000e+00) (00000000)
+- vctuxs: 513fffff ( 5.153960e+10), 0 => ffffffff ( nan) (00000000)
+- vctuxs: 513fffff ( 5.153960e+10), 9 => ffffffff ( nan) (00000000)
+- vctuxs: 513fffff ( 5.153960e+10), 18 => ffffffff ( nan) (00000000)
+- vctuxs: 513fffff ( 5.153960e+10), 27 => ffffffff ( nan) (00000000)
++ vctuxs: 513fffff ( 5.153960e+10), 0 => ffffffff ( -nan) (00000000)
++ vctuxs: 513fffff ( 5.153960e+10), 9 => ffffffff ( -nan) (00000000)
++ vctuxs: 513fffff ( 5.153960e+10), 18 => ffffffff ( -nan) (00000000)
++ vctuxs: 513fffff ( 5.153960e+10), 27 => ffffffff ( -nan) (00000000)
+ vctuxs: 82bfffff (-2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 82bfffff (-2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 82bfffff (-2.821186e-37), 18 => 00000000 ( 0.000000e+00) (00000000)
+@@ -3537,10 +3537,10 @@ Altivec float special insns:
+ vctuxs: 80000000 (-0.000000e+00), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 80000000 (-0.000000e+00), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 80000000 (-0.000000e+00), 27 => 00000000 ( 0.000000e+00) (00000000)
+- vctuxs: 7f800000 ( inf), 0 => ffffffff ( nan) (00000000)
+- vctuxs: 7f800000 ( inf), 9 => ffffffff ( nan) (00000000)
+- vctuxs: 7f800000 ( inf), 18 => ffffffff ( nan) (00000000)
+- vctuxs: 7f800000 ( inf), 27 => ffffffff ( nan) (00000000)
++ vctuxs: 7f800000 ( inf), 0 => ffffffff ( -nan) (00000000)
++ vctuxs: 7f800000 ( inf), 9 => ffffffff ( -nan) (00000000)
++ vctuxs: 7f800000 ( inf), 18 => ffffffff ( -nan) (00000000)
++ vctuxs: 7f800000 ( inf), 27 => ffffffff ( -nan) (00000000)
+ vctuxs: ff800000 ( -inf), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: ff800000 ( -inf), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: ff800000 ( -inf), 18 => 00000000 ( 0.000000e+00) (00000000)
+@@ -3549,18 +3549,18 @@ Altivec float special insns:
+ vctuxs: 7fffffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 7fffffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 7fffffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
+- vctuxs: ffffffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
+- vctuxs: ffffffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
+- vctuxs: ffffffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
+- vctuxs: ffffffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: ffffffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: ffffffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: ffffffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: ffffffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 7fbfffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 7fbfffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 7fbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctuxs: 7fbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
+- vctuxs: ffbfffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
+- vctuxs: ffbfffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
+- vctuxs: ffbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
+- vctuxs: ffbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: ffbfffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: ffbfffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: ffbfffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: ffbfffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000)
+
+ vctsxs: 02bfffff ( 2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 02bfffff ( 2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000)
+@@ -3598,17 +3598,17 @@ Altivec float special insns:
+ vctsxs: 7fffffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 7fffffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 7fffffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
+- vctsxs: ffffffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
+- vctsxs: ffffffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
+- vctsxs: ffffffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
+- vctsxs: ffffffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: ffffffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: ffffffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: ffffffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: ffffffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 7fbfffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 7fbfffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 7fbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
+ vctsxs: 7fbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
+- vctsxs: ffbfffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
+- vctsxs: ffbfffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
+- vctsxs: ffbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
+- vctsxs: ffbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: ffbfffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: ffbfffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: ffbfffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: ffbfffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000)
+
+ All done. Tested 165 different instructions
+diff --git a/none/tests/ppc64/jm-vmx.stdout.exp-LE b/none/tests/ppc64/jm-vmx.stdout.exp-LE
+new file mode 100644
+index 0000000..55efcb7
+--- /dev/null
++++ b/none/tests/ppc64/jm-vmx.stdout.exp-LE
+@@ -0,0 +1,3614 @@
++PPC altivec integer arith insns with three args:
++ vmhaddshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vmhaddshs: => 010403160538076a09ad0c000f970f9a (00000000)
++ vmhaddshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmhaddshs: => f1f4f406f628f85afa9dfcf00087008a (00000000)
++ vmhaddshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vmhaddshs: => 00e502bb04a10697089d0ab30df00df2 (00000000)
++ vmhaddshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmhaddshs: => f1d5f3abf591f787f98dfba3fee0fee2 (00000000)
++ vmhaddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vmhaddshs: => 00e502bb04a10697089d0ab30df00df2 (00000000)
++ vmhaddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmhaddshs: => f1d5f3abf591f787f98dfba3fee0fee2 (00000000)
++ vmhaddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vmhaddshs: => 028d042605cf078909520b2c0e0f0e11 (00000000)
++ vmhaddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmhaddshs: => f37df516f6bff879fa42fc1cfeffff01 (00000000)
++
++ vmhraddshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vmhraddshs: => 010403160538076b09ad0c000f980f9a (00000000)
++ vmhraddshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmhraddshs: => f1f4f406f628f85bfa9dfcf00088008a (00000000)
++ vmhraddshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vmhraddshs: => 00e602bb04a10697089d0ab30df10df3 (00000000)
++ vmhraddshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmhraddshs: => f1d6f3abf591f787f98dfba3fee1fee3 (00000000)
++ vmhraddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vmhraddshs: => 00e602bb04a10697089d0ab30df10df3 (00000000)
++ vmhraddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmhraddshs: => f1d6f3abf591f787f98dfba3fee1fee3 (00000000)
++ vmhraddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vmhraddshs: => 028d042605d0078909530b2c0e0f0e11 (00000000)
++ vmhraddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmhraddshs: => f37df516f6c0f879fa43fc1cfeffff01 (00000000)
++
++ vmladduhm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vmladduhm: => 05061b14412a7748bd6e139c7ab6b2f0 (00000000)
++ vmladduhm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmladduhm: => f5f60c04321a6838ae5e048c6ba6a3e0 (00000000)
++ vmladduhm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vmladduhm: => d6e6aed496ca8ec896ceaedcd6e6f100 (00000000)
++ vmladduhm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmladduhm: => c7d69fc487ba7fb887be9fccc7d6e1f0 (00000000)
++ vmladduhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vmladduhm: => d6e6aed496ca8ec896ceaedcd6e6f100 (00000000)
++ vmladduhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmladduhm: => c7d69fc487ba7fb887be9fccc7d6e1f0 (00000000)
++ vmladduhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vmladduhm: => 89c62394cd6a8748512e2b1c14161010 (00000000)
++ vmladduhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmladduhm: => 7ab61484be5a7838421e1c0c05060100 (00000000)
++
++ vmsumubm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vmsumubm: => 01020322050607b6090a0cca0e0d1121 (00000000)
++ vmsumubm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmsumubm: => f1f2f412f5f6f8a6f9fafdbafefe0211 (00000000)
++ vmsumubm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vmsumubm: => 01020c8205062016090a342a0e0d45a1 (00000000)
++ vmsumubm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmsumubm: => f1f2fd72f5f71106f9fb251afefe3691 (00000000)
++ vmsumubm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vmsumubm: => 01020c8205062016090a342a0e0d45a1 (00000000)
++ vmsumubm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmsumubm: => f1f2fd72f5f71106f9fb251afefe3691 (00000000)
++ vmsumubm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vmsumubm: => 010599e20509bc76090ddf8a0e10fe21 (00000000)
++ vmsumubm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmsumubm: => f1f68ad2f5faad66f9fed07aff01ef11 (00000000)
++
++ vmsumuhm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vmsumuhm: => 010c1f180550b36c09d5c8000f981f99 (00000000)
++ vmsumuhm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmsumuhm: => f1fd1008f641a45cfac6b8f000891089 (00000000)
++ vmsumuhm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vmsumuhm: => 04d584b810a9208c1cbd3ca02a0cb9d9 (00000000)
++ vmsumuhm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmsumuhm: => f5c675a8019a117c0dae2d901afdaac9 (00000000)
++ vmsumuhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vmsumuhm: => 04d584b810a9208c1cbd3ca02a0cb9d9 (00000000)
++ vmsumuhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmsumuhm: => f5c675a8019a117c0dae2d901afdaac9 (00000000)
++ vmsumuhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vmsumuhm: => ce24ac58e1874facf52a73400a071619 (00000000)
++ vmsumuhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmsumuhm: => bf159d48d278409ce61b6430faf80709 (00000000)
++
++ vmsumshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vmsumshs: => 010c1f180550b36c09d5c8000f981f99 (00000000)
++ vmsumshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmsumshs: => f1fd1008f641a45cfac6b8f000891089 (00000000)
++ vmsumshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vmsumshs: => 00cf84b8049b208c08a73ca00df0b9d9 (00000000)
++ vmsumshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmsumshs: => f1c075a8f58c117cf9982d90fee1aac9 (00000000)
++ vmsumshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vmsumshs: => 00cf84b8049b208c08a73ca00df0b9d9 (00000000)
++ vmsumshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmsumshs: => f1c075a8f58c117cf9982d90fee1aac9 (00000000)
++ vmsumshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vmsumshs: => 0258ac5805ab4fac093e73400e0f1619 (00000000)
++ vmsumshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmsumshs: => f3499d48f69c409cfa2f6430ff000709 (00000000)
++
++ vmsumuhs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vmsumuhs: => 010c1f180550b36c09d5c8000f981f99 (00000000)
++ vmsumuhs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmsumuhs: => f1fd1008f641a45cfac6b8f0ffffffff (00000000)
++ vmsumuhs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vmsumuhs: => 04d584b810a9208c1cbd3ca02a0cb9d9 (00000000)
++ vmsumuhs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmsumuhs: => f5c675a8ffffffffffffffffffffffff (00000000)
++ vmsumuhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vmsumuhs: => 04d584b810a9208c1cbd3ca02a0cb9d9 (00000000)
++ vmsumuhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmsumuhs: => f5c675a8ffffffffffffffffffffffff (00000000)
++ vmsumuhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vmsumuhs: => ffffffffffffffffffffffffffffffff (00000000)
++ vmsumuhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmsumuhs: => ffffffffffffffffffffffffffffffff (00000000)
++
++ vmsummbm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vmsummbm: => 01020322050607b6090a0cca0e0d1121 (00000000)
++ vmsummbm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmsummbm: => f1f2f412f5f6f8a6f9fafdbafefe0211 (00000000)
++ vmsummbm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vmsummbm: => 01020c8205062016090a342a0e0d45a1 (00000000)
++ vmsummbm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmsummbm: => f1f2fd72f5f71106f9fb251afefe3691 (00000000)
++ vmsummbm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vmsummbm: => 0102028205060616090a0a2a0e0d0da1 (00000000)
++ vmsummbm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmsummbm: => f1f2f372f5f6f706f9fafb1afefdfe91 (00000000)
++ vmsummbm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vmsummbm: => 0101cfe20505e2760909f58a0e0d0621 (00000000)
++ vmsummbm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmsummbm: => f1f2c0d2f5f6d366f9fae67afefdf711 (00000000)
++
++ vmsumshm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vmsumshm: => 010c1f180550b36c09d5c8000f981f99 (00000000)
++ vmsumshm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmsumshm: => f1fd1008f641a45cfac6b8f000891089 (00000000)
++ vmsumshm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vmsumshm: => 00cf84b8049b208c08a73ca00df0b9d9 (00000000)
++ vmsumshm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmsumshm: => f1c075a8f58c117cf9982d90fee1aac9 (00000000)
++ vmsumshm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vmsumshm: => 00cf84b8049b208c08a73ca00df0b9d9 (00000000)
++ vmsumshm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmsumshm: => f1c075a8f58c117cf9982d90fee1aac9 (00000000)
++ vmsumshm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vmsumshm: => 0258ac5805ab4fac093e73400e0f1619 (00000000)
++ vmsumshm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmsumshm: => f3499d48f69c409cfa2f6430ff000709 (00000000)
++
++PPC altivec integer logical insns with three args:
++ vperm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vperm: => 0d0e0f090a0b0c050607080103020304 (00000000)
++ vperm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vperm: => 0d0e0f090a0b0c050607080103020304 (00000000)
++ vperm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vperm: => 0d0e0f090a0b0c050607080103020304 (00000000)
++ vperm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vperm: => fdfefff9fafbfcf5f6f7f8f1f3f2f3f4 (00000000)
++ vperm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vperm: => fdfefff9fafbfcf5f6f7f8f1f3f2f3f4 (00000000)
++ vperm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vperm: => 0d0e0f090a0b0c050607080103020304 (00000000)
++ vperm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vperm: => fdfefff9fafbfcf5f6f7f8f1f3f2f3f4 (00000000)
++ vperm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vperm: => fdfefff9fafbfcf5f6f7f8f1f3f2f3f4 (00000000)
++
++ vsel: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vsel: => 0102030405060708090a0b0c0e0d0e0f (00000000)
++ vsel: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsel: => 0102030405060708090a0b0c0e0d0e0f (00000000)
++ vsel: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vsel: => 0102030405060708090a0b0c0e0d0e0f (00000000)
++ vsel: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsel: => f1f2f3f4f5f6f7f8f9fafbfcfefdfeff (00000000)
++ vsel: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vsel: => f1f2f3f4f5f6f7f8f9fafbfcfefdfeff (00000000)
++ vsel: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsel: => 0102030405060708090a0b0c0e0d0e0f (00000000)
++ vsel: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vsel: => f1f2f3f4f5f6f7f8f9fafbfcfefdfeff (00000000)
++ vsel: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsel: => f1f2f3f4f5f6f7f8f9fafbfcfefdfeff (00000000)
++
++PPC altivec integer arith insns with two args:
++ vaddubm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vaddubm: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000)
++ vaddubm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vaddubm: => f2f4f6f8 fafcfe00 02040608 0c0a0c0e (00000000)
++ vaddubm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vaddubm: => f2f4f6f8 fafcfe00 02040608 0c0a0c0e (00000000)
++ vaddubm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vaddubm: => e2e4e6e8 eaeceef0 f2f4f6f8 fcfafcfe (00000000)
++
++ vadduhm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vadduhm: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000)
++ vadduhm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vadduhm: => f2f4f6f8 fafcff00 03040708 0d0a0d0e (00000000)
++ vadduhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vadduhm: => f2f4f6f8 fafcff00 03040708 0d0a0d0e (00000000)
++ vadduhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vadduhm: => e3e4e7e8 ebeceff0 f3f4f7f8 fdfafdfe (00000000)
++
++ vadduwm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vadduwm: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000)
++ vadduwm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vadduwm: => f2f4f6f8 fafcff00 03050708 0d0b0d0e (00000000)
++ vadduwm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vadduwm: => f2f4f6f8 fafcff00 03050708 0d0b0d0e (00000000)
++ vadduwm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vadduwm: => e3e5e7e8 ebedeff0 f3f5f7f8 fdfbfdfe (00000000)
++
++ vaddubs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vaddubs: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000)
++ vaddubs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vaddubs: => f2f4f6f8 fafcfeff ffffffff ffffffff (00000000)
++ vaddubs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vaddubs: => f2f4f6f8 fafcfeff ffffffff ffffffff (00000000)
++ vaddubs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vaddubs: => ffffffff ffffffff ffffffff ffffffff (00000000)
++
++ vadduhs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vadduhs: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000)
++ vadduhs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vadduhs: => f2f4f6f8 fafcff00 ffffffff ffffffff (00000000)
++ vadduhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vadduhs: => f2f4f6f8 fafcff00 ffffffff ffffffff (00000000)
++ vadduhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vadduhs: => ffffffff ffffffff ffffffff ffffffff (00000000)
++
++ vadduws: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vadduws: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000)
++ vadduws: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vadduws: => f2f4f6f8 fafcff00 ffffffff ffffffff (00000000)
++ vadduws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vadduws: => f2f4f6f8 fafcff00 ffffffff ffffffff (00000000)
++ vadduws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vadduws: => ffffffff ffffffff ffffffff ffffffff (00000000)
++
++ vaddsbs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vaddsbs: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000)
++ vaddsbs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vaddsbs: => f2f4f6f8 fafcfe00 02040608 0c0a0c0e (00000000)
++ vaddsbs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vaddsbs: => f2f4f6f8 fafcfe00 02040608 0c0a0c0e (00000000)
++ vaddsbs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vaddsbs: => e2e4e6e8 eaeceef0 f2f4f6f8 fcfafcfe (00000000)
++
++ vaddshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vaddshs: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000)
++ vaddshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vaddshs: => f2f4f6f8 fafcff00 03040708 0d0a0d0e (00000000)
++ vaddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vaddshs: => f2f4f6f8 fafcff00 03040708 0d0a0d0e (00000000)
++ vaddshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vaddshs: => e3e4e7e8 ebeceff0 f3f4f7f8 fdfafdfe (00000000)
++
++ vaddsws: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vaddsws: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000)
++ vaddsws: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vaddsws: => f2f4f6f8 fafcff00 03050708 0d0b0d0e (00000000)
++ vaddsws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vaddsws: => f2f4f6f8 fafcff00 03050708 0d0b0d0e (00000000)
++ vaddsws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vaddsws: => e3e5e7e8 ebedeff0 f3f5f7f8 fdfbfdfe (00000000)
++
++ vaddcuw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vaddcuw: => 00000000 00000000 00000000 00000000 (00000000)
++ vaddcuw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vaddcuw: => 00000000 00000000 00000001 00000001 (00000000)
++ vaddcuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vaddcuw: => 00000000 00000000 00000001 00000001 (00000000)
++ vaddcuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vaddcuw: => 00000001 00000001 00000001 00000001 (00000000)
++
++ vsububm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vsububm: => 00000000 00000000 00000000 00000000 (00000000)
++ vsububm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsububm: => 10101010 10101010 10101010 10101010 (00000000)
++ vsububm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vsububm: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
++ vsububm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsububm: => 00000000 00000000 00000000 00000000 (00000000)
++
++ vsubuhm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vsubuhm: => 00000000 00000000 00000000 00000000 (00000000)
++ vsubuhm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsubuhm: => 0f100f10 0f100f10 0f100f10 0f100f10 (00000000)
++ vsubuhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vsubuhm: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
++ vsubuhm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsubuhm: => 00000000 00000000 00000000 00000000 (00000000)
++
++ vsubuwm: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vsubuwm: => 00000000 00000000 00000000 00000000 (00000000)
++ vsubuwm: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsubuwm: => 0f0f0f10 0f0f0f10 0f0f0f10 0f0f0f10 (00000000)
++ vsubuwm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vsubuwm: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
++ vsubuwm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsubuwm: => 00000000 00000000 00000000 00000000 (00000000)
++
++ vsububs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vsububs: => 00000000 00000000 00000000 00000000 (00000000)
++ vsububs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsububs: => 00000000 00000000 00000000 00000000 (00000000)
++ vsububs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vsububs: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
++ vsububs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsububs: => 00000000 00000000 00000000 00000000 (00000000)
++
++ vsubuhs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vsubuhs: => 00000000 00000000 00000000 00000000 (00000000)
++ vsubuhs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsubuhs: => 00000000 00000000 00000000 00000000 (00000000)
++ vsubuhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vsubuhs: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
++ vsubuhs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsubuhs: => 00000000 00000000 00000000 00000000 (00000000)
++
++ vsubuws: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vsubuws: => 00000000 00000000 00000000 00000000 (00000000)
++ vsubuws: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsubuws: => 00000000 00000000 00000000 00000000 (00000000)
++ vsubuws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vsubuws: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
++ vsubuws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsubuws: => 00000000 00000000 00000000 00000000 (00000000)
++
++ vsubsbs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vsubsbs: => 00000000 00000000 00000000 00000000 (00000000)
++ vsubsbs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsubsbs: => 10101010 10101010 10101010 10101010 (00000000)
++ vsubsbs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vsubsbs: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
++ vsubsbs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsubsbs: => 00000000 00000000 00000000 00000000 (00000000)
++
++ vsubshs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vsubshs: => 00000000 00000000 00000000 00000000 (00000000)
++ vsubshs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsubshs: => 0f100f10 0f100f10 0f100f10 0f100f10 (00000000)
++ vsubshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vsubshs: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
++ vsubshs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsubshs: => 00000000 00000000 00000000 00000000 (00000000)
++
++ vsubsws: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vsubsws: => 00000000 00000000 00000000 00000000 (00000000)
++ vsubsws: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsubsws: => 0f0f0f10 0f0f0f10 0f0f0f10 0f0f0f10 (00000000)
++ vsubsws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vsubsws: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
++ vsubsws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsubsws: => 00000000 00000000 00000000 00000000 (00000000)
++
++ vsubcuw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vsubcuw: => 00000001 00000001 00000001 00000001 (00000000)
++ vsubcuw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsubcuw: => 00000000 00000000 00000000 00000000 (00000000)
++ vsubcuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vsubcuw: => 00000001 00000001 00000001 00000001 (00000000)
++ vsubcuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsubcuw: => 00000001 00000001 00000001 00000001 (00000000)
++
++ vmuloub: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vmuloub: => 00040010 00240040 00640090 00a900e1 (00000000)
++ vmuloub: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmuloub: => 01e403d0 05c407c0 09c40bd0 0cd90ef1 (00000000)
++ vmuloub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vmuloub: => 01e403d0 05c407c0 09c40bd0 0cd90ef1 (00000000)
++ vmuloub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmuloub: => e4c4e890 ec64f040 f424f810 fa09fe01 (00000000)
++
++ vmulouh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vmulouh: => 00091810 00317040 007a0890 00c5a4e1 (00000000)
++ vmulouh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmulouh: => 02dfabd0 06cf87c0 0adfa3d0 0e00e2f1 (00000000)
++ vmulouh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vmulouh: => 02dfabd0 06cf87c0 0adfa3d0 0e00e2f1 (00000000)
++ vmulouh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmulouh: => e8792090 f0308040 f8082010 fdff0201 (00000000)
++
++ vmulosb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vmulosb: => 00040010 00240040 00640090 00a900e1 (00000000)
++ vmulosb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmulosb: => ffe4ffd0 ffc4ffc0 ffc4ffd0 ffd9fff1 (00000000)
++ vmulosb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vmulosb: => ffe4ffd0 ffc4ffc0 ffc4ffd0 ffd9fff1 (00000000)
++ vmulosb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmulosb: => 00c40090 00640040 00240010 00090001 (00000000)
++
++ vmulosh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vmulosh: => 00091810 00317040 007a0890 00c5a4e1 (00000000)
++ vmulosh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmulosh: => ffdbabd0 ffc787c0 ffd3a3d0 fff1e2f1 (00000000)
++ vmulosh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vmulosh: => ffdbabd0 ffc787c0 ffd3a3d0 fff1e2f1 (00000000)
++ vmulosh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmulosh: => 00912090 00408040 00102010 00010201 (00000000)
++
++ vmuleub: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vmuleub: => 00010009 00190031 00510079 00c400c4 (00000000)
++ vmuleub: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmuleub: => 00f102d9 04c906c1 08c10ac9 0de40de4 (00000000)
++ vmuleub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vmuleub: => 00f102d9 04c906c1 08c10ac9 0de40de4 (00000000)
++ vmuleub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmuleub: => e2e1e6a9 ea79ee51 f231f619 fc04fc04 (00000000)
++
++ vmuleuh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vmuleuh: => 00010404 00193c24 0051b464 00c56ca9 (00000000)
++ vmuleuh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmuleuh: => 00f3d5e4 04d391c4 08d38dc4 0dfec8d9 (00000000)
++ vmuleuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vmuleuh: => 00f3d5e4 04d391c4 08d38dc4 0dfec8d9 (00000000)
++ vmuleuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmuleuh: => e4a988c4 ec50c864 f4184824 fdfb0609 (00000000)
++
++ vmulesb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vmulesb: => 00010009 00190031 00510079 00c400c4 (00000000)
++ vmulesb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmulesb: => fff1ffd9 ffc9ffc1 ffc1ffc9 ffe4ffe4 (00000000)
++ vmulesb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vmulesb: => fff1ffd9 ffc9ffc1 ffc1ffc9 ffe4ffe4 (00000000)
++ vmulesb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmulesb: => 00e100a9 00790051 00310019 00040004 (00000000)
++
++ vmulesh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vmulesh: => 00010404 00193c24 0051b464 00c56ca9 (00000000)
++ vmulesh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmulesh: => fff1d5e4 ffcd91c4 ffc98dc4 fff1c8d9 (00000000)
++ vmulesh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vmulesh: => fff1d5e4 ffcd91c4 ffc98dc4 fff1c8d9 (00000000)
++ vmulesh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmulesh: => 00c588c4 0064c864 00244824 00010609 (00000000)
++
++ vsumsws: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vsumsws: => 1e21262b 00000000 00000000 00000000 (00000000)
++ vsumsws: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsumsws: => 0f12171b 00000000 00000000 00000000 (00000000)
++ vsumsws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vsumsws: => e1e4e9eb 00000000 00000000 00000000 (00000000)
++ vsumsws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsumsws: => d2d5dadb 00000000 00000000 00000000 (00000000)
++
++ vsum2sws: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vsum2sws: => 070a0d10 00000000 20212427 00000000 (00000000)
++ vsum2sws: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsum2sws: => f7fafe00 00000000 11121517 00000000 (00000000)
++ vsum2sws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vsum2sws: => e8ebeef0 00000000 02030607 00000000 (00000000)
++ vsum2sws: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsum2sws: => d9dcdfe0 00000000 f2f3f6f7 00000000 (00000000)
++
++ vsum4ubs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vsum4ubs: => 0102030e 05060722 090a0b36 0e0d0e47 (00000000)
++ vsum4ubs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsum4ubs: => f1f2f3fe f5f6f812 f9fafc26 fefdff37 (00000000)
++ vsum4ubs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vsum4ubs: => 010206ce 05060ae2 090a0ef6 0e0d1207 (00000000)
++ vsum4ubs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsum4ubs: => f1f2f7be f5f6fbd2 f9faffe6 fefe02f7 (00000000)
++
++ vsum4sbs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vsum4sbs: => 0102030e 05060722 090a0b36 0e0d0e47 (00000000)
++ vsum4sbs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsum4sbs: => f1f2f3fe f5f6f812 f9fafc26 fefdff37 (00000000)
++ vsum4sbs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vsum4sbs: => 010202ce 050606e2 090a0af6 0e0d0e07 (00000000)
++ vsum4sbs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsum4sbs: => f1f2f3be f5f6f7d2 f9fafbe6 fefdfef7 (00000000)
++
++ vsum4shs: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vsum4shs: => 0102070a 05061316 090a1f22 0e0d2a2b (00000000)
++ vsum4shs: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsum4shs: => f1f2f7fa f5f70406 f9fb1012 fefe1b1b (00000000)
++ vsum4shs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vsum4shs: => 0101e8ea 0505f4f6 090a0102 0e0d0c0b (00000000)
++ vsum4shs: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsum4shs: => f1f2d9da f5f6e5e6 f9faf1f2 fefdfcfb (00000000)
++
++ vavgub: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vavgub: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ vavgub: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vavgub: => 797a7b7c 7d7e7f80 81828384 86858687 (00000000)
++ vavgub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vavgub: => 797a7b7c 7d7e7f80 81828384 86858687 (00000000)
++ vavgub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vavgub: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++
++ vavguh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vavguh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ vavguh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vavguh: => 797a7b7c 7d7e7f80 81828384 86858687 (00000000)
++ vavguh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vavguh: => 797a7b7c 7d7e7f80 81828384 86858687 (00000000)
++ vavguh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vavguh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++
++ vavguw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vavguw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ vavguw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vavguw: => 797a7b7c 7d7e7f80 81828384 86858687 (00000000)
++ vavguw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vavguw: => 797a7b7c 7d7e7f80 81828384 86858687 (00000000)
++ vavguw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vavguw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++
++ vavgsb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vavgsb: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ vavgsb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vavgsb: => f9fafbfc fdfeff00 01020304 06050607 (00000000)
++ vavgsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vavgsb: => f9fafbfc fdfeff00 01020304 06050607 (00000000)
++ vavgsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vavgsb: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++
++ vavgsh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vavgsh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ vavgsh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vavgsh: => f97afb7c fd7eff80 01820384 06850687 (00000000)
++ vavgsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vavgsh: => f97afb7c fd7eff80 01820384 06850687 (00000000)
++ vavgsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vavgsh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++
++ vavgsw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vavgsw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ vavgsw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vavgsw: => f97a7b7c fd7e7f80 01828384 06858687 (00000000)
++ vavgsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vavgsw: => f97a7b7c fd7e7f80 01828384 06858687 (00000000)
++ vavgsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vavgsw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++
++ vmaxub: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vmaxub: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ vmaxub: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmaxub: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++ vmaxub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vmaxub: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++ vmaxub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmaxub: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++
++ vmaxuh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vmaxuh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ vmaxuh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmaxuh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++ vmaxuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vmaxuh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++ vmaxuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmaxuh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++
++ vmaxuw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vmaxuw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ vmaxuw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmaxuw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++ vmaxuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vmaxuw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++ vmaxuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmaxuw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++
++ vmaxsb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vmaxsb: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ vmaxsb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmaxsb: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ vmaxsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vmaxsb: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ vmaxsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmaxsb: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++
++ vmaxsh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vmaxsh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ vmaxsh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmaxsh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ vmaxsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vmaxsh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ vmaxsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmaxsh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++
++ vmaxsw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vmaxsw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ vmaxsw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmaxsw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ vmaxsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vmaxsw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ vmaxsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmaxsw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++
++ vminub: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vminub: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ vminub: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vminub: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ vminub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vminub: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ vminub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vminub: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++
++ vminuh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vminuh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ vminuh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vminuh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ vminuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vminuh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ vminuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vminuh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++
++ vminuw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vminuw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ vminuw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vminuw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ vminuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vminuw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ vminuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vminuw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++
++ vminsb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vminsb: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ vminsb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vminsb: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++ vminsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vminsb: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++ vminsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vminsb: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++
++ vminsh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vminsh: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ vminsh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vminsh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++ vminsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vminsh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++ vminsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vminsh: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++
++ vminsw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vminsw: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ vminsw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vminsw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++ vminsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vminsw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++ vminsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vminsw: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++
++PPC altivec integer logical insns with two args:
++ vand: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vand: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ vand: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vand: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ vand: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vand: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ vand: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vand: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++
++ vor: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vor: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ vor: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vor: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++ vor: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vor: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++ vor: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vor: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++
++ vxor: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vxor: => 00000000 00000000 00000000 00000000 (00000000)
++ vxor: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vxor: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
++ vxor: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vxor: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
++ vxor: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vxor: => 00000000 00000000 00000000 00000000 (00000000)
++
++ vandc: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vandc: => 00000000 00000000 00000000 00000000 (00000000)
++ vandc: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vandc: => 00000000 00000000 00000000 00000000 (00000000)
++ vandc: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vandc: => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
++ vandc: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vandc: => 00000000 00000000 00000000 00000000 (00000000)
++
++ vnor: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vnor: => fefdfcfb faf9f8f7 f6f5f4f3 f1f2f1f0 (00000000)
++ vnor: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vnor: => 0e0d0c0b 0a090807 06050403 01020100 (00000000)
++ vnor: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vnor: => 0e0d0c0b 0a090807 06050403 01020100 (00000000)
++ vnor: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vnor: => 0e0d0c0b 0a090807 06050403 01020100 (00000000)
++
++ vrlb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vrlb: => 02081840 a0818308 122858c0 83a18387 (00000000)
++ vrlb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vrlb: => 02081840 a0818308 122858c0 83a18387 (00000000)
++ vrlb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vrlb: => e3cb9f4f bebdfbf8 f3ebdfcf bfbfbfff (00000000)
++ vrlb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vrlb: => e3cb9f4f bebdfbf8 f3ebdfcf bfbfbfff (00000000)
++
++ vrlh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vrlh: => 04083040 41810807 2824c0b0 a1c18707 (00000000)
++ vrlh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vrlh: => 04083040 41810807 2824c0b0 a1c18707 (00000000)
++ vrlh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vrlh: => c7cb3f4f 7dbdf8f7 ebe7cfbf bfdfff7f (00000000)
++ vrlh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vrlh: => c7cb3f4f 7dbdf8f7 ebe7cfbf bfdfff7f (00000000)
++
++ vrlw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vrlw: => 10203040 06070805 a0b0c090 87078706 (00000000)
++ vrlw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vrlw: => 30401020 08050607 c090a0b0 87068707 (00000000)
++ vrlw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vrlw: => 1f2f3f4f f6f7f8f5 afbfcf9f ff7fff7e (00000000)
++ vrlw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vrlw: => 3f4f1f2f f8f5f6f7 cf9fafbf ff7eff7f (00000000)
++
++ vslb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vslb: => 02081840 a0808008 122858c0 80a08080 (00000000)
++ vslb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vslb: => 02081840 a0808008 122858c0 80a08080 (00000000)
++ vslb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vslb: => e2c89840 a08080f8 f2e8d8c0 80a08080 (00000000)
++ vslb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vslb: => e2c89840 a08080f8 f2e8d8c0 80a08080 (00000000)
++
++ vslh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vslh: => 04083040 41800800 2800c000 a0008000 (00000000)
++ vslh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vslh: => 04083040 41800800 2800c000 a0008000 (00000000)
++ vslh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vslh: => c7c83f40 7d80f800 e800c000 a0008000 (00000000)
++ vslh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vslh: => c7c83f40 7d80f800 e800c000 a0008000 (00000000)
++
++ vslw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vslw: => 10203040 06070800 a0b0c000 87078000 (00000000)
++ vslw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vslw: => 30400000 08000000 c0000000 80000000 (00000000)
++ vslw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vslw: => 1f2f3f40 f6f7f800 afbfc000 ff7f8000 (00000000)
++ vslw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vslw: => 3f400000 f8000000 c0000000 80000000 (00000000)
++
++ vsrb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vsrb: => 00000000 00000008 04020100 00000000 (00000000)
++ vsrb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsrb: => 00000000 00000008 04020100 00000000 (00000000)
++ vsrb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vsrb: => 783c1e0f 070301f8 7c3e1f0f 03070301 (00000000)
++ vsrb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsrb: => 783c1e0f 070301f8 7c3e1f0f 03070301 (00000000)
++
++ vsrh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vsrh: => 00400030 00140007 00020000 00000000 (00000000)
++ vsrh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsrh: => 00400030 00140007 00020000 00000000 (00000000)
++ vsrh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vsrh: => 3c7c0f3f 03d700f7 003e000f 00070001 (00000000)
++ vsrh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsrh: => 3c7c0f3f 03d700f7 003e000f 00070001 (00000000)
++
++ vsrw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vsrw: => 00102030 00050607 000090a0 00001c1a (00000000)
++ vsrw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsrw: => 00000010 00000005 00000000 00000000 (00000000)
++ vsrw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vsrw: => 0f1f2f3f 00f5f6f7 000f9faf 0001fdfb (00000000)
++ vsrw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsrw: => 00000f1f 000000f5 0000000f 00000001 (00000000)
++
++ vsrab: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vsrab: => 00000000 00000008 04020100 00000000 (00000000)
++ vsrab: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsrab: => 00000000 00000008 04020100 00000000 (00000000)
++ vsrab: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vsrab: => f8fcfeff fffffff8 fcfeffff ffffffff (00000000)
++ vsrab: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsrab: => f8fcfeff fffffff8 fcfeffff ffffffff (00000000)
++
++ vsrah: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vsrah: => 00400030 00140007 00020000 00000000 (00000000)
++ vsrah: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsrah: => 00400030 00140007 00020000 00000000 (00000000)
++ vsrah: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vsrah: => fc7cff3f ffd7fff7 fffeffff ffffffff (00000000)
++ vsrah: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsrah: => fc7cff3f ffd7fff7 fffeffff ffffffff (00000000)
++
++ vsraw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vsraw: => 00102030 00050607 000090a0 00001c1a (00000000)
++ vsraw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsraw: => 00000010 00000005 00000000 00000000 (00000000)
++ vsraw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vsraw: => ff1f2f3f fff5f6f7 ffff9faf fffffdfb (00000000)
++ vsraw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsraw: => ffffff1f fffffff5 ffffffff ffffffff (00000000)
++
++ vpkuhum: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vpkuhum: => 06080204 0d0f0a0c 06080204 0d0f0a0c (00000000)
++ vpkuhum: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vpkuhum: => f6f8f2f4 fdfffafc 06080204 0d0f0a0c (00000000)
++ vpkuhum: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vpkuhum: => 06080204 0d0f0a0c f6f8f2f4 fdfffafc (00000000)
++ vpkuhum: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vpkuhum: => f6f8f2f4 fdfffafc f6f8f2f4 fdfffafc (00000000)
++
++ vpkuwum: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vpkuwum: => 07080304 0e0f0b0c 07080304 0e0f0b0c (00000000)
++ vpkuwum: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vpkuwum: => f7f8f3f4 fefffbfc 07080304 0e0f0b0c (00000000)
++ vpkuwum: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vpkuwum: => 07080304 0e0f0b0c f7f8f3f4 fefffbfc (00000000)
++ vpkuwum: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vpkuwum: => f7f8f3f4 fefffbfc f7f8f3f4 fefffbfc (00000000)
++
++ vpkuhus: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vpkuhus: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vpkuhus: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vpkuhus: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vpkuhus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vpkuhus: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vpkuhus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vpkuhus: => ffffffff ffffffff ffffffff ffffffff (00000000)
++
++ vpkuwus: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vpkuwus: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vpkuwus: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vpkuwus: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vpkuwus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vpkuwus: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vpkuwus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vpkuwus: => ffffffff ffffffff ffffffff ffffffff (00000000)
++
++ vpkshus: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vpkshus: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vpkshus: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vpkshus: => 00000000 00000000 ffffffff ffffffff (00000000)
++ vpkshus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vpkshus: => ffffffff ffffffff 00000000 00000000 (00000000)
++ vpkshus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vpkshus: => 00000000 00000000 00000000 00000000 (00000000)
++
++ vpkswus: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vpkswus: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vpkswus: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vpkswus: => 00000000 00000000 ffffffff ffffffff (00000000)
++ vpkswus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vpkswus: => ffffffff ffffffff 00000000 00000000 (00000000)
++ vpkswus: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vpkswus: => 00000000 00000000 00000000 00000000 (00000000)
++
++ vpkshss: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vpkshss: => 7f7f7f7f 7f7f7f7f 7f7f7f7f 7f7f7f7f (00000000)
++ vpkshss: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vpkshss: => 80808080 80808080 7f7f7f7f 7f7f7f7f (00000000)
++ vpkshss: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vpkshss: => 7f7f7f7f 7f7f7f7f 80808080 80808080 (00000000)
++ vpkshss: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vpkshss: => 80808080 80808080 80808080 80808080 (00000000)
++
++ vpkswss: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vpkswss: => 7fff7fff 7fff7fff 7fff7fff 7fff7fff (00000000)
++ vpkswss: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vpkswss: => 80008000 80008000 7fff7fff 7fff7fff (00000000)
++ vpkswss: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vpkswss: => 7fff7fff 7fff7fff 80008000 80008000 (00000000)
++ vpkswss: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vpkswss: => 80008000 80008000 80008000 80008000 (00000000)
++
++ vpkpx: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vpkpx: => 80018000 04218421 80018000 04218421 (00000000)
++ vpkpx: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vpkpx: => fbdffbde 7fffffff 80018000 04218421 (00000000)
++ vpkpx: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vpkpx: => 80018000 04218421 fbdffbde 7fffffff (00000000)
++ vpkpx: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vpkpx: => fbdffbde 7fffffff fbdffbde 7fffffff (00000000)
++
++ vmrghb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vmrghb: => 0b0b0c0c 09090a0a 0e0e0f0f 0e0e0d0d (00000000)
++ vmrghb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmrghb: => 0bfb0cfc 09f90afa 0efe0fff 0efe0dfd (00000000)
++ vmrghb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vmrghb: => fb0bfc0c f909fa0a fe0eff0f fe0efd0d (00000000)
++ vmrghb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmrghb: => fbfbfcfc f9f9fafa fefeffff fefefdfd (00000000)
++
++ vmrghh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vmrghh: => 0b0c0b0c 090a090a 0e0f0e0f 0e0d0e0d (00000000)
++ vmrghh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmrghh: => 0b0cfbfc 090af9fa 0e0ffeff 0e0dfefd (00000000)
++ vmrghh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vmrghh: => fbfc0b0c f9fa090a feff0e0f fefd0e0d (00000000)
++ vmrghh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmrghh: => fbfcfbfc f9faf9fa fefffeff fefdfefd (00000000)
++
++ vmrghw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vmrghw: => 090a0b0c 090a0b0c 0e0d0e0f 0e0d0e0f (00000000)
++ vmrghw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmrghw: => f9fafbfc 090a0b0c fefdfeff 0e0d0e0f (00000000)
++ vmrghw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vmrghw: => 090a0b0c f9fafbfc 0e0d0e0f fefdfeff (00000000)
++ vmrghw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmrghw: => f9fafbfc f9fafbfc fefdfeff fefdfeff (00000000)
++
++ vmrglb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vmrglb: => 03030404 01010202 07070808 05050606 (00000000)
++ vmrglb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmrglb: => 03f304f4 01f102f2 07f708f8 05f506f6 (00000000)
++ vmrglb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vmrglb: => f303f404 f101f202 f707f808 f505f606 (00000000)
++ vmrglb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmrglb: => f3f3f4f4 f1f1f2f2 f7f7f8f8 f5f5f6f6 (00000000)
++
++ vmrglh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vmrglh: => 03040304 01020102 07080708 05060506 (00000000)
++ vmrglh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmrglh: => 0304f3f4 0102f1f2 0708f7f8 0506f5f6 (00000000)
++ vmrglh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vmrglh: => f3f40304 f1f20102 f7f80708 f5f60506 (00000000)
++ vmrglh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmrglh: => f3f4f3f4 f1f2f1f2 f7f8f7f8 f5f6f5f6 (00000000)
++
++ vmrglw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vmrglw: => 01020304 01020304 05060708 05060708 (00000000)
++ vmrglw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmrglw: => f1f2f3f4 01020304 f5f6f7f8 05060708 (00000000)
++ vmrglw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vmrglw: => 01020304 f1f2f3f4 05060708 f5f6f7f8 (00000000)
++ vmrglw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vmrglw: => f1f2f3f4 f1f2f3f4 f5f6f7f8 f5f6f7f8 (00000000)
++
++ vslo: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vslo: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ vslo: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vslo: => 00000000 00000000 00000000 03040000 (00000000)
++ vslo: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vslo: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++ vslo: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vslo: => 00000000 00000000 00000000 f3f40000 (00000000)
++
++ vsro: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vsro: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ vsro: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsro: => 00000e0d 00000000 00000000 00000000 (00000000)
++ vsro: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vsro: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++ vsro: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vsro: => 0000fefd 00000000 00000000 00000000 (00000000)
++
++PPC altivec integer logical insns with one arg:
++ vupkhsb: 01020304 05060708 090a0b0c 0e0d0e0f
++ vupkhsb: => 000b000c 0009000a 000e000f 000e000d (00000000)
++ vupkhsb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff
++ vupkhsb: => fffbfffc fff9fffa fffeffff fffefffd (00000000)
++
++ vupkhsh: 01020304 05060708 090a0b0c 0e0d0e0f
++ vupkhsh: => 00000b0c 0000090a 00000e0f 00000e0d (00000000)
++ vupkhsh: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff
++ vupkhsh: => fffffbfc fffff9fa fffffeff fffffefd (00000000)
++
++ vupkhpx: 01020304 05060708 090a0b0c 0e0d0e0f
++ vupkhpx: => 0002180c 0002080a 0003100f 0003100d (00000000)
++ vupkhpx: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff
++ vupkhpx: => ff1e1f1c ff1e0f1a ff1f171f ff1f171d (00000000)
++
++ vupklsb: 01020304 05060708 090a0b0c 0e0d0e0f
++ vupklsb: => 00030004 00010002 00070008 00050006 (00000000)
++ vupklsb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff
++ vupklsb: => fff3fff4 fff1fff2 fff7fff8 fff5fff6 (00000000)
++
++ vupklsh: 01020304 05060708 090a0b0c 0e0d0e0f
++ vupklsh: => 00000304 00000102 00000708 00000506 (00000000)
++ vupklsh: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff
++ vupklsh: => fffff3f4 fffff1f2 fffff7f8 fffff5f6 (00000000)
++
++ vupklpx: 01020304 05060708 090a0b0c 0e0d0e0f
++ vupklpx: => 00001804 00000802 00011808 00010806 (00000000)
++ vupklpx: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff
++ vupklpx: => ff1c1f14 ff1c0f12 ff1d1f18 ff1d0f16 (00000000)
++
++Altivec integer compare insns:
++ vcmpgtub: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vcmpgtub: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtub: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vcmpgtub: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vcmpgtub: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vcmpgtub: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vcmpgtub: => 00000000 00000000 00000000 00000000 (00000000)
++
++ vcmpgtuh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vcmpgtuh: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtuh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vcmpgtuh: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vcmpgtuh: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vcmpgtuh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vcmpgtuh: => 00000000 00000000 00000000 00000000 (00000000)
++
++ vcmpgtuw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vcmpgtuw: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtuw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vcmpgtuw: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vcmpgtuw: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vcmpgtuw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vcmpgtuw: => 00000000 00000000 00000000 00000000 (00000000)
++
++ vcmpgtsb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vcmpgtsb: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtsb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vcmpgtsb: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vcmpgtsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vcmpgtsb: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtsb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vcmpgtsb: => 00000000 00000000 00000000 00000000 (00000000)
++
++ vcmpgtsh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vcmpgtsh: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtsh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vcmpgtsh: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vcmpgtsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vcmpgtsh: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtsh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vcmpgtsh: => 00000000 00000000 00000000 00000000 (00000000)
++
++ vcmpgtsw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vcmpgtsw: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtsw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vcmpgtsw: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vcmpgtsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vcmpgtsw: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtsw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vcmpgtsw: => 00000000 00000000 00000000 00000000 (00000000)
++
++ vcmpequb: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vcmpequb: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vcmpequb: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vcmpequb: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpequb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vcmpequb: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpequb: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vcmpequb: => ffffffff ffffffff ffffffff ffffffff (00000000)
++
++ vcmpequh: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vcmpequh: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vcmpequh: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vcmpequh: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpequh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vcmpequh: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpequh: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vcmpequh: => ffffffff ffffffff ffffffff ffffffff (00000000)
++
++ vcmpequw: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vcmpequw: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vcmpequw: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vcmpequw: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpequw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vcmpequw: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpequw: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vcmpequw: => ffffffff ffffffff ffffffff ffffffff (00000000)
++
++Altivec integer compare insns with flags update:
++ vcmpgtub.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vcmpgtub.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtub.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vcmpgtub.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtub.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vcmpgtub.: => ffffffff ffffffff ffffffff ffffffff (00000080)
++ vcmpgtub.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vcmpgtub.: => 00000000 00000000 00000000 00000000 (00000020)
++
++ vcmpgtuh.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vcmpgtuh.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtuh.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vcmpgtuh.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtuh.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vcmpgtuh.: => ffffffff ffffffff ffffffff ffffffff (00000080)
++ vcmpgtuh.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vcmpgtuh.: => 00000000 00000000 00000000 00000000 (00000020)
++
++ vcmpgtuw.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vcmpgtuw.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtuw.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vcmpgtuw.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtuw.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vcmpgtuw.: => ffffffff ffffffff ffffffff ffffffff (00000080)
++ vcmpgtuw.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vcmpgtuw.: => 00000000 00000000 00000000 00000000 (00000020)
++
++ vcmpgtsb.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vcmpgtsb.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtsb.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vcmpgtsb.: => ffffffff ffffffff ffffffff ffffffff (00000080)
++ vcmpgtsb.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vcmpgtsb.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtsb.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vcmpgtsb.: => 00000000 00000000 00000000 00000000 (00000020)
++
++ vcmpgtsh.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vcmpgtsh.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtsh.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vcmpgtsh.: => ffffffff ffffffff ffffffff ffffffff (00000080)
++ vcmpgtsh.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vcmpgtsh.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtsh.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vcmpgtsh.: => 00000000 00000000 00000000 00000000 (00000020)
++
++ vcmpgtsw.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vcmpgtsw.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtsw.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vcmpgtsw.: => ffffffff ffffffff ffffffff ffffffff (00000080)
++ vcmpgtsw.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vcmpgtsw.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtsw.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vcmpgtsw.: => 00000000 00000000 00000000 00000000 (00000020)
++
++ vcmpequb.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vcmpequb.: => ffffffff ffffffff ffffffff ffffffff (00000080)
++ vcmpequb.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vcmpequb.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpequb.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vcmpequb.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpequb.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vcmpequb.: => ffffffff ffffffff ffffffff ffffffff (00000080)
++
++ vcmpequh.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vcmpequh.: => ffffffff ffffffff ffffffff ffffffff (00000080)
++ vcmpequh.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vcmpequh.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpequh.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vcmpequh.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpequh.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vcmpequh.: => ffffffff ffffffff ffffffff ffffffff (00000080)
++
++ vcmpequw.: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f
++ vcmpequw.: => ffffffff ffffffff ffffffff ffffffff (00000080)
++ vcmpequw.: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vcmpequw.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpequw.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f
++ vcmpequw.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpequw.: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff
++ vcmpequw.: => ffffffff ffffffff ffffffff ffffffff (00000080)
++
++Altivec integer special insns:
++ vsl: 0102030405060708090a0b0c0e0d0e0f, 00000000000000000000000000000000
++ vsl: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ vsl: 0102030405060708090a0b0c0e0d0e0f, 01010101010101010101010101010101
++ vsl: => 02040608 0a0c0e10 12141618 1c1a1c1e (00000000)
++ vsl: 0102030405060708090a0b0c0e0d0e0f, 02020202020202020202020202020202
++ vsl: => 04080c10 14181c20 24282c30 3834383c (00000000)
++ vsl: 0102030405060708090a0b0c0e0d0e0f, 03030303030303030303030303030303
++ vsl: => 08101820 28303840 48505860 70687078 (00000000)
++ vsl: 0102030405060708090a0b0c0e0d0e0f, 04040404040404040404040404040404
++ vsl: => 10203040 50607080 90a0b0c0 e0d0e0f0 (00000000)
++ vsl: 0102030405060708090a0b0c0e0d0e0f, 05050505050505050505050505050505
++ vsl: => 20406080 a0c0e100 21416180 c1a1c1e1 (00000000)
++ vsl: 0102030405060708090a0b0c0e0d0e0f, 06060606060606060606060606060606
++ vsl: => 4080c100 4181c200 4282c301 834383c2 (00000000)
++ vsl: 0102030405060708090a0b0c0e0d0e0f, 07070707070707070707070707070707
++ vsl: => 81018200 83038400 85058602 06870784 (00000000)
++ vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 00000000000000000000000000000000
++ vsl: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++ vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 01010101010101010101010101010101
++ vsl: => e3e5e7e8 ebedeff1 f3f5f7f9 fdfbfdff (00000000)
++ vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 02020202020202020202020202020202
++ vsl: => c7cbcfd0 d7dbdfe3 e7ebeff3 fbf7fbff (00000000)
++ vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 03030303030303030303030303030303
++ vsl: => 8f979fa0 afb7bfc7 cfd7dfe7 f7eff7ff (00000000)
++ vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 04040404040404040404040404040404
++ vsl: => 1f2f3f40 5f6f7f8f 9fafbfcf efdfefff (00000000)
++ vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 05050505050505050505050505050505
++ vsl: => 3e5e7e80 bedeff1e 3f5f7f9e dfbfdfff (00000000)
++ vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 06060606060606060606060606060606
++ vsl: => 7cbcfd00 7dbdfe3c 7ebeff3d bf7fbffe (00000000)
++ vsl: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 07070707070707070707070707070707
++ vsl: => f979fa00 fb7bfc78 fd7dfe7a 7eff7ffc (00000000)
++
++ vsr: 0102030405060708090a0b0c0e0d0e0f, 00000000000000000000000000000000
++ vsr: => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ vsr: 0102030405060708090a0b0c0e0d0e0f, 01010101010101010101010101010101
++ vsr: => 00810182 02830384 84850586 07068707 (00000000)
++ vsr: 0102030405060708090a0b0c0e0d0e0f, 02020202020202020202020202020202
++ vsr: => 004080c1 014181c2 c24282c3 03834383 (00000000)
++ vsr: 0102030405060708090a0b0c0e0d0e0f, 03030303030303030303030303030303
++ vsr: => 00204060 80a0c0e1 e1214161 01c1a1c1 (00000000)
++ vsr: 0102030405060708090a0b0c0e0d0e0f, 04040404040404040404040404040404
++ vsr: => 80102030 c0506070 f090a0b0 00e0d0e0 (00000000)
++ vsr: 0102030405060708090a0b0c0e0d0e0f, 05050505050505050505050505050505
++ vsr: => 40081018 60283038 78485058 00706870 (00000000)
++ vsr: 0102030405060708090a0b0c0e0d0e0f, 06060606060606060606060606060606
++ vsr: => 2004080c 3014181c 3c24282c 00383438 (00000000)
++ vsr: 0102030405060708090a0b0c0e0d0e0f, 07070707070707070707070707070707
++ vsr: => 10020406 180a0c0e 1e121416 001c1a1c (00000000)
++ vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 00000000000000000000000000000000
++ vsr: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++ vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 01010101010101010101010101010101
++ vsr: => 78f979fa 7afb7bfc fcfd7dfe 7f7eff7f (00000000)
++ vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 02020202020202020202020202020202
++ vsr: => 3c7cbcfd 3d7dbdfe fe7ebeff 3fbf7fbf (00000000)
++ vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 03030303030303030303030303030303
++ vsr: => 1e3e5e7e 9ebedeff ff3f5f7f 1fdfbfdf (00000000)
++ vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 04040404040404040404040404040404
++ vsr: => 8f1f2f3f cf5f6f7f ff9fafbf 0fefdfef (00000000)
++ vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 05050505050505050505050505050505
++ vsr: => c78f979f e7afb7bf ffcfd7df 07f7eff7 (00000000)
++ vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 06060606060606060606060606060606
++ vsr: => e3c7cbcf f3d7dbdf ffe7ebef 03fbf7fb (00000000)
++ vsr: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 07070707070707070707070707070707
++ vsr: => f1e3e5e7 f9ebedef fff3f5f7 01fdfbfd (00000000)
++
++ vspltb: 01020304 05060708 090a0b0c 0e0d0e0f, 0
++ vspltb: => 0e0e0e0e 0e0e0e0e 0e0e0e0e 0e0e0e0e (00000000)
++ vspltb: 01020304 05060708 090a0b0c 0e0d0e0f, 3
++ vspltb: => 0f0f0f0f 0f0f0f0f 0f0f0f0f 0f0f0f0f (00000000)
++ vspltb: 01020304 05060708 090a0b0c 0e0d0e0f, 6
++ vspltb: => 0b0b0b0b 0b0b0b0b 0b0b0b0b 0b0b0b0b (00000000)
++ vspltb: 01020304 05060708 090a0b0c 0e0d0e0f, 9
++ vspltb: => 06060606 06060606 06060606 06060606 (00000000)
++ vspltb: 01020304 05060708 090a0b0c 0e0d0e0f, 12
++ vspltb: => 01010101 01010101 01010101 01010101 (00000000)
++ vspltb: 01020304 05060708 090a0b0c 0e0d0e0f, 15
++ vspltb: => 04040404 04040404 04040404 04040404 (00000000)
++ vspltb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 0
++ vspltb: => fefefefe fefefefe fefefefe fefefefe (00000000)
++ vspltb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 3
++ vspltb: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vspltb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 6
++ vspltb: => fbfbfbfb fbfbfbfb fbfbfbfb fbfbfbfb (00000000)
++ vspltb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 9
++ vspltb: => f6f6f6f6 f6f6f6f6 f6f6f6f6 f6f6f6f6 (00000000)
++ vspltb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 12
++ vspltb: => f1f1f1f1 f1f1f1f1 f1f1f1f1 f1f1f1f1 (00000000)
++ vspltb: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 15
++ vspltb: => f4f4f4f4 f4f4f4f4 f4f4f4f4 f4f4f4f4 (00000000)
++
++ vsplth: 01020304 05060708 090a0b0c 0e0d0e0f, 0
++ vsplth: => 0e0d0e0d 0e0d0e0d 0e0d0e0d 0e0d0e0d (00000000)
++ vsplth: 01020304 05060708 090a0b0c 0e0d0e0f, 3
++ vsplth: => 0b0c0b0c 0b0c0b0c 0b0c0b0c 0b0c0b0c (00000000)
++ vsplth: 01020304 05060708 090a0b0c 0e0d0e0f, 6
++ vsplth: => 01020102 01020102 01020102 01020102 (00000000)
++ vsplth: 01020304 05060708 090a0b0c 0e0d0e0f, 9
++ vsplth: => 0e0f0e0f 0e0f0e0f 0e0f0e0f 0e0f0e0f (00000000)
++ vsplth: 01020304 05060708 090a0b0c 0e0d0e0f, 12
++ vsplth: => 05060506 05060506 05060506 05060506 (00000000)
++ vsplth: 01020304 05060708 090a0b0c 0e0d0e0f, 15
++ vsplth: => 03040304 03040304 03040304 03040304 (00000000)
++ vsplth: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 0
++ vsplth: => fefdfefd fefdfefd fefdfefd fefdfefd (00000000)
++ vsplth: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 3
++ vsplth: => fbfcfbfc fbfcfbfc fbfcfbfc fbfcfbfc (00000000)
++ vsplth: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 6
++ vsplth: => f1f2f1f2 f1f2f1f2 f1f2f1f2 f1f2f1f2 (00000000)
++ vsplth: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 9
++ vsplth: => fefffeff fefffeff fefffeff fefffeff (00000000)
++ vsplth: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 12
++ vsplth: => f5f6f5f6 f5f6f5f6 f5f6f5f6 f5f6f5f6 (00000000)
++ vsplth: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 15
++ vsplth: => f3f4f3f4 f3f4f3f4 f3f4f3f4 f3f4f3f4 (00000000)
++
++ vspltw: 01020304 05060708 090a0b0c 0e0d0e0f, 0
++ vspltw: => 0e0d0e0f 0e0d0e0f 0e0d0e0f 0e0d0e0f (00000000)
++ vspltw: 01020304 05060708 090a0b0c 0e0d0e0f, 3
++ vspltw: => 01020304 01020304 01020304 01020304 (00000000)
++ vspltw: 01020304 05060708 090a0b0c 0e0d0e0f, 6
++ vspltw: => 05060708 05060708 05060708 05060708 (00000000)
++ vspltw: 01020304 05060708 090a0b0c 0e0d0e0f, 9
++ vspltw: => 090a0b0c 090a0b0c 090a0b0c 090a0b0c (00000000)
++ vspltw: 01020304 05060708 090a0b0c 0e0d0e0f, 12
++ vspltw: => 0e0d0e0f 0e0d0e0f 0e0d0e0f 0e0d0e0f (00000000)
++ vspltw: 01020304 05060708 090a0b0c 0e0d0e0f, 15
++ vspltw: => 01020304 01020304 01020304 01020304 (00000000)
++ vspltw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 0
++ vspltw: => fefdfeff fefdfeff fefdfeff fefdfeff (00000000)
++ vspltw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 3
++ vspltw: => f1f2f3f4 f1f2f3f4 f1f2f3f4 f1f2f3f4 (00000000)
++ vspltw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 6
++ vspltw: => f5f6f7f8 f5f6f7f8 f5f6f7f8 f5f6f7f8 (00000000)
++ vspltw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 9
++ vspltw: => f9fafbfc f9fafbfc f9fafbfc f9fafbfc (00000000)
++ vspltw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 12
++ vspltw: => fefdfeff fefdfeff fefdfeff fefdfeff (00000000)
++ vspltw: f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff, 15
++ vspltw: => f1f2f3f4 f1f2f3f4 f1f2f3f4 f1f2f3f4 (00000000)
++
++ vspltisb: 0 => 00000000 00000000 00000000 00000000 (00000000)
++ vspltisb: 1 => 01010101 01010101 01010101 01010101 (00000000)
++ vspltisb: 2 => 02020202 02020202 02020202 02020202 (00000000)
++ vspltisb: 3 => 03030303 03030303 03030303 03030303 (00000000)
++ vspltisb: 4 => 04040404 04040404 04040404 04040404 (00000000)
++ vspltisb: 5 => 05050505 05050505 05050505 05050505 (00000000)
++ vspltisb: 6 => 06060606 06060606 06060606 06060606 (00000000)
++ vspltisb: 7 => 07070707 07070707 07070707 07070707 (00000000)
++ vspltisb: 8 => 08080808 08080808 08080808 08080808 (00000000)
++ vspltisb: 9 => 09090909 09090909 09090909 09090909 (00000000)
++ vspltisb: 10 => 0a0a0a0a 0a0a0a0a 0a0a0a0a 0a0a0a0a (00000000)
++ vspltisb: 11 => 0b0b0b0b 0b0b0b0b 0b0b0b0b 0b0b0b0b (00000000)
++ vspltisb: 12 => 0c0c0c0c 0c0c0c0c 0c0c0c0c 0c0c0c0c (00000000)
++ vspltisb: 13 => 0d0d0d0d 0d0d0d0d 0d0d0d0d 0d0d0d0d (00000000)
++ vspltisb: 14 => 0e0e0e0e 0e0e0e0e 0e0e0e0e 0e0e0e0e (00000000)
++ vspltisb: 15 => 0f0f0f0f 0f0f0f0f 0f0f0f0f 0f0f0f0f (00000000)
++ vspltisb: 16 => f0f0f0f0 f0f0f0f0 f0f0f0f0 f0f0f0f0 (00000000)
++ vspltisb: 17 => f1f1f1f1 f1f1f1f1 f1f1f1f1 f1f1f1f1 (00000000)
++ vspltisb: 18 => f2f2f2f2 f2f2f2f2 f2f2f2f2 f2f2f2f2 (00000000)
++ vspltisb: 19 => f3f3f3f3 f3f3f3f3 f3f3f3f3 f3f3f3f3 (00000000)
++ vspltisb: 20 => f4f4f4f4 f4f4f4f4 f4f4f4f4 f4f4f4f4 (00000000)
++ vspltisb: 21 => f5f5f5f5 f5f5f5f5 f5f5f5f5 f5f5f5f5 (00000000)
++ vspltisb: 22 => f6f6f6f6 f6f6f6f6 f6f6f6f6 f6f6f6f6 (00000000)
++ vspltisb: 23 => f7f7f7f7 f7f7f7f7 f7f7f7f7 f7f7f7f7 (00000000)
++ vspltisb: 24 => f8f8f8f8 f8f8f8f8 f8f8f8f8 f8f8f8f8 (00000000)
++ vspltisb: 25 => f9f9f9f9 f9f9f9f9 f9f9f9f9 f9f9f9f9 (00000000)
++ vspltisb: 26 => fafafafa fafafafa fafafafa fafafafa (00000000)
++ vspltisb: 27 => fbfbfbfb fbfbfbfb fbfbfbfb fbfbfbfb (00000000)
++ vspltisb: 28 => fcfcfcfc fcfcfcfc fcfcfcfc fcfcfcfc (00000000)
++ vspltisb: 29 => fdfdfdfd fdfdfdfd fdfdfdfd fdfdfdfd (00000000)
++ vspltisb: 30 => fefefefe fefefefe fefefefe fefefefe (00000000)
++ vspltisb: 31 => ffffffff ffffffff ffffffff ffffffff (00000000)
++
++ vspltish: 0 => 00000000 00000000 00000000 00000000 (00000000)
++ vspltish: 1 => 00010001 00010001 00010001 00010001 (00000000)
++ vspltish: 2 => 00020002 00020002 00020002 00020002 (00000000)
++ vspltish: 3 => 00030003 00030003 00030003 00030003 (00000000)
++ vspltish: 4 => 00040004 00040004 00040004 00040004 (00000000)
++ vspltish: 5 => 00050005 00050005 00050005 00050005 (00000000)
++ vspltish: 6 => 00060006 00060006 00060006 00060006 (00000000)
++ vspltish: 7 => 00070007 00070007 00070007 00070007 (00000000)
++ vspltish: 8 => 00080008 00080008 00080008 00080008 (00000000)
++ vspltish: 9 => 00090009 00090009 00090009 00090009 (00000000)
++ vspltish: 10 => 000a000a 000a000a 000a000a 000a000a (00000000)
++ vspltish: 11 => 000b000b 000b000b 000b000b 000b000b (00000000)
++ vspltish: 12 => 000c000c 000c000c 000c000c 000c000c (00000000)
++ vspltish: 13 => 000d000d 000d000d 000d000d 000d000d (00000000)
++ vspltish: 14 => 000e000e 000e000e 000e000e 000e000e (00000000)
++ vspltish: 15 => 000f000f 000f000f 000f000f 000f000f (00000000)
++ vspltish: 16 => fff0fff0 fff0fff0 fff0fff0 fff0fff0 (00000000)
++ vspltish: 17 => fff1fff1 fff1fff1 fff1fff1 fff1fff1 (00000000)
++ vspltish: 18 => fff2fff2 fff2fff2 fff2fff2 fff2fff2 (00000000)
++ vspltish: 19 => fff3fff3 fff3fff3 fff3fff3 fff3fff3 (00000000)
++ vspltish: 20 => fff4fff4 fff4fff4 fff4fff4 fff4fff4 (00000000)
++ vspltish: 21 => fff5fff5 fff5fff5 fff5fff5 fff5fff5 (00000000)
++ vspltish: 22 => fff6fff6 fff6fff6 fff6fff6 fff6fff6 (00000000)
++ vspltish: 23 => fff7fff7 fff7fff7 fff7fff7 fff7fff7 (00000000)
++ vspltish: 24 => fff8fff8 fff8fff8 fff8fff8 fff8fff8 (00000000)
++ vspltish: 25 => fff9fff9 fff9fff9 fff9fff9 fff9fff9 (00000000)
++ vspltish: 26 => fffafffa fffafffa fffafffa fffafffa (00000000)
++ vspltish: 27 => fffbfffb fffbfffb fffbfffb fffbfffb (00000000)
++ vspltish: 28 => fffcfffc fffcfffc fffcfffc fffcfffc (00000000)
++ vspltish: 29 => fffdfffd fffdfffd fffdfffd fffdfffd (00000000)
++ vspltish: 30 => fffefffe fffefffe fffefffe fffefffe (00000000)
++ vspltish: 31 => ffffffff ffffffff ffffffff ffffffff (00000000)
++
++ vspltisw: 0 => 00000000 00000000 00000000 00000000 (00000000)
++ vspltisw: 1 => 00000001 00000001 00000001 00000001 (00000000)
++ vspltisw: 2 => 00000002 00000002 00000002 00000002 (00000000)
++ vspltisw: 3 => 00000003 00000003 00000003 00000003 (00000000)
++ vspltisw: 4 => 00000004 00000004 00000004 00000004 (00000000)
++ vspltisw: 5 => 00000005 00000005 00000005 00000005 (00000000)
++ vspltisw: 6 => 00000006 00000006 00000006 00000006 (00000000)
++ vspltisw: 7 => 00000007 00000007 00000007 00000007 (00000000)
++ vspltisw: 8 => 00000008 00000008 00000008 00000008 (00000000)
++ vspltisw: 9 => 00000009 00000009 00000009 00000009 (00000000)
++ vspltisw: 10 => 0000000a 0000000a 0000000a 0000000a (00000000)
++ vspltisw: 11 => 0000000b 0000000b 0000000b 0000000b (00000000)
++ vspltisw: 12 => 0000000c 0000000c 0000000c 0000000c (00000000)
++ vspltisw: 13 => 0000000d 0000000d 0000000d 0000000d (00000000)
++ vspltisw: 14 => 0000000e 0000000e 0000000e 0000000e (00000000)
++ vspltisw: 15 => 0000000f 0000000f 0000000f 0000000f (00000000)
++ vspltisw: 16 => fffffff0 fffffff0 fffffff0 fffffff0 (00000000)
++ vspltisw: 17 => fffffff1 fffffff1 fffffff1 fffffff1 (00000000)
++ vspltisw: 18 => fffffff2 fffffff2 fffffff2 fffffff2 (00000000)
++ vspltisw: 19 => fffffff3 fffffff3 fffffff3 fffffff3 (00000000)
++ vspltisw: 20 => fffffff4 fffffff4 fffffff4 fffffff4 (00000000)
++ vspltisw: 21 => fffffff5 fffffff5 fffffff5 fffffff5 (00000000)
++ vspltisw: 22 => fffffff6 fffffff6 fffffff6 fffffff6 (00000000)
++ vspltisw: 23 => fffffff7 fffffff7 fffffff7 fffffff7 (00000000)
++ vspltisw: 24 => fffffff8 fffffff8 fffffff8 fffffff8 (00000000)
++ vspltisw: 25 => fffffff9 fffffff9 fffffff9 fffffff9 (00000000)
++ vspltisw: 26 => fffffffa fffffffa fffffffa fffffffa (00000000)
++ vspltisw: 27 => fffffffb fffffffb fffffffb fffffffb (00000000)
++ vspltisw: 28 => fffffffc fffffffc fffffffc fffffffc (00000000)
++ vspltisw: 29 => fffffffd fffffffd fffffffd fffffffd (00000000)
++ vspltisw: 30 => fffffffe fffffffe fffffffe fffffffe (00000000)
++ vspltisw: 31 => ffffffff ffffffff ffffffff ffffffff (00000000)
++
++ vsldoi: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 0
++ vsldoi: => 01020304 05060708 090a0b0c 0e0d0e0f] (00000000)
++ vsldoi: 0102030405060708090a0b0c0e0d0e0f, 0102030405060708090a0b0c0e0d0e0f, 14
++ vsldoi: => 07080102 0b0c0506 0e0f090a 03040e0d] (00000000)
++ vsldoi: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0
++ vsldoi: => 01020304 05060708 090a0b0c 0e0d0e0f] (00000000)
++ vsldoi: 0102030405060708090a0b0c0e0d0e0f, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 14
++ vsldoi: => f7f8f1f2 fbfcf5f6 fefff9fa 0304fefd] (00000000)
++ vsldoi: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 0
++ vsldoi: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff] (00000000)
++ vsldoi: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0102030405060708090a0b0c0e0d0e0f, 14
++ vsldoi: => 07080102 0b0c0506 0e0f090a f3f40e0d] (00000000)
++ vsldoi: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 0
++ vsldoi: => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff] (00000000)
++ vsldoi: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, f1f2f3f4f5f6f7f8f9fafbfcfefdfeff, 14
++ vsldoi: => f7f8f1f2 fbfcf5f6 fefff9fa f3f4fefd] (00000000)
++
++ lvsl 3, 0 => 0x1211100f0e0d0c0b 0x0a09080706050403 (00000000)
++ lvsl 4, 0 => 0x131211100f0e0d0c 0x0b0a090807060504 (00000000)
++ lvsl 5, 0 => 0x14131211100f0e0d 0x0c0b0a0908070605 (00000000)
++ lvsl 6, 0 => 0x1514131211100f0e 0x0d0c0b0a09080706 (00000000)
++ lvsl 7, 0 => 0x161514131211100f 0x0e0d0c0b0a090807 (00000000)
++ lvsl 8, 0 => 0x1716151413121110 0x0f0e0d0c0b0a0908 (00000000)
++ lvsl 9, 0 => 0x1817161514131211 0x100f0e0d0c0b0a09 (00000000)
++ lvsl a, 0 => 0x1918171615141312 0x11100f0e0d0c0b0a (00000000)
++ lvsl b, 0 => 0x1a19181716151413 0x1211100f0e0d0c0b (00000000)
++ lvsl c, 0 => 0x1b1a191817161514 0x131211100f0e0d0c (00000000)
++ lvsl d, 0 => 0x1c1b1a1918171615 0x14131211100f0e0d (00000000)
++ lvsl e, 0 => 0x1d1c1b1a19181716 0x1514131211100f0e (00000000)
++ lvsl f, 0 => 0x1e1d1c1b1a191817 0x161514131211100f (00000000)
++ lvsl 0, 0 => 0x0f0e0d0c0b0a0908 0x0706050403020100 (00000000)
++ lvsl 1, 0 => 0x100f0e0d0c0b0a09 0x0807060504030201 (00000000)
++ lvsl 2, 0 => 0x11100f0e0d0c0b0a 0x0908070605040302 (00000000)
++ lvsl 3, 0 => 0x1211100f0e0d0c0b 0x0a09080706050403 (00000000)
++ lvsl 4, 0 => 0x131211100f0e0d0c 0x0b0a090807060504 (00000000)
++
++ lvsr 3, 0 => 0x1c1b1a1918171615 0x14131211100f0e0d (00000000)
++ lvsr 4, 0 => 0x1b1a191817161514 0x131211100f0e0d0c (00000000)
++ lvsr 5, 0 => 0x1a19181716151413 0x1211100f0e0d0c0b (00000000)
++ lvsr 6, 0 => 0x1918171615141312 0x11100f0e0d0c0b0a (00000000)
++ lvsr 7, 0 => 0x1817161514131211 0x100f0e0d0c0b0a09 (00000000)
++ lvsr 8, 0 => 0x1716151413121110 0x0f0e0d0c0b0a0908 (00000000)
++ lvsr 9, 0 => 0x161514131211100f 0x0e0d0c0b0a090807 (00000000)
++ lvsr a, 0 => 0x1514131211100f0e 0x0d0c0b0a09080706 (00000000)
++ lvsr b, 0 => 0x14131211100f0e0d 0x0c0b0a0908070605 (00000000)
++ lvsr c, 0 => 0x131211100f0e0d0c 0x0b0a090807060504 (00000000)
++ lvsr d, 0 => 0x1211100f0e0d0c0b 0x0a09080706050403 (00000000)
++ lvsr e, 0 => 0x11100f0e0d0c0b0a 0x0908070605040302 (00000000)
++ lvsr f, 0 => 0x100f0e0d0c0b0a09 0x0807060504030201 (00000000)
++ lvsr 0, 0 => 0x1f1e1d1c1b1a1918 0x1716151413121110 (00000000)
++ lvsr 1, 0 => 0x1e1d1c1b1a191817 0x161514131211100f (00000000)
++ lvsr 2, 0 => 0x1d1c1b1a19181716 0x1514131211100f0e (00000000)
++ lvsr 3, 0 => 0x1c1b1a1918171615 0x14131211100f0e0d (00000000)
++ lvsr 4, 0 => 0x1b1a191817161514 0x131211100f0e0d0c (00000000)
++
++Altivec load insns with two register args:
++ lvebx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 00000004 00000000 00000000 00000000 (00000000)
++ lvebx 7, 01020304 05060708 090a0b0c 0e0d0e0f => 00000000 05000000 00000000 00000000 (00000000)
++ lvebx 14, 01020304 05060708 090a0b0c 0e0d0e0f => 00000000 00000000 00000000 000d0000 (00000000)
++ lvebx 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 000000f4 00000000 00000000 00000000 (00000000)
++ lvebx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 00000000 f5000000 00000000 00000000 (00000000)
++ lvebx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 00000000 00000000 00000000 00fd0000 (00000000)
++
++ lvehx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 00000304 00000000 00000000 00000000 (00000000)
++ lvehx 7, 01020304 05060708 090a0b0c 0e0d0e0f => 00000000 05060000 00000000 00000000 (00000000)
++ lvehx 14, 01020304 05060708 090a0b0c 0e0d0e0f => 00000000 00000000 00000000 0e0d0000 (00000000)
++ lvehx 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 0000f3f4 00000000 00000000 00000000 (00000000)
++ lvehx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 00000000 f5f60000 00000000 00000000 (00000000)
++ lvehx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 00000000 00000000 00000000 fefd0000 (00000000)
++
++ lvewx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 00000000 00000000 00000000 (00000000)
++ lvewx 7, 01020304 05060708 090a0b0c 0e0d0e0f => 00000000 05060708 00000000 00000000 (00000000)
++ lvewx 14, 01020304 05060708 090a0b0c 0e0d0e0f => 00000000 00000000 00000000 0e0d0e0f (00000000)
++ lvewx 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 00000000 00000000 00000000 (00000000)
++ lvewx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 00000000 f5f6f7f8 00000000 00000000 (00000000)
++ lvewx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 00000000 00000000 00000000 fefdfeff (00000000)
++
++ lvx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ lvx 7, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ lvx 14, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ lvx 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++ lvx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++ lvx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++
++ lvxl 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ lvxl 7, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ lvxl 14, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ lvxl 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++ lvxl 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++ lvxl 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++
++Altivec store insns with three register args:
++ stvebx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 00000004 00000000 00000000 00000000 (00000000)
++ stvebx 7, 01020304 05060708 090a0b0c 0e0d0e0f => 00000004 05000000 00000000 00000000 (00000000)
++ stvebx 14, 01020304 05060708 090a0b0c 0e0d0e0f => 00000004 05000000 00000000 000d0000 (00000000)
++ stvebx 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 000000f4 00000000 00000000 00000000 (00000000)
++ stvebx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 000000f4 f5000000 00000000 00000000 (00000000)
++ stvebx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 000000f4 f5000000 00000000 00fd0000 (00000000)
++
++ stvehx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 00000304 00000000 00000000 00000000 (00000000)
++ stvehx 7, 01020304 05060708 090a0b0c 0e0d0e0f => 00000304 05060000 00000000 00000000 (00000000)
++ stvehx 14, 01020304 05060708 090a0b0c 0e0d0e0f => 00000304 05060000 00000000 0e0d0000 (00000000)
++ stvehx 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 0000f3f4 00000000 00000000 00000000 (00000000)
++ stvehx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 0000f3f4 f5f60000 00000000 00000000 (00000000)
++ stvehx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => 0000f3f4 f5f60000 00000000 fefd0000 (00000000)
++
++ stvewx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 00000000 00000000 00000000 (00000000)
++ stvewx 7, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 00000000 00000000 (00000000)
++ stvewx 14, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 00000000 0e0d0e0f (00000000)
++ stvewx 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 00000000 00000000 00000000 (00000000)
++ stvewx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 00000000 00000000 (00000000)
++ stvewx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 00000000 fefdfeff (00000000)
++
++ stvx 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ stvx 7, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ stvx 14, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ stvx 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++ stvx 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++ stvx 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++
++ stvxl 0, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ stvxl 7, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ stvxl 14, 01020304 05060708 090a0b0c 0e0d0e0f => 01020304 05060708 090a0b0c 0e0d0e0f (00000000)
++ stvxl 0, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++ stvxl 7, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++ stvxl 14, f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff => f1f2f3f4 f5f6f7f8 f9fafbfc fefdfeff (00000000)
++
++Altivec floating point arith insns with two args:
++ vaddfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vaddfp: => 033fffff 033fffff 033fffff 033fffff (00000000)
++ vaddfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
++ vaddfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
++ vaddfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
++ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vaddfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
++ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vaddfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
++ vaddfp: => 513fffff 513fffff 513fffff 513fffff (00000000)
++ vaddfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
++ vaddfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vaddfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
++ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vaddfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
++ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vaddfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vaddfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vaddfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
++ vaddfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
++ vaddfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
++ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vaddfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
++ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vaddfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
++ vaddfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
++ vaddfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
++ vaddfp: => d1bfffff d1bfffff d1bfffff d1bfffff (00000000)
++ vaddfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
++ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vaddfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
++ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vaddfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
++ vaddfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
++ vaddfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
++ vaddfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
++ vaddfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
++ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vaddfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
++ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vaddfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
++ vaddfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
++ vaddfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
++ vaddfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
++ vaddfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
++ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vaddfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
++ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vaddfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
++ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vaddfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
++ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vaddfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
++ vaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vaddfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
++ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vaddfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
++ vaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
++ vaddfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
++ vaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
++ vaddfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
++ vaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
++ vaddfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
++ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vaddfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
++ vaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vaddfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
++ vaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vaddfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
++ vaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vaddfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
++ vaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vaddfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
++ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vaddfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
++ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vaddfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
++ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vaddfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
++ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
++ vaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
++ vaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
++ vaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
++ vaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vaddfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
++ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vaddfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
++ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vaddfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
++ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vaddfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
++ vaddfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++
++ vsubfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vsubfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vsubfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
++ vsubfp: => 513fffff 513fffff 513fffff 513fffff (00000000)
++ vsubfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
++ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
++ vsubfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
++ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vsubfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
++ vsubfp: => 513fffff 513fffff 513fffff 513fffff (00000000)
++ vsubfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
++ vsubfp: => 51bfffff 51bfffff 51bfffff 51bfffff (00000000)
++ vsubfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
++ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
++ vsubfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
++ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vsubfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vsubfp: => 833fffff 833fffff 833fffff 833fffff (00000000)
++ vsubfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
++ vsubfp: => 513fffff 513fffff 513fffff 513fffff (00000000)
++ vsubfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
++ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
++ vsubfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
++ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vsubfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
++ vsubfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
++ vsubfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
++ vsubfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vsubfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
++ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
++ vsubfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
++ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vsubfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
++ vsubfp: => 82bfffff 82bfffff 82bfffff 82bfffff (00000000)
++ vsubfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
++ vsubfp: => 513fffff 513fffff 513fffff 513fffff (00000000)
++ vsubfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
++ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
++ vsubfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
++ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vsubfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
++ vsubfp: => 82bfffff 82bfffff 82bfffff 82bfffff (00000000)
++ vsubfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
++ vsubfp: => 513fffff 513fffff 513fffff 513fffff (00000000)
++ vsubfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
++ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
++ vsubfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
++ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vsubfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
++ vsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vsubfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
++ vsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vsubfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
++ vsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
++ vsubfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
++ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vsubfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
++ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
++ vsubfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
++ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
++ vsubfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
++ vsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
++ vsubfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
++ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vsubfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
++ vsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vsubfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
++ vsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vsubfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
++ vsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vsubfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
++ vsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vsubfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
++ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vsubfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
++ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vsubfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
++ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vsubfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
++ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
++ vsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
++ vsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
++ vsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
++ vsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vsubfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
++ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vsubfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
++ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vsubfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
++ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vsubfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
++ vsubfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++
++ vmaxfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaxfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
++ vmaxfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
++ vmaxfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
++ vmaxfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
++ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vmaxfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
++ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vmaxfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaxfp: => 513fffff 513fffff 513fffff 513fffff (00000000)
++ vmaxfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
++ vmaxfp: => 513fffff 513fffff 513fffff 513fffff (00000000)
++ vmaxfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
++ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vmaxfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
++ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vmaxfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaxfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
++ vmaxfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
++ vmaxfp: => 82bfffff 82bfffff 82bfffff 82bfffff (00000000)
++ vmaxfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
++ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vmaxfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
++ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vmaxfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaxfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
++ vmaxfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
++ vmaxfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
++ vmaxfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
++ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vmaxfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
++ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vmaxfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
++ vmaxfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
++ vmaxfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
++ vmaxfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vmaxfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
++ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vmaxfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
++ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vmaxfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
++ vmaxfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
++ vmaxfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
++ vmaxfp: => 80000000 80000000 80000000 80000000 (00000000)
++ vmaxfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
++ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vmaxfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
++ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vmaxfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
++ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vmaxfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
++ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vmaxfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
++ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vmaxfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
++ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vmaxfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
++ vmaxfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
++ vmaxfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
++ vmaxfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
++ vmaxfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
++ vmaxfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vmaxfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
++ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vmaxfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaxfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaxfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
++ vmaxfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaxfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
++ vmaxfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaxfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
++ vmaxfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaxfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vmaxfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
++ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vmaxfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
++ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vmaxfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
++ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vmaxfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaxfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaxfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
++ vmaxfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaxfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
++ vmaxfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaxfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
++ vmaxfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaxfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vmaxfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
++ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vmaxfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
++ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vmaxfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
++ vmaxfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++
++ vminfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vminfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
++ vminfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
++ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
++ vminfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
++ vminfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
++ vminfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
++ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vminfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
++ vminfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
++ vminfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
++ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
++ vminfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
++ vminfp: => 513fffff 513fffff 513fffff 513fffff (00000000)
++ vminfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
++ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vminfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vminfp: => 82bfffff 82bfffff 82bfffff 82bfffff (00000000)
++ vminfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
++ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
++ vminfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
++ vminfp: => 82bfffff 82bfffff 82bfffff 82bfffff (00000000)
++ vminfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
++ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vminfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
++ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
++ vminfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
++ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
++ vminfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
++ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
++ vminfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
++ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vminfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
++ vminfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vminfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
++ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
++ vminfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
++ vminfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vminfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
++ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vminfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
++ vminfp: => 80000000 80000000 80000000 80000000 (00000000)
++ vminfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
++ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
++ vminfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
++ vminfp: => 80000000 80000000 80000000 80000000 (00000000)
++ vminfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
++ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vminfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
++ vminfp: => 02bfffff 02bfffff 02bfffff 02bfffff (00000000)
++ vminfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
++ vminfp: => d13fffff d13fffff d13fffff d13fffff (00000000)
++ vminfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
++ vminfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vminfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
++ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vminfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
++ vminfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
++ vminfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
++ vminfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
++ vminfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
++ vminfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
++ vminfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
++ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vminfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
++ vminfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vminfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
++ vminfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vminfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
++ vminfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vminfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
++ vminfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vminfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
++ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vminfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
++ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vminfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
++ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vminfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
++ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vminfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
++ vminfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vminfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
++ vminfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vminfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
++ vminfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vminfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
++ vminfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vminfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
++ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vminfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
++ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vminfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
++ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vminfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
++ vminfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++
++Altivec floating point arith insns with three args:
++ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
++ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
++ vmaddfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
++ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
++ vmaddfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
++ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
++ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
++ vmaddfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
++ vmaddfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
++ vmaddfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => e30ffffe e30ffffe e30ffffe e30ffffe (00000000)
++ vmaddfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
++ vmaddfp: => e30ffffe e30ffffe e30ffffe e30ffffe (00000000)
++ vmaddfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vmaddfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
++ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vmaddfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
++ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
++ vmaddfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
++ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
++ vmaddfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
++ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
++ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
++ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
++ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
++ vmaddfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
++ vmaddfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
++ vmaddfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => 630ffffe 630ffffe 630ffffe 630ffffe (00000000)
++ vmaddfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
++ vmaddfp: => 630ffffe 630ffffe 630ffffe 630ffffe (00000000)
++ vmaddfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
++ vmaddfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
++ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
++ vmaddfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
++ vmaddfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
++ vmaddfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vmaddfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
++ vmaddfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
++ vmaddfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vmaddfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
++ vmaddfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
++ vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
++ vmaddfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
++ vmaddfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
++ vmaddfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vmaddfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
++ vmaddfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
++ vmaddfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vmaddfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
++ vmaddfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
++ vmaddfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
++ vmaddfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vmaddfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
++ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vmaddfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
++ vmaddfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
++ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
++ vmaddfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vmaddfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
++ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vmaddfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
++ vmaddfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
++ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
++ vmaddfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vmaddfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
++ vmaddfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vmaddfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
++ vmaddfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
++ vmaddfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
++ vmaddfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vmaddfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vmaddfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++
++ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
++ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
++ vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
++ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
++ vnmsubfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
++ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
++ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
++ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
++ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
++ vnmsubfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
++ vnmsubfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
++ vnmsubfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => 630ffffe 630ffffe 630ffffe 630ffffe (00000000)
++ vnmsubfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
++ vnmsubfp: => 630ffffe 630ffffe 630ffffe 630ffffe (00000000)
++ vnmsubfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
++ vnmsubfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
++ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
++ vnmsubfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
++ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
++ vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
++ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
++ vnmsubfp: => 948ffffe 948ffffe 948ffffe 948ffffe (00000000)
++ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
++ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
++ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
++ vnmsubfp: => 148ffffe 148ffffe 148ffffe 148ffffe (00000000)
++ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => e30ffffe e30ffffe e30ffffe e30ffffe (00000000)
++ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
++ vnmsubfp: => e30ffffe e30ffffe e30ffffe e30ffffe (00000000)
++ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
++ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
++ vnmsubfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
++ vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vnmsubfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
++ vnmsubfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
++ vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vnmsubfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
++ vnmsubfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
++ vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
++ vnmsubfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
++ vnmsubfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
++ vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vnmsubfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => 02bffffe 02bffffe 02bffffe 02bffffe (00000000)
++ vnmsubfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
++ vnmsubfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vnmsubfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
++ vnmsubfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
++ vnmsubfp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
++ vnmsubfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
++ vnmsubfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
++ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
++ vnmsubfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vnmsubfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
++ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vnmsubfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
++ vnmsubfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
++ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
++ vnmsubfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vnmsubfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
++ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vnmsubfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
++ vnmsubfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
++ vnmsubfp: => ff800000 ff800000 ff800000 ff800000 (00000000)
++ vnmsubfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vnmsubfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
++ vnmsubfp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vnmsubfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 80000000800000008000000080000000
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 80000000800000008000000080000000
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 80000000800000008000000080000000
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 80000000800000008000000080000000
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vnmsubfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff, 7fbfffff7fbfffff7fbfffff7fbfffff
++ vnmsubfp: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++
++Altivec floating point arith insns with one arg:
++ vrfin: 02bfffff 02bfffff 02bfffff 02bfffff
++ vrfin: => 00000000 00000000 00000000 00000000 (00000000)
++ vrfin: 513fffff 513fffff 513fffff 513fffff
++ vrfin: => 513fffff 513fffff 513fffff 513fffff (00000000)
++ vrfin: 82bfffff 82bfffff 82bfffff 82bfffff
++ vrfin: => 80000000 80000000 80000000 80000000 (00000000)
++ vrfin: d13fffff d13fffff d13fffff d13fffff
++ vrfin: => d13fffff d13fffff d13fffff d13fffff (00000000)
++ vrfin: 00000000 00000000 00000000 00000000
++ vrfin: => 00000000 00000000 00000000 00000000 (00000000)
++ vrfin: 80000000 80000000 80000000 80000000
++ vrfin: => 80000000 80000000 80000000 80000000 (00000000)
++ vrfin: 7f800000 7f800000 7f800000 7f800000
++ vrfin: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vrfin: ff800000 ff800000 ff800000 ff800000
++ vrfin: => ff800000 ff800000 ff800000 ff800000 (00000000)
++ vrfin: 7fffffff 7fffffff 7fffffff 7fffffff
++ vrfin: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vrfin: ffffffff ffffffff ffffffff ffffffff
++ vrfin: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vrfin: 7fbfffff 7fbfffff 7fbfffff 7fbfffff
++ vrfin: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vrfin: ffbfffff ffbfffff ffbfffff ffbfffff
++ vrfin: => ffffffff ffffffff ffffffff ffffffff (00000000)
++
++ vrfiz: 02bfffff 02bfffff 02bfffff 02bfffff
++ vrfiz: => 00000000 00000000 00000000 00000000 (00000000)
++ vrfiz: 513fffff 513fffff 513fffff 513fffff
++ vrfiz: => 513fffff 513fffff 513fffff 513fffff (00000000)
++ vrfiz: 82bfffff 82bfffff 82bfffff 82bfffff
++ vrfiz: => 80000000 80000000 80000000 80000000 (00000000)
++ vrfiz: d13fffff d13fffff d13fffff d13fffff
++ vrfiz: => d13fffff d13fffff d13fffff d13fffff (00000000)
++ vrfiz: 00000000 00000000 00000000 00000000
++ vrfiz: => 00000000 00000000 00000000 00000000 (00000000)
++ vrfiz: 80000000 80000000 80000000 80000000
++ vrfiz: => 80000000 80000000 80000000 80000000 (00000000)
++ vrfiz: 7f800000 7f800000 7f800000 7f800000
++ vrfiz: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vrfiz: ff800000 ff800000 ff800000 ff800000
++ vrfiz: => ff800000 ff800000 ff800000 ff800000 (00000000)
++ vrfiz: 7fffffff 7fffffff 7fffffff 7fffffff
++ vrfiz: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vrfiz: ffffffff ffffffff ffffffff ffffffff
++ vrfiz: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vrfiz: 7fbfffff 7fbfffff 7fbfffff 7fbfffff
++ vrfiz: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vrfiz: ffbfffff ffbfffff ffbfffff ffbfffff
++ vrfiz: => ffffffff ffffffff ffffffff ffffffff (00000000)
++
++ vrfip: 02bfffff 02bfffff 02bfffff 02bfffff
++ vrfip: => 3f800000 3f800000 3f800000 3f800000 (00000000)
++ vrfip: 513fffff 513fffff 513fffff 513fffff
++ vrfip: => 513fffff 513fffff 513fffff 513fffff (00000000)
++ vrfip: 82bfffff 82bfffff 82bfffff 82bfffff
++ vrfip: => 80000000 80000000 80000000 80000000 (00000000)
++ vrfip: d13fffff d13fffff d13fffff d13fffff
++ vrfip: => d13fffff d13fffff d13fffff d13fffff (00000000)
++ vrfip: 00000000 00000000 00000000 00000000
++ vrfip: => 00000000 00000000 00000000 00000000 (00000000)
++ vrfip: 80000000 80000000 80000000 80000000
++ vrfip: => 80000000 80000000 80000000 80000000 (00000000)
++ vrfip: 7f800000 7f800000 7f800000 7f800000
++ vrfip: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vrfip: ff800000 ff800000 ff800000 ff800000
++ vrfip: => ff800000 ff800000 ff800000 ff800000 (00000000)
++ vrfip: 7fffffff 7fffffff 7fffffff 7fffffff
++ vrfip: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vrfip: ffffffff ffffffff ffffffff ffffffff
++ vrfip: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vrfip: 7fbfffff 7fbfffff 7fbfffff 7fbfffff
++ vrfip: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vrfip: ffbfffff ffbfffff ffbfffff ffbfffff
++ vrfip: => ffffffff ffffffff ffffffff ffffffff (00000000)
++
++ vrfim: 02bfffff 02bfffff 02bfffff 02bfffff
++ vrfim: => 00000000 00000000 00000000 00000000 (00000000)
++ vrfim: 513fffff 513fffff 513fffff 513fffff
++ vrfim: => 513fffff 513fffff 513fffff 513fffff (00000000)
++ vrfim: 82bfffff 82bfffff 82bfffff 82bfffff
++ vrfim: => bf800000 bf800000 bf800000 bf800000 (00000000)
++ vrfim: d13fffff d13fffff d13fffff d13fffff
++ vrfim: => d13fffff d13fffff d13fffff d13fffff (00000000)
++ vrfim: 00000000 00000000 00000000 00000000
++ vrfim: => 00000000 00000000 00000000 00000000 (00000000)
++ vrfim: 80000000 80000000 80000000 80000000
++ vrfim: => 80000000 80000000 80000000 80000000 (00000000)
++ vrfim: 7f800000 7f800000 7f800000 7f800000
++ vrfim: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vrfim: ff800000 ff800000 ff800000 ff800000
++ vrfim: => ff800000 ff800000 ff800000 ff800000 (00000000)
++ vrfim: 7fffffff 7fffffff 7fffffff 7fffffff
++ vrfim: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vrfim: ffffffff ffffffff ffffffff ffffffff
++ vrfim: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vrfim: 7fbfffff 7fbfffff 7fbfffff 7fbfffff
++ vrfim: => 7fffffff 7fffffff 7fffffff 7fffffff (00000000)
++ vrfim: ffbfffff ffbfffff ffbfffff ffbfffff
++ vrfim: => ffffffff ffffffff ffffffff ffffffff (00000000)
++
++ vrefp: 02bfffff 02bfffff 02bfffff 02bfffff
++ vrefp: => 7c2a8000 7c2a8000 7c2a8000 7c2a8000 (00000000)
++ vrefp: 513fffff 513fffff 513fffff 513fffff
++ vrefp: => 2daa8000 2daa8000 2daa8000 2daa8000 (00000000)
++ vrefp: 82bfffff 82bfffff 82bfffff 82bfffff
++ vrefp: => fc2a8000 fc2a8000 fc2a8000 fc2a8000 (00000000)
++ vrefp: d13fffff d13fffff d13fffff d13fffff
++ vrefp: => adaa8000 adaa8000 adaa8000 adaa8000 (00000000)
++ vrefp: 00000000 00000000 00000000 00000000
++ vrefp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vrefp: 80000000 80000000 80000000 80000000
++ vrefp: => ff800000 ff800000 ff800000 ff800000 (00000000)
++ vrefp: 7f800000 7f800000 7f800000 7f800000
++ vrefp: => 00000000 00000000 00000000 00000000 (00000000)
++ vrefp: ff800000 ff800000 ff800000 ff800000
++ vrefp: => 80000000 80000000 80000000 80000000 (00000000)
++ vrefp: 7fffffff 7fffffff 7fffffff 7fffffff
++ vrefp: => 7fffc000 7fffc000 7fffc000 7fffc000 (00000000)
++ vrefp: ffffffff ffffffff ffffffff ffffffff
++ vrefp: => ffffc000 ffffc000 ffffc000 ffffc000 (00000000)
++ vrefp: 7fbfffff 7fbfffff 7fbfffff 7fbfffff
++ vrefp: => 7fffc000 7fffc000 7fffc000 7fffc000 (00000000)
++ vrefp: ffbfffff ffbfffff ffbfffff ffbfffff
++ vrefp: => ffffc000 ffffc000 ffffc000 ffffc000 (00000000)
++
++ vrsqrtefp: 02bfffff 02bfffff 02bfffff 02bfffff
++ vrsqrtefp: => 5dd10000 5dd10000 5dd10000 5dd10000 (00000000)
++ vrsqrtefp: 513fffff 513fffff 513fffff 513fffff
++ vrsqrtefp: => 3693c000 3693c000 3693c000 3693c000 (00000000)
++ vrsqrtefp: 82bfffff 82bfffff 82bfffff 82bfffff
++ vrsqrtefp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
++ vrsqrtefp: d13fffff d13fffff d13fffff d13fffff
++ vrsqrtefp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
++ vrsqrtefp: 00000000 00000000 00000000 00000000
++ vrsqrtefp: => 7f800000 7f800000 7f800000 7f800000 (00000000)
++ vrsqrtefp: 80000000 80000000 80000000 80000000
++ vrsqrtefp: => ff800000 ff800000 ff800000 ff800000 (00000000)
++ vrsqrtefp: 7f800000 7f800000 7f800000 7f800000
++ vrsqrtefp: => 00000000 00000000 00000000 00000000 (00000000)
++ vrsqrtefp: ff800000 ff800000 ff800000 ff800000
++ vrsqrtefp: => 7fc00000 7fc00000 7fc00000 7fc00000 (00000000)
++ vrsqrtefp: 7fffffff 7fffffff 7fffffff 7fffffff
++ vrsqrtefp: => 7fffc000 7fffc000 7fffc000 7fffc000 (00000000)
++ vrsqrtefp: ffffffff ffffffff ffffffff ffffffff
++ vrsqrtefp: => ffffc000 ffffc000 ffffc000 ffffc000 (00000000)
++ vrsqrtefp: 7fbfffff 7fbfffff 7fbfffff 7fbfffff
++ vrsqrtefp: => 7fffc000 7fffc000 7fffc000 7fffc000 (00000000)
++ vrsqrtefp: ffbfffff ffbfffff ffbfffff ffbfffff
++ vrsqrtefp: => ffffc000 ffffc000 ffffc000 ffffc000 (00000000)
++
++Altivec floating point compare insns:
++ vcmpgtfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpgtfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vcmpgtfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
++ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
++ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgtfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vcmpgtfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpgtfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vcmpgtfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
++ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
++ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpgtfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vcmpgtfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
++ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
++ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
++ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
++ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
++ vcmpgtfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vcmpgtfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
++ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
++ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
++ vcmpgtfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vcmpgtfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
++ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
++ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgtfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vcmpgtfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
++ vcmpgtfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vcmpgtfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
++ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
++ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
++ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
++ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
++ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
++ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
++ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
++ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
++ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
++ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
++ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
++ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgtfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
++ vcmpgtfp: => 00000000 00000000 00000000 00000000 (00000000)
++
++ vcmpeqfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpeqfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vcmpeqfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpeqfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vcmpeqfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
++ vcmpeqfp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vcmpeqfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpeqfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
++ vcmpeqfp: => 00000000 00000000 00000000 00000000 (00000000)
++
++ vcmpgefp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vcmpgefp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vcmpgefp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
++ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgefp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
++ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgefp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vcmpgefp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vcmpgefp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
++ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgefp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
++ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgefp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgefp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vcmpgefp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
++ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgefp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
++ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgefp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgefp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vcmpgefp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
++ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgefp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
++ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgefp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgefp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
++ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vcmpgefp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
++ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgefp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
++ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgefp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgefp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
++ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vcmpgefp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
++ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgefp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
++ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgefp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vcmpgefp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
++ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vcmpgefp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
++ vcmpgefp: => ffffffff ffffffff ffffffff ffffffff (00000000)
++ vcmpgefp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
++ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgefp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgefp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
++ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgefp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
++ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgefp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
++ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgefp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgefp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgefp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
++ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgefp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
++ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgefp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgefp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgefp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
++ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgefp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
++ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgefp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgefp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgefp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
++ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgefp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
++ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgefp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgefp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgefp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
++ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpgefp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
++ vcmpgefp: => 00000000 00000000 00000000 00000000 (00000000)
++
++ vcmpbfp: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpbfp: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
++ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpbfp: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
++ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpbfp: => 80000000 80000000 80000000 80000000 (00000000)
++ vcmpbfp: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpbfp: => 80000000 80000000 80000000 80000000 (00000000)
++ vcmpbfp: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
++ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpbfp: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
++ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpbfp: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
++ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpbfp: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
++ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpbfp: => 40000000 40000000 40000000 40000000 (00000000)
++ vcmpbfp: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpbfp: => 40000000 40000000 40000000 40000000 (00000000)
++ vcmpbfp: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
++ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpbfp: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
++ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
++ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpbfp: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
++ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
++ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpbfp: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
++ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
++ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpbfp: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
++ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
++ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpbfp: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
++ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
++ vcmpbfp: => 80000000 80000000 80000000 80000000 (00000000)
++ vcmpbfp: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
++ vcmpbfp: => 80000000 80000000 80000000 80000000 (00000000)
++ vcmpbfp: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
++ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpbfp: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
++ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
++ vcmpbfp: => 40000000 40000000 40000000 40000000 (00000000)
++ vcmpbfp: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
++ vcmpbfp: => 40000000 40000000 40000000 40000000 (00000000)
++ vcmpbfp: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
++ vcmpbfp: => 00000000 00000000 00000000 00000000 (00000000)
++ vcmpbfp: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
++ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
++ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
++ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
++ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
++ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
++ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
++ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
++ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
++ vcmpbfp: => c0000000 c0000000 c0000000 c0000000 (00000000)
++
++Altivec floating point compare insns with flags update:
++ vcmpgtfp.: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtfp.: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpgtfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
++ vcmpgtfp.: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
++ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtfp.: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
++ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtfp.: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgtfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
++ vcmpgtfp.: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpgtfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
++ vcmpgtfp.: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
++ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtfp.: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
++ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtfp.: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtfp.: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpgtfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
++ vcmpgtfp.: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
++ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtfp.: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
++ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtfp.: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtfp.: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtfp.: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
++ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtfp.: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
++ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtfp.: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtfp.: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
++ vcmpgtfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
++ vcmpgtfp.: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
++ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtfp.: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
++ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtfp.: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtfp.: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
++ vcmpgtfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
++ vcmpgtfp.: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
++ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtfp.: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
++ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtfp.: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgtfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
++ vcmpgtfp.: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
++ vcmpgtfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
++ vcmpgtfp.: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
++ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtfp.: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
++ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtfp.: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtfp.: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
++ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtfp.: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
++ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtfp.: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
++ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtfp.: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtfp.: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtfp.: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
++ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtfp.: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
++ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtfp.: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtfp.: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtfp.: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
++ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtfp.: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
++ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
++ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
++ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtfp.: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtfp.: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtfp.: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
++ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgtfp.: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
++ vcmpgtfp.: => 00000000 00000000 00000000 00000000 (00000020)
++
++ vcmpeqfp.: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpeqfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
++ vcmpeqfp.: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpeqfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
++ vcmpeqfp.: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
++ vcmpeqfp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
++ vcmpeqfp.: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpeqfp.: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
++ vcmpeqfp.: => 00000000 00000000 00000000 00000000 (00000020)
++
++ vcmpgefp.: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
++ vcmpgefp.: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
++ vcmpgefp.: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
++ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgefp.: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
++ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgefp.: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
++ vcmpgefp.: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
++ vcmpgefp.: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
++ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgefp.: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
++ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgefp.: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgefp.: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
++ vcmpgefp.: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
++ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgefp.: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
++ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgefp.: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgefp.: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
++ vcmpgefp.: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
++ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgefp.: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
++ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgefp.: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgefp.: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
++ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
++ vcmpgefp.: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
++ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgefp.: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
++ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgefp.: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgefp.: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
++ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
++ vcmpgefp.: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
++ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgefp.: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
++ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgefp.: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
++ vcmpgefp.: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
++ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
++ vcmpgefp.: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
++ vcmpgefp.: => ffffffff ffffffff ffffffff ffffffff (00000080)
++ vcmpgefp.: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
++ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgefp.: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgefp.: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
++ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgefp.: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
++ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgefp.: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
++ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgefp.: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgefp.: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgefp.: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
++ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgefp.: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
++ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgefp.: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgefp.: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgefp.: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
++ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgefp.: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
++ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgefp.: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgefp.: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgefp.: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
++ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgefp.: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
++ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgefp.: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgefp.: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgefp.: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
++ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpgefp.: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
++ vcmpgefp.: => 00000000 00000000 00000000 00000000 (00000020)
++
++ vcmpbfp.: 02bfffff02bfffff02bfffff02bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpbfp.: 02bfffff02bfffff02bfffff02bfffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp.: 02bfffff02bfffff02bfffff02bfffff, 7f8000007f8000007f8000007f800000
++ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpbfp.: 02bfffff02bfffff02bfffff02bfffff, ffffffffffffffffffffffffffffffff
++ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp.: 513fffff513fffff513fffff513fffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpbfp.: => 80000000 80000000 80000000 80000000 (00000000)
++ vcmpbfp.: 513fffff513fffff513fffff513fffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpbfp.: => 80000000 80000000 80000000 80000000 (00000000)
++ vcmpbfp.: 513fffff513fffff513fffff513fffff, 7f8000007f8000007f8000007f800000
++ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpbfp.: 513fffff513fffff513fffff513fffff, ffffffffffffffffffffffffffffffff
++ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp.: 82bfffff82bfffff82bfffff82bfffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpbfp.: 82bfffff82bfffff82bfffff82bfffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp.: 82bfffff82bfffff82bfffff82bfffff, 7f8000007f8000007f8000007f800000
++ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpbfp.: 82bfffff82bfffff82bfffff82bfffff, ffffffffffffffffffffffffffffffff
++ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp.: d13fffffd13fffffd13fffffd13fffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpbfp.: => 40000000 40000000 40000000 40000000 (00000000)
++ vcmpbfp.: d13fffffd13fffffd13fffffd13fffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpbfp.: => 40000000 40000000 40000000 40000000 (00000000)
++ vcmpbfp.: d13fffffd13fffffd13fffffd13fffff, 7f8000007f8000007f8000007f800000
++ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpbfp.: d13fffffd13fffffd13fffffd13fffff, ffffffffffffffffffffffffffffffff
++ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp.: 00000000000000000000000000000000, 02bfffff02bfffff02bfffff02bfffff
++ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpbfp.: 00000000000000000000000000000000, d13fffffd13fffffd13fffffd13fffff
++ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp.: 00000000000000000000000000000000, 7f8000007f8000007f8000007f800000
++ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpbfp.: 00000000000000000000000000000000, ffffffffffffffffffffffffffffffff
++ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp.: 80000000800000008000000080000000, 02bfffff02bfffff02bfffff02bfffff
++ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpbfp.: 80000000800000008000000080000000, d13fffffd13fffffd13fffffd13fffff
++ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp.: 80000000800000008000000080000000, 7f8000007f8000007f8000007f800000
++ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpbfp.: 80000000800000008000000080000000, ffffffffffffffffffffffffffffffff
++ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp.: 7f8000007f8000007f8000007f800000, 02bfffff02bfffff02bfffff02bfffff
++ vcmpbfp.: => 80000000 80000000 80000000 80000000 (00000000)
++ vcmpbfp.: 7f8000007f8000007f8000007f800000, d13fffffd13fffffd13fffffd13fffff
++ vcmpbfp.: => 80000000 80000000 80000000 80000000 (00000000)
++ vcmpbfp.: 7f8000007f8000007f8000007f800000, 7f8000007f8000007f8000007f800000
++ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpbfp.: 7f8000007f8000007f8000007f800000, ffffffffffffffffffffffffffffffff
++ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp.: ff800000ff800000ff800000ff800000, 02bfffff02bfffff02bfffff02bfffff
++ vcmpbfp.: => 40000000 40000000 40000000 40000000 (00000000)
++ vcmpbfp.: ff800000ff800000ff800000ff800000, d13fffffd13fffffd13fffffd13fffff
++ vcmpbfp.: => 40000000 40000000 40000000 40000000 (00000000)
++ vcmpbfp.: ff800000ff800000ff800000ff800000, 7f8000007f8000007f8000007f800000
++ vcmpbfp.: => 00000000 00000000 00000000 00000000 (00000020)
++ vcmpbfp.: ff800000ff800000ff800000ff800000, ffffffffffffffffffffffffffffffff
++ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp.: 7fffffff7fffffff7fffffff7fffffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp.: 7fffffff7fffffff7fffffff7fffffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp.: 7fffffff7fffffff7fffffff7fffffff, 7f8000007f8000007f8000007f800000
++ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp.: 7fffffff7fffffff7fffffff7fffffff, ffffffffffffffffffffffffffffffff
++ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp.: ffffffffffffffffffffffffffffffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp.: ffffffffffffffffffffffffffffffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp.: ffffffffffffffffffffffffffffffff, 7f8000007f8000007f8000007f800000
++ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp.: ffffffffffffffffffffffffffffffff, ffffffffffffffffffffffffffffffff
++ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, 7f8000007f8000007f8000007f800000
++ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp.: 7fbfffff7fbfffff7fbfffff7fbfffff, ffffffffffffffffffffffffffffffff
++ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp.: ffbfffffffbfffffffbfffffffbfffff, 02bfffff02bfffff02bfffff02bfffff
++ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp.: ffbfffffffbfffffffbfffffffbfffff, d13fffffd13fffffd13fffffd13fffff
++ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp.: ffbfffffffbfffffffbfffffffbfffff, 7f8000007f8000007f8000007f800000
++ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
++ vcmpbfp.: ffbfffffffbfffffffbfffffffbfffff, ffffffffffffffffffffffffffffffff
++ vcmpbfp.: => c0000000 c0000000 c0000000 c0000000 (00000000)
++
++Altivec float special insns:
++ vcfux: 02bfffff ( 2.821186e-37), 0 => 4c300000 ( 4.613734e+07) (00000000)
++ vcfux: 02bfffff ( 2.821186e-37), 9 => 47b00000 ( 9.011200e+04) (00000000)
++ vcfux: 02bfffff ( 2.821186e-37), 18 => 43300000 ( 1.760000e+02) (00000000)
++ vcfux: 02bfffff ( 2.821186e-37), 27 => 3eb00000 ( 3.437500e-01) (00000000)
++ vcfux: 513fffff ( 5.153960e+10), 0 => 4ea28000 ( 1.363149e+09) (00000000)
++ vcfux: 513fffff ( 5.153960e+10), 9 => 4a228000 ( 2.662400e+06) (00000000)
++ vcfux: 513fffff ( 5.153960e+10), 18 => 45a28000 ( 5.200000e+03) (00000000)
++ vcfux: 513fffff ( 5.153960e+10), 27 => 41228000 ( 1.015625e+01) (00000000)
++ vcfux: 82bfffff (-2.821186e-37), 0 => 4f02c000 ( 2.193621e+09) (00000000)
++ vcfux: 82bfffff (-2.821186e-37), 9 => 4a82c000 ( 4.284416e+06) (00000000)
++ vcfux: 82bfffff (-2.821186e-37), 18 => 4602c000 ( 8.368000e+03) (00000000)
++ vcfux: 82bfffff (-2.821186e-37), 27 => 4182c000 ( 1.634375e+01) (00000000)
++ vcfux: d13fffff (-5.153960e+10), 0 => 4f514000 ( 3.510632e+09) (00000000)
++ vcfux: d13fffff (-5.153960e+10), 9 => 4ad14000 ( 6.856704e+06) (00000000)
++ vcfux: d13fffff (-5.153960e+10), 18 => 46514000 ( 1.339200e+04) (00000000)
++ vcfux: d13fffff (-5.153960e+10), 27 => 41d14000 ( 2.615625e+01) (00000000)
++ vcfux: 00000000 ( 0.000000e+00), 0 => 00000000 ( 0.000000e+00) (00000000)
++ vcfux: 00000000 ( 0.000000e+00), 9 => 00000000 ( 0.000000e+00) (00000000)
++ vcfux: 00000000 ( 0.000000e+00), 18 => 00000000 ( 0.000000e+00) (00000000)
++ vcfux: 00000000 ( 0.000000e+00), 27 => 00000000 ( 0.000000e+00) (00000000)
++ vcfux: 80000000 (-0.000000e+00), 0 => 4f000000 ( 2.147484e+09) (00000000)
++ vcfux: 80000000 (-0.000000e+00), 9 => 4a800000 ( 4.194304e+06) (00000000)
++ vcfux: 80000000 (-0.000000e+00), 18 => 46000000 ( 8.192000e+03) (00000000)
++ vcfux: 80000000 (-0.000000e+00), 27 => 41800000 ( 1.600000e+01) (00000000)
++ vcfux: 7f800000 ( inf), 0 => 4eff0000 ( 2.139095e+09) (00000000)
++ vcfux: 7f800000 ( inf), 9 => 4a7f0000 ( 4.177920e+06) (00000000)
++ vcfux: 7f800000 ( inf), 18 => 45ff0000 ( 8.160000e+03) (00000000)
++ vcfux: 7f800000 ( inf), 27 => 417f0000 ( 1.593750e+01) (00000000)
++ vcfux: ff800000 ( -inf), 0 => 4f7f8000 ( 4.286579e+09) (00000000)
++ vcfux: ff800000 ( -inf), 9 => 4aff8000 ( 8.372224e+06) (00000000)
++ vcfux: ff800000 ( -inf), 18 => 467f8000 ( 1.635200e+04) (00000000)
++ vcfux: ff800000 ( -inf), 27 => 41ff8000 ( 3.193750e+01) (00000000)
++ vcfux: 7fffffff ( nan), 0 => 4f000000 ( 2.147484e+09) (00000000)
++ vcfux: 7fffffff ( nan), 9 => 4a800000 ( 4.194304e+06) (00000000)
++ vcfux: 7fffffff ( nan), 18 => 46000000 ( 8.192000e+03) (00000000)
++ vcfux: 7fffffff ( nan), 27 => 41800000 ( 1.600000e+01) (00000000)
++ vcfux: ffffffff ( -nan), 0 => 4f800000 ( 4.294967e+09) (00000000)
++ vcfux: ffffffff ( -nan), 9 => 4b000000 ( 8.388608e+06) (00000000)
++ vcfux: ffffffff ( -nan), 18 => 46800000 ( 1.638400e+04) (00000000)
++ vcfux: ffffffff ( -nan), 27 => 42000000 ( 3.200000e+01) (00000000)
++ vcfux: 7fbfffff ( nan), 0 => 4eff8000 ( 2.143289e+09) (00000000)
++ vcfux: 7fbfffff ( nan), 9 => 4a7f8000 ( 4.186112e+06) (00000000)
++ vcfux: 7fbfffff ( nan), 18 => 45ff8000 ( 8.176000e+03) (00000000)
++ vcfux: 7fbfffff ( nan), 27 => 417f8000 ( 1.596875e+01) (00000000)
++ vcfux: ffbfffff ( -nan), 0 => 4f7fc000 ( 4.290773e+09) (00000000)
++ vcfux: ffbfffff ( -nan), 9 => 4affc000 ( 8.380416e+06) (00000000)
++ vcfux: ffbfffff ( -nan), 18 => 467fc000 ( 1.636800e+04) (00000000)
++ vcfux: ffbfffff ( -nan), 27 => 41ffc000 ( 3.196875e+01) (00000000)
++
++ vcfsx: 02bfffff ( 2.821186e-37), 0 => 4c300000 ( 4.613734e+07) (00000000)
++ vcfsx: 02bfffff ( 2.821186e-37), 9 => 47b00000 ( 9.011200e+04) (00000000)
++ vcfsx: 02bfffff ( 2.821186e-37), 18 => 43300000 ( 1.760000e+02) (00000000)
++ vcfsx: 02bfffff ( 2.821186e-37), 27 => 3eb00000 ( 3.437500e-01) (00000000)
++ vcfsx: 513fffff ( 5.153960e+10), 0 => 4ea28000 ( 1.363149e+09) (00000000)
++ vcfsx: 513fffff ( 5.153960e+10), 9 => 4a228000 ( 2.662400e+06) (00000000)
++ vcfsx: 513fffff ( 5.153960e+10), 18 => 45a28000 ( 5.200000e+03) (00000000)
++ vcfsx: 513fffff ( 5.153960e+10), 27 => 41228000 ( 1.015625e+01) (00000000)
++ vcfsx: 82bfffff (-2.821186e-37), 0 => cefa8000 (-2.101346e+09) (00000000)
++ vcfsx: 82bfffff (-2.821186e-37), 9 => ca7a8000 (-4.104192e+06) (00000000)
++ vcfsx: 82bfffff (-2.821186e-37), 18 => c5fa8000 (-8.016000e+03) (00000000)
++ vcfsx: 82bfffff (-2.821186e-37), 27 => c17a8000 (-1.565625e+01) (00000000)
++ vcfsx: d13fffff (-5.153960e+10), 0 => ce3b0000 (-7.843348e+08) (00000000)
++ vcfsx: d13fffff (-5.153960e+10), 9 => c9bb0000 (-1.531904e+06) (00000000)
++ vcfsx: d13fffff (-5.153960e+10), 18 => c53b0000 (-2.992000e+03) (00000000)
++ vcfsx: d13fffff (-5.153960e+10), 27 => c0bb0000 (-5.843750e+00) (00000000)
++ vcfsx: 00000000 ( 0.000000e+00), 0 => 00000000 ( 0.000000e+00) (00000000)
++ vcfsx: 00000000 ( 0.000000e+00), 9 => 00000000 ( 0.000000e+00) (00000000)
++ vcfsx: 00000000 ( 0.000000e+00), 18 => 00000000 ( 0.000000e+00) (00000000)
++ vcfsx: 00000000 ( 0.000000e+00), 27 => 00000000 ( 0.000000e+00) (00000000)
++ vcfsx: 80000000 (-0.000000e+00), 0 => cf000000 (-2.147484e+09) (00000000)
++ vcfsx: 80000000 (-0.000000e+00), 9 => ca800000 (-4.194304e+06) (00000000)
++ vcfsx: 80000000 (-0.000000e+00), 18 => c6000000 (-8.192000e+03) (00000000)
++ vcfsx: 80000000 (-0.000000e+00), 27 => c1800000 (-1.600000e+01) (00000000)
++ vcfsx: 7f800000 ( inf), 0 => 4eff0000 ( 2.139095e+09) (00000000)
++ vcfsx: 7f800000 ( inf), 9 => 4a7f0000 ( 4.177920e+06) (00000000)
++ vcfsx: 7f800000 ( inf), 18 => 45ff0000 ( 8.160000e+03) (00000000)
++ vcfsx: 7f800000 ( inf), 27 => 417f0000 ( 1.593750e+01) (00000000)
++ vcfsx: ff800000 ( -inf), 0 => cb000000 (-8.388608e+06) (00000000)
++ vcfsx: ff800000 ( -inf), 9 => c6800000 (-1.638400e+04) (00000000)
++ vcfsx: ff800000 ( -inf), 18 => c2000000 (-3.200000e+01) (00000000)
++ vcfsx: ff800000 ( -inf), 27 => bd800000 (-6.250000e-02) (00000000)
++ vcfsx: 7fffffff ( nan), 0 => 4f000000 ( 2.147484e+09) (00000000)
++ vcfsx: 7fffffff ( nan), 9 => 4a800000 ( 4.194304e+06) (00000000)
++ vcfsx: 7fffffff ( nan), 18 => 46000000 ( 8.192000e+03) (00000000)
++ vcfsx: 7fffffff ( nan), 27 => 41800000 ( 1.600000e+01) (00000000)
++ vcfsx: ffffffff ( -nan), 0 => bf800000 (-1.000000e+00) (00000000)
++ vcfsx: ffffffff ( -nan), 9 => bb000000 (-1.953125e-03) (00000000)
++ vcfsx: ffffffff ( -nan), 18 => b6800000 (-3.814697e-06) (00000000)
++ vcfsx: ffffffff ( -nan), 27 => b2000000 (-7.450581e-09) (00000000)
++ vcfsx: 7fbfffff ( nan), 0 => 4eff8000 ( 2.143289e+09) (00000000)
++ vcfsx: 7fbfffff ( nan), 9 => 4a7f8000 ( 4.186112e+06) (00000000)
++ vcfsx: 7fbfffff ( nan), 18 => 45ff8000 ( 8.176000e+03) (00000000)
++ vcfsx: 7fbfffff ( nan), 27 => 417f8000 ( 1.596875e+01) (00000000)
++ vcfsx: ffbfffff ( -nan), 0 => ca800002 (-4.194305e+06) (00000000)
++ vcfsx: ffbfffff ( -nan), 9 => c6000002 (-8.192002e+03) (00000000)
++ vcfsx: ffbfffff ( -nan), 18 => c1800002 (-1.600000e+01) (00000000)
++ vcfsx: ffbfffff ( -nan), 27 => bd000002 (-3.125001e-02) (00000000)
++
++ vctuxs: 02bfffff ( 2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: 02bfffff ( 2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: 02bfffff ( 2.821186e-37), 18 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: 02bfffff ( 2.821186e-37), 27 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: 513fffff ( 5.153960e+10), 0 => ffffffff ( -nan) (00000000)
++ vctuxs: 513fffff ( 5.153960e+10), 9 => ffffffff ( -nan) (00000000)
++ vctuxs: 513fffff ( 5.153960e+10), 18 => ffffffff ( -nan) (00000000)
++ vctuxs: 513fffff ( 5.153960e+10), 27 => ffffffff ( -nan) (00000000)
++ vctuxs: 82bfffff (-2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: 82bfffff (-2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: 82bfffff (-2.821186e-37), 18 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: 82bfffff (-2.821186e-37), 27 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: d13fffff (-5.153960e+10), 0 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: d13fffff (-5.153960e+10), 9 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: d13fffff (-5.153960e+10), 18 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: d13fffff (-5.153960e+10), 27 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: 00000000 ( 0.000000e+00), 0 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: 00000000 ( 0.000000e+00), 9 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: 00000000 ( 0.000000e+00), 18 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: 00000000 ( 0.000000e+00), 27 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: 80000000 (-0.000000e+00), 0 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: 80000000 (-0.000000e+00), 9 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: 80000000 (-0.000000e+00), 18 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: 80000000 (-0.000000e+00), 27 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: 7f800000 ( inf), 0 => ffffffff ( -nan) (00000000)
++ vctuxs: 7f800000 ( inf), 9 => ffffffff ( -nan) (00000000)
++ vctuxs: 7f800000 ( inf), 18 => ffffffff ( -nan) (00000000)
++ vctuxs: 7f800000 ( inf), 27 => ffffffff ( -nan) (00000000)
++ vctuxs: ff800000 ( -inf), 0 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: ff800000 ( -inf), 9 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: ff800000 ( -inf), 18 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: ff800000 ( -inf), 27 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: 7fffffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: 7fffffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: 7fffffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: 7fffffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: ffffffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: ffffffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: ffffffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: ffffffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: 7fbfffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: 7fbfffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: 7fbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: 7fbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: ffbfffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: ffbfffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: ffbfffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000)
++ vctuxs: ffbfffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000)
++
++ vctsxs: 02bfffff ( 2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: 02bfffff ( 2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: 02bfffff ( 2.821186e-37), 18 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: 02bfffff ( 2.821186e-37), 27 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: 513fffff ( 5.153960e+10), 0 => 7fffffff ( nan) (00000000)
++ vctsxs: 513fffff ( 5.153960e+10), 9 => 7fffffff ( nan) (00000000)
++ vctsxs: 513fffff ( 5.153960e+10), 18 => 7fffffff ( nan) (00000000)
++ vctsxs: 513fffff ( 5.153960e+10), 27 => 7fffffff ( nan) (00000000)
++ vctsxs: 82bfffff (-2.821186e-37), 0 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: 82bfffff (-2.821186e-37), 9 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: 82bfffff (-2.821186e-37), 18 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: 82bfffff (-2.821186e-37), 27 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: d13fffff (-5.153960e+10), 0 => 80000000 (-0.000000e+00) (00000000)
++ vctsxs: d13fffff (-5.153960e+10), 9 => 80000000 (-0.000000e+00) (00000000)
++ vctsxs: d13fffff (-5.153960e+10), 18 => 80000000 (-0.000000e+00) (00000000)
++ vctsxs: d13fffff (-5.153960e+10), 27 => 80000000 (-0.000000e+00) (00000000)
++ vctsxs: 00000000 ( 0.000000e+00), 0 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: 00000000 ( 0.000000e+00), 9 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: 00000000 ( 0.000000e+00), 18 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: 00000000 ( 0.000000e+00), 27 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: 80000000 (-0.000000e+00), 0 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: 80000000 (-0.000000e+00), 9 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: 80000000 (-0.000000e+00), 18 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: 80000000 (-0.000000e+00), 27 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: 7f800000 ( inf), 0 => 7fffffff ( nan) (00000000)
++ vctsxs: 7f800000 ( inf), 9 => 7fffffff ( nan) (00000000)
++ vctsxs: 7f800000 ( inf), 18 => 7fffffff ( nan) (00000000)
++ vctsxs: 7f800000 ( inf), 27 => 7fffffff ( nan) (00000000)
++ vctsxs: ff800000 ( -inf), 0 => 80000000 (-0.000000e+00) (00000000)
++ vctsxs: ff800000 ( -inf), 9 => 80000000 (-0.000000e+00) (00000000)
++ vctsxs: ff800000 ( -inf), 18 => 80000000 (-0.000000e+00) (00000000)
++ vctsxs: ff800000 ( -inf), 27 => 80000000 (-0.000000e+00) (00000000)
++ vctsxs: 7fffffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: 7fffffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: 7fffffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: 7fffffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: ffffffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: ffffffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: ffffffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: ffffffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: 7fbfffff ( nan), 0 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: 7fbfffff ( nan), 9 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: 7fbfffff ( nan), 18 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: 7fbfffff ( nan), 27 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: ffbfffff ( -nan), 0 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: ffbfffff ( -nan), 9 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: ffbfffff ( -nan), 18 => 00000000 ( 0.000000e+00) (00000000)
++ vctsxs: ffbfffff ( -nan), 27 => 00000000 ( 0.000000e+00) (00000000)
++
++All done. Tested 165 different instructions
+diff --git a/none/tests/ppc64/jm_vec_isa_2_07.stdout.exp b/none/tests/ppc64/jm_vec_isa_2_07.stdout.exp
+index 604cb7d..9b5c24f 100644
+--- a/none/tests/ppc64/jm_vec_isa_2_07.stdout.exp
++++ b/none/tests/ppc64/jm_vec_isa_2_07.stdout.exp
+@@ -443,9 +443,9 @@ vsubuqm: 0102030405060708090a0b0c0e0d0e0f @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==
+ vsubuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f ==> f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0
+ vsubuqm: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==> 00000000000000000000000000000000
+
+-vbpermq: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f ==> 0000000000000000000000000000020a
++vbpermq: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f ==> 000000000000020a0000000000000000
+ vbpermq: 0102030405060708090a0b0c0e0d0e0f @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==> 00000000000000000000000000000000
+-vbpermq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f ==> 0000000000000000000000000000e3ea
++vbpermq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ 0102030405060708090a0b0c0e0d0e0f ==> 000000000000e3ea0000000000000000
+ vbpermq: f1f2f3f4f5f6f7f8f9fafbfcfefdfeff @@ f1f2f3f4f5f6f7f8f9fafbfcfefdfeff ==> 00000000000000000000000000000000
+
+ vaddecuq: 0102030405060708090a0b0c0e0d0e0f @@ 0102030405060708090a0b0c0e0d0e0f @@ f000000000000000 ==> 00000000000000000000000000000000
+diff --git a/none/tests/ppc64/lsw.vgtest b/none/tests/ppc64/lsw.vgtest
+index 8039094..4aec364 100644
+--- a/none/tests/ppc64/lsw.vgtest
++++ b/none/tests/ppc64/lsw.vgtest
+@@ -1 +1,2 @@
++prereq: ../../../tests/is_ppc64_BE
+ prog: lsw
+diff --git a/none/tests/ppc64/round.c b/none/tests/ppc64/round.c
+index dd2bef6..296710d 100644
+--- a/none/tests/ppc64/round.c
++++ b/none/tests/ppc64/round.c
+@@ -49,19 +49,32 @@ typedef unsigned int fpscr_t;
+ typedef union {
+ float flt;
+ struct {
++#if defined(VGP_ppc64le_linux)
++ unsigned int frac:23;
++ unsigned int exp:8;
++ unsigned int sign:1;
++#else
+ unsigned int sign:1;
+ unsigned int exp:8;
+ unsigned int frac:23;
++#endif
+ } layout;
+ } flt_overlay;
+
+ typedef union {
+ double dbl;
+ struct {
++#if defined(VGP_ppc64le_linux)
++ unsigned int frac_lo:32;
++ unsigned int frac_hi:20;
++ unsigned int exp:11;
++ unsigned int sign:1;
++#else
+ unsigned int sign:1;
+ unsigned int exp:11;
+ unsigned int frac_hi:20;
+ unsigned int frac_lo:32;
++#endif
+ } layout;
+ struct {
+ unsigned int hi;
+@@ -227,7 +240,7 @@ init()
+ F.layout.frac = 1;
+ denorm_small = F.flt; /* == 2^(-149) */
+ if (debug) {
+- print_double("float small", F.flt);
++ print_single("float small", &F.flt);
+ }
+
+ D.layout.sign = 0;
+diff --git a/none/tests/ppc64/round.stdout.exp-RM-fix b/none/tests/ppc64/round.stdout.exp-RM-fix
+new file mode 100644
+index 0000000..bf01bd4
+--- /dev/null
++++ b/none/tests/ppc64/round.stdout.exp-RM-fix
+@@ -0,0 +1,2384 @@
++-------------------------- test denormalized convert --------------------------
++near:PASSED:(double)(0x1p-148 ) = 0x1.cp-149
++near:PASSED:(double)(0x1p-149 ) = 0x1.4p-149
++zero:PASSED:(double)(0x1p-149 ) = 0x1.cp-149
++zero:PASSED:(double)(0x1p-149 ) = 0x1.4p-149
+++inf:PASSED:(double)(0x1p-148 ) = 0x1.cp-149
+++inf:PASSED:(double)(0x1p-148 ) = 0x1.4p-149
++-inf:PASSED:(double)(0x1p-149 ) = 0x1.cp-149
++-inf:PASSED:(double)(0x1p-149 ) = 0x1.4p-149
++-------------------------- test normalized convert --------------------------
++near:PASSED:(double)(0x1.000004p-126 ) = 0x1.0000038p-126
++near:PASSED:(double)(0x1.000002p-126 ) = 0x1.0000028p-126
++zero:PASSED:(double)(0x1.000002p-126 ) = 0x1.0000038p-126
++zero:PASSED:(double)(0x1.000002p-126 ) = 0x1.0000028p-126
+++inf:PASSED:(double)(0x1.000004p-126 ) = 0x1.0000038p-126
+++inf:PASSED:(double)(0x1.000004p-126 ) = 0x1.0000028p-126
++-inf:PASSED:(double)(0x1.000002p-126 ) = 0x1.0000038p-126
++-inf:PASSED:(double)(0x1.000002p-126 ) = 0x1.0000028p-126
++-------------------------- test (float)int convert --------------------------
++near:PASSED:(float)( int) 67047421 = 67047420.0
++near:PASSED:(float)(long) 67047421 = 67047420.0
++near:PASSED:(float)( int) 67047423 = 67047424.0
++near:PASSED:(float)(long) 67047423 = 67047424.0
++zero:PASSED:(float)( int) 67047421 = 67047420.0
++zero:PASSED:(float)(long) 67047421 = 67047420.0
++zero:PASSED:(float)( int) 67047423 = 67047420.0
++zero:PASSED:(float)(long) 67047423 = 67047420.0
+++inf:PASSED:(float)( int) 67047421 = 67047424.0
+++inf:PASSED:(float)(long) 67047421 = 67047424.0
+++inf:PASSED:(float)( int) 67047423 = 67047424.0
+++inf:PASSED:(float)(long) 67047423 = 67047424.0
++-inf:PASSED:(float)( int) 67047421 = 67047420.0
++-inf:PASSED:(float)(long) 67047421 = 67047420.0
++-inf:PASSED:(float)( int) 67047423 = 67047420.0
++-inf:PASSED:(float)(long) 67047423 = 67047420.0
++near:PASSED:(float)( int)-67047421 = -67047420.0
++near:PASSED:(float)(long)-67047421 = -67047420.0
++near:PASSED:(float)( int)-67047423 = -67047424.0
++near:PASSED:(float)(long)-67047423 = -67047424.0
++zero:PASSED:(float)( int)-67047421 = -67047420.0
++zero:PASSED:(float)(long)-67047421 = -67047420.0
++zero:PASSED:(float)( int)-67047423 = -67047420.0
++zero:PASSED:(float)(long)-67047423 = -67047420.0
+++inf:PASSED:(float)( int)-67047421 = -67047420.0
+++inf:PASSED:(float)(long)-67047421 = -67047420.0
+++inf:PASSED:(float)( int)-67047423 = -67047420.0
+++inf:PASSED:(float)(long)-67047423 = -67047420.0
++-inf:PASSED:(float)( int)-67047421 = -67047424.0
++-inf:PASSED:(float)(long)-67047421 = -67047424.0
++-inf:PASSED:(float)( int)-67047423 = -67047424.0
++-inf:PASSED:(float)(long)-67047423 = -67047424.0
++-------------------------- test (float)int convert --------------------------
++near:PASSED:(float)( int) 67047421 = 67047420.0
++near:PASSED:(float)(long) 67047421 = 67047420.0
++near:PASSED:(float)( int) 67047423 = 67047424.0
++near:PASSED:(float)(long) 67047423 = 67047424.0
++zero:PASSED:(float)( int) 67047421 = 67047420.0
++zero:PASSED:(float)(long) 67047421 = 67047420.0
++zero:PASSED:(float)( int) 67047423 = 67047420.0
++zero:PASSED:(float)(long) 67047423 = 67047420.0
+++inf:PASSED:(float)( int) 67047421 = 67047424.0
+++inf:PASSED:(float)(long) 67047421 = 67047424.0
+++inf:PASSED:(float)( int) 67047423 = 67047424.0
+++inf:PASSED:(float)(long) 67047423 = 67047424.0
++-inf:PASSED:(float)( int) 67047421 = 67047420.0
++-inf:PASSED:(float)(long) 67047421 = 67047420.0
++-inf:PASSED:(float)( int) 67047423 = 67047420.0
++-inf:PASSED:(float)(long) 67047423 = 67047420.0
++near:PASSED:(float)( int)-67047421 = -67047420.0
++near:PASSED:(float)(long)-67047421 = -67047420.0
++near:PASSED:(float)( int)-67047423 = -67047424.0
++near:PASSED:(float)(long)-67047423 = -67047424.0
++zero:PASSED:(float)( int)-67047421 = -67047420.0
++zero:PASSED:(float)(long)-67047421 = -67047420.0
++zero:PASSED:(float)( int)-67047423 = -67047420.0
++zero:PASSED:(float)(long)-67047423 = -67047420.0
+++inf:PASSED:(float)( int)-67047421 = -67047420.0
+++inf:PASSED:(float)(long)-67047421 = -67047420.0
+++inf:PASSED:(float)( int)-67047423 = -67047420.0
+++inf:PASSED:(float)(long)-67047423 = -67047420.0
++-inf:PASSED:(float)( int)-67047421 = -67047424.0
++-inf:PASSED:(float)(long)-67047421 = -67047424.0
++-inf:PASSED:(float)( int)-67047423 = -67047424.0
++-inf:PASSED:(float)(long)-67047423 = -67047424.0
++-------------------------- test (double)long convert --------------------------
++near:PASSED:(double)( 36012304344547325) = 36012304344547324.0
++near:PASSED:(double)( 36012304344547327) = 36012304344547328.0
++zero:PASSED:(double)( 36012304344547325) = 36012304344547324.0
++zero:PASSED:(double)( 36012304344547327) = 36012304344547324.0
+++inf:PASSED:(double)( 36012304344547325) = 36012304344547328.0
+++inf:PASSED:(double)( 36012304344547327) = 36012304344547328.0
++-inf:PASSED:(double)( 36012304344547325) = 36012304344547324.0
++-inf:PASSED:(double)( 36012304344547327) = 36012304344547324.0
++near:PASSED:(double)(-36012304344547325) = -36012304344547324.0
++near:PASSED:(double)(-36012304344547327) = -36012304344547328.0
++zero:PASSED:(double)(-36012304344547325) = -36012304344547324.0
++zero:PASSED:(double)(-36012304344547327) = -36012304344547324.0
+++inf:PASSED:(double)(-36012304344547325) = -36012304344547324.0
+++inf:PASSED:(double)(-36012304344547327) = -36012304344547324.0
++-inf:PASSED:(double)(-36012304344547325) = -36012304344547328.0
++-inf:PASSED:(double)(-36012304344547327) = -36012304344547328.0
++-------------------------- test rounding of float operators without guard bits --------------------------
++near:PASSED:fadds(-0x1p-149 , -0x1p-151 ) = -0x1p-149
++near:PASSED:fadds(-0x1p-149 , -0x1.8p-150 ) = -0x1p-148
++near:PASSED:fadds(0x1p-149 , 0x1p-151 ) = 0x1p-149
++near:PASSED:fadds(0x1p-149 , 0x1.8p-150 ) = 0x1p-148
++zero:PASSED:fadds(-0x1p-149 , -0x1p-151 ) = -0x1p-149
++zero:PASSED:fadds(-0x1p-149 , -0x1.8p-150 ) = -0x1p-149
++zero:PASSED:fadds(0x1p-149 , 0x1p-151 ) = 0x1p-149
++zero:PASSED:fadds(0x1p-149 , 0x1.8p-150 ) = 0x1p-149
+++inf:PASSED:fadds(-0x1p-149 , -0x1p-151 ) = -0x1p-149
+++inf:PASSED:fadds(-0x1p-149 , -0x1.8p-150 ) = -0x1p-149
+++inf:PASSED:fadds(0x1p-149 , 0x1p-151 ) = 0x1p-148
+++inf:PASSED:fadds(0x1p-149 , 0x1.8p-150 ) = 0x1p-148
++-inf:PASSED:fadds(-0x1p-149 , -0x1p-151 ) = -0x1p-148
++-inf:PASSED:fadds(-0x1p-149 , -0x1.8p-150 ) = -0x1p-148
++-inf:PASSED:fadds(0x1p-149 , 0x1p-151 ) = 0x1p-149
++-inf:PASSED:fadds(0x1p-149 , 0x1.8p-150 ) = 0x1p-149
++near:PASSED:fsubs(-0x1p-148 , -0x1.8p-150 ) = -0x1p-149
++near:PASSED:fsubs(-0x1p-148 , -0x1p-151 ) = -0x1p-148
++near:PASSED:fsubs(0x1p-148 , 0x1.8p-150 ) = 0x1p-149
++near:PASSED:fsubs(0x1p-148 , 0x1p-151 ) = 0x1p-148
++zero:PASSED:fsubs(-0x1p-148 , -0x1.8p-150 ) = -0x1p-149
++zero:PASSED:fsubs(-0x1p-148 , -0x1p-151 ) = -0x1p-149
++zero:PASSED:fsubs(0x1p-148 , 0x1.8p-150 ) = 0x1p-149
++zero:PASSED:fsubs(0x1p-148 , 0x1p-151 ) = 0x1p-149
+++inf:PASSED:fsubs(-0x1p-148 , -0x1.8p-150 ) = -0x1p-149
+++inf:PASSED:fsubs(-0x1p-148 , -0x1p-151 ) = -0x1p-149
+++inf:PASSED:fsubs(0x1p-148 , 0x1.8p-150 ) = 0x1p-148
+++inf:PASSED:fsubs(0x1p-148 , 0x1p-151 ) = 0x1p-148
++-inf:PASSED:fsubs(-0x1p-148 , -0x1.8p-150 ) = -0x1p-148
++-inf:PASSED:fsubs(-0x1p-148 , -0x1p-151 ) = -0x1p-148
++-inf:PASSED:fsubs(0x1p-148 , 0x1.8p-150 ) = 0x1p-149
++-inf:PASSED:fsubs(0x1p-148 , 0x1p-151 ) = 0x1p-149
++near:PASSED:fmuls(0x1p-1 , -0x1.4p-148 ) = -0x1p-149
++near:PASSED:fmuls(0x1p-1 , -0x1.cp-148 ) = -0x1p-148
++near:PASSED:fmuls(0x1p-1 , 0x1.4p-148 ) = 0x1p-149
++near:PASSED:fmuls(0x1p-1 , 0x1.cp-148 ) = 0x1p-148
++zero:PASSED:fmuls(0x1p-1 , -0x1.4p-148 ) = -0x1p-149
++zero:PASSED:fmuls(0x1p-1 , -0x1.cp-148 ) = -0x1p-149
++zero:PASSED:fmuls(0x1p-1 , 0x1.4p-148 ) = 0x1p-149
++zero:PASSED:fmuls(0x1p-1 , 0x1.cp-148 ) = 0x1p-149
+++inf:PASSED:fmuls(0x1p-1 , -0x1.4p-148 ) = -0x1p-149
+++inf:PASSED:fmuls(0x1p-1 , -0x1.cp-148 ) = -0x1p-149
+++inf:PASSED:fmuls(0x1p-1 , 0x1.4p-148 ) = 0x1p-148
+++inf:PASSED:fmuls(0x1p-1 , 0x1.cp-148 ) = 0x1p-148
++-inf:PASSED:fmuls(0x1p-1 , -0x1.4p-148 ) = -0x1p-148
++-inf:PASSED:fmuls(0x1p-1 , -0x1.cp-148 ) = -0x1p-148
++-inf:PASSED:fmuls(0x1p-1 , 0x1.4p-148 ) = 0x1p-149
++-inf:PASSED:fmuls(0x1p-1 , 0x1.cp-148 ) = 0x1p-149
++near:PASSED:fdivs(-0x1.4p-148 , 0x1p+1 ) = -0x1p-149
++near:PASSED:fdivs(-0x1.cp-148 , 0x1p+1 ) = -0x1p-148
++near:PASSED:fdivs(0x1.4p-148 , 0x1p+1 ) = 0x1p-149
++near:PASSED:fdivs(0x1.cp-148 , 0x1p+1 ) = 0x1p-148
++zero:PASSED:fdivs(-0x1.4p-148 , 0x1p+1 ) = -0x1p-149
++zero:PASSED:fdivs(-0x1.cp-148 , 0x1p+1 ) = -0x1p-149
++zero:PASSED:fdivs(0x1.4p-148 , 0x1p+1 ) = 0x1p-149
++zero:PASSED:fdivs(0x1.cp-148 , 0x1p+1 ) = 0x1p-149
+++inf:PASSED:fdivs(-0x1.4p-148 , 0x1p+1 ) = -0x1p-149
+++inf:PASSED:fdivs(-0x1.cp-148 , 0x1p+1 ) = -0x1p-149
+++inf:PASSED:fdivs(0x1.4p-148 , 0x1p+1 ) = 0x1p-148
+++inf:PASSED:fdivs(0x1.cp-148 , 0x1p+1 ) = 0x1p-148
++-inf:PASSED:fdivs(-0x1.4p-148 , 0x1p+1 ) = -0x1p-148
++-inf:PASSED:fdivs(-0x1.cp-148 , 0x1p+1 ) = -0x1p-148
++-inf:PASSED:fdivs(0x1.4p-148 , 0x1p+1 ) = 0x1p-149
++-inf:PASSED:fdivs(0x1.cp-148 , 0x1p+1 ) = 0x1p-149
++-------------------------- test rounding of float operators with guard bits --------------------------
++near:PASSED:fadds(-1.000000 , -0x1p-3 ) = -0x1.2p+0
++near:PASSED:fadds(-1.000000 , -0x1.000002p-3) = -0x1.2p+0
++near:PASSED:fadds(-1.000000 , -0x1.000004p-3) = -0x1.2p+0
++near:PASSED:fadds(-1.000000 , -0x1.000006p-3) = -0x1.2p+0
++near:PASSED:fadds(-1.000000 , -0x1.000008p-3) = -0x1.2p+0
++near:PASSED:fadds(-1.000000 , -0x1.00000ap-3) = -0x1.200002p+0
++near:PASSED:fadds(-1.000000 , -0x1.00000cp-3) = -0x1.200002p+0
++near:PASSED:fadds(-1.000000 , -0x1.00000ep-3) = -0x1.200002p+0
++near:PASSED:fadds(-1.000000 , -0x1.00001p-3) = -0x1.200002p+0
++near:PASSED:fadds(-1.000000 , -0x1.000012p-3) = -0x1.200002p+0
++near:PASSED:fadds(-1.000000 , -0x1.000014p-3) = -0x1.200002p+0
++near:PASSED:fadds(-1.000000 , -0x1.000016p-3) = -0x1.200002p+0
++near:PASSED:fadds(-1.000000 , -0x1.000018p-3) = -0x1.200004p+0
++near:PASSED:fadds(-1.000000 , -0x1.00001ap-3) = -0x1.200004p+0
++near:PASSED:fadds(-1.000000 , -0x1.00001cp-3) = -0x1.200004p+0
++near:PASSED:fadds(-1.000000 , -0x1.00001ep-3) = -0x1.200004p+0
++near:PASSED:fadds(1.000000 , 0x1p-3 ) = 0x1.2p+0
++near:PASSED:fadds(1.000000 , 0x1.000002p-3) = 0x1.2p+0
++near:PASSED:fadds(1.000000 , 0x1.000004p-3) = 0x1.2p+0
++near:PASSED:fadds(1.000000 , 0x1.000006p-3) = 0x1.2p+0
++near:PASSED:fadds(1.000000 , 0x1.000008p-3) = 0x1.2p+0
++near:PASSED:fadds(1.000000 , 0x1.00000ap-3) = 0x1.200002p+0
++near:PASSED:fadds(1.000000 , 0x1.00000cp-3) = 0x1.200002p+0
++near:PASSED:fadds(1.000000 , 0x1.00000ep-3) = 0x1.200002p+0
++near:PASSED:fadds(1.000000 , 0x1.00001p-3 ) = 0x1.200002p+0
++near:PASSED:fadds(1.000000 , 0x1.000012p-3) = 0x1.200002p+0
++near:PASSED:fadds(1.000000 , 0x1.000014p-3) = 0x1.200002p+0
++near:PASSED:fadds(1.000000 , 0x1.000016p-3) = 0x1.200002p+0
++near:PASSED:fadds(1.000000 , 0x1.000018p-3) = 0x1.200004p+0
++near:PASSED:fadds(1.000000 , 0x1.00001ap-3) = 0x1.200004p+0
++near:PASSED:fadds(1.000000 , 0x1.00001cp-3) = 0x1.200004p+0
++near:PASSED:fadds(1.000000 , 0x1.00001ep-3) = 0x1.200004p+0
++zero:PASSED:fadds(-1.000000 , -0x1p-3 ) = -0x1.2p+0
++zero:PASSED:fadds(-1.000000 , -0x1.000002p-3) = -0x1.2p+0
++zero:PASSED:fadds(-1.000000 , -0x1.000004p-3) = -0x1.2p+0
++zero:PASSED:fadds(-1.000000 , -0x1.000006p-3) = -0x1.2p+0
++zero:PASSED:fadds(-1.000000 , -0x1.000008p-3) = -0x1.2p+0
++zero:PASSED:fadds(-1.000000 , -0x1.00000ap-3) = -0x1.2p+0
++zero:PASSED:fadds(-1.000000 , -0x1.00000cp-3) = -0x1.2p+0
++zero:PASSED:fadds(-1.000000 , -0x1.00000ep-3) = -0x1.2p+0
++zero:PASSED:fadds(-1.000000 , -0x1.00001p-3) = -0x1.200002p+0
++zero:PASSED:fadds(-1.000000 , -0x1.000012p-3) = -0x1.200002p+0
++zero:PASSED:fadds(-1.000000 , -0x1.000014p-3) = -0x1.200002p+0
++zero:PASSED:fadds(-1.000000 , -0x1.000016p-3) = -0x1.200002p+0
++zero:PASSED:fadds(-1.000000 , -0x1.000018p-3) = -0x1.200002p+0
++zero:PASSED:fadds(-1.000000 , -0x1.00001ap-3) = -0x1.200002p+0
++zero:PASSED:fadds(-1.000000 , -0x1.00001cp-3) = -0x1.200002p+0
++zero:PASSED:fadds(-1.000000 , -0x1.00001ep-3) = -0x1.200002p+0
++zero:PASSED:fadds(1.000000 , 0x1p-3 ) = 0x1.2p+0
++zero:PASSED:fadds(1.000000 , 0x1.000002p-3) = 0x1.2p+0
++zero:PASSED:fadds(1.000000 , 0x1.000004p-3) = 0x1.2p+0
++zero:PASSED:fadds(1.000000 , 0x1.000006p-3) = 0x1.2p+0
++zero:PASSED:fadds(1.000000 , 0x1.000008p-3) = 0x1.2p+0
++zero:PASSED:fadds(1.000000 , 0x1.00000ap-3) = 0x1.2p+0
++zero:PASSED:fadds(1.000000 , 0x1.00000cp-3) = 0x1.2p+0
++zero:PASSED:fadds(1.000000 , 0x1.00000ep-3) = 0x1.2p+0
++zero:PASSED:fadds(1.000000 , 0x1.00001p-3 ) = 0x1.200002p+0
++zero:PASSED:fadds(1.000000 , 0x1.000012p-3) = 0x1.200002p+0
++zero:PASSED:fadds(1.000000 , 0x1.000014p-3) = 0x1.200002p+0
++zero:PASSED:fadds(1.000000 , 0x1.000016p-3) = 0x1.200002p+0
++zero:PASSED:fadds(1.000000 , 0x1.000018p-3) = 0x1.200002p+0
++zero:PASSED:fadds(1.000000 , 0x1.00001ap-3) = 0x1.200002p+0
++zero:PASSED:fadds(1.000000 , 0x1.00001cp-3) = 0x1.200002p+0
++zero:PASSED:fadds(1.000000 , 0x1.00001ep-3) = 0x1.200002p+0
+++inf:PASSED:fadds(-1.000000 , -0x1p-3 ) = -0x1.2p+0
+++inf:PASSED:fadds(-1.000000 , -0x1.000002p-3) = -0x1.2p+0
+++inf:PASSED:fadds(-1.000000 , -0x1.000004p-3) = -0x1.2p+0
+++inf:PASSED:fadds(-1.000000 , -0x1.000006p-3) = -0x1.2p+0
+++inf:PASSED:fadds(-1.000000 , -0x1.000008p-3) = -0x1.2p+0
+++inf:PASSED:fadds(-1.000000 , -0x1.00000ap-3) = -0x1.2p+0
+++inf:PASSED:fadds(-1.000000 , -0x1.00000cp-3) = -0x1.2p+0
+++inf:PASSED:fadds(-1.000000 , -0x1.00000ep-3) = -0x1.2p+0
+++inf:PASSED:fadds(-1.000000 , -0x1.00001p-3) = -0x1.200002p+0
+++inf:PASSED:fadds(-1.000000 , -0x1.000012p-3) = -0x1.200002p+0
+++inf:PASSED:fadds(-1.000000 , -0x1.000014p-3) = -0x1.200002p+0
+++inf:PASSED:fadds(-1.000000 , -0x1.000016p-3) = -0x1.200002p+0
+++inf:PASSED:fadds(-1.000000 , -0x1.000018p-3) = -0x1.200002p+0
+++inf:PASSED:fadds(-1.000000 , -0x1.00001ap-3) = -0x1.200002p+0
+++inf:PASSED:fadds(-1.000000 , -0x1.00001cp-3) = -0x1.200002p+0
+++inf:PASSED:fadds(-1.000000 , -0x1.00001ep-3) = -0x1.200002p+0
+++inf:PASSED:fadds(1.000000 , 0x1p-3 ) = 0x1.2p+0
+++inf:PASSED:fadds(1.000000 , 0x1.000002p-3) = 0x1.200002p+0
+++inf:PASSED:fadds(1.000000 , 0x1.000004p-3) = 0x1.200002p+0
+++inf:PASSED:fadds(1.000000 , 0x1.000006p-3) = 0x1.200002p+0
+++inf:PASSED:fadds(1.000000 , 0x1.000008p-3) = 0x1.200002p+0
+++inf:PASSED:fadds(1.000000 , 0x1.00000ap-3) = 0x1.200002p+0
+++inf:PASSED:fadds(1.000000 , 0x1.00000cp-3) = 0x1.200002p+0
+++inf:PASSED:fadds(1.000000 , 0x1.00000ep-3) = 0x1.200002p+0
+++inf:PASSED:fadds(1.000000 , 0x1.00001p-3 ) = 0x1.200002p+0
+++inf:PASSED:fadds(1.000000 , 0x1.000012p-3) = 0x1.200004p+0
+++inf:PASSED:fadds(1.000000 , 0x1.000014p-3) = 0x1.200004p+0
+++inf:PASSED:fadds(1.000000 , 0x1.000016p-3) = 0x1.200004p+0
+++inf:PASSED:fadds(1.000000 , 0x1.000018p-3) = 0x1.200004p+0
+++inf:PASSED:fadds(1.000000 , 0x1.00001ap-3) = 0x1.200004p+0
+++inf:PASSED:fadds(1.000000 , 0x1.00001cp-3) = 0x1.200004p+0
+++inf:PASSED:fadds(1.000000 , 0x1.00001ep-3) = 0x1.200004p+0
++-inf:PASSED:fadds(-1.000000 , -0x1p-3 ) = -0x1.2p+0
++-inf:PASSED:fadds(-1.000000 , -0x1.000002p-3) = -0x1.200002p+0
++-inf:PASSED:fadds(-1.000000 , -0x1.000004p-3) = -0x1.200002p+0
++-inf:PASSED:fadds(-1.000000 , -0x1.000006p-3) = -0x1.200002p+0
++-inf:PASSED:fadds(-1.000000 , -0x1.000008p-3) = -0x1.200002p+0
++-inf:PASSED:fadds(-1.000000 , -0x1.00000ap-3) = -0x1.200002p+0
++-inf:PASSED:fadds(-1.000000 , -0x1.00000cp-3) = -0x1.200002p+0
++-inf:PASSED:fadds(-1.000000 , -0x1.00000ep-3) = -0x1.200002p+0
++-inf:PASSED:fadds(-1.000000 , -0x1.00001p-3) = -0x1.200002p+0
++-inf:PASSED:fadds(-1.000000 , -0x1.000012p-3) = -0x1.200004p+0
++-inf:PASSED:fadds(-1.000000 , -0x1.000014p-3) = -0x1.200004p+0
++-inf:PASSED:fadds(-1.000000 , -0x1.000016p-3) = -0x1.200004p+0
++-inf:PASSED:fadds(-1.000000 , -0x1.000018p-3) = -0x1.200004p+0
++-inf:PASSED:fadds(-1.000000 , -0x1.00001ap-3) = -0x1.200004p+0
++-inf:PASSED:fadds(-1.000000 , -0x1.00001cp-3) = -0x1.200004p+0
++-inf:PASSED:fadds(-1.000000 , -0x1.00001ep-3) = -0x1.200004p+0
++-inf:PASSED:fadds(1.000000 , 0x1p-3 ) = 0x1.2p+0
++-inf:PASSED:fadds(1.000000 , 0x1.000002p-3) = 0x1.2p+0
++-inf:PASSED:fadds(1.000000 , 0x1.000004p-3) = 0x1.2p+0
++-inf:PASSED:fadds(1.000000 , 0x1.000006p-3) = 0x1.2p+0
++-inf:PASSED:fadds(1.000000 , 0x1.000008p-3) = 0x1.2p+0
++-inf:PASSED:fadds(1.000000 , 0x1.00000ap-3) = 0x1.2p+0
++-inf:PASSED:fadds(1.000000 , 0x1.00000cp-3) = 0x1.2p+0
++-inf:PASSED:fadds(1.000000 , 0x1.00000ep-3) = 0x1.2p+0
++-inf:PASSED:fadds(1.000000 , 0x1.00001p-3 ) = 0x1.200002p+0
++-inf:PASSED:fadds(1.000000 , 0x1.000012p-3) = 0x1.200002p+0
++-inf:PASSED:fadds(1.000000 , 0x1.000014p-3) = 0x1.200002p+0
++-inf:PASSED:fadds(1.000000 , 0x1.000016p-3) = 0x1.200002p+0
++-inf:PASSED:fadds(1.000000 , 0x1.000018p-3) = 0x1.200002p+0
++-inf:PASSED:fadds(1.000000 , 0x1.00001ap-3) = 0x1.200002p+0
++-inf:PASSED:fadds(1.000000 , 0x1.00001cp-3) = 0x1.200002p+0
++-inf:PASSED:fadds(1.000000 , 0x1.00001ep-3) = 0x1.200002p+0
++near:PASSED:fsubs(-1.125000 , -0x1p-3 ) = -0x1.000004p+0
++near:PASSED:fsubs(-1.125000 , -0x1.000002p-3) = -0x1.000004p+0
++near:PASSED:fsubs(-1.125000 , -0x1.000004p-3) = -0x1.000004p+0
++near:PASSED:fsubs(-1.125000 , -0x1.000006p-3) = -0x1.000004p+0
++near:PASSED:fsubs(-1.125000 , -0x1.000008p-3) = -0x1.000004p+0
++near:PASSED:fsubs(-1.125000 , -0x1.00000ap-3) = -0x1.000002p+0
++near:PASSED:fsubs(-1.125000 , -0x1.00000cp-3) = -0x1.000002p+0
++near:PASSED:fsubs(-1.125000 , -0x1.00000ep-3) = -0x1.000002p+0
++near:PASSED:fsubs(-1.125000 , -0x1.00001p-3) = -0x1.000002p+0
++near:PASSED:fsubs(-1.125000 , -0x1.000012p-3) = -0x1.000002p+0
++near:PASSED:fsubs(-1.125000 , -0x1.000014p-3) = -0x1.000002p+0
++near:PASSED:fsubs(-1.125000 , -0x1.000016p-3) = -0x1.000002p+0
++near:PASSED:fsubs(-1.125000 , -0x1.000018p-3) = -0x1p+0
++near:PASSED:fsubs(-1.125000 , -0x1.00001ap-3) = -0x1p+0
++near:PASSED:fsubs(-1.125000 , -0x1.00001cp-3) = -0x1p+0
++near:PASSED:fsubs(-1.125000 , -0x1.00001ep-3) = -0x1p+0
++near:PASSED:fsubs(1.125000 , 0x1p-3 ) = 0x1.000004p+0
++near:PASSED:fsubs(1.125000 , 0x1.000002p-3) = 0x1.000004p+0
++near:PASSED:fsubs(1.125000 , 0x1.000004p-3) = 0x1.000004p+0
++near:PASSED:fsubs(1.125000 , 0x1.000006p-3) = 0x1.000004p+0
++near:PASSED:fsubs(1.125000 , 0x1.000008p-3) = 0x1.000004p+0
++near:PASSED:fsubs(1.125000 , 0x1.00000ap-3) = 0x1.000002p+0
++near:PASSED:fsubs(1.125000 , 0x1.00000cp-3) = 0x1.000002p+0
++near:PASSED:fsubs(1.125000 , 0x1.00000ep-3) = 0x1.000002p+0
++near:PASSED:fsubs(1.125000 , 0x1.00001p-3 ) = 0x1.000002p+0
++near:PASSED:fsubs(1.125000 , 0x1.000012p-3) = 0x1.000002p+0
++near:PASSED:fsubs(1.125000 , 0x1.000014p-3) = 0x1.000002p+0
++near:PASSED:fsubs(1.125000 , 0x1.000016p-3) = 0x1.000002p+0
++near:PASSED:fsubs(1.125000 , 0x1.000018p-3) = 0x1p+0
++near:PASSED:fsubs(1.125000 , 0x1.00001ap-3) = 0x1p+0
++near:PASSED:fsubs(1.125000 , 0x1.00001cp-3) = 0x1p+0
++near:PASSED:fsubs(1.125000 , 0x1.00001ep-3) = 0x1p+0
++zero:PASSED:fsubs(-1.125000 , -0x1p-3 ) = -0x1.000004p+0
++zero:PASSED:fsubs(-1.125000 , -0x1.000002p-3) = -0x1.000002p+0
++zero:PASSED:fsubs(-1.125000 , -0x1.000004p-3) = -0x1.000002p+0
++zero:PASSED:fsubs(-1.125000 , -0x1.000006p-3) = -0x1.000002p+0
++zero:PASSED:fsubs(-1.125000 , -0x1.000008p-3) = -0x1.000002p+0
++zero:PASSED:fsubs(-1.125000 , -0x1.00000ap-3) = -0x1.000002p+0
++zero:PASSED:fsubs(-1.125000 , -0x1.00000cp-3) = -0x1.000002p+0
++zero:PASSED:fsubs(-1.125000 , -0x1.00000ep-3) = -0x1.000002p+0
++zero:PASSED:fsubs(-1.125000 , -0x1.00001p-3) = -0x1.000002p+0
++zero:PASSED:fsubs(-1.125000 , -0x1.000012p-3) = -0x1p+0
++zero:PASSED:fsubs(-1.125000 , -0x1.000014p-3) = -0x1p+0
++zero:PASSED:fsubs(-1.125000 , -0x1.000016p-3) = -0x1p+0
++zero:PASSED:fsubs(-1.125000 , -0x1.000018p-3) = -0x1p+0
++zero:PASSED:fsubs(-1.125000 , -0x1.00001ap-3) = -0x1p+0
++zero:PASSED:fsubs(-1.125000 , -0x1.00001cp-3) = -0x1p+0
++zero:PASSED:fsubs(-1.125000 , -0x1.00001ep-3) = -0x1p+0
++zero:PASSED:fsubs(1.125000 , 0x1p-3 ) = 0x1.000004p+0
++zero:PASSED:fsubs(1.125000 , 0x1.000002p-3) = 0x1.000002p+0
++zero:PASSED:fsubs(1.125000 , 0x1.000004p-3) = 0x1.000002p+0
++zero:PASSED:fsubs(1.125000 , 0x1.000006p-3) = 0x1.000002p+0
++zero:PASSED:fsubs(1.125000 , 0x1.000008p-3) = 0x1.000002p+0
++zero:PASSED:fsubs(1.125000 , 0x1.00000ap-3) = 0x1.000002p+0
++zero:PASSED:fsubs(1.125000 , 0x1.00000cp-3) = 0x1.000002p+0
++zero:PASSED:fsubs(1.125000 , 0x1.00000ep-3) = 0x1.000002p+0
++zero:PASSED:fsubs(1.125000 , 0x1.00001p-3 ) = 0x1.000002p+0
++zero:PASSED:fsubs(1.125000 , 0x1.000012p-3) = 0x1p+0
++zero:PASSED:fsubs(1.125000 , 0x1.000014p-3) = 0x1p+0
++zero:PASSED:fsubs(1.125000 , 0x1.000016p-3) = 0x1p+0
++zero:PASSED:fsubs(1.125000 , 0x1.000018p-3) = 0x1p+0
++zero:PASSED:fsubs(1.125000 , 0x1.00001ap-3) = 0x1p+0
++zero:PASSED:fsubs(1.125000 , 0x1.00001cp-3) = 0x1p+0
++zero:PASSED:fsubs(1.125000 , 0x1.00001ep-3) = 0x1p+0
+++inf:PASSED:fsubs(-1.125000 , -0x1p-3 ) = -0x1.000004p+0
+++inf:PASSED:fsubs(-1.125000 , -0x1.000002p-3) = -0x1.000002p+0
+++inf:PASSED:fsubs(-1.125000 , -0x1.000004p-3) = -0x1.000002p+0
+++inf:PASSED:fsubs(-1.125000 , -0x1.000006p-3) = -0x1.000002p+0
+++inf:PASSED:fsubs(-1.125000 , -0x1.000008p-3) = -0x1.000002p+0
+++inf:PASSED:fsubs(-1.125000 , -0x1.00000ap-3) = -0x1.000002p+0
+++inf:PASSED:fsubs(-1.125000 , -0x1.00000cp-3) = -0x1.000002p+0
+++inf:PASSED:fsubs(-1.125000 , -0x1.00000ep-3) = -0x1.000002p+0
+++inf:PASSED:fsubs(-1.125000 , -0x1.00001p-3) = -0x1.000002p+0
+++inf:PASSED:fsubs(-1.125000 , -0x1.000012p-3) = -0x1p+0
+++inf:PASSED:fsubs(-1.125000 , -0x1.000014p-3) = -0x1p+0
+++inf:PASSED:fsubs(-1.125000 , -0x1.000016p-3) = -0x1p+0
+++inf:PASSED:fsubs(-1.125000 , -0x1.000018p-3) = -0x1p+0
+++inf:PASSED:fsubs(-1.125000 , -0x1.00001ap-3) = -0x1p+0
+++inf:PASSED:fsubs(-1.125000 , -0x1.00001cp-3) = -0x1p+0
+++inf:PASSED:fsubs(-1.125000 , -0x1.00001ep-3) = -0x1p+0
+++inf:PASSED:fsubs(1.125001 , 0x1p-3 ) = 0x1.000004p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.000002p-3) = 0x1.000004p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.000004p-3) = 0x1.000004p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.000006p-3) = 0x1.000004p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.000008p-3) = 0x1.000004p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.00000ap-3) = 0x1.000004p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.00000cp-3) = 0x1.000004p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.00000ep-3) = 0x1.000004p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.00001p-3 ) = 0x1.000002p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.000012p-3) = 0x1.000002p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.000014p-3) = 0x1.000002p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.000016p-3) = 0x1.000002p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.000018p-3) = 0x1.000002p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.00001ap-3) = 0x1.000002p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.00001cp-3) = 0x1.000002p+0
+++inf:PASSED:fsubs(1.125001 , 0x1.00001ep-3) = 0x1.000002p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1p-3 ) = -0x1.000004p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.000002p-3) = -0x1.000004p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.000004p-3) = -0x1.000004p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.000006p-3) = -0x1.000004p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.000008p-3) = -0x1.000004p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.00000ap-3) = -0x1.000004p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.00000cp-3) = -0x1.000004p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.00000ep-3) = -0x1.000004p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.00001p-3) = -0x1.000002p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.000012p-3) = -0x1.000002p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.000014p-3) = -0x1.000002p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.000016p-3) = -0x1.000002p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.000018p-3) = -0x1.000002p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.00001ap-3) = -0x1.000002p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.00001cp-3) = -0x1.000002p+0
++-inf:PASSED:fsubs(-1.125001 , -0x1.00001ep-3) = -0x1.000002p+0
++-inf:PASSED:fsubs(1.125000 , 0x1p-3 ) = 0x1.000004p+0
++-inf:PASSED:fsubs(1.125000 , 0x1.000002p-3) = 0x1.000002p+0
++-inf:PASSED:fsubs(1.125000 , 0x1.000004p-3) = 0x1.000002p+0
++-inf:PASSED:fsubs(1.125000 , 0x1.000006p-3) = 0x1.000002p+0
++-inf:PASSED:fsubs(1.125000 , 0x1.000008p-3) = 0x1.000002p+0
++-inf:PASSED:fsubs(1.125000 , 0x1.00000ap-3) = 0x1.000002p+0
++-inf:PASSED:fsubs(1.125000 , 0x1.00000cp-3) = 0x1.000002p+0
++-inf:PASSED:fsubs(1.125000 , 0x1.00000ep-3) = 0x1.000002p+0
++-inf:PASSED:fsubs(1.125000 , 0x1.00001p-3 ) = 0x1.000002p+0
++-inf:PASSED:fsubs(1.125000 , 0x1.000012p-3) = 0x1p+0
++-inf:PASSED:fsubs(1.125000 , 0x1.000014p-3) = 0x1p+0
++-inf:PASSED:fsubs(1.125000 , 0x1.000016p-3) = 0x1p+0
++-inf:PASSED:fsubs(1.125000 , 0x1.000018p-3) = 0x1p+0
++-inf:PASSED:fsubs(1.125000 , 0x1.00001ap-3) = 0x1p+0
++-inf:PASSED:fsubs(1.125000 , 0x1.00001cp-3) = 0x1p+0
++-inf:PASSED:fsubs(1.125000 , 0x1.00001ep-3) = 0x1p+0
++near:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.2p+0
++near:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200002p+0
++near:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200004p+0
++near:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200006p+0
++near:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200008p+0
++near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000cp+0
++near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000ep+0
++near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001p+0
++near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200012p+0
++near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200014p+0
++near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200016p+0
++near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200018p+0
++near:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001cp+0
++near:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001ep+0
++near:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20002p+0
++near:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.200022p+0
++near:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.2p+0
++near:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200002p+0
++near:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200004p+0
++near:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200006p+0
++near:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200008p+0
++near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000cp+0
++near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000ep+0
++near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001p+0
++near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200012p+0
++near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200014p+0
++near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200016p+0
++near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200018p+0
++near:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001cp+0
++near:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001ep+0
++near:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20002p+0
++near:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.200022p+0
++zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.2p+0
++zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200002p+0
++zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200004p+0
++zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200006p+0
++zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200008p+0
++zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ap+0
++zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000cp+0
++zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ep+0
++zero:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200012p+0
++zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200014p+0
++zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200016p+0
++zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200018p+0
++zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ap+0
++zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001cp+0
++zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ep+0
++zero:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20002p+0
++zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.2p+0
++zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200002p+0
++zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200004p+0
++zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200006p+0
++zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200008p+0
++zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ap+0
++zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000cp+0
++zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ep+0
++zero:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200012p+0
++zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200014p+0
++zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200016p+0
++zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200018p+0
++zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ap+0
++zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001cp+0
++zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ep+0
++zero:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20002p+0
+++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.2p+0
+++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200002p+0
+++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200004p+0
+++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200006p+0
+++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200008p+0
+++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ap+0
+++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000cp+0
+++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.20000ep+0
+++inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.200012p+0
+++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200014p+0
+++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200016p+0
+++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200018p+0
+++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ap+0
+++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001cp+0
+++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001ep+0
+++inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20002p+0
+++inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.2p+0
+++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200004p+0
+++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200006p+0
+++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200008p+0
+++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000ap+0
+++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000cp+0
+++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20000ep+0
+++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001p+0
+++inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200012p+0
+++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.200016p+0
+++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.200018p+0
+++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001ap+0
+++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001cp+0
+++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20001ep+0
+++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.20002p+0
+++inf:PASSED:fmuls(1.000002 , 0x1.2p+0 ) = 0x1.200022p+0
++-inf:PASSED:fmuls(-1.000000 , 0x1.2p+0 ) = -0x1.2p+0
++-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200004p+0
++-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200006p+0
++-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200008p+0
++-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000ap+0
++-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000cp+0
++-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20000ep+0
++-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.20001p+0
++-inf:PASSED:fmuls(-1.000001 , 0x1.2p+0 ) = -0x1.200012p+0
++-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.200016p+0
++-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.200018p+0
++-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001ap+0
++-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001cp+0
++-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20001ep+0
++-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.20002p+0
++-inf:PASSED:fmuls(-1.000002 , 0x1.2p+0 ) = -0x1.200022p+0
++-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.2p+0
++-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200002p+0
++-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200004p+0
++-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200006p+0
++-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200008p+0
++-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ap+0
++-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000cp+0
++-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.20000ep+0
++-inf:PASSED:fmuls(1.000000 , 0x1.2p+0 ) = 0x1.200012p+0
++-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200014p+0
++-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200016p+0
++-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.200018p+0
++-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ap+0
++-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001cp+0
++-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20001ep+0
++-inf:PASSED:fmuls(1.000001 , 0x1.2p+0 ) = 0x1.20002p+0
++near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
++near:PASSED:fdivs(-100.000000 , 0x1.c8p+5 ) = -0x1.c11f7p+0
++near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
++near:PASSED:fdivs(-100.000000 , 0x1.ap+5 ) = -0x1.ec4ec4p+0
++near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
++near:PASSED:fdivs(-100.000000 , 0x1.b8p+5 ) = -0x1.d1745ep+0
++near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
++near:PASSED:fdivs(-100.000000 , 0x1.98p+5 ) = -0x1.f5f5f6p+0
++near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
++near:PASSED:fdivs(-100.000000 , 0x1.cp+5 ) = -0x1.c92492p+0
++near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
++near:PASSED:fdivs(-100.000000 , 0x1.bp+5 ) = -0x1.da12f6p+0
++near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-148
++near:PASSED:fdivs(-100.000000 , 0x1.d8p+5 ) = -0x1.b1e5f8p+0
++near:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-148
++near:PASSED:fdivs(-101.000000 , 0x1.ap+5 ) = -0x1.f13b14p+0
++near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
++near:PASSED:fdivs(100.000000 , 0x1.c8p+5 ) = 0x1.c11f7p+0
++near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
++near:PASSED:fdivs(100.000000 , 0x1.ap+5 ) = 0x1.ec4ec4p+0
++near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
++near:PASSED:fdivs(100.000000 , 0x1.b8p+5 ) = 0x1.d1745ep+0
++near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
++near:PASSED:fdivs(100.000000 , 0x1.98p+5 ) = 0x1.f5f5f6p+0
++near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
++near:PASSED:fdivs(100.000000 , 0x1.cp+5 ) = 0x1.c92492p+0
++near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
++near:PASSED:fdivs(100.000000 , 0x1.bp+5 ) = 0x1.da12f6p+0
++near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-148
++near:PASSED:fdivs(100.000000 , 0x1.d8p+5 ) = 0x1.b1e5f8p+0
++near:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-148
++near:PASSED:fdivs(101.000000 , 0x1.ap+5 ) = 0x1.f13b14p+0
++zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
++zero:PASSED:fdivs(-100.000000 , 0x1.c8p+5 ) = -0x1.c11f7p+0
++zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
++zero:PASSED:fdivs(-100.000000 , 0x1.ap+5 ) = -0x1.ec4ec4p+0
++zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
++zero:PASSED:fdivs(-100.000000 , 0x1.b8p+5 ) = -0x1.d1745cp+0
++zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
++zero:PASSED:fdivs(-100.000000 , 0x1.98p+5 ) = -0x1.f5f5f4p+0
++zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
++zero:PASSED:fdivs(-100.000000 , 0x1.cp+5 ) = -0x1.c92492p+0
++zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
++zero:PASSED:fdivs(-100.000000 , 0x1.bp+5 ) = -0x1.da12f6p+0
++zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
++zero:PASSED:fdivs(-100.000000 , 0x1.d8p+5 ) = -0x1.b1e5f6p+0
++zero:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
++zero:PASSED:fdivs(-101.000000 , 0x1.ap+5 ) = -0x1.f13b12p+0
++zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
++zero:PASSED:fdivs(100.000000 , 0x1.c8p+5 ) = 0x1.c11f7p+0
++zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
++zero:PASSED:fdivs(100.000000 , 0x1.ap+5 ) = 0x1.ec4ec4p+0
++zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
++zero:PASSED:fdivs(100.000000 , 0x1.b8p+5 ) = 0x1.d1745cp+0
++zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
++zero:PASSED:fdivs(100.000000 , 0x1.98p+5 ) = 0x1.f5f5f4p+0
++zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
++zero:PASSED:fdivs(100.000000 , 0x1.cp+5 ) = 0x1.c92492p+0
++zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
++zero:PASSED:fdivs(100.000000 , 0x1.bp+5 ) = 0x1.da12f6p+0
++zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
++zero:PASSED:fdivs(100.000000 , 0x1.d8p+5 ) = 0x1.b1e5f6p+0
++zero:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
++zero:PASSED:fdivs(101.000000 , 0x1.ap+5 ) = 0x1.f13b12p+0
+++inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
+++inf:PASSED:fdivs(-100.000000 , 0x1.c8p+5 ) = -0x1.c11f7p+0
+++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x0p+0
+++inf:PASSED:fdivs(-100.000000 , 0x1.ap+5 ) = -0x1.ec4ec4p+0
+++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x0p+0
+++inf:PASSED:fdivs(-100.000000 , 0x1.b8p+5 ) = -0x1.d1745cp+0
+++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x0p+0
+++inf:PASSED:fdivs(-100.000000 , 0x1.98p+5 ) = -0x1.f5f5f4p+0
+++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x1p-149
+++inf:PASSED:fdivs(-100.000000 , 0x1.cp+5 ) = -0x1.c92492p+0
+++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x1p-149
+++inf:PASSED:fdivs(-100.000000 , 0x1.bp+5 ) = -0x1.da12f6p+0
+++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x1p-149
+++inf:PASSED:fdivs(-100.000000 , 0x1.d8p+5 ) = -0x1.b1e5f6p+0
+++inf:PASSED:fdivs(0.000001 , -0x1p+3 ) = -0x1p-149
+++inf:PASSED:fdivs(-101.000000 , 0x1.ap+5 ) = -0x1.f13b12p+0
+++inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
+++inf:PASSED:fdivs(100.000000 , 0x1.c8p+5 ) = 0x1.c11f72p+0
+++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-149
+++inf:PASSED:fdivs(100.000000 , 0x1.ap+5 ) = 0x1.ec4ec6p+0
+++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-149
+++inf:PASSED:fdivs(100.000000 , 0x1.b8p+5 ) = 0x1.d1745ep+0
+++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-149
+++inf:PASSED:fdivs(100.000000 , 0x1.98p+5 ) = 0x1.f5f5f6p+0
+++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-149
+++inf:PASSED:fdivs(100.000000 , 0x1.cp+5 ) = 0x1.c92494p+0
+++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-148
+++inf:PASSED:fdivs(100.000000 , 0x1.bp+5 ) = 0x1.da12f8p+0
+++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-148
+++inf:PASSED:fdivs(100.000000 , 0x1.d8p+5 ) = 0x1.b1e5f8p+0
+++inf:PASSED:fdivs(0.000001 , 0x1p+3 ) = 0x1p-148
+++inf:PASSED:fdivs(101.000000 , 0x1.ap+5 ) = 0x1.f13b14p+0
++-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x0p+0
++-inf:PASSED:fdivs(-100.000000 , 0x1.c8p+5 ) = -0x1.c11f72p+0
++-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
++-inf:PASSED:fdivs(-100.000000 , 0x1.ap+5 ) = -0x1.ec4ec6p+0
++-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
++-inf:PASSED:fdivs(-100.000000 , 0x1.b8p+5 ) = -0x1.d1745ep+0
++-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
++-inf:PASSED:fdivs(-100.000000 , 0x1.98p+5 ) = -0x1.f5f5f6p+0
++-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-149
++-inf:PASSED:fdivs(-100.000000 , 0x1.cp+5 ) = -0x1.c92494p+0
++-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-148
++-inf:PASSED:fdivs(-100.000000 , 0x1.bp+5 ) = -0x1.da12f8p+0
++-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-148
++-inf:PASSED:fdivs(-100.000000 , 0x1.d8p+5 ) = -0x1.b1e5f8p+0
++-inf:PASSED:fdivs(0.000000 , -0x1p+3 ) = -0x1p-148
++-inf:PASSED:fdivs(-101.000000 , 0x1.ap+5 ) = -0x1.f13b14p+0
++-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
++-inf:PASSED:fdivs(100.000000 , 0x1.c8p+5 ) = 0x1.c11f7p+0
++-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
++-inf:PASSED:fdivs(100.000000 , 0x1.ap+5 ) = 0x1.ec4ec4p+0
++-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
++-inf:PASSED:fdivs(100.000000 , 0x1.b8p+5 ) = 0x1.d1745cp+0
++-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x0p+0
++-inf:PASSED:fdivs(100.000000 , 0x1.98p+5 ) = 0x1.f5f5f4p+0
++-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
++-inf:PASSED:fdivs(100.000000 , 0x1.cp+5 ) = 0x1.c92492p+0
++-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
++-inf:PASSED:fdivs(100.000000 , 0x1.bp+5 ) = 0x1.da12f6p+0
++-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
++-inf:PASSED:fdivs(100.000000 , 0x1.d8p+5 ) = 0x1.b1e5f6p+0
++-inf:PASSED:fdivs(0.000000 , 0x1p+3 ) = 0x1p-149
++-inf:PASSED:fdivs(101.000000 , 0x1.ap+5 ) = 0x1.f13b12p+0
++near:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0
++near:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
++near:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
++near:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00008p+0
++near:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
++near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
++near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
++near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
++near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
++near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
++near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
++near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ap+0
++near:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
++near:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
++near:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
++near:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
++near:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0
++near:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
++near:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
++near:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00008p+0
++near:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
++near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
++near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
++near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
++near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
++near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
++near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
++near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ap+0
++near:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
++near:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
++near:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
++near:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
++zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0
++zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0
++zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
++zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
++zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
++zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
++zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
++zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
++zero:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
++zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
++zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
++zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
++zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
++zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
++zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
++zero:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
++zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0
++zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0
++zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
++zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
++zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
++zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
++zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
++zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
++zero:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
++zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
++zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
++zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
++zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
++zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
++zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
++zero:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
+++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0
+++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0
+++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
+++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
+++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
+++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
+++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
+++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
+++inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
+++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
+++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
+++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
+++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
+++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
+++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
+++inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
+++inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0
+++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
+++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
+++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00008p+0
+++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
+++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
+++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
+++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
+++inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
+++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
+++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
+++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ap+0
+++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
+++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
+++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
+++inf:PASSED:fmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00024p+0
++-inf:PASSED:fmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0
++-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
++-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
++-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00008p+0
++-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
++-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
++-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
++-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
++-inf:PASSED:fmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
++-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
++-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
++-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ap+0
++-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
++-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
++-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
++-inf:PASSED:fmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00024p+0
++-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0
++-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0
++-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
++-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
++-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
++-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
++-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
++-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
++-inf:PASSED:fmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
++-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
++-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
++-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
++-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
++-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
++-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
++-inf:PASSED:fmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
++near:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0
++near:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
++near:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
++near:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00008p+0
++near:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
++near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
++near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
++near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
++near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
++near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
++near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
++near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ap+0
++near:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
++near:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
++near:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
++near:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
++near:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0
++near:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
++near:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
++near:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00008p+0
++near:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
++near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
++near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
++near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
++near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
++near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
++near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
++near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ap+0
++near:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
++near:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
++near:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
++near:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
++zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0
++zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0
++zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
++zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
++zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
++zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
++zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
++zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
++zero:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
++zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
++zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
++zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
++zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
++zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
++zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
++zero:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
++zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0
++zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0
++zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
++zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
++zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
++zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
++zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
++zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
++zero:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
++zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
++zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
++zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
++zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
++zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
++zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
++zero:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
+++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0
+++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0
+++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
+++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
+++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
+++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
+++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
+++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
+++inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
+++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
+++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
+++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
+++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
+++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
+++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
+++inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
+++inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0
+++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
+++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
+++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00008p+0
+++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
+++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
+++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
+++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
+++inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
+++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
+++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
+++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ap+0
+++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
+++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
+++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
+++inf:PASSED:fmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00024p+0
++-inf:PASSED:fmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0
++-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
++-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
++-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00008p+0
++-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
++-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
++-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
++-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
++-inf:PASSED:fmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
++-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
++-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
++-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ap+0
++-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
++-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
++-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
++-inf:PASSED:fmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00024p+0
++-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0
++-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0
++-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
++-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
++-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
++-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
++-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
++-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
++-inf:PASSED:fmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
++-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
++-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
++-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
++-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
++-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
++-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
++-inf:PASSED:fmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
++near:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0
++near:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
++near:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
++near:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00008p+0
++near:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
++near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
++near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
++near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
++near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
++near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
++near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
++near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ap+0
++near:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
++near:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
++near:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
++near:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
++near:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0
++near:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
++near:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
++near:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00008p+0
++near:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
++near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
++near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
++near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
++near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
++near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
++near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
++near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ap+0
++near:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
++near:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
++near:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
++near:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
++zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0
++zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0
++zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
++zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
++zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
++zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
++zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
++zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
++zero:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
++zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
++zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
++zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
++zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
++zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
++zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
++zero:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
++zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0
++zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0
++zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
++zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
++zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
++zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
++zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
++zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
++zero:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
++zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
++zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
++zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
++zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
++zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
++zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
++zero:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
+++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.ap+0
+++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0
+++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
+++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
+++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
+++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000cp+0
+++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
+++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
+++inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
+++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
+++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
+++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
+++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
+++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ep+0
+++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
+++inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
+++inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0
+++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
+++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
+++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00008p+0
+++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
+++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
+++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
+++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
+++inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
+++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
+++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
+++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ap+0
+++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
+++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
+++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
+++inf:PASSED:fnmadds(1.000002 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00024p+0
++-inf:PASSED:fnmadds(-1.000000 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00002p+0
++-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00004p+0
++-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00006p+0
++-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00008p+0
++-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ap+0
++-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0000ep+0
++-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001p+0
++-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00012p+0
++-inf:PASSED:fnmadds(-1.000001 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00014p+0
++-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00016p+0
++-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00018p+0
++-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001ap+0
++-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0001cp+0
++-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a0002p+0
++-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00022p+0
++-inf:PASSED:fnmadds(-1.000002 , 0x1.2p+0 , -0x1.000002p-1) = 0x1.a00024p+0
++-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.ap+0
++-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00002p+0
++-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00004p+0
++-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00006p+0
++-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ap+0
++-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000cp+0
++-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0000ep+0
++-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001p+0
++-inf:PASSED:fnmadds(1.000000 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00012p+0
++-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00014p+0
++-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00016p+0
++-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00018p+0
++-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001cp+0
++-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0001ep+0
++-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a0002p+0
++-inf:PASSED:fnmadds(1.000001 , 0x1.2p+0 , 0x1.000002p-1) = -0x1.a00022p+0
++near:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0
++near:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
++near:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
++near:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00008p+0
++near:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
++near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
++near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
++near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
++near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
++near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
++near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
++near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ap+0
++near:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
++near:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
++near:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
++near:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
++near:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0
++near:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
++near:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
++near:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00008p+0
++near:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
++near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
++near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
++near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
++near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
++near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
++near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
++near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ap+0
++near:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
++near:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
++near:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
++near:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
++zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0
++zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0
++zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
++zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
++zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
++zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
++zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
++zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
++zero:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
++zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
++zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
++zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
++zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
++zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
++zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
++zero:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
++zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0
++zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0
++zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
++zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
++zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
++zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
++zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
++zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
++zero:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
++zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
++zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
++zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
++zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
++zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
++zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
++zero:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
+++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.ap+0
+++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0
+++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
+++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
+++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
+++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000cp+0
+++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
+++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
+++inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
+++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
+++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
+++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
+++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
+++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ep+0
+++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
+++inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
+++inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0
+++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
+++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
+++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00008p+0
+++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
+++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
+++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
+++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
+++inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
+++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
+++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
+++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ap+0
+++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
+++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
+++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
+++inf:PASSED:fnmsubs(1.000002 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00024p+0
++-inf:PASSED:fnmsubs(-1.000000 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00002p+0
++-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00004p+0
++-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00006p+0
++-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00008p+0
++-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ap+0
++-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0000ep+0
++-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001p+0
++-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00012p+0
++-inf:PASSED:fnmsubs(-1.000001 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00014p+0
++-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00016p+0
++-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00018p+0
++-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001ap+0
++-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0001cp+0
++-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a0002p+0
++-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00022p+0
++-inf:PASSED:fnmsubs(-1.000002 , 0x1.2p+0 , 0x1.000002p-1) = 0x1.a00024p+0
++-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.ap+0
++-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00002p+0
++-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00004p+0
++-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00006p+0
++-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ap+0
++-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000cp+0
++-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0000ep+0
++-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001p+0
++-inf:PASSED:fnmsubs(1.000000 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00012p+0
++-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00014p+0
++-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00016p+0
++-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00018p+0
++-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001cp+0
++-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0001ep+0
++-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a0002p+0
++-inf:PASSED:fnmsubs(1.000001 , 0x1.2p+0 , -0x1.000002p-1) = -0x1.a00022p+0
++-------------------------- test rounding of double operators with guard bits --------------------------
++near:PASSED:fadd(-0x1p+0 , -0x1p-3 ) = -0x1.2p+0
++near:PASSED:fadd(-0x1p+0 , -0x1.0000000000001p-3) = -0x1.2p+0
++near:PASSED:fadd(-0x1p+0 , -0x1.0000000000002p-3) = -0x1.2p+0
++near:PASSED:fadd(-0x1p+0 , -0x1.0000000000003p-3) = -0x1.2p+0
++near:PASSED:fadd(-0x1p+0 , -0x1.0000000000004p-3) = -0x1.2p+0
++near:PASSED:fadd(-0x1p+0 , -0x1.0000000000005p-3) = -0x1.2000000000001p+0
++near:PASSED:fadd(-0x1p+0 , -0x1.0000000000006p-3) = -0x1.2000000000001p+0
++near:PASSED:fadd(-0x1p+0 , -0x1.0000000000007p-3) = -0x1.2000000000001p+0
++near:PASSED:fadd(-0x1p+0 , -0x1.0000000000008p-3) = -0x1.2000000000001p+0
++near:PASSED:fadd(-0x1p+0 , -0x1.0000000000009p-3) = -0x1.2000000000001p+0
++near:PASSED:fadd(-0x1p+0 , -0x1.000000000000ap-3) = -0x1.2000000000001p+0
++near:PASSED:fadd(-0x1p+0 , -0x1.000000000000bp-3) = -0x1.2000000000001p+0
++near:PASSED:fadd(-0x1p+0 , -0x1.000000000000cp-3) = -0x1.2000000000002p+0
++near:PASSED:fadd(-0x1p+0 , -0x1.000000000000dp-3) = -0x1.2000000000002p+0
++near:PASSED:fadd(-0x1p+0 , -0x1.000000000000ep-3) = -0x1.2000000000002p+0
++near:PASSED:fadd(-0x1p+0 , -0x1.000000000000fp-3) = -0x1.2000000000002p+0
++near:PASSED:fadd(0x1p+0 , 0x1p-3 ) = 0x1.2p+0
++near:PASSED:fadd(0x1p+0 , 0x1.0000000000001p-3) = 0x1.2p+0
++near:PASSED:fadd(0x1p+0 , 0x1.0000000000002p-3) = 0x1.2p+0
++near:PASSED:fadd(0x1p+0 , 0x1.0000000000003p-3) = 0x1.2p+0
++near:PASSED:fadd(0x1p+0 , 0x1.0000000000004p-3) = 0x1.2p+0
++near:PASSED:fadd(0x1p+0 , 0x1.0000000000005p-3) = 0x1.2000000000001p+0
++near:PASSED:fadd(0x1p+0 , 0x1.0000000000006p-3) = 0x1.2000000000001p+0
++near:PASSED:fadd(0x1p+0 , 0x1.0000000000007p-3) = 0x1.2000000000001p+0
++near:PASSED:fadd(0x1p+0 , 0x1.0000000000008p-3) = 0x1.2000000000001p+0
++near:PASSED:fadd(0x1p+0 , 0x1.0000000000009p-3) = 0x1.2000000000001p+0
++near:PASSED:fadd(0x1p+0 , 0x1.000000000000ap-3) = 0x1.2000000000001p+0
++near:PASSED:fadd(0x1p+0 , 0x1.000000000000bp-3) = 0x1.2000000000001p+0
++near:PASSED:fadd(0x1p+0 , 0x1.000000000000cp-3) = 0x1.2000000000002p+0
++near:PASSED:fadd(0x1p+0 , 0x1.000000000000dp-3) = 0x1.2000000000002p+0
++near:PASSED:fadd(0x1p+0 , 0x1.000000000000ep-3) = 0x1.2000000000002p+0
++near:PASSED:fadd(0x1p+0 , 0x1.000000000000fp-3) = 0x1.2000000000002p+0
++zero:PASSED:fadd(-0x1p+0 , -0x1p-3 ) = -0x1.2p+0
++zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000001p-3) = -0x1.2p+0
++zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000002p-3) = -0x1.2p+0
++zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000003p-3) = -0x1.2p+0
++zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000004p-3) = -0x1.2p+0
++zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000005p-3) = -0x1.2p+0
++zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000006p-3) = -0x1.2p+0
++zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000007p-3) = -0x1.2p+0
++zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000008p-3) = -0x1.2000000000001p+0
++zero:PASSED:fadd(-0x1p+0 , -0x1.0000000000009p-3) = -0x1.2000000000001p+0
++zero:PASSED:fadd(-0x1p+0 , -0x1.000000000000ap-3) = -0x1.2000000000001p+0
++zero:PASSED:fadd(-0x1p+0 , -0x1.000000000000bp-3) = -0x1.2000000000001p+0
++zero:PASSED:fadd(-0x1p+0 , -0x1.000000000000cp-3) = -0x1.2000000000001p+0
++zero:PASSED:fadd(-0x1p+0 , -0x1.000000000000dp-3) = -0x1.2000000000001p+0
++zero:PASSED:fadd(-0x1p+0 , -0x1.000000000000ep-3) = -0x1.2000000000001p+0
++zero:PASSED:fadd(-0x1p+0 , -0x1.000000000000fp-3) = -0x1.2000000000001p+0
++zero:PASSED:fadd(0x1p+0 , 0x1p-3 ) = 0x1.2p+0
++zero:PASSED:fadd(0x1p+0 , 0x1.0000000000001p-3) = 0x1.2p+0
++zero:PASSED:fadd(0x1p+0 , 0x1.0000000000002p-3) = 0x1.2p+0
++zero:PASSED:fadd(0x1p+0 , 0x1.0000000000003p-3) = 0x1.2p+0
++zero:PASSED:fadd(0x1p+0 , 0x1.0000000000004p-3) = 0x1.2p+0
++zero:PASSED:fadd(0x1p+0 , 0x1.0000000000005p-3) = 0x1.2p+0
++zero:PASSED:fadd(0x1p+0 , 0x1.0000000000006p-3) = 0x1.2p+0
++zero:PASSED:fadd(0x1p+0 , 0x1.0000000000007p-3) = 0x1.2p+0
++zero:PASSED:fadd(0x1p+0 , 0x1.0000000000008p-3) = 0x1.2000000000001p+0
++zero:PASSED:fadd(0x1p+0 , 0x1.0000000000009p-3) = 0x1.2000000000001p+0
++zero:PASSED:fadd(0x1p+0 , 0x1.000000000000ap-3) = 0x1.2000000000001p+0
++zero:PASSED:fadd(0x1p+0 , 0x1.000000000000bp-3) = 0x1.2000000000001p+0
++zero:PASSED:fadd(0x1p+0 , 0x1.000000000000cp-3) = 0x1.2000000000001p+0
++zero:PASSED:fadd(0x1p+0 , 0x1.000000000000dp-3) = 0x1.2000000000001p+0
++zero:PASSED:fadd(0x1p+0 , 0x1.000000000000ep-3) = 0x1.2000000000001p+0
++zero:PASSED:fadd(0x1p+0 , 0x1.000000000000fp-3) = 0x1.2000000000001p+0
+++inf:PASSED:fadd(-0x1p+0 , -0x1p-3 ) = -0x1.2p+0
+++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000001p-3) = -0x1.2p+0
+++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000002p-3) = -0x1.2p+0
+++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000003p-3) = -0x1.2p+0
+++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000004p-3) = -0x1.2p+0
+++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000005p-3) = -0x1.2p+0
+++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000006p-3) = -0x1.2p+0
+++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000007p-3) = -0x1.2p+0
+++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000008p-3) = -0x1.2000000000001p+0
+++inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000009p-3) = -0x1.2000000000001p+0
+++inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000ap-3) = -0x1.2000000000001p+0
+++inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000bp-3) = -0x1.2000000000001p+0
+++inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000cp-3) = -0x1.2000000000001p+0
+++inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000dp-3) = -0x1.2000000000001p+0
+++inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000ep-3) = -0x1.2000000000001p+0
+++inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000fp-3) = -0x1.2000000000001p+0
+++inf:PASSED:fadd(0x1p+0 , 0x1p-3 ) = 0x1.2p+0
+++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000001p-3) = 0x1.2000000000001p+0
+++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000002p-3) = 0x1.2000000000001p+0
+++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000003p-3) = 0x1.2000000000001p+0
+++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000004p-3) = 0x1.2000000000001p+0
+++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000005p-3) = 0x1.2000000000001p+0
+++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000006p-3) = 0x1.2000000000001p+0
+++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000007p-3) = 0x1.2000000000001p+0
+++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000008p-3) = 0x1.2000000000001p+0
+++inf:PASSED:fadd(0x1p+0 , 0x1.0000000000009p-3) = 0x1.2000000000002p+0
+++inf:PASSED:fadd(0x1p+0 , 0x1.000000000000ap-3) = 0x1.2000000000002p+0
+++inf:PASSED:fadd(0x1p+0 , 0x1.000000000000bp-3) = 0x1.2000000000002p+0
+++inf:PASSED:fadd(0x1p+0 , 0x1.000000000000cp-3) = 0x1.2000000000002p+0
+++inf:PASSED:fadd(0x1p+0 , 0x1.000000000000dp-3) = 0x1.2000000000002p+0
+++inf:PASSED:fadd(0x1p+0 , 0x1.000000000000ep-3) = 0x1.2000000000002p+0
+++inf:PASSED:fadd(0x1p+0 , 0x1.000000000000fp-3) = 0x1.2000000000002p+0
++-inf:PASSED:fadd(-0x1p+0 , -0x1p-3 ) = -0x1.2p+0
++-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000001p-3) = -0x1.2000000000001p+0
++-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000002p-3) = -0x1.2000000000001p+0
++-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000003p-3) = -0x1.2000000000001p+0
++-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000004p-3) = -0x1.2000000000001p+0
++-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000005p-3) = -0x1.2000000000001p+0
++-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000006p-3) = -0x1.2000000000001p+0
++-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000007p-3) = -0x1.2000000000001p+0
++-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000008p-3) = -0x1.2000000000001p+0
++-inf:PASSED:fadd(-0x1p+0 , -0x1.0000000000009p-3) = -0x1.2000000000002p+0
++-inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000ap-3) = -0x1.2000000000002p+0
++-inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000bp-3) = -0x1.2000000000002p+0
++-inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000cp-3) = -0x1.2000000000002p+0
++-inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000dp-3) = -0x1.2000000000002p+0
++-inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000ep-3) = -0x1.2000000000002p+0
++-inf:PASSED:fadd(-0x1p+0 , -0x1.000000000000fp-3) = -0x1.2000000000002p+0
++-inf:PASSED:fadd(0x1p+0 , 0x1p-3 ) = 0x1.2p+0
++-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000001p-3) = 0x1.2p+0
++-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000002p-3) = 0x1.2p+0
++-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000003p-3) = 0x1.2p+0
++-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000004p-3) = 0x1.2p+0
++-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000005p-3) = 0x1.2p+0
++-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000006p-3) = 0x1.2p+0
++-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000007p-3) = 0x1.2p+0
++-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000008p-3) = 0x1.2000000000001p+0
++-inf:PASSED:fadd(0x1p+0 , 0x1.0000000000009p-3) = 0x1.2000000000001p+0
++-inf:PASSED:fadd(0x1p+0 , 0x1.000000000000ap-3) = 0x1.2000000000001p+0
++-inf:PASSED:fadd(0x1p+0 , 0x1.000000000000bp-3) = 0x1.2000000000001p+0
++-inf:PASSED:fadd(0x1p+0 , 0x1.000000000000cp-3) = 0x1.2000000000001p+0
++-inf:PASSED:fadd(0x1p+0 , 0x1.000000000000dp-3) = 0x1.2000000000001p+0
++-inf:PASSED:fadd(0x1p+0 , 0x1.000000000000ep-3) = 0x1.2000000000001p+0
++-inf:PASSED:fadd(0x1p+0 , 0x1.000000000000fp-3) = 0x1.2000000000001p+0
++near:PASSED:fsub(-0x1.2000000000002p+0, -0x1p-3 ) = -0x1.0000000000002p+0
++near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000001p-3) = -0x1.0000000000002p+0
++near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000002p-3) = -0x1.0000000000002p+0
++near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000003p-3) = -0x1.0000000000002p+0
++near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000004p-3) = -0x1.0000000000002p+0
++near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000005p-3) = -0x1.0000000000001p+0
++near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000006p-3) = -0x1.0000000000001p+0
++near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000007p-3) = -0x1.0000000000001p+0
++near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000008p-3) = -0x1.0000000000001p+0
++near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000009p-3) = -0x1.0000000000001p+0
++near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ap-3) = -0x1.0000000000001p+0
++near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000bp-3) = -0x1.0000000000001p+0
++near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000cp-3) = -0x1p+0
++near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000dp-3) = -0x1p+0
++near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ep-3) = -0x1p+0
++near:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000fp-3) = -0x1p+0
++near:PASSED:fsub(0x1.2000000000002p+0, 0x1p-3 ) = 0x1.0000000000002p+0
++near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000001p-3) = 0x1.0000000000002p+0
++near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000002p-3) = 0x1.0000000000002p+0
++near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000003p-3) = 0x1.0000000000002p+0
++near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000004p-3) = 0x1.0000000000002p+0
++near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000005p-3) = 0x1.0000000000001p+0
++near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000006p-3) = 0x1.0000000000001p+0
++near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000007p-3) = 0x1.0000000000001p+0
++near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000008p-3) = 0x1.0000000000001p+0
++near:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000009p-3) = 0x1.0000000000001p+0
++near:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ap-3) = 0x1.0000000000001p+0
++near:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000bp-3) = 0x1.0000000000001p+0
++near:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000cp-3) = 0x1p+0
++near:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000dp-3) = 0x1p+0
++near:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ep-3) = 0x1p+0
++near:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000fp-3) = 0x1p+0
++zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1p-3 ) = -0x1.0000000000002p+0
++zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000001p-3) = -0x1.0000000000001p+0
++zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000002p-3) = -0x1.0000000000001p+0
++zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000003p-3) = -0x1.0000000000001p+0
++zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000004p-3) = -0x1.0000000000001p+0
++zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000005p-3) = -0x1.0000000000001p+0
++zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000006p-3) = -0x1.0000000000001p+0
++zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000007p-3) = -0x1.0000000000001p+0
++zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000008p-3) = -0x1.0000000000001p+0
++zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000009p-3) = -0x1p+0
++zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ap-3) = -0x1p+0
++zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000bp-3) = -0x1p+0
++zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000cp-3) = -0x1p+0
++zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000dp-3) = -0x1p+0
++zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ep-3) = -0x1p+0
++zero:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000fp-3) = -0x1p+0
++zero:PASSED:fsub(0x1.2000000000002p+0, 0x1p-3 ) = 0x1.0000000000002p+0
++zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000001p-3) = 0x1.0000000000001p+0
++zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000002p-3) = 0x1.0000000000001p+0
++zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000003p-3) = 0x1.0000000000001p+0
++zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000004p-3) = 0x1.0000000000001p+0
++zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000005p-3) = 0x1.0000000000001p+0
++zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000006p-3) = 0x1.0000000000001p+0
++zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000007p-3) = 0x1.0000000000001p+0
++zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000008p-3) = 0x1.0000000000001p+0
++zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000009p-3) = 0x1p+0
++zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ap-3) = 0x1p+0
++zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000bp-3) = 0x1p+0
++zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000cp-3) = 0x1p+0
++zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000dp-3) = 0x1p+0
++zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ep-3) = 0x1p+0
++zero:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000fp-3) = 0x1p+0
+++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1p-3 ) = -0x1.0000000000002p+0
+++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000001p-3) = -0x1.0000000000001p+0
+++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000002p-3) = -0x1.0000000000001p+0
+++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000003p-3) = -0x1.0000000000001p+0
+++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000004p-3) = -0x1.0000000000001p+0
+++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000005p-3) = -0x1.0000000000001p+0
+++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000006p-3) = -0x1.0000000000001p+0
+++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000007p-3) = -0x1.0000000000001p+0
+++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000008p-3) = -0x1.0000000000001p+0
+++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000009p-3) = -0x1p+0
+++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ap-3) = -0x1p+0
+++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000bp-3) = -0x1p+0
+++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000cp-3) = -0x1p+0
+++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000dp-3) = -0x1p+0
+++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ep-3) = -0x1p+0
+++inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000fp-3) = -0x1p+0
+++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1p-3 ) = 0x1.0000000000002p+0
+++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000001p-3) = 0x1.0000000000002p+0
+++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000002p-3) = 0x1.0000000000002p+0
+++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000003p-3) = 0x1.0000000000002p+0
+++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000004p-3) = 0x1.0000000000002p+0
+++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000005p-3) = 0x1.0000000000002p+0
+++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000006p-3) = 0x1.0000000000002p+0
+++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000007p-3) = 0x1.0000000000002p+0
+++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000008p-3) = 0x1.0000000000001p+0
+++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000009p-3) = 0x1.0000000000001p+0
+++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ap-3) = 0x1.0000000000001p+0
+++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000bp-3) = 0x1.0000000000001p+0
+++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000cp-3) = 0x1.0000000000001p+0
+++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000dp-3) = 0x1.0000000000001p+0
+++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ep-3) = 0x1.0000000000001p+0
+++inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000fp-3) = 0x1.0000000000001p+0
++-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1p-3 ) = -0x1.0000000000002p+0
++-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000001p-3) = -0x1.0000000000002p+0
++-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000002p-3) = -0x1.0000000000002p+0
++-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000003p-3) = -0x1.0000000000002p+0
++-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000004p-3) = -0x1.0000000000002p+0
++-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000005p-3) = -0x1.0000000000002p+0
++-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000006p-3) = -0x1.0000000000002p+0
++-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000007p-3) = -0x1.0000000000002p+0
++-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000008p-3) = -0x1.0000000000001p+0
++-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.0000000000009p-3) = -0x1.0000000000001p+0
++-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ap-3) = -0x1.0000000000001p+0
++-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000bp-3) = -0x1.0000000000001p+0
++-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000cp-3) = -0x1.0000000000001p+0
++-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000dp-3) = -0x1.0000000000001p+0
++-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000ep-3) = -0x1.0000000000001p+0
++-inf:PASSED:fsub(-0x1.2000000000002p+0, -0x1.000000000000fp-3) = -0x1.0000000000001p+0
++-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1p-3 ) = 0x1.0000000000002p+0
++-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000001p-3) = 0x1.0000000000001p+0
++-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000002p-3) = 0x1.0000000000001p+0
++-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000003p-3) = 0x1.0000000000001p+0
++-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000004p-3) = 0x1.0000000000001p+0
++-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000005p-3) = 0x1.0000000000001p+0
++-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000006p-3) = 0x1.0000000000001p+0
++-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000007p-3) = 0x1.0000000000001p+0
++-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000008p-3) = 0x1.0000000000001p+0
++-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.0000000000009p-3) = 0x1p+0
++-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ap-3) = 0x1p+0
++-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000bp-3) = 0x1p+0
++-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000cp-3) = 0x1p+0
++-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000dp-3) = 0x1p+0
++-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000ep-3) = 0x1p+0
++-inf:PASSED:fsub(0x1.2000000000002p+0, 0x1.000000000000fp-3) = 0x1p+0
++near:PASSED:fmul(-0x1p+0 , 0x1.2p+0 ) = -0x1.2p+0
++near:PASSED:fmul(-0x1.0000000000001p+0, 0x1.2p+0 ) = -0x1.2000000000001p+0
++near:PASSED:fmul(-0x1.0000000000002p+0, 0x1.2p+0 ) = -0x1.2000000000002p+0
++near:PASSED:fmul(-0x1.0000000000003p+0, 0x1.2p+0 ) = -0x1.2000000000003p+0
++near:PASSED:fmul(-0x1.0000000000004p+0, 0x1.2p+0 ) = -0x1.2000000000004p+0
++near:PASSED:fmul(-0x1.0000000000005p+0, 0x1.2p+0 ) = -0x1.2000000000006p+0
++near:PASSED:fmul(-0x1.0000000000006p+0, 0x1.2p+0 ) = -0x1.2000000000007p+0
++near:PASSED:fmul(-0x1.0000000000007p+0, 0x1.2p+0 ) = -0x1.2000000000008p+0
++near:PASSED:fmul(-0x1.0000000000008p+0, 0x1.2p+0 ) = -0x1.2000000000009p+0
++near:PASSED:fmul(-0x1.0000000000009p+0, 0x1.2p+0 ) = -0x1.200000000000ap+0
++near:PASSED:fmul(-0x1.000000000000ap+0, 0x1.2p+0 ) = -0x1.200000000000bp+0
++near:PASSED:fmul(-0x1.000000000000bp+0, 0x1.2p+0 ) = -0x1.200000000000cp+0
++near:PASSED:fmul(-0x1.000000000000cp+0, 0x1.2p+0 ) = -0x1.200000000000ep+0
++near:PASSED:fmul(-0x1.000000000000dp+0, 0x1.2p+0 ) = -0x1.200000000000fp+0
++near:PASSED:fmul(-0x1.000000000000ep+0, 0x1.2p+0 ) = -0x1.200000000001p+0
++near:PASSED:fmul(-0x1.000000000000fp+0, 0x1.2p+0 ) = -0x1.2000000000011p+0
++near:PASSED:fmul(0x1p+0 , 0x1.2p+0 ) = 0x1.2p+0
++near:PASSED:fmul(0x1.0000000000001p+0, 0x1.2p+0 ) = 0x1.2000000000001p+0
++near:PASSED:fmul(0x1.0000000000002p+0, 0x1.2p+0 ) = 0x1.2000000000002p+0
++near:PASSED:fmul(0x1.0000000000003p+0, 0x1.2p+0 ) = 0x1.2000000000003p+0
++near:PASSED:fmul(0x1.0000000000004p+0, 0x1.2p+0 ) = 0x1.2000000000004p+0
++near:PASSED:fmul(0x1.0000000000005p+0, 0x1.2p+0 ) = 0x1.2000000000006p+0
++near:PASSED:fmul(0x1.0000000000006p+0, 0x1.2p+0 ) = 0x1.2000000000007p+0
++near:PASSED:fmul(0x1.0000000000007p+0, 0x1.2p+0 ) = 0x1.2000000000008p+0
++near:PASSED:fmul(0x1.0000000000008p+0, 0x1.2p+0 ) = 0x1.2000000000009p+0
++near:PASSED:fmul(0x1.0000000000009p+0, 0x1.2p+0 ) = 0x1.200000000000ap+0
++near:PASSED:fmul(0x1.000000000000ap+0, 0x1.2p+0 ) = 0x1.200000000000bp+0
++near:PASSED:fmul(0x1.000000000000bp+0, 0x1.2p+0 ) = 0x1.200000000000cp+0
++near:PASSED:fmul(0x1.000000000000cp+0, 0x1.2p+0 ) = 0x1.200000000000ep+0
++near:PASSED:fmul(0x1.000000000000dp+0, 0x1.2p+0 ) = 0x1.200000000000fp+0
++near:PASSED:fmul(0x1.000000000000ep+0, 0x1.2p+0 ) = 0x1.200000000001p+0
++near:PASSED:fmul(0x1.000000000000fp+0, 0x1.2p+0 ) = 0x1.2000000000011p+0
++zero:PASSED:fmul(-0x1p+0 , 0x1.2p+0 ) = -0x1.2p+0
++zero:PASSED:fmul(-0x1.0000000000001p+0, 0x1.2p+0 ) = -0x1.2000000000001p+0
++zero:PASSED:fmul(-0x1.0000000000002p+0, 0x1.2p+0 ) = -0x1.2000000000002p+0
++zero:PASSED:fmul(-0x1.0000000000003p+0, 0x1.2p+0 ) = -0x1.2000000000003p+0
++zero:PASSED:fmul(-0x1.0000000000004p+0, 0x1.2p+0 ) = -0x1.2000000000004p+0
++zero:PASSED:fmul(-0x1.0000000000005p+0, 0x1.2p+0 ) = -0x1.2000000000005p+0
++zero:PASSED:fmul(-0x1.0000000000006p+0, 0x1.2p+0 ) = -0x1.2000000000006p+0
++zero:PASSED:fmul(-0x1.0000000000007p+0, 0x1.2p+0 ) = -0x1.2000000000007p+0
++zero:PASSED:fmul(-0x1.0000000000008p+0, 0x1.2p+0 ) = -0x1.2000000000009p+0
++zero:PASSED:fmul(-0x1.0000000000009p+0, 0x1.2p+0 ) = -0x1.200000000000ap+0
++zero:PASSED:fmul(-0x1.000000000000ap+0, 0x1.2p+0 ) = -0x1.200000000000bp+0
++zero:PASSED:fmul(-0x1.000000000000bp+0, 0x1.2p+0 ) = -0x1.200000000000cp+0
++zero:PASSED:fmul(-0x1.000000000000cp+0, 0x1.2p+0 ) = -0x1.200000000000dp+0
++zero:PASSED:fmul(-0x1.000000000000dp+0, 0x1.2p+0 ) = -0x1.200000000000ep+0
++zero:PASSED:fmul(-0x1.000000000000ep+0, 0x1.2p+0 ) = -0x1.200000000000fp+0
++zero:PASSED:fmul(-0x1.000000000000fp+0, 0x1.2p+0 ) = -0x1.200000000001p+0
++zero:PASSED:fmul(0x1p+0 , 0x1.2p+0 ) = 0x1.2p+0
++zero:PASSED:fmul(0x1.0000000000001p+0, 0x1.2p+0 ) = 0x1.2000000000001p+0
++zero:PASSED:fmul(0x1.0000000000002p+0, 0x1.2p+0 ) = 0x1.2000000000002p+0
++zero:PASSED:fmul(0x1.0000000000003p+0, 0x1.2p+0 ) = 0x1.2000000000003p+0
++zero:PASSED:fmul(0x1.0000000000004p+0, 0x1.2p+0 ) = 0x1.2000000000004p+0
++zero:PASSED:fmul(0x1.0000000000005p+0, 0x1.2p+0 ) = 0x1.2000000000005p+0
++zero:PASSED:fmul(0x1.0000000000006p+0, 0x1.2p+0 ) = 0x1.2000000000006p+0
++zero:PASSED:fmul(0x1.0000000000007p+0, 0x1.2p+0 ) = 0x1.2000000000007p+0
++zero:PASSED:fmul(0x1.0000000000008p+0, 0x1.2p+0 ) = 0x1.2000000000009p+0
++zero:PASSED:fmul(0x1.0000000000009p+0, 0x1.2p+0 ) = 0x1.200000000000ap+0
++zero:PASSED:fmul(0x1.000000000000ap+0, 0x1.2p+0 ) = 0x1.200000000000bp+0
++zero:PASSED:fmul(0x1.000000000000bp+0, 0x1.2p+0 ) = 0x1.200000000000cp+0
++zero:PASSED:fmul(0x1.000000000000cp+0, 0x1.2p+0 ) = 0x1.200000000000dp+0
++zero:PASSED:fmul(0x1.000000000000dp+0, 0x1.2p+0 ) = 0x1.200000000000ep+0
++zero:PASSED:fmul(0x1.000000000000ep+0, 0x1.2p+0 ) = 0x1.200000000000fp+0
++zero:PASSED:fmul(0x1.000000000000fp+0, 0x1.2p+0 ) = 0x1.200000000001p+0
+++inf:PASSED:fmul(-0x1p+0 , 0x1.2p+0 ) = -0x1.2p+0
+++inf:PASSED:fmul(-0x1.0000000000001p+0, 0x1.2p+0 ) = -0x1.2000000000001p+0
+++inf:PASSED:fmul(-0x1.0000000000002p+0, 0x1.2p+0 ) = -0x1.2000000000002p+0
+++inf:PASSED:fmul(-0x1.0000000000003p+0, 0x1.2p+0 ) = -0x1.2000000000003p+0
+++inf:PASSED:fmul(-0x1.0000000000004p+0, 0x1.2p+0 ) = -0x1.2000000000004p+0
+++inf:PASSED:fmul(-0x1.0000000000005p+0, 0x1.2p+0 ) = -0x1.2000000000005p+0
+++inf:PASSED:fmul(-0x1.0000000000006p+0, 0x1.2p+0 ) = -0x1.2000000000006p+0
+++inf:PASSED:fmul(-0x1.0000000000007p+0, 0x1.2p+0 ) = -0x1.2000000000007p+0
+++inf:PASSED:fmul(-0x1.0000000000008p+0, 0x1.2p+0 ) = -0x1.2000000000009p+0
+++inf:PASSED:fmul(-0x1.0000000000009p+0, 0x1.2p+0 ) = -0x1.200000000000ap+0
+++inf:PASSED:fmul(-0x1.000000000000ap+0, 0x1.2p+0 ) = -0x1.200000000000bp+0
+++inf:PASSED:fmul(-0x1.000000000000bp+0, 0x1.2p+0 ) = -0x1.200000000000cp+0
+++inf:PASSED:fmul(-0x1.000000000000cp+0, 0x1.2p+0 ) = -0x1.200000000000dp+0
+++inf:PASSED:fmul(-0x1.000000000000dp+0, 0x1.2p+0 ) = -0x1.200000000000ep+0
+++inf:PASSED:fmul(-0x1.000000000000ep+0, 0x1.2p+0 ) = -0x1.200000000000fp+0
+++inf:PASSED:fmul(-0x1.000000000000fp+0, 0x1.2p+0 ) = -0x1.200000000001p+0
+++inf:PASSED:fmul(0x1p+0 , 0x1.2p+0 ) = 0x1.2p+0
+++inf:PASSED:fmul(0x1.0000000000001p+0, 0x1.2p+0 ) = 0x1.2000000000002p+0
+++inf:PASSED:fmul(0x1.0000000000002p+0, 0x1.2p+0 ) = 0x1.2000000000003p+0
+++inf:PASSED:fmul(0x1.0000000000003p+0, 0x1.2p+0 ) = 0x1.2000000000004p+0
+++inf:PASSED:fmul(0x1.0000000000004p+0, 0x1.2p+0 ) = 0x1.2000000000005p+0
+++inf:PASSED:fmul(0x1.0000000000005p+0, 0x1.2p+0 ) = 0x1.2000000000006p+0
+++inf:PASSED:fmul(0x1.0000000000006p+0, 0x1.2p+0 ) = 0x1.2000000000007p+0
+++inf:PASSED:fmul(0x1.0000000000007p+0, 0x1.2p+0 ) = 0x1.2000000000008p+0
+++inf:PASSED:fmul(0x1.0000000000008p+0, 0x1.2p+0 ) = 0x1.2000000000009p+0
+++inf:PASSED:fmul(0x1.0000000000009p+0, 0x1.2p+0 ) = 0x1.200000000000bp+0
+++inf:PASSED:fmul(0x1.000000000000ap+0, 0x1.2p+0 ) = 0x1.200000000000cp+0
+++inf:PASSED:fmul(0x1.000000000000bp+0, 0x1.2p+0 ) = 0x1.200000000000dp+0
+++inf:PASSED:fmul(0x1.000000000000cp+0, 0x1.2p+0 ) = 0x1.200000000000ep+0
+++inf:PASSED:fmul(0x1.000000000000dp+0, 0x1.2p+0 ) = 0x1.200000000000fp+0
+++inf:PASSED:fmul(0x1.000000000000ep+0, 0x1.2p+0 ) = 0x1.200000000001p+0
+++inf:PASSED:fmul(0x1.000000000000fp+0, 0x1.2p+0 ) = 0x1.2000000000011p+0
++-inf:PASSED:fmul(-0x1p+0 , 0x1.2p+0 ) = -0x1.2p+0
++-inf:PASSED:fmul(-0x1.0000000000001p+0, 0x1.2p+0 ) = -0x1.2000000000002p+0
++-inf:PASSED:fmul(-0x1.0000000000002p+0, 0x1.2p+0 ) = -0x1.2000000000003p+0
++-inf:PASSED:fmul(-0x1.0000000000003p+0, 0x1.2p+0 ) = -0x1.2000000000004p+0
++-inf:PASSED:fmul(-0x1.0000000000004p+0, 0x1.2p+0 ) = -0x1.2000000000005p+0
++-inf:PASSED:fmul(-0x1.0000000000005p+0, 0x1.2p+0 ) = -0x1.2000000000006p+0
++-inf:PASSED:fmul(-0x1.0000000000006p+0, 0x1.2p+0 ) = -0x1.2000000000007p+0
++-inf:PASSED:fmul(-0x1.0000000000007p+0, 0x1.2p+0 ) = -0x1.2000000000008p+0
++-inf:PASSED:fmul(-0x1.0000000000008p+0, 0x1.2p+0 ) = -0x1.2000000000009p+0
++-inf:PASSED:fmul(-0x1.0000000000009p+0, 0x1.2p+0 ) = -0x1.200000000000bp+0
++-inf:PASSED:fmul(-0x1.000000000000ap+0, 0x1.2p+0 ) = -0x1.200000000000cp+0
++-inf:PASSED:fmul(-0x1.000000000000bp+0, 0x1.2p+0 ) = -0x1.200000000000dp+0
++-inf:PASSED:fmul(-0x1.000000000000cp+0, 0x1.2p+0 ) = -0x1.200000000000ep+0
++-inf:PASSED:fmul(-0x1.000000000000dp+0, 0x1.2p+0 ) = -0x1.200000000000fp+0
++-inf:PASSED:fmul(-0x1.000000000000ep+0, 0x1.2p+0 ) = -0x1.200000000001p+0
++-inf:PASSED:fmul(-0x1.000000000000fp+0, 0x1.2p+0 ) = -0x1.2000000000011p+0
++-inf:PASSED:fmul(0x1p+0 , 0x1.2p+0 ) = 0x1.2p+0
++-inf:PASSED:fmul(0x1.0000000000001p+0, 0x1.2p+0 ) = 0x1.2000000000001p+0
++-inf:PASSED:fmul(0x1.0000000000002p+0, 0x1.2p+0 ) = 0x1.2000000000002p+0
++-inf:PASSED:fmul(0x1.0000000000003p+0, 0x1.2p+0 ) = 0x1.2000000000003p+0
++-inf:PASSED:fmul(0x1.0000000000004p+0, 0x1.2p+0 ) = 0x1.2000000000004p+0
++-inf:PASSED:fmul(0x1.0000000000005p+0, 0x1.2p+0 ) = 0x1.2000000000005p+0
++-inf:PASSED:fmul(0x1.0000000000006p+0, 0x1.2p+0 ) = 0x1.2000000000006p+0
++-inf:PASSED:fmul(0x1.0000000000007p+0, 0x1.2p+0 ) = 0x1.2000000000007p+0
++-inf:PASSED:fmul(0x1.0000000000008p+0, 0x1.2p+0 ) = 0x1.2000000000009p+0
++-inf:PASSED:fmul(0x1.0000000000009p+0, 0x1.2p+0 ) = 0x1.200000000000ap+0
++-inf:PASSED:fmul(0x1.000000000000ap+0, 0x1.2p+0 ) = 0x1.200000000000bp+0
++-inf:PASSED:fmul(0x1.000000000000bp+0, 0x1.2p+0 ) = 0x1.200000000000cp+0
++-inf:PASSED:fmul(0x1.000000000000cp+0, 0x1.2p+0 ) = 0x1.200000000000dp+0
++-inf:PASSED:fmul(0x1.000000000000dp+0, 0x1.2p+0 ) = 0x1.200000000000ep+0
++-inf:PASSED:fmul(0x1.000000000000ep+0, 0x1.2p+0 ) = 0x1.200000000000fp+0
++-inf:PASSED:fmul(0x1.000000000000fp+0, 0x1.2p+0 ) = 0x1.200000000001p+0
++-62/62
++near:PASSED:fdiv(-0x1.fp+5 , 0x1.fp+5 ) = -0x1p+0
++-64/62
++near:PASSED:fdiv(-0x1p+6 , 0x1.fp+5 ) = -0x1.0842108421084p+0
++-66/62
++near:PASSED:fdiv(-0x1.08p+6 , 0x1.fp+5 ) = -0x1.1084210842108p+0
++-100/62
++near:PASSED:fdiv(-0x1.9p+6 , 0x1.fp+5 ) = -0x1.9ce739ce739cep+0
++near:PASSED:fdiv(0x0.0000000000001p-1022, -0x1p+1 ) = -0x0p+0
++-102/62
++near:PASSED:fdiv(-0x1.98p+6 , 0x1.fp+5 ) = -0x1.a5294a5294a53p+0
++-106/62
++near:PASSED:fdiv(-0x1.a8p+6 , 0x1.fp+5 ) = -0x1.b5ad6b5ad6b5bp+0
++-108/62
++near:PASSED:fdiv(-0x1.bp+6 , 0x1.fp+5 ) = -0x1.bdef7bdef7bdfp+0
++-108/108
++near:PASSED:fdiv(-0x1.bp+6 , 0x1.bp+6 ) = -0x1p+0
++-112/62
++near:PASSED:fdiv(-0x1.cp+6 , 0x1.fp+5 ) = -0x1.ce739ce739ce7p+0
++-114/62
++near:PASSED:fdiv(-0x1.c8p+6 , 0x1.fp+5 ) = -0x1.d6b5ad6b5ad6bp+0
++-116/62
++near:PASSED:fdiv(-0x1.dp+6 , 0x1.fp+5 ) = -0x1.def7bdef7bdefp+0
++near:PASSED:fdiv(0x0.0000000000003p-1022, -0x1p+1 ) = -0x0.0000000000002p-1022
++-118/62
++near:PASSED:fdiv(-0x1.d8p+6 , 0x1.fp+5 ) = -0x1.e739ce739ce74p+0
++-90/62
++near:PASSED:fdiv(-0x1.68p+6 , 0x1.fp+5 ) = -0x1.739ce739ce73ap+0
++-92/62
++near:PASSED:fdiv(-0x1.7p+6 , 0x1.fp+5 ) = -0x1.7bdef7bdef7bep+0
++62/62
++near:PASSED:fdiv(0x1.fp+5 , 0x1.fp+5 ) = 0x1p+0
++64/62
++near:PASSED:fdiv(0x1p+6 , 0x1.fp+5 ) = 0x1.0842108421084p+0
++66/62
++near:PASSED:fdiv(0x1.08p+6 , 0x1.fp+5 ) = 0x1.1084210842108p+0
++100/62
++near:PASSED:fdiv(0x1.9p+6 , 0x1.fp+5 ) = 0x1.9ce739ce739cep+0
++near:PASSED:fdiv(0x0.0000000000001p-1022, 0x1p+1 ) = 0x0p+0
++102/62
++near:PASSED:fdiv(0x1.98p+6 , 0x1.fp+5 ) = 0x1.a5294a5294a53p+0
++106/62
++near:PASSED:fdiv(0x1.a8p+6 , 0x1.fp+5 ) = 0x1.b5ad6b5ad6b5bp+0
++108/62
++near:PASSED:fdiv(0x1.bp+6 , 0x1.fp+5 ) = 0x1.bdef7bdef7bdfp+0
++108/108
++near:PASSED:fdiv(0x1.bp+6 , 0x1.bp+6 ) = 0x1p+0
++112/62
++near:PASSED:fdiv(0x1.cp+6 , 0x1.fp+5 ) = 0x1.ce739ce739ce7p+0
++114/62
++near:PASSED:fdiv(0x1.c8p+6 , 0x1.fp+5 ) = 0x1.d6b5ad6b5ad6bp+0
++116/62
++near:PASSED:fdiv(0x1.dp+6 , 0x1.fp+5 ) = 0x1.def7bdef7bdefp+0
++near:PASSED:fdiv(0x0.0000000000003p-1022, 0x1p+1 ) = 0x0.0000000000002p-1022
++118/62
++near:PASSED:fdiv(0x1.d8p+6 , 0x1.fp+5 ) = 0x1.e739ce739ce74p+0
++90/62
++near:PASSED:fdiv(0x1.68p+6 , 0x1.fp+5 ) = 0x1.739ce739ce73ap+0
++92/62
++near:PASSED:fdiv(0x1.7p+6 , 0x1.fp+5 ) = 0x1.7bdef7bdef7bep+0
++-62/62
++zero:PASSED:fdiv(-0x1.fp+5 , 0x1.fp+5 ) = -0x1p+0
++-64/62
++zero:PASSED:fdiv(-0x1p+6 , 0x1.fp+5 ) = -0x1.0842108421084p+0
++-66/62
++zero:PASSED:fdiv(-0x1.08p+6 , 0x1.fp+5 ) = -0x1.1084210842108p+0
++-100/62
++zero:PASSED:fdiv(-0x1.9p+6 , 0x1.fp+5 ) = -0x1.9ce739ce739cep+0
++zero:PASSED:fdiv(0x0.0000000000001p-1022, -0x1p+1 ) = -0x0p+0
++-102/62
++zero:PASSED:fdiv(-0x1.98p+6 , 0x1.fp+5 ) = -0x1.a5294a5294a52p+0
++-106/62
++zero:PASSED:fdiv(-0x1.a8p+6 , 0x1.fp+5 ) = -0x1.b5ad6b5ad6b5ap+0
++-108/62
++zero:PASSED:fdiv(-0x1.bp+6 , 0x1.fp+5 ) = -0x1.bdef7bdef7bdep+0
++-108/108
++zero:PASSED:fdiv(-0x1.bp+6 , 0x1.bp+6 ) = -0x1p+0
++-112/62
++zero:PASSED:fdiv(-0x1.cp+6 , 0x1.fp+5 ) = -0x1.ce739ce739ce7p+0
++-114/62
++zero:PASSED:fdiv(-0x1.c8p+6 , 0x1.fp+5 ) = -0x1.d6b5ad6b5ad6bp+0
++-116/62
++zero:PASSED:fdiv(-0x1.dp+6 , 0x1.fp+5 ) = -0x1.def7bdef7bdefp+0
++zero:PASSED:fdiv(0x0.0000000000003p-1022, -0x1p+1 ) = -0x0.0000000000001p-1022
++-118/62
++zero:PASSED:fdiv(-0x1.d8p+6 , 0x1.fp+5 ) = -0x1.e739ce739ce73p+0
++-90/62
++zero:PASSED:fdiv(-0x1.68p+6 , 0x1.fp+5 ) = -0x1.739ce739ce739p+0
++-92/62
++zero:PASSED:fdiv(-0x1.7p+6 , 0x1.fp+5 ) = -0x1.7bdef7bdef7bdp+0
++62/62
++zero:PASSED:fdiv(0x1.fp+5 , 0x1.fp+5 ) = 0x1p+0
++64/62
++zero:PASSED:fdiv(0x1p+6 , 0x1.fp+5 ) = 0x1.0842108421084p+0
++66/62
++zero:PASSED:fdiv(0x1.08p+6 , 0x1.fp+5 ) = 0x1.1084210842108p+0
++100/62
++zero:PASSED:fdiv(0x1.9p+6 , 0x1.fp+5 ) = 0x1.9ce739ce739cep+0
++zero:PASSED:fdiv(0x0.0000000000001p-1022, 0x1p+1 ) = 0x0p+0
++102/62
++zero:PASSED:fdiv(0x1.98p+6 , 0x1.fp+5 ) = 0x1.a5294a5294a52p+0
++106/62
++zero:PASSED:fdiv(0x1.a8p+6 , 0x1.fp+5 ) = 0x1.b5ad6b5ad6b5ap+0
++108/62
++zero:PASSED:fdiv(0x1.bp+6 , 0x1.fp+5 ) = 0x1.bdef7bdef7bdep+0
++108/108
++zero:PASSED:fdiv(0x1.bp+6 , 0x1.bp+6 ) = 0x1p+0
++112/62
++zero:PASSED:fdiv(0x1.cp+6 , 0x1.fp+5 ) = 0x1.ce739ce739ce7p+0
++114/62
++zero:PASSED:fdiv(0x1.c8p+6 , 0x1.fp+5 ) = 0x1.d6b5ad6b5ad6bp+0
++116/62
++zero:PASSED:fdiv(0x1.dp+6 , 0x1.fp+5 ) = 0x1.def7bdef7bdefp+0
++zero:PASSED:fdiv(0x0.0000000000003p-1022, 0x1p+1 ) = 0x0.0000000000001p-1022
++118/62
++zero:PASSED:fdiv(0x1.d8p+6 , 0x1.fp+5 ) = 0x1.e739ce739ce73p+0
++90/62
++zero:PASSED:fdiv(0x1.68p+6 , 0x1.fp+5 ) = 0x1.739ce739ce739p+0
++92/62
++zero:PASSED:fdiv(0x1.7p+6 , 0x1.fp+5 ) = 0x1.7bdef7bdef7bdp+0
++-62/62
+++inf:PASSED:fdiv(-0x1.fp+5 , 0x1.fp+5 ) = -0x1p+0
++-64/62
+++inf:PASSED:fdiv(-0x1p+6 , 0x1.fp+5 ) = -0x1.0842108421084p+0
++-66/62
+++inf:PASSED:fdiv(-0x1.08p+6 , 0x1.fp+5 ) = -0x1.1084210842108p+0
++-100/62
+++inf:PASSED:fdiv(-0x1.9p+6 , 0x1.fp+5 ) = -0x1.9ce739ce739cep+0
+++inf:PASSED:fdiv(0x0.0000000000001p-1022, -0x1p+1 ) = -0x0p+0
++-102/62
+++inf:PASSED:fdiv(-0x1.98p+6 , 0x1.fp+5 ) = -0x1.a5294a5294a52p+0
++-106/62
+++inf:PASSED:fdiv(-0x1.a8p+6 , 0x1.fp+5 ) = -0x1.b5ad6b5ad6b5ap+0
++-108/62
+++inf:PASSED:fdiv(-0x1.bp+6 , 0x1.fp+5 ) = -0x1.bdef7bdef7bdep+0
++-108/108
+++inf:PASSED:fdiv(-0x1.bp+6 , 0x1.bp+6 ) = -0x1p+0
++-112/62
+++inf:PASSED:fdiv(-0x1.cp+6 , 0x1.fp+5 ) = -0x1.ce739ce739ce7p+0
++-114/62
+++inf:PASSED:fdiv(-0x1.c8p+6 , 0x1.fp+5 ) = -0x1.d6b5ad6b5ad6bp+0
++-116/62
+++inf:PASSED:fdiv(-0x1.dp+6 , 0x1.fp+5 ) = -0x1.def7bdef7bdefp+0
+++inf:PASSED:fdiv(0x0.0000000000003p-1022, -0x1p+1 ) = -0x0.0000000000001p-1022
++-118/62
+++inf:PASSED:fdiv(-0x1.d8p+6 , 0x1.fp+5 ) = -0x1.e739ce739ce73p+0
++-90/62
+++inf:PASSED:fdiv(-0x1.68p+6 , 0x1.fp+5 ) = -0x1.739ce739ce739p+0
++-92/62
+++inf:PASSED:fdiv(-0x1.7p+6 , 0x1.fp+5 ) = -0x1.7bdef7bdef7bdp+0
++62/62
+++inf:PASSED:fdiv(0x1.fp+5 , 0x1.fp+5 ) = 0x1p+0
++64/62
+++inf:PASSED:fdiv(0x1p+6 , 0x1.fp+5 ) = 0x1.0842108421085p+0
++66/62
+++inf:PASSED:fdiv(0x1.08p+6 , 0x1.fp+5 ) = 0x1.1084210842109p+0
++100/62
+++inf:PASSED:fdiv(0x1.9p+6 , 0x1.fp+5 ) = 0x1.9ce739ce739cfp+0
+++inf:PASSED:fdiv(0x0.0000000000001p-1022, 0x1p+1 ) = 0x0.0000000000001p-1022
++102/62
+++inf:PASSED:fdiv(0x1.98p+6 , 0x1.fp+5 ) = 0x1.a5294a5294a53p+0
++106/62
+++inf:PASSED:fdiv(0x1.a8p+6 , 0x1.fp+5 ) = 0x1.b5ad6b5ad6b5bp+0
++108/62
+++inf:PASSED:fdiv(0x1.bp+6 , 0x1.fp+5 ) = 0x1.bdef7bdef7bdfp+0
++108/108
+++inf:PASSED:fdiv(0x1.bp+6 , 0x1.bp+6 ) = 0x1p+0
++112/62
+++inf:PASSED:fdiv(0x1.cp+6 , 0x1.fp+5 ) = 0x1.ce739ce739ce8p+0
++114/62
+++inf:PASSED:fdiv(0x1.c8p+6 , 0x1.fp+5 ) = 0x1.d6b5ad6b5ad6cp+0
++116/62
+++inf:PASSED:fdiv(0x1.dp+6 , 0x1.fp+5 ) = 0x1.def7bdef7bdfp+0
+++inf:PASSED:fdiv(0x0.0000000000003p-1022, 0x1p+1 ) = 0x0.0000000000002p-1022
++118/62
+++inf:PASSED:fdiv(0x1.d8p+6 , 0x1.fp+5 ) = 0x1.e739ce739ce74p+0
++90/62
+++inf:PASSED:fdiv(0x1.68p+6 , 0x1.fp+5 ) = 0x1.739ce739ce73ap+0
++92/62
+++inf:PASSED:fdiv(0x1.7p+6 , 0x1.fp+5 ) = 0x1.7bdef7bdef7bep+0
++-62/62
++-inf:PASSED:fdiv(-0x1.fp+5 , 0x1.fp+5 ) = -0x1p+0
++-64/62
++-inf:PASSED:fdiv(-0x1p+6 , 0x1.fp+5 ) = -0x1.0842108421085p+0
++-66/62
++-inf:PASSED:fdiv(-0x1.08p+6 , 0x1.fp+5 ) = -0x1.1084210842109p+0
++-100/62
++-inf:PASSED:fdiv(-0x1.9p+6 , 0x1.fp+5 ) = -0x1.9ce739ce739cfp+0
++-inf:PASSED:fdiv(0x0.0000000000001p-1022, -0x1p+1 ) = -0x0.0000000000001p-1022
++-102/62
++-inf:PASSED:fdiv(-0x1.98p+6 , 0x1.fp+5 ) = -0x1.a5294a5294a53p+0
++-106/62
++-inf:PASSED:fdiv(-0x1.a8p+6 , 0x1.fp+5 ) = -0x1.b5ad6b5ad6b5bp+0
++-108/62
++-inf:PASSED:fdiv(-0x1.bp+6 , 0x1.fp+5 ) = -0x1.bdef7bdef7bdfp+0
++-108/108
++-inf:PASSED:fdiv(-0x1.bp+6 , 0x1.bp+6 ) = -0x1p+0
++-112/62
++-inf:PASSED:fdiv(-0x1.cp+6 , 0x1.fp+5 ) = -0x1.ce739ce739ce8p+0
++-114/62
++-inf:PASSED:fdiv(-0x1.c8p+6 , 0x1.fp+5 ) = -0x1.d6b5ad6b5ad6cp+0
++-116/62
++-inf:PASSED:fdiv(-0x1.dp+6 , 0x1.fp+5 ) = -0x1.def7bdef7bdfp+0
++-inf:PASSED:fdiv(0x0.0000000000003p-1022, -0x1p+1 ) = -0x0.0000000000002p-1022
++-118/62
++-inf:PASSED:fdiv(-0x1.d8p+6 , 0x1.fp+5 ) = -0x1.e739ce739ce74p+0
++-90/62
++-inf:PASSED:fdiv(-0x1.68p+6 , 0x1.fp+5 ) = -0x1.739ce739ce73ap+0
++-92/62
++-inf:PASSED:fdiv(-0x1.7p+6 , 0x1.fp+5 ) = -0x1.7bdef7bdef7bep+0
++62/62
++-inf:PASSED:fdiv(0x1.fp+5 , 0x1.fp+5 ) = 0x1p+0
++64/62
++-inf:PASSED:fdiv(0x1p+6 , 0x1.fp+5 ) = 0x1.0842108421084p+0
++66/62
++-inf:PASSED:fdiv(0x1.08p+6 , 0x1.fp+5 ) = 0x1.1084210842108p+0
++100/62
++-inf:PASSED:fdiv(0x1.9p+6 , 0x1.fp+5 ) = 0x1.9ce739ce739cep+0
++-inf:PASSED:fdiv(0x0.0000000000001p-1022, 0x1p+1 ) = 0x0p+0
++102/62
++-inf:PASSED:fdiv(0x1.98p+6 , 0x1.fp+5 ) = 0x1.a5294a5294a52p+0
++106/62
++-inf:PASSED:fdiv(0x1.a8p+6 , 0x1.fp+5 ) = 0x1.b5ad6b5ad6b5ap+0
++108/62
++-inf:PASSED:fdiv(0x1.bp+6 , 0x1.fp+5 ) = 0x1.bdef7bdef7bdep+0
++108/108
++-inf:PASSED:fdiv(0x1.bp+6 , 0x1.bp+6 ) = 0x1p+0
++112/62
++-inf:PASSED:fdiv(0x1.cp+6 , 0x1.fp+5 ) = 0x1.ce739ce739ce7p+0
++114/62
++-inf:PASSED:fdiv(0x1.c8p+6 , 0x1.fp+5 ) = 0x1.d6b5ad6b5ad6bp+0
++116/62
++-inf:PASSED:fdiv(0x1.dp+6 , 0x1.fp+5 ) = 0x1.def7bdef7bdefp+0
++-inf:PASSED:fdiv(0x0.0000000000003p-1022, 0x1p+1 ) = 0x0.0000000000001p-1022
++118/62
++-inf:PASSED:fdiv(0x1.d8p+6 , 0x1.fp+5 ) = 0x1.e739ce739ce73p+0
++90/62
++-inf:PASSED:fdiv(0x1.68p+6 , 0x1.fp+5 ) = 0x1.739ce739ce739p+0
++92/62
++-inf:PASSED:fdiv(0x1.7p+6 , 0x1.fp+5 ) = 0x1.7bdef7bdef7bdp+0
++near:PASSED:fmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.ap+0
++near:PASSED:fmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0
++near:PASSED:fmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0
++near:PASSED:fmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000004p+0
++near:PASSED:fmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0
++near:PASSED:fmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000006p+0
++near:PASSED:fmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0
++near:PASSED:fmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0
++near:PASSED:fmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0
++near:PASSED:fmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0
++near:PASSED:fmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0
++near:PASSED:fmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000dp+0
++near:PASSED:fmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0
++near:PASSED:fmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000fp+0
++near:PASSED:fmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0
++near:PASSED:fmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0
++near:PASSED:fmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.ap+0
++near:PASSED:fmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0
++near:PASSED:fmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0
++near:PASSED:fmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000004p+0
++near:PASSED:fmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0
++near:PASSED:fmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000006p+0
++near:PASSED:fmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0
++near:PASSED:fmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0
++near:PASSED:fmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0
++near:PASSED:fmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0
++near:PASSED:fmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0
++near:PASSED:fmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000dp+0
++near:PASSED:fmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0
++near:PASSED:fmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000fp+0
++near:PASSED:fmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0
++near:PASSED:fmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0
++zero:PASSED:fmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.ap+0
++zero:PASSED:fmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000001p+0
++zero:PASSED:fmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0
++zero:PASSED:fmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0
++zero:PASSED:fmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0
++zero:PASSED:fmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000006p+0
++zero:PASSED:fmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0
++zero:PASSED:fmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0
++zero:PASSED:fmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000009p+0
++zero:PASSED:fmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0
++zero:PASSED:fmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0
++zero:PASSED:fmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0
++zero:PASSED:fmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0
++zero:PASSED:fmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000fp+0
++zero:PASSED:fmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0
++zero:PASSED:fmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0
++zero:PASSED:fmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.ap+0
++zero:PASSED:fmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000001p+0
++zero:PASSED:fmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0
++zero:PASSED:fmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0
++zero:PASSED:fmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0
++zero:PASSED:fmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000006p+0
++zero:PASSED:fmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0
++zero:PASSED:fmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0
++zero:PASSED:fmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000009p+0
++zero:PASSED:fmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0
++zero:PASSED:fmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0
++zero:PASSED:fmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0
++zero:PASSED:fmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0
++zero:PASSED:fmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000fp+0
++zero:PASSED:fmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0
++zero:PASSED:fmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0
+++inf:PASSED:fmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.ap+0
+++inf:PASSED:fmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000001p+0
+++inf:PASSED:fmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0
+++inf:PASSED:fmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0
+++inf:PASSED:fmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0
+++inf:PASSED:fmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000006p+0
+++inf:PASSED:fmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0
+++inf:PASSED:fmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0
+++inf:PASSED:fmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000009p+0
+++inf:PASSED:fmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0
+++inf:PASSED:fmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0
+++inf:PASSED:fmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0
+++inf:PASSED:fmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0
+++inf:PASSED:fmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000fp+0
+++inf:PASSED:fmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0
+++inf:PASSED:fmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0
+++inf:PASSED:fmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000001p+0
+++inf:PASSED:fmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0
+++inf:PASSED:fmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0
+++inf:PASSED:fmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000004p+0
+++inf:PASSED:fmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0
+++inf:PASSED:fmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0
+++inf:PASSED:fmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0
+++inf:PASSED:fmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000009p+0
+++inf:PASSED:fmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0
+++inf:PASSED:fmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0
+++inf:PASSED:fmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0
+++inf:PASSED:fmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000dp+0
+++inf:PASSED:fmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0
+++inf:PASSED:fmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0
+++inf:PASSED:fmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0
+++inf:PASSED:fmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000012p+0
++-inf:PASSED:fmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000001p+0
++-inf:PASSED:fmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0
++-inf:PASSED:fmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0
++-inf:PASSED:fmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000004p+0
++-inf:PASSED:fmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0
++-inf:PASSED:fmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0
++-inf:PASSED:fmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0
++-inf:PASSED:fmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000009p+0
++-inf:PASSED:fmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0
++-inf:PASSED:fmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0
++-inf:PASSED:fmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0
++-inf:PASSED:fmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000dp+0
++-inf:PASSED:fmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0
++-inf:PASSED:fmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0
++-inf:PASSED:fmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0
++-inf:PASSED:fmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000012p+0
++-inf:PASSED:fmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.ap+0
++-inf:PASSED:fmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000001p+0
++-inf:PASSED:fmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0
++-inf:PASSED:fmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0
++-inf:PASSED:fmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0
++-inf:PASSED:fmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000006p+0
++-inf:PASSED:fmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0
++-inf:PASSED:fmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0
++-inf:PASSED:fmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000009p+0
++-inf:PASSED:fmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0
++-inf:PASSED:fmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0
++-inf:PASSED:fmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0
++-inf:PASSED:fmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0
++-inf:PASSED:fmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000fp+0
++-inf:PASSED:fmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0
++-inf:PASSED:fmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0
++near:PASSED:fmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.ap+0
++near:PASSED:fmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0
++near:PASSED:fmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0
++near:PASSED:fmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000004p+0
++near:PASSED:fmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0
++near:PASSED:fmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000006p+0
++near:PASSED:fmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0
++near:PASSED:fmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0
++near:PASSED:fmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0
++near:PASSED:fmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0
++near:PASSED:fmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0
++near:PASSED:fmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000dp+0
++near:PASSED:fmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0
++near:PASSED:fmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000fp+0
++near:PASSED:fmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0
++near:PASSED:fmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0
++near:PASSED:fmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.ap+0
++near:PASSED:fmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0
++near:PASSED:fmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0
++near:PASSED:fmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000004p+0
++near:PASSED:fmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0
++near:PASSED:fmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000006p+0
++near:PASSED:fmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0
++near:PASSED:fmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0
++near:PASSED:fmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0
++near:PASSED:fmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0
++near:PASSED:fmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0
++near:PASSED:fmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000dp+0
++near:PASSED:fmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0
++near:PASSED:fmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000fp+0
++near:PASSED:fmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0
++near:PASSED:fmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0
++zero:PASSED:fmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.ap+0
++zero:PASSED:fmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000001p+0
++zero:PASSED:fmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0
++zero:PASSED:fmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0
++zero:PASSED:fmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0
++zero:PASSED:fmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000006p+0
++zero:PASSED:fmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0
++zero:PASSED:fmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0
++zero:PASSED:fmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000009p+0
++zero:PASSED:fmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0
++zero:PASSED:fmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0
++zero:PASSED:fmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0
++zero:PASSED:fmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0
++zero:PASSED:fmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000fp+0
++zero:PASSED:fmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0
++zero:PASSED:fmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0
++zero:PASSED:fmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.ap+0
++zero:PASSED:fmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000001p+0
++zero:PASSED:fmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0
++zero:PASSED:fmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0
++zero:PASSED:fmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0
++zero:PASSED:fmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000006p+0
++zero:PASSED:fmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0
++zero:PASSED:fmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0
++zero:PASSED:fmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000009p+0
++zero:PASSED:fmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0
++zero:PASSED:fmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0
++zero:PASSED:fmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0
++zero:PASSED:fmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0
++zero:PASSED:fmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000fp+0
++zero:PASSED:fmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0
++zero:PASSED:fmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0
+++inf:PASSED:fmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.ap+0
+++inf:PASSED:fmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000001p+0
+++inf:PASSED:fmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0
+++inf:PASSED:fmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0
+++inf:PASSED:fmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0
+++inf:PASSED:fmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000006p+0
+++inf:PASSED:fmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0
+++inf:PASSED:fmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0
+++inf:PASSED:fmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000009p+0
+++inf:PASSED:fmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0
+++inf:PASSED:fmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0
+++inf:PASSED:fmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0
+++inf:PASSED:fmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0
+++inf:PASSED:fmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000fp+0
+++inf:PASSED:fmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0
+++inf:PASSED:fmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0
+++inf:PASSED:fmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000001p+0
+++inf:PASSED:fmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0
+++inf:PASSED:fmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0
+++inf:PASSED:fmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000004p+0
+++inf:PASSED:fmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0
+++inf:PASSED:fmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0
+++inf:PASSED:fmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0
+++inf:PASSED:fmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000009p+0
+++inf:PASSED:fmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0
+++inf:PASSED:fmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0
+++inf:PASSED:fmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0
+++inf:PASSED:fmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000dp+0
+++inf:PASSED:fmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0
+++inf:PASSED:fmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0
+++inf:PASSED:fmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0
+++inf:PASSED:fmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000012p+0
++-inf:PASSED:fmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000001p+0
++-inf:PASSED:fmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0
++-inf:PASSED:fmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0
++-inf:PASSED:fmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000004p+0
++-inf:PASSED:fmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0
++-inf:PASSED:fmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0
++-inf:PASSED:fmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0
++-inf:PASSED:fmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000009p+0
++-inf:PASSED:fmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0
++-inf:PASSED:fmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0
++-inf:PASSED:fmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0
++-inf:PASSED:fmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000dp+0
++-inf:PASSED:fmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0
++-inf:PASSED:fmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0
++-inf:PASSED:fmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0
++-inf:PASSED:fmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000012p+0
++-inf:PASSED:fmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.ap+0
++-inf:PASSED:fmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000001p+0
++-inf:PASSED:fmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0
++-inf:PASSED:fmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0
++-inf:PASSED:fmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0
++-inf:PASSED:fmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000006p+0
++-inf:PASSED:fmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0
++-inf:PASSED:fmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0
++-inf:PASSED:fmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000009p+0
++-inf:PASSED:fmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0
++-inf:PASSED:fmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0
++-inf:PASSED:fmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0
++-inf:PASSED:fmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0
++-inf:PASSED:fmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000fp+0
++-inf:PASSED:fmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0
++-inf:PASSED:fmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0
++near:PASSED:fnmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.ap+0
++near:PASSED:fnmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0
++near:PASSED:fnmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0
++near:PASSED:fnmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000004p+0
++near:PASSED:fnmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0
++near:PASSED:fnmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000006p+0
++near:PASSED:fnmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0
++near:PASSED:fnmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0
++near:PASSED:fnmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0
++near:PASSED:fnmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0
++near:PASSED:fnmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0
++near:PASSED:fnmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000dp+0
++near:PASSED:fnmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0
++near:PASSED:fnmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000fp+0
++near:PASSED:fnmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0
++near:PASSED:fnmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0
++near:PASSED:fnmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.ap+0
++near:PASSED:fnmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0
++near:PASSED:fnmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0
++near:PASSED:fnmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000004p+0
++near:PASSED:fnmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0
++near:PASSED:fnmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000006p+0
++near:PASSED:fnmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0
++near:PASSED:fnmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0
++near:PASSED:fnmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0
++near:PASSED:fnmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0
++near:PASSED:fnmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0
++near:PASSED:fnmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000dp+0
++near:PASSED:fnmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0
++near:PASSED:fnmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000fp+0
++near:PASSED:fnmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0
++near:PASSED:fnmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0
++zero:PASSED:fnmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.ap+0
++zero:PASSED:fnmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000001p+0
++zero:PASSED:fnmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0
++zero:PASSED:fnmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0
++zero:PASSED:fnmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0
++zero:PASSED:fnmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000006p+0
++zero:PASSED:fnmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0
++zero:PASSED:fnmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0
++zero:PASSED:fnmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000009p+0
++zero:PASSED:fnmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0
++zero:PASSED:fnmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0
++zero:PASSED:fnmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0
++zero:PASSED:fnmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0
++zero:PASSED:fnmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000fp+0
++zero:PASSED:fnmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0
++zero:PASSED:fnmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0
++zero:PASSED:fnmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.ap+0
++zero:PASSED:fnmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000001p+0
++zero:PASSED:fnmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0
++zero:PASSED:fnmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0
++zero:PASSED:fnmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0
++zero:PASSED:fnmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000006p+0
++zero:PASSED:fnmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0
++zero:PASSED:fnmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0
++zero:PASSED:fnmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000009p+0
++zero:PASSED:fnmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0
++zero:PASSED:fnmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0
++zero:PASSED:fnmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0
++zero:PASSED:fnmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0
++zero:PASSED:fnmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000fp+0
++zero:PASSED:fnmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0
++zero:PASSED:fnmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0
+++inf:PASSED:fnmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.ap+0
+++inf:PASSED:fnmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000001p+0
+++inf:PASSED:fnmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0
+++inf:PASSED:fnmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0
+++inf:PASSED:fnmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0
+++inf:PASSED:fnmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000006p+0
+++inf:PASSED:fnmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0
+++inf:PASSED:fnmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0
+++inf:PASSED:fnmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000009p+0
+++inf:PASSED:fnmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0
+++inf:PASSED:fnmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0
+++inf:PASSED:fnmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0
+++inf:PASSED:fnmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0
+++inf:PASSED:fnmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000fp+0
+++inf:PASSED:fnmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0
+++inf:PASSED:fnmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0
+++inf:PASSED:fnmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000001p+0
+++inf:PASSED:fnmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0
+++inf:PASSED:fnmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0
+++inf:PASSED:fnmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000004p+0
+++inf:PASSED:fnmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0
+++inf:PASSED:fnmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0
+++inf:PASSED:fnmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0
+++inf:PASSED:fnmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000009p+0
+++inf:PASSED:fnmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0
+++inf:PASSED:fnmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0
+++inf:PASSED:fnmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0
+++inf:PASSED:fnmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000dp+0
+++inf:PASSED:fnmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0
+++inf:PASSED:fnmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0
+++inf:PASSED:fnmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0
+++inf:PASSED:fnmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000012p+0
++-inf:PASSED:fnmadd(-0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000001p+0
++-inf:PASSED:fnmadd(-0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000002p+0
++-inf:PASSED:fnmadd(-0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000003p+0
++-inf:PASSED:fnmadd(-0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000004p+0
++-inf:PASSED:fnmadd(-0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000005p+0
++-inf:PASSED:fnmadd(-0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000007p+0
++-inf:PASSED:fnmadd(-0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000008p+0
++-inf:PASSED:fnmadd(-0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000009p+0
++-inf:PASSED:fnmadd(-0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ap+0
++-inf:PASSED:fnmadd(-0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000bp+0
++-inf:PASSED:fnmadd(-0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000cp+0
++-inf:PASSED:fnmadd(-0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000dp+0
++-inf:PASSED:fnmadd(-0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000000ep+0
++-inf:PASSED:fnmadd(-0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a00000000001p+0
++-inf:PASSED:fnmadd(-0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000011p+0
++-inf:PASSED:fnmadd(-0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = 0x1.a000000000012p+0
++-inf:PASSED:fnmadd(0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.ap+0
++-inf:PASSED:fnmadd(0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000001p+0
++-inf:PASSED:fnmadd(0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000002p+0
++-inf:PASSED:fnmadd(0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000003p+0
++-inf:PASSED:fnmadd(0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000005p+0
++-inf:PASSED:fnmadd(0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000006p+0
++-inf:PASSED:fnmadd(0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000007p+0
++-inf:PASSED:fnmadd(0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000008p+0
++-inf:PASSED:fnmadd(0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000009p+0
++-inf:PASSED:fnmadd(0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ap+0
++-inf:PASSED:fnmadd(0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000bp+0
++-inf:PASSED:fnmadd(0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000cp+0
++-inf:PASSED:fnmadd(0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000ep+0
++-inf:PASSED:fnmadd(0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000000fp+0
++-inf:PASSED:fnmadd(0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a00000000001p+0
++-inf:PASSED:fnmadd(0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = -0x1.a000000000011p+0
++near:PASSED:fnmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.ap+0
++near:PASSED:fnmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0
++near:PASSED:fnmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0
++near:PASSED:fnmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000004p+0
++near:PASSED:fnmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0
++near:PASSED:fnmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000006p+0
++near:PASSED:fnmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0
++near:PASSED:fnmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0
++near:PASSED:fnmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0
++near:PASSED:fnmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0
++near:PASSED:fnmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0
++near:PASSED:fnmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000dp+0
++near:PASSED:fnmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0
++near:PASSED:fnmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000fp+0
++near:PASSED:fnmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0
++near:PASSED:fnmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0
++near:PASSED:fnmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.ap+0
++near:PASSED:fnmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0
++near:PASSED:fnmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0
++near:PASSED:fnmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000004p+0
++near:PASSED:fnmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0
++near:PASSED:fnmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000006p+0
++near:PASSED:fnmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0
++near:PASSED:fnmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0
++near:PASSED:fnmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0
++near:PASSED:fnmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0
++near:PASSED:fnmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0
++near:PASSED:fnmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000dp+0
++near:PASSED:fnmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0
++near:PASSED:fnmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000fp+0
++near:PASSED:fnmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0
++near:PASSED:fnmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0
++zero:PASSED:fnmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.ap+0
++zero:PASSED:fnmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000001p+0
++zero:PASSED:fnmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0
++zero:PASSED:fnmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0
++zero:PASSED:fnmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0
++zero:PASSED:fnmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000006p+0
++zero:PASSED:fnmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0
++zero:PASSED:fnmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0
++zero:PASSED:fnmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000009p+0
++zero:PASSED:fnmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0
++zero:PASSED:fnmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0
++zero:PASSED:fnmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0
++zero:PASSED:fnmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0
++zero:PASSED:fnmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000fp+0
++zero:PASSED:fnmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0
++zero:PASSED:fnmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0
++zero:PASSED:fnmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.ap+0
++zero:PASSED:fnmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000001p+0
++zero:PASSED:fnmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0
++zero:PASSED:fnmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0
++zero:PASSED:fnmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0
++zero:PASSED:fnmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000006p+0
++zero:PASSED:fnmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0
++zero:PASSED:fnmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0
++zero:PASSED:fnmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000009p+0
++zero:PASSED:fnmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0
++zero:PASSED:fnmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0
++zero:PASSED:fnmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0
++zero:PASSED:fnmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0
++zero:PASSED:fnmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000fp+0
++zero:PASSED:fnmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0
++zero:PASSED:fnmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0
+++inf:PASSED:fnmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.ap+0
+++inf:PASSED:fnmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000001p+0
+++inf:PASSED:fnmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0
+++inf:PASSED:fnmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0
+++inf:PASSED:fnmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0
+++inf:PASSED:fnmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000006p+0
+++inf:PASSED:fnmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0
+++inf:PASSED:fnmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0
+++inf:PASSED:fnmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000009p+0
+++inf:PASSED:fnmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0
+++inf:PASSED:fnmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0
+++inf:PASSED:fnmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0
+++inf:PASSED:fnmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0
+++inf:PASSED:fnmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000fp+0
+++inf:PASSED:fnmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0
+++inf:PASSED:fnmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0
+++inf:PASSED:fnmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000001p+0
+++inf:PASSED:fnmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0
+++inf:PASSED:fnmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0
+++inf:PASSED:fnmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000004p+0
+++inf:PASSED:fnmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0
+++inf:PASSED:fnmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0
+++inf:PASSED:fnmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0
+++inf:PASSED:fnmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000009p+0
+++inf:PASSED:fnmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0
+++inf:PASSED:fnmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0
+++inf:PASSED:fnmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0
+++inf:PASSED:fnmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000dp+0
+++inf:PASSED:fnmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0
+++inf:PASSED:fnmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0
+++inf:PASSED:fnmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0
+++inf:PASSED:fnmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000012p+0
++-inf:PASSED:fnmsub(-0x1p+0 , 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000001p+0
++-inf:PASSED:fnmsub(-0x1.0000000000001p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000002p+0
++-inf:PASSED:fnmsub(-0x1.0000000000002p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000003p+0
++-inf:PASSED:fnmsub(-0x1.0000000000003p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000004p+0
++-inf:PASSED:fnmsub(-0x1.0000000000004p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000005p+0
++-inf:PASSED:fnmsub(-0x1.0000000000005p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000007p+0
++-inf:PASSED:fnmsub(-0x1.0000000000006p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000008p+0
++-inf:PASSED:fnmsub(-0x1.0000000000007p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000009p+0
++-inf:PASSED:fnmsub(-0x1.0000000000008p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ap+0
++-inf:PASSED:fnmsub(-0x1.0000000000009p+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000bp+0
++-inf:PASSED:fnmsub(-0x1.000000000000ap+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000cp+0
++-inf:PASSED:fnmsub(-0x1.000000000000bp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000dp+0
++-inf:PASSED:fnmsub(-0x1.000000000000cp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000000ep+0
++-inf:PASSED:fnmsub(-0x1.000000000000dp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a00000000001p+0
++-inf:PASSED:fnmsub(-0x1.000000000000ep+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000011p+0
++-inf:PASSED:fnmsub(-0x1.000000000000fp+0, 0x1.2p+0 , 0x1.0000000000001p-1) = 0x1.a000000000012p+0
++-inf:PASSED:fnmsub(0x1p+0 , 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.ap+0
++-inf:PASSED:fnmsub(0x1.0000000000001p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000001p+0
++-inf:PASSED:fnmsub(0x1.0000000000002p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000002p+0
++-inf:PASSED:fnmsub(0x1.0000000000003p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000003p+0
++-inf:PASSED:fnmsub(0x1.0000000000004p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000005p+0
++-inf:PASSED:fnmsub(0x1.0000000000005p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000006p+0
++-inf:PASSED:fnmsub(0x1.0000000000006p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000007p+0
++-inf:PASSED:fnmsub(0x1.0000000000007p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000008p+0
++-inf:PASSED:fnmsub(0x1.0000000000008p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000009p+0
++-inf:PASSED:fnmsub(0x1.0000000000009p+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ap+0
++-inf:PASSED:fnmsub(0x1.000000000000ap+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000bp+0
++-inf:PASSED:fnmsub(0x1.000000000000bp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000cp+0
++-inf:PASSED:fnmsub(0x1.000000000000cp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000ep+0
++-inf:PASSED:fnmsub(0x1.000000000000dp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000000fp+0
++-inf:PASSED:fnmsub(0x1.000000000000ep+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a00000000001p+0
++-inf:PASSED:fnmsub(0x1.000000000000fp+0, 0x1.2p+0 , -0x1.0000000000001p-1) = -0x1.a000000000011p+0
++near:PASSED:fsqrt(0x1.a44p-1 ) = 0x1.cfdcaf353049ep-1
++near:PASSED:fsqrt(0x1.a822p+0 ) = 0x1.498302b49cd6dp+0
++near:PASSED:fsqrt(0x1.05a2p+0 ) = 0x1.02cd13b44f3bfp+0
++near:PASSED:fsqrt(0x1.9504p-1 ) = 0x1.c76073cec0937p-1
++near:PASSED:fsqrt(0x1.dca2p+0 ) = 0x1.5d4f8d4e4c2b2p+0
++near:PASSED:fsqrt(0x1.02c8p+0 ) = 0x1.016309cde7483p+0
++near:PASSED:fsqrt(0x1.b9p-1 ) = 0x1.db2cfe686fe7cp-1
++near:PASSED:fsqrt(0x1.1d02p+0 ) = 0x1.0e1d62e78ed9ep+0
++near:PASSED:fsqrt(0x1.c39p-1 ) = 0x1.e0d526020fb6cp-1
++near:PASSED:fsqrt(0x1.9p-1 ) = 0x1.c48c6001f0acp-1
++near:PASSED:fsqrt(0x1.4852p+0 ) = 0x1.21e9ed813e2e3p+0
++near:PASSED:fsqrt(0x1.e984p-1 ) = 0x1.f4a1b09bbf0b1p-1
++near:PASSED:fsqrt(0x1.9a1p-1 ) = 0x1.ca34879b907afp-1
++near:PASSED:fsqrt(0x1.76b2p+0 ) = 0x1.35b6781aed828p+0
++zero:PASSED:fsqrt(0x1.a44p-1 ) = 0x1.cfdcaf353049ep-1
++zero:PASSED:fsqrt(0x1.a822p+0 ) = 0x1.498302b49cd6dp+0
++zero:PASSED:fsqrt(0x1.05a2p+0 ) = 0x1.02cd13b44f3bfp+0
++zero:PASSED:fsqrt(0x1.9504p-1 ) = 0x1.c76073cec0937p-1
++zero:PASSED:fsqrt(0x1.dca2p+0 ) = 0x1.5d4f8d4e4c2b2p+0
++zero:PASSED:fsqrt(0x1.02c8p+0 ) = 0x1.016309cde7483p+0
++zero:PASSED:fsqrt(0x1.b9p-1 ) = 0x1.db2cfe686fe7cp-1
++zero:PASSED:fsqrt(0x1.1d02p+0 ) = 0x1.0e1d62e78ed9dp+0
++zero:PASSED:fsqrt(0x1.c39p-1 ) = 0x1.e0d526020fb6bp-1
++zero:PASSED:fsqrt(0x1.9p-1 ) = 0x1.c48c6001f0abfp-1
++zero:PASSED:fsqrt(0x1.4852p+0 ) = 0x1.21e9ed813e2e2p+0
++zero:PASSED:fsqrt(0x1.e984p-1 ) = 0x1.f4a1b09bbf0bp-1
++zero:PASSED:fsqrt(0x1.9a1p-1 ) = 0x1.ca34879b907aep-1
++zero:PASSED:fsqrt(0x1.76b2p+0 ) = 0x1.35b6781aed827p+0
+++inf:PASSED:fsqrt(0x1.a44p-1 ) = 0x1.cfdcaf353049fp-1
+++inf:PASSED:fsqrt(0x1.a822p+0 ) = 0x1.498302b49cd6ep+0
+++inf:PASSED:fsqrt(0x1.05a2p+0 ) = 0x1.02cd13b44f3cp+0
+++inf:PASSED:fsqrt(0x1.9504p-1 ) = 0x1.c76073cec0938p-1
+++inf:PASSED:fsqrt(0x1.dca2p+0 ) = 0x1.5d4f8d4e4c2b3p+0
+++inf:PASSED:fsqrt(0x1.02c8p+0 ) = 0x1.016309cde7484p+0
+++inf:PASSED:fsqrt(0x1.b9p-1 ) = 0x1.db2cfe686fe7dp-1
+++inf:PASSED:fsqrt(0x1.1d02p+0 ) = 0x1.0e1d62e78ed9ep+0
+++inf:PASSED:fsqrt(0x1.c39p-1 ) = 0x1.e0d526020fb6cp-1
+++inf:PASSED:fsqrt(0x1.9p-1 ) = 0x1.c48c6001f0acp-1
+++inf:PASSED:fsqrt(0x1.4852p+0 ) = 0x1.21e9ed813e2e3p+0
+++inf:PASSED:fsqrt(0x1.e984p-1 ) = 0x1.f4a1b09bbf0b1p-1
+++inf:PASSED:fsqrt(0x1.9a1p-1 ) = 0x1.ca34879b907afp-1
+++inf:PASSED:fsqrt(0x1.76b2p+0 ) = 0x1.35b6781aed828p+0
++-inf:PASSED:fsqrt(0x1.a44p-1 ) = 0x1.cfdcaf353049ep-1
++-inf:PASSED:fsqrt(0x1.a822p+0 ) = 0x1.498302b49cd6dp+0
++-inf:PASSED:fsqrt(0x1.05a2p+0 ) = 0x1.02cd13b44f3bfp+0
++-inf:PASSED:fsqrt(0x1.9504p-1 ) = 0x1.c76073cec0937p-1
++-inf:PASSED:fsqrt(0x1.dca2p+0 ) = 0x1.5d4f8d4e4c2b2p+0
++-inf:PASSED:fsqrt(0x1.02c8p+0 ) = 0x1.016309cde7483p+0
++-inf:PASSED:fsqrt(0x1.b9p-1 ) = 0x1.db2cfe686fe7cp-1
++-inf:PASSED:fsqrt(0x1.1d02p+0 ) = 0x1.0e1d62e78ed9dp+0
++-inf:PASSED:fsqrt(0x1.c39p-1 ) = 0x1.e0d526020fb6bp-1
++-inf:PASSED:fsqrt(0x1.9p-1 ) = 0x1.c48c6001f0abfp-1
++-inf:PASSED:fsqrt(0x1.4852p+0 ) = 0x1.21e9ed813e2e2p+0
++-inf:PASSED:fsqrt(0x1.e984p-1 ) = 0x1.f4a1b09bbf0bp-1
++-inf:PASSED:fsqrt(0x1.9a1p-1 ) = 0x1.ca34879b907aep-1
++-inf:PASSED:fsqrt(0x1.76b2p+0 ) = 0x1.35b6781aed827p+0
+diff --git a/none/tests/ppc64/std_reg_imm.stdout.exp-LE b/none/tests/ppc64/std_reg_imm.stdout.exp-LE
+new file mode 100644
+index 0000000..dec21ec
+--- /dev/null
++++ b/none/tests/ppc64/std_reg_imm.stdout.exp-LE
+@@ -0,0 +1 @@
++....8877665544332211............
+diff --git a/none/tests/ppc64/test_isa_2_06_part1.stdout.exp b/none/tests/ppc64/test_isa_2_06_part1.stdout.exp
+index d234f79..4def7c0 100644
+--- a/none/tests/ppc64/test_isa_2_06_part1.stdout.exp
++++ b/none/tests/ppc64/test_isa_2_06_part1.stdout.exp
+@@ -66,9 +66,9 @@ xxlandc: 00112233 44556677 8899aabb 91929394 xxlandc a1a2a3a4 b1b2b3b4 c1c2c3c4
+ xxlandc: 44556677 8899aabb 91929394 a1a2a3a4 xxlandc b1b2b3b4 c1c2c3c4 d1d2d3d4 7a6b5d3e => 44454443 0819283b 00000000 8180a280
+
+ Test ldbrx instruction
+-ldbrx: 01 23 45 67 89 ab cd (reverse) => ef cd ab 89 67 45 23 01
+-ldbrx: 89 ab cd ef 00 11 22 (reverse) => 33 22 11 00 ef cd ab 89
+-ldbrx: 00 11 22 33 44 55 66 (reverse) => 77 66 55 44 33 22 11 00
++ldbrx: 01 23 45 67 89 ab cd ef (reverse) => ef cd ab 89 67 45 23 01
++ldbrx: 89 ab cd ef 00 11 22 33 (reverse) => 33 22 11 00 ef cd ab 89
++ldbrx: 00 11 22 33 44 55 66 77 (reverse) => 77 66 55 44 33 22 11 00
+
+ Test popcntd instruction
+ popcntd: 0x9182736405504536 => 24
+@@ -138,13 +138,27 @@ ftdiv: 0000000000000000 <=> 0000000000000000 ? e (CRx)
+ ftdiv: 0000000000000000 <=> 8000000000000000 ? e (CRx)
+
+ Test VSX move instructions
+-xsabsdp: 01234567 89abcdef xsabsdp 8899aabb 91929394x => 0899aabb 91929394
++xsabsdp: X[B]: 0123456789abcdef => 0123456789abcdef
++xsabsdp: X[B]: 8899aabb19293942 => 0899aabb19293942
++xsabsdp: X[B]: c1c2c3c4d1d2d3d4 => 41c2c3c4d1d2d3d4
+
+-xscpsgndp: 8899aabb 91929394 xscpsgndp 01234567 89abcdefx => 81234567 89abcdef
++xscpsgndp: X[A]: 0123456789abcdef X[B]: 0123456789abcdef => 0123456789abcdef
++xscpsgndp: X[A]: 8899aabb19293942 X[B]: 0123456789abcdef => 8123456789abcdef
++xscpsgndp: X[A]: c1c2c3c4d1d2d3d4 X[B]: 0123456789abcdef => 8123456789abcdef
++xscpsgndp: X[A]: 0123456789abcdef X[B]: 8899aabb19293942 => 0899aabb19293942
++xscpsgndp: X[A]: 8899aabb19293942 X[B]: 8899aabb19293942 => 8899aabb19293942
++xscpsgndp: X[A]: c1c2c3c4d1d2d3d4 X[B]: 8899aabb19293942 => 8899aabb19293942
++xscpsgndp: X[A]: 0123456789abcdef X[B]: c1c2c3c4d1d2d3d4 => 41c2c3c4d1d2d3d4
++xscpsgndp: X[A]: 8899aabb19293942 X[B]: c1c2c3c4d1d2d3d4 => c1c2c3c4d1d2d3d4
++xscpsgndp: X[A]: c1c2c3c4d1d2d3d4 X[B]: c1c2c3c4d1d2d3d4 => c1c2c3c4d1d2d3d4
+
+-xsnabsdp: b1b2b3b4 c1c2c3c4 xsnabsdp 44556677 8899aabbx => c4556677 8899aabb
++xsnabsdp: X[B]: 0123456789abcdef => 8123456789abcdef
++xsnabsdp: X[B]: 8899aabb19293942 => 8899aabb19293942
++xsnabsdp: X[B]: c1c2c3c4d1d2d3d4 => c1c2c3c4d1d2d3d4
+
+-xsnegdp: 01234567 89abcdef xsnegdp b1b2b3b4 c1c2c3c4x => 31b2b3b4 c1c2c3c4
++xsnegdp: X[B]: 0123456789abcdef => 8123456789abcdef
++xsnegdp: X[B]: 8899aabb19293942 => 0899aabb19293942
++xsnegdp: X[B]: c1c2c3c4d1d2d3d4 => 41c2c3c4d1d2d3d4
+
+ Test VSX permute instructions
+ xxmrghw:
+@@ -1028,4 +1042,3 @@ Test VSX scalar integer conversion instructions
+ #14: xscvuxddp c0d0650f5a07b353 => 43e81a0ca1eb40f6
+
+
+-Testcase PASSED
+diff --git a/none/tests/ppc64/test_isa_2_06_part1.stdout.exp-LE b/none/tests/ppc64/test_isa_2_06_part1.stdout.exp-LE
+new file mode 100644
+index 0000000..9dc4666
+--- /dev/null
++++ b/none/tests/ppc64/test_isa_2_06_part1.stdout.exp-LE
+@@ -0,0 +1,1044 @@
++Test VSX load/store instructions
++lxsdx: 01234567 89abcdef => 01234567 89abcdef
++lxsdx: 8899aabb 91929394 => 8899aabb 91929394
++
++lxsdx: 01234567 89abcdef => 01234567 89abcdef
++lxsdx: 89abcdef 00112233 => 89abcdef 00112233
++lxsdx: 8899aabb 91929394 => 8899aabb 91929394
++lxsdx: 91929394 a1a2a3a4 => 91929394 a1a2a3a4
++
++lxvd2x: 01234567 89abcdef 00112233 44556677 => 00112233 44556677 01234567 89abcdef
++lxvd2x: 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => a1a2a3a4 b1b2b3b4 8899aabb 91929394
++
++lxvd2x: 01234567 89abcdef 00112233 44556677 => 00112233 44556677 01234567 89abcdef
++lxvd2x: 89abcdef 00112233 44556677 8899aabb => 44556677 8899aabb 89abcdef 00112233
++lxvd2x: 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => a1a2a3a4 b1b2b3b4 8899aabb 91929394
++lxvd2x: 91929394 a1a2a3a4 b1b2b3b4 c1c2c3c4 => b1b2b3b4 c1c2c3c4 91929394 a1a2a3a4
++
++lxvdsx: 01234567 89abcdef 01234567 89abcdef => 01234567 89abcdef 01234567 89abcdef
++lxvdsx: 8899aabb 91929394 8899aabb 91929394 => 8899aabb 91929394 8899aabb 91929394
++
++lxvdsx: 01234567 89abcdef 01234567 89abcdef => 01234567 89abcdef 01234567 89abcdef
++lxvdsx: 89abcdef 00112233 89abcdef 00112233 => 89abcdef 00112233 89abcdef 00112233
++lxvdsx: 8899aabb 91929394 8899aabb 91929394 => 8899aabb 91929394 8899aabb 91929394
++lxvdsx: 91929394 a1a2a3a4 91929394 a1a2a3a4 => 91929394 a1a2a3a4 91929394 a1a2a3a4
++
++lxvw4x: 01234567 89abcdef 00112233 44556677 => 44556677 00112233 89abcdef 01234567
++lxvw4x: 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => b1b2b3b4 a1a2a3a4 91929394 8899aabb
++
++lxvw4x: 01234567 89abcdef 00112233 44556677 => 44556677 00112233 89abcdef 01234567
++lxvw4x: 89abcdef 00112233 44556677 8899aabb => 8899aabb 44556677 00112233 89abcdef
++lxvw4x: 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => b1b2b3b4 a1a2a3a4 91929394 8899aabb
++lxvw4x: 91929394 a1a2a3a4 b1b2b3b4 c1c2c3c4 => c1c2c3c4 b1b2b3b4 a1a2a3a4 91929394
++
++stxsdx: 01234567 89abcdef => 00112233 44556677
++
++stxsdx: 01234567 89abcdef => 00112233 44556677
++
++stxvd2x: 01234567 89abcdef 00112233 44556677 => 00112233 44556677 01234567 89abcdef
++
++stxvd2x: 01234567 89abcdef 00112233 44556677 => 00112233 44556677 01234567 89abcdef
++
++stxvw4x: 01234567 89abcdef 00112233 44556677 => 44556677 00112233 89abcdef 01234567
++
++stxvw4x: 01234567 89abcdef 00112233 44556677 => 44556677 00112233 89abcdef 01234567
++
++Test VSX logic instructions
++xxlxor: 01234567 89abcdef 00112233 44556677 xxlxor 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => 89baefdc 18395e7b a1b38197 f5e7d5c3
++xxlxor: 89abcdef 00112233 44556677 8899aabb xxlxor 91929394 a1a2a3a4 b1b2b3b4 c1c2c3c4 => 18395e7b a1b38197 f5e7d5c3 495b697f
++xxlxor: 00112233 44556677 8899aabb 91929394 xxlxor a1a2a3a4 b1b2b3b4 c1c2c3c4 d1d2d3d4 => a1b38197 f5e7d5c3 495b697f 40404040
++xxlxor: 44556677 8899aabb 91929394 a1a2a3a4 xxlxor b1b2b3b4 c1c2c3c4 d1d2d3d4 7a6b5d3e => f5e7d5c3 495b697f 40404040 dbc9fe9a
++xxlor: 01234567 89abcdef 00112233 44556677 xxlor 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => 89bbefff 99bbdfff a1b3a3b7 f5f7f7f7
++xxlor: 89abcdef 00112233 44556677 8899aabb xxlor 91929394 a1a2a3a4 b1b2b3b4 c1c2c3c4 => 99bbdfff a1b3a3b7 f5f7f7f7 c9dbebff
++xxlor: 00112233 44556677 8899aabb 91929394 xxlor a1a2a3a4 b1b2b3b4 c1c2c3c4 d1d2d3d4 => a1b3a3b7 f5f7f7f7 c9dbebff d1d2d3d4
++xxlor: 44556677 8899aabb 91929394 a1a2a3a4 xxlor b1b2b3b4 c1c2c3c4 d1d2d3d4 7a6b5d3e => f5f7f7f7 c9dbebff d1d2d3d4 fbebffbe
++xxlnor: 01234567 89abcdef 00112233 44556677 xxlnor 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => 76441000 66442000 5e4c5c48 0a080808
++xxlnor: 89abcdef 00112233 44556677 8899aabb xxlnor 91929394 a1a2a3a4 b1b2b3b4 c1c2c3c4 => 66442000 5e4c5c48 0a080808 36241400
++xxlnor: 00112233 44556677 8899aabb 91929394 xxlnor a1a2a3a4 b1b2b3b4 c1c2c3c4 d1d2d3d4 => 5e4c5c48 0a080808 36241400 2e2d2c2b
++xxlnor: 44556677 8899aabb 91929394 a1a2a3a4 xxlnor b1b2b3b4 c1c2c3c4 d1d2d3d4 7a6b5d3e => 0a080808 36241400 2e2d2c2b 04140041
++xxland: 01234567 89abcdef 00112233 44556677 xxland 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => 00010023 81828184 00002220 00102234
++xxland: 89abcdef 00112233 44556677 8899aabb xxland 91929394 a1a2a3a4 b1b2b3b4 c1c2c3c4 => 81828184 00002220 00102234 80808280
++xxland: 00112233 44556677 8899aabb 91929394 xxland a1a2a3a4 b1b2b3b4 c1c2c3c4 d1d2d3d4 => 00002220 00102234 80808280 91929394
++xxland: 44556677 8899aabb 91929394 a1a2a3a4 xxland b1b2b3b4 c1c2c3c4 d1d2d3d4 7a6b5d3e => 00102234 80808280 91929394 20220124
++xxlandc: 01234567 89abcdef 00112233 44556677 xxlandc 8899aabb 91929394 a1a2a3a4 b1b2b3b4 => 01224544 08294c6b 00110013 44454443
++xxlandc: 89abcdef 00112233 44556677 8899aabb xxlandc 91929394 a1a2a3a4 b1b2b3b4 c1c2c3c4 => 08294c6b 00110013 44454443 0819283b
++xxlandc: 00112233 44556677 8899aabb 91929394 xxlandc a1a2a3a4 b1b2b3b4 c1c2c3c4 d1d2d3d4 => 00110013 44454443 0819283b 00000000
++xxlandc: 44556677 8899aabb 91929394 a1a2a3a4 xxlandc b1b2b3b4 c1c2c3c4 d1d2d3d4 7a6b5d3e => 44454443 0819283b 00000000 8180a280
++
++Test ldbrx instruction
++ldbrx: 67 45 23 01 ef cd ab 89 (reverse) => 89 ab cd ef 01 23 45 67
++ldbrx: ef cd ab 89 33 22 11 00 (reverse) => 00 11 22 33 89 ab cd ef
++ldbrx: 33 22 11 00 77 66 55 44 (reverse) => 44 55 66 77 00 11 22 33
++
++Test popcntd instruction
++popcntd: 0x9182736405504536 => 24
++
++Test lfiwzx instruction
++lfiwzx: 19088743 => 19088743.00
++lfiwzx: 2309737967 => 2309737967.00
++lfiwzx: 1122867 => 1122867.00
++
++Test P7 floating point convert instructions
++fcfids 0010000000000001 => (raw sp) 59800000)
++fcfids 00100094e0000359 => (raw sp) 598004a7)
++fcfids 3fe0000000000001 => (raw sp) 5e7f8000)
++fcfids 3fe00094e0000359 => (raw sp) 5e7f8002)
++fcfids 8010000000000001 => (raw sp) deffe000)
++fcfids 80100094e0000359 => (raw sp) deffdfff)
++fcfids bfe0000000000001 => (raw sp) de804000)
++fcfids bfe00094e0000359 => (raw sp) de803fff)
++fcfids 0020000000000b01 => (raw sp) 5a000000)
++fcfids 00000000203f0b3d => (raw sp) 4e00fc2d)
++fcfids 00000000005a203d => (raw sp) 4ab4407a)
++fcfids 8020000000000b01 => (raw sp) deffc000)
++fcfids 80000000203f0b3d => (raw sp) df000000)
++
++fcfidus 0010000000000001 => (raw sp) 59800000)
++fcfidus 00100094e0000359 => (raw sp) 598004a7)
++fcfidus 3fe0000000000001 => (raw sp) 5e7f8000)
++fcfidus 3fe00094e0000359 => (raw sp) 5e7f8002)
++fcfidus 8010000000000001 => (raw sp) 5f001000)
++fcfidus 80100094e0000359 => (raw sp) 5f001001)
++fcfidus bfe0000000000001 => (raw sp) 5f3fe000)
++fcfidus bfe00094e0000359 => (raw sp) 5f3fe001)
++fcfidus 0020000000000b01 => (raw sp) 5a000000)
++fcfidus 00000000203f0b3d => (raw sp) 4e00fc2d)
++fcfidus 00000000005a203d => (raw sp) 4ab4407a)
++fcfidus 8020000000000b01 => (raw sp) 5f002000)
++fcfidus 80000000203f0b3d => (raw sp) 5f000000)
++
++fcfidu 0010000000000001 => (raw sp) 4330000000000001)
++fcfidu 00100094e0000359 => (raw sp) 43300094e0000359)
++fcfidu 3fe0000000000001 => (raw sp) 43cff00000000000)
++fcfidu 3fe00094e0000359 => (raw sp) 43cff0004a700002)
++fcfidu 8010000000000001 => (raw sp) 43e0020000000000)
++fcfidu 80100094e0000359 => (raw sp) 43e00200129c0000)
++fcfidu bfe0000000000001 => (raw sp) 43e7fc0000000000)
++fcfidu bfe00094e0000359 => (raw sp) 43e7fc00129c0000)
++fcfidu 0020000000000b01 => (raw sp) 4340000000000580)
++fcfidu 00000000203f0b3d => (raw sp) 41c01f859e800000)
++fcfidu 00000000005a203d => (raw sp) 4156880f40000000)
++fcfidu 8020000000000b01 => (raw sp) 43e0040000000001)
++fcfidu 80000000203f0b3d => (raw sp) 43e00000000407e1)
++
++Test ftdiv instruction
++ftdiv: 3fd8000000000000 <=> 404f000000000000 ? 8 (CRx)
++ftdiv: 7ff7ffffffffffff <=> 404f000000000000 ? a (CRx)
++ftdiv: 404f000000000000 <=> fff8000000000000 ? a (CRx)
++ftdiv: 3fd8000000000000 <=> 0018000000b77501 ? a (CRx)
++ftdiv: 404f000000000000 <=> 7fe800000000051b ? a (CRx)
++ftdiv: 7fe800000000051b <=> 3fd8000000000000 ? a (CRx)
++ftdiv: 3fd8000000000000 <=> 7fe800000000051b ? a (CRx)
++ftdiv: 0123214569900000 <=> 3fd8000000000000 ? a (CRx)
++ftdiv: 7ff0000000000000 <=> 404f000000000000 ? e (CRx)
++ftdiv: fff0000000000000 <=> 404f000000000000 ? e (CRx)
++ftdiv: 404f000000000000 <=> 7ff0000000000000 ? e (CRx)
++ftdiv: 3fd8000000000000 <=> 8008340000078000 ? e (CRx)
++ftdiv: 0000000000000000 <=> 0000000000000000 ? e (CRx)
++ftdiv: 0000000000000000 <=> 8000000000000000 ? e (CRx)
++
++Test VSX move instructions
++xsabsdp: X[B]: 0011223344556677 => 0011223344556677
++xsabsdp: X[B]: a1a2a3a4b1b2b3b4 => 21a2a3a4b1b2b3b4
++xsabsdp: X[B]: 7a6b5d3efc032778 => 7a6b5d3efc032778
++
++xscpsgndp: X[A]: 0011223344556677 X[B]: 0011223344556677 => 0011223344556677
++xscpsgndp: X[A]: a1a2a3a4b1b2b3b4 X[B]: 0011223344556677 => 8011223344556677
++xscpsgndp: X[A]: 7a6b5d3efc032778 X[B]: 0011223344556677 => 0011223344556677
++xscpsgndp: X[A]: 0011223344556677 X[B]: a1a2a3a4b1b2b3b4 => 21a2a3a4b1b2b3b4
++xscpsgndp: X[A]: a1a2a3a4b1b2b3b4 X[B]: a1a2a3a4b1b2b3b4 => a1a2a3a4b1b2b3b4
++xscpsgndp: X[A]: 7a6b5d3efc032778 X[B]: a1a2a3a4b1b2b3b4 => 21a2a3a4b1b2b3b4
++xscpsgndp: X[A]: 0011223344556677 X[B]: 7a6b5d3efc032778 => 7a6b5d3efc032778
++xscpsgndp: X[A]: a1a2a3a4b1b2b3b4 X[B]: 7a6b5d3efc032778 => fa6b5d3efc032778
++xscpsgndp: X[A]: 7a6b5d3efc032778 X[B]: 7a6b5d3efc032778 => 7a6b5d3efc032778
++
++xsnabsdp: X[B]: 0011223344556677 => 8011223344556677
++xsnabsdp: X[B]: a1a2a3a4b1b2b3b4 => a1a2a3a4b1b2b3b4
++xsnabsdp: X[B]: 7a6b5d3efc032778 => fa6b5d3efc032778
++
++xsnegdp: X[B]: 0011223344556677 => 8011223344556677
++xsnegdp: X[B]: a1a2a3a4b1b2b3b4 => 21a2a3a4b1b2b3b4
++xsnegdp: X[B]: 7a6b5d3efc032778 => fa6b5d3efc032778
++
++Test VSX permute instructions
++xxmrghw:
++ XA[11111111,22222222,33333333,44444444]
++ XB[55555555,66666666,77777777,88888888]
++ => XT[77777777,33333333,88888888,44444444]
++xxmrghw:
++ XA[00112233,44556677,8899aabb,ccddeeff]
++ XB[11111111,22222222,33333333,44444444]
++ => XT[33333333,8899aabb,44444444,ccddeeff]
++xxmrglw:
++ XA[11111111,22222222,33333333,44444444]
++ XB[55555555,66666666,77777777,88888888]
++ => XT[55555555,11111111,66666666,22222222]
++xxmrglw:
++ XA[00112233,44556677,8899aabb,ccddeeff]
++ XB[11111111,22222222,33333333,44444444]
++ => XT[11111111,00112233,22222222,44556677]
++xxpermdi DM=00:
++ XA[11111111,22222222,33333333,44444444]
++ XB[55555555,66666666,77777777,88888888]
++ => XT[77777777,88888888,33333333,44444444]
++xxpermdi DM=01:
++ XA[11111111,22222222,33333333,44444444]
++ XB[55555555,66666666,77777777,88888888]
++ => XT[55555555,66666666,33333333,44444444]
++xxpermdi DM=10:
++ XA[11111111,22222222,33333333,44444444]
++ XB[55555555,66666666,77777777,88888888]
++ => XT[77777777,88888888,11111111,22222222]
++xxpermdi DM=11:
++ XA[11111111,22222222,33333333,44444444]
++ XB[55555555,66666666,77777777,88888888]
++ => XT[55555555,66666666,11111111,22222222]
++xxsldwi SHW=0:
++ XA[11111111,22222222,33333333,44444444]
++ XB[55555555,66666666,77777777,88888888]
++ => XT[11111111,22222222,33333333,44444444]
++xxsldwi SHW=1:
++ XA[11111111,22222222,33333333,44444444]
++ XB[55555555,66666666,77777777,88888888]
++ => XT[88888888,11111111,22222222,33333333]
++xxsldwi SHW=2:
++ XA[11111111,22222222,33333333,44444444]
++ XB[55555555,66666666,77777777,88888888]
++ => XT[77777777,88888888,11111111,22222222]
++xxsldwi SHW=3:
++ XA[11111111,22222222,33333333,44444444]
++ XB[55555555,66666666,77777777,88888888]
++ => XT[66666666,77777777,88888888,11111111]
++
++Test VSX floating point instructions
++#0: xscmpudp fff0000000000000 <=> fff0000000000000 ? 2 (CRx)
++#1: xscmpudp fff0000000000000 <=> c0d0650f5a07b353 ? 8 (CRx)
++#2: xscmpudp fff0000000000000 <=> 8000000000000000 ? 8 (CRx)
++#3: xscmpudp fff0000000000000 <=> 0000000000000000 ? 8 (CRx)
++#4: xscmpudp fff0000000000000 <=> 0123214569900000 ? 8 (CRx)
++#5: xscmpudp fff0000000000000 <=> 7ff0000000000000 ? 8 (CRx)
++#6: xscmpudp fff0000000000000 <=> 7ff7ffffffffffff ? 1 (CRx)
++#7: xscmpudp fff0000000000000 <=> 7ff8000000000000 ? 1 (CRx)
++#8: xscmpudp c0d0650f5a07b353 <=> fff0000000000000 ? 4 (CRx)
++#9: xscmpudp c0d0650f5a07b353 <=> c0d0650f5a07b353 ? 2 (CRx)
++#10: xscmpudp c0d0650f5a07b353 <=> 8000000000000000 ? 8 (CRx)
++#11: xscmpudp c0d0650f5a07b353 <=> 0000000000000000 ? 8 (CRx)
++#12: xscmpudp c0d0650f5a07b353 <=> 0123214569900000 ? 8 (CRx)
++#13: xscmpudp c0d0650f5a07b353 <=> 7ff0000000000000 ? 8 (CRx)
++#14: xscmpudp c0d0650f5a07b353 <=> 7ff7ffffffffffff ? 1 (CRx)
++#15: xscmpudp c0d0650f5a07b353 <=> 7ff8000000000000 ? 1 (CRx)
++#16: xscmpudp 8000000000000000 <=> fff0000000000000 ? 4 (CRx)
++#17: xscmpudp 8000000000000000 <=> c0d0650f5a07b353 ? 4 (CRx)
++#18: xscmpudp 8000000000000000 <=> 8000000000000000 ? 2 (CRx)
++#19: xscmpudp 8000000000000000 <=> 0000000000000000 ? 2 (CRx)
++#20: xscmpudp 8000000000000000 <=> 0123214569900000 ? 8 (CRx)
++#21: xscmpudp 8000000000000000 <=> 7ff0000000000000 ? 8 (CRx)
++#22: xscmpudp 8000000000000000 <=> 7ff7ffffffffffff ? 1 (CRx)
++#23: xscmpudp 8000000000000000 <=> 7ff8000000000000 ? 1 (CRx)
++#24: xscmpudp 0000000000000000 <=> fff0000000000000 ? 4 (CRx)
++#25: xscmpudp 0000000000000000 <=> c0d0650f5a07b353 ? 4 (CRx)
++#26: xscmpudp 0000000000000000 <=> 8000000000000000 ? 2 (CRx)
++#27: xscmpudp 0000000000000000 <=> 0000000000000000 ? 2 (CRx)
++#28: xscmpudp 0000000000000000 <=> 0123214569900000 ? 8 (CRx)
++#29: xscmpudp 0000000000000000 <=> 7ff0000000000000 ? 8 (CRx)
++#30: xscmpudp 0000000000000000 <=> 7ff7ffffffffffff ? 1 (CRx)
++#31: xscmpudp 0000000000000000 <=> 7ff8000000000000 ? 1 (CRx)
++#32: xscmpudp 0123214569900000 <=> fff0000000000000 ? 4 (CRx)
++#33: xscmpudp 0123214569900000 <=> c0d0650f5a07b353 ? 4 (CRx)
++#34: xscmpudp 0123214569900000 <=> 8000000000000000 ? 4 (CRx)
++#35: xscmpudp 0123214569900000 <=> 0000000000000000 ? 4 (CRx)
++#36: xscmpudp 0123214569900000 <=> 404f000000000000 ? 8 (CRx)
++#37: xscmpudp 0123214569900000 <=> 7ff0000000000000 ? 8 (CRx)
++#38: xscmpudp 0123214569900000 <=> 7ff7ffffffffffff ? 1 (CRx)
++#39: xscmpudp 0123214569900000 <=> 7ff8000000000000 ? 1 (CRx)
++#40: xscmpudp 7ff0000000000000 <=> fff0000000000000 ? 4 (CRx)
++#41: xscmpudp 7ff0000000000000 <=> c0d0650f5a07b353 ? 4 (CRx)
++#42: xscmpudp 7ff0000000000000 <=> 8000000000000000 ? 4 (CRx)
++#43: xscmpudp 7ff0000000000000 <=> 0000000000000000 ? 4 (CRx)
++#44: xscmpudp 7ff0000000000000 <=> 0123214569900000 ? 4 (CRx)
++#45: xscmpudp 7ff0000000000000 <=> 7ff0000000000000 ? 2 (CRx)
++#46: xscmpudp 7ff0000000000000 <=> 7ff7ffffffffffff ? 1 (CRx)
++#47: xscmpudp 7ff0000000000000 <=> 7ff8000000000000 ? 1 (CRx)
++#48: xscmpudp fff7ffffffffffff <=> fff0000000000000 ? 1 (CRx)
++#49: xscmpudp fff7ffffffffffff <=> c0d0650f5a07b353 ? 1 (CRx)
++#50: xscmpudp fff7ffffffffffff <=> 8000000000000000 ? 1 (CRx)
++#51: xscmpudp fff7ffffffffffff <=> 0000000000000000 ? 1 (CRx)
++#52: xscmpudp fff7ffffffffffff <=> 0123214569900000 ? 1 (CRx)
++#53: xscmpudp fff7ffffffffffff <=> 7ff0000000000000 ? 1 (CRx)
++#54: xscmpudp fff7ffffffffffff <=> 7ff7ffffffffffff ? 1 (CRx)
++#55: xscmpudp fff7ffffffffffff <=> 7ff8000000000000 ? 1 (CRx)
++#56: xscmpudp fff8000000000000 <=> fff0000000000000 ? 1 (CRx)
++#57: xscmpudp fff8000000000000 <=> c0d0650f5a07b353 ? 1 (CRx)
++#58: xscmpudp fff8000000000000 <=> 8000000000000000 ? 1 (CRx)
++#59: xscmpudp fff8000000000000 <=> 0000000000000000 ? 1 (CRx)
++#60: xscmpudp fff8000000000000 <=> 0123214569900000 ? 1 (CRx)
++#61: xscmpudp fff8000000000000 <=> 7ff0000000000000 ? 1 (CRx)
++#62: xscmpudp fff8000000000000 <=> 7ff7ffffffffffff ? 1 (CRx)
++#63: xscmpudp fff8000000000000 <=> 7ff8000000000000 ? 1 (CRx)
++
++#0: xscmpodp fff0000000000000 <=> fff0000000000000 ? 2 (CRx)
++#1: xscmpodp fff0000000000000 <=> c0d0650f5a07b353 ? 8 (CRx)
++#2: xscmpodp fff0000000000000 <=> 8000000000000000 ? 8 (CRx)
++#3: xscmpodp fff0000000000000 <=> 0000000000000000 ? 8 (CRx)
++#4: xscmpodp fff0000000000000 <=> 0123214569900000 ? 8 (CRx)
++#5: xscmpodp fff0000000000000 <=> 7ff0000000000000 ? 8 (CRx)
++#6: xscmpodp fff0000000000000 <=> 7ff7ffffffffffff ? 1 (CRx)
++#7: xscmpodp fff0000000000000 <=> 7ff8000000000000 ? 1 (CRx)
++#8: xscmpodp c0d0650f5a07b353 <=> fff0000000000000 ? 4 (CRx)
++#9: xscmpodp c0d0650f5a07b353 <=> c0d0650f5a07b353 ? 2 (CRx)
++#10: xscmpodp c0d0650f5a07b353 <=> 8000000000000000 ? 8 (CRx)
++#11: xscmpodp c0d0650f5a07b353 <=> 0000000000000000 ? 8 (CRx)
++#12: xscmpodp c0d0650f5a07b353 <=> 0123214569900000 ? 8 (CRx)
++#13: xscmpodp c0d0650f5a07b353 <=> 7ff0000000000000 ? 8 (CRx)
++#14: xscmpodp c0d0650f5a07b353 <=> 7ff7ffffffffffff ? 1 (CRx)
++#15: xscmpodp c0d0650f5a07b353 <=> 7ff8000000000000 ? 1 (CRx)
++#16: xscmpodp 8000000000000000 <=> fff0000000000000 ? 4 (CRx)
++#17: xscmpodp 8000000000000000 <=> c0d0650f5a07b353 ? 4 (CRx)
++#18: xscmpodp 8000000000000000 <=> 8000000000000000 ? 2 (CRx)
++#19: xscmpodp 8000000000000000 <=> 0000000000000000 ? 2 (CRx)
++#20: xscmpodp 8000000000000000 <=> 0123214569900000 ? 8 (CRx)
++#21: xscmpodp 8000000000000000 <=> 7ff0000000000000 ? 8 (CRx)
++#22: xscmpodp 8000000000000000 <=> 7ff7ffffffffffff ? 1 (CRx)
++#23: xscmpodp 8000000000000000 <=> 7ff8000000000000 ? 1 (CRx)
++#24: xscmpodp 0000000000000000 <=> fff0000000000000 ? 4 (CRx)
++#25: xscmpodp 0000000000000000 <=> c0d0650f5a07b353 ? 4 (CRx)
++#26: xscmpodp 0000000000000000 <=> 8000000000000000 ? 2 (CRx)
++#27: xscmpodp 0000000000000000 <=> 0000000000000000 ? 2 (CRx)
++#28: xscmpodp 0000000000000000 <=> 0123214569900000 ? 8 (CRx)
++#29: xscmpodp 0000000000000000 <=> 7ff0000000000000 ? 8 (CRx)
++#30: xscmpodp 0000000000000000 <=> 7ff7ffffffffffff ? 1 (CRx)
++#31: xscmpodp 0000000000000000 <=> 7ff8000000000000 ? 1 (CRx)
++#32: xscmpodp 0123214569900000 <=> fff0000000000000 ? 4 (CRx)
++#33: xscmpodp 0123214569900000 <=> c0d0650f5a07b353 ? 4 (CRx)
++#34: xscmpodp 0123214569900000 <=> 8000000000000000 ? 4 (CRx)
++#35: xscmpodp 0123214569900000 <=> 0000000000000000 ? 4 (CRx)
++#36: xscmpodp 0123214569900000 <=> 404f000000000000 ? 8 (CRx)
++#37: xscmpodp 0123214569900000 <=> 7ff0000000000000 ? 8 (CRx)
++#38: xscmpodp 0123214569900000 <=> 7ff7ffffffffffff ? 1 (CRx)
++#39: xscmpodp 0123214569900000 <=> 7ff8000000000000 ? 1 (CRx)
++#40: xscmpodp 7ff0000000000000 <=> fff0000000000000 ? 4 (CRx)
++#41: xscmpodp 7ff0000000000000 <=> c0d0650f5a07b353 ? 4 (CRx)
++#42: xscmpodp 7ff0000000000000 <=> 8000000000000000 ? 4 (CRx)
++#43: xscmpodp 7ff0000000000000 <=> 0000000000000000 ? 4 (CRx)
++#44: xscmpodp 7ff0000000000000 <=> 0123214569900000 ? 4 (CRx)
++#45: xscmpodp 7ff0000000000000 <=> 7ff0000000000000 ? 2 (CRx)
++#46: xscmpodp 7ff0000000000000 <=> 7ff7ffffffffffff ? 1 (CRx)
++#47: xscmpodp 7ff0000000000000 <=> 7ff8000000000000 ? 1 (CRx)
++#48: xscmpodp fff7ffffffffffff <=> fff0000000000000 ? 1 (CRx)
++#49: xscmpodp fff7ffffffffffff <=> c0d0650f5a07b353 ? 1 (CRx)
++#50: xscmpodp fff7ffffffffffff <=> 8000000000000000 ? 1 (CRx)
++#51: xscmpodp fff7ffffffffffff <=> 0000000000000000 ? 1 (CRx)
++#52: xscmpodp fff7ffffffffffff <=> 0123214569900000 ? 1 (CRx)
++#53: xscmpodp fff7ffffffffffff <=> 7ff0000000000000 ? 1 (CRx)
++#54: xscmpodp fff7ffffffffffff <=> 7ff7ffffffffffff ? 1 (CRx)
++#55: xscmpodp fff7ffffffffffff <=> 7ff8000000000000 ? 1 (CRx)
++#56: xscmpodp fff8000000000000 <=> fff0000000000000 ? 1 (CRx)
++#57: xscmpodp fff8000000000000 <=> c0d0650f5a07b353 ? 1 (CRx)
++#58: xscmpodp fff8000000000000 <=> 8000000000000000 ? 1 (CRx)
++#59: xscmpodp fff8000000000000 <=> 0000000000000000 ? 1 (CRx)
++#60: xscmpodp fff8000000000000 <=> 0123214569900000 ? 1 (CRx)
++#61: xscmpodp fff8000000000000 <=> 7ff0000000000000 ? 1 (CRx)
++#62: xscmpodp fff8000000000000 <=> 7ff7ffffffffffff ? 1 (CRx)
++#63: xscmpodp fff8000000000000 <=> 7ff8000000000000 ? 1 (CRx)
++
++#0: xsadddp fff0000000000000 fff0000000000000 = fff0000000000000
++#1: xsadddp fff0000000000000 c0d0650f5a07b353 = fff0000000000000
++#2: xsadddp fff0000000000000 8000000000000000 = fff0000000000000
++#3: xsadddp fff0000000000000 0000000000000000 = fff0000000000000
++#4: xsadddp fff0000000000000 0123214569900000 = fff0000000000000
++#5: xsadddp fff0000000000000 7ff0000000000000 = 7ff8000000000000
++#6: xsadddp fff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
++#7: xsadddp fff0000000000000 7ff8000000000000 = 7ff8000000000000
++#8: xsadddp c0d0650f5a07b353 fff0000000000000 = fff0000000000000
++#9: xsadddp c0d0650f5a07b353 c0d0650f5a07b353 = c0e0650f5a07b353
++#10: xsadddp c0d0650f5a07b353 8000000000000000 = c0d0650f5a07b353
++#11: xsadddp c0d0650f5a07b353 0000000000000000 = c0d0650f5a07b353
++#12: xsadddp c0d0650f5a07b353 0123214569900000 = c0d0650f5a07b353
++#13: xsadddp c0d0650f5a07b353 7ff0000000000000 = 7ff0000000000000
++#14: xsadddp c0d0650f5a07b353 7ff7ffffffffffff = 7fffffffffffffff
++#15: xsadddp c0d0650f5a07b353 7ff8000000000000 = 7ff8000000000000
++#16: xsadddp 8000000000000000 fff0000000000000 = fff0000000000000
++#17: xsadddp 8000000000000000 c0d0650f5a07b353 = c0d0650f5a07b353
++#18: xsadddp 8000000000000000 8000000000000000 = 8000000000000000
++#19: xsadddp 8000000000000000 0000000000000000 = 0000000000000000
++#20: xsadddp 8000000000000000 0123214569900000 = 0123214569900000
++#21: xsadddp 8000000000000000 7ff0000000000000 = 7ff0000000000000
++#22: xsadddp 8000000000000000 7ff7ffffffffffff = 7fffffffffffffff
++#23: xsadddp 8000000000000000 7ff8000000000000 = 7ff8000000000000
++#24: xsadddp 0000000000000000 fff0000000000000 = fff0000000000000
++#25: xsadddp 0000000000000000 c0d0650f5a07b353 = c0d0650f5a07b353
++#26: xsadddp 0000000000000000 8000000000000000 = 0000000000000000
++#27: xsadddp 0000000000000000 0000000000000000 = 0000000000000000
++#28: xsadddp 0000000000000000 0123214569900000 = 0123214569900000
++#29: xsadddp 0000000000000000 7ff0000000000000 = 7ff0000000000000
++#30: xsadddp 0000000000000000 7ff7ffffffffffff = 7fffffffffffffff
++#31: xsadddp 0000000000000000 7ff8000000000000 = 7ff8000000000000
++#32: xsadddp 0123214569900000 fff0000000000000 = fff0000000000000
++#33: xsadddp 0123214569900000 c0d0650f5a07b353 = c0d0650f5a07b353
++#34: xsadddp 0123214569900000 8000000000000000 = 0123214569900000
++#35: xsadddp 0123214569900000 0000000000000000 = 0123214569900000
++#36: xsadddp 0123214569900000 404f000000000000 = 404f000000000000
++#37: xsadddp 0123214569900000 7ff0000000000000 = 7ff0000000000000
++#38: xsadddp 0123214569900000 7ff7ffffffffffff = 7fffffffffffffff
++#39: xsadddp 0123214569900000 7ff8000000000000 = 7ff8000000000000
++#40: xsadddp 7ff0000000000000 fff0000000000000 = 7ff8000000000000
++#41: xsadddp 7ff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
++#42: xsadddp 7ff0000000000000 8000000000000000 = 7ff0000000000000
++#43: xsadddp 7ff0000000000000 0000000000000000 = 7ff0000000000000
++#44: xsadddp 7ff0000000000000 0123214569900000 = 7ff0000000000000
++#45: xsadddp 7ff0000000000000 7ff0000000000000 = 7ff0000000000000
++#46: xsadddp 7ff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
++#47: xsadddp 7ff0000000000000 7ff8000000000000 = 7ff8000000000000
++#48: xsadddp fff7ffffffffffff fff0000000000000 = ffffffffffffffff
++#49: xsadddp fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
++#50: xsadddp fff7ffffffffffff 8000000000000000 = ffffffffffffffff
++#51: xsadddp fff7ffffffffffff 0000000000000000 = ffffffffffffffff
++#52: xsadddp fff7ffffffffffff 0123214569900000 = ffffffffffffffff
++#53: xsadddp fff7ffffffffffff 7ff0000000000000 = ffffffffffffffff
++#54: xsadddp fff7ffffffffffff 7ff7ffffffffffff = ffffffffffffffff
++#55: xsadddp fff7ffffffffffff 7ff8000000000000 = ffffffffffffffff
++#56: xsadddp fff8000000000000 fff0000000000000 = fff8000000000000
++#57: xsadddp fff8000000000000 c0d0650f5a07b353 = fff8000000000000
++#58: xsadddp fff8000000000000 8000000000000000 = fff8000000000000
++#59: xsadddp fff8000000000000 0000000000000000 = fff8000000000000
++#60: xsadddp fff8000000000000 0123214569900000 = fff8000000000000
++#61: xsadddp fff8000000000000 7ff0000000000000 = fff8000000000000
++#62: xsadddp fff8000000000000 7ff7ffffffffffff = fff8000000000000
++#63: xsadddp fff8000000000000 7ff8000000000000 = fff8000000000000
++
++#0: xsdivdp fff0000000000000 fff0000000000000 = 7ff8000000000000
++#1: xsdivdp fff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
++#2: xsdivdp fff0000000000000 8000000000000000 = 7ff0000000000000
++#3: xsdivdp fff0000000000000 0000000000000000 = fff0000000000000
++#4: xsdivdp fff0000000000000 0123214569900000 = fff0000000000000
++#5: xsdivdp fff0000000000000 7ff0000000000000 = 7ff8000000000000
++#6: xsdivdp fff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
++#7: xsdivdp fff0000000000000 7ff8000000000000 = 7ff8000000000000
++#8: xsdivdp c0d0650f5a07b353 fff0000000000000 = 0000000000000000
++#9: xsdivdp c0d0650f5a07b353 c0d0650f5a07b353 = 3ff0000000000000
++#10: xsdivdp c0d0650f5a07b353 8000000000000000 = 7ff0000000000000
++#11: xsdivdp c0d0650f5a07b353 0000000000000000 = fff0000000000000
++#12: xsdivdp c0d0650f5a07b353 0123214569900000 = ff9b6cb57ca13c00
++#13: xsdivdp c0d0650f5a07b353 7ff0000000000000 = 8000000000000000
++#14: xsdivdp c0d0650f5a07b353 7ff7ffffffffffff = 7fffffffffffffff
++#15: xsdivdp c0d0650f5a07b353 7ff8000000000000 = 7ff8000000000000
++#16: xsdivdp 8000000000000000 fff0000000000000 = 0000000000000000
++#17: xsdivdp 8000000000000000 c0d0650f5a07b353 = 0000000000000000
++#18: xsdivdp 8000000000000000 8000000000000000 = 7ff8000000000000
++#19: xsdivdp 8000000000000000 0000000000000000 = 7ff8000000000000
++#20: xsdivdp 8000000000000000 0123214569900000 = 8000000000000000
++#21: xsdivdp 8000000000000000 7ff0000000000000 = 8000000000000000
++#22: xsdivdp 8000000000000000 7ff7ffffffffffff = 7fffffffffffffff
++#23: xsdivdp 8000000000000000 7ff8000000000000 = 7ff8000000000000
++#24: xsdivdp 0000000000000000 fff0000000000000 = 8000000000000000
++#25: xsdivdp 0000000000000000 c0d0650f5a07b353 = 8000000000000000
++#26: xsdivdp 0000000000000000 8000000000000000 = 7ff8000000000000
++#27: xsdivdp 0000000000000000 0000000000000000 = 7ff8000000000000
++#28: xsdivdp 0000000000000000 0123214569900000 = 0000000000000000
++#29: xsdivdp 0000000000000000 7ff0000000000000 = 0000000000000000
++#30: xsdivdp 0000000000000000 7ff7ffffffffffff = 7fffffffffffffff
++#31: xsdivdp 0000000000000000 7ff8000000000000 = 7ff8000000000000
++#32: xsdivdp 0123214569900000 fff0000000000000 = 8000000000000000
++#33: xsdivdp 0123214569900000 c0d0650f5a07b353 = 8042ab59d8b6ec87
++#34: xsdivdp 0123214569900000 8000000000000000 = fff0000000000000
++#35: xsdivdp 0123214569900000 0000000000000000 = 7ff0000000000000
++#36: xsdivdp 0123214569900000 404f000000000000 = 00c3bf3f64b5ad6b
++#37: xsdivdp 0123214569900000 7ff0000000000000 = 0000000000000000
++#38: xsdivdp 0123214569900000 7ff7ffffffffffff = 7fffffffffffffff
++#39: xsdivdp 0123214569900000 7ff8000000000000 = 7ff8000000000000
++#40: xsdivdp 7ff0000000000000 fff0000000000000 = 7ff8000000000000
++#41: xsdivdp 7ff0000000000000 c0d0650f5a07b353 = fff0000000000000
++#42: xsdivdp 7ff0000000000000 8000000000000000 = fff0000000000000
++#43: xsdivdp 7ff0000000000000 0000000000000000 = 7ff0000000000000
++#44: xsdivdp 7ff0000000000000 0123214569900000 = 7ff0000000000000
++#45: xsdivdp 7ff0000000000000 7ff0000000000000 = 7ff8000000000000
++#46: xsdivdp 7ff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
++#47: xsdivdp 7ff0000000000000 7ff8000000000000 = 7ff8000000000000
++#48: xsdivdp fff7ffffffffffff fff0000000000000 = ffffffffffffffff
++#49: xsdivdp fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
++#50: xsdivdp fff7ffffffffffff 8000000000000000 = ffffffffffffffff
++#51: xsdivdp fff7ffffffffffff 0000000000000000 = ffffffffffffffff
++#52: xsdivdp fff7ffffffffffff 0123214569900000 = ffffffffffffffff
++#53: xsdivdp fff7ffffffffffff 7ff0000000000000 = ffffffffffffffff
++#54: xsdivdp fff7ffffffffffff 7ff7ffffffffffff = ffffffffffffffff
++#55: xsdivdp fff7ffffffffffff 7ff8000000000000 = ffffffffffffffff
++#56: xsdivdp fff8000000000000 fff0000000000000 = fff8000000000000
++#57: xsdivdp fff8000000000000 c0d0650f5a07b353 = fff8000000000000
++#58: xsdivdp fff8000000000000 8000000000000000 = fff8000000000000
++#59: xsdivdp fff8000000000000 0000000000000000 = fff8000000000000
++#60: xsdivdp fff8000000000000 0123214569900000 = fff8000000000000
++#61: xsdivdp fff8000000000000 7ff0000000000000 = fff8000000000000
++#62: xsdivdp fff8000000000000 7ff7ffffffffffff = fff8000000000000
++#63: xsdivdp fff8000000000000 7ff8000000000000 = fff8000000000000
++
++#0: xsmaddadp fff0000000000000 fff0000000000000 c0d0650f5a07b353 = 7ff8000000000000
++#1: xsmaddadp c0d0650f5a07b353 fff0000000000000 0123214569900000 = fff0000000000000
++#2: xsmaddadp 8000000000000000 fff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
++#3: xsmaddadp 0000000000000000 fff0000000000000 0123214569900000 = fff0000000000000
++#4: xsmaddadp 0123214569900000 fff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
++#5: xsmaddadp 7ff0000000000000 fff0000000000000 0123214569900000 = 7ff8000000000000
++#6: xsmaddadp 7ff7ffffffffffff fff0000000000000 c0d0650f5a07b353 = 7fffffffffffffff
++#7: xsmaddadp 7ff8000000000000 fff0000000000000 0123214569900000 = 7ff8000000000000
++#8: xsmaddadp fff0000000000000 c0d0650f5a07b353 c0d0650f5a07b353 = fff0000000000000
++#9: xsmaddadp c0d0650f5a07b353 c0d0650f5a07b353 0123214569900000 = c0d0650f5a07b353
++#10: xsmaddadp 8000000000000000 c0d0650f5a07b353 c0d0650f5a07b353 = 41b0cc9d05eec2a7
++#11: xsmaddadp 0000000000000000 c0d0650f5a07b353 0123214569900000 = 82039a19ca8fcb5f
++#12: xsmaddadp 0123214569900000 c0d0650f5a07b353 c0d0650f5a07b353 = 41b0cc9d05eec2a7
++#13: xsmaddadp 7ff0000000000000 c0d0650f5a07b353 0123214569900000 = 7ff0000000000000
++#14: xsmaddadp 7ff7ffffffffffff c0d0650f5a07b353 c0d0650f5a07b353 = 7fffffffffffffff
++#15: xsmaddadp 7ff8000000000000 c0d0650f5a07b353 0123214569900000 = 7ff8000000000000
++#16: xsmaddadp fff0000000000000 8000000000000000 c0d0650f5a07b353 = fff0000000000000
++#17: xsmaddadp c0d0650f5a07b353 8000000000000000 0123214569900000 = c0d0650f5a07b353
++#18: xsmaddadp 8000000000000000 8000000000000000 c0d0650f5a07b353 = 0000000000000000
++#19: xsmaddadp 0000000000000000 8000000000000000 0123214569900000 = 0000000000000000
++#20: xsmaddadp 0123214569900000 8000000000000000 c0d0650f5a07b353 = 0123214569900000
++#21: xsmaddadp 7ff0000000000000 8000000000000000 0123214569900000 = 7ff0000000000000
++#22: xsmaddadp 7ff7ffffffffffff 8000000000000000 c0d0650f5a07b353 = 7fffffffffffffff
++#23: xsmaddadp 7ff8000000000000 8000000000000000 0123214569900000 = 7ff8000000000000
++#24: xsmaddadp fff0000000000000 0000000000000000 c0d0650f5a07b353 = fff0000000000000
++#25: xsmaddadp c0d0650f5a07b353 0000000000000000 0123214569900000 = c0d0650f5a07b353
++#26: xsmaddadp 8000000000000000 0000000000000000 c0d0650f5a07b353 = 8000000000000000
++#27: xsmaddadp 0000000000000000 0000000000000000 0123214569900000 = 0000000000000000
++#28: xsmaddadp 0123214569900000 0000000000000000 c0d0650f5a07b353 = 0123214569900000
++#29: xsmaddadp 7ff0000000000000 0000000000000000 0123214569900000 = 7ff0000000000000
++#30: xsmaddadp 7ff7ffffffffffff 0000000000000000 c0d0650f5a07b353 = 7fffffffffffffff
++#31: xsmaddadp 7ff8000000000000 0000000000000000 0123214569900000 = 7ff8000000000000
++#32: xsmaddadp fff0000000000000 0123214569900000 c0d0650f5a07b353 = fff0000000000000
++#33: xsmaddadp c0d0650f5a07b353 0123214569900000 0123214569900000 = c0d0650f5a07b353
++#34: xsmaddadp 8000000000000000 0123214569900000 c0d0650f5a07b353 = 82039a19ca8fcb5f
++#35: xsmaddadp 0000000000000000 0123214569900000 0123214569900000 = 0000000000000000
++#36: xsmaddadp 404f000000000000 0123214569900000 c0d0650f5a07b353 = 404f000000000000
++#37: xsmaddadp 7ff0000000000000 0123214569900000 0123214569900000 = 7ff0000000000000
++#38: xsmaddadp 7ff7ffffffffffff 0123214569900000 c0d0650f5a07b353 = 7fffffffffffffff
++#39: xsmaddadp 7ff8000000000000 0123214569900000 0123214569900000 = 7ff8000000000000
++#40: xsmaddadp fff0000000000000 7ff0000000000000 c0d0650f5a07b353 = fff0000000000000
++#41: xsmaddadp c0d0650f5a07b353 7ff0000000000000 0123214569900000 = 7ff0000000000000
++#42: xsmaddadp 8000000000000000 7ff0000000000000 c0d0650f5a07b353 = fff0000000000000
++#43: xsmaddadp 0000000000000000 7ff0000000000000 0123214569900000 = 7ff0000000000000
++#44: xsmaddadp 0123214569900000 7ff0000000000000 c0d0650f5a07b353 = fff0000000000000
++#45: xsmaddadp 7ff0000000000000 7ff0000000000000 0123214569900000 = 7ff0000000000000
++#46: xsmaddadp 7ff7ffffffffffff 7ff0000000000000 c0d0650f5a07b353 = 7fffffffffffffff
++#47: xsmaddadp 7ff8000000000000 7ff0000000000000 0123214569900000 = 7ff8000000000000
++#48: xsmaddadp fff0000000000000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
++#49: xsmaddadp c0d0650f5a07b353 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
++#50: xsmaddadp 8000000000000000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
++#51: xsmaddadp 0000000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
++#52: xsmaddadp 0123214569900000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
++#53: xsmaddadp 7ff0000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
++#54: xsmaddadp 7ff7ffffffffffff fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
++#55: xsmaddadp 7ff8000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
++#56: xsmaddadp fff0000000000000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
++#57: xsmaddadp c0d0650f5a07b353 fff8000000000000 0123214569900000 = fff8000000000000
++#58: xsmaddadp 8000000000000000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
++#59: xsmaddadp 0000000000000000 fff8000000000000 0123214569900000 = fff8000000000000
++#60: xsmaddadp 0123214569900000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
++#61: xsmaddadp 7ff0000000000000 fff8000000000000 0123214569900000 = fff8000000000000
++#62: xsmaddadp 7ff7ffffffffffff fff8000000000000 c0d0650f5a07b353 = fff8000000000000
++#63: xsmaddadp 7ff8000000000000 fff8000000000000 0123214569900000 = fff8000000000000
++
++#0: xsmaddmdp c0d0650f5a07b353 fff0000000000000 fff0000000000000 = 7ff8000000000000
++#1: xsmaddmdp 0123214569900000 fff0000000000000 c0d0650f5a07b353 = fff0000000000000
++#2: xsmaddmdp c0d0650f5a07b353 fff0000000000000 8000000000000000 = 7ff0000000000000
++#3: xsmaddmdp 0123214569900000 fff0000000000000 0000000000000000 = fff0000000000000
++#4: xsmaddmdp c0d0650f5a07b353 fff0000000000000 0123214569900000 = 7ff0000000000000
++#5: xsmaddmdp 0123214569900000 fff0000000000000 7ff0000000000000 = 7ff8000000000000
++#6: xsmaddmdp c0d0650f5a07b353 fff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
++#7: xsmaddmdp 0123214569900000 fff0000000000000 7ff8000000000000 = 7ff8000000000000
++#8: xsmaddmdp c0d0650f5a07b353 c0d0650f5a07b353 fff0000000000000 = fff0000000000000
++#9: xsmaddmdp 0123214569900000 c0d0650f5a07b353 c0d0650f5a07b353 = c0d0650f5a07b353
++#10: xsmaddmdp c0d0650f5a07b353 c0d0650f5a07b353 8000000000000000 = 41b0cc9d05eec2a7
++#11: xsmaddmdp 0123214569900000 c0d0650f5a07b353 0000000000000000 = 82039a19ca8fcb5f
++#12: xsmaddmdp c0d0650f5a07b353 c0d0650f5a07b353 0123214569900000 = 41b0cc9d05eec2a7
++#13: xsmaddmdp 0123214569900000 c0d0650f5a07b353 7ff0000000000000 = 7ff0000000000000
++#14: xsmaddmdp c0d0650f5a07b353 c0d0650f5a07b353 7ff7ffffffffffff = 7fffffffffffffff
++#15: xsmaddmdp 0123214569900000 c0d0650f5a07b353 7ff8000000000000 = 7ff8000000000000
++#16: xsmaddmdp c0d0650f5a07b353 8000000000000000 fff0000000000000 = fff0000000000000
++#17: xsmaddmdp 0123214569900000 8000000000000000 c0d0650f5a07b353 = c0d0650f5a07b353
++#18: xsmaddmdp c0d0650f5a07b353 8000000000000000 8000000000000000 = 0000000000000000
++#19: xsmaddmdp 0123214569900000 8000000000000000 0000000000000000 = 0000000000000000
++#20: xsmaddmdp c0d0650f5a07b353 8000000000000000 0123214569900000 = 0123214569900000
++#21: xsmaddmdp 0123214569900000 8000000000000000 7ff0000000000000 = 7ff0000000000000
++#22: xsmaddmdp c0d0650f5a07b353 8000000000000000 7ff7ffffffffffff = 7fffffffffffffff
++#23: xsmaddmdp 0123214569900000 8000000000000000 7ff8000000000000 = 7ff8000000000000
++#24: xsmaddmdp c0d0650f5a07b353 0000000000000000 fff0000000000000 = fff0000000000000
++#25: xsmaddmdp 0123214569900000 0000000000000000 c0d0650f5a07b353 = c0d0650f5a07b353
++#26: xsmaddmdp c0d0650f5a07b353 0000000000000000 8000000000000000 = 8000000000000000
++#27: xsmaddmdp 0123214569900000 0000000000000000 0000000000000000 = 0000000000000000
++#28: xsmaddmdp c0d0650f5a07b353 0000000000000000 0123214569900000 = 0123214569900000
++#29: xsmaddmdp 0123214569900000 0000000000000000 7ff0000000000000 = 7ff0000000000000
++#30: xsmaddmdp c0d0650f5a07b353 0000000000000000 7ff7ffffffffffff = 7fffffffffffffff
++#31: xsmaddmdp 0123214569900000 0000000000000000 7ff8000000000000 = 7ff8000000000000
++#32: xsmaddmdp c0d0650f5a07b353 0123214569900000 fff0000000000000 = fff0000000000000
++#33: xsmaddmdp 0123214569900000 0123214569900000 c0d0650f5a07b353 = c0d0650f5a07b353
++#34: xsmaddmdp c0d0650f5a07b353 0123214569900000 8000000000000000 = 82039a19ca8fcb5f
++#35: xsmaddmdp 0123214569900000 0123214569900000 0000000000000000 = 0000000000000000
++#36: xsmaddmdp c0d0650f5a07b353 0123214569900000 404f000000000000 = 404f000000000000
++#37: xsmaddmdp 0123214569900000 0123214569900000 7ff0000000000000 = 7ff0000000000000
++#38: xsmaddmdp c0d0650f5a07b353 0123214569900000 7ff7ffffffffffff = 7fffffffffffffff
++#39: xsmaddmdp 0123214569900000 0123214569900000 7ff8000000000000 = 7ff8000000000000
++#40: xsmaddmdp c0d0650f5a07b353 7ff0000000000000 fff0000000000000 = fff0000000000000
++#41: xsmaddmdp 0123214569900000 7ff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
++#42: xsmaddmdp c0d0650f5a07b353 7ff0000000000000 8000000000000000 = fff0000000000000
++#43: xsmaddmdp 0123214569900000 7ff0000000000000 0000000000000000 = 7ff0000000000000
++#44: xsmaddmdp c0d0650f5a07b353 7ff0000000000000 0123214569900000 = fff0000000000000
++#45: xsmaddmdp 0123214569900000 7ff0000000000000 7ff0000000000000 = 7ff0000000000000
++#46: xsmaddmdp c0d0650f5a07b353 7ff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
++#47: xsmaddmdp 0123214569900000 7ff0000000000000 7ff8000000000000 = 7ff8000000000000
++#48: xsmaddmdp c0d0650f5a07b353 fff7ffffffffffff fff0000000000000 = ffffffffffffffff
++#49: xsmaddmdp 0123214569900000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
++#50: xsmaddmdp c0d0650f5a07b353 fff7ffffffffffff 8000000000000000 = ffffffffffffffff
++#51: xsmaddmdp 0123214569900000 fff7ffffffffffff 0000000000000000 = ffffffffffffffff
++#52: xsmaddmdp c0d0650f5a07b353 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
++#53: xsmaddmdp 0123214569900000 fff7ffffffffffff 7ff0000000000000 = ffffffffffffffff
++#54: xsmaddmdp c0d0650f5a07b353 fff7ffffffffffff 7ff7ffffffffffff = ffffffffffffffff
++#55: xsmaddmdp 0123214569900000 fff7ffffffffffff 7ff8000000000000 = ffffffffffffffff
++#56: xsmaddmdp c0d0650f5a07b353 fff8000000000000 fff0000000000000 = fff8000000000000
++#57: xsmaddmdp 0123214569900000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
++#58: xsmaddmdp c0d0650f5a07b353 fff8000000000000 8000000000000000 = fff8000000000000
++#59: xsmaddmdp 0123214569900000 fff8000000000000 0000000000000000 = fff8000000000000
++#60: xsmaddmdp c0d0650f5a07b353 fff8000000000000 0123214569900000 = fff8000000000000
++#61: xsmaddmdp 0123214569900000 fff8000000000000 7ff0000000000000 = fff8000000000000
++#62: xsmaddmdp c0d0650f5a07b353 fff8000000000000 7ff7ffffffffffff = fff8000000000000
++#63: xsmaddmdp 0123214569900000 fff8000000000000 7ff8000000000000 = fff8000000000000
++
++#0: xsmsubadp fff0000000000000 fff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
++#1: xsmsubadp c0d0650f5a07b353 fff0000000000000 0123214569900000 = fff0000000000000
++#2: xsmsubadp 8000000000000000 fff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
++#3: xsmsubadp 0000000000000000 fff0000000000000 0123214569900000 = fff0000000000000
++#4: xsmsubadp 0123214569900000 fff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
++#5: xsmsubadp 7ff0000000000000 fff0000000000000 0123214569900000 = fff0000000000000
++#6: xsmsubadp 7ff7ffffffffffff fff0000000000000 c0d0650f5a07b353 = 7fffffffffffffff
++#7: xsmsubadp 7ff8000000000000 fff0000000000000 0123214569900000 = 7ff8000000000000
++#8: xsmsubadp fff0000000000000 c0d0650f5a07b353 c0d0650f5a07b353 = 7ff0000000000000
++#9: xsmsubadp c0d0650f5a07b353 c0d0650f5a07b353 0123214569900000 = 40d0650f5a07b353
++#10: xsmsubadp 8000000000000000 c0d0650f5a07b353 c0d0650f5a07b353 = 41b0cc9d05eec2a7
++#11: xsmsubadp 0000000000000000 c0d0650f5a07b353 0123214569900000 = 82039a19ca8fcb5f
++#12: xsmsubadp 0123214569900000 c0d0650f5a07b353 c0d0650f5a07b353 = 41b0cc9d05eec2a7
++#13: xsmsubadp 7ff0000000000000 c0d0650f5a07b353 0123214569900000 = fff0000000000000
++#14: xsmsubadp 7ff7ffffffffffff c0d0650f5a07b353 c0d0650f5a07b353 = 7fffffffffffffff
++#15: xsmsubadp 7ff8000000000000 c0d0650f5a07b353 0123214569900000 = 7ff8000000000000
++#16: xsmsubadp fff0000000000000 8000000000000000 c0d0650f5a07b353 = 7ff0000000000000
++#17: xsmsubadp c0d0650f5a07b353 8000000000000000 0123214569900000 = 40d0650f5a07b353
++#18: xsmsubadp 8000000000000000 8000000000000000 c0d0650f5a07b353 = 0000000000000000
++#19: xsmsubadp 0000000000000000 8000000000000000 0123214569900000 = 8000000000000000
++#20: xsmsubadp 0123214569900000 8000000000000000 c0d0650f5a07b353 = 8123214569900000
++#21: xsmsubadp 7ff0000000000000 8000000000000000 0123214569900000 = fff0000000000000
++#22: xsmsubadp 7ff7ffffffffffff 8000000000000000 c0d0650f5a07b353 = 7fffffffffffffff
++#23: xsmsubadp 7ff8000000000000 8000000000000000 0123214569900000 = 7ff8000000000000
++#24: xsmsubadp fff0000000000000 0000000000000000 c0d0650f5a07b353 = 7ff0000000000000
++#25: xsmsubadp c0d0650f5a07b353 0000000000000000 0123214569900000 = 40d0650f5a07b353
++#26: xsmsubadp 8000000000000000 0000000000000000 c0d0650f5a07b353 = 0000000000000000
++#27: xsmsubadp 0000000000000000 0000000000000000 0123214569900000 = 0000000000000000
++#28: xsmsubadp 0123214569900000 0000000000000000 c0d0650f5a07b353 = 8123214569900000
++#29: xsmsubadp 7ff0000000000000 0000000000000000 0123214569900000 = fff0000000000000
++#30: xsmsubadp 7ff7ffffffffffff 0000000000000000 c0d0650f5a07b353 = 7fffffffffffffff
++#31: xsmsubadp 7ff8000000000000 0000000000000000 0123214569900000 = 7ff8000000000000
++#32: xsmsubadp fff0000000000000 0123214569900000 c0d0650f5a07b353 = 7ff0000000000000
++#33: xsmsubadp c0d0650f5a07b353 0123214569900000 0123214569900000 = 40d0650f5a07b353
++#34: xsmsubadp 8000000000000000 0123214569900000 c0d0650f5a07b353 = 82039a19ca8fcb5f
++#35: xsmsubadp 0000000000000000 0123214569900000 0123214569900000 = 0000000000000000
++#36: xsmsubadp 404f000000000000 0123214569900000 c0d0650f5a07b353 = c04f000000000000
++#37: xsmsubadp 7ff0000000000000 0123214569900000 0123214569900000 = fff0000000000000
++#38: xsmsubadp 7ff7ffffffffffff 0123214569900000 c0d0650f5a07b353 = 7fffffffffffffff
++#39: xsmsubadp 7ff8000000000000 0123214569900000 0123214569900000 = 7ff8000000000000
++#40: xsmsubadp fff0000000000000 7ff0000000000000 c0d0650f5a07b353 = 7ff8000000000000
++#41: xsmsubadp c0d0650f5a07b353 7ff0000000000000 0123214569900000 = 7ff0000000000000
++#42: xsmsubadp 8000000000000000 7ff0000000000000 c0d0650f5a07b353 = fff0000000000000
++#43: xsmsubadp 0000000000000000 7ff0000000000000 0123214569900000 = 7ff0000000000000
++#44: xsmsubadp 0123214569900000 7ff0000000000000 c0d0650f5a07b353 = fff0000000000000
++#45: xsmsubadp 7ff0000000000000 7ff0000000000000 0123214569900000 = 7ff8000000000000
++#46: xsmsubadp 7ff7ffffffffffff 7ff0000000000000 c0d0650f5a07b353 = 7fffffffffffffff
++#47: xsmsubadp 7ff8000000000000 7ff0000000000000 0123214569900000 = 7ff8000000000000
++#48: xsmsubadp fff0000000000000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
++#49: xsmsubadp c0d0650f5a07b353 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
++#50: xsmsubadp 8000000000000000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
++#51: xsmsubadp 0000000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
++#52: xsmsubadp 0123214569900000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
++#53: xsmsubadp 7ff0000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
++#54: xsmsubadp 7ff7ffffffffffff fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
++#55: xsmsubadp 7ff8000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
++#56: xsmsubadp fff0000000000000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
++#57: xsmsubadp c0d0650f5a07b353 fff8000000000000 0123214569900000 = fff8000000000000
++#58: xsmsubadp 8000000000000000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
++#59: xsmsubadp 0000000000000000 fff8000000000000 0123214569900000 = fff8000000000000
++#60: xsmsubadp 0123214569900000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
++#61: xsmsubadp 7ff0000000000000 fff8000000000000 0123214569900000 = fff8000000000000
++#62: xsmsubadp 7ff7ffffffffffff fff8000000000000 c0d0650f5a07b353 = fff8000000000000
++#63: xsmsubadp 7ff8000000000000 fff8000000000000 0123214569900000 = fff8000000000000
++
++#0: xsmsubmdp c0d0650f5a07b353 fff0000000000000 fff0000000000000 = 7ff0000000000000
++#1: xsmsubmdp 0123214569900000 fff0000000000000 c0d0650f5a07b353 = fff0000000000000
++#2: xsmsubmdp c0d0650f5a07b353 fff0000000000000 8000000000000000 = 7ff0000000000000
++#3: xsmsubmdp 0123214569900000 fff0000000000000 0000000000000000 = fff0000000000000
++#4: xsmsubmdp c0d0650f5a07b353 fff0000000000000 0123214569900000 = 7ff0000000000000
++#5: xsmsubmdp 0123214569900000 fff0000000000000 7ff0000000000000 = fff0000000000000
++#6: xsmsubmdp c0d0650f5a07b353 fff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
++#7: xsmsubmdp 0123214569900000 fff0000000000000 7ff8000000000000 = 7ff8000000000000
++#8: xsmsubmdp c0d0650f5a07b353 c0d0650f5a07b353 fff0000000000000 = 7ff0000000000000
++#9: xsmsubmdp 0123214569900000 c0d0650f5a07b353 c0d0650f5a07b353 = 40d0650f5a07b353
++#10: xsmsubmdp c0d0650f5a07b353 c0d0650f5a07b353 8000000000000000 = 41b0cc9d05eec2a7
++#11: xsmsubmdp 0123214569900000 c0d0650f5a07b353 0000000000000000 = 82039a19ca8fcb5f
++#12: xsmsubmdp c0d0650f5a07b353 c0d0650f5a07b353 0123214569900000 = 41b0cc9d05eec2a7
++#13: xsmsubmdp 0123214569900000 c0d0650f5a07b353 7ff0000000000000 = fff0000000000000
++#14: xsmsubmdp c0d0650f5a07b353 c0d0650f5a07b353 7ff7ffffffffffff = 7fffffffffffffff
++#15: xsmsubmdp 0123214569900000 c0d0650f5a07b353 7ff8000000000000 = 7ff8000000000000
++#16: xsmsubmdp c0d0650f5a07b353 8000000000000000 fff0000000000000 = 7ff0000000000000
++#17: xsmsubmdp 0123214569900000 8000000000000000 c0d0650f5a07b353 = 40d0650f5a07b353
++#18: xsmsubmdp c0d0650f5a07b353 8000000000000000 8000000000000000 = 0000000000000000
++#19: xsmsubmdp 0123214569900000 8000000000000000 0000000000000000 = 8000000000000000
++#20: xsmsubmdp c0d0650f5a07b353 8000000000000000 0123214569900000 = 8123214569900000
++#21: xsmsubmdp 0123214569900000 8000000000000000 7ff0000000000000 = fff0000000000000
++#22: xsmsubmdp c0d0650f5a07b353 8000000000000000 7ff7ffffffffffff = 7fffffffffffffff
++#23: xsmsubmdp 0123214569900000 8000000000000000 7ff8000000000000 = 7ff8000000000000
++#24: xsmsubmdp c0d0650f5a07b353 0000000000000000 fff0000000000000 = 7ff0000000000000
++#25: xsmsubmdp 0123214569900000 0000000000000000 c0d0650f5a07b353 = 40d0650f5a07b353
++#26: xsmsubmdp c0d0650f5a07b353 0000000000000000 8000000000000000 = 0000000000000000
++#27: xsmsubmdp 0123214569900000 0000000000000000 0000000000000000 = 0000000000000000
++#28: xsmsubmdp c0d0650f5a07b353 0000000000000000 0123214569900000 = 8123214569900000
++#29: xsmsubmdp 0123214569900000 0000000000000000 7ff0000000000000 = fff0000000000000
++#30: xsmsubmdp c0d0650f5a07b353 0000000000000000 7ff7ffffffffffff = 7fffffffffffffff
++#31: xsmsubmdp 0123214569900000 0000000000000000 7ff8000000000000 = 7ff8000000000000
++#32: xsmsubmdp c0d0650f5a07b353 0123214569900000 fff0000000000000 = 7ff0000000000000
++#33: xsmsubmdp 0123214569900000 0123214569900000 c0d0650f5a07b353 = 40d0650f5a07b353
++#34: xsmsubmdp c0d0650f5a07b353 0123214569900000 8000000000000000 = 82039a19ca8fcb5f
++#35: xsmsubmdp 0123214569900000 0123214569900000 0000000000000000 = 0000000000000000
++#36: xsmsubmdp c0d0650f5a07b353 0123214569900000 404f000000000000 = c04f000000000000
++#37: xsmsubmdp 0123214569900000 0123214569900000 7ff0000000000000 = fff0000000000000
++#38: xsmsubmdp c0d0650f5a07b353 0123214569900000 7ff7ffffffffffff = 7fffffffffffffff
++#39: xsmsubmdp 0123214569900000 0123214569900000 7ff8000000000000 = 7ff8000000000000
++#40: xsmsubmdp c0d0650f5a07b353 7ff0000000000000 fff0000000000000 = 7ff8000000000000
++#41: xsmsubmdp 0123214569900000 7ff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
++#42: xsmsubmdp c0d0650f5a07b353 7ff0000000000000 8000000000000000 = fff0000000000000
++#43: xsmsubmdp 0123214569900000 7ff0000000000000 0000000000000000 = 7ff0000000000000
++#44: xsmsubmdp c0d0650f5a07b353 7ff0000000000000 0123214569900000 = fff0000000000000
++#45: xsmsubmdp 0123214569900000 7ff0000000000000 7ff0000000000000 = 7ff8000000000000
++#46: xsmsubmdp c0d0650f5a07b353 7ff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
++#47: xsmsubmdp 0123214569900000 7ff0000000000000 7ff8000000000000 = 7ff8000000000000
++#48: xsmsubmdp c0d0650f5a07b353 fff7ffffffffffff fff0000000000000 = ffffffffffffffff
++#49: xsmsubmdp 0123214569900000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
++#50: xsmsubmdp c0d0650f5a07b353 fff7ffffffffffff 8000000000000000 = ffffffffffffffff
++#51: xsmsubmdp 0123214569900000 fff7ffffffffffff 0000000000000000 = ffffffffffffffff
++#52: xsmsubmdp c0d0650f5a07b353 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
++#53: xsmsubmdp 0123214569900000 fff7ffffffffffff 7ff0000000000000 = ffffffffffffffff
++#54: xsmsubmdp c0d0650f5a07b353 fff7ffffffffffff 7ff7ffffffffffff = ffffffffffffffff
++#55: xsmsubmdp 0123214569900000 fff7ffffffffffff 7ff8000000000000 = ffffffffffffffff
++#56: xsmsubmdp c0d0650f5a07b353 fff8000000000000 fff0000000000000 = fff8000000000000
++#57: xsmsubmdp 0123214569900000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
++#58: xsmsubmdp c0d0650f5a07b353 fff8000000000000 8000000000000000 = fff8000000000000
++#59: xsmsubmdp 0123214569900000 fff8000000000000 0000000000000000 = fff8000000000000
++#60: xsmsubmdp c0d0650f5a07b353 fff8000000000000 0123214569900000 = fff8000000000000
++#61: xsmsubmdp 0123214569900000 fff8000000000000 7ff0000000000000 = fff8000000000000
++#62: xsmsubmdp c0d0650f5a07b353 fff8000000000000 7ff7ffffffffffff = fff8000000000000
++#63: xsmsubmdp 0123214569900000 fff8000000000000 7ff8000000000000 = fff8000000000000
++
++#0: xsnmaddadp fff0000000000000 fff0000000000000 c0d0650f5a07b353 = 7ff8000000000000
++#1: xsnmaddadp c0d0650f5a07b353 fff0000000000000 0123214569900000 = 7ff0000000000000
++#2: xsnmaddadp 8000000000000000 fff0000000000000 c0d0650f5a07b353 = fff0000000000000
++#3: xsnmaddadp 0000000000000000 fff0000000000000 0123214569900000 = 7ff0000000000000
++#4: xsnmaddadp 0123214569900000 fff0000000000000 c0d0650f5a07b353 = fff0000000000000
++#5: xsnmaddadp 7ff0000000000000 fff0000000000000 0123214569900000 = 7ff8000000000000
++#6: xsnmaddadp 7ff7ffffffffffff fff0000000000000 c0d0650f5a07b353 = 7fffffffffffffff
++#7: xsnmaddadp 7ff8000000000000 fff0000000000000 0123214569900000 = 7ff8000000000000
++#8: xsnmaddadp fff0000000000000 c0d0650f5a07b353 c0d0650f5a07b353 = 7ff0000000000000
++#9: xsnmaddadp c0d0650f5a07b353 c0d0650f5a07b353 0123214569900000 = 40d0650f5a07b353
++#10: xsnmaddadp 8000000000000000 c0d0650f5a07b353 c0d0650f5a07b353 = c1b0cc9d05eec2a7
++#11: xsnmaddadp 0000000000000000 c0d0650f5a07b353 0123214569900000 = 02039a19ca8fcb5f
++#12: xsnmaddadp 0123214569900000 c0d0650f5a07b353 c0d0650f5a07b353 = c1b0cc9d05eec2a7
++#13: xsnmaddadp 7ff0000000000000 c0d0650f5a07b353 0123214569900000 = fff0000000000000
++#14: xsnmaddadp 7ff7ffffffffffff c0d0650f5a07b353 c0d0650f5a07b353 = 7fffffffffffffff
++#15: xsnmaddadp 7ff8000000000000 c0d0650f5a07b353 0123214569900000 = 7ff8000000000000
++#16: xsnmaddadp fff0000000000000 8000000000000000 c0d0650f5a07b353 = 7ff0000000000000
++#17: xsnmaddadp c0d0650f5a07b353 8000000000000000 0123214569900000 = 40d0650f5a07b353
++#18: xsnmaddadp 8000000000000000 8000000000000000 c0d0650f5a07b353 = 8000000000000000
++#19: xsnmaddadp 0000000000000000 8000000000000000 0123214569900000 = 8000000000000000
++#20: xsnmaddadp 0123214569900000 8000000000000000 c0d0650f5a07b353 = 8123214569900000
++#21: xsnmaddadp 7ff0000000000000 8000000000000000 0123214569900000 = fff0000000000000
++#22: xsnmaddadp 7ff7ffffffffffff 8000000000000000 c0d0650f5a07b353 = 7fffffffffffffff
++#23: xsnmaddadp 7ff8000000000000 8000000000000000 0123214569900000 = 7ff8000000000000
++#24: xsnmaddadp fff0000000000000 0000000000000000 c0d0650f5a07b353 = 7ff0000000000000
++#25: xsnmaddadp c0d0650f5a07b353 0000000000000000 0123214569900000 = 40d0650f5a07b353
++#26: xsnmaddadp 8000000000000000 0000000000000000 c0d0650f5a07b353 = 0000000000000000
++#27: xsnmaddadp 0000000000000000 0000000000000000 0123214569900000 = 8000000000000000
++#28: xsnmaddadp 0123214569900000 0000000000000000 c0d0650f5a07b353 = 8123214569900000
++#29: xsnmaddadp 7ff0000000000000 0000000000000000 0123214569900000 = fff0000000000000
++#30: xsnmaddadp 7ff7ffffffffffff 0000000000000000 c0d0650f5a07b353 = 7fffffffffffffff
++#31: xsnmaddadp 7ff8000000000000 0000000000000000 0123214569900000 = 7ff8000000000000
++#32: xsnmaddadp fff0000000000000 0123214569900000 c0d0650f5a07b353 = 7ff0000000000000
++#33: xsnmaddadp c0d0650f5a07b353 0123214569900000 0123214569900000 = 40d0650f5a07b353
++#34: xsnmaddadp 8000000000000000 0123214569900000 c0d0650f5a07b353 = 02039a19ca8fcb5f
++#35: xsnmaddadp 0000000000000000 0123214569900000 0123214569900000 = 8000000000000000
++#36: xsnmaddadp 404f000000000000 0123214569900000 c0d0650f5a07b353 = c04f000000000000
++#37: xsnmaddadp 7ff0000000000000 0123214569900000 0123214569900000 = fff0000000000000
++#38: xsnmaddadp 7ff7ffffffffffff 0123214569900000 c0d0650f5a07b353 = 7fffffffffffffff
++#39: xsnmaddadp 7ff8000000000000 0123214569900000 0123214569900000 = 7ff8000000000000
++#40: xsnmaddadp fff0000000000000 7ff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
++#41: xsnmaddadp c0d0650f5a07b353 7ff0000000000000 0123214569900000 = fff0000000000000
++#42: xsnmaddadp 8000000000000000 7ff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
++#43: xsnmaddadp 0000000000000000 7ff0000000000000 0123214569900000 = fff0000000000000
++#44: xsnmaddadp 0123214569900000 7ff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
++#45: xsnmaddadp 7ff0000000000000 7ff0000000000000 0123214569900000 = fff0000000000000
++#46: xsnmaddadp 7ff7ffffffffffff 7ff0000000000000 c0d0650f5a07b353 = 7fffffffffffffff
++#47: xsnmaddadp 7ff8000000000000 7ff0000000000000 0123214569900000 = 7ff8000000000000
++#48: xsnmaddadp fff0000000000000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
++#49: xsnmaddadp c0d0650f5a07b353 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
++#50: xsnmaddadp 8000000000000000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
++#51: xsnmaddadp 0000000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
++#52: xsnmaddadp 0123214569900000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
++#53: xsnmaddadp 7ff0000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
++#54: xsnmaddadp 7ff7ffffffffffff fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
++#55: xsnmaddadp 7ff8000000000000 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
++#56: xsnmaddadp fff0000000000000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
++#57: xsnmaddadp c0d0650f5a07b353 fff8000000000000 0123214569900000 = fff8000000000000
++#58: xsnmaddadp 8000000000000000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
++#59: xsnmaddadp 0000000000000000 fff8000000000000 0123214569900000 = fff8000000000000
++#60: xsnmaddadp 0123214569900000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
++#61: xsnmaddadp 7ff0000000000000 fff8000000000000 0123214569900000 = fff8000000000000
++#62: xsnmaddadp 7ff7ffffffffffff fff8000000000000 c0d0650f5a07b353 = fff8000000000000
++#63: xsnmaddadp 7ff8000000000000 fff8000000000000 0123214569900000 = fff8000000000000
++
++#0: xsnmaddmdp c0d0650f5a07b353 fff0000000000000 fff0000000000000 = 7ff8000000000000
++#1: xsnmaddmdp 0123214569900000 fff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
++#2: xsnmaddmdp c0d0650f5a07b353 fff0000000000000 8000000000000000 = fff0000000000000
++#3: xsnmaddmdp 0123214569900000 fff0000000000000 0000000000000000 = 7ff0000000000000
++#4: xsnmaddmdp c0d0650f5a07b353 fff0000000000000 0123214569900000 = fff0000000000000
++#5: xsnmaddmdp 0123214569900000 fff0000000000000 7ff0000000000000 = 7ff8000000000000
++#6: xsnmaddmdp c0d0650f5a07b353 fff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
++#7: xsnmaddmdp 0123214569900000 fff0000000000000 7ff8000000000000 = 7ff8000000000000
++#8: xsnmaddmdp c0d0650f5a07b353 c0d0650f5a07b353 fff0000000000000 = 7ff0000000000000
++#9: xsnmaddmdp 0123214569900000 c0d0650f5a07b353 c0d0650f5a07b353 = 40d0650f5a07b353
++#10: xsnmaddmdp c0d0650f5a07b353 c0d0650f5a07b353 8000000000000000 = c1b0cc9d05eec2a7
++#11: xsnmaddmdp 0123214569900000 c0d0650f5a07b353 0000000000000000 = 02039a19ca8fcb5f
++#12: xsnmaddmdp c0d0650f5a07b353 c0d0650f5a07b353 0123214569900000 = c1b0cc9d05eec2a7
++#13: xsnmaddmdp 0123214569900000 c0d0650f5a07b353 7ff0000000000000 = fff0000000000000
++#14: xsnmaddmdp c0d0650f5a07b353 c0d0650f5a07b353 7ff7ffffffffffff = 7fffffffffffffff
++#15: xsnmaddmdp 0123214569900000 c0d0650f5a07b353 7ff8000000000000 = 7ff8000000000000
++#16: xsnmaddmdp c0d0650f5a07b353 8000000000000000 fff0000000000000 = 7ff0000000000000
++#17: xsnmaddmdp 0123214569900000 8000000000000000 c0d0650f5a07b353 = 40d0650f5a07b353
++#18: xsnmaddmdp c0d0650f5a07b353 8000000000000000 8000000000000000 = 8000000000000000
++#19: xsnmaddmdp 0123214569900000 8000000000000000 0000000000000000 = 8000000000000000
++#20: xsnmaddmdp c0d0650f5a07b353 8000000000000000 0123214569900000 = 8123214569900000
++#21: xsnmaddmdp 0123214569900000 8000000000000000 7ff0000000000000 = fff0000000000000
++#22: xsnmaddmdp c0d0650f5a07b353 8000000000000000 7ff7ffffffffffff = 7fffffffffffffff
++#23: xsnmaddmdp 0123214569900000 8000000000000000 7ff8000000000000 = 7ff8000000000000
++#24: xsnmaddmdp c0d0650f5a07b353 0000000000000000 fff0000000000000 = 7ff0000000000000
++#25: xsnmaddmdp 0123214569900000 0000000000000000 c0d0650f5a07b353 = 40d0650f5a07b353
++#26: xsnmaddmdp c0d0650f5a07b353 0000000000000000 8000000000000000 = 0000000000000000
++#27: xsnmaddmdp 0123214569900000 0000000000000000 0000000000000000 = 8000000000000000
++#28: xsnmaddmdp c0d0650f5a07b353 0000000000000000 0123214569900000 = 8123214569900000
++#29: xsnmaddmdp 0123214569900000 0000000000000000 7ff0000000000000 = fff0000000000000
++#30: xsnmaddmdp c0d0650f5a07b353 0000000000000000 7ff7ffffffffffff = 7fffffffffffffff
++#31: xsnmaddmdp 0123214569900000 0000000000000000 7ff8000000000000 = 7ff8000000000000
++#32: xsnmaddmdp c0d0650f5a07b353 0123214569900000 fff0000000000000 = 7ff0000000000000
++#33: xsnmaddmdp 0123214569900000 0123214569900000 c0d0650f5a07b353 = 40d0650f5a07b353
++#34: xsnmaddmdp c0d0650f5a07b353 0123214569900000 8000000000000000 = 02039a19ca8fcb5f
++#35: xsnmaddmdp 0123214569900000 0123214569900000 0000000000000000 = 8000000000000000
++#36: xsnmaddmdp c0d0650f5a07b353 0123214569900000 404f000000000000 = c04f000000000000
++#37: xsnmaddmdp 0123214569900000 0123214569900000 7ff0000000000000 = fff0000000000000
++#38: xsnmaddmdp c0d0650f5a07b353 0123214569900000 7ff7ffffffffffff = 7fffffffffffffff
++#39: xsnmaddmdp 0123214569900000 0123214569900000 7ff8000000000000 = 7ff8000000000000
++#40: xsnmaddmdp c0d0650f5a07b353 7ff0000000000000 fff0000000000000 = 7ff0000000000000
++#41: xsnmaddmdp 0123214569900000 7ff0000000000000 c0d0650f5a07b353 = fff0000000000000
++#42: xsnmaddmdp c0d0650f5a07b353 7ff0000000000000 8000000000000000 = 7ff0000000000000
++#43: xsnmaddmdp 0123214569900000 7ff0000000000000 0000000000000000 = fff0000000000000
++#44: xsnmaddmdp c0d0650f5a07b353 7ff0000000000000 0123214569900000 = 7ff0000000000000
++#45: xsnmaddmdp 0123214569900000 7ff0000000000000 7ff0000000000000 = fff0000000000000
++#46: xsnmaddmdp c0d0650f5a07b353 7ff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
++#47: xsnmaddmdp 0123214569900000 7ff0000000000000 7ff8000000000000 = 7ff8000000000000
++#48: xsnmaddmdp c0d0650f5a07b353 fff7ffffffffffff fff0000000000000 = ffffffffffffffff
++#49: xsnmaddmdp 0123214569900000 fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
++#50: xsnmaddmdp c0d0650f5a07b353 fff7ffffffffffff 8000000000000000 = ffffffffffffffff
++#51: xsnmaddmdp 0123214569900000 fff7ffffffffffff 0000000000000000 = ffffffffffffffff
++#52: xsnmaddmdp c0d0650f5a07b353 fff7ffffffffffff 0123214569900000 = ffffffffffffffff
++#53: xsnmaddmdp 0123214569900000 fff7ffffffffffff 7ff0000000000000 = ffffffffffffffff
++#54: xsnmaddmdp c0d0650f5a07b353 fff7ffffffffffff 7ff7ffffffffffff = ffffffffffffffff
++#55: xsnmaddmdp 0123214569900000 fff7ffffffffffff 7ff8000000000000 = ffffffffffffffff
++#56: xsnmaddmdp c0d0650f5a07b353 fff8000000000000 fff0000000000000 = fff8000000000000
++#57: xsnmaddmdp 0123214569900000 fff8000000000000 c0d0650f5a07b353 = fff8000000000000
++#58: xsnmaddmdp c0d0650f5a07b353 fff8000000000000 8000000000000000 = fff8000000000000
++#59: xsnmaddmdp 0123214569900000 fff8000000000000 0000000000000000 = fff8000000000000
++#60: xsnmaddmdp c0d0650f5a07b353 fff8000000000000 0123214569900000 = fff8000000000000
++#61: xsnmaddmdp 0123214569900000 fff8000000000000 7ff0000000000000 = fff8000000000000
++#62: xsnmaddmdp c0d0650f5a07b353 fff8000000000000 7ff7ffffffffffff = fff8000000000000
++#63: xsnmaddmdp 0123214569900000 fff8000000000000 7ff8000000000000 = fff8000000000000
++
++#0: xsmuldp fff0000000000000 fff0000000000000 = 7ff0000000000000
++#1: xsmuldp fff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
++#2: xsmuldp fff0000000000000 8000000000000000 = 7ff8000000000000
++#3: xsmuldp fff0000000000000 0000000000000000 = 7ff8000000000000
++#4: xsmuldp fff0000000000000 0123214569900000 = fff0000000000000
++#5: xsmuldp fff0000000000000 7ff0000000000000 = fff0000000000000
++#6: xsmuldp fff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
++#7: xsmuldp fff0000000000000 7ff8000000000000 = 7ff8000000000000
++#8: xsmuldp c0d0650f5a07b353 fff0000000000000 = 7ff0000000000000
++#9: xsmuldp c0d0650f5a07b353 c0d0650f5a07b353 = 41b0cc9d05eec2a7
++#10: xsmuldp c0d0650f5a07b353 8000000000000000 = 0000000000000000
++#11: xsmuldp c0d0650f5a07b353 0000000000000000 = 8000000000000000
++#12: xsmuldp c0d0650f5a07b353 0123214569900000 = 82039a19ca8fcb5f
++#13: xsmuldp c0d0650f5a07b353 7ff0000000000000 = fff0000000000000
++#14: xsmuldp c0d0650f5a07b353 7ff7ffffffffffff = 7fffffffffffffff
++#15: xsmuldp c0d0650f5a07b353 7ff8000000000000 = 7ff8000000000000
++#16: xsmuldp 8000000000000000 fff0000000000000 = 7ff8000000000000
++#17: xsmuldp 8000000000000000 c0d0650f5a07b353 = 0000000000000000
++#18: xsmuldp 8000000000000000 8000000000000000 = 0000000000000000
++#19: xsmuldp 8000000000000000 0000000000000000 = 8000000000000000
++#20: xsmuldp 8000000000000000 0123214569900000 = 8000000000000000
++#21: xsmuldp 8000000000000000 7ff0000000000000 = 7ff8000000000000
++#22: xsmuldp 8000000000000000 7ff7ffffffffffff = 7fffffffffffffff
++#23: xsmuldp 8000000000000000 7ff8000000000000 = 7ff8000000000000
++#24: xsmuldp 0000000000000000 fff0000000000000 = 7ff8000000000000
++#25: xsmuldp 0000000000000000 c0d0650f5a07b353 = 8000000000000000
++#26: xsmuldp 0000000000000000 8000000000000000 = 8000000000000000
++#27: xsmuldp 0000000000000000 0000000000000000 = 0000000000000000
++#28: xsmuldp 0000000000000000 0123214569900000 = 0000000000000000
++#29: xsmuldp 0000000000000000 7ff0000000000000 = 7ff8000000000000
++#30: xsmuldp 0000000000000000 7ff7ffffffffffff = 7fffffffffffffff
++#31: xsmuldp 0000000000000000 7ff8000000000000 = 7ff8000000000000
++#32: xsmuldp 0123214569900000 fff0000000000000 = fff0000000000000
++#33: xsmuldp 0123214569900000 c0d0650f5a07b353 = 82039a19ca8fcb5f
++#34: xsmuldp 0123214569900000 8000000000000000 = 8000000000000000
++#35: xsmuldp 0123214569900000 0000000000000000 = 0000000000000000
++#36: xsmuldp 0123214569900000 404f000000000000 = 0182883b3e438000
++#37: xsmuldp 0123214569900000 7ff0000000000000 = 7ff0000000000000
++#38: xsmuldp 0123214569900000 7ff7ffffffffffff = 7fffffffffffffff
++#39: xsmuldp 0123214569900000 7ff8000000000000 = 7ff8000000000000
++#40: xsmuldp 7ff0000000000000 fff0000000000000 = fff0000000000000
++#41: xsmuldp 7ff0000000000000 c0d0650f5a07b353 = fff0000000000000
++#42: xsmuldp 7ff0000000000000 8000000000000000 = 7ff8000000000000
++#43: xsmuldp 7ff0000000000000 0000000000000000 = 7ff8000000000000
++#44: xsmuldp 7ff0000000000000 0123214569900000 = 7ff0000000000000
++#45: xsmuldp 7ff0000000000000 7ff0000000000000 = 7ff0000000000000
++#46: xsmuldp 7ff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
++#47: xsmuldp 7ff0000000000000 7ff8000000000000 = 7ff8000000000000
++#48: xsmuldp fff7ffffffffffff fff0000000000000 = ffffffffffffffff
++#49: xsmuldp fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
++#50: xsmuldp fff7ffffffffffff 8000000000000000 = ffffffffffffffff
++#51: xsmuldp fff7ffffffffffff 0000000000000000 = ffffffffffffffff
++#52: xsmuldp fff7ffffffffffff 0123214569900000 = ffffffffffffffff
++#53: xsmuldp fff7ffffffffffff 7ff0000000000000 = ffffffffffffffff
++#54: xsmuldp fff7ffffffffffff 7ff7ffffffffffff = ffffffffffffffff
++#55: xsmuldp fff7ffffffffffff 7ff8000000000000 = ffffffffffffffff
++#56: xsmuldp fff8000000000000 fff0000000000000 = fff8000000000000
++#57: xsmuldp fff8000000000000 c0d0650f5a07b353 = fff8000000000000
++#58: xsmuldp fff8000000000000 8000000000000000 = fff8000000000000
++#59: xsmuldp fff8000000000000 0000000000000000 = fff8000000000000
++#60: xsmuldp fff8000000000000 0123214569900000 = fff8000000000000
++#61: xsmuldp fff8000000000000 7ff0000000000000 = fff8000000000000
++#62: xsmuldp fff8000000000000 7ff7ffffffffffff = fff8000000000000
++#63: xsmuldp fff8000000000000 7ff8000000000000 = fff8000000000000
++
++#0: xssubdp fff0000000000000 fff0000000000000 = 7ff8000000000000
++#1: xssubdp fff0000000000000 c0d0650f5a07b353 = fff0000000000000
++#2: xssubdp fff0000000000000 8000000000000000 = fff0000000000000
++#3: xssubdp fff0000000000000 0000000000000000 = fff0000000000000
++#4: xssubdp fff0000000000000 0123214569900000 = fff0000000000000
++#5: xssubdp fff0000000000000 7ff0000000000000 = fff0000000000000
++#6: xssubdp fff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
++#7: xssubdp fff0000000000000 7ff8000000000000 = 7ff8000000000000
++#8: xssubdp c0d0650f5a07b353 fff0000000000000 = 7ff0000000000000
++#9: xssubdp c0d0650f5a07b353 c0d0650f5a07b353 = 0000000000000000
++#10: xssubdp c0d0650f5a07b353 8000000000000000 = c0d0650f5a07b353
++#11: xssubdp c0d0650f5a07b353 0000000000000000 = c0d0650f5a07b353
++#12: xssubdp c0d0650f5a07b353 0123214569900000 = c0d0650f5a07b353
++#13: xssubdp c0d0650f5a07b353 7ff0000000000000 = fff0000000000000
++#14: xssubdp c0d0650f5a07b353 7ff7ffffffffffff = 7fffffffffffffff
++#15: xssubdp c0d0650f5a07b353 7ff8000000000000 = 7ff8000000000000
++#16: xssubdp 8000000000000000 fff0000000000000 = 7ff0000000000000
++#17: xssubdp 8000000000000000 c0d0650f5a07b353 = 40d0650f5a07b353
++#18: xssubdp 8000000000000000 8000000000000000 = 0000000000000000
++#19: xssubdp 8000000000000000 0000000000000000 = 8000000000000000
++#20: xssubdp 8000000000000000 0123214569900000 = 8123214569900000
++#21: xssubdp 8000000000000000 7ff0000000000000 = fff0000000000000
++#22: xssubdp 8000000000000000 7ff7ffffffffffff = 7fffffffffffffff
++#23: xssubdp 8000000000000000 7ff8000000000000 = 7ff8000000000000
++#24: xssubdp 0000000000000000 fff0000000000000 = 7ff0000000000000
++#25: xssubdp 0000000000000000 c0d0650f5a07b353 = 40d0650f5a07b353
++#26: xssubdp 0000000000000000 8000000000000000 = 0000000000000000
++#27: xssubdp 0000000000000000 0000000000000000 = 0000000000000000
++#28: xssubdp 0000000000000000 0123214569900000 = 8123214569900000
++#29: xssubdp 0000000000000000 7ff0000000000000 = fff0000000000000
++#30: xssubdp 0000000000000000 7ff7ffffffffffff = 7fffffffffffffff
++#31: xssubdp 0000000000000000 7ff8000000000000 = 7ff8000000000000
++#32: xssubdp 0123214569900000 fff0000000000000 = 7ff0000000000000
++#33: xssubdp 0123214569900000 c0d0650f5a07b353 = 40d0650f5a07b353
++#34: xssubdp 0123214569900000 8000000000000000 = 0123214569900000
++#35: xssubdp 0123214569900000 0000000000000000 = 0123214569900000
++#36: xssubdp 0123214569900000 404f000000000000 = c04f000000000000
++#37: xssubdp 0123214569900000 7ff0000000000000 = fff0000000000000
++#38: xssubdp 0123214569900000 7ff7ffffffffffff = 7fffffffffffffff
++#39: xssubdp 0123214569900000 7ff8000000000000 = 7ff8000000000000
++#40: xssubdp 7ff0000000000000 fff0000000000000 = 7ff0000000000000
++#41: xssubdp 7ff0000000000000 c0d0650f5a07b353 = 7ff0000000000000
++#42: xssubdp 7ff0000000000000 8000000000000000 = 7ff0000000000000
++#43: xssubdp 7ff0000000000000 0000000000000000 = 7ff0000000000000
++#44: xssubdp 7ff0000000000000 0123214569900000 = 7ff0000000000000
++#45: xssubdp 7ff0000000000000 7ff0000000000000 = 7ff8000000000000
++#46: xssubdp 7ff0000000000000 7ff7ffffffffffff = 7fffffffffffffff
++#47: xssubdp 7ff0000000000000 7ff8000000000000 = 7ff8000000000000
++#48: xssubdp fff7ffffffffffff fff0000000000000 = ffffffffffffffff
++#49: xssubdp fff7ffffffffffff c0d0650f5a07b353 = ffffffffffffffff
++#50: xssubdp fff7ffffffffffff 8000000000000000 = ffffffffffffffff
++#51: xssubdp fff7ffffffffffff 0000000000000000 = ffffffffffffffff
++#52: xssubdp fff7ffffffffffff 0123214569900000 = ffffffffffffffff
++#53: xssubdp fff7ffffffffffff 7ff0000000000000 = ffffffffffffffff
++#54: xssubdp fff7ffffffffffff 7ff7ffffffffffff = ffffffffffffffff
++#55: xssubdp fff7ffffffffffff 7ff8000000000000 = ffffffffffffffff
++#56: xssubdp fff8000000000000 fff0000000000000 = fff8000000000000
++#57: xssubdp fff8000000000000 c0d0650f5a07b353 = fff8000000000000
++#58: xssubdp fff8000000000000 8000000000000000 = fff8000000000000
++#59: xssubdp fff8000000000000 0000000000000000 = fff8000000000000
++#60: xssubdp fff8000000000000 0123214569900000 = fff8000000000000
++#61: xssubdp fff8000000000000 7ff0000000000000 = fff8000000000000
++#62: xssubdp fff8000000000000 7ff7ffffffffffff = fff8000000000000
++#63: xssubdp fff8000000000000 7ff8000000000000 = fff8000000000000
++
++
++Test VSX scalar integer conversion instructions
++#0: xscvdpsxds 3fd8000000000000 => 0000000000000000
++#1: xscvdpsxds 404f000000000000 => 000000000000003e
++#2: xscvdpsxds 0018000000b77501 => 0000000000000000
++#3: xscvdpsxds 7fe800000000051b => 7fffffffffffffff
++#4: xscvdpsxds 0123214569900000 => 0000000000000000
++#5: xscvdpsxds 0000000000000000 => 0000000000000000
++#6: xscvdpsxds 8000000000000000 => 0000000000000000
++#7: xscvdpsxds 7ff0000000000000 => 7fffffffffffffff
++#8: xscvdpsxds fff0000000000000 => 8000000000000000
++#9: xscvdpsxds 7ff7ffffffffffff => 8000000000000000
++#10: xscvdpsxds fff7ffffffffffff => 8000000000000000
++#11: xscvdpsxds 7ff8000000000000 => 8000000000000000
++#12: xscvdpsxds fff8000000000000 => 8000000000000000
++#13: xscvdpsxds 8008340000078000 => 0000000000000000
++#14: xscvdpsxds c0d0650f5a07b353 => ffffffffffffbe6c
++
++#0: xscvsxddp 3fd8000000000000 => 43cfec0000000000
++#1: xscvsxddp 404f000000000000 => 43d013c000000000
++#2: xscvsxddp 0018000000b77501 => 4338000000b77501
++#3: xscvsxddp 7fe800000000051b => 43dffa0000000001
++#4: xscvsxddp 0123214569900000 => 4372321456990000
++#5: xscvsxddp 0000000000000000 => 0000000000000000
++#6: xscvsxddp 8000000000000000 => c3e0000000000000
++#7: xscvsxddp 7ff0000000000000 => 43dffc0000000000
++#8: xscvsxddp fff0000000000000 => c330000000000000
++#9: xscvsxddp 7ff7ffffffffffff => 43dffe0000000000
++#10: xscvsxddp fff7ffffffffffff => c320000000000002
++#11: xscvsxddp 7ff8000000000000 => 43dffe0000000000
++#12: xscvsxddp fff8000000000000 => c320000000000000
++#13: xscvsxddp 8008340000078000 => c3dffdf2fffffe20
++#14: xscvsxddp c0d0650f5a07b353 => c3cf97cd7852fc26
++
++#0: xscvuxddp 3fd8000000000000 => 43cfec0000000000
++#1: xscvuxddp 404f000000000000 => 43d013c000000000
++#2: xscvuxddp 0018000000b77501 => 4338000000b77501
++#3: xscvuxddp 7fe800000000051b => 43dffa0000000001
++#4: xscvuxddp 0123214569900000 => 4372321456990000
++#5: xscvuxddp 0000000000000000 => 0000000000000000
++#6: xscvuxddp 8000000000000000 => 43e0000000000000
++#7: xscvuxddp 7ff0000000000000 => 43dffc0000000000
++#8: xscvuxddp fff0000000000000 => 43effe0000000000
++#9: xscvuxddp 7ff7ffffffffffff => 43dffe0000000000
++#10: xscvuxddp fff7ffffffffffff => 43efff0000000000
++#11: xscvuxddp 7ff8000000000000 => 43dffe0000000000
++#12: xscvuxddp fff8000000000000 => 43efff0000000000
++#13: xscvuxddp 8008340000078000 => 43e00106800000f0
++#14: xscvuxddp c0d0650f5a07b353 => 43e81a0ca1eb40f6
++
++
+diff --git a/none/tests/ppc64/test_isa_2_07_part1.c b/none/tests/ppc64/test_isa_2_07_part1.c
+index 7cdf620..26b7ac2 100644
+--- a/none/tests/ppc64/test_isa_2_07_part1.c
++++ b/none/tests/ppc64/test_isa_2_07_part1.c
+@@ -135,6 +135,12 @@ typedef uint64_t HWord_t;
+ #define ZERO 0ULL
+ #endif /* __powerpc64__ */
+
++#ifdef VGP_ppc64le_linux
++#define isLE 1
++#else
++#define isLE 0
++#endif
++
+ typedef uint64_t Word_t;
+
+ enum {
+@@ -1116,7 +1122,10 @@ static void mfvs(const char* name, test_func_t func,
+
+ for (i=0; i < NB_VDARGS; i++) {
+ r14 = ZERO;
+- vec_inA = (vector unsigned long long){ vdargs[i], 0ULL };
++ if (isLE)
++ vec_inA = (vector unsigned long long){ 0ULL, vdargs[i] };
++ else
++ vec_inA = (vector unsigned long long){ vdargs[i], 0ULL };
+
+ (*func)();
+ result = r14;
+@@ -1139,6 +1148,8 @@ static void mtvs(const char* name, test_func_t func,
+
+ (*func)();
+ dst = (unsigned long long *) &vec_out;
++ if (isLE)
++ dst++;
+ printf("%s: %016llx => %016llx\n", name, vdargs[i], *dst);
+ }
+ }
+@@ -1154,13 +1165,16 @@ static void mtvs2s(const char* name, test_func_t func,
+ for (i=0; i < NB_VDARGS; i++) {
+ // Only the lower half of the vdarg doubleword arg will be used as input by mtvsrwa
+ unsigned int * src = (unsigned int *)&vdargs[i];
+- src++;
++ if (!isLE)
++ src++;
+ r14 = vdargs[i];
+ vec_out = (vector unsigned long long){ 0ULL, 0ULL };
+
+ (*func)();
+ // Only doubleword 0 is used in output
+ dst = (unsigned long long *) &vec_out;
++ if (isLE)
++ dst++;
+ printf("%s: %08x => %016llx\n", name, *src, *dst);
+ }
+ }
+@@ -1222,16 +1236,27 @@ static void test_av_dint_two_args (const char* name, test_func_t func,
+ unsigned int * dst_int;
+ int i,j;
+ int family = test_flags & PPC_FAMILY;
+- int is_vpkudum;
++ int is_vpkudum, is_vpmsumd;
+ if (strcmp(name, "vpkudum") == 0)
+ is_vpkudum = 1;
+ else
+ is_vpkudum = 0;
+
++ if (strcmp(name, "vpmsumd") == 0)
++ is_vpmsumd = 1;
++ else
++ is_vpmsumd = 0;
++
+ for (i = 0; i < NB_VDARGS; i+=2) {
+- vec_inA = (vector unsigned long long){ vdargs[i], vdargs[i+1] };
++ if (isLE && family == PPC_ALTIVECQ)
++ vec_inA = (vector unsigned long long){ vdargs[i+1], vdargs[i] };
++ else
++ vec_inA = (vector unsigned long long){ vdargs[i], vdargs[i+1] };
+ for (j = 0; j < NB_VDARGS; j+=2) {
+- vec_inB = (vector unsigned long long){ vdargs[j], vdargs[j+1] };
++ if (isLE && family == PPC_ALTIVECQ)
++ vec_inB = (vector unsigned long long){ vdargs[j+1], vdargs[j] };
++ else
++ vec_inB = (vector unsigned long long){ vdargs[j], vdargs[j+1] };
+ vec_out = (vector unsigned long long){ 0,0 };
+
+ (*func)();
+@@ -1244,12 +1269,32 @@ static void test_av_dint_two_args (const char* name, test_func_t func,
+ printf("Inputs: %08llx %08llx %08llx %08llx\n", vdargs[i] & 0x00000000ffffffffULL,
+ vdargs[i+1] & 0x00000000ffffffffULL, vdargs[j] & 0x00000000ffffffffULL,
+ vdargs[j+1] & 0x00000000ffffffffULL);
+- printf(" Output: %08x %08x %08x %08x\n", dst_int[0], dst_int[1],
+- dst_int[2], dst_int[3]);
++ if (isLE)
++ printf(" Output: %08x %08x %08x %08x\n", dst_int[2], dst_int[3],
++ dst_int[0], dst_int[1]);
++ else
++ printf(" Output: %08x %08x %08x %08x\n", dst_int[0], dst_int[1],
++ dst_int[2], dst_int[3]);
++ } else if (is_vpmsumd) {
++ printf("%016llx @@ %016llx ", vdargs[i], vdargs[j]);
++ if (isLE)
++ printf(" ==> %016llx\n", dst[1]);
++ else
++ printf(" ==> %016llx\n", dst[0]);
++ printf("\t%016llx @@ %016llx ", vdargs[i+1], vdargs[j+1]);
++ if (isLE)
++ printf(" ==> %016llx\n", dst[0]);
++ else
++ printf(" ==> %016llx\n", dst[1]);
+ } else if (family == PPC_ALTIVECQ) {
+- printf("%016llx%016llx @@ %016llx%016llx ==> %016llx%016llx\n",
+- vdargs[i], vdargs[i+1], vdargs[j], vdargs[j+1],
+- dst[0], dst[1]);
++ if (isLE)
++ printf("%016llx%016llx @@ %016llx%016llx ==> %016llx%016llx\n",
++ vdargs[i], vdargs[i+1], vdargs[j], vdargs[j+1],
++ dst[1], dst[0]);
++ else
++ printf("%016llx%016llx @@ %016llx%016llx ==> %016llx%016llx\n",
++ vdargs[i], vdargs[i+1], vdargs[j], vdargs[j+1],
++ dst[0], dst[1]);
+ } else {
+ printf("%016llx @@ %016llx ", vdargs[i], vdargs[j]);
+ printf(" ==> %016llx\n", dst[0]);
+@@ -1311,9 +1356,15 @@ static void test_av_bcd (const char* name, test_func_t func,
+ int i, j;
+
+ for (i = 0; i < NUM_VBCD_VALS; i+=2) {
+- vec_inA = (vector unsigned long long){ vbcd_args[i], vbcd_args[i +1 ] };
++ if (isLE)
++ vec_inA = (vector unsigned long long){ vbcd_args[i+1], vbcd_args[i] };
++ else
++ vec_inA = (vector unsigned long long){ vbcd_args[i], vbcd_args[i+1] };
+ for (j = 0; j < NUM_VBCD_VALS; j+=2) {
+- vec_inB = (vector unsigned long long){ vbcd_args[j], vbcd_args[j +1 ] };
++ if (isLE)
++ vec_inB = (vector unsigned long long){ vbcd_args[j+1], vbcd_args[j] };
++ else
++ vec_inB = (vector unsigned long long){ vbcd_args[j], vbcd_args[j+1] };
+ vec_out = (vector unsigned long long){ 0, 0 };
+
+ for (PS_bit = 0; PS_bit < 2; PS_bit++) {
+@@ -1323,7 +1374,10 @@ static void test_av_bcd (const char* name, test_func_t func,
+ printf("%016llx || %016llx @@ %016llx || %016llx",
+ vbcd_args[i], vbcd_args[i + 1],
+ vbcd_args[j], vbcd_args[j + 1]);
+- printf(" ==> %016llx || %016llx\n", dst[0], dst[1]);
++ if (isLE)
++ printf(" ==> %016llx || %016llx\n", dst[1], dst[0]);
++ else
++ printf(" ==> %016llx || %016llx\n", dst[0], dst[1]);
+ }
+ }
+ }
+@@ -1349,8 +1403,12 @@ static void test_av_dint_to_int_two_args (const char* name, test_func_t func,
+ printf("%016llx, %016llx @@ %016llx, %016llx ",
+ vdargs_x[i], vdargs_x[i+1],
+ vdargs_x[j], vdargs_x[j+1]);
+- printf(" ==> %08x %08x %08x %08x\n", dst_int[0], dst_int[1],
+- dst_int[2], dst_int[3]);
++ if (isLE)
++ printf(" ==> %08x %08x %08x %08x\n", dst_int[2], dst_int[3],
++ dst_int[0], dst_int[1]);
++ else
++ printf(" ==> %08x %08x %08x %08x\n", dst_int[0], dst_int[1],
++ dst_int[2], dst_int[3]);
+ }
+ }
+ }
+@@ -1365,16 +1423,26 @@ static void test_av_wint_two_args_dres (const char* name, test_func_t func,
+ int i,j;
+
+ for (i = 0; i < NB_VWARGS; i+=4) {
+- vec_inA_wd = (vector unsigned int){ vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3] };
++ if (isLE)
++ vec_inA_wd = (vector unsigned int){ vwargs[i+3], vwargs[i+2], vwargs[i+1], vwargs[i] };
++ else
++ vec_inA_wd = (vector unsigned int){ vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3] };
+ for (j = 0; j < NB_VWARGS; j+=4) {
+- vec_inB_wd = (vector unsigned int){ vwargs[j], vwargs[j+1], vwargs[j+2], vwargs[j+3] };
++ if (isLE)
++ vec_inB_wd = (vector unsigned int){ vwargs[j+3], vwargs[j+2], vwargs[j+1], vwargs[j] };
++ else
++ vec_inB_wd = (vector unsigned int){ vwargs[j], vwargs[j+1], vwargs[j+2], vwargs[j+3] };
+ vec_out = (vector unsigned long long){ 0, 0 };
+
+ (*func)();
+ dst = (unsigned long long *)&vec_out;
+ printf("%s: ", name);
+- printf("%08x %08x %08x %08x ==> %016llx %016llx\n",
+- vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3], dst[0], dst[1]);
++ if (isLE)
++ printf("%08x %08x %08x %08x ==> %016llx %016llx\n",
++ vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3], dst[1], dst[0]);
++ else
++ printf("%08x %08x %08x %08x ==> %016llx %016llx\n",
++ vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3], dst[0], dst[1]);
+ }
+ }
+ }
+@@ -1387,14 +1455,21 @@ static void test_av_wint_one_arg_dres (const char* name, test_func_t func,
+ unsigned long long * dst;
+ int i;
+ for (i = 0; i < NB_VWARGS; i+=4) {
+- vec_inB_wd = (vector unsigned int){ vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3] };
++ if (isLE)
++ vec_inB_wd = (vector unsigned int){ vwargs[i+3], vwargs[i+2], vwargs[i+1], vwargs[i] };
++ else
++ vec_inB_wd = (vector unsigned int){ vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3] };
+ vec_out = (vector unsigned long long){ 0, 0 };
+
+ (*func)();
+ dst = (unsigned long long *)&vec_out;
+ printf("%s: ", name);
+- printf("%08x %08x %08x %08x ==> %016llx %016llx\n",
+- vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3], dst[0], dst[1]);
++ if (isLE)
++ printf("%08x %08x %08x %08x ==> %016llx %016llx\n",
++ vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3], dst[1], dst[0]);
++ else
++ printf("%08x %08x %08x %08x ==> %016llx %016llx\n",
++ vwargs[i], vwargs[i+1], vwargs[i+2], vwargs[i+3], dst[0], dst[1]);
+ }
+ }
+
+@@ -1556,28 +1631,52 @@ static void test_av_dint_three_args (const char* name, test_func_t func,
+ 0xf000000000000000ULL, 0xf000000000000001ULL
+ };
+ for (i = 0; i < NB_VDARGS; i+=2) {
+- vec_inA = (vector unsigned long long){ vdargs[i], vdargs[i+1] };
++ if (isLE)
++ vec_inA = (vector unsigned long long){ vdargs[i+1], vdargs[i] };
++ else
++ vec_inA = (vector unsigned long long){ vdargs[i], vdargs[i+1] };
+ for (j = 0; j < NB_VDARGS; j+=2) {
+- vec_inB = (vector unsigned long long){ vdargs[j], vdargs[j+1] };
++ if (isLE)
++ vec_inB = (vector unsigned long long){ vdargs[j+1], vdargs[j] };
++ else
++ vec_inB = (vector unsigned long long){ vdargs[j], vdargs[j+1] };
+ for (k = 0; k < 4; k+=2) {
+- if (family == PPC_ALTIVECQ)
+- vec_inC = (vector unsigned long long){ cin_vals[k], cin_vals[k+1] };
+- else
+- vec_inC = (vector unsigned long long){ vdargs[k], vdargs[k+1] };
++ if (family == PPC_ALTIVECQ) {
++ if (isLE)
++ vec_inC = (vector unsigned long long){ cin_vals[k+1], cin_vals[k] };
++ else
++ vec_inC = (vector unsigned long long){ cin_vals[k], cin_vals[k+1] };
++ } else {
++ if (isLE)
++ vec_inC = (vector unsigned long long){ vdargs[k+1], vdargs[k] };
++ else
++ vec_inC = (vector unsigned long long){ vdargs[k], vdargs[k+1] };
++ }
+ vec_out = (vector unsigned long long){ 0,0 };
+
+ (*func)();
+ dst = (unsigned long long*)&vec_out;
+ printf("%s: ", name);
+ if (family == PPC_ALTIVECQ) {
+- printf("%016llx%016llx @@ %016llx%016llx @@ %llx ==> %016llx%016llx\n",
+- vdargs[i], vdargs[i+1], vdargs[j], vdargs[j+1], cin_vals[k+1],
+- dst[0], dst[1]);
++ if (isLE)
++ printf("%016llx%016llx @@ %016llx%016llx @@ %llx ==> %016llx%016llx\n",
++ vdargs[i], vdargs[i+1], vdargs[j], vdargs[j+1], cin_vals[k+1],
++ dst[1], dst[0]);
++ else
++ printf("%016llx%016llx @@ %016llx%016llx @@ %llx ==> %016llx%016llx\n",
++ vdargs[i], vdargs[i+1], vdargs[j], vdargs[j+1], cin_vals[k+1],
++ dst[0], dst[1]);
+ } else {
+ printf("%016llx @@ %016llx @@ %016llx ", vdargs[i], vdargs[j], vdargs[k]);
+- printf(" ==> %016llx\n", dst[0]);
++ if (isLE)
++ printf(" ==> %016llx\n", dst[1]);
++ else
++ printf(" ==> %016llx\n", dst[0]);
+ printf("\t%016llx @@ %016llx @@ %016llx ", vdargs[i+1], vdargs[j+1], vdargs[k+1]);
+- printf(" ==> %016llx\n", dst[1]);
++ if (isLE)
++ printf(" ==> %016llx\n", dst[0]);
++ else
++ printf(" ==> %016llx\n", dst[1]);
+ }
+ }
+ }
+diff --git a/none/tests/ppc64/test_isa_2_07_part2.c b/none/tests/ppc64/test_isa_2_07_part2.c
+index f5ec672..a2458a9 100644
+--- a/none/tests/ppc64/test_isa_2_07_part2.c
++++ b/none/tests/ppc64/test_isa_2_07_part2.c
+@@ -40,6 +40,12 @@ typedef uint32_t HWord_t;
+ typedef uint64_t HWord_t;
+ #endif /* __powerpc64__ */
+
++#ifdef VGP_ppc64le_linux
++#define isLE 1
++#else
++#define isLE 0
++#endif
++
+ register HWord_t r14 __asm__ ("r14");
+ register HWord_t r15 __asm__ ("r15");
+ register HWord_t r16 __asm__ ("r16");
+@@ -341,6 +347,16 @@ static unsigned int viargs[] __attribute__ ((aligned (16))) = { 0x80000001,
+ #define NUM_VIARGS_INTS (sizeof viargs/sizeof viargs[0])
+ #define NUM_VIARGS_VECS (NUM_VIARGS_INTS/4)
+
++
++static unsigned long long vdargs[] __attribute__ ((aligned (16))) = {
++ 0x0102030405060708ULL,
++ 0x090A0B0C0E0D0E0FULL,
++ 0xF1F2F3F4F5F6F7F8ULL,
++ 0xF9FAFBFCFEFDFEFFULL
++};
++#define NUM_VDARGS_INTS (sizeof vdargs/sizeof vdargs[0])
++#define NUM_VDARGS_VECS (NUM_VDARGS_INTS/2)
++
+ typedef void (*test_func_t)(void);
+
+ struct test_table
+@@ -727,7 +743,7 @@ static vx_fp_test_basic_t vx_fp_tests[] = {
+
+ static vx_fp_test2_t
+ vsx_one_fp_arg_tests[] = {
+- { &test_xscvdpspn, "xscvdpspn", NULL, 20, SINGLE_TEST_SINGLE_RES, VX_SCALAR_SP_TO_VECTOR_SP, "conv"},
++ { &test_xscvdpspn, "xscvdpspn", NULL, 20, DOUBLE_TEST_SINGLE_RES, VX_SCALAR_SP_TO_VECTOR_SP, "conv"},
+ { &test_xscvspdpn, "xscvspdpn", NULL, 20, SINGLE_TEST, VX_DEFAULT, "conv"},
+ { &test_xsresp, "xsresp", NULL, 20, DOUBLE_TEST, VX_ESTIMATE, "1/x"},
+ { &test_xsrsp, "xsrsp", NULL, 20, DOUBLE_TEST, VX_DEFAULT, "round"},
+@@ -749,7 +765,7 @@ ldst_tests[] = {
+ { &test_stxsspx, "stxsspx", DOUBLE_TEST_SINGLE_RES, vstg, 0, VSX_STORE },
+ { &test_stxsiwx, "stxsiwx", SINGLE_TEST_SINGLE_RES, vstg, 4, VSX_STORE },
+ { &test_lxsiwax, "lxsiwax", SINGLE_TEST, viargs, 0, VSX_LOAD },
+- { &test_lxsiwzx, "lxsiwzx", SINGLE_TEST, viargs, 1, VSX_LOAD },
++ { &test_lxsiwzx, "lxsiwzx", SINGLE_TEST, viargs, 4, VSX_LOAD },
+ { &test_lxsspx, "lxsspx", SINGLE_TEST, NULL, 0, VSX_LOAD },
+ { NULL, NULL, 0, NULL, 0, 0 } };
+
+@@ -881,8 +897,19 @@ static void test_vx_fp_ops(void)
+ test_func_t func;
+ int k;
+ char * test_name = (char *)malloc(20);
+- k = 0;
++ void * vecA_void_ptr, * vecB_void_ptr, * vecOut_void_ptr;
++
++ if (isLE) {
++ vecA_void_ptr = (void *)&vec_inA + 8;
++ vecB_void_ptr = (void *)&vec_inB + 8;
++ vecOut_void_ptr = (void *)&vec_out + 8;
++ } else {
++ vecA_void_ptr = (void *)&vec_inA;
++ vecB_void_ptr = (void *)&vec_inB;
++ vecOut_void_ptr = (void *)&vec_out;
++ }
+
++ k = 0;
+ build_special_fargs_table();
+ while ((func = vx_fp_tests[k].test_func)) {
+ int i, repeat = 0;
+@@ -932,8 +959,8 @@ again:
+ pv = (unsigned int *)&vec_out;
+
+ // Only need to copy one doubleword into each vector's element 0
+- memcpy(&vec_inA, inA, 8);
+- memcpy(&vec_inB, inB, 8);
++ memcpy(vecA_void_ptr, inA, 8);
++ memcpy(vecB_void_ptr, inB, 8);
+
+ // clear vec_out
+ for (idx = 0; idx < 4; idx++, pv++)
+@@ -963,18 +990,20 @@ again:
+ * src2 <= VSX[XT]
+ * src3 <= VSX[XB]
+ */
+- memcpy(&vec_out, inB, 8); // src2
+- memcpy(&vec_inB, &spec_fargs[extra_arg_idx], 8); //src3
++ memcpy(vecOut_void_ptr, inB, 8); // src2
++ memcpy(vecB_void_ptr, &spec_fargs[extra_arg_idx], 8); //src3
+ frbp = (unsigned long long *)&spec_fargs[extra_arg_idx];
+ } else {
+ // Don't need to init src2, as it's done before the switch()
+- memcpy(&vec_out, &spec_fargs[extra_arg_idx], 8); //src3
++ memcpy(vecOut_void_ptr, &spec_fargs[extra_arg_idx], 8); //src3
+ }
+- memcpy(&vsr_XT, &vec_out, 8);
++ memcpy(&vsr_XT, vecOut_void_ptr, 8);
+ }
+
+ (*func)();
+ dst = (unsigned long long *) &vec_out;
++ if (isLE)
++ dst++;
+
+ if (test_type == VX_FP_OTHER)
+ printf("#%d: %s %016llx %016llx = %016llx\n", i, test_name,
+@@ -1033,6 +1062,8 @@ static void test_vsx_one_fp_arg(void)
+ {
+ test_func_t func;
+ int k;
++ void * vecB_void_ptr;
++
+ k = 0;
+ build_special_fargs_table();
+
+@@ -1047,26 +1078,13 @@ static void test_vsx_one_fp_arg(void)
+ /* size of result */
+ Bool dp_res = IS_DP_RESULT(test_group.precision);
+ Bool is_sqrt = (strstr(test_group.name, "sqrt")) ? True : False;
+- Bool is_scalar = (strstr(test_group.name, "xs")) ? True : False;
+- Bool sparse_sp = False;
+- int stride = dp ? 2 : 4;
+- int loops = is_scalar ? 1 : stride;
+- stride = is_scalar ? 1: stride;
+-
+- /* For conversions of single to double, the 128-bit input register is sparsely populated:
+- * |___ SP___|_Unused_|___SP___|__Unused__| // for vector op
+- * or
+- * |___ SP___|_Unused_|_Unused_|__Unused__| // for scalar op
+- *
+- * For the vector op case, we need to adjust stride from '4' to '2', since
+- * we'll only be loading two values per loop into the input register.
+- */
+- if (!dp && !is_scalar && test_group.test_type == VX_CONV_TO_DOUBLE) {
+- sparse_sp = True;
+- stride = 2;
++
++ vecB_void_ptr = (void *)&vec_inB;
++ if (isLE) {
++ vecB_void_ptr += dp? 8 : 12;
+ }
+
+- for (i = 0; i < test_group.num_tests; i+=stride) {
++ for (i = 0; i < test_group.num_tests; i++) {
+ unsigned int * pv;
+ void * inB;
+
+@@ -1076,13 +1094,26 @@ static void test_vsx_one_fp_arg(void)
+ *pv = 0;
+
+ if (dp) {
+- int j;
++ int vec_out_idx;
+ unsigned long long * frB_dp;
+- for (j = 0; j < loops; j++) {
+- inB = (void *)&spec_fargs[i + j];
+- // copy double precision FP into vector element i
+- memcpy(((void *)&vec_inB) + (j * 8), inB, 8);
++ if (isLE)
++ vec_out_idx = dp_res ? 1 : 3;
++ else
++ vec_out_idx = 0;
++
++ if (test_group.test_type == VX_SCALAR_SP_TO_VECTOR_SP) {
++ /* Take a single-precision value stored in double word element 0
++ * of src in double-precision format and convert to single-
++ * precision and store in word element 0 of dst.
++ */
++ double input = spec_sp_fargs[i];
++ memcpy(vecB_void_ptr, (void *)&input, 8);
++ } else {
++ inB = (void *)&spec_fargs[i];
++ // copy double precision FP into input vector element 0
++ memcpy(vecB_void_ptr, inB, 8);
+ }
++
+ // execute test insn
+ (*func)();
+ if (dp_res)
+@@ -1090,56 +1121,34 @@ static void test_vsx_one_fp_arg(void)
+ else
+ dst_sp = (unsigned int *) &vec_out;
+
+- printf("#%d: %s ", i/stride, test_group.name);
+- for (j = 0; j < loops; j++) {
+- if (j)
+- printf("; ");
+- frB_dp = (unsigned long long *)&spec_fargs[i + j];
+- printf("%s(%016llx)", test_group.op, *frB_dp);
+- if (test_group.test_type == VX_ESTIMATE)
+- {
+- Bool res;
+- res = check_reciprocal_estimate(is_sqrt, i + j, j);
+- printf(" ==> %s)", res ? "PASS" : "FAIL");
+- } else if (dp_res) {
+- printf(" = %016llx", dst_dp[j]);
+- } else {
+- printf(" = %08x", dst_sp[j]);
+- }
++ printf("#%d: %s ", i, test_group.name);
++ frB_dp = (unsigned long long *)&spec_fargs[i];
++ printf("%s(%016llx)", test_group.op, *frB_dp);
++ if (test_group.test_type == VX_ESTIMATE)
++ {
++ Bool res;
++ res = check_reciprocal_estimate(is_sqrt, i, vec_out_idx);
++ printf(" ==> %s)", res ? "PASS" : "FAIL");
++ } else if (dp_res) {
++ printf(" = %016llx", dst_dp[vec_out_idx]);
++ } else {
++ printf(" = %08x", dst_sp[vec_out_idx]);
+ }
++
+ printf("\n");
+ } else { // single precision test type
+- int j;
++ int vec_out_idx;
++ if (isLE)
++ vec_out_idx = dp_res ? 1 : 3;
++ else
++ vec_out_idx = 0;
+ // Clear input vector
+ pv = (unsigned int *)&vec_inB;
+ for (idx = 0; idx < 4; idx++, pv++)
+ *pv = 0;
+-
+- if (test_group.test_type == VX_SCALAR_SP_TO_VECTOR_SP) {
+- /* Take a single-precision value stored in double word element 0
+- * of src in double-precision format and convert to single-
+- * precision and store in word element 0 of dst.
+- */
+- double input = spec_sp_fargs[i];
+- memcpy(((void *)&vec_inB), (void *)&input, 8);
+- } else {
+- int skip_slot;
+- if (sparse_sp) {
+- skip_slot = 1;
+- loops = 2;
+- } else {
+- skip_slot = 0;
+- }
+- for (j = 0; j < loops; j++) {
+- inB = (void *)&spec_sp_fargs[i + j];
+- // copy single precision FP into vector element i
+-
+- if (skip_slot && j > 0)
+- memcpy(((void *)&vec_inB) + ((j + j) * 4), inB, 4);
+- else
+- memcpy(((void *)&vec_inB) + (j * 4), inB, 4);
+- }
+- }
++ inB = (void *)&spec_sp_fargs[i];
++ // copy single precision FP into input vector element i
++ memcpy(vecB_void_ptr, inB, 4);
+ // execute test insn
+ (*func)();
+ if (dp_res)
+@@ -1147,16 +1156,13 @@ static void test_vsx_one_fp_arg(void)
+ else
+ dst_sp = (unsigned int *) &vec_out;
+ // print result
+- printf("#%d: %s ", i/stride, test_group.name);
+- for (j = 0; j < loops; j++) {
+- if (j)
+- printf("; ");
+- printf("%s(%08x)", test_group.op, *((unsigned int *)&spec_sp_fargs[i + j]));
++ printf("#%d: %s ", i, test_group.name);
++ printf("%s(%08x)", test_group.op, *((unsigned int *)&spec_sp_fargs[i]));
+ if (dp_res)
+- printf(" = %016llx", dst_dp[j]);
++ printf(" = %016llx", dst_dp[vec_out_idx]);
+ else
+- printf(" = %08x", dst_sp[j]);
+- }
++ printf(" = %08x", dst_sp[vec_out_idx]);
++
+ printf("\n");
+ }
+ }
+@@ -1170,6 +1176,15 @@ static void test_vsx_two_fp_arg(void)
+ {
+ test_func_t func;
+ int k = 0;
++ void * vecA_void_ptr, * vecB_void_ptr;
++
++ if (isLE) {
++ vecA_void_ptr = (void *)&vec_inA + 8;
++ vecB_void_ptr = (void *)&vec_inB + 8;
++ } else {
++ vecA_void_ptr = (void *)&vec_inA;
++ vecB_void_ptr = (void *)&vec_inB;
++ }
+
+ build_special_fargs_table();
+ while ((func = vx_simple_scalar_fp_tests[k].test_func)) {
+@@ -1191,10 +1206,12 @@ static void test_vsx_two_fp_arg(void)
+ frap = (unsigned long long *)&spec_fargs[aTest.fra_idx];
+ frbp = (unsigned long long *)&spec_fargs[aTest.frb_idx];
+ // Only need to copy one doubleword into each vector's element 0
+- memcpy(&vec_inA, inA, 8);
+- memcpy(&vec_inB, inB, 8);
++ memcpy(vecA_void_ptr, inA, 8);
++ memcpy(vecB_void_ptr, inB, 8);
+ (*func)();
+ dst = (unsigned long long *) &vec_out;
++ if (isLE)
++ dst++;
+ printf("#%d: %s %016llx,%016llx => %016llx\n", i, test_group.name,
+ *frap, *frbp, *dst);
+ }
+@@ -1214,84 +1231,91 @@ static void _do_store_test (ldst_test_t storeTest)
+ unsigned int *dst32;
+ unsigned int i, idx;
+ unsigned int * pv = (unsigned int *) storeTest.base_addr;
++ void * vecA_void_ptr;
++
++ if (isLE) {
++ if (storeTest.precision == SINGLE_TEST_SINGLE_RES)
++ vecA_void_ptr = (void *)&vec_inA + 8;
++ } else {
++ if (storeTest.precision == SINGLE_TEST_SINGLE_RES)
++ vecA_void_ptr = (void *)&vec_inA + 4;
++ else
++ vecA_void_ptr = (void *)&vec_inA;
++ }
+
+ func = storeTest.test_func;
+ r14 = (HWord_t) storeTest.base_addr;
+ r15 = (HWord_t) storeTest.offset;
+
+- if (storeTest.precision == DOUBLE_TEST_SINGLE_RES) {
+- /* source is single precision stored in double precision format */
+- /* test some of the pre-defined single precision values */
+- for (i = 0; i < nb_special_fargs; i+=3) {
+- // clear out storage destination
+- for (idx = 0; idx < 4; idx++)
+- *(pv + idx) = 0;
+-
+- printf( "%s:", storeTest.name );
++ /* test some of the pre-defined single precision values */
++ for (i = 0; i < nb_special_fargs; i+=3) {
++ // clear out storage destination
++ for (idx = 0; idx < 4; idx++)
++ *(pv + idx) = 0;
++
++ printf( "%s:", storeTest.name );
++ if (storeTest.precision == SINGLE_TEST_SINGLE_RES)
++ {
++ unsigned int * arg_ptr = (unsigned int *)&spec_sp_fargs[i];
++ memcpy(vecA_void_ptr, arg_ptr, sizeof(unsigned int));
++ printf(" %08x ==> ", *arg_ptr);
++ } else {
+ unsigned long long * dp;
+ double input = spec_sp_fargs[i];
+ dp = (unsigned long long *)&input;
+- memcpy(&vec_inA, dp, sizeof(unsigned long long));
++ memcpy(vecA_void_ptr, dp, sizeof(unsigned long long));
+ printf(" %016llx ==> ", *dp);
+-
+- // execute test insn
+- (*func)();
+- dst32 = (unsigned int*)(storeTest.base_addr + storeTest.offset);
+- printf( "%08x\n", *dst32);
+ }
+- } else {
+- // source is an integer word
+- for (i = 0; i < NUM_VIARGS_INTS; i++) {
+- // clear out storage destination
+- for (idx = 0; idx < 4; idx++)
+- *(pv + idx) = 0;
+- printf( "%s:", storeTest.name );
+- unsigned int * pi = (unsigned int *)&vec_inA;
+- memcpy(pi + 1, &viargs[i], sizeof(unsigned int));
+- printf(" %08x ==> ", *(pi + 1));
+
+- // execute test insn
+- (*func)();
+- dst32 = (unsigned int*)(storeTest.base_addr + storeTest.offset);
+- printf( "%08x\n", *dst32);
+- }
++ // execute test insn
++ (*func)();
++ dst32 = (unsigned int*)(storeTest.base_addr);
++ dst32 += (storeTest.offset/sizeof(int));
++ printf( "%08x\n", *dst32);
+ }
++
+ printf("\n");
+ }
+
+-static void _do_load_test(ldst_test_t storeTest)
++static void _do_load_test(ldst_test_t loadTest)
+ {
+ test_func_t func;
+ unsigned int i;
+ unsigned long long * dst_dp;
+
+- func = storeTest.test_func;
+- r15 = (HWord_t) storeTest.offset;
++ func = loadTest.test_func;
++ r15 = (HWord_t) loadTest.offset;
+
+- if (storeTest.base_addr == NULL) {
++ if (loadTest.base_addr == NULL) {
+ /* Test lxsspx: source is single precision value, so let's */
+ /* test some of the pre-defined single precision values. */
+- for (i = 0; i + storeTest.offset < nb_special_fargs; i+=3) {
+- unsigned int * sp = (unsigned int *)&spec_sp_fargs[i + storeTest.offset];
+- printf( "%s:", storeTest.name );
++ int num_loops = (loadTest.offset == 0) ? nb_special_fargs : (nb_special_fargs - (loadTest.offset/sizeof(int)));
++ for (i = 0; i < num_loops; i+=3) {
++ unsigned int * sp = (unsigned int *)&spec_sp_fargs[i + (loadTest.offset/sizeof(int))];
++ printf( "%s:", loadTest.name );
+ printf(" %08x ==> ", *sp);
+ r14 = (HWord_t)&spec_sp_fargs[i];
+
+ // execute test insn
+ (*func)();
+ dst_dp = (unsigned long long *) &vec_out;
++ if (isLE)
++ dst_dp++;
+ printf("%016llx\n", *dst_dp);
+ }
+ } else {
+ // source is an integer word
+- for (i = 0; i < NUM_VIARGS_INTS; i++) {
+- printf( "%s:", storeTest.name );
+- r14 = (HWord_t)&viargs[i + storeTest.offset];
+- printf(" %08x ==> ", viargs[i + storeTest.offset]);
++ int num_loops = (loadTest.offset == 0) ? NUM_VIARGS_INTS : (NUM_VIARGS_INTS - (loadTest.offset/sizeof(int)));
++ for (i = 0; i < num_loops; i++) {
++ printf( "%s:", loadTest.name );
++ r14 = (HWord_t)&viargs[i];
++ printf(" %08x ==> ", viargs[i + (loadTest.offset/sizeof(int))]);
+
+ // execute test insn
+ (*func)();
+ dst_dp = (unsigned long long *) &vec_out;
++ if (isLE)
++ dst_dp++;
+ printf("%016llx\n", *dst_dp);
+ }
+ }
+@@ -1318,24 +1342,32 @@ static void test_xs_conv_ops(void)
+
+ test_func_t func;
+ int k = 0;
++ void * vecB_void_ptr;
++
++ if (isLE)
++ vecB_void_ptr = (void *)&vec_inB + 8;
++ else
++ vecB_void_ptr = (void *)&vec_inB;
+
+ build_special_fargs_table();
+ while ((func = xs_conv_tests[k].test_func)) {
+ int i;
+ unsigned long long * dst;
+ xs_conv_test_t test_group = xs_conv_tests[k];
+- for (i = 0; i < NUM_VIARGS_INTS; i++) {
+- unsigned int * inB, * pv;
++ for (i = 0; i < NUM_VDARGS_INTS; i++) {
++ unsigned long long * inB, * pv;
+ int idx;
+- inB = (unsigned int *)&viargs[i];
+- memcpy(&vec_inB, inB, 4);
+- pv = (unsigned int *)&vec_out;
++ inB = (unsigned long long *)&vdargs[i];
++ memcpy(vecB_void_ptr, inB, 8);
++ pv = (unsigned long long *)&vec_out;
+ // clear vec_out
+- for (idx = 0; idx < 4; idx++, pv++)
+- *pv = 0;
++ for (idx = 0; idx < 2; idx++, pv++)
++ *pv = 0ULL;
+ (*func)();
+ dst = (unsigned long long *) &vec_out;
+- printf("#%d: %s %08x => %016llx\n", i, test_group.name, viargs[i], *dst);
++ if (isLE)
++ dst++;
++ printf("#%d: %s %016llx => %016llx\n", i, test_group.name, vdargs[i], *dst);
+ }
+ k++;
+ printf("\n");
+diff --git a/none/tests/ppc64/test_isa_2_07_part2.stdout.exp b/none/tests/ppc64/test_isa_2_07_part2.stdout.exp
+index e7c43c1..3539405 100644
+--- a/none/tests/ppc64/test_isa_2_07_part2.stdout.exp
++++ b/none/tests/ppc64/test_isa_2_07_part2.stdout.exp
+@@ -651,26 +651,26 @@ Test VSX floating point instructions
+
+
+ Test VSX vector and scalar single argument instructions
+-#0: xscvdpspn conv(3ec00000) = 3ec00000
+-#1: xscvdpspn conv(42780000) = 42780000
+-#2: xscvdpspn conv(00000000) = 00000000
+-#3: xscvdpspn conv(7f800000) = 7f800000
+-#4: xscvdpspn conv(00000000) = 00000000
+-#5: xscvdpspn conv(00000000) = 00000000
+-#6: xscvdpspn conv(80000000) = 80000000
+-#7: xscvdpspn conv(7f800000) = 7f800000
+-#8: xscvdpspn conv(ff800000) = ff800000
+-#9: xscvdpspn conv(7fbfffff) = 7fbfffff
+-#10: xscvdpspn conv(ffbfffff) = ffbfffff
+-#11: xscvdpspn conv(7fc00000) = 7fc00000
+-#12: xscvdpspn conv(ffc00000) = ffc00000
+-#13: xscvdpspn conv(80000000) = 80000000
+-#14: xscvdpspn conv(c683287b) = c683287b
+-#15: xscvdpspn conv(49192c2d) = 49192c2d
+-#16: xscvdpspn conv(49c1288d) = 49c1288d
+-#17: xscvdpspn conv(418977ad) = 418977ad
+-#18: xscvdpspn conv(428a5faf) = 428a5faf
+-#19: xscvdpspn conv(44bb5fcc) = 44bb5fcc
++#0: xscvdpspn conv(3fd8000000000000) = 3ec00000
++#1: xscvdpspn conv(404f000000000000) = 42780000
++#2: xscvdpspn conv(0018000000b77501) = 00000000
++#3: xscvdpspn conv(7fe800000000051b) = 7f800000
++#4: xscvdpspn conv(0123214569900000) = 00000000
++#5: xscvdpspn conv(0000000000000000) = 00000000
++#6: xscvdpspn conv(8000000000000000) = 80000000
++#7: xscvdpspn conv(7ff0000000000000) = 7f800000
++#8: xscvdpspn conv(fff0000000000000) = ff800000
++#9: xscvdpspn conv(7ff7ffffffffffff) = 7fbfffff
++#10: xscvdpspn conv(fff7ffffffffffff) = ffbfffff
++#11: xscvdpspn conv(7ff8000000000000) = 7fc00000
++#12: xscvdpspn conv(fff8000000000000) = ffc00000
++#13: xscvdpspn conv(8008340000078000) = 80000000
++#14: xscvdpspn conv(c0d0650f5a07b353) = c683287b
++#15: xscvdpspn conv(41232585a9900000) = 49192c2d
++#16: xscvdpspn conv(41382511a2000000) = 49c1288d
++#17: xscvdpspn conv(40312ef5a9300000) = 418977ad
++#18: xscvdpspn conv(40514bf5d2300000) = 428a5faf
++#19: xscvdpspn conv(40976bf982440000) = 44bb5fcc
+
+ #0: xscvspdpn conv(3ec00000) = 3fd8000000000000
+ #1: xscvspdpn conv(42780000) = 404f000000000000
+@@ -783,23 +783,15 @@ Test VSX logic instructions
+ #2: xxlnand (80000001 89abcdef 00112233 74556677, 80000001 89abcdef 00112233 74556677) ==> 7ffffffe 76543210 ffeeddcc 8baa9988
+
+ Test VSX scalar integer conversion instructions
+-#0: xscvsxdsp 80000001 => c3e0000000000000
+-#1: xscvsxdsp 89abcdef => c3dd950c80000000
+-#2: xscvsxdsp 00112233 => 4331223380000000
+-#3: xscvsxdsp 74556677 => 43dd1559a0000000
+-#4: xscvsxdsp 00001abb => 42babb89a0000000
+-#5: xscvsxdsp 00000001 => 41f89abce0000000
+-#6: xscvsxdsp 31929394 => 43c8c949c0000000
+-#7: xscvsxdsp a1a2a3a4 => c3d7975720000000
+-
+-#0: xscvuxdsp 80000001 => 43e0000000000000
+-#1: xscvuxdsp 89abcdef => 43e13579c0000000
+-#2: xscvuxdsp 00112233 => 4331223380000000
+-#3: xscvuxdsp 74556677 => 43dd1559a0000000
+-#4: xscvuxdsp 00001abb => 42babb89a0000000
+-#5: xscvuxdsp 00000001 => 41f89abce0000000
+-#6: xscvuxdsp 31929394 => 43c8c949c0000000
+-#7: xscvuxdsp a1a2a3a4 => 43e4345480000000
++#0: xscvsxdsp 0102030405060708 => 4370203040000000
++#1: xscvsxdsp 090a0b0c0e0d0e0f => 43a2141620000000
++#2: xscvsxdsp f1f2f3f4f5f6f7f8 => c3ac1a1820000000
++#3: xscvsxdsp f9fafbfcfefdfeff => c398141000000000
++
++#0: xscvuxdsp 0102030405060708 => 4370203040000000
++#1: xscvuxdsp 090a0b0c0e0d0e0f => 43a2141620000000
++#2: xscvuxdsp f1f2f3f4f5f6f7f8 => 43ee3e5e80000000
++#3: xscvuxdsp f9fafbfcfefdfeff => 43ef3f5f80000000
+
+
+ Test VSX load/store dp to sp instructions
+@@ -812,14 +804,13 @@ stxsspx: 41232585a0000000 ==> 49192c2d
+ stxsspx: 40514bf5e0000000 ==> 428a5faf
+
+
+-stxsiwx: 80000001 ==> 80000001
+-stxsiwx: 89abcdef ==> 89abcdef
+-stxsiwx: 00112233 ==> 00112233
+-stxsiwx: 74556677 ==> 74556677
+-stxsiwx: 00001abb ==> 00001abb
+-stxsiwx: 00000001 ==> 00000001
+-stxsiwx: 31929394 ==> 31929394
+-stxsiwx: a1a2a3a4 ==> a1a2a3a4
++stxsiwx: 3ec00000 ==> 3ec00000
++stxsiwx: 7f800000 ==> 7f800000
++stxsiwx: 80000000 ==> 80000000
++stxsiwx: 7fbfffff ==> 7fbfffff
++stxsiwx: ffc00000 ==> ffc00000
++stxsiwx: 49192c2d ==> 49192c2d
++stxsiwx: 428a5faf ==> 428a5faf
+
+
+ lxsiwax: 80000001 ==> ffffffff80000001
+@@ -832,14 +823,13 @@ lxsiwax: 31929394 ==> 0000000031929394
+ lxsiwax: a1a2a3a4 ==> ffffffffa1a2a3a4
+
+
+-lxsiwzx: 89abcdef ==> 00000000abcdef00
+-lxsiwzx: 00112233 ==> 0000000011223374
+-lxsiwzx: 74556677 ==> 0000000055667700
+-lxsiwzx: 00001abb ==> 00000000001abb00
+-lxsiwzx: 00000001 ==> 0000000000000131
+-lxsiwzx: 31929394 ==> 00000000929394a1
+-lxsiwzx: a1a2a3a4 ==> 00000000a2a3a400
+-lxsiwzx: 00000000 ==> 0000000000000010
++lxsiwzx: 89abcdef ==> 0000000089abcdef
++lxsiwzx: 00112233 ==> 0000000000112233
++lxsiwzx: 74556677 ==> 0000000074556677
++lxsiwzx: 00001abb ==> 0000000000001abb
++lxsiwzx: 00000001 ==> 0000000000000001
++lxsiwzx: 31929394 ==> 0000000031929394
++lxsiwzx: a1a2a3a4 ==> 00000000a1a2a3a4
+
+
+ lxsspx: 3ec00000 ==> 3fd8000000000000
+--
+1.8.4.2
+
diff --git a/valgrind.spec b/valgrind.spec
index aa16f2a..d392e12 100644
--- a/valgrind.spec
+++ b/valgrind.spec
@@ -1,12 +1,12 @@
%{?scl:%scl_package valgrind}
-%define svn_date 20140715
-%define svn_rev 14165
+%define svn_date 20140718
+%define svn_rev 14176
Summary: Tool for finding memory management bugs in programs
Name: %{?scl_prefix}valgrind
Version: 3.9.0
-Release: 19.svn%{?svn_date}r%{?svn_rev}%{?dist}
+Release: 20.svn%{?svn_date}r%{?svn_rev}%{?dist}
Epoch: 1
License: GPLv2+
URL: http://www.valgrind.org/
@@ -24,7 +24,7 @@ BuildRoot: %{_tmppath}/%{name}-%{version}-%{release}-root-%(%{__id_u} -n)
%endif
# Note s390x doesn't have an openmpi port available.
-%ifarch %{ix86} x86_64 ppc ppc64 %{arm} aarch64
+%ifarch %{ix86} x86_64 ppc ppc64 ppc64le %{arm} aarch64
%global build_openmpi 1
%else
%global build_openmpi 0
@@ -57,9 +57,15 @@ Patch4: valgrind-3.9.0-ldso-supp.patch
# KDE#327943 - s390x missing index/strchr suppression for ld.so bad backtrace?
Patch5: valgrind-3.9.0-s390x-ld-supp.patch
-# Newer glibc define user_regs_struct and don't include the kernel
-# asm/ptrace.h header that defines user_pt_regs.
-Patch6: valgrind-3.9.0-arm64-user_regs.patch
+# ppc64le
+# Initial PPC LE support KDE#334384
+# PPC LE functional support KDE#334834
+# PPC LE testsuite change KDE#334836
+# Note these require regeneration of the auto* files in %%build.
+Patch1001: valgrind-3.9.0-ppc64le-initial.patch
+Patch1002: valgrind-3.9.0-ppc64le-functional.patch
+Patch1003: valgrind-3.9.0-ppc64le-test.patch
+Patch1004: valgrind-3.9.0-ppc64le-extra.patch
%if %{build_multilib}
# Ensure glibc{,-devel} is installed for both multilib arches
@@ -88,9 +94,12 @@ BuildRequires: %{?scl_prefix}binutils
# gdbserver_tests/filter_make_empty uses ps in test
BuildRequires: procps
+# ppc64le needs to regenerate auto* files.
+BuildRequires: autoconf automake
+
%{?scl:Requires:%scl_runtime}
-ExclusiveArch: %{ix86} x86_64 ppc ppc64 s390x %{arm} aarch64
+ExclusiveArch: %{ix86} x86_64 ppc ppc64 ppc64le s390x %{arm} aarch64
%ifarch %{ix86}
%define valarch x86
%define valsecarch %{nil}
@@ -107,6 +116,10 @@ ExclusiveArch: %{ix86} x86_64 ppc ppc64 s390x %{arm} aarch64
%define valarch ppc64
%define valsecarch ppc32
%endif
+%ifarch ppc64le
+%define valarch ppc64le
+%define valsecarch %{nil}
+%endif
%ifarch s390x
%define valarch s390x
%define valsecarch %{nil}
@@ -165,9 +178,26 @@ Valgrind User Manual for details.
%patch5 -p1
%endif
-%patch6 -p1
+# ppc64le support.
+%patch1001 -p1
+%patch1002 -p1
+%patch1003 -p1
+%patch1004 -p1
+
+# In the svn setup, these are symlinked, but not in our source archive.
+# So the above ppc64le patches only patched the ppc32 variants. Sync up
+# the ppc64 versions of these tests.
+cp none/tests/ppc32/jm-insns.c none/tests/ppc64/jm-insns.c
+cp none/tests/ppc32/test_dfp4.c none/tests/ppc64/test_dfp4.c
+cp none/tests/ppc32/test_dfp5.c none/tests/ppc64/test_dfp5.c
+cp none/tests/ppc32/test_isa_2_06_part1.c none/tests/ppc64/test_isa_2_06_part1.c
+cp none/tests/ppc32/test_isa_2_06_part2.c none/tests/ppc64/test_isa_2_06_part2.c
+cp none/tests/ppc32/test_isa_2_06_part3.c none/tests/ppc64/test_isa_2_06_part3.c
%build
+# The ppc64le patches touch a lot of auto* files. Lets just regenerate.
+./autogen.sh
+
# We need to use the software collection compiler and binutils if available.
# The configure checks might otherwise miss support for various newer
# assembler instructions.
@@ -327,6 +357,15 @@ echo ===============END TESTING===============
%endif
%changelog
+* Fri Jul 18 2014 Mark Wielaard <mjw at redhat.com> 3.9.0-20.svn20140718r14176
+- Update to upstream svn r14176
+ Remove valgrind-3.9.0-arm64-user_regs.patch
+- Add ppc64le support
+ valgrind-3.9.0-ppc64le-initial.patch
+ valgrind-3.9.0-ppc64le-functional.patch
+ valgrind-3.9.0-ppc64le-test.patch
+ valgrind-3.9.0-ppc64le-extra.patch
+
* Tue Jul 15 2014 Mark Wielaard <mjw at redhat.com> 3.9.0-19.svn20140715r14165
- Add valgrind-3.9.0-arm64-user_regs.patch
- Disable full regtest on aarch64 (gdb integration tests sometimes hang).
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