jforbes pushed to kernel (f21). "Linux v4.0.3 rebase"
notifications at fedoraproject.org
notifications at fedoraproject.org
Thu May 14 16:24:20 UTC 2015
From 09b06469de7217f71af2e46fd943585623d7b33c Mon Sep 17 00:00:00 2001
From: "Justin M. Forbes" <jforbes at redhat.com>
Date: Thu, 14 May 2015 11:24:02 -0500
Subject: Linux v4.0.3 rebase
diff --git a/0001-ALSA-hda-realtek-Support-Dell-headset-mode-for-ALC28.patch b/0001-ALSA-hda-realtek-Support-Dell-headset-mode-for-ALC28.patch
new file mode 100644
index 0000000..470e22e
--- /dev/null
+++ b/0001-ALSA-hda-realtek-Support-Dell-headset-mode-for-ALC28.patch
@@ -0,0 +1,125 @@
+From e1e62b98ebddc3234f3259019d3236f66fc667f8 Mon Sep 17 00:00:00 2001
+From: Kailang Yang <kailang at realtek.com>
+Date: Wed, 8 Apr 2015 16:01:22 +0800
+Subject: [PATCH] ALSA: hda/realtek - Support Dell headset mode for ALC288
+
+Dell create new platform with ALC288 codec.
+This patch will enable headset mode for Dino platform.
+
+[slight code refactoring and compile fix by tiwai]
+
+Signed-off-by: Kailang Yang <kailang at realtek.com>
+Signed-off-by: Takashi Iwai <tiwai at suse.de>
+---
+ sound/pci/hda/patch_realtek.c | 67 +++++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 67 insertions(+)
+
+diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c
+index ceb599a..7b5c93e 100644
+--- a/sound/pci/hda/patch_realtek.c
++++ b/sound/pci/hda/patch_realtek.c
+@@ -4121,6 +4121,29 @@ static void alc_fixup_headset_mode_alc255_no_hp_mic(struct hda_codec *codec,
+ alc_fixup_headset_mode(codec, fix, action);
+ }
+
++static void alc288_update_headset_jack_cb(struct hda_codec *codec,
++ struct hda_jack_callback *jack)
++{
++ struct alc_spec *spec = codec->spec;
++ int present;
++
++ alc_update_headset_jack_cb(codec, jack);
++ /* Headset Mic enable or disable, only for Dell Dino */
++ present = spec->gen.hp_jack_present ? 0x40 : 0;
++ snd_hda_codec_write(codec, 0x01, 0, AC_VERB_SET_GPIO_DATA,
++ present);
++}
++
++static void alc_fixup_headset_mode_dell_alc288(struct hda_codec *codec,
++ const struct hda_fixup *fix, int action)
++{
++ alc_fixup_headset_mode(codec, fix, action);
++ if (action == HDA_FIXUP_ACT_PROBE) {
++ struct alc_spec *spec = codec->spec;
++ spec->gen.hp_automute_hook = alc288_update_headset_jack_cb;
++ }
++}
++
+ static void alc_fixup_auto_mute_via_amp(struct hda_codec *codec,
+ const struct hda_fixup *fix, int action)
+ {
+@@ -4460,6 +4483,9 @@ enum {
+ ALC286_FIXUP_HP_GPIO_LED,
+ ALC280_FIXUP_HP_GPIO2_MIC_HOTKEY,
+ ALC280_FIXUP_HP_DOCK_PINS,
++ ALC288_FIXUP_DELL_HEADSET_MODE,
++ ALC288_FIXUP_DELL1_MIC_NO_PRESENCE,
++ ALC288_FIXUP_DELL_XPS_13_GPIO6,
+ };
+
+ static const struct hda_fixup alc269_fixups[] = {
+@@ -4948,6 +4974,33 @@ static const struct hda_fixup alc269_fixups[] = {
+ .chained = true,
+ .chain_id = ALC280_FIXUP_HP_GPIO4
+ },
++ [ALC288_FIXUP_DELL_HEADSET_MODE] = {
++ .type = HDA_FIXUP_FUNC,
++ .v.func = alc_fixup_headset_mode_dell_alc288,
++ .chained = true,
++ .chain_id = ALC255_FIXUP_DELL_WMI_MIC_MUTE_LED
++ },
++ [ALC288_FIXUP_DELL1_MIC_NO_PRESENCE] = {
++ .type = HDA_FIXUP_PINS,
++ .v.pins = (const struct hda_pintbl[]) {
++ { 0x18, 0x01a1913c }, /* use as headset mic, without its own jack detect */
++ { 0x1a, 0x01a1913d }, /* use as headphone mic, without its own jack detect */
++ { }
++ },
++ .chained = true,
++ .chain_id = ALC288_FIXUP_DELL_HEADSET_MODE
++ },
++ [ALC288_FIXUP_DELL_XPS_13_GPIO6] = {
++ .type = HDA_FIXUP_VERBS,
++ .v.verbs = (const struct hda_verb[]) {
++ {0x01, AC_VERB_SET_GPIO_MASK, 0x40},
++ {0x01, AC_VERB_SET_GPIO_DIRECTION, 0x40},
++ {0x01, AC_VERB_SET_GPIO_DATA, 0x00},
++ { }
++ },
++ .chained = true,
++ .chain_id = ALC288_FIXUP_DELL1_MIC_NO_PRESENCE
++ },
+ };
+
+ static const struct snd_pci_quirk alc269_fixup_tbl[] = {
+@@ -5174,6 +5227,13 @@ static const struct hda_model_fixup alc269_fixup_models[] = {
+ {0x1b, 0x411111f0}, \
+ {0x1e, 0x411111f0}
+
++#define ALC288_STANDARD_PINS \
++ {0x17, 0x411111f0}, \
++ {0x18, 0x411111f0}, \
++ {0x19, 0x411111f0}, \
++ {0x1a, 0x411111f0}, \
++ {0x1e, 0x411111f0}
++
+ #define ALC290_STANDARD_PINS \
+ {0x12, 0x99a30130}, \
+ {0x13, 0x40000000}, \
+@@ -5369,6 +5429,13 @@ static const struct snd_hda_pin_quirk alc269_pin_fixup_tbl[] = {
+ {0x19, 0x03a11020},
+ {0x1d, 0x40e00001},
+ {0x21, 0x0321101f}),
++ SND_HDA_PIN_QUIRK(0x10ec0288, 0x1028, "Dell", ALC288_FIXUP_DELL_XPS_13_GPIO6,
++ ALC288_STANDARD_PINS,
++ {0x12, 0x90a60120},
++ {0x13, 0x40000000},
++ {0x14, 0x90170110},
++ {0x1d, 0x4076832d},
++ {0x21, 0x0321101f}),
+ SND_HDA_PIN_QUIRK(0x10ec0290, 0x103c, "HP", ALC269_FIXUP_HP_MUTE_LED_MIC1,
+ ALC290_STANDARD_PINS,
+ {0x14, 0x411111f0},
+--
+2.1.0
+
diff --git a/0001-ALSA-hda-realtek-Support-headset-mode-for-ALC286-288.patch b/0001-ALSA-hda-realtek-Support-headset-mode-for-ALC286-288.patch
new file mode 100644
index 0000000..1deac4f
--- /dev/null
+++ b/0001-ALSA-hda-realtek-Support-headset-mode-for-ALC286-288.patch
@@ -0,0 +1,181 @@
+From f3b703326541d0c1ce85f5e570f6d2b6bd4296ec Mon Sep 17 00:00:00 2001
+From: Kailang Yang <kailang at realtek.com>
+Date: Wed, 8 Apr 2015 15:01:17 +0800
+Subject: [PATCH] ALSA: hda/realtek - Support headset mode for ALC286/288
+
+Support headset mode for ALC286 and ALC288 platforms.
+
+Signed-off-by: Kailang Yang <kailang at realtek.com>
+Signed-off-by: Takashi Iwai <tiwai at suse.de>
+---
+ sound/pci/hda/patch_realtek.c | 77 +++++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 77 insertions(+)
+
+diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c
+index 7f46d06..ceb599a 100644
+--- a/sound/pci/hda/patch_realtek.c
++++ b/sound/pci/hda/patch_realtek.c
+@@ -3542,6 +3542,14 @@ static void alc_headset_mode_unplugged(struct hda_codec *codec)
+ WRITE_COEF(0x32, 0x42a3),
+ {}
+ };
++ static struct coef_fw coef0288[] = {
++ UPDATE_COEF(0x4f, 0xfcc0, 0xc400),
++ UPDATE_COEF(0x50, 0x2000, 0x2000),
++ UPDATE_COEF(0x56, 0x0006, 0x0006),
++ UPDATE_COEF(0x66, 0x0008, 0),
++ UPDATE_COEF(0x67, 0x2000, 0),
++ {}
++ };
+ static struct coef_fw coef0292[] = {
+ WRITE_COEF(0x76, 0x000e),
+ WRITE_COEF(0x6c, 0x2400),
+@@ -3573,6 +3581,10 @@ static void alc_headset_mode_unplugged(struct hda_codec *codec)
+ case 0x10ec0283:
+ alc_process_coef_fw(codec, coef0233);
+ break;
++ case 0x10ec0286:
++ case 0x10ec0288:
++ alc_process_coef_fw(codec, coef0288);
++ break;
+ case 0x10ec0292:
+ alc_process_coef_fw(codec, coef0292);
+ break;
+@@ -3602,6 +3614,14 @@ static void alc_headset_mode_mic_in(struct hda_codec *codec, hda_nid_t hp_pin,
+ WRITE_COEF(0x26, 0x008c),
+ {}
+ };
++ static struct coef_fw coef0288[] = {
++ UPDATE_COEF(0x50, 0x2000, 0),
++ UPDATE_COEF(0x56, 0x0006, 0),
++ UPDATE_COEF(0x4f, 0xfcc0, 0xc400),
++ UPDATE_COEF(0x66, 0x0008, 0x0008),
++ UPDATE_COEF(0x67, 0x2000, 0x2000),
++ {}
++ };
+ static struct coef_fw coef0292[] = {
+ WRITE_COEF(0x19, 0xa208),
+ WRITE_COEF(0x2e, 0xacf0),
+@@ -3635,6 +3655,13 @@ static void alc_headset_mode_mic_in(struct hda_codec *codec, hda_nid_t hp_pin,
+ alc_process_coef_fw(codec, coef0233);
+ snd_hda_set_pin_ctl_cache(codec, mic_pin, PIN_VREF50);
+ break;
++ case 0x10ec0286:
++ case 0x10ec0288:
++ alc_update_coef_idx(codec, 0x4f, 0x000c, 0);
++ snd_hda_set_pin_ctl_cache(codec, hp_pin, 0);
++ alc_process_coef_fw(codec, coef0288);
++ snd_hda_set_pin_ctl_cache(codec, mic_pin, PIN_VREF50);
++ break;
+ case 0x10ec0292:
+ snd_hda_set_pin_ctl_cache(codec, hp_pin, 0);
+ alc_process_coef_fw(codec, coef0292);
+@@ -3670,6 +3697,14 @@ static void alc_headset_mode_default(struct hda_codec *codec)
+ WRITE_COEF(0x32, 0x4ea3),
+ {}
+ };
++ static struct coef_fw coef0288[] = {
++ UPDATE_COEF(0x4f, 0xfcc0, 0xc400), /* Set to TRS type */
++ UPDATE_COEF(0x50, 0x2000, 0x2000),
++ UPDATE_COEF(0x56, 0x0006, 0x0006),
++ UPDATE_COEF(0x66, 0x0008, 0),
++ UPDATE_COEF(0x67, 0x2000, 0),
++ {}
++ };
+ static struct coef_fw coef0292[] = {
+ WRITE_COEF(0x76, 0x000e),
+ WRITE_COEF(0x6c, 0x2400),
+@@ -3699,6 +3734,11 @@ static void alc_headset_mode_default(struct hda_codec *codec)
+ case 0x10ec0283:
+ alc_process_coef_fw(codec, coef0233);
+ break;
++ case 0x10ec0286:
++ case 0x10ec0288:
++ alc_process_coef_fw(codec, coef0288);
++ break;
++ break;
+ case 0x10ec0292:
+ alc_process_coef_fw(codec, coef0292);
+ break;
+@@ -3727,6 +3767,13 @@ static void alc_headset_mode_ctia(struct hda_codec *codec)
+ WRITE_COEF(0x32, 0x4ea3),
+ {}
+ };
++ static struct coef_fw coef0288[] = {
++ UPDATE_COEF(0x50, 0x2000, 0x2000),
++ UPDATE_COEF(0x56, 0x0006, 0x0006),
++ UPDATE_COEF(0x66, 0x0008, 0),
++ UPDATE_COEF(0x67, 0x2000, 0),
++ {}
++ };
+ static struct coef_fw coef0292[] = {
+ WRITE_COEF(0x6b, 0xd429),
+ WRITE_COEF(0x76, 0x0008),
+@@ -3754,6 +3801,12 @@ static void alc_headset_mode_ctia(struct hda_codec *codec)
+ case 0x10ec0283:
+ alc_process_coef_fw(codec, coef0233);
+ break;
++ case 0x10ec0286:
++ case 0x10ec0288:
++ alc_update_coef_idx(codec, 0x4f, 0xfcc0, 0xd400);
++ msleep(300);
++ alc_process_coef_fw(codec, coef0288);
++ break;
+ case 0x10ec0292:
+ alc_process_coef_fw(codec, coef0292);
+ break;
+@@ -3782,6 +3835,13 @@ static void alc_headset_mode_omtp(struct hda_codec *codec)
+ WRITE_COEF(0x32, 0x4ea3),
+ {}
+ };
++ static struct coef_fw coef0288[] = {
++ UPDATE_COEF(0x50, 0x2000, 0x2000),
++ UPDATE_COEF(0x56, 0x0006, 0x0006),
++ UPDATE_COEF(0x66, 0x0008, 0),
++ UPDATE_COEF(0x67, 0x2000, 0),
++ {}
++ };
+ static struct coef_fw coef0292[] = {
+ WRITE_COEF(0x6b, 0xe429),
+ WRITE_COEF(0x76, 0x0008),
+@@ -3809,6 +3869,12 @@ static void alc_headset_mode_omtp(struct hda_codec *codec)
+ case 0x10ec0283:
+ alc_process_coef_fw(codec, coef0233);
+ break;
++ case 0x10ec0286:
++ case 0x10ec0288:
++ alc_update_coef_idx(codec, 0x4f, 0xfcc0, 0xe400);
++ msleep(300);
++ alc_process_coef_fw(codec, coef0288);
++ break;
+ case 0x10ec0292:
+ alc_process_coef_fw(codec, coef0292);
+ break;
+@@ -3833,6 +3899,10 @@ static void alc_determine_headset_type(struct hda_codec *codec)
+ conteol) */
+ {}
+ };
++ static struct coef_fw coef0288[] = {
++ UPDATE_COEF(0x4f, 0xfcc0, 0xd400), /* Check Type */
++ {}
++ };
+ static struct coef_fw coef0293[] = {
+ UPDATE_COEF(0x4a, 0x000f, 0x0008), /* Combo Jack auto detect */
+ WRITE_COEF(0x45, 0xD429), /* Set to ctia type */
+@@ -3861,6 +3931,13 @@ static void alc_determine_headset_type(struct hda_codec *codec)
+ val = alc_read_coef_idx(codec, 0x46);
+ is_ctia = (val & 0x0070) == 0x0070;
+ break;
++ case 0x10ec0286:
++ case 0x10ec0288:
++ alc_process_coef_fw(codec, coef0288);
++ msleep(350);
++ val = alc_read_coef_idx(codec, 0x50);
++ is_ctia = (val & 0x0070) == 0x0070;
++ break;
+ case 0x10ec0292:
+ alc_write_coef_idx(codec, 0x6b, 0xd429);
+ msleep(300);
+--
+2.1.0
+
diff --git a/0001-HID-usbhid-Add-HID_QUIRK_NOGET-for-Aten-DVI-KVM-swit.patch b/0001-HID-usbhid-Add-HID_QUIRK_NOGET-for-Aten-DVI-KVM-swit.patch
new file mode 100644
index 0000000..d1859af
--- /dev/null
+++ b/0001-HID-usbhid-Add-HID_QUIRK_NOGET-for-Aten-DVI-KVM-swit.patch
@@ -0,0 +1,52 @@
+From 25c1b8af5b11bd1dbd17d0c1212586bb56ec4efd Mon Sep 17 00:00:00 2001
+From: Laura Abbott <labbott at fedoraproject.org>
+Date: Fri, 8 May 2015 14:13:56 -0700
+Subject: [PATCH] HID: usbhid: Add HID_QUIRK_NOGET for Aten DVI KVM switch
+To: Jiri Kosina <jkosina at suse.cz>
+Cc: linux-input at vger.kernel.org
+Cc: linux-kernel at vger.kernel.org
+Cc: linux-usb at vger.kernel.org
+Cc: stephane.tranchemer at devinci.fr
+
+Like other KVM switches, the Aten DVI KVM switch needs a
+quirk to avoid spewing errors:
+
+[791759.606542] usb 1-5.4: input irq status -75 received
+[791759.614537] usb 1-5.4: input irq status -75 received
+[791759.622542] usb 1-5.4: input irq status -75 received
+
+Add it.
+
+Signed-off-by: Laura Abbott <labbott at fedoraproject.org>
+---
+ drivers/hid/hid-ids.h | 1 +
+ drivers/hid/usbhid/hid-quirks.c | 1 +
+ 2 files changed, 2 insertions(+)
+
+diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h
+index 41f167e..7ce93d9 100644
+--- a/drivers/hid/hid-ids.h
++++ b/drivers/hid/hid-ids.h
+@@ -164,6 +164,7 @@
+ #define USB_DEVICE_ID_ATEN_2PORTKVM 0x2204
+ #define USB_DEVICE_ID_ATEN_4PORTKVM 0x2205
+ #define USB_DEVICE_ID_ATEN_4PORTKVMC 0x2208
++#define USB_DEVICE_ID_ATEN_CS682 0x2213
+
+ #define USB_VENDOR_ID_ATMEL 0x03eb
+ #define USB_DEVICE_ID_ATMEL_MULTITOUCH 0x211c
+diff --git a/drivers/hid/usbhid/hid-quirks.c b/drivers/hid/usbhid/hid-quirks.c
+index a775143..4696895e 100644
+--- a/drivers/hid/usbhid/hid-quirks.c
++++ b/drivers/hid/usbhid/hid-quirks.c
+@@ -61,6 +61,7 @@ static const struct hid_blacklist {
+ { USB_VENDOR_ID_ATEN, USB_DEVICE_ID_ATEN_2PORTKVM, HID_QUIRK_NOGET },
+ { USB_VENDOR_ID_ATEN, USB_DEVICE_ID_ATEN_4PORTKVM, HID_QUIRK_NOGET },
+ { USB_VENDOR_ID_ATEN, USB_DEVICE_ID_ATEN_4PORTKVMC, HID_QUIRK_NOGET },
++ { USB_VENDOR_ID_ATEN, USB_DEVICE_ID_ATEN_CS682, HID_QUIRK_NOGET },
+ { USB_VENDOR_ID_CH, USB_DEVICE_ID_CH_FIGHTERSTICK, HID_QUIRK_NOGET },
+ { USB_VENDOR_ID_CH, USB_DEVICE_ID_CH_COMBATSTICK, HID_QUIRK_NOGET },
+ { USB_VENDOR_ID_CH, USB_DEVICE_ID_CH_FLIGHT_SIM_ECLIPSE_YOKE, HID_QUIRK_NOGET },
+--
+2.1.0
+
diff --git a/0001-cx18-add-missing-caps-for-the-PCM-video-device.patch b/0001-cx18-add-missing-caps-for-the-PCM-video-device.patch
deleted file mode 100644
index 23040a7..0000000
--- a/0001-cx18-add-missing-caps-for-the-PCM-video-device.patch
+++ /dev/null
@@ -1,75 +0,0 @@
-From 0ce518efc8ddd9d2d45dcc2f14b20032d1e88946 Mon Sep 17 00:00:00 2001
-From: Hans Verkuil <hverkuil at xs4all.nl>
-Date: Fri, 24 Apr 2015 08:55:07 +0200
-Subject: [PATCH] cx18: add missing caps for the PCM video device
-
-The cx18 PCM video device didn't have any capabilities set, which caused a warnings
-in the v4l2 core:
-
-[ 6.229393] ------------[ cut here ]------------
-[ 6.229414] WARNING: CPU: 1 PID: 593 at
-drivers/media/v4l2-core/v4l2-ioctl.c:1025 v4l_querycap+0x41/0x70
-[videodev]()
-[ 6.229415] Modules linked in: cx18_alsa mxl5005s s5h1409
-tuner_simple tuner_types cs5345 tuner intel_rapl iosf_mbi
-x86_pkg_temp_thermal coretemp raid1 snd_hda_codec_realtek kvm_intel
-snd_hda_codec_generic snd_hda_codec_hdmi kvm snd_oxygen(+) snd_hda_intel
-snd_oxygen_lib snd_hda_controller snd_hda_codec snd_mpu401_uart iTCO_wdt
-snd_rawmidi iTCO_vendor_support snd_hwdep crct10dif_pclmul crc32_pclmul
-crc32c_intel snd_seq cx18 snd_seq_device ghash_clmulni_intel
-videobuf_vmalloc tveeprom cx2341x snd_pcm serio_raw videobuf_core vfat
-dvb_core fat v4l2_common snd_timer videodev snd lpc_ich i2c_i801 joydev
-mfd_core mei_me media soundcore tpm_infineon soc_button_array tpm_tis
-mei shpchp tpm nfsd auth_rpcgss nfs_acl lockd grace sunrpc binfmt_misc
-i915 nouveau mxm_wmi wmi e1000e ttm i2c_algo_bit drm_kms_helper
-[ 6.229444] drm ptp pps_core video
-[ 6.229446] CPU: 1 PID: 593 Comm: v4l_id Not tainted
-3.19.3-200.fc21.x86_64 #1
-[ 6.229447] Hardware name: Gigabyte Technology Co., Ltd.
-Z87-D3HP/Z87-D3HP-CF, BIOS F6 01/20/2014
-[ 6.229448] 0000000000000000 00000000d12b1131 ffff88042dacfc28
-ffffffff8176e215
-[ 6.229449] 0000000000000000 0000000000000000 ffff88042dacfc68
-ffffffff8109bc1a
-[ 6.229451] ffffffffa0594000 ffff88042dacfd90 0000000000000000
-ffffffffa04e2140
-[ 6.229452] Call Trace:
-[ 6.229466] [<ffffffff8176e215>] dump_stack+0x45/0x57
-[ 6.229469] [<ffffffff8109bc1a>] warn_slowpath_common+0x8a/0xc0
-[ 6.229472] [<ffffffff8109bd4a>] warn_slowpath_null+0x1a/0x20
-[ 6.229474] [<ffffffffa04ca401>] v4l_querycap+0x41/0x70 [videodev]
-[ 6.229477] [<ffffffffa04ca6cc>] __video_do_ioctl+0x29c/0x320 [videodev]
-[ 6.229479] [<ffffffff81227131>] ? do_last+0x2f1/0x1210
-[ 6.229491] [<ffffffffa04cc776>] video_usercopy+0x366/0x5d0 [videodev]
-[ 6.229494] [<ffffffffa04ca430>] ? v4l_querycap+0x70/0x70 [videodev]
-[ 6.229497] [<ffffffffa04cc9f5>] video_ioctl2+0x15/0x20 [videodev]
-[ 6.229499] [<ffffffffa04c6794>] v4l2_ioctl+0x164/0x180 [videodev]
-[ 6.229501] [<ffffffff8122e298>] do_vfs_ioctl+0x2f8/0x500
-[ 6.229502] [<ffffffff8122e521>] SyS_ioctl+0x81/0xa0
-[ 6.229505] [<ffffffff81774a09>] system_call_fastpath+0x12/0x17
-[ 6.229506] ---[ end trace dacd80d4b19277ea ]---
-
-Added the necessary capabilities to stop this warning.
-
-Signed-off-by: Hans Verkuil <hans.verkuil at cisco.com>
-Reported-by: Laura Abbott <labbott at redhat.com>
-Cc: <stable at vger.kernel.org> # for v3.19 and up
----
- drivers/media/pci/cx18/cx18-streams.c | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/drivers/media/pci/cx18/cx18-streams.c b/drivers/media/pci/cx18/cx18-streams.c
-index c82d25d..c986084 100644
---- a/drivers/media/pci/cx18/cx18-streams.c
-+++ b/drivers/media/pci/cx18/cx18-streams.c
-@@ -90,6 +90,7 @@ static struct {
- "encoder PCM audio",
- VFL_TYPE_GRABBER, CX18_V4L2_ENC_PCM_OFFSET,
- PCI_DMA_FROMDEVICE,
-+ V4L2_CAP_TUNER | V4L2_CAP_AUDIO | V4L2_CAP_READWRITE,
- },
- { /* CX18_ENC_STREAM_TYPE_IDX */
- "encoder IDX",
---
-2.1.0
-
diff --git a/0001-drivers-rtc-rtc-em3027.c-add-device-tree-support.patch b/0001-drivers-rtc-rtc-em3027.c-add-device-tree-support.patch
new file mode 100644
index 0000000..1c6af9d
--- /dev/null
+++ b/0001-drivers-rtc-rtc-em3027.c-add-device-tree-support.patch
@@ -0,0 +1,51 @@
+From fc7789f5d8061c8d26f2e9be9ce5bd91f5033479 Mon Sep 17 00:00:00 2001
+From: Peter Robinson <pbrobinson at gmail.com>
+Date: Tue, 30 Dec 2014 07:32:03 +0000
+Subject: [PATCH] drivers/rtc/rtc-em3027.c: add device tree support
+
+Set the of_match_table for this driver so that devices can be described
+in the device tree. This device is used in the Trimslice and is already
+defined in the Trimslice device tree.
+
+Signed-off-by: Peter Robinson <pbrobinson at gmail.com>
+---
+ drivers/rtc/rtc-em3027.c | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+diff --git a/drivers/rtc/rtc-em3027.c b/drivers/rtc/rtc-em3027.c
+index fccf366..7fbb051 100644
+--- a/drivers/rtc/rtc-em3027.c
++++ b/drivers/rtc/rtc-em3027.c
+@@ -15,6 +15,7 @@
+ #include <linux/rtc.h>
+ #include <linux/bcd.h>
+ #include <linux/module.h>
++#include <linux/of.h>
+
+ /* Registers */
+ #define EM3027_REG_ON_OFF_CTRL 0x00
+@@ -135,10 +136,21 @@ static struct i2c_device_id em3027_id[] = {
+ { "em3027", 0 },
+ { }
+ };
++MODULE_DEVICE_TABLE(i2c, em3027_id);
++
++#ifdef CONFIG_OF
++static const struct of_device_id em3027_of_match[] = {
++ { .compatible = "emmicro,em3027", },
++ {}
++};
++MODULE_DEVICE_TABLE(of, em3027_of_match);
++#endif
+
+ static struct i2c_driver em3027_driver = {
+ .driver = {
+ .name = "rtc-em3027",
++ .owner = THIS_MODULE,
++ .of_match_table = of_match_ptr(em3027_of_match),
+ },
+ .probe = &em3027_probe,
+ .id_table = em3027_id,
+--
+2.1.0
+
diff --git a/0001-iwlwifi-mvm-remove-WARN_ON-for-invalid-BA-notificati.patch b/0001-iwlwifi-mvm-remove-WARN_ON-for-invalid-BA-notificati.patch
deleted file mode 100644
index 8dc4e89..0000000
--- a/0001-iwlwifi-mvm-remove-WARN_ON-for-invalid-BA-notificati.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From 1f16ea294d2ef63013740f4c8539e430b6c12dff Mon Sep 17 00:00:00 2001
-From: Johannes Berg <johannes.berg at intel.com>
-Date: Fri, 6 Mar 2015 09:17:37 +0100
-Subject: [PATCH] iwlwifi: mvm: remove WARN_ON for invalid BA notification
-
-The firmware frequently manages to trigger this, and there's
-no known driver workaround, so stop warning.
-
-Signed-off-by: Johannes Berg <johannes.berg at intel.com>
-Signed-off-by: Emmanuel Grumbach <emmanuel.grumbach at intel.com>
----
- drivers/net/wireless/iwlwifi/mvm/tx.c | 6 ++++--
- 1 file changed, 4 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/net/wireless/iwlwifi/mvm/tx.c b/drivers/net/wireless/iwlwifi/mvm/tx.c
-index 07304e1..96a0540 100644
---- a/drivers/net/wireless/iwlwifi/mvm/tx.c
-+++ b/drivers/net/wireless/iwlwifi/mvm/tx.c
-@@ -949,8 +949,10 @@ int iwl_mvm_rx_ba_notif(struct iwl_mvm *mvm, struct iwl_rx_cmd_buffer *rxb,
- mvmsta = iwl_mvm_sta_from_mac80211(sta);
- tid_data = &mvmsta->tid_data[tid];
-
-- if (WARN_ONCE(tid_data->txq_id != scd_flow, "Q %d, tid %d, flow %d",
-- tid_data->txq_id, tid, scd_flow)) {
-+ if (tid_data->txq_id != scd_flow) {
-+ IWL_ERR(mvm,
-+ "invalid BA notification: Q %d, tid %d, flow %d\n",
-+ tid_data->txq_id, tid, scd_flow);
- rcu_read_unlock();
- return 0;
- }
---
-2.1.0
-
diff --git a/Add-option-to-automatically-enforce-module-signature.patch b/Add-option-to-automatically-enforce-module-signature.patch
index af77cd7..b3ce38c 100644
--- a/Add-option-to-automatically-enforce-module-signature.patch
+++ b/Add-option-to-automatically-enforce-module-signature.patch
@@ -20,7 +20,7 @@ Signed-off-by: Matthew Garrett <matthew.garrett at nebula.com>
7 files changed, 69 insertions(+), 1 deletion(-)
diff --git a/Documentation/x86/zero-page.txt b/Documentation/x86/zero-page.txt
-index 199f453cb4de..ec38acf00b40 100644
+index 82fbdbc1e0b0..a811210ad486 100644
--- a/Documentation/x86/zero-page.txt
+++ b/Documentation/x86/zero-page.txt
@@ -30,6 +30,8 @@ Offset Proto Name Meaning
@@ -33,10 +33,10 @@ index 199f453cb4de..ec38acf00b40 100644
290/040 ALL edd_mbr_sig_buffer EDD MBR signatures
2D0/A00 ALL e820_map E820 memory map table
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
-index 0dc9d0144a27..58273956750d 100644
+index b7d31ca55187..ab403a636357 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
-@@ -1660,6 +1660,16 @@ config EFI_MIXED
+@@ -1695,6 +1695,16 @@ config EFI_MIXED
If unsure, say N.
@@ -54,7 +54,7 @@ index 0dc9d0144a27..58273956750d 100644
def_bool y
prompt "Enable seccomp to safely compute untrusted bytecode"
diff --git a/arch/x86/boot/compressed/eboot.c b/arch/x86/boot/compressed/eboot.c
-index 92b9a5f2aed6..2192da755e34 100644
+index ef17683484e9..105e7360d747 100644
--- a/arch/x86/boot/compressed/eboot.c
+++ b/arch/x86/boot/compressed/eboot.c
@@ -12,6 +12,7 @@
@@ -63,9 +63,9 @@ index 92b9a5f2aed6..2192da755e34 100644
#include <asm/desc.h>
+#include <asm/bootparam_utils.h>
- #undef memcpy /* Use memcpy from misc.c */
-
-@@ -828,6 +829,37 @@ out:
+ #include "../string.h"
+ #include "eboot.h"
+@@ -827,6 +828,37 @@ out:
return status;
}
@@ -103,7 +103,7 @@ index 92b9a5f2aed6..2192da755e34 100644
/*
* See if we have Graphics Output Protocol
*/
-@@ -1407,6 +1439,10 @@ struct boot_params *efi_main(struct efi_config *c,
+@@ -1406,6 +1438,10 @@ struct boot_params *efi_main(struct efi_config *c,
else
setup_boot_services32(efi_early);
@@ -129,10 +129,10 @@ index 225b0988043a..90dbfb73e11f 100644
* The sentinel is set to a nonzero value (0xff) in header.S.
*
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
-index ab4734e5411d..5d52d67d5097 100644
+index 0a2421cca01f..a3d8174dedf9 100644
--- a/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
-@@ -1152,6 +1152,12 @@ void __init setup_arch(char **cmdline_p)
+@@ -1151,6 +1151,12 @@ void __init setup_arch(char **cmdline_p)
io_delay_init();
@@ -146,7 +146,7 @@ index ab4734e5411d..5d52d67d5097 100644
* Parse the ACPI tables for possible boot-time SMP configuration.
*/
diff --git a/include/linux/module.h b/include/linux/module.h
-index d4b96d6c926a..c47f75720dbd 100644
+index b033dab5c8bf..f526b6e02f59 100644
--- a/include/linux/module.h
+++ b/include/linux/module.h
@@ -188,6 +188,12 @@ const struct exception_table_entry *search_exception_tables(unsigned long add);
@@ -163,10 +163,10 @@ index d4b96d6c926a..c47f75720dbd 100644
extern int modules_disabled; /* for sysctl */
diff --git a/kernel/module.c b/kernel/module.c
-index 98c3d7955a51..6244f24abe27 100644
+index 0372c3961016..55dacebb687b 100644
--- a/kernel/module.c
+++ b/kernel/module.c
-@@ -3896,6 +3896,13 @@ void module_layout(struct module *mod,
+@@ -3909,6 +3909,13 @@ void module_layout(struct module *mod,
EXPORT_SYMBOL(module_layout);
#endif
diff --git a/Add-sysrq-option-to-disable-secure-boot-mode.patch b/Add-sysrq-option-to-disable-secure-boot-mode.patch
index 346b010..7e23c81 100644
--- a/Add-sysrq-option-to-disable-secure-boot-mode.patch
+++ b/Add-sysrq-option-to-disable-secure-boot-mode.patch
@@ -15,7 +15,7 @@ Upstream-status: Fedora mustard
7 files changed, 65 insertions(+), 10 deletions(-)
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
-index b40d6174242f..0ee7749bad74 100644
+index 26c5d54124c1..dab298f03a9c 100644
--- a/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
@@ -70,6 +70,11 @@
@@ -30,7 +30,7 @@ index b40d6174242f..0ee7749bad74 100644
#include <video/edid.h>
#include <asm/mtrr.h>
-@@ -1277,6 +1282,37 @@ void __init i386_reserve_resources(void)
+@@ -1278,6 +1283,37 @@ void __init i386_reserve_resources(void)
#endif /* CONFIG_X86_32 */
@@ -81,10 +81,10 @@ index 421e29e4cd81..61c1eb97806c 100644
input_set_drvdata(udev->dev, udev);
diff --git a/drivers/tty/sysrq.c b/drivers/tty/sysrq.c
-index 42bad18c66c9..496e073b09d7 100644
+index 259a4d5a4e8f..512c21dcb86f 100644
--- a/drivers/tty/sysrq.c
+++ b/drivers/tty/sysrq.c
-@@ -463,6 +463,7 @@ static struct sysrq_key_op *sysrq_key_table[36] = {
+@@ -464,6 +464,7 @@ static struct sysrq_key_op *sysrq_key_table[36] = {
&sysrq_showstate_blocked_op, /* w */
/* x: May be registered on ppc/powerpc for xmon */
/* x: May be registered on sparc64 for global PMU dump */
@@ -92,7 +92,7 @@ index 42bad18c66c9..496e073b09d7 100644
NULL, /* x */
/* y: May be registered on sparc64 for global register dump */
NULL, /* y */
-@@ -506,7 +507,7 @@ static void __sysrq_put_key_op(int key, struct sysrq_key_op *op_p)
+@@ -507,7 +508,7 @@ static void __sysrq_put_key_op(int key, struct sysrq_key_op *op_p)
sysrq_key_table[i] = op_p;
}
@@ -101,7 +101,7 @@ index 42bad18c66c9..496e073b09d7 100644
{
struct sysrq_key_op *op_p;
int orig_log_level;
-@@ -526,11 +527,15 @@ void __handle_sysrq(int key, bool check_mask)
+@@ -527,11 +528,15 @@ void __handle_sysrq(int key, bool check_mask)
op_p = __sysrq_get_key_op(key);
if (op_p) {
@@ -115,10 +115,10 @@ index 42bad18c66c9..496e073b09d7 100644
*/
- if (!check_mask || sysrq_on_mask(op_p->enable_mask)) {
+ if (from == SYSRQ_FROM_KERNEL || sysrq_on_mask(op_p->enable_mask)) {
- printk("%s\n", op_p->action_msg);
+ pr_cont("%s\n", op_p->action_msg);
console_loglevel = orig_log_level;
op_p->handler(key);
-@@ -562,7 +567,7 @@ void __handle_sysrq(int key, bool check_mask)
+@@ -563,7 +568,7 @@ void __handle_sysrq(int key, bool check_mask)
void handle_sysrq(int key)
{
if (sysrq_on())
@@ -127,7 +127,7 @@ index 42bad18c66c9..496e073b09d7 100644
}
EXPORT_SYMBOL(handle_sysrq);
-@@ -642,7 +647,7 @@ static void sysrq_do_reset(unsigned long _state)
+@@ -643,7 +648,7 @@ static void sysrq_do_reset(unsigned long _state)
static void sysrq_handle_reset_request(struct sysrq_state *state)
{
if (state->reset_requested)
@@ -136,7 +136,7 @@ index 42bad18c66c9..496e073b09d7 100644
if (sysrq_reset_downtime_ms)
mod_timer(&state->keyreset_timer,
-@@ -793,8 +798,10 @@ static bool sysrq_handle_keypress(struct sysrq_state *sysrq,
+@@ -794,8 +799,10 @@ static bool sysrq_handle_keypress(struct sysrq_state *sysrq,
default:
if (sysrq->active && value && value != 2) {
@@ -148,7 +148,7 @@ index 42bad18c66c9..496e073b09d7 100644
}
break;
}
-@@ -1089,7 +1096,7 @@ static ssize_t write_sysrq_trigger(struct file *file, const char __user *buf,
+@@ -1090,7 +1097,7 @@ static ssize_t write_sysrq_trigger(struct file *file, const char __user *buf,
if (get_user(c, buf))
return -EFAULT;
@@ -215,7 +215,7 @@ index 387fa7d05c98..4b07e30b3279 100644
int unregister_sysrq_key(int key, struct sysrq_key_op *op);
struct sysrq_key_op *__sysrq_get_key_op(int key);
diff --git a/kernel/debug/kdb/kdb_main.c b/kernel/debug/kdb/kdb_main.c
-index 60f6bb817f70..c0a20ee0ad96 100644
+index 4121345498e0..0ff3cef5df96 100644
--- a/kernel/debug/kdb/kdb_main.c
+++ b/kernel/debug/kdb/kdb_main.c
@@ -1968,7 +1968,7 @@ static int kdb_sr(int argc, const char **argv)
@@ -228,7 +228,7 @@ index 60f6bb817f70..c0a20ee0ad96 100644
return 0;
diff --git a/kernel/module.c b/kernel/module.c
-index 6244f24abe27..b77554170d76 100644
+index 55dacebb687b..9d4deeb9268e 100644
--- a/kernel/module.c
+++ b/kernel/module.c
@@ -107,9 +107,9 @@ struct list_head *kdb_modules = &modules; /* kdb needs the list of modules */
diff --git a/HID-logitech-hidpp-add-a-module-parameter-to-keep-fi.patch b/HID-logitech-hidpp-add-a-module-parameter-to-keep-fi.patch
index c873141..ef6cb0c 100644
--- a/HID-logitech-hidpp-add-a-module-parameter-to-keep-fi.patch
+++ b/HID-logitech-hidpp-add-a-module-parameter-to-keep-fi.patch
@@ -20,7 +20,7 @@ Signed-off-by: Jiri Kosina <jkosina at suse.cz>
1 file changed, 10 insertions(+)
diff --git a/drivers/hid/hid-logitech-hidpp.c b/drivers/hid/hid-logitech-hidpp.c
-index a93cefe0e522..00304f742eca 100644
+index e77658cd037c..8e9cb25f45cb 100644
--- a/drivers/hid/hid-logitech-hidpp.c
+++ b/drivers/hid/hid-logitech-hidpp.c
@@ -28,6 +28,11 @@ MODULE_LICENSE("GPL");
@@ -35,7 +35,7 @@ index a93cefe0e522..00304f742eca 100644
#define REPORT_ID_HIDPP_SHORT 0x10
#define REPORT_ID_HIDPP_LONG 0x11
-@@ -1159,6 +1164,11 @@ static int hidpp_probe(struct hid_device *hdev, const struct hid_device_id *id)
+@@ -1188,6 +1193,11 @@ static int hidpp_probe(struct hid_device *hdev, const struct hid_device_id *id)
hidpp->quirks = id->driver_data;
diff --git a/Input-atmel_mxt_ts-add-support-for-Google-Pixel-2.patch b/Input-atmel_mxt_ts-add-support-for-Google-Pixel-2.patch
new file mode 100644
index 0000000..2f8362e
--- /dev/null
+++ b/Input-atmel_mxt_ts-add-support-for-Google-Pixel-2.patch
@@ -0,0 +1,220 @@
+From: Dmitry Torokhov <dmitry.torokhov at gmail.com>
+Date: Tue, 7 Apr 2015 16:30:01 -0700
+Subject: [PATCH] Input: atmel_mxt_ts - add support for Google Pixel 2
+
+This change allows atmel_mxt_ts to bind to ACPI-enumerated devices in
+Google Pixel 2 (2015).
+
+While newer version of ACPI standard allow use of device-tree-like
+properties in device descriptions, the version of ACPI implemented in
+Google BIOS does not support them, and we have to resort to DMI data to
+specify exact characteristics of the devices (touchpad vs. touchscreen,
+GPIO to button mapping, etc).
+
+Pixel 1 continues to use i2c devices and platform data created by
+chromeos-laptop driver, since ACPI does not enumerate them.
+
+Reviewed-by: Javier Martinez Canillas <javier.martinez at collabora.co.uk>
+Tested-by: Javier Martinez Canillas <javier.martinez at collabora.co.uk>
+Signed-off-by: Dmitry Torokhov <dmitry.torokhov at gmail.com>
+---
+ drivers/input/touchscreen/atmel_mxt_ts.c | 141 ++++++++++++++++++++++++++++---
+ 1 file changed, 130 insertions(+), 11 deletions(-)
+
+diff --git a/drivers/input/touchscreen/atmel_mxt_ts.c b/drivers/input/touchscreen/atmel_mxt_ts.c
+index 2875ddf37289..40b98dda8f38 100644
+--- a/drivers/input/touchscreen/atmel_mxt_ts.c
++++ b/drivers/input/touchscreen/atmel_mxt_ts.c
+@@ -14,6 +14,8 @@
+ *
+ */
+
++#include <linux/acpi.h>
++#include <linux/dmi.h>
+ #include <linux/module.h>
+ #include <linux/init.h>
+ #include <linux/completion.h>
+@@ -2371,7 +2373,7 @@ static void mxt_input_close(struct input_dev *dev)
+ }
+
+ #ifdef CONFIG_OF
+-static struct mxt_platform_data *mxt_parse_dt(struct i2c_client *client)
++static const struct mxt_platform_data *mxt_parse_dt(struct i2c_client *client)
+ {
+ struct mxt_platform_data *pdata;
+ u32 *keymap;
+@@ -2379,7 +2381,7 @@ static struct mxt_platform_data *mxt_parse_dt(struct i2c_client *client)
+ int proplen, i, ret;
+
+ if (!client->dev.of_node)
+- return ERR_PTR(-ENODEV);
++ return ERR_PTR(-ENOENT);
+
+ pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
+ if (!pdata)
+@@ -2410,25 +2412,132 @@ static struct mxt_platform_data *mxt_parse_dt(struct i2c_client *client)
+ return pdata;
+ }
+ #else
+-static struct mxt_platform_data *mxt_parse_dt(struct i2c_client *client)
++static const struct mxt_platform_data *mxt_parse_dt(struct i2c_client *client)
+ {
+- dev_dbg(&client->dev, "No platform data specified\n");
+- return ERR_PTR(-EINVAL);
++ return ERR_PTR(-ENOENT);
++}
++#endif
++
++#ifdef CONFIG_ACPI
++
++struct mxt_acpi_platform_data {
++ const char *hid;
++ struct mxt_platform_data pdata;
++};
++
++static unsigned int samus_touchpad_buttons[] = {
++ KEY_RESERVED,
++ KEY_RESERVED,
++ KEY_RESERVED,
++ BTN_LEFT
++};
++
++static struct mxt_acpi_platform_data samus_platform_data[] = {
++ {
++ /* Touchpad */
++ .hid = "ATML0000",
++ .pdata = {
++ .t19_num_keys = ARRAY_SIZE(samus_touchpad_buttons),
++ .t19_keymap = samus_touchpad_buttons,
++ },
++ },
++ {
++ /* Touchscreen */
++ .hid = "ATML0001",
++ },
++ { }
++};
++
++static const struct dmi_system_id mxt_dmi_table[] = {
++ {
++ /* 2015 Google Pixel */
++ .ident = "Chromebook Pixel 2",
++ .matches = {
++ DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"),
++ DMI_MATCH(DMI_PRODUCT_NAME, "Samus"),
++ },
++ .driver_data = samus_platform_data,
++ },
++ { }
++};
++
++static const struct mxt_platform_data *mxt_parse_acpi(struct i2c_client *client)
++{
++ struct acpi_device *adev;
++ const struct dmi_system_id *system_id;
++ const struct mxt_acpi_platform_data *acpi_pdata;
++
++ /*
++ * Ignore ACPI devices representing bootloader mode.
++ *
++ * This is a bit of a hack: Google Chromebook BIOS creates ACPI
++ * devices for both application and bootloader modes, but we are
++ * interested in application mode only (if device is in bootloader
++ * mode we'll end up switching into application anyway). So far
++ * application mode addresses were all above 0x40, so we'll use it
++ * as a threshold.
++ */
++ if (client->addr < 0x40)
++ return ERR_PTR(-ENXIO);
++
++ adev = ACPI_COMPANION(&client->dev);
++ if (!adev)
++ return ERR_PTR(-ENOENT);
++
++ system_id = dmi_first_match(mxt_dmi_table);
++ if (!system_id)
++ return ERR_PTR(-ENOENT);
++
++ acpi_pdata = system_id->driver_data;
++ if (!acpi_pdata)
++ return ERR_PTR(-ENOENT);
++
++ while (acpi_pdata->hid) {
++ if (!strcmp(acpi_device_hid(adev), acpi_pdata->hid))
++ return &acpi_pdata->pdata;
++
++ acpi_pdata++;
++ }
++
++ return ERR_PTR(-ENOENT);
++}
++#else
++static const struct mxt_platform_data *mxt_parse_acpi(struct i2c_client *client)
++{
++ return ERR_PTR(-ENOENT);
+ }
+ #endif
+
++static const struct mxt_platform_data *
++mxt_get_platform_data(struct i2c_client *client)
++{
++ const struct mxt_platform_data *pdata;
++
++ pdata = dev_get_platdata(&client->dev);
++ if (pdata)
++ return pdata;
++
++ pdata = mxt_parse_dt(client);
++ if (!IS_ERR(pdata) || PTR_ERR(pdata) != -ENOENT)
++ return pdata;
++
++ pdata = mxt_parse_acpi(client);
++ if (!IS_ERR(pdata) || PTR_ERR(pdata) != -ENOENT)
++ return pdata;
++
++ dev_err(&client->dev, "No platform data specified\n");
++ return ERR_PTR(-EINVAL);
++}
++
+ static int mxt_probe(struct i2c_client *client, const struct i2c_device_id *id)
+ {
+ struct mxt_data *data;
+ const struct mxt_platform_data *pdata;
+ int error;
+
+- pdata = dev_get_platdata(&client->dev);
+- if (!pdata) {
+- pdata = mxt_parse_dt(client);
+- if (IS_ERR(pdata))
+- return PTR_ERR(pdata);
+- }
++ pdata = mxt_get_platform_data(client);
++ if (IS_ERR(pdata))
++ return PTR_ERR(pdata);
+
+ data = kzalloc(sizeof(struct mxt_data), GFP_KERNEL);
+ if (!data) {
+@@ -2536,6 +2645,15 @@ static const struct of_device_id mxt_of_match[] = {
+ };
+ MODULE_DEVICE_TABLE(of, mxt_of_match);
+
++#ifdef CONFIG_ACPI
++static const struct acpi_device_id mxt_acpi_id[] = {
++ { "ATML0000", 0 }, /* Touchpad */
++ { "ATML0001", 0 }, /* Touchscreen */
++ { }
++};
++MODULE_DEVICE_TABLE(acpi, mxt_acpi_id);
++#endif
++
+ static const struct i2c_device_id mxt_id[] = {
+ { "qt602240_ts", 0 },
+ { "atmel_mxt_ts", 0 },
+@@ -2550,6 +2668,7 @@ static struct i2c_driver mxt_driver = {
+ .name = "atmel_mxt_ts",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(mxt_of_match),
++ .acpi_match_table = ACPI_PTR(mxt_acpi_id),
+ .pm = &mxt_pm_ops,
+ },
+ .probe = mxt_probe,
diff --git a/Input-atmel_mxt_ts-implement-support-for-T100-touch-.patch b/Input-atmel_mxt_ts-implement-support-for-T100-touch-.patch
new file mode 100644
index 0000000..603e441
--- /dev/null
+++ b/Input-atmel_mxt_ts-implement-support-for-T100-touch-.patch
@@ -0,0 +1,512 @@
+From: Nick Dyer <nick.dyer at itdev.co.uk>
+Date: Mon, 6 Apr 2015 11:25:13 -0700
+Subject: [PATCH] Input: atmel_mxt_ts - implement support for T100 touch object
+
+Add support for the new T100 object which replaces the previous T9
+multitouch touchscreen object in recent maXTouch devices. T100 provides
+improved reporting with selectable auxiliary information, and a type field
+for hover/stylus/glove reporting.
+
+The hovering finger support was based on Chung-Yih's work in the ChromiumOS
+downstream kernel:
+
+https://chromium-review.googlesource.com/#/c/219280/
+
+Signed-off-by: Nick Dyer <nick.dyer at itdev.co.uk>
+Acked-by: Yufeng Shen <miletus at chromium.org>
+[javier: Factor out T9 and T100 init functions and rework hover support]
+Signed-off-by: Javier Martinez Canillas <javier.martinez at collabora.co.uk>
+Signed-off-by: Dmitry Torokhov <dmitry.torokhov at gmail.com>
+---
+ drivers/input/touchscreen/atmel_mxt_ts.c | 345 ++++++++++++++++++++++++++++---
+ 1 file changed, 318 insertions(+), 27 deletions(-)
+
+diff --git a/drivers/input/touchscreen/atmel_mxt_ts.c b/drivers/input/touchscreen/atmel_mxt_ts.c
+index 95ee92a91bd2..1b3b845d92f4 100644
+--- a/drivers/input/touchscreen/atmel_mxt_ts.c
++++ b/drivers/input/touchscreen/atmel_mxt_ts.c
+@@ -25,6 +25,7 @@
+ #include <linux/interrupt.h>
+ #include <linux/of.h>
+ #include <linux/slab.h>
++#include <asm/unaligned.h>
+
+ /* Version */
+ #define MXT_VER_20 20
+@@ -79,6 +80,7 @@
+ #define MXT_SPT_DIGITIZER_T43 43
+ #define MXT_SPT_MESSAGECOUNT_T44 44
+ #define MXT_SPT_CTECONFIG_T46 46
++#define MXT_TOUCH_MULTITOUCHSCREEN_T100 100
+
+ /* MXT_GEN_MESSAGE_T5 object */
+ #define MXT_RPTID_NOMSG 0xff
+@@ -185,6 +187,36 @@ struct t9_range {
+ #define MXT_RESET_VALUE 0x01
+ #define MXT_BACKUP_VALUE 0x55
+
++/* T100 Multiple Touch Touchscreen */
++#define MXT_T100_CTRL 0
++#define MXT_T100_CFG1 1
++#define MXT_T100_TCHAUX 3
++#define MXT_T100_XRANGE 13
++#define MXT_T100_YRANGE 24
++
++#define MXT_T100_CFG_SWITCHXY BIT(5)
++
++#define MXT_T100_TCHAUX_VECT BIT(0)
++#define MXT_T100_TCHAUX_AMPL BIT(1)
++#define MXT_T100_TCHAUX_AREA BIT(2)
++
++#define MXT_T100_DETECT BIT(7)
++#define MXT_T100_TYPE_MASK 0x70
++
++enum t100_type {
++ MXT_T100_TYPE_FINGER = 1,
++ MXT_T100_TYPE_PASSIVE_STYLUS = 2,
++ MXT_T100_TYPE_HOVERING_FINGER = 4,
++ MXT_T100_TYPE_GLOVE = 5,
++ MXT_T100_TYPE_LARGE_TOUCH = 6,
++};
++
++#define MXT_DISTANCE_ACTIVE_TOUCH 0
++#define MXT_DISTANCE_HOVERING 1
++
++#define MXT_TOUCH_MAJOR_DEFAULT 1
++#define MXT_PRESSURE_DEFAULT 1
++
+ /* Delay times */
+ #define MXT_BACKUP_TIME 50 /* msec */
+ #define MXT_RESET_TIME 200 /* msec */
+@@ -244,6 +276,9 @@ struct mxt_data {
+ unsigned int max_y;
+ bool in_bootloader;
+ u16 mem_size;
++ u8 t100_aux_ampl;
++ u8 t100_aux_area;
++ u8 t100_aux_vect;
+ u8 max_reportid;
+ u32 config_crc;
+ u32 info_crc;
+@@ -253,6 +288,7 @@ struct mxt_data {
+ bool update_input;
+ u8 last_message_count;
+ u8 num_touchids;
++ u8 multitouch;
+
+ /* Cached parameters from object table */
+ u16 T5_address;
+@@ -264,6 +300,8 @@ struct mxt_data {
+ u8 T9_reportid_max;
+ u8 T19_reportid;
+ u16 T44_address;
++ u8 T100_reportid_min;
++ u8 T100_reportid_max;
+
+ /* for fw update in bootloader */
+ struct completion bl_completion;
+@@ -771,6 +809,114 @@ static void mxt_proc_t9_message(struct mxt_data *data, u8 *message)
+ data->update_input = true;
+ }
+
++static void mxt_proc_t100_message(struct mxt_data *data, u8 *message)
++{
++ struct device *dev = &data->client->dev;
++ struct input_dev *input_dev = data->input_dev;
++ int id;
++ u8 status;
++ u8 type = 0;
++ u16 x;
++ u16 y;
++ int distance = 0;
++ int tool = 0;
++ u8 major = 0;
++ u8 pressure = 0;
++ u8 orientation = 0;
++
++ id = message[0] - data->T100_reportid_min - 2;
++
++ /* ignore SCRSTATUS events */
++ if (id < 0)
++ return;
++
++ status = message[1];
++ x = get_unaligned_le16(&message[2]);
++ y = get_unaligned_le16(&message[4]);
++
++ if (status & MXT_T100_DETECT) {
++ type = (status & MXT_T100_TYPE_MASK) >> 4;
++
++ switch (type) {
++ case MXT_T100_TYPE_HOVERING_FINGER:
++ tool = MT_TOOL_FINGER;
++ distance = MXT_DISTANCE_HOVERING;
++
++ if (data->t100_aux_vect)
++ orientation = message[data->t100_aux_vect];
++
++ break;
++
++ case MXT_T100_TYPE_FINGER:
++ case MXT_T100_TYPE_GLOVE:
++ tool = MT_TOOL_FINGER;
++ distance = MXT_DISTANCE_ACTIVE_TOUCH;
++
++ if (data->t100_aux_area)
++ major = message[data->t100_aux_area];
++
++ if (data->t100_aux_ampl)
++ pressure = message[data->t100_aux_ampl];
++
++ if (data->t100_aux_vect)
++ orientation = message[data->t100_aux_vect];
++
++ break;
++
++ case MXT_T100_TYPE_PASSIVE_STYLUS:
++ tool = MT_TOOL_PEN;
++
++ /*
++ * Passive stylus is reported with size zero so
++ * hardcode.
++ */
++ major = MXT_TOUCH_MAJOR_DEFAULT;
++
++ if (data->t100_aux_ampl)
++ pressure = message[data->t100_aux_ampl];
++
++ break;
++
++ case MXT_T100_TYPE_LARGE_TOUCH:
++ /* Ignore suppressed touch */
++ break;
++
++ default:
++ dev_dbg(dev, "Unexpected T100 type\n");
++ return;
++ }
++ }
++
++ /*
++ * Values reported should be non-zero if tool is touching the
++ * device
++ */
++ if (!pressure && type != MXT_T100_TYPE_HOVERING_FINGER)
++ pressure = MXT_PRESSURE_DEFAULT;
++
++ input_mt_slot(input_dev, id);
++
++ if (status & MXT_T100_DETECT) {
++ dev_dbg(dev, "[%u] type:%u x:%u y:%u a:%02X p:%02X v:%02X\n",
++ id, type, x, y, major, pressure, orientation);
++
++ input_mt_report_slot_state(input_dev, tool, 1);
++ input_report_abs(input_dev, ABS_MT_POSITION_X, x);
++ input_report_abs(input_dev, ABS_MT_POSITION_Y, y);
++ input_report_abs(input_dev, ABS_MT_TOUCH_MAJOR, major);
++ input_report_abs(input_dev, ABS_MT_PRESSURE, pressure);
++ input_report_abs(input_dev, ABS_MT_DISTANCE, distance);
++ input_report_abs(input_dev, ABS_MT_ORIENTATION, orientation);
++ } else {
++ dev_dbg(dev, "[%u] release\n", id);
++
++ /* close out slot */
++ input_mt_report_slot_state(input_dev, 0, 0);
++ }
++
++ data->update_input = true;
++}
++
+ static int mxt_proc_message(struct mxt_data *data, u8 *message)
+ {
+ u8 report_id = message[0];
+@@ -786,9 +932,12 @@ static int mxt_proc_message(struct mxt_data *data, u8 *message)
+ * is not yet registered.
+ */
+ mxt_dump_message(data, message);
+- } else if (report_id >= data->T9_reportid_min
+- && report_id <= data->T9_reportid_max) {
++ } else if (report_id >= data->T9_reportid_min &&
++ report_id <= data->T9_reportid_max) {
+ mxt_proc_t9_message(data, message);
++ } else if (report_id >= data->T100_reportid_min &&
++ report_id <= data->T100_reportid_max) {
++ mxt_proc_t100_message(data, message);
+ } else if (report_id == data->T19_reportid) {
+ mxt_input_button(data, message);
+ data->update_input = true;
+@@ -1411,6 +1560,8 @@ static void mxt_free_object_table(struct mxt_data *data)
+ data->T9_reportid_max = 0;
+ data->T19_reportid = 0;
+ data->T44_address = 0;
++ data->T100_reportid_min = 0;
++ data->T100_reportid_max = 0;
+ data->max_reportid = 0;
+ }
+
+@@ -1487,6 +1638,7 @@ static int mxt_get_object_table(struct mxt_data *data)
+ data->T7_address = object->start_address;
+ break;
+ case MXT_TOUCH_MULTI_T9:
++ data->multitouch = MXT_TOUCH_MULTI_T9;
+ data->T9_reportid_min = min_id;
+ data->T9_reportid_max = max_id;
+ data->num_touchids = object->num_report_ids
+@@ -1498,6 +1650,13 @@ static int mxt_get_object_table(struct mxt_data *data)
+ case MXT_SPT_GPIOPWM_T19:
+ data->T19_reportid = min_id;
+ break;
++ case MXT_TOUCH_MULTITOUCHSCREEN_T100:
++ data->multitouch = MXT_TOUCH_MULTITOUCHSCREEN_T100;
++ data->T100_reportid_min = min_id;
++ data->T100_reportid_max = max_id;
++ /* first two report IDs reserved */
++ data->num_touchids = object->num_report_ids - 2;
++ break;
+ }
+
+ end_address = object->start_address
+@@ -1582,10 +1741,88 @@ static int mxt_read_t9_resolution(struct mxt_data *data)
+ return 0;
+ }
+
++static int mxt_read_t100_config(struct mxt_data *data)
++{
++ struct i2c_client *client = data->client;
++ int error;
++ struct mxt_object *object;
++ u16 range_x, range_y;
++ u8 cfg, tchaux;
++ u8 aux;
++
++ object = mxt_get_object(data, MXT_TOUCH_MULTITOUCHSCREEN_T100);
++ if (!object)
++ return -EINVAL;
++
++ error = __mxt_read_reg(client,
++ object->start_address + MXT_T100_XRANGE,
++ sizeof(range_x), &range_x);
++ if (error)
++ return error;
++
++ le16_to_cpus(&range_x);
++
++ error = __mxt_read_reg(client,
++ object->start_address + MXT_T100_YRANGE,
++ sizeof(range_y), &range_y);
++ if (error)
++ return error;
++
++ le16_to_cpus(&range_y);
++
++ error = __mxt_read_reg(client,
++ object->start_address + MXT_T100_CFG1,
++ 1, &cfg);
++ if (error)
++ return error;
++
++ error = __mxt_read_reg(client,
++ object->start_address + MXT_T100_TCHAUX,
++ 1, &tchaux);
++ if (error)
++ return error;
++
++ /* Handle default values */
++ if (range_x == 0)
++ range_x = 1023;
++
++ if (range_y == 0)
++ range_y = 1023;
++
++ if (cfg & MXT_T100_CFG_SWITCHXY) {
++ data->max_x = range_y;
++ data->max_y = range_x;
++ } else {
++ data->max_x = range_x;
++ data->max_y = range_y;
++ }
++
++ /* allocate aux bytes */
++ aux = 6;
++
++ if (tchaux & MXT_T100_TCHAUX_VECT)
++ data->t100_aux_vect = aux++;
++
++ if (tchaux & MXT_T100_TCHAUX_AMPL)
++ data->t100_aux_ampl = aux++;
++
++ if (tchaux & MXT_T100_TCHAUX_AREA)
++ data->t100_aux_area = aux++;
++
++ dev_dbg(&client->dev,
++ "T100 aux mappings vect:%u ampl:%u area:%u\n",
++ data->t100_aux_vect, data->t100_aux_ampl, data->t100_aux_area);
++
++ dev_info(&client->dev,
++ "T100 Touchscreen size X%uY%u\n", data->max_x, data->max_y);
++
++ return 0;
++}
++
+ static int mxt_input_open(struct input_dev *dev);
+ static void mxt_input_close(struct input_dev *dev);
+
+-static int mxt_initialize_t9_input_device(struct mxt_data *data)
++static int mxt_initialize_input_device(struct mxt_data *data)
+ {
+ struct device *dev = &data->client->dev;
+ const struct mxt_platform_data *pdata = data->pdata;
+@@ -1595,9 +1832,25 @@ static int mxt_initialize_t9_input_device(struct mxt_data *data)
+ unsigned int mt_flags = 0;
+ int i;
+
+- error = mxt_read_t9_resolution(data);
+- if (error)
+- dev_warn(dev, "Failed to initialize T9 resolution\n");
++ switch (data->multitouch) {
++ case MXT_TOUCH_MULTI_T9:
++ num_mt_slots = data->T9_reportid_max - data->T9_reportid_min + 1;
++ error = mxt_read_t9_resolution(data);
++ if (error)
++ dev_warn(dev, "Failed to initialize T9 resolution\n");
++ break;
++
++ case MXT_TOUCH_MULTITOUCHSCREEN_T100:
++ num_mt_slots = data->num_touchids;
++ error = mxt_read_t100_config(data);
++ if (error)
++ dev_warn(dev, "Failed to read T100 config\n");
++ break;
++
++ default:
++ dev_err(dev, "Invalid multitouch object\n");
++ return -EINVAL;
++ }
+
+ input_dev = input_allocate_device();
+ if (!input_dev) {
+@@ -1612,9 +1865,7 @@ static int mxt_initialize_t9_input_device(struct mxt_data *data)
+ input_dev->open = mxt_input_open;
+ input_dev->close = mxt_input_close;
+
+- __set_bit(EV_ABS, input_dev->evbit);
+- __set_bit(EV_KEY, input_dev->evbit);
+- __set_bit(BTN_TOUCH, input_dev->keybit);
++ input_set_capability(input_dev, EV_KEY, BTN_TOUCH);
+
+ if (pdata->t19_num_keys) {
+ __set_bit(INPUT_PROP_BUTTONPAD, input_dev->propbit);
+@@ -1637,29 +1888,67 @@ static int mxt_initialize_t9_input_device(struct mxt_data *data)
+ }
+
+ /* For single touch */
+- input_set_abs_params(input_dev, ABS_X,
+- 0, data->max_x, 0, 0);
+- input_set_abs_params(input_dev, ABS_Y,
+- 0, data->max_y, 0, 0);
+- input_set_abs_params(input_dev, ABS_PRESSURE,
+- 0, 255, 0, 0);
++ input_set_abs_params(input_dev, ABS_X, 0, data->max_x, 0, 0);
++ input_set_abs_params(input_dev, ABS_Y, 0, data->max_y, 0, 0);
++
++ if (data->multitouch == MXT_TOUCH_MULTI_T9 ||
++ (data->multitouch == MXT_TOUCH_MULTITOUCHSCREEN_T100 &&
++ data->t100_aux_ampl)) {
++ input_set_abs_params(input_dev, ABS_PRESSURE, 0, 255, 0, 0);
++ }
+
+ /* For multi touch */
+- num_mt_slots = data->T9_reportid_max - data->T9_reportid_min + 1;
+ error = input_mt_init_slots(input_dev, num_mt_slots, mt_flags);
+ if (error) {
+ dev_err(dev, "Error %d initialising slots\n", error);
+ goto err_free_mem;
+ }
+
+- input_set_abs_params(input_dev, ABS_MT_TOUCH_MAJOR,
+- 0, MXT_MAX_AREA, 0, 0);
++ if (data->multitouch == MXT_TOUCH_MULTITOUCHSCREEN_T100) {
++ input_set_abs_params(input_dev, ABS_MT_TOOL_TYPE,
++ 0, MT_TOOL_MAX, 0, 0);
++ input_set_abs_params(input_dev, ABS_MT_DISTANCE,
++ MXT_DISTANCE_ACTIVE_TOUCH,
++ MXT_DISTANCE_HOVERING,
++ 0, 0);
++ }
++
+ input_set_abs_params(input_dev, ABS_MT_POSITION_X,
+ 0, data->max_x, 0, 0);
+ input_set_abs_params(input_dev, ABS_MT_POSITION_Y,
+ 0, data->max_y, 0, 0);
+- input_set_abs_params(input_dev, ABS_MT_PRESSURE,
+- 0, 255, 0, 0);
++
++ if (data->multitouch == MXT_TOUCH_MULTI_T9 ||
++ (data->multitouch == MXT_TOUCH_MULTITOUCHSCREEN_T100 &&
++ data->t100_aux_area)) {
++ input_set_abs_params(input_dev, ABS_MT_TOUCH_MAJOR,
++ 0, MXT_MAX_AREA, 0, 0);
++ }
++
++ if (data->multitouch == MXT_TOUCH_MULTI_T9 ||
++ (data->multitouch == MXT_TOUCH_MULTITOUCHSCREEN_T100 &&
++ data->t100_aux_ampl)) {
++ input_set_abs_params(input_dev, ABS_MT_PRESSURE,
++ 0, 255, 0, 0);
++ }
++
++ if (data->multitouch == MXT_TOUCH_MULTITOUCHSCREEN_T100 &&
++ data->t100_aux_vect) {
++ input_set_abs_params(input_dev, ABS_MT_ORIENTATION,
++ 0, 255, 0, 0);
++ }
++
++ if (data->multitouch == MXT_TOUCH_MULTITOUCHSCREEN_T100 &&
++ data->t100_aux_ampl) {
++ input_set_abs_params(input_dev, ABS_MT_PRESSURE,
++ 0, 255, 0, 0);
++ }
++
++ if (data->multitouch == MXT_TOUCH_MULTITOUCHSCREEN_T100 &&
++ data->t100_aux_vect) {
++ input_set_abs_params(input_dev, ABS_MT_ORIENTATION,
++ 0, 255, 0, 0);
++ }
+
+ input_set_drvdata(input_dev, data);
+
+@@ -1765,9 +2054,13 @@ static int mxt_configure_objects(struct mxt_data *data,
+ dev_warn(dev, "Error %d updating config\n", error);
+ }
+
+- error = mxt_initialize_t9_input_device(data);
+- if (error)
+- return error;
++ if (data->multitouch) {
++ error = mxt_initialize_input_device(data);
++ if (error)
++ return error;
++ } else {
++ dev_warn(dev, "No touch object detected\n");
++ }
+
+ dev_info(dev,
+ "Family: %u Variant: %u Firmware V%u.%u.%02X Objects: %u\n",
+@@ -2044,15 +2337,13 @@ static const struct attribute_group mxt_attr_group = {
+ static void mxt_start(struct mxt_data *data)
+ {
+ /* Touch enable */
+- mxt_write_object(data,
+- MXT_TOUCH_MULTI_T9, MXT_TOUCH_CTRL, 0x83);
++ mxt_write_object(data, data->multitouch, MXT_TOUCH_CTRL, 0x83);
+ }
+
+ static void mxt_stop(struct mxt_data *data)
+ {
+ /* Touch disable */
+- mxt_write_object(data,
+- MXT_TOUCH_MULTI_T9, MXT_TOUCH_CTRL, 0);
++ mxt_write_object(data, data->multitouch, MXT_TOUCH_CTRL, 0);
+ }
+
+ static int mxt_input_open(struct input_dev *dev)
diff --git a/Input-atmel_mxt_ts-split-out-touchpad-initialisation.patch b/Input-atmel_mxt_ts-split-out-touchpad-initialisation.patch
new file mode 100644
index 0000000..5b5cb6a
--- /dev/null
+++ b/Input-atmel_mxt_ts-split-out-touchpad-initialisation.patch
@@ -0,0 +1,100 @@
+From: Sjoerd Simons <sjoerd.simons at collabora.co.uk>
+Date: Mon, 6 Apr 2015 13:10:30 -0700
+Subject: [PATCH] Input: atmel_mxt_ts - split out touchpad initialisation logic
+
+If the "linux,gpio-keymap" DT property is defined, the T19 keys are
+configured and the device is setup as a touchpad rather than a touchscreen.
+The logic is part of the input device initialization routine but it can be
+factored out to its own function to simplify the former.
+
+Signed-off-by: Sjoerd Simons <sjoerd.simons at collabora.co.uk>
+Signed-off-by: Javier Martinez Canillas <javier.martinez at collabora.co.uk>
+Signed-off-by: Dmitry Torokhov <dmitry.torokhov at gmail.com>
+---
+ drivers/input/touchscreen/atmel_mxt_ts.c | 52 ++++++++++++++++++--------------
+ 1 file changed, 30 insertions(+), 22 deletions(-)
+
+diff --git a/drivers/input/touchscreen/atmel_mxt_ts.c b/drivers/input/touchscreen/atmel_mxt_ts.c
+index 1b3b845d92f4..2875ddf37289 100644
+--- a/drivers/input/touchscreen/atmel_mxt_ts.c
++++ b/drivers/input/touchscreen/atmel_mxt_ts.c
+@@ -1822,15 +1822,37 @@ static int mxt_read_t100_config(struct mxt_data *data)
+ static int mxt_input_open(struct input_dev *dev);
+ static void mxt_input_close(struct input_dev *dev);
+
++static void mxt_set_up_as_touchpad(struct input_dev *input_dev,
++ struct mxt_data *data)
++{
++ const struct mxt_platform_data *pdata = data->pdata;
++ int i;
++
++ input_dev->name = "Atmel maXTouch Touchpad";
++
++ __set_bit(INPUT_PROP_BUTTONPAD, input_dev->propbit);
++
++ input_abs_set_res(input_dev, ABS_X, MXT_PIXELS_PER_MM);
++ input_abs_set_res(input_dev, ABS_Y, MXT_PIXELS_PER_MM);
++ input_abs_set_res(input_dev, ABS_MT_POSITION_X,
++ MXT_PIXELS_PER_MM);
++ input_abs_set_res(input_dev, ABS_MT_POSITION_Y,
++ MXT_PIXELS_PER_MM);
++
++ for (i = 0; i < pdata->t19_num_keys; i++)
++ if (pdata->t19_keymap[i] != KEY_RESERVED)
++ input_set_capability(input_dev, EV_KEY,
++ pdata->t19_keymap[i]);
++}
++
+ static int mxt_initialize_input_device(struct mxt_data *data)
+ {
+- struct device *dev = &data->client->dev;
+ const struct mxt_platform_data *pdata = data->pdata;
++ struct device *dev = &data->client->dev;
+ struct input_dev *input_dev;
+ int error;
+ unsigned int num_mt_slots;
+ unsigned int mt_flags = 0;
+- int i;
+
+ switch (data->multitouch) {
+ case MXT_TOUCH_MULTI_T9:
+@@ -1867,26 +1889,6 @@ static int mxt_initialize_input_device(struct mxt_data *data)
+
+ input_set_capability(input_dev, EV_KEY, BTN_TOUCH);
+
+- if (pdata->t19_num_keys) {
+- __set_bit(INPUT_PROP_BUTTONPAD, input_dev->propbit);
+-
+- for (i = 0; i < pdata->t19_num_keys; i++)
+- if (pdata->t19_keymap[i] != KEY_RESERVED)
+- input_set_capability(input_dev, EV_KEY,
+- pdata->t19_keymap[i]);
+-
+- mt_flags |= INPUT_MT_POINTER;
+-
+- input_abs_set_res(input_dev, ABS_X, MXT_PIXELS_PER_MM);
+- input_abs_set_res(input_dev, ABS_Y, MXT_PIXELS_PER_MM);
+- input_abs_set_res(input_dev, ABS_MT_POSITION_X,
+- MXT_PIXELS_PER_MM);
+- input_abs_set_res(input_dev, ABS_MT_POSITION_Y,
+- MXT_PIXELS_PER_MM);
+-
+- input_dev->name = "Atmel maXTouch Touchpad";
+- }
+-
+ /* For single touch */
+ input_set_abs_params(input_dev, ABS_X, 0, data->max_x, 0, 0);
+ input_set_abs_params(input_dev, ABS_Y, 0, data->max_y, 0, 0);
+@@ -1897,6 +1899,12 @@ static int mxt_initialize_input_device(struct mxt_data *data)
+ input_set_abs_params(input_dev, ABS_PRESSURE, 0, 255, 0, 0);
+ }
+
++ /* If device has buttons we assume it is a touchpad */
++ if (pdata->t19_num_keys) {
++ mxt_set_up_as_touchpad(input_dev, data);
++ mt_flags |= INPUT_MT_POINTER;
++ }
++
+ /* For multi touch */
+ error = input_mt_init_slots(input_dev, num_mt_slots, mt_flags);
+ if (error) {
diff --git a/Input-synaptics-re-route-tracksticks-buttons-on-the-.patch b/Input-synaptics-re-route-tracksticks-buttons-on-the-.patch
deleted file mode 100644
index bda1af0..0000000
--- a/Input-synaptics-re-route-tracksticks-buttons-on-the-.patch
+++ /dev/null
@@ -1,148 +0,0 @@
-From: Benjamin Tissoires <benjamin.tissoires at redhat.com>
-Date: Sun, 8 Mar 2015 22:35:41 -0700
-Subject: [PATCH] Input: synaptics - re-route tracksticks buttons on the Lenovo
- 2015 series
-
-The 2015 series of the Lenovo thinkpads added back the hardware buttons on
-top of the touchpad for the trackstick.
-
-Unfortunately, they are wired to the touchpad, and not the trackstick.
-Thus, they are seen as extra buttons from the kernel point of view.
-
-This leads to a problem in user space because extra buttons on synaptics
-devices used to be used as scroll up/down buttons. So in the end, the
-experience for the user is scroll events for buttons left and right when
-using the trackstick. Yay!
-
-Fortunately, the firmware advertises such behavior in the extended
-capability $10, and so we can re-route the buttons through the pass-through
-interface.
-
-Hallelujah-expressed-by: Peter Hutterer <peter.hutterer at who-t.net>
-Signed-off-by: Benjamin Tissoires <benjamin.tissoires at redhat.com>
-Acked-by: Hans de Goede <hdegoede at redhat.com>
-Signed-off-by: Dmitry Torokhov <dmitry.torokhov at gmail.com>
----
- drivers/input/mouse/synaptics.c | 47 +++++++++++++++++++++++++++++++----------
- drivers/input/mouse/synaptics.h | 5 +++++
- 2 files changed, 41 insertions(+), 11 deletions(-)
-
-diff --git a/drivers/input/mouse/synaptics.c b/drivers/input/mouse/synaptics.c
-index 9d599eb79f17..ecc7811cbd46 100644
---- a/drivers/input/mouse/synaptics.c
-+++ b/drivers/input/mouse/synaptics.c
-@@ -579,18 +579,22 @@ static int synaptics_is_pt_packet(unsigned char *buf)
- return (buf[0] & 0xFC) == 0x84 && (buf[3] & 0xCC) == 0xC4;
- }
-
--static void synaptics_pass_pt_packet(struct serio *ptport, unsigned char *packet)
-+static void synaptics_pass_pt_packet(struct psmouse *psmouse,
-+ struct serio *ptport,
-+ unsigned char *packet)
- {
-+ struct synaptics_data *priv = psmouse->private;
- struct psmouse *child = serio_get_drvdata(ptport);
-
- if (child && child->state == PSMOUSE_ACTIVATED) {
-- serio_interrupt(ptport, packet[1], 0);
-+ serio_interrupt(ptport, packet[1] | priv->pt_buttons, 0);
- serio_interrupt(ptport, packet[4], 0);
- serio_interrupt(ptport, packet[5], 0);
- if (child->pktsize == 4)
- serio_interrupt(ptport, packet[2], 0);
-- } else
-+ } else {
- serio_interrupt(ptport, packet[1], 0);
-+ }
- }
-
- static void synaptics_pt_activate(struct psmouse *psmouse)
-@@ -847,6 +851,7 @@ static void synaptics_report_ext_buttons(struct psmouse *psmouse,
- struct input_dev *dev = psmouse->dev;
- struct synaptics_data *priv = psmouse->private;
- int ext_bits = (SYN_CAP_MULTI_BUTTON_NO(priv->ext_cap) + 1) >> 1;
-+ char buf[6] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
- int i;
-
- if (!SYN_CAP_MULTI_BUTTON_NO(priv->ext_cap))
-@@ -857,12 +862,30 @@ static void synaptics_report_ext_buttons(struct psmouse *psmouse,
- !((psmouse->packet[0] ^ psmouse->packet[3]) & 0x02))
- return;
-
-- for (i = 0; i < ext_bits; i++) {
-- input_report_key(dev, BTN_0 + 2 * i,
-- hw->ext_buttons & (1 << i));
-- input_report_key(dev, BTN_1 + 2 * i,
-- hw->ext_buttons & (1 << (i + ext_bits)));
-+ if (!SYN_CAP_EXT_BUTTONS_STICK(priv->ext_cap_10)) {
-+ for (i = 0; i < ext_bits; i++) {
-+ input_report_key(dev, BTN_0 + 2 * i,
-+ hw->ext_buttons & (1 << i));
-+ input_report_key(dev, BTN_1 + 2 * i,
-+ hw->ext_buttons & (1 << (i + ext_bits)));
-+ }
-+ return;
- }
-+
-+ /*
-+ * This generation of touchpads has the trackstick buttons
-+ * physically wired to the touchpad. Re-route them through
-+ * the pass-through interface.
-+ */
-+ if (!priv->pt_port)
-+ return;
-+
-+ /* The trackstick expects at most 3 buttons */
-+ priv->pt_buttons = SYN_CAP_EXT_BUTTON_STICK_L(hw->ext_buttons) |
-+ SYN_CAP_EXT_BUTTON_STICK_R(hw->ext_buttons) << 1 |
-+ SYN_CAP_EXT_BUTTON_STICK_M(hw->ext_buttons) << 2;
-+
-+ synaptics_pass_pt_packet(psmouse, priv->pt_port, buf);
- }
-
- static void synaptics_report_buttons(struct psmouse *psmouse,
-@@ -1459,7 +1482,8 @@ static psmouse_ret_t synaptics_process_byte(struct psmouse *psmouse)
- if (SYN_CAP_PASS_THROUGH(priv->capabilities) &&
- synaptics_is_pt_packet(psmouse->packet)) {
- if (priv->pt_port)
-- synaptics_pass_pt_packet(priv->pt_port, psmouse->packet);
-+ synaptics_pass_pt_packet(psmouse, priv->pt_port,
-+ psmouse->packet);
- } else
- synaptics_process_packet(psmouse);
-
-@@ -1561,8 +1585,9 @@ static void set_input_params(struct psmouse *psmouse,
- __set_bit(BTN_BACK, dev->keybit);
- }
-
-- for (i = 0; i < SYN_CAP_MULTI_BUTTON_NO(priv->ext_cap); i++)
-- __set_bit(BTN_0 + i, dev->keybit);
-+ if (!SYN_CAP_EXT_BUTTONS_STICK(priv->ext_cap_10))
-+ for (i = 0; i < SYN_CAP_MULTI_BUTTON_NO(priv->ext_cap); i++)
-+ __set_bit(BTN_0 + i, dev->keybit);
-
- __clear_bit(EV_REL, dev->evbit);
- __clear_bit(REL_X, dev->relbit);
-diff --git a/drivers/input/mouse/synaptics.h b/drivers/input/mouse/synaptics.h
-index 8d3761ce8f54..f39539c70219 100644
---- a/drivers/input/mouse/synaptics.h
-+++ b/drivers/input/mouse/synaptics.h
-@@ -111,6 +111,10 @@
- #define SYN_CAP_EXT_BUTTONS_STICK(ex10) ((ex10) & 0x010000)
- #define SYN_CAP_SECUREPAD(ex10) ((ex10) & 0x020000)
-
-+#define SYN_CAP_EXT_BUTTON_STICK_L(eb) (!!((eb) & 0x01))
-+#define SYN_CAP_EXT_BUTTON_STICK_M(eb) (!!((eb) & 0x02))
-+#define SYN_CAP_EXT_BUTTON_STICK_R(eb) (!!((eb) & 0x04))
-+
- /* synaptics modes query bits */
- #define SYN_MODE_ABSOLUTE(m) ((m) & (1 << 7))
- #define SYN_MODE_RATE(m) ((m) & (1 << 6))
-@@ -192,6 +196,7 @@ struct synaptics_data {
- bool disable_gesture; /* disable gestures */
-
- struct serio *pt_port; /* Pass-through serio port */
-+ unsigned char pt_buttons; /* Pass-through buttons */
-
- struct synaptics_mt_state mt_state; /* Current mt finger state */
- bool mt_state_lost; /* mt_state may be incorrect */
diff --git a/Input-synaptics-remove-TOPBUTTONPAD-property-for-Len.patch b/Input-synaptics-remove-TOPBUTTONPAD-property-for-Len.patch
deleted file mode 100644
index 24e112d..0000000
--- a/Input-synaptics-remove-TOPBUTTONPAD-property-for-Len.patch
+++ /dev/null
@@ -1,41 +0,0 @@
-From: Benjamin Tissoires <benjamin.tissoires at redhat.com>
-Date: Sun, 8 Mar 2015 22:34:50 -0700
-Subject: [PATCH] Input: synaptics - remove TOPBUTTONPAD property for Lenovos
- 2015
-
-The 2015 series of the Lenovo thinkpads added back the hardware buttons on
-top of the touchpad for the trackstick.
-
-Unfortunately, Lenovo used the PNPIDs that are supposed to be "5 buttons"
-touchpads, so the new laptops also have the INPUT_PROP_TOPBUTTONPAD. Yay!
-
-Instead of manually removing each of the new ones, or hoping that we know
-all the current ones, we can consider that the PNPIDs list that were given
-contains touchpads that have the trackstick buttons, either physically
-wired to them, or emulated with the top software button property.
-
-Thanks to the extra buttons capability in query $10, we can reliably detect
-the physical buttons from the software ones, and so we can remove the
-TOPBUTTONPAD property even if it was declared as such.
-
-Signed-off-by: Benjamin Tissoires <benjamin.tissoires at redhat.com>
-Acked-by: Hans de Goede <hdegoede at redhat.com>
-Signed-off-by: Dmitry Torokhov <dmitry.torokhov at gmail.com>
----
- drivers/input/mouse/synaptics.c | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
-diff --git a/drivers/input/mouse/synaptics.c b/drivers/input/mouse/synaptics.c
-index 8f6a153677b9..9d599eb79f17 100644
---- a/drivers/input/mouse/synaptics.c
-+++ b/drivers/input/mouse/synaptics.c
-@@ -1570,7 +1570,8 @@ static void set_input_params(struct psmouse *psmouse,
-
- if (SYN_CAP_CLICKPAD(priv->ext_cap_0c)) {
- __set_bit(INPUT_PROP_BUTTONPAD, dev->propbit);
-- if (psmouse_matches_pnp_id(psmouse, topbuttonpad_pnp_ids))
-+ if (psmouse_matches_pnp_id(psmouse, topbuttonpad_pnp_ids) &&
-+ !SYN_CAP_EXT_BUTTONS_STICK(priv->ext_cap_10))
- __set_bit(INPUT_PROP_TOPBUTTONPAD, dev->propbit);
- /* Clickpads report only left button */
- __clear_bit(BTN_RIGHT, dev->keybit);
diff --git a/Input-synaptics-remove-X1-Carbon-3rd-gen-from-the-to.patch b/Input-synaptics-remove-X1-Carbon-3rd-gen-from-the-to.patch
deleted file mode 100644
index 951557d..0000000
--- a/Input-synaptics-remove-X1-Carbon-3rd-gen-from-the-to.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From: Benjamin Tissoires <benjamin.tissoires at redhat.com>
-Date: Sun, 8 Mar 2015 22:38:55 -0700
-Subject: [PATCH] Input: synaptics - remove X1 Carbon 3rd gen from the
- topbuttonpad list
-
-Lenovo decided to switch back to physical buttons for the trackstick on
-their latest series. The PNPId list was provided before they reverted back
-to physical buttons, so it contains the new models too. We can know from
-the touchpad capabilities that the touchpad has physical buttons, so
-removing the ids from the list is not mandatory. It is still nicer to
-remove the wrong ids, so start by removing the X1 Carbon 3rd gen, with the
-PNPId of LEN0048.
-
-Signed-off-by: Benjamin Tissoires <benjamin.tissoires at redhat.com>
-Acked-by: Hans de Goede <hdegoede at redhat.com>
-Signed-off-by: Dmitry Torokhov <dmitry.torokhov at gmail.com>
----
- drivers/input/mouse/synaptics.c | 1 -
- 1 file changed, 1 deletion(-)
-
-diff --git a/drivers/input/mouse/synaptics.c b/drivers/input/mouse/synaptics.c
-index ecc7811cbd46..160def02cde2 100644
---- a/drivers/input/mouse/synaptics.c
-+++ b/drivers/input/mouse/synaptics.c
-@@ -183,7 +183,6 @@ static const char * const topbuttonpad_pnp_ids[] = {
- "LEN0045",
- "LEN0046",
- "LEN0047",
-- "LEN0048",
- "LEN0049",
- "LEN2000",
- "LEN2001", /* Edge E431 */
diff --git a/Input-synaptics-remove-X250-from-the-topbuttonpad-li.patch b/Input-synaptics-remove-X250-from-the-topbuttonpad-li.patch
deleted file mode 100644
index 2f1c970..0000000
--- a/Input-synaptics-remove-X250-from-the-topbuttonpad-li.patch
+++ /dev/null
@@ -1,29 +0,0 @@
-From: Benjamin Tissoires <benjamin.tissoires at redhat.com>
-Date: Sun, 8 Mar 2015 22:39:17 -0700
-Subject: [PATCH] Input: synaptics - remove X250 from the topbuttonpad list
-
-Lenovo X250 has a PnpID of LEN0046, but it does not have the top software
-button requirement.
-
-For the record, Lenovo T450s and W541 have a PnpID of LEN200f and LEN004a,
-so they are not on the top software button list.
-
-Signed-off-by: Benjamin Tissoires <benjamin.tissoires at redhat.com>
-Reviewed-by: Daniel Martin <consume.noise at gmail.com>
-Signed-off-by: Dmitry Torokhov <dmitry.torokhov at gmail.com>
----
- drivers/input/mouse/synaptics.c | 1 -
- 1 file changed, 1 deletion(-)
-
-diff --git a/drivers/input/mouse/synaptics.c b/drivers/input/mouse/synaptics.c
-index 160def02cde2..ca7ca8d4eb33 100644
---- a/drivers/input/mouse/synaptics.c
-+++ b/drivers/input/mouse/synaptics.c
-@@ -181,7 +181,6 @@ static const char * const topbuttonpad_pnp_ids[] = {
- "LEN0041",
- "LEN0042", /* Yoga */
- "LEN0045",
-- "LEN0046",
- "LEN0047",
- "LEN0049",
- "LEN2000",
diff --git a/Input-synaptics-retrieve-the-extended-capabilities-i.patch b/Input-synaptics-retrieve-the-extended-capabilities-i.patch
deleted file mode 100644
index 1ef718f..0000000
--- a/Input-synaptics-retrieve-the-extended-capabilities-i.patch
+++ /dev/null
@@ -1,122 +0,0 @@
-From: Benjamin Tissoires <benjamin.tissoires at redhat.com>
-Date: Sun, 8 Mar 2015 22:34:03 -0700
-Subject: [PATCH] Input: synaptics - retrieve the extended capabilities in
- query $10
-
-Newer Synaptics touchpads need to get information from the query $10.
-Retrieve it if available.
-
-Signed-off-by: Benjamin Tissoires <benjamin.tissoires at redhat.com>
-Acked-by: Hans de Goede <hdegoede at redhat.com>
-Signed-off-by: Dmitry Torokhov <dmitry.torokhov at gmail.com>
----
- drivers/input/mouse/synaptics.c | 23 ++++++++++++++++++++---
- drivers/input/mouse/synaptics.h | 23 +++++++++++++++++++++++
- 2 files changed, 43 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/input/mouse/synaptics.c b/drivers/input/mouse/synaptics.c
-index 2176874a41b1..8f6a153677b9 100644
---- a/drivers/input/mouse/synaptics.c
-+++ b/drivers/input/mouse/synaptics.c
-@@ -241,11 +241,24 @@ static int synaptics_model_id(struct psmouse *psmouse)
- return 0;
- }
-
-+static int synaptics_more_extended_queries(struct psmouse *psmouse)
-+{
-+ struct synaptics_data *priv = psmouse->private;
-+ unsigned char buf[3];
-+
-+ if (synaptics_send_cmd(psmouse, SYN_QUE_MEXT_CAPAB_10, buf))
-+ return -1;
-+
-+ priv->ext_cap_10 = (buf[0]<<16) | (buf[1]<<8) | buf[2];
-+
-+ return 0;
-+}
-+
- /*
-- * Read the board id from the touchpad
-+ * Read the board id and the "More Extended Queries" from the touchpad
- * The board id is encoded in the "QUERY MODES" response
- */
--static int synaptics_board_id(struct psmouse *psmouse)
-+static int synaptics_query_modes(struct psmouse *psmouse)
- {
- struct synaptics_data *priv = psmouse->private;
- unsigned char bid[3];
-@@ -257,6 +270,10 @@ static int synaptics_board_id(struct psmouse *psmouse)
- if (synaptics_send_cmd(psmouse, SYN_QUE_MODES, bid))
- return -1;
- priv->board_id = ((bid[0] & 0xfc) << 6) | bid[1];
-+
-+ if (SYN_MEXT_CAP_BIT(bid[0]))
-+ return synaptics_more_extended_queries(psmouse);
-+
- return 0;
- }
-
-@@ -446,7 +463,7 @@ static int synaptics_query_hardware(struct psmouse *psmouse)
- return -1;
- if (synaptics_firmware_id(psmouse))
- return -1;
-- if (synaptics_board_id(psmouse))
-+ if (synaptics_query_modes(psmouse))
- return -1;
- if (synaptics_capability(psmouse))
- return -1;
-diff --git a/drivers/input/mouse/synaptics.h b/drivers/input/mouse/synaptics.h
-index 1bd01f21783b..8d3761ce8f54 100644
---- a/drivers/input/mouse/synaptics.h
-+++ b/drivers/input/mouse/synaptics.h
-@@ -22,6 +22,7 @@
- #define SYN_QUE_EXT_CAPAB_0C 0x0c
- #define SYN_QUE_EXT_MAX_COORDS 0x0d
- #define SYN_QUE_EXT_MIN_COORDS 0x0f
-+#define SYN_QUE_MEXT_CAPAB_10 0x10
-
- /* synatics modes */
- #define SYN_BIT_ABSOLUTE_MODE (1 << 7)
-@@ -53,6 +54,7 @@
- #define SYN_EXT_CAP_REQUESTS(c) (((c) & 0x700000) >> 20)
- #define SYN_CAP_MULTI_BUTTON_NO(ec) (((ec) & 0x00f000) >> 12)
- #define SYN_CAP_PRODUCT_ID(ec) (((ec) & 0xff0000) >> 16)
-+#define SYN_MEXT_CAP_BIT(m) ((m) & (1 << 1))
-
- /*
- * The following describes response for the 0x0c query.
-@@ -89,6 +91,26 @@
- #define SYN_CAP_REDUCED_FILTERING(ex0c) ((ex0c) & 0x000400)
- #define SYN_CAP_IMAGE_SENSOR(ex0c) ((ex0c) & 0x000800)
-
-+/*
-+ * The following descibes response for the 0x10 query.
-+ *
-+ * byte mask name meaning
-+ * ---- ---- ------- ------------
-+ * 1 0x01 ext buttons are stick buttons exported in the extended
-+ * capability are actually meant to be used
-+ * by the tracktick (pass-through).
-+ * 1 0x02 SecurePad the touchpad is a SecurePad, so it
-+ * contains a built-in fingerprint reader.
-+ * 1 0xe0 more ext count how many more extented queries are
-+ * available after this one.
-+ * 2 0xff SecurePad width the width of the SecurePad fingerprint
-+ * reader.
-+ * 3 0xff SecurePad height the height of the SecurePad fingerprint
-+ * reader.
-+ */
-+#define SYN_CAP_EXT_BUTTONS_STICK(ex10) ((ex10) & 0x010000)
-+#define SYN_CAP_SECUREPAD(ex10) ((ex10) & 0x020000)
-+
- /* synaptics modes query bits */
- #define SYN_MODE_ABSOLUTE(m) ((m) & (1 << 7))
- #define SYN_MODE_RATE(m) ((m) & (1 << 6))
-@@ -156,6 +178,7 @@ struct synaptics_data {
- unsigned long int capabilities; /* Capabilities */
- unsigned long int ext_cap; /* Extended Capabilities */
- unsigned long int ext_cap_0c; /* Ext Caps from 0x0c query */
-+ unsigned long int ext_cap_10; /* Ext Caps from 0x10 query */
- unsigned long int identity; /* Identification */
- unsigned int x_res, y_res; /* X/Y resolution in units/mm */
- unsigned int x_max, y_max; /* Max coordinates (from FW) */
diff --git a/Kbuild-Add-an-option-to-enable-GCC-VTA.patch b/Kbuild-Add-an-option-to-enable-GCC-VTA.patch
index 33b9569..bc95069 100644
--- a/Kbuild-Add-an-option-to-enable-GCC-VTA.patch
+++ b/Kbuild-Add-an-option-to-enable-GCC-VTA.patch
@@ -43,7 +43,7 @@ Signed-off-by: Josh Stone <jistone at redhat.com>
2 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/Makefile b/Makefile
-index 69952c1404b2..c0aa7af8ee68 100644
+index dc9f43a019d6..89b47324c032 100644
--- a/Makefile
+++ b/Makefile
@@ -706,7 +706,11 @@ KBUILD_CFLAGS += -fomit-frame-pointer
@@ -59,7 +59,7 @@ index 69952c1404b2..c0aa7af8ee68 100644
ifdef CONFIG_DEBUG_INFO
ifdef CONFIG_DEBUG_INFO_SPLIT
diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug
-index 5f2ce616c046..6525e2a5619a 100644
+index c5cefb3c009c..b663e8e211b0 100644
--- a/lib/Kconfig.debug
+++ b/lib/Kconfig.debug
@@ -165,7 +165,23 @@ config DEBUG_INFO_DWARF4
@@ -85,5 +85,5 @@ index 5f2ce616c046..6525e2a5619a 100644
+ environment to automatically compile everything both ways,
+ generating an error if anything differs.
- config ENABLE_WARN_DEPRECATED
- bool "Enable __deprecated logic"
+ config GDB_SCRIPTS
+ bool "Provide GDB scripts for kernel debugging"
diff --git a/SCSI-add-1024-max-sectors-black-list-flag.patch b/SCSI-add-1024-max-sectors-black-list-flag.patch
deleted file mode 100644
index 86cd0d0..0000000
--- a/SCSI-add-1024-max-sectors-black-list-flag.patch
+++ /dev/null
@@ -1,92 +0,0 @@
-From: Mike Christie <michaelc at cs.wisc.edu>
-Date: Tue, 21 Apr 2015 03:42:24 -0400
-Subject: [PATCH] SCSI: add 1024 max sectors black list flag
-
-This works around a issue with qnap iscsi targets not handling large IOs
-very well.
-
-The target returns:
-
-VPD INQUIRY: Block limits page (SBC)
- Maximum compare and write length: 1 blocks
- Optimal transfer length granularity: 1 blocks
- Maximum transfer length: 4294967295 blocks
- Optimal transfer length: 4294967295 blocks
- Maximum prefetch, xdread, xdwrite transfer length: 0 blocks
- Maximum unmap LBA count: 8388607
- Maximum unmap block descriptor count: 1
- Optimal unmap granularity: 16383
- Unmap granularity alignment valid: 0
- Unmap granularity alignment: 0
- Maximum write same length: 0xffffffff blocks
- Maximum atomic transfer length: 0
- Atomic alignment: 0
- Atomic transfer length granularity: 0
-
-and it is *sometimes* able to handle at least one IO of size up to 8 MB. We
-have seen in traces where it will sometimes work, but other times it
-looks like it fails and it looks like it returns failures if we send
-multiple large IOs sometimes. Also it looks like it can return 2 different
-errors. It will sometimes send iscsi reject errors indicating out of
-resources or it will send invalid cdb illegal requests check conditions.
-And then when it sends iscsi rejects it does not seem to handle retries
-when there are command sequence holes, so I could not just add code to
-try and gracefully handle that error code.
-
-The problem is that we do not have a good contact for the company,
-so we are not able to determine under what conditions it returns
-which error and why it sometimes works.
-
-So, this patch just adds a new black list flag to set targets like this to
-the old max safe sectors of 1024. The max_hw_sectors changes added in 3.19
-caused this regression, so I also ccing stable.
-
-Reported-by: Christian Hesse <list at eworm.de>
-Signed-off-by: Mike Christie <michaelc at cs.wisc.edu>
-Cc: stable at vger.kernel.org
----
- drivers/scsi/scsi_devinfo.c | 1 +
- drivers/scsi/scsi_scan.c | 6 ++++++
- include/scsi/scsi_devinfo.h | 1 +
- 3 files changed, 8 insertions(+)
-
-diff --git a/drivers/scsi/scsi_devinfo.c b/drivers/scsi/scsi_devinfo.c
-index 262ab837a704..9f77d23239a2 100644
---- a/drivers/scsi/scsi_devinfo.c
-+++ b/drivers/scsi/scsi_devinfo.c
-@@ -226,6 +226,7 @@ static struct {
- {"PIONEER", "CD-ROM DRM-624X", NULL, BLIST_FORCELUN | BLIST_SINGLELUN},
- {"Promise", "VTrak E610f", NULL, BLIST_SPARSELUN | BLIST_NO_RSOC},
- {"Promise", "", NULL, BLIST_SPARSELUN},
-+ {"QNAP", "iSCSI Storage", NULL, BLIST_MAX_1024},
- {"QUANTUM", "XP34301", "1071", BLIST_NOTQ},
- {"REGAL", "CDC-4X", NULL, BLIST_MAX5LUN | BLIST_SINGLELUN},
- {"SanDisk", "ImageMate CF-SD1", NULL, BLIST_FORCELUN},
-diff --git a/drivers/scsi/scsi_scan.c b/drivers/scsi/scsi_scan.c
-index 983aed10ff2f..cc662c98d2b6 100644
---- a/drivers/scsi/scsi_scan.c
-+++ b/drivers/scsi/scsi_scan.c
-@@ -909,6 +909,12 @@ static int scsi_add_lun(struct scsi_device *sdev, unsigned char *inq_result,
- */
- if (*bflags & BLIST_MAX_512)
- blk_queue_max_hw_sectors(sdev->request_queue, 512);
-+ /*
-+ * Max 1024 sector transfer length for targets that report incorrect
-+ * max/optimal lengths and relied on the old block layer safe default
-+ */
-+ else if (*bflags & BLIST_MAX_1024)
-+ blk_queue_max_hw_sectors(sdev->request_queue, 1024);
-
- /*
- * Some devices may not want to have a start command automatically
-diff --git a/include/scsi/scsi_devinfo.h b/include/scsi/scsi_devinfo.h
-index 183eaab7c380..96e3f56519e7 100644
---- a/include/scsi/scsi_devinfo.h
-+++ b/include/scsi/scsi_devinfo.h
-@@ -36,5 +36,6 @@
- for sequential scan */
- #define BLIST_TRY_VPD_PAGES 0x10000000 /* Attempt to read VPD pages */
- #define BLIST_NO_RSOC 0x20000000 /* don't try to issue RSOC */
-+#define BLIST_MAX_1024 0x40000000 /* maximum 1024 sector cdb length */
-
- #endif
diff --git a/acpi-video-add-disable_native_backlight_quirk_for_samsung_510r.patch b/acpi-video-add-disable_native_backlight_quirk_for_samsung_510r.patch
deleted file mode 100644
index 9a123dd..0000000
--- a/acpi-video-add-disable_native_backlight_quirk_for_samsung_510r.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From b29c0d36da67a64f5de1fe167c0b807815aa1da4 Mon Sep 17 00:00:00 2001
-From: Hans de Goede <hdegoede at redhat.com>
-Date: Wed, 4 Feb 2015 14:44:51 +0100
-Subject: [PATCH 2/2] acpi-video: Add disable_native_backlight quirk for
- Samsung 510R
-
-Backlight control through the native intel interface does not work properly
-on the Samsung 510R, where as using the acpi_video interface does work, add
-a quirk for this.
-
-BugLink: https://bugzilla.redhat.com/show_bug.cgi?id=1186097
-Signed-off-by: Hans de Goede <hdegoede at redhat.com>
----
- drivers/acpi/video.c | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
-diff --git a/drivers/acpi/video.c b/drivers/acpi/video.c
-index 497d986..88a4f99 100644
---- a/drivers/acpi/video.c
-+++ b/drivers/acpi/video.c
-@@ -523,6 +523,15 @@ static struct dmi_system_id video_dmi_table[] __initdata = {
- },
- },
- {
-+ /* https://bugzilla.redhat.com/show_bug.cgi?id=1186097 */
-+ .callback = video_disable_native_backlight,
-+ .ident = "SAMSUNG 3570R/370R/470R/450R/510R/4450RV",
-+ .matches = {
-+ DMI_MATCH(DMI_SYS_VENDOR, "SAMSUNG ELECTRONICS CO., LTD."),
-+ DMI_MATCH(DMI_PRODUCT_NAME, "3570R/370R/470R/450R/510R/4450RV"),
-+ },
-+ },
-+ {
- /* https://bugzilla.redhat.com/show_bug.cgi?id=1094948 */
- .callback = video_disable_native_backlight,
- .ident = "SAMSUNG 730U3E/740U3E",
---
-2.1.0
-
diff --git a/amd-xgbe-phy-a0-Add-support-for-XGBE-PHY-on-A0.patch b/amd-xgbe-phy-a0-Add-support-for-XGBE-PHY-on-A0.patch
new file mode 100644
index 0000000..2dc32fa
--- /dev/null
+++ b/amd-xgbe-phy-a0-Add-support-for-XGBE-PHY-on-A0.patch
@@ -0,0 +1,1843 @@
+From: Tom Lendacky <thomas.lendacky at amd.com>
+Date: Tue, 17 Mar 2015 10:58:38 -0500
+Subject: [PATCH] amd-xgbe-phy-a0: Add support for XGBE PHY on A0
+
+Add XGBE phy driver support for A0 hardware.
+
+Signed-off-by: Tom Lendacky <thomas.lendacky at amd.com>
+---
+ drivers/net/phy/Makefile | 1 +
+ drivers/net/phy/amd-xgbe-phy-a0.c | 1814 +++++++++++++++++++++++++++++++++++++
+ 2 files changed, 1815 insertions(+)
+ create mode 100644 drivers/net/phy/amd-xgbe-phy-a0.c
+
+diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
+index 501ea7699a2d..92e76446033e 100644
+--- a/drivers/net/phy/Makefile
++++ b/drivers/net/phy/Makefile
+@@ -34,4 +34,5 @@ obj-$(CONFIG_MDIO_BUS_MUX_MMIOREG) += mdio-mux-mmioreg.o
+ obj-$(CONFIG_MDIO_SUN4I) += mdio-sun4i.o
+ obj-$(CONFIG_MDIO_MOXART) += mdio-moxart.o
+ obj-$(CONFIG_AMD_XGBE_PHY) += amd-xgbe-phy.o
++obj-$(CONFIG_AMD_XGBE_PHY) += amd-xgbe-phy-a0.o
+ obj-$(CONFIG_MDIO_BCM_UNIMAC) += mdio-bcm-unimac.o
+diff --git a/drivers/net/phy/amd-xgbe-phy-a0.c b/drivers/net/phy/amd-xgbe-phy-a0.c
+new file mode 100644
+index 000000000000..c352d5c2989b
+--- /dev/null
++++ b/drivers/net/phy/amd-xgbe-phy-a0.c
+@@ -0,0 +1,1814 @@
++/*
++ * AMD 10Gb Ethernet PHY driver
++ *
++ * This file is available to you under your choice of the following two
++ * licenses:
++ *
++ * License 1: GPLv2
++ *
++ * Copyright (c) 2014 Advanced Micro Devices, Inc.
++ *
++ * This file is free software; you may copy, redistribute and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 2 of the License, or (at
++ * your option) any later version.
++ *
++ * This file is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ *
++ *
++ * License 2: Modified BSD
++ *
++ * Copyright (c) 2014 Advanced Micro Devices, Inc.
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * * Neither the name of Advanced Micro Devices, Inc. nor the
++ * names of its contributors may be used to endorse or promote products
++ * derived from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include <linux/kernel.h>
++#include <linux/device.h>
++#include <linux/platform_device.h>
++#include <linux/string.h>
++#include <linux/errno.h>
++#include <linux/unistd.h>
++#include <linux/slab.h>
++#include <linux/interrupt.h>
++#include <linux/init.h>
++#include <linux/delay.h>
++#include <linux/workqueue.h>
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/skbuff.h>
++#include <linux/mm.h>
++#include <linux/module.h>
++#include <linux/mii.h>
++#include <linux/ethtool.h>
++#include <linux/phy.h>
++#include <linux/mdio.h>
++#include <linux/io.h>
++#include <linux/of.h>
++#include <linux/of_platform.h>
++#include <linux/of_device.h>
++#include <linux/uaccess.h>
++#include <linux/bitops.h>
++#include <linux/property.h>
++#include <linux/acpi.h>
++#include <linux/irq.h>
++
++MODULE_AUTHOR("Tom Lendacky <thomas.lendacky at amd.com>");
++MODULE_LICENSE("Dual BSD/GPL");
++MODULE_VERSION("0.0.0-a");
++MODULE_DESCRIPTION("AMD 10GbE (amd-xgbe) PHY driver");
++
++#define XGBE_PHY_ID 0x7996ced0
++#define XGBE_PHY_MASK 0xfffffff0
++
++#define XGBE_PHY_SERDES_RETRY 32
++#define XGBE_PHY_CHANNEL_PROPERTY "amd,serdes-channel"
++#define XGBE_PHY_SPEEDSET_PROPERTY "amd,speed-set"
++#define XGBE_PHY_BLWC_PROPERTY "amd,serdes-blwc"
++#define XGBE_PHY_CDR_RATE_PROPERTY "amd,serdes-cdr-rate"
++#define XGBE_PHY_PQ_SKEW_PROPERTY "amd,serdes-pq-skew"
++#define XGBE_PHY_TX_AMP_PROPERTY "amd,serdes-tx-amp"
++
++#define XGBE_PHY_SPEEDS 3
++#define XGBE_PHY_SPEED_1000 0
++#define XGBE_PHY_SPEED_2500 1
++#define XGBE_PHY_SPEED_10000 2
++
++#define XGBE_AN_INT_CMPLT 0x01
++#define XGBE_AN_INC_LINK 0x02
++#define XGBE_AN_PG_RCV 0x04
++#define XGBE_AN_INT_MASK 0x07
++
++#define XNP_MCF_NULL_MESSAGE 0x001
++#define XNP_ACK_PROCESSED BIT(12)
++#define XNP_MP_FORMATTED BIT(13)
++#define XNP_NP_EXCHANGE BIT(15)
++
++#define XGBE_PHY_RATECHANGE_COUNT 500
++
++#define XGBE_PHY_KR_TRAINING_START 0x01
++#define XGBE_PHY_KR_TRAINING_ENABLE 0x02
++
++#define XGBE_PHY_FEC_ENABLE 0x01
++#define XGBE_PHY_FEC_FORWARD 0x02
++#define XGBE_PHY_FEC_MASK 0x03
++
++#ifndef MDIO_PMA_10GBR_PMD_CTRL
++#define MDIO_PMA_10GBR_PMD_CTRL 0x0096
++#endif
++
++#ifndef MDIO_PMA_10GBR_FEC_ABILITY
++#define MDIO_PMA_10GBR_FEC_ABILITY 0x00aa
++#endif
++
++#ifndef MDIO_PMA_10GBR_FEC_CTRL
++#define MDIO_PMA_10GBR_FEC_CTRL 0x00ab
++#endif
++
++#ifndef MDIO_AN_XNP
++#define MDIO_AN_XNP 0x0016
++#endif
++
++#ifndef MDIO_AN_LPX
++#define MDIO_AN_LPX 0x0019
++#endif
++
++#ifndef MDIO_AN_INTMASK
++#define MDIO_AN_INTMASK 0x8001
++#endif
++
++#ifndef MDIO_AN_INT
++#define MDIO_AN_INT 0x8002
++#endif
++
++#ifndef MDIO_AN_KR_CTRL
++#define MDIO_AN_KR_CTRL 0x8003
++#endif
++
++#ifndef MDIO_CTRL1_SPEED1G
++#define MDIO_CTRL1_SPEED1G (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100)
++#endif
++
++#ifndef MDIO_KR_CTRL_PDETECT
++#define MDIO_KR_CTRL_PDETECT 0x01
++#endif
++
++#define GET_BITS(_var, _index, _width) \
++ (((_var) >> (_index)) & ((0x1 << (_width)) - 1))
++
++#define SET_BITS(_var, _index, _width, _val) \
++do { \
++ (_var) &= ~(((0x1 << (_width)) - 1) << (_index)); \
++ (_var) |= (((_val) & ((0x1 << (_width)) - 1)) << (_index)); \
++} while (0)
++
++#define XCMU_IOREAD(_priv, _reg) \
++ ioread16((_priv)->cmu_regs + _reg)
++
++#define XCMU_IOWRITE(_priv, _reg, _val) \
++ iowrite16((_val), (_priv)->cmu_regs + _reg)
++
++#define XRXTX_IOREAD(_priv, _reg) \
++ ioread16((_priv)->rxtx_regs + _reg)
++
++#define XRXTX_IOREAD_BITS(_priv, _reg, _field) \
++ GET_BITS(XRXTX_IOREAD((_priv), _reg), \
++ _reg##_##_field##_INDEX, \
++ _reg##_##_field##_WIDTH)
++
++#define XRXTX_IOWRITE(_priv, _reg, _val) \
++ iowrite16((_val), (_priv)->rxtx_regs + _reg)
++
++#define XRXTX_IOWRITE_BITS(_priv, _reg, _field, _val) \
++do { \
++ u16 reg_val = XRXTX_IOREAD((_priv), _reg); \
++ SET_BITS(reg_val, \
++ _reg##_##_field##_INDEX, \
++ _reg##_##_field##_WIDTH, (_val)); \
++ XRXTX_IOWRITE((_priv), _reg, reg_val); \
++} while (0)
++
++/* SerDes CMU register offsets */
++#define CMU_REG15 0x003c
++#define CMU_REG16 0x0040
++
++/* SerDes CMU register entry bit positions and sizes */
++#define CMU_REG16_TX_RATE_CHANGE_BASE 15
++#define CMU_REG16_RX_RATE_CHANGE_BASE 14
++#define CMU_REG16_RATE_CHANGE_DECR 2
++
++/* SerDes RxTx register offsets */
++#define RXTX_REG2 0x0008
++#define RXTX_REG3 0x000c
++#define RXTX_REG5 0x0014
++#define RXTX_REG6 0x0018
++#define RXTX_REG20 0x0050
++#define RXTX_REG53 0x00d4
++#define RXTX_REG114 0x01c8
++#define RXTX_REG115 0x01cc
++#define RXTX_REG142 0x0238
++
++/* SerDes RxTx register entry bit positions and sizes */
++#define RXTX_REG2_RESETB_INDEX 15
++#define RXTX_REG2_RESETB_WIDTH 1
++#define RXTX_REG3_TX_DATA_RATE_INDEX 14
++#define RXTX_REG3_TX_DATA_RATE_WIDTH 2
++#define RXTX_REG3_TX_WORD_MODE_INDEX 11
++#define RXTX_REG3_TX_WORD_MODE_WIDTH 3
++#define RXTX_REG5_TXAMP_CNTL_INDEX 7
++#define RXTX_REG5_TXAMP_CNTL_WIDTH 4
++#define RXTX_REG6_RX_DATA_RATE_INDEX 9
++#define RXTX_REG6_RX_DATA_RATE_WIDTH 2
++#define RXTX_REG6_RX_WORD_MODE_INDEX 11
++#define RXTX_REG6_RX_WORD_MODE_WIDTH 3
++#define RXTX_REG20_BLWC_ENA_INDEX 2
++#define RXTX_REG20_BLWC_ENA_WIDTH 1
++#define RXTX_REG53_RX_PLLSELECT_INDEX 15
++#define RXTX_REG53_RX_PLLSELECT_WIDTH 1
++#define RXTX_REG53_TX_PLLSELECT_INDEX 14
++#define RXTX_REG53_TX_PLLSELECT_WIDTH 1
++#define RXTX_REG53_PI_SPD_SEL_CDR_INDEX 10
++#define RXTX_REG53_PI_SPD_SEL_CDR_WIDTH 4
++#define RXTX_REG114_PQ_REG_INDEX 9
++#define RXTX_REG114_PQ_REG_WIDTH 7
++#define RXTX_REG115_FORCE_LAT_CAL_START_INDEX 2
++#define RXTX_REG115_FORCE_LAT_CAL_START_WIDTH 1
++#define RXTX_REG115_FORCE_SUM_CAL_START_INDEX 1
++#define RXTX_REG115_FORCE_SUM_CAL_START_WIDTH 1
++#define RXTX_REG142_SUM_CALIB_DONE_INDEX 15
++#define RXTX_REG142_SUM_CALIB_DONE_WIDTH 1
++#define RXTX_REG142_SUM_CALIB_ERR_INDEX 14
++#define RXTX_REG142_SUM_CALIB_ERR_WIDTH 1
++#define RXTX_REG142_LAT_CALIB_DONE_INDEX 11
++#define RXTX_REG142_LAT_CALIB_DONE_WIDTH 1
++
++#define RXTX_FULL_RATE 0x0
++#define RXTX_HALF_RATE 0x1
++#define RXTX_FIFTH_RATE 0x3
++#define RXTX_66BIT_WORD 0x7
++#define RXTX_10BIT_WORD 0x1
++#define RXTX_10G_BLWC 0x0
++#define RXTX_1G_BLWC 0x1
++#define RXTX_10G_TX_AMP 0xa
++#define RXTX_1G_TX_AMP 0xf
++#define RXTX_10G_CDR 0x7
++#define RXTX_1G_CDR 0x2
++#define RXTX_10G_PLL 0x1
++#define RXTX_1G_PLL 0x0
++#define RXTX_10G_PQ 0x1e
++#define RXTX_1G_PQ 0xa
++
++DEFINE_SPINLOCK(cmu_lock);
++
++static const u32 amd_xgbe_phy_serdes_blwc[] = {
++ RXTX_1G_BLWC,
++ RXTX_1G_BLWC,
++ RXTX_10G_BLWC,
++};
++
++static const u32 amd_xgbe_phy_serdes_cdr_rate[] = {
++ RXTX_1G_CDR,
++ RXTX_1G_CDR,
++ RXTX_10G_CDR,
++};
++
++static const u32 amd_xgbe_phy_serdes_pq_skew[] = {
++ RXTX_1G_PQ,
++ RXTX_1G_PQ,
++ RXTX_10G_PQ,
++};
++
++static const u32 amd_xgbe_phy_serdes_tx_amp[] = {
++ RXTX_1G_TX_AMP,
++ RXTX_1G_TX_AMP,
++ RXTX_10G_TX_AMP,
++};
++
++enum amd_xgbe_phy_an {
++ AMD_XGBE_AN_READY = 0,
++ AMD_XGBE_AN_PAGE_RECEIVED,
++ AMD_XGBE_AN_INCOMPAT_LINK,
++ AMD_XGBE_AN_COMPLETE,
++ AMD_XGBE_AN_NO_LINK,
++ AMD_XGBE_AN_ERROR,
++};
++
++enum amd_xgbe_phy_rx {
++ AMD_XGBE_RX_BPA = 0,
++ AMD_XGBE_RX_XNP,
++ AMD_XGBE_RX_COMPLETE,
++ AMD_XGBE_RX_ERROR,
++};
++
++enum amd_xgbe_phy_mode {
++ AMD_XGBE_MODE_KR,
++ AMD_XGBE_MODE_KX,
++};
++
++enum amd_xgbe_phy_speedset {
++ AMD_XGBE_PHY_SPEEDSET_1000_10000 = 0,
++ AMD_XGBE_PHY_SPEEDSET_2500_10000,
++};
++
++struct amd_xgbe_phy_priv {
++ struct platform_device *pdev;
++ struct acpi_device *adev;
++ struct device *dev;
++
++ struct phy_device *phydev;
++
++ /* SerDes related mmio resources */
++ struct resource *rxtx_res;
++ struct resource *cmu_res;
++
++ /* SerDes related mmio registers */
++ void __iomem *rxtx_regs; /* SerDes Rx/Tx CSRs */
++ void __iomem *cmu_regs; /* SerDes CMU CSRs */
++
++ int an_irq;
++ char an_irq_name[IFNAMSIZ + 32];
++ struct work_struct an_irq_work;
++ unsigned int an_irq_allocated;
++
++ unsigned int serdes_channel;
++ unsigned int speed_set;
++
++ /* Maintain link status for re-starting auto-negotiation */
++ unsigned int link;
++
++ /* SerDes UEFI configurable settings.
++ * Switching between modes/speeds requires new values for some
++ * SerDes settings. The values can be supplied as device
++ * properties in array format. The first array entry is for
++ * 1GbE, second for 2.5GbE and third for 10GbE
++ */
++ u32 serdes_blwc[XGBE_PHY_SPEEDS];
++ u32 serdes_cdr_rate[XGBE_PHY_SPEEDS];
++ u32 serdes_pq_skew[XGBE_PHY_SPEEDS];
++ u32 serdes_tx_amp[XGBE_PHY_SPEEDS];
++
++ /* Auto-negotiation state machine support */
++ struct mutex an_mutex;
++ enum amd_xgbe_phy_an an_result;
++ enum amd_xgbe_phy_an an_state;
++ enum amd_xgbe_phy_rx kr_state;
++ enum amd_xgbe_phy_rx kx_state;
++ struct work_struct an_work;
++ struct workqueue_struct *an_workqueue;
++ unsigned int an_supported;
++ unsigned int parallel_detect;
++ unsigned int fec_ability;
++
++ unsigned int lpm_ctrl; /* CTRL1 for resume */
++};
++
++static int amd_xgbe_an_disable_kr_training(struct phy_device *phydev)
++{
++ int ret;
++
++ ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
++ if (ret < 0)
++ return ret;
++
++ ret &= ~XGBE_PHY_KR_TRAINING_ENABLE;
++ phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, ret);
++
++ return 0;
++}
++
++static int amd_xgbe_phy_pcs_power_cycle(struct phy_device *phydev)
++{
++ int ret;
++
++ ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
++ if (ret < 0)
++ return ret;
++
++ ret |= MDIO_CTRL1_LPOWER;
++ phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
++
++ usleep_range(75, 100);
++
++ ret &= ~MDIO_CTRL1_LPOWER;
++ phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
++
++ return 0;
++}
++
++static void amd_xgbe_phy_serdes_start_ratechange(struct phy_device *phydev)
++{
++ struct amd_xgbe_phy_priv *priv = phydev->priv;
++ u16 val, mask;
++
++ /* Assert Rx and Tx ratechange in CMU_reg16 */
++ val = XCMU_IOREAD(priv, CMU_REG16);
++
++ mask = (1 << (CMU_REG16_TX_RATE_CHANGE_BASE -
++ (priv->serdes_channel * CMU_REG16_RATE_CHANGE_DECR))) |
++ (1 << (CMU_REG16_RX_RATE_CHANGE_BASE -
++ (priv->serdes_channel * CMU_REG16_RATE_CHANGE_DECR)));
++ val |= mask;
++
++ XCMU_IOWRITE(priv, CMU_REG16, val);
++}
++
++static void amd_xgbe_phy_serdes_complete_ratechange(struct phy_device *phydev)
++{
++ struct amd_xgbe_phy_priv *priv = phydev->priv;
++ u16 val, mask;
++ unsigned int wait;
++
++ /* Release Rx and Tx ratechange for proper channel in CMU_reg16 */
++ val = XCMU_IOREAD(priv, CMU_REG16);
++
++ mask = (1 << (CMU_REG16_TX_RATE_CHANGE_BASE -
++ (priv->serdes_channel * CMU_REG16_RATE_CHANGE_DECR))) |
++ (1 << (CMU_REG16_RX_RATE_CHANGE_BASE -
++ (priv->serdes_channel * CMU_REG16_RATE_CHANGE_DECR)));
++ val &= ~mask;
++
++ XCMU_IOWRITE(priv, CMU_REG16, val);
++
++ /* Wait for Rx and Tx ready in CMU_reg15 */
++ mask = (1 << priv->serdes_channel) |
++ (1 << (priv->serdes_channel + 8));
++ wait = XGBE_PHY_RATECHANGE_COUNT;
++ while (wait--) {
++ udelay(50);
++
++ val = XCMU_IOREAD(priv, CMU_REG15);
++ if ((val & mask) == mask)
++ return;
++ }
++
++ netdev_dbg(phydev->attached_dev, "SerDes rx/tx not ready (%#hx)\n",
++ val);
++}
++
++static int amd_xgbe_phy_xgmii_mode(struct phy_device *phydev)
++{
++ struct amd_xgbe_phy_priv *priv = phydev->priv;
++ int ret;
++
++ /* Disable KR training */
++ ret = amd_xgbe_an_disable_kr_training(phydev);
++ if (ret < 0)
++ return ret;
++
++ /* Set PCS to KR/10G speed */
++ ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
++ if (ret < 0)
++ return ret;
++
++ ret &= ~MDIO_PCS_CTRL2_TYPE;
++ ret |= MDIO_PCS_CTRL2_10GBR;
++ phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2, ret);
++
++ ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
++ if (ret < 0)
++ return ret;
++
++ ret &= ~MDIO_CTRL1_SPEEDSEL;
++ ret |= MDIO_CTRL1_SPEED10G;
++ phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
++
++ ret = amd_xgbe_phy_pcs_power_cycle(phydev);
++ if (ret < 0)
++ return ret;
++
++ /* Set SerDes to 10G speed */
++ spin_lock(&cmu_lock);
++
++ amd_xgbe_phy_serdes_start_ratechange(phydev);
++
++ XRXTX_IOWRITE_BITS(priv, RXTX_REG3, TX_DATA_RATE, RXTX_FULL_RATE);
++ XRXTX_IOWRITE_BITS(priv, RXTX_REG3, TX_WORD_MODE, RXTX_66BIT_WORD);
++
++ XRXTX_IOWRITE_BITS(priv, RXTX_REG5, TXAMP_CNTL,
++ priv->serdes_tx_amp[XGBE_PHY_SPEED_10000]);
++
++ XRXTX_IOWRITE_BITS(priv, RXTX_REG6, RX_DATA_RATE, RXTX_FULL_RATE);
++ XRXTX_IOWRITE_BITS(priv, RXTX_REG6, RX_WORD_MODE, RXTX_66BIT_WORD);
++
++ XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA,
++ priv->serdes_blwc[XGBE_PHY_SPEED_10000]);
++
++ XRXTX_IOWRITE_BITS(priv, RXTX_REG53, RX_PLLSELECT, RXTX_10G_PLL);
++ XRXTX_IOWRITE_BITS(priv, RXTX_REG53, TX_PLLSELECT, RXTX_10G_PLL);
++ XRXTX_IOWRITE_BITS(priv, RXTX_REG53, PI_SPD_SEL_CDR,
++ priv->serdes_cdr_rate[XGBE_PHY_SPEED_10000]);
++
++ XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG,
++ priv->serdes_pq_skew[XGBE_PHY_SPEED_10000]);
++
++ amd_xgbe_phy_serdes_complete_ratechange(phydev);
++
++ spin_unlock(&cmu_lock);
++
++ return 0;
++}
++
++static int amd_xgbe_phy_gmii_2500_mode(struct phy_device *phydev)
++{
++ struct amd_xgbe_phy_priv *priv = phydev->priv;
++ int ret;
++
++ /* Disable KR training */
++ ret = amd_xgbe_an_disable_kr_training(phydev);
++ if (ret < 0)
++ return ret;
++
++ /* Set PCS to KX/1G speed */
++ ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
++ if (ret < 0)
++ return ret;
++
++ ret &= ~MDIO_PCS_CTRL2_TYPE;
++ ret |= MDIO_PCS_CTRL2_10GBX;
++ phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2, ret);
++
++ ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
++ if (ret < 0)
++ return ret;
++
++ ret &= ~MDIO_CTRL1_SPEEDSEL;
++ ret |= MDIO_CTRL1_SPEED1G;
++ phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
++
++ ret = amd_xgbe_phy_pcs_power_cycle(phydev);
++ if (ret < 0)
++ return ret;
++
++ /* Set SerDes to 2.5G speed */
++ spin_lock(&cmu_lock);
++
++ amd_xgbe_phy_serdes_start_ratechange(phydev);
++
++ XRXTX_IOWRITE_BITS(priv, RXTX_REG3, TX_DATA_RATE, RXTX_HALF_RATE);
++ XRXTX_IOWRITE_BITS(priv, RXTX_REG3, TX_WORD_MODE, RXTX_10BIT_WORD);
++
++ XRXTX_IOWRITE_BITS(priv, RXTX_REG5, TXAMP_CNTL,
++ priv->serdes_tx_amp[XGBE_PHY_SPEED_2500]);
++
++ XRXTX_IOWRITE_BITS(priv, RXTX_REG6, RX_DATA_RATE, RXTX_HALF_RATE);
++ XRXTX_IOWRITE_BITS(priv, RXTX_REG6, RX_WORD_MODE, RXTX_10BIT_WORD);
++
++ XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA,
++ priv->serdes_blwc[XGBE_PHY_SPEED_2500]);
++
++ XRXTX_IOWRITE_BITS(priv, RXTX_REG53, RX_PLLSELECT, RXTX_1G_PLL);
++ XRXTX_IOWRITE_BITS(priv, RXTX_REG53, TX_PLLSELECT, RXTX_1G_PLL);
++ XRXTX_IOWRITE_BITS(priv, RXTX_REG53, PI_SPD_SEL_CDR,
++ priv->serdes_cdr_rate[XGBE_PHY_SPEED_2500]);
++
++ XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG,
++ priv->serdes_pq_skew[XGBE_PHY_SPEED_2500]);
++
++ amd_xgbe_phy_serdes_complete_ratechange(phydev);
++
++ spin_unlock(&cmu_lock);
++
++ return 0;
++}
++
++static int amd_xgbe_phy_gmii_mode(struct phy_device *phydev)
++{
++ struct amd_xgbe_phy_priv *priv = phydev->priv;
++ int ret;
++
++ /* Disable KR training */
++ ret = amd_xgbe_an_disable_kr_training(phydev);
++ if (ret < 0)
++ return ret;
++
++ /* Set PCS to KX/1G speed */
++ ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
++ if (ret < 0)
++ return ret;
++
++ ret &= ~MDIO_PCS_CTRL2_TYPE;
++ ret |= MDIO_PCS_CTRL2_10GBX;
++ phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2, ret);
++
++ ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
++ if (ret < 0)
++ return ret;
++
++ ret &= ~MDIO_CTRL1_SPEEDSEL;
++ ret |= MDIO_CTRL1_SPEED1G;
++ phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
++
++ ret = amd_xgbe_phy_pcs_power_cycle(phydev);
++ if (ret < 0)
++ return ret;
++
++ /* Set SerDes to 1G speed */
++ spin_lock(&cmu_lock);
++
++ amd_xgbe_phy_serdes_start_ratechange(phydev);
++
++ XRXTX_IOWRITE_BITS(priv, RXTX_REG3, TX_DATA_RATE, RXTX_FIFTH_RATE);
++ XRXTX_IOWRITE_BITS(priv, RXTX_REG3, TX_WORD_MODE, RXTX_10BIT_WORD);
++
++ XRXTX_IOWRITE_BITS(priv, RXTX_REG5, TXAMP_CNTL,
++ priv->serdes_tx_amp[XGBE_PHY_SPEED_1000]);
++
++ XRXTX_IOWRITE_BITS(priv, RXTX_REG6, RX_DATA_RATE, RXTX_FIFTH_RATE);
++ XRXTX_IOWRITE_BITS(priv, RXTX_REG6, RX_WORD_MODE, RXTX_10BIT_WORD);
++
++ XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA,
++ priv->serdes_blwc[XGBE_PHY_SPEED_1000]);
++
++ XRXTX_IOWRITE_BITS(priv, RXTX_REG53, RX_PLLSELECT, RXTX_1G_PLL);
++ XRXTX_IOWRITE_BITS(priv, RXTX_REG53, TX_PLLSELECT, RXTX_1G_PLL);
++ XRXTX_IOWRITE_BITS(priv, RXTX_REG53, PI_SPD_SEL_CDR,
++ priv->serdes_cdr_rate[XGBE_PHY_SPEED_1000]);
++
++ XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG,
++ priv->serdes_pq_skew[XGBE_PHY_SPEED_1000]);
++
++ amd_xgbe_phy_serdes_complete_ratechange(phydev);
++
++ spin_unlock(&cmu_lock);
++
++ return 0;
++}
++
++static int amd_xgbe_phy_cur_mode(struct phy_device *phydev,
++ enum amd_xgbe_phy_mode *mode)
++{
++ int ret;
++
++ ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
++ if (ret < 0)
++ return ret;
++
++ if ((ret & MDIO_PCS_CTRL2_TYPE) == MDIO_PCS_CTRL2_10GBR)
++ *mode = AMD_XGBE_MODE_KR;
++ else
++ *mode = AMD_XGBE_MODE_KX;
++
++ return 0;
++}
++
++static bool amd_xgbe_phy_in_kr_mode(struct phy_device *phydev)
++{
++ enum amd_xgbe_phy_mode mode;
++
++ if (amd_xgbe_phy_cur_mode(phydev, &mode))
++ return false;
++
++ return (mode == AMD_XGBE_MODE_KR);
++}
++
++static int amd_xgbe_phy_switch_mode(struct phy_device *phydev)
++{
++ struct amd_xgbe_phy_priv *priv = phydev->priv;
++ int ret;
++
++ /* If we are in KR switch to KX, and vice-versa */
++ if (amd_xgbe_phy_in_kr_mode(phydev)) {
++ if (priv->speed_set == AMD_XGBE_PHY_SPEEDSET_1000_10000)
++ ret = amd_xgbe_phy_gmii_mode(phydev);
++ else
++ ret = amd_xgbe_phy_gmii_2500_mode(phydev);
++ } else {
++ ret = amd_xgbe_phy_xgmii_mode(phydev);
++ }
++
++ return ret;
++}
++
++static int amd_xgbe_phy_set_mode(struct phy_device *phydev,
++ enum amd_xgbe_phy_mode mode)
++{
++ enum amd_xgbe_phy_mode cur_mode;
++ int ret;
++
++ ret = amd_xgbe_phy_cur_mode(phydev, &cur_mode);
++ if (ret)
++ return ret;
++
++ if (mode != cur_mode)
++ ret = amd_xgbe_phy_switch_mode(phydev);
++
++ return ret;
++}
++
++static int amd_xgbe_phy_set_an(struct phy_device *phydev, bool enable,
++ bool restart)
++{
++ int ret;
++
++ ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
++ if (ret < 0)
++ return ret;
++
++ ret &= ~MDIO_AN_CTRL1_ENABLE;
++
++ if (enable)
++ ret |= MDIO_AN_CTRL1_ENABLE;
++
++ if (restart)
++ ret |= MDIO_AN_CTRL1_RESTART;
++
++ phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1, ret);
++
++ return 0;
++}
++
++static int amd_xgbe_phy_restart_an(struct phy_device *phydev)
++{
++ return amd_xgbe_phy_set_an(phydev, true, true);
++}
++
++static int amd_xgbe_phy_disable_an(struct phy_device *phydev)
++{
++ return amd_xgbe_phy_set_an(phydev, false, false);
++}
++
++static enum amd_xgbe_phy_an amd_xgbe_an_tx_training(struct phy_device *phydev,
++ enum amd_xgbe_phy_rx *state)
++{
++ struct amd_xgbe_phy_priv *priv = phydev->priv;
++ int ad_reg, lp_reg, ret;
++
++ *state = AMD_XGBE_RX_COMPLETE;
++
++ /* If we're not in KR mode then we're done */
++ if (!amd_xgbe_phy_in_kr_mode(phydev))
++ return AMD_XGBE_AN_PAGE_RECEIVED;
++
++ /* Enable/Disable FEC */
++ ad_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
++ if (ad_reg < 0)
++ return AMD_XGBE_AN_ERROR;
++
++ lp_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA + 2);
++ if (lp_reg < 0)
++ return AMD_XGBE_AN_ERROR;
++
++ ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FEC_CTRL);
++ if (ret < 0)
++ return AMD_XGBE_AN_ERROR;
++
++ ret &= ~XGBE_PHY_FEC_MASK;
++ if ((ad_reg & 0xc000) && (lp_reg & 0xc000))
++ ret |= priv->fec_ability;
++
++ phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FEC_CTRL, ret);
++
++ /* Start KR training */
++ ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL);
++ if (ret < 0)
++ return AMD_XGBE_AN_ERROR;
++
++ if (ret & XGBE_PHY_KR_TRAINING_ENABLE) {
++ ret |= XGBE_PHY_KR_TRAINING_START;
++ phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL,
++ ret);
++ }
++
++ return AMD_XGBE_AN_PAGE_RECEIVED;
++}
++
++static enum amd_xgbe_phy_an amd_xgbe_an_tx_xnp(struct phy_device *phydev,
++ enum amd_xgbe_phy_rx *state)
++{
++ u16 msg;
++
++ *state = AMD_XGBE_RX_XNP;
++
++ msg = XNP_MCF_NULL_MESSAGE;
++ msg |= XNP_MP_FORMATTED;
++
++ phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_XNP + 2, 0);
++ phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_XNP + 1, 0);
++ phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_XNP, msg);
++
++ return AMD_XGBE_AN_PAGE_RECEIVED;
++}
++
++static enum amd_xgbe_phy_an amd_xgbe_an_rx_bpa(struct phy_device *phydev,
++ enum amd_xgbe_phy_rx *state)
++{
++ unsigned int link_support;
++ int ret, ad_reg, lp_reg;
++
++ /* Read Base Ability register 2 first */
++ ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA + 1);
++ if (ret < 0)
++ return AMD_XGBE_AN_ERROR;
++
++ /* Check for a supported mode, otherwise restart in a different one */
++ link_support = amd_xgbe_phy_in_kr_mode(phydev) ? 0x80 : 0x20;
++ if (!(ret & link_support))
++ return AMD_XGBE_AN_INCOMPAT_LINK;
++
++ /* Check Extended Next Page support */
++ ad_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
++ if (ad_reg < 0)
++ return AMD_XGBE_AN_ERROR;
++
++ lp_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA);
++ if (lp_reg < 0)
++ return AMD_XGBE_AN_ERROR;
++
++ return ((ad_reg & XNP_NP_EXCHANGE) || (lp_reg & XNP_NP_EXCHANGE)) ?
++ amd_xgbe_an_tx_xnp(phydev, state) :
++ amd_xgbe_an_tx_training(phydev, state);
++}
++
++static enum amd_xgbe_phy_an amd_xgbe_an_rx_xnp(struct phy_device *phydev,
++ enum amd_xgbe_phy_rx *state)
++{
++ int ad_reg, lp_reg;
++
++ /* Check Extended Next Page support */
++ ad_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_XNP);
++ if (ad_reg < 0)
++ return AMD_XGBE_AN_ERROR;
++
++ lp_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPX);
++ if (lp_reg < 0)
++ return AMD_XGBE_AN_ERROR;
++
++ return ((ad_reg & XNP_NP_EXCHANGE) || (lp_reg & XNP_NP_EXCHANGE)) ?
++ amd_xgbe_an_tx_xnp(phydev, state) :
++ amd_xgbe_an_tx_training(phydev, state);
++}
++
++static enum amd_xgbe_phy_an amd_xgbe_an_page_received(struct phy_device *phydev)
++{
++ struct amd_xgbe_phy_priv *priv = phydev->priv;
++ enum amd_xgbe_phy_rx *state;
++ int ret;
++
++ state = amd_xgbe_phy_in_kr_mode(phydev) ? &priv->kr_state
++ : &priv->kx_state;
++
++ switch (*state) {
++ case AMD_XGBE_RX_BPA:
++ ret = amd_xgbe_an_rx_bpa(phydev, state);
++ break;
++
++ case AMD_XGBE_RX_XNP:
++ ret = amd_xgbe_an_rx_xnp(phydev, state);
++ break;
++
++ default:
++ ret = AMD_XGBE_AN_ERROR;
++ }
++
++ return ret;
++}
++
++static enum amd_xgbe_phy_an amd_xgbe_an_incompat_link(struct phy_device *phydev)
++{
++ struct amd_xgbe_phy_priv *priv = phydev->priv;
++ int ret;
++
++ /* Be sure we aren't looping trying to negotiate */
++ if (amd_xgbe_phy_in_kr_mode(phydev)) {
++ priv->kr_state = AMD_XGBE_RX_ERROR;
++
++ if (!(phydev->supported & SUPPORTED_1000baseKX_Full) &&
++ !(phydev->supported & SUPPORTED_2500baseX_Full))
++ return AMD_XGBE_AN_NO_LINK;
++
++ if (priv->kx_state != AMD_XGBE_RX_BPA)
++ return AMD_XGBE_AN_NO_LINK;
++ } else {
++ priv->kx_state = AMD_XGBE_RX_ERROR;
++
++ if (!(phydev->supported & SUPPORTED_10000baseKR_Full))
++ return AMD_XGBE_AN_NO_LINK;
++
++ if (priv->kr_state != AMD_XGBE_RX_BPA)
++ return AMD_XGBE_AN_NO_LINK;
++ }
++
++ ret = amd_xgbe_phy_disable_an(phydev);
++ if (ret)
++ return AMD_XGBE_AN_ERROR;
++
++ ret = amd_xgbe_phy_switch_mode(phydev);
++ if (ret)
++ return AMD_XGBE_AN_ERROR;
++
++ ret = amd_xgbe_phy_restart_an(phydev);
++ if (ret)
++ return AMD_XGBE_AN_ERROR;
++
++ return AMD_XGBE_AN_INCOMPAT_LINK;
++}
++
++static irqreturn_t amd_xgbe_an_isr(int irq, void *data)
++{
++ struct amd_xgbe_phy_priv *priv = (struct amd_xgbe_phy_priv *)data;
++
++ /* Interrupt reason must be read and cleared outside of IRQ context */
++ disable_irq_nosync(priv->an_irq);
++
++ queue_work(priv->an_workqueue, &priv->an_irq_work);
++
++ return IRQ_HANDLED;
++}
++
++static void amd_xgbe_an_irq_work(struct work_struct *work)
++{
++ struct amd_xgbe_phy_priv *priv = container_of(work,
++ struct amd_xgbe_phy_priv,
++ an_irq_work);
++
++ /* Avoid a race between enabling the IRQ and exiting the work by
++ * waiting for the work to finish and then queueing it
++ */
++ flush_work(&priv->an_work);
++ queue_work(priv->an_workqueue, &priv->an_work);
++}
++
++static void amd_xgbe_an_state_machine(struct work_struct *work)
++{
++ struct amd_xgbe_phy_priv *priv = container_of(work,
++ struct amd_xgbe_phy_priv,
++ an_work);
++ struct phy_device *phydev = priv->phydev;
++ enum amd_xgbe_phy_an cur_state = priv->an_state;
++ int int_reg, int_mask;
++
++ mutex_lock(&priv->an_mutex);
++
++ /* Read the interrupt */
++ int_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT);
++ if (!int_reg)
++ goto out;
++
++next_int:
++ if (int_reg < 0) {
++ priv->an_state = AMD_XGBE_AN_ERROR;
++ int_mask = XGBE_AN_INT_MASK;
++ } else if (int_reg & XGBE_AN_PG_RCV) {
++ priv->an_state = AMD_XGBE_AN_PAGE_RECEIVED;
++ int_mask = XGBE_AN_PG_RCV;
++ } else if (int_reg & XGBE_AN_INC_LINK) {
++ priv->an_state = AMD_XGBE_AN_INCOMPAT_LINK;
++ int_mask = XGBE_AN_INC_LINK;
++ } else if (int_reg & XGBE_AN_INT_CMPLT) {
++ priv->an_state = AMD_XGBE_AN_COMPLETE;
++ int_mask = XGBE_AN_INT_CMPLT;
++ } else {
++ priv->an_state = AMD_XGBE_AN_ERROR;
++ int_mask = 0;
++ }
++
++ /* Clear the interrupt to be processed */
++ int_reg &= ~int_mask;
++ phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, int_reg);
++
++ priv->an_result = priv->an_state;
++
++again:
++ cur_state = priv->an_state;
++
++ switch (priv->an_state) {
++ case AMD_XGBE_AN_READY:
++ priv->an_supported = 0;
++ break;
++
++ case AMD_XGBE_AN_PAGE_RECEIVED:
++ priv->an_state = amd_xgbe_an_page_received(phydev);
++ priv->an_supported++;
++ break;
++
++ case AMD_XGBE_AN_INCOMPAT_LINK:
++ priv->an_supported = 0;
++ priv->parallel_detect = 0;
++ priv->an_state = amd_xgbe_an_incompat_link(phydev);
++ break;
++
++ case AMD_XGBE_AN_COMPLETE:
++ priv->parallel_detect = priv->an_supported ? 0 : 1;
++ netdev_dbg(phydev->attached_dev, "%s successful\n",
++ priv->an_supported ? "Auto negotiation"
++ : "Parallel detection");
++ break;
++
++ case AMD_XGBE_AN_NO_LINK:
++ break;
++
++ default:
++ priv->an_state = AMD_XGBE_AN_ERROR;
++ }
++
++ if (priv->an_state == AMD_XGBE_AN_NO_LINK) {
++ /* Disable auto-negotiation for now - it will be
++ * re-enabled once a link is established
++ */
++ amd_xgbe_phy_disable_an(phydev);
++
++ int_reg = 0;
++ phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0);
++ } else if (priv->an_state == AMD_XGBE_AN_ERROR) {
++ netdev_err(phydev->attached_dev,
++ "error during auto-negotiation, state=%u\n",
++ cur_state);
++
++ int_reg = 0;
++ phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0);
++ }
++
++ if (priv->an_state >= AMD_XGBE_AN_COMPLETE) {
++ priv->an_result = priv->an_state;
++ priv->an_state = AMD_XGBE_AN_READY;
++ priv->kr_state = AMD_XGBE_RX_BPA;
++ priv->kx_state = AMD_XGBE_RX_BPA;
++ }
++
++ if (cur_state != priv->an_state)
++ goto again;
++
++ if (int_reg)
++ goto next_int;
++
++out:
++ enable_irq(priv->an_irq);
++
++ mutex_unlock(&priv->an_mutex);
++}
++
++static int amd_xgbe_an_init(struct phy_device *phydev)
++{
++ int ret;
++
++ /* Set up Advertisement register 3 first */
++ ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2);
++ if (ret < 0)
++ return ret;
++
++ if (phydev->supported & SUPPORTED_10000baseR_FEC)
++ ret |= 0xc000;
++ else
++ ret &= ~0xc000;
++
++ phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2, ret);
++
++ /* Set up Advertisement register 2 next */
++ ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1);
++ if (ret < 0)
++ return ret;
++
++ if (phydev->supported & SUPPORTED_10000baseKR_Full)
++ ret |= 0x80;
++ else
++ ret &= ~0x80;
++
++ if ((phydev->supported & SUPPORTED_1000baseKX_Full) ||
++ (phydev->supported & SUPPORTED_2500baseX_Full))
++ ret |= 0x20;
++ else
++ ret &= ~0x20;
++
++ phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1, ret);
++
++ /* Set up Advertisement register 1 last */
++ ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
++ if (ret < 0)
++ return ret;
++
++ if (phydev->supported & SUPPORTED_Pause)
++ ret |= 0x400;
++ else
++ ret &= ~0x400;
++
++ if (phydev->supported & SUPPORTED_Asym_Pause)
++ ret |= 0x800;
++ else
++ ret &= ~0x800;
++
++ /* We don't intend to perform XNP */
++ ret &= ~XNP_NP_EXCHANGE;
++
++ phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, ret);
++
++ return 0;
++}
++
++static int amd_xgbe_phy_soft_reset(struct phy_device *phydev)
++{
++ int count, ret;
++
++ ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
++ if (ret < 0)
++ return ret;
++
++ ret |= MDIO_CTRL1_RESET;
++ phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
++
++ count = 50;
++ do {
++ msleep(20);
++ ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
++ if (ret < 0)
++ return ret;
++ } while ((ret & MDIO_CTRL1_RESET) && --count);
++
++ if (ret & MDIO_CTRL1_RESET)
++ return -ETIMEDOUT;
++
++ /* Disable auto-negotiation for now */
++ ret = amd_xgbe_phy_disable_an(phydev);
++ if (ret < 0)
++ return ret;
++
++ /* Clear auto-negotiation interrupts */
++ phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0);
++
++ return 0;
++}
++
++static int amd_xgbe_phy_config_init(struct phy_device *phydev)
++{
++ struct amd_xgbe_phy_priv *priv = phydev->priv;
++ struct net_device *netdev = phydev->attached_dev;
++ int ret;
++
++ if (!priv->an_irq_allocated) {
++ /* Allocate the auto-negotiation workqueue and interrupt */
++ snprintf(priv->an_irq_name, sizeof(priv->an_irq_name) - 1,
++ "%s-pcs", netdev_name(netdev));
++
++ priv->an_workqueue =
++ create_singlethread_workqueue(priv->an_irq_name);
++ if (!priv->an_workqueue) {
++ netdev_err(netdev, "phy workqueue creation failed\n");
++ return -ENOMEM;
++ }
++
++ ret = devm_request_irq(priv->dev, priv->an_irq,
++ amd_xgbe_an_isr, 0, priv->an_irq_name,
++ priv);
++ if (ret) {
++ netdev_err(netdev, "phy irq request failed\n");
++ destroy_workqueue(priv->an_workqueue);
++ return ret;
++ }
++
++ priv->an_irq_allocated = 1;
++ }
++
++ ret = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FEC_ABILITY);
++ if (ret < 0)
++ return ret;
++ priv->fec_ability = ret & XGBE_PHY_FEC_MASK;
++
++ /* Initialize supported features */
++ phydev->supported = SUPPORTED_Autoneg;
++ phydev->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
++ phydev->supported |= SUPPORTED_Backplane;
++ phydev->supported |= SUPPORTED_10000baseKR_Full;
++ switch (priv->speed_set) {
++ case AMD_XGBE_PHY_SPEEDSET_1000_10000:
++ phydev->supported |= SUPPORTED_1000baseKX_Full;
++ break;
++ case AMD_XGBE_PHY_SPEEDSET_2500_10000:
++ phydev->supported |= SUPPORTED_2500baseX_Full;
++ break;
++ }
++
++ if (priv->fec_ability & XGBE_PHY_FEC_ENABLE)
++ phydev->supported |= SUPPORTED_10000baseR_FEC;
++
++ phydev->advertising = phydev->supported;
++
++ /* Set initial mode - call the mode setting routines
++ * directly to insure we are properly configured
++ */
++ if (phydev->supported & SUPPORTED_10000baseKR_Full)
++ ret = amd_xgbe_phy_xgmii_mode(phydev);
++ else if (phydev->supported & SUPPORTED_1000baseKX_Full)
++ ret = amd_xgbe_phy_gmii_mode(phydev);
++ else if (phydev->supported & SUPPORTED_2500baseX_Full)
++ ret = amd_xgbe_phy_gmii_2500_mode(phydev);
++ else
++ ret = -EINVAL;
++ if (ret < 0)
++ return ret;
++
++ /* Set up advertisement registers based on current settings */
++ ret = amd_xgbe_an_init(phydev);
++ if (ret)
++ return ret;
++
++ /* Enable auto-negotiation interrupts */
++ phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INTMASK, 0x07);
++
++ return 0;
++}
++
++static int amd_xgbe_phy_setup_forced(struct phy_device *phydev)
++{
++ int ret;
++
++ /* Disable auto-negotiation */
++ ret = amd_xgbe_phy_disable_an(phydev);
++ if (ret < 0)
++ return ret;
++
++ /* Validate/Set specified speed */
++ switch (phydev->speed) {
++ case SPEED_10000:
++ ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KR);
++ break;
++
++ case SPEED_2500:
++ case SPEED_1000:
++ ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KX);
++ break;
++
++ default:
++ ret = -EINVAL;
++ }
++
++ if (ret < 0)
++ return ret;
++
++ /* Validate duplex mode */
++ if (phydev->duplex != DUPLEX_FULL)
++ return -EINVAL;
++
++ phydev->pause = 0;
++ phydev->asym_pause = 0;
++
++ return 0;
++}
++
++static int __amd_xgbe_phy_config_aneg(struct phy_device *phydev)
++{
++ struct amd_xgbe_phy_priv *priv = phydev->priv;
++ u32 mmd_mask = phydev->c45_ids.devices_in_package;
++ int ret;
++
++ if (phydev->autoneg != AUTONEG_ENABLE)
++ return amd_xgbe_phy_setup_forced(phydev);
++
++ /* Make sure we have the AN MMD present */
++ if (!(mmd_mask & MDIO_DEVS_AN))
++ return -EINVAL;
++
++ /* Disable auto-negotiation interrupt */
++ disable_irq(priv->an_irq);
++
++ /* Start auto-negotiation in a supported mode */
++ if (phydev->supported & SUPPORTED_10000baseKR_Full)
++ ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KR);
++ else if ((phydev->supported & SUPPORTED_1000baseKX_Full) ||
++ (phydev->supported & SUPPORTED_2500baseX_Full))
++ ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KX);
++ else
++ ret = -EINVAL;
++ if (ret < 0) {
++ enable_irq(priv->an_irq);
++ return ret;
++ }
++
++ /* Disable and stop any in progress auto-negotiation */
++ ret = amd_xgbe_phy_disable_an(phydev);
++ if (ret < 0)
++ return ret;
++
++ /* Clear any auto-negotitation interrupts */
++ phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0);
++
++ priv->an_result = AMD_XGBE_AN_READY;
++ priv->an_state = AMD_XGBE_AN_READY;
++ priv->kr_state = AMD_XGBE_RX_BPA;
++ priv->kx_state = AMD_XGBE_RX_BPA;
++
++ /* Re-enable auto-negotiation interrupt */
++ enable_irq(priv->an_irq);
++
++ /* Set up advertisement registers based on current settings */
++ ret = amd_xgbe_an_init(phydev);
++ if (ret)
++ return ret;
++
++ /* Enable and start auto-negotiation */
++ ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_KR_CTRL);
++ if (ret < 0)
++ return ret;
++
++ ret |= MDIO_KR_CTRL_PDETECT;
++ phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_KR_CTRL, ret);
++
++ return amd_xgbe_phy_restart_an(phydev);
++}
++
++static int amd_xgbe_phy_config_aneg(struct phy_device *phydev)
++{
++ struct amd_xgbe_phy_priv *priv = phydev->priv;
++ int ret;
++
++ mutex_lock(&priv->an_mutex);
++
++ ret = __amd_xgbe_phy_config_aneg(phydev);
++
++ mutex_unlock(&priv->an_mutex);
++
++ return ret;
++}
++
++static int amd_xgbe_phy_aneg_done(struct phy_device *phydev)
++{
++ struct amd_xgbe_phy_priv *priv = phydev->priv;
++
++ return (priv->an_result == AMD_XGBE_AN_COMPLETE);
++}
++
++static int amd_xgbe_phy_update_link(struct phy_device *phydev)
++{
++ struct amd_xgbe_phy_priv *priv = phydev->priv;
++ unsigned int check_again, autoneg;
++ int ret;
++
++ /* If we're doing auto-negotiation don't report link down */
++ if (priv->an_state != AMD_XGBE_AN_READY) {
++ phydev->link = 1;
++ return 0;
++ }
++
++ /* Since the device can be in the wrong mode when a link is
++ * (re-)established (cable connected after the interface is
++ * up, etc.), the link status may report no link. If there
++ * is no link, try switching modes and checking the status
++ * again if auto negotiation is enabled.
++ */
++ check_again = (phydev->autoneg == AUTONEG_ENABLE) ? 1 : 0;
++again:
++ /* Link status is latched low, so read once to clear
++ * and then read again to get current state
++ */
++ ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_STAT1);
++ if (ret < 0)
++ return ret;
++
++ ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_STAT1);
++ if (ret < 0)
++ return ret;
++
++ phydev->link = (ret & MDIO_STAT1_LSTATUS) ? 1 : 0;
++
++ if (!phydev->link) {
++ if (check_again) {
++ ret = amd_xgbe_phy_switch_mode(phydev);
++ if (ret < 0)
++ return ret;
++ check_again = 0;
++ goto again;
++ }
++ }
++
++ autoneg = (phydev->link && !priv->link) ? 1 : 0;
++ priv->link = phydev->link;
++ if (autoneg) {
++ /* Link is (back) up, re-start auto-negotiation */
++ ret = amd_xgbe_phy_config_aneg(phydev);
++ if (ret < 0)
++ return ret;
++ }
++
++ return 0;
++}
++
++static int amd_xgbe_phy_read_status(struct phy_device *phydev)
++{
++ struct amd_xgbe_phy_priv *priv = phydev->priv;
++ u32 mmd_mask = phydev->c45_ids.devices_in_package;
++ int ret, ad_ret, lp_ret;
++
++ ret = amd_xgbe_phy_update_link(phydev);
++ if (ret)
++ return ret;
++
++ if ((phydev->autoneg == AUTONEG_ENABLE) &&
++ !priv->parallel_detect) {
++ if (!(mmd_mask & MDIO_DEVS_AN))
++ return -EINVAL;
++
++ if (!amd_xgbe_phy_aneg_done(phydev))
++ return 0;
++
++ /* Compare Advertisement and Link Partner register 1 */
++ ad_ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
++ if (ad_ret < 0)
++ return ad_ret;
++ lp_ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA);
++ if (lp_ret < 0)
++ return lp_ret;
++
++ ad_ret &= lp_ret;
++ phydev->pause = (ad_ret & 0x400) ? 1 : 0;
++ phydev->asym_pause = (ad_ret & 0x800) ? 1 : 0;
++
++ /* Compare Advertisement and Link Partner register 2 */
++ ad_ret = phy_read_mmd(phydev, MDIO_MMD_AN,
++ MDIO_AN_ADVERTISE + 1);
++ if (ad_ret < 0)
++ return ad_ret;
++ lp_ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA + 1);
++ if (lp_ret < 0)
++ return lp_ret;
++
++ ad_ret &= lp_ret;
++ if (ad_ret & 0x80) {
++ phydev->speed = SPEED_10000;
++ ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KR);
++ if (ret)
++ return ret;
++ } else {
++ switch (priv->speed_set) {
++ case AMD_XGBE_PHY_SPEEDSET_1000_10000:
++ phydev->speed = SPEED_1000;
++ break;
++
++ case AMD_XGBE_PHY_SPEEDSET_2500_10000:
++ phydev->speed = SPEED_2500;
++ break;
++ }
++
++ ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KX);
++ if (ret)
++ return ret;
++ }
++
++ phydev->duplex = DUPLEX_FULL;
++ } else {
++ if (amd_xgbe_phy_in_kr_mode(phydev)) {
++ phydev->speed = SPEED_10000;
++ } else {
++ switch (priv->speed_set) {
++ case AMD_XGBE_PHY_SPEEDSET_1000_10000:
++ phydev->speed = SPEED_1000;
++ break;
++
++ case AMD_XGBE_PHY_SPEEDSET_2500_10000:
++ phydev->speed = SPEED_2500;
++ break;
++ }
++ }
++ phydev->duplex = DUPLEX_FULL;
++ phydev->pause = 0;
++ phydev->asym_pause = 0;
++ }
++
++ return 0;
++}
++
++static int amd_xgbe_phy_suspend(struct phy_device *phydev)
++{
++ struct amd_xgbe_phy_priv *priv = phydev->priv;
++ int ret;
++
++ mutex_lock(&phydev->lock);
++
++ ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1);
++ if (ret < 0)
++ goto unlock;
++
++ priv->lpm_ctrl = ret;
++
++ ret |= MDIO_CTRL1_LPOWER;
++ phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, ret);
++
++ ret = 0;
++
++unlock:
++ mutex_unlock(&phydev->lock);
++
++ return ret;
++}
++
++static int amd_xgbe_phy_resume(struct phy_device *phydev)
++{
++ struct amd_xgbe_phy_priv *priv = phydev->priv;
++
++ mutex_lock(&phydev->lock);
++
++ priv->lpm_ctrl &= ~MDIO_CTRL1_LPOWER;
++ phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, priv->lpm_ctrl);
++
++ mutex_unlock(&phydev->lock);
++
++ return 0;
++}
++
++static unsigned int amd_xgbe_phy_resource_count(struct platform_device *pdev,
++ unsigned int type)
++{
++ unsigned int count;
++ int i;
++
++ for (i = 0, count = 0; i < pdev->num_resources; i++) {
++ struct resource *r = &pdev->resource[i];
++
++ if (type == resource_type(r))
++ count++;
++ }
++
++ return count;
++}
++
++static int amd_xgbe_phy_probe(struct phy_device *phydev)
++{
++ struct amd_xgbe_phy_priv *priv;
++ struct platform_device *phy_pdev;
++ struct device *dev, *phy_dev;
++ unsigned int phy_resnum, phy_irqnum;
++ int ret;
++
++ if (!phydev->bus || !phydev->bus->parent)
++ return -EINVAL;
++
++ dev = phydev->bus->parent;
++
++ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
++ if (!priv)
++ return -ENOMEM;
++
++ priv->pdev = to_platform_device(dev);
++ priv->adev = ACPI_COMPANION(dev);
++ priv->dev = dev;
++ priv->phydev = phydev;
++ mutex_init(&priv->an_mutex);
++ INIT_WORK(&priv->an_irq_work, amd_xgbe_an_irq_work);
++ INIT_WORK(&priv->an_work, amd_xgbe_an_state_machine);
++
++ if (!priv->adev || acpi_disabled) {
++ struct device_node *bus_node;
++ struct device_node *phy_node;
++
++ bus_node = priv->dev->of_node;
++ phy_node = of_parse_phandle(bus_node, "phy-handle", 0);
++ if (!phy_node) {
++ dev_err(dev, "unable to parse phy-handle\n");
++ ret = -EINVAL;
++ goto err_priv;
++ }
++
++ phy_pdev = of_find_device_by_node(phy_node);
++ of_node_put(phy_node);
++
++ if (!phy_pdev) {
++ dev_err(dev, "unable to obtain phy device\n");
++ ret = -EINVAL;
++ goto err_priv;
++ }
++
++ phy_resnum = 0;
++ phy_irqnum = 0;
++ } else {
++ /* In ACPI, the XGBE and PHY resources are the grouped
++ * together with the PHY resources at the end
++ */
++ phy_pdev = priv->pdev;
++ phy_resnum = amd_xgbe_phy_resource_count(phy_pdev,
++ IORESOURCE_MEM) - 2;
++ phy_irqnum = amd_xgbe_phy_resource_count(phy_pdev,
++ IORESOURCE_IRQ) - 1;
++ }
++ phy_dev = &phy_pdev->dev;
++
++ /* Get the device mmio areas */
++ priv->rxtx_res = platform_get_resource(phy_pdev, IORESOURCE_MEM,
++ phy_resnum++);
++ priv->rxtx_regs = devm_ioremap_resource(dev, priv->rxtx_res);
++ if (IS_ERR(priv->rxtx_regs)) {
++ dev_err(dev, "rxtx ioremap failed\n");
++ ret = PTR_ERR(priv->rxtx_regs);
++ goto err_put;
++ }
++
++ /* All xgbe phy devices share the CMU registers so retrieve
++ * the resource and do the ioremap directly rather than
++ * the devm_ioremap_resource call
++ */
++ priv->cmu_res = platform_get_resource(phy_pdev, IORESOURCE_MEM,
++ phy_resnum++);
++ if (!priv->cmu_res) {
++ dev_err(dev, "cmu invalid resource\n");
++ ret = -EINVAL;
++ goto err_rxtx;
++ }
++ priv->cmu_regs = devm_ioremap_nocache(dev, priv->cmu_res->start,
++ resource_size(priv->cmu_res));
++ if (!priv->cmu_regs) {
++ dev_err(dev, "cmu ioremap failed\n");
++ ret = -ENOMEM;
++ goto err_rxtx;
++ }
++
++ /* Get the auto-negotiation interrupt */
++ ret = platform_get_irq(phy_pdev, phy_irqnum);
++ if (ret < 0) {
++ dev_err(dev, "platform_get_irq failed\n");
++ goto err_cmu;
++ }
++ if (priv->adev && !acpi_disabled && !phy_irqnum) {
++ struct irq_data *d = irq_get_irq_data(ret);
++ if (!d) {
++ dev_err(dev, "unable to set AN interrupt\n");
++ ret = -EINVAL;
++ goto err_cmu;
++ }
++
++#ifdef CONFIG_ACPI
++ ret = acpi_register_gsi(dev, d->hwirq - 2,
++ ACPI_LEVEL_SENSITIVE, ACPI_ACTIVE_HIGH);
++#else
++ ret = -EINVAL;
++#endif
++ if (ret < 0) {
++ dev_err(dev, "unable to set AN interrupt\n");
++ goto err_cmu;
++ }
++ }
++ priv->an_irq = ret;
++
++ /* Get the device serdes channel property */
++ ret = device_property_read_u32(phy_dev, XGBE_PHY_CHANNEL_PROPERTY,
++ &priv->serdes_channel);
++ if (ret) {
++ dev_err(dev, "invalid %s property\n",
++ XGBE_PHY_CHANNEL_PROPERTY);
++ goto err_cmu;
++ }
++
++ /* Get the device speed set property */
++ ret = device_property_read_u32(phy_dev, XGBE_PHY_SPEEDSET_PROPERTY,
++ &priv->speed_set);
++ if (ret) {
++ dev_err(dev, "invalid %s property\n",
++ XGBE_PHY_SPEEDSET_PROPERTY);
++ goto err_cmu;
++ }
++
++ switch (priv->speed_set) {
++ case AMD_XGBE_PHY_SPEEDSET_1000_10000:
++ case AMD_XGBE_PHY_SPEEDSET_2500_10000:
++ break;
++ default:
++ dev_err(dev, "invalid %s property\n",
++ XGBE_PHY_SPEEDSET_PROPERTY);
++ ret = -EINVAL;
++ goto err_cmu;
++ }
++
++ if (device_property_present(phy_dev, XGBE_PHY_BLWC_PROPERTY)) {
++ ret = device_property_read_u32_array(phy_dev,
++ XGBE_PHY_BLWC_PROPERTY,
++ priv->serdes_blwc,
++ XGBE_PHY_SPEEDS);
++ if (ret) {
++ dev_err(dev, "invalid %s property\n",
++ XGBE_PHY_BLWC_PROPERTY);
++ goto err_cmu;
++ }
++ } else {
++ memcpy(priv->serdes_blwc, amd_xgbe_phy_serdes_blwc,
++ sizeof(priv->serdes_blwc));
++ }
++
++ if (device_property_present(phy_dev, XGBE_PHY_CDR_RATE_PROPERTY)) {
++ ret = device_property_read_u32_array(phy_dev,
++ XGBE_PHY_CDR_RATE_PROPERTY,
++ priv->serdes_cdr_rate,
++ XGBE_PHY_SPEEDS);
++ if (ret) {
++ dev_err(dev, "invalid %s property\n",
++ XGBE_PHY_CDR_RATE_PROPERTY);
++ goto err_cmu;
++ }
++ } else {
++ memcpy(priv->serdes_cdr_rate, amd_xgbe_phy_serdes_cdr_rate,
++ sizeof(priv->serdes_cdr_rate));
++ }
++
++ if (device_property_present(phy_dev, XGBE_PHY_PQ_SKEW_PROPERTY)) {
++ ret = device_property_read_u32_array(phy_dev,
++ XGBE_PHY_PQ_SKEW_PROPERTY,
++ priv->serdes_pq_skew,
++ XGBE_PHY_SPEEDS);
++ if (ret) {
++ dev_err(dev, "invalid %s property\n",
++ XGBE_PHY_PQ_SKEW_PROPERTY);
++ goto err_cmu;
++ }
++ } else {
++ memcpy(priv->serdes_pq_skew, amd_xgbe_phy_serdes_pq_skew,
++ sizeof(priv->serdes_pq_skew));
++ }
++
++ if (device_property_present(phy_dev, XGBE_PHY_TX_AMP_PROPERTY)) {
++ ret = device_property_read_u32_array(phy_dev,
++ XGBE_PHY_TX_AMP_PROPERTY,
++ priv->serdes_tx_amp,
++ XGBE_PHY_SPEEDS);
++ if (ret) {
++ dev_err(dev, "invalid %s property\n",
++ XGBE_PHY_TX_AMP_PROPERTY);
++ goto err_cmu;
++ }
++ } else {
++ memcpy(priv->serdes_tx_amp, amd_xgbe_phy_serdes_tx_amp,
++ sizeof(priv->serdes_tx_amp));
++ }
++
++ priv->link = 1;
++
++ phydev->priv = priv;
++
++ if (!priv->adev || acpi_disabled)
++ platform_device_put(phy_pdev);
++
++ return 0;
++
++err_cmu:
++ devm_iounmap(dev, priv->cmu_regs);
++
++err_rxtx:
++ devm_iounmap(dev, priv->rxtx_regs);
++ devm_release_mem_region(dev, priv->rxtx_res->start,
++ resource_size(priv->rxtx_res));
++
++err_put:
++ if (!priv->adev || acpi_disabled)
++ platform_device_put(phy_pdev);
++
++err_priv:
++ devm_kfree(dev, priv);
++
++ return ret;
++}
++
++static void amd_xgbe_phy_remove(struct phy_device *phydev)
++{
++ struct amd_xgbe_phy_priv *priv = phydev->priv;
++ struct device *dev = priv->dev;
++
++ if (priv->an_irq_allocated) {
++ devm_free_irq(dev, priv->an_irq, priv);
++
++ flush_workqueue(priv->an_workqueue);
++ destroy_workqueue(priv->an_workqueue);
++ }
++
++ devm_iounmap(dev, priv->cmu_regs);
++
++ devm_iounmap(dev, priv->rxtx_regs);
++ devm_release_mem_region(dev, priv->rxtx_res->start,
++ resource_size(priv->rxtx_res));
++
++ devm_kfree(dev, priv);
++}
++
++static int amd_xgbe_match_phy_device(struct phy_device *phydev)
++{
++ return phydev->c45_ids.device_ids[MDIO_MMD_PCS] == XGBE_PHY_ID;
++}
++
++static struct phy_driver amd_xgbe_phy_a0_driver[] = {
++ {
++ .phy_id = XGBE_PHY_ID,
++ .phy_id_mask = XGBE_PHY_MASK,
++ .name = "AMD XGBE PHY A0",
++ .features = 0,
++ .probe = amd_xgbe_phy_probe,
++ .remove = amd_xgbe_phy_remove,
++ .soft_reset = amd_xgbe_phy_soft_reset,
++ .config_init = amd_xgbe_phy_config_init,
++ .suspend = amd_xgbe_phy_suspend,
++ .resume = amd_xgbe_phy_resume,
++ .config_aneg = amd_xgbe_phy_config_aneg,
++ .aneg_done = amd_xgbe_phy_aneg_done,
++ .read_status = amd_xgbe_phy_read_status,
++ .match_phy_device = amd_xgbe_match_phy_device,
++ .driver = {
++ .owner = THIS_MODULE,
++ },
++ },
++};
++
++module_phy_driver(amd_xgbe_phy_a0_driver);
++
++static struct mdio_device_id __maybe_unused amd_xgbe_phy_a0_ids[] = {
++ { XGBE_PHY_ID, XGBE_PHY_MASK },
++ { }
++};
++MODULE_DEVICE_TABLE(mdio, amd_xgbe_phy_a0_ids);
diff --git a/arm-dts-am335x-bone-common-setup-default-pinmux-http.patch b/arm-dts-am335x-bone-common-setup-default-pinmux-http.patch
index 7e50fce..2105fcb 100644
--- a/arm-dts-am335x-bone-common-setup-default-pinmux-http.patch
+++ b/arm-dts-am335x-bone-common-setup-default-pinmux-http.patch
@@ -5,14 +5,14 @@ Subject: [PATCH] arm: dts: am335x-bone-common: setup default pinmux
Signed-off-by: Robert Nelson <robertcnelson at gmail.com>
---
- arch/arm/boot/dts/am335x-bone-common.dtsi | 130 ++++++++++++++++++++++++++++++
- 1 file changed, 130 insertions(+)
+ arch/arm/boot/dts/am335x-bone-common.dtsi | 222 ++++++++++++++++++++++++++++++
+ 1 file changed, 222 insertions(+)
diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi
-index ec755eeb78ee..db880bf46135 100644
+index 1fd496fe1a68..9688dda39e7a 100644
--- a/arch/arm/boot/dts/am335x-bone-common.dtsi
+++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
-@@ -95,6 +95,13 @@
+@@ -95,6 +95,20 @@
>;
};
@@ -23,10 +23,17 @@ index ec755eeb78ee..db880bf46135 100644
+ >;
+ };
+
++ uart1_pins: pinmux_uart1_pins {
++ pinctrl-single,pins = <
++ 0x180 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
++ 0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
++ >;
++ };
++
clkout2_pin: pinmux_clkout2_pin {
pinctrl-single,pins = <
0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
-@@ -175,6 +182,33 @@
+@@ -175,6 +189,60 @@
0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
>;
};
@@ -57,10 +64,37 @@ index ec755eeb78ee..db880bf46135 100644
+ 0x164 0x0 /* P9_42 (ZCZ ball C18) | MODE 0 */
+ >;
+ };
++
++ spi0_pins: pinmux_spi0_pins {
++ pinctrl-single,pins = <
++ 0x150 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_sclk.spi0_sclk */
++ 0x154 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d0.spi0_d0 */
++ 0x158 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */
++ 0x15c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
++ >;
++ };
++
++ ehrpwm1_pin_p9_14: pinmux_ehrpwm1_pin_p9_14 {
++ pinctrl-single,pins = <
++ 0x048 0x6 /* P9_14 (ZCZ ball U14) | MODE 6 */
++ >;
++ };
++
++ ehrpwm1_pin_p9_16: pinmux_ehrpwm1_pin_p9_16 {
++ pinctrl-single,pins = <
++ 0x04c 0x6 /* P9_16 (ZCZ ball T14) | MODE 6 */
++ >;
++ };
++
++ ecap0_pin_p9_42: pinmux_ecap0_pin_p9_42 {
++ pinctrl-single,pins = <
++ 0x164 0x0 /* P9_42 (ZCZ ball C18) | MODE 0 */
++ >;
++ };
};
&uart0 {
-@@ -184,6 +218,13 @@
+@@ -184,6 +252,20 @@
status = "okay";
};
@@ -71,10 +105,17 @@ index ec755eeb78ee..db880bf46135 100644
+ status = "okay";
+};
+
++&uart1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&uart1_pins>;
++
++ status = "okay";
++};
++
&usb {
status = "okay";
};
-@@ -259,6 +300,56 @@
+@@ -259,6 +341,106 @@
};
};
@@ -128,13 +169,65 @@ index ec755eeb78ee..db880bf46135 100644
+ };
+};
+
++&epwmss0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&ecap0_pin_p9_42>;
++ status = "okay";
++
++ ecap at 48300100 {
++ status = "okay";
++ };
++};
++
++&epwmss1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <
++ &ehrpwm1_pin_p9_14
++ &ehrpwm1_pin_p9_16
++ >;
++
++ status = "okay";
++
++ ehrpwm at 48302200 {
++ status = "okay";
++ };
++};
++
++&spi0 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&spi0_pins>;
++ status = "okay";
++
++ spidev0: spi at 0 {
++ compatible = "spidev";
++ reg = <0>;
++ spi-max-frequency = <16000000>;
++ spi-cpha;
++ };
++
++ spidev1: spi at 1 {
++ compatible = "spidev";
++ reg = <1>;
++ spi-max-frequency = <16000000>;
++ };
++};
++
++&tscadc {
++ status = "okay";
++ adc {
++ ti,adc-channels = <4 5 6>;
++ };
++};
++
/include/ "tps65217.dtsi"
&tps {
-@@ -340,3 +431,42 @@
- cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
- cd-inverted;
- };
+@@ -347,4 +529,44 @@
+
+ &sham {
+ status = "okay";
++
++};
+
+/ {
+ ocp {
@@ -173,4 +266,4 @@ index ec755eeb78ee..db880bf46135 100644
+ status = "okay";
+ };
+ };
-+};
+ };
diff --git a/arm64-avoid-needing-console-to-enable-serial-console.patch b/arm64-avoid-needing-console-to-enable-serial-console.patch
new file mode 100644
index 0000000..13f5cb6
--- /dev/null
+++ b/arm64-avoid-needing-console-to-enable-serial-console.patch
@@ -0,0 +1,42 @@
+From: Mark Salter <msalter at redhat.com>
+Date: Wed, 25 Mar 2015 14:17:50 -0400
+Subject: [PATCH] arm64: avoid needing console= to enable serial console
+
+Tell kernel to prefer one of the serial ports for console on
+platforms currently supported (pl011 or 8250). console= on
+command line will override these assumed preferences. This is
+just a hack to get the behavior we want from DT provided by
+firmware.
+
+Signed-off-by: Mark Salter <msalter at redhat.com>
+---
+ arch/arm64/kernel/setup.c | 19 +++++++++++++++++++
+ 1 file changed, 19 insertions(+)
+
+diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
+index 781f4697dc26..164d618d988c 100644
+--- a/arch/arm64/kernel/setup.c
++++ b/arch/arm64/kernel/setup.c
+@@ -559,3 +559,22 @@ const struct seq_operations cpuinfo_op = {
+ .stop = c_stop,
+ .show = c_show
+ };
++
++/*
++ * Temporary hack to avoid need for console= on command line
++ */
++static int __init arm64_console_setup(void)
++{
++ /* Allow cmdline to override our assumed preferences */
++ if (console_set_on_cmdline)
++ return 0;
++
++ if (IS_ENABLED(CONFIG_SERIAL_AMBA_PL011))
++ add_preferred_console("ttyAMA", 0, "115200");
++
++ if (IS_ENABLED(CONFIG_SERIAL_8250))
++ add_preferred_console("ttyS", 0, "115200");
++
++ return 0;
++}
++early_initcall(arm64_console_setup);
diff --git a/blk-loop-avoid-too-many-pending-per-work-IO.patch b/blk-loop-avoid-too-many-pending-per-work-IO.patch
new file mode 100644
index 0000000..1016995
--- /dev/null
+++ b/blk-loop-avoid-too-many-pending-per-work-IO.patch
@@ -0,0 +1,169 @@
+Documentation/workqueue.txt:
+ If there is dependency among multiple work items used
+ during memory reclaim, they should be queued to separate
+ wq each with WQ_MEM_RECLAIM.
+
+Loop devices can be stacked, so we have to convert to per-device
+workqueue. One example is Fedora live CD.
+
+Fixes: b5dd2f6047ca108001328aac0e8588edd15f1778
+Cc: stable at vger.kernel.org (v4.0)
+Cc: Justin M. Forbes <jforbes at fedoraproject.org>
+Signed-off-by: Ming Lei <ming.lei at canonical.com>
+---
+ drivers/block/loop.c | 30 ++++++++++++++----------------
+ drivers/block/loop.h | 1 +
+ 2 files changed, 15 insertions(+), 16 deletions(-)
+
+diff --git a/drivers/block/loop.c b/drivers/block/loop.c
+index ae3fcb4..3dc1598 100644
+--- a/drivers/block/loop.c
++++ b/drivers/block/loop.c
+@@ -86,8 +86,6 @@ static DEFINE_MUTEX(loop_index_mutex);
+ static int max_part;
+ static int part_shift;
+
+-static struct workqueue_struct *loop_wq;
+-
+ /*
+ * Transfer functions
+ */
+@@ -725,6 +723,12 @@ static int loop_set_fd(struct loop_device *lo, fmode_t mode,
+ size = get_loop_size(lo, file);
+ if ((loff_t)(sector_t)size != size)
+ goto out_putf;
++ error = -ENOMEM;
++ lo->wq = alloc_workqueue("kloopd%d",
++ WQ_MEM_RECLAIM | WQ_HIGHPRI | WQ_UNBOUND, 0,
++ lo->lo_number);
++ if (!lo->wq)
++ goto out_putf;
+
+ error = 0;
+
+@@ -872,6 +876,8 @@ static int loop_clr_fd(struct loop_device *lo)
+ lo->lo_flags = 0;
+ if (!part_shift)
+ lo->lo_disk->flags |= GENHD_FL_NO_PART_SCAN;
++ destroy_workqueue(lo->wq);
++ lo->wq = NULL;
+ mutex_unlock(&lo->lo_ctl_mutex);
+ /*
+ * Need not hold lo_ctl_mutex to fput backing file.
+@@ -1425,9 +1431,13 @@ static int loop_queue_rq(struct blk_mq_hw_ctx *hctx,
+ const struct blk_mq_queue_data *bd)
+ {
+ struct loop_cmd *cmd = blk_mq_rq_to_pdu(bd->rq);
++ struct loop_device *lo = cmd->rq->q->queuedata;
+
+ blk_mq_start_request(bd->rq);
+
++ if (lo->lo_state != Lo_bound)
++ return -EIO;
++
+ if (cmd->rq->cmd_flags & REQ_WRITE) {
+ struct loop_device *lo = cmd->rq->q->queuedata;
+ bool need_sched = true;
+@@ -1441,9 +1451,9 @@ static int loop_queue_rq(struct blk_mq_hw_ctx *hctx,
+ spin_unlock_irq(&lo->lo_lock);
+
+ if (need_sched)
+- queue_work(loop_wq, &lo->write_work);
++ queue_work(lo->wq, &lo->write_work);
+ } else {
+- queue_work(loop_wq, &cmd->read_work);
++ queue_work(lo->wq, &cmd->read_work);
+ }
+
+ return BLK_MQ_RQ_QUEUE_OK;
+@@ -1455,9 +1465,6 @@ static void loop_handle_cmd(struct loop_cmd *cmd)
+ struct loop_device *lo = cmd->rq->q->queuedata;
+ int ret = -EIO;
+
+- if (lo->lo_state != Lo_bound)
+- goto failed;
+-
+ if (write && (lo->lo_flags & LO_FLAGS_READ_ONLY))
+ goto failed;
+
+@@ -1806,13 +1813,6 @@ static int __init loop_init(void)
+ goto misc_out;
+ }
+
+- loop_wq = alloc_workqueue("kloopd",
+- WQ_MEM_RECLAIM | WQ_HIGHPRI | WQ_UNBOUND, 0);
+- if (!loop_wq) {
+- err = -ENOMEM;
+- goto misc_out;
+- }
+-
+ blk_register_region(MKDEV(LOOP_MAJOR, 0), range,
+ THIS_MODULE, loop_probe, NULL, NULL);
+
+@@ -1850,8 +1850,6 @@ static void __exit loop_exit(void)
+ blk_unregister_region(MKDEV(LOOP_MAJOR, 0), range);
+ unregister_blkdev(LOOP_MAJOR, "loop");
+
+- destroy_workqueue(loop_wq);
+-
+ misc_deregister(&loop_misc);
+ }
+
+diff --git a/drivers/block/loop.h b/drivers/block/loop.h
+index 301c27f..49564ed 100644
+--- a/drivers/block/loop.h
++++ b/drivers/block/loop.h
+@@ -54,6 +54,7 @@ struct loop_device {
+ gfp_t old_gfp_mask;
+
+ spinlock_t lo_lock;
++ struct workqueue_struct *wq;
+ struct list_head write_cmd_head;
+ struct work_struct write_work;
+ bool write_started;
+--
+1.9.1
+If there are too many pending per work I/O, too many
+high priority work thread can be generated so that
+system performance can be effected.
+
+This patch limits the max_active parameter of workqueue as 16.
+
+This patch fixes Fedora 22 live booting performance
+regression when it is booted from squashfs over dm
+based on loop, and looks the following reasons are
+related with the problem:
+
+- not like other filesyststems(such as ext4), squashfs
+is a bit special, and I observed that increasing I/O jobs
+to access file in squashfs only improve I/O performance a
+little, but it can make big difference for ext4
+
+- nested loop: both squashfs.img and ext3fs.img are mounted
+as loop block, and ext3fs.img is inside the squashfs
+
+- during booting, lots of tasks may run concurrently
+
+Fixes: b5dd2f6047ca108001328aac0e8588edd15f1778
+Cc: stable at vger.kernel.org (v4.0)
+Cc: Justin M. Forbes <jforbes at fedoraproject.org>
+Signed-off-by: Ming Lei <ming.lei at canonical.com>
+---
+ drivers/block/loop.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/drivers/block/loop.c b/drivers/block/loop.c
+index 3dc1598..1bee523 100644
+--- a/drivers/block/loop.c
++++ b/drivers/block/loop.c
+@@ -725,7 +725,7 @@ static int loop_set_fd(struct loop_device *lo, fmode_t mode,
+ goto out_putf;
+ error = -ENOMEM;
+ lo->wq = alloc_workqueue("kloopd%d",
+- WQ_MEM_RECLAIM | WQ_HIGHPRI | WQ_UNBOUND, 0,
++ WQ_MEM_RECLAIM | WQ_HIGHPRI | WQ_UNBOUND, 16,
+ lo->lo_number);
+ if (!lo->wq)
+ goto out_putf;
+--
+1.9.1
diff --git a/config-arm-generic b/config-arm-generic
index c47b3e9..b457038 100644
--- a/config-arm-generic
+++ b/config-arm-generic
@@ -58,7 +58,6 @@ CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
CONFIG_SERIAL_8250_DW=y
CONFIG_SERIO_AMBAKMI=y
-CONFIG_OC_ETM=y
CONFIG_FB_ARMCLCD=y
# ARM VExpress
@@ -101,7 +100,6 @@ CONFIG_OF_RESERVED_MEM=y
CONFIG_OF_RESOLVE=y
CONFIG_PM_GENERIC_DOMAINS_OF=y
CONFIG_PATA_OF_PLATFORM=m
-# CONFIG_OF_SELFTEST is not set
CONFIG_SERIAL_OF_PLATFORM=y
CONFIG_THERMAL_OF=y
@@ -114,6 +112,33 @@ CONFIG_USB_OHCI_HCD_PLATFORM=m
CONFIG_USB_EHCI_HCD_PLATFORM=m
CONFIG_USB_XHCI_PLATFORM=m
+# MMC/SD
+CONFIG_MMC_SPI=m
+
+# Designware (used by numerous devices)
+CONFIG_MMC_DW=m
+CONFIG_MMC_DW_PLTFM=m
+CONFIG_MMC_DW_PCI=m
+CONFIG_SPI_DW_MMIO=m
+CONFIG_SPI_DW_PCI=m
+# CONFIG_MMC_DW_IDMAC is not set
+# CONFIG_MMC_DW_K3 is not set
+# CONFIG_MMC_QCOM_DML is not set
+CONFIG_USB_DWC2=m
+CONFIG_USB_DWC2_DUAL_ROLE=y
+CONFIG_USB_DWC2_PLATFORM=m
+CONFIG_USB_DWC2_PCI=m
+# CONFIG_USB_DWC2_DEBUG is not set
+# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
+CONFIG_USB_DWC3=m
+CONFIG_USB_DWC3_DUAL_ROLE=y
+CONFIG_USB_DWC3_PCI=m
+# CONFIG_USB_DWC3_DEBUG is not set
+# CONFIG_DWC3_HOST_USB3_LPM_ENABLE is not set
+CONFIG_DW_WATCHDOG=m
+CONFIG_PCIE_DW=y
+# CONFIG_MMC_DW_EXYNOS is not set
+
# External Connectors
CONFIG_EXTCON=m
CONFIG_EXTCON_GPIO=m
@@ -169,9 +194,6 @@ CONFIG_IIO_SYSFS_TRIGGER=m
# PHY framework
CONFIG_GENERIC_PHY=y
-# MFD
-CONFIG_MFD_CORE=m
-
CONFIG_SMC91X=m
CONFIG_SMC911X=m
@@ -282,3 +304,8 @@ CONFIG_CMA_AREAS=7
# CONFIG_BMP085_SPI is not set
# CONFIG_TI_DAC7512 is not set
# CONFIG_SPI_ROCKCHIP is not set
+
+# EDAC
+CONFIG_EDAC=y
+CONFIG_EDAC_MM_EDAC=m
+CONFIG_EDAC_LEGACY_SYSFS=y
diff --git a/config-arm64 b/config-arm64
index 1c48624..02dc10b 100644
--- a/config-arm64
+++ b/config-arm64
@@ -10,6 +10,10 @@ CONFIG_SCHED_SMT=y
CONFIG_ARCH_XGENE=y
CONFIG_ARCH_SEATTLE=y
# CONFIG_ARCH_THUNDER is not set
+# CONFIG_ARCH_EXYNOS7 is not set
+# CONFIG_ARCH_FSL_LS2085A is not set
+# CONFIG_ARCH_MEDIATEK is not set
+# CONFIG_ARCH_TEGRA is not set
# Erratum
CONFIG_ARM64_ERRATUM_826319=y
@@ -103,6 +107,7 @@ CONFIG_NET_XGENE=y
CONFIG_RTC_DRV_XGENE=m
CONFIG_HW_RANDOM_XGENE=m
CONFIG_GPIO_XGENE=y
+CONFIG_GPIO_XGENE_SB=m
# busted build for various reasons
# uses pci_* for some reason to allocate DMA buffers
@@ -141,8 +146,12 @@ CONFIG_AMD_XGBE=m
CONFIG_AMD_XGBE_PHY=m
# CONFIG_AMD_XGBE_DCB is not set
+CONFIG_NET_VENDOR_MELLANOX=y
+CONFIG_MLX4_EN=m
+CONFIG_MLX4_EN_DCB=y
+CONFIG_MLX4_EN_VXLAN=y
+
# CONFIG_IMX_THERMAL is not set
-# CONFIG_MMC_DW is not set
CONFIG_DMI=y
CONFIG_DMIID=y
@@ -153,3 +162,8 @@ CONFIG_SATA_AHCI_PLATFORM=y
# CONFIG_SND_SOC is not set
# CONFIG_PMIC_OPREGION is not set
+# CONFIG_DEBUG_RODATA is not set
+
+CONFIG_DEBUG_SECTION_MISMATCH=y
+
+CONFIG_EDAC_XGENE=y
diff --git a/config-armv7 b/config-armv7
index c59977a..41dc87c 100644
--- a/config-armv7
+++ b/config-armv7
@@ -41,6 +41,7 @@ CONFIG_RTC_DRV_S35390A=m
CONFIG_RTC_DRV_88PM80X=m
CONFIG_RTC_DRV_ISL12057=m
CONFIG_RTC_DRV_MV=m
+CONFIG_RTC_DRV_ARMADA38X=m
CONFIG_MVNETA=m
CONFIG_GPIO_MVEBU=y
CONFIG_MVEBU_CLK_CORE=y
@@ -63,6 +64,7 @@ CONFIG_USB_EHCI_HCD_ORION=m
CONFIG_MMC_SDHCI_PXAV3=m
CONFIG_MVPP2=m
CONFIG_COMMON_CLK_SI5351=m
+CONFIG_RTC_DRV_ARMADA38X=m
# CONFIG_CACHE_FEROCEON_L2 is not set
# CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH is not set
@@ -73,8 +75,6 @@ CONFIG_SOC_OMAP5=y
CONFIG_SOC_OMAP3430=y
CONFIG_SOC_TI81XX=y
# CONFIG_MACH_CM_T35 is not set
-# CONFIG_MACH_CM_T3517 is not set
-# CONFIG_MACH_CRANEBOARD is not set
# CONFIG_MACH_DEVKIT8000 is not set
# CONFIG_MACH_NOKIA_RX51 is not set
# CONFIG_MACH_OMAP_LDP is not set
@@ -98,9 +98,7 @@ CONFIG_OMAP_PACKAGE_CUS=y
CONFIG_OMAP2PLUS_MBOX=m
CONFIG_OMAP_MBOX_KFIFO_SIZE=256
-CONFIG_OMAP_DM_TIMER=y
-CONFIG_OMAP_PM_NOOP=y
-CONFIG_DMA_OMAP=y
+CONFIG_DMA_OMAP=m
CONFIG_OMAP_IOMMU=y
CONFIG_HWSPINLOCK_OMAP=m
# CONFIG_OMAP3_SDRC_AC_TIMING is not set
@@ -114,6 +112,8 @@ CONFIG_GPIO_TWL6040=m
CONFIG_GPIO_PCF857X=m
CONFIG_I2C_OMAP=m
CONFIG_CHARGER_TWL4030=m
+CONFIG_CHARGER_ISP1704=m
+CONFIG_CHARGER_BQ2415X=m
CONFIG_OMAP_WATCHDOG=m
CONFIG_TWL4030_CORE=y
CONFIG_TWL4030_MADC=m
@@ -159,7 +159,6 @@ CONFIG_REGULATOR_PALMAS=y
CONFIG_REGULATOR_PBIAS=m
CONFIG_RTC_DRV_PALMAS=m
CONFIG_OMAP5_DSS_HDMI=y
-CONFIG_OMAP5_DSS_HDMI_AUDIO=y
CONFIG_COMMON_CLK_PALMAS=m
CONFIG_INPUT_PALMAS_PWRBUTTON=m
@@ -223,6 +222,7 @@ CONFIG_OMAP2_DSS_DSI=y
CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK=0
CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET=y
+CONFIG_DISPLAY_ENCODER_OPA362=m
CONFIG_DISPLAY_ENCODER_TFP410=m
CONFIG_DISPLAY_ENCODER_TPD12S015=m
CONFIG_DISPLAY_CONNECTOR_DVI=m
@@ -259,7 +259,10 @@ CONFIG_SND_OMAP_SOC_OMAP_TWL4030=m
CONFIG_SND_OMAP_SOC_OMAP3_PANDORA=m
CONFIG_SND_OMAP_SOC_RX51=m
CONFIG_SND_SOC_TLV320AIC23=m
+CONFIG_SND_SOC_TLV320AIC23_I2C=m
+CONFIG_SND_SOC_TLV320AIC23_SPI=m
CONFIG_SND_SOC_TLV320AIC3X=m
+CONFIG_SND_SOC_TLV320AIC31XX=m
CONFIG_SND_SOC_TPA6130A2=m
CONFIG_SND_SOC_TWL4030=m
CONFIG_SND_SOC_TWL6040=m
@@ -289,9 +292,11 @@ CONFIG_TI_DAVINCI_EMAC=m
CONFIG_TI_DAVINCI_MDIO=m
CONFIG_TI_CPSW=m
CONFIG_TI_CPSW_PHY_SEL=y
+CONFIG_TI_CPSW_ALE=m
CONFIG_TI_CPTS=y
# Builtin needed for BBone White
CONFIG_REGULATOR_TPS65217=y
+CONFIG_INPUT_TPS65218_PWRBUTTON=m
CONFIG_TI_EMIF=m
CONFIG_DRM_TILCDC=m
CONFIG_SPI_DAVINCI=m
@@ -308,6 +313,7 @@ CONFIG_TI_AM335X_ADC=m
CONFIG_PWM_TIPWMSS=y
CONFIG_MFD_TPS65218=m
CONFIG_REGULATOR_TPS65218=m
+CONFIG_VIDEO_AM437X_VPFE=m
# QCom
CONFIG_ARCH_MSM8X60=y
@@ -321,8 +327,11 @@ CONFIG_PINCTRL_APQ8084=m
CONFIG_PINCTRL_IPQ8064=m
CONFIG_PINCTRL_MSM8960=m
CONFIG_PINCTRL_MSM8X74=m
+CONFIG_PINCTRL_MSM8916=m
CONFIG_PINCTRL_QCOM_SPMI_PMIC=m
CONFIG_COMMON_CLK_QCOM=m
+# CONFIG_IPQ_LCC_806X is not set
+# CONFIG_MSM_LCC_8960 is not set
CONFIG_MFD_QCOM_RPM=m
CONFIG_MFD_PM8921_CORE=m
CONFIG_REGULATOR_QCOM_RPM=m
@@ -363,6 +372,7 @@ CONFIG_MFD_SPMI_PMIC=m
CONFIG_SPMI=m
CONFIG_SPMI_MSM_PMIC_ARB=m
CONFIG_QCOM_SPMI_IADC=m
+CONFIG_QCOM_SPMI_VADC=m
# i.MX
# CONFIG_MXC_DEBUG_BOARD is not set
@@ -628,6 +638,8 @@ CONFIG_USB_GADGET_XILINX=m
CONFIG_PCIE_XILINX=y
CONFIG_CADENCE_WATCHDOG=m
CONFIG_REGULATOR_ISL9305=m
+CONFIG_EDAC_SYNOPSYS=m
+CONFIG_PINCTRL_ZYNQ=y
# Multi function devices
CONFIG_MFD_88PM800=m
diff --git a/config-armv7-generic b/config-armv7-generic
index 0a930f3..f403e81 100644
--- a/config-armv7-generic
+++ b/config-armv7-generic
@@ -24,7 +24,6 @@ CONFIG_ARM_CPU_TOPOLOGY=y
CONFIG_ARM_DMA_MEM_BUFFERABLE=y
CONFIG_SWP_EMULATE=y
CONFIG_CACHE_L2X0=y
-CONFIG_CACHE_PL310=y
CONFIG_HIGHPTE=y
CONFIG_AUTO_ZRELADDR=y
CONFIG_ATAGS=y
@@ -34,6 +33,7 @@ CONFIG_ZBOOT_ROM_BSS=0x0
CONFIG_XZ_DEC_ARMTHUMB=y
CONFIG_ARCH_HAS_TICK_BROADCAST=y
CONFIG_IRQ_CROSSBAR=y
+CONFIG_IOMMU_IO_PGTABLE_LPAE=y
# CONFIG_MCPM is not set
# CONFIG_OABI_COMPAT is not set
@@ -71,6 +71,7 @@ CONFIG_ARCH_VIRT=y
# CONFIG_ARCH_U8500 is not set
# CONFIG_ARCH_VEXPRESS_SPC is not set
# CONFIG_ARCH_WM8850 is not set
+# CONFIG_ARCH_DIGICOLOR is not set
# errata
# v5/v6
@@ -127,6 +128,12 @@ CONFIG_THERMAL=y
CONFIG_CLOCK_THERMAL=y
CONFIG_CPUFREQ_DT=y
# CONFIG_ARM_BIG_LITTLE_CPUFREQ is not set
+CONFIG_PM_DEVFREQ=y
+CONFIG_PM_DEVFREQ_EVENT=y
+CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
+CONFIG_DEVFREQ_GOV_PERFORMANCE=y
+CONFIG_DEVFREQ_GOV_POWERSAVE=y
+CONFIG_DEVFREQ_GOV_USERSPACE=y
CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
CONFIG_LSM_MMAP_MIN_ADDR=32768
@@ -154,7 +161,6 @@ CONFIG_ARM_TIMER_SP804=y
CONFIG_SERIO_AMBAKMI=m
CONFIG_SERIAL_AMBA_PL010=y
CONFIG_SERIAL_AMBA_PL010_CONSOLE=y
-CONFIG_SERIAL_MRST_MAX3110=m
CONFIG_RTC_DRV_PL030=y
CONFIG_RTC_DRV_PL031=y
@@ -164,6 +170,7 @@ CONFIG_AMBA_PL08X=y
CONFIG_GPIO_PL061=y
CONFIG_PL320_MBOX=y
CONFIG_SND_ARMAACI=m
+CONFIG_USB_ISP1760=m
# highbank
CONFIG_EDAC_HIGHBANK_MC=m
@@ -172,7 +179,7 @@ CONFIG_SATA_HIGHBANK=m
CONFIG_ARM_HIGHBANK_CPUFREQ=m
# CONFIG_ARM_HIGHBANK_CPUIDLE is not set
-# Allwinner
+# AllWinner
# CONFIG_MACH_SUN4I is not set
# CONFIG_MACH_SUN5I is not set
CONFIG_MACH_SUN6I=y
@@ -192,7 +199,6 @@ CONFIG_SPI_SUN6I=m
CONFIG_MMC_SUNXI=m
CONFIG_I2C_SUN6I_P2WI=m
CONFIG_GPIO_PCA953X=m
-CONFIG_POWER_RESET_SUN6I=y
CONFIG_TOUCHSCREEN_SUN4I=m
CONFIG_MFD_AXP20X=y
CONFIG_REGULATOR_AXP20X=m
@@ -202,6 +208,9 @@ CONFIG_SUN4I_EMAC=m
CONFIG_RTC_DRV_SUN6I=m
CONFIG_AXP288_ADC=m
CONFIG_MTD_NAND_SUNXI=m
+CONFIG_SERIO_SUN4I_PS2=m
+CONFIG_KEYBOARD_SUN4I_LRADC=m
+CONFIG_PWM_SUN4I=m
# Exynos
CONFIG_ARCH_EXYNOS3=y
@@ -220,13 +229,15 @@ CONFIG_ARM_EXYNOS5250_CPUFREQ=y
CONFIG_ARM_EXYNOS5440_CPUFREQ=y
CONFIG_ARM_EXYNOS_CPU_FREQ_BOOST_SW=y
CONFIG_ARM_EXYNOS_CPUIDLE=y
+CONFIG_DEVFREQ_EVENT_EXYNOS_PPMU=y
+CONFIG_ARM_EXYNOS5_BUS_DEVFREQ=m
# CONFIG_EXYNOS5420_MCPM not set
+CONFIG_ARM_EXYNOS_CPUFREQ=m
CONFIG_I2C_EXYNOS5=m
CONFIG_I2C_S3C2410=m
CONFIG_SPI_S3C64XX=m
CONFIG_EXYNOS_THERMAL=m
-CONFIG_EXYNOS_THERMAL_CORE=y
CONFIG_EXYNOS_ADC=m
CONFIG_MMC_SDHCI_S3C=m
CONFIG_MMC_SDHCI_S3C_DMA=y
@@ -256,12 +267,12 @@ CONFIG_REGULATOR_WM8994=m
CONFIG_EXYNOS_VIDEO=y
CONFIG_EXYNOS_MIPI_DSI=y
CONFIG_DRM_EXYNOS=m
-CONFIG_DRM_EXYNOS_DMABUF=y
CONFIG_DRM_EXYNOS_DP=y
CONFIG_DRM_EXYNOS_DPI=y
CONFIG_DRM_EXYNOS_DSI=y
CONFIG_DRM_EXYNOS_FIMC=y
CONFIG_DRM_EXYNOS_FIMD=y
+CONFIG_DRM_EXYNOS7_DECON=y
CONFIG_DRM_EXYNOS_G2D=y
CONFIG_DRM_EXYNOS_GSC=y
CONFIG_DRM_EXYNOS_HDMI=y
@@ -294,7 +305,6 @@ CONFIG_SND_SOC_ODROIDX2=m
# CONFIG_EXYNOS_IOMMU_DEBUG is not set
# CONFIG_SAMSUNG_PM_DEBUG is not set
# CONFIG_SAMSUNG_PM_CHECK is not set
-# CONFIG_ARM_EXYNOS5_BUS_DEVFREQ is not set
# Arndale/Origen
CONFIG_MFD_MAX8997=y
@@ -333,6 +343,8 @@ CONFIG_SND_SOC_ROCKCHIP=m
CONFIG_SND_SOC_ROCKCHIP_I2S=m
CONFIG_ROCKCHIP_THERMAL=m
CONFIG_DRM_ROCKCHIP=m
+CONFIG_ROCKCHIP_DW_HDMI=m
+CONFIG_PHY_ROCKCHIP_USB=m
# Tegra
CONFIG_ARCH_TEGRA_114_SOC=y
@@ -340,7 +352,6 @@ CONFIG_ARCH_TEGRA_124_SOC=y
CONFIG_ARM_TEGRA_CPUFREQ=y
CONFIG_TRUSTED_FOUNDATIONS=y
CONFIG_SERIAL_TEGRA=y
-CONFIG_TEGRA30_MC=y
CONFIG_PCI_TEGRA=y
CONFIG_AHCI_TEGRA=m
CONFIG_TEGRA_IOMMU_SMMU=y
@@ -359,6 +370,7 @@ CONFIG_SND_SOC_TEGRA_MAX98090=m
CONFIG_SND_SOC_TEGRA_RT5640=m
CONFIG_SND_SOC_TEGRA30_AHUB=m
CONFIG_SND_SOC_TEGRA30_I2S=m
+CONFIG_SND_SOC_TEGRA_RT5677=m
CONFIG_SND_HDA_TEGRA=m
CONFIG_TEGRA_HOST1X=m
CONFIG_TEGRA_HOST1X_FIREWALL=y
@@ -366,12 +378,13 @@ CONFIG_DRM_TEGRA=m
CONFIG_DRM_TEGRA_FBDEV=y
# CONFIG_DRM_TEGRA_DEBUG is not set
CONFIG_DRM_TEGRA_STAGING=y
-CONFIG_NOUVEAU_PLATFORM_DRIVER=m
+CONFIG_NOUVEAU_PLATFORM_DRIVER=y
CONFIG_AD525X_DPOT=m
CONFIG_AD525X_DPOT_I2C=m
CONFIG_AD525X_DPOT_SPI=m
CONFIG_TEGRA_SOCTHERM=m
CONFIG_TEGRA_MC=y
+CONFIG_ARM_TEGRA_DEVFREQ=m
# Jetson TK1
CONFIG_PINCTRL_AS3722=y
@@ -390,10 +403,9 @@ CONFIG_DRM_PANEL_SIMPLE=m
CONFIG_DRM_PANEL_LD9040=m
CONFIG_DRM_PANEL_S6E8AA0=m
CONFIG_DRM_PANEL_SHARP_LQ101R1SX01=m
+CONFIG_DRM_DW_HDMI=m
# regmap
-CONFIG_REGMAP=y
-CONFIG_REGMAP_I2C=m
CONFIG_REGMAP_SPI=m
CONFIG_REGMAP_SPMI=m
CONFIG_REGMAP_MMIO=m
@@ -410,12 +422,11 @@ CONFIG_USB_OTG=y
CONFIG_USB_GADGET=m
CONFIG_USB_GADGET_VBUS_DRAW=100
CONFIG_USB_GADGET_STORAGE_NUM_BUFFERS=2
-# Use PIO on musb as upstream doesn't support multiple DMA engines yet :-/
-CONFIG_MUSB_PIO_ONLY=y
-# CONFIG_USB_GADGET_XILINX is not set
CONFIG_USB_MUSB_HDRC=m
CONFIG_USB_MUSB_DUAL_ROLE=y
CONFIG_USB_MUSB_DSPS=m
+# Use PIO on musb as upstream doesn't support multiple DMA engines yet :-/
+CONFIG_MUSB_PIO_ONLY=y
# CONFIG_USB_MUSB_TUSB6010 is not set
# CONFIG_USB_MUSB_UX500 is not set
CONFIG_USB_GPIO_VBUS=m
@@ -435,6 +446,7 @@ CONFIG_USB_CONFIGFS_SERIAL=y
# CONFIG_USB_CONFIGFS_F_UAC2 is not set
# CONFIG_USB_CONFIGFS_F_MIDI is not set
# CONFIG_USB_CONFIGFS_F_HID is not set
+# CONFIG_USB_CONFIGFS_F_UVC is not set
# CONFIG_USB_GADGET_DEBUG is not set
# CONFIG_USB_GADGET_DEBUG_FILES is not set
@@ -549,11 +561,6 @@ CONFIG_CRYPTO_SHA512_ARM_NEON=m
CONFIG_TI_PRIV_EDMA=y
CONFIG_TI_EDMA=y
-# EDAC
-CONFIG_EDAC=y
-CONFIG_EDAC_MM_EDAC=m
-CONFIG_EDAC_LEGACY_SYSFS=y
-
# Watchdog
# Mailbox
@@ -588,32 +595,6 @@ CONFIG_MTD_ST_SPI_FSM=m
CONFIG_EEPROM_AT25=m
CONFIG_EEPROM_93XX46=m
-# MMC/SD
-CONFIG_MMC_SPI=m
-
-# Designware (used by numerous devices)
-CONFIG_MMC_DW=m
-CONFIG_MMC_DW_PLTFM=m
-CONFIG_MMC_DW_PCI=m
-CONFIG_SPI_DW_MMIO=m
-CONFIG_SPI_DW_PCI=m
-# CONFIG_MMC_DW_IDMAC is not set
-# CONFIG_MMC_DW_K3 is not set
-# CONFIG_MMC_QCOM_DML is not set
-CONFIG_USB_DWC2=m
-CONFIG_USB_DWC2_DUAL_ROLE=y
-CONFIG_USB_DWC2_PLATFORM=m
-CONFIG_USB_DWC2_PCI=m
-# CONFIG_USB_DWC2_DEBUG is not set
-# CONFIG_USB_DWC2_TRACK_MISSED_SOFS is not set
-CONFIG_USB_DWC3=m
-CONFIG_USB_DWC3_DUAL_ROLE=y
-CONFIG_USB_DWC3_PCI=m
-# CONFIG_USB_DWC3_DEBUG is not set
-# CONFIG_DWC3_HOST_USB3_LPM_ENABLE is not set
-CONFIG_DW_WATCHDOG=m
-CONFIG_PCIE_DW=y
-
# Sound
CONFIG_SND_ARM=y
CONFIG_SND_SOC_AC97_BUS=y
@@ -787,6 +768,9 @@ CONFIG_KEYBOARD_CROS_EC=m
CONFIG_I2C_CROS_EC_TUNNEL=m
CONFIG_SND_SOC_TS3A227E=m
+CONFIG_R8188EU=m
+# CONFIG_88EU_AP_MODE is not set
+
# Needs work/investigation
# CONFIG_ARM_KPROBES_TEST is not set
@@ -817,6 +801,7 @@ CONFIG_SND_SOC_TS3A227E=m
# CONFIG_SERIAL_IFX6X60 is not set
# CONFIG_SERIAL_BCM63XX is not set
# CONFIG_FB_XILINX is not set
+# CONFIG_USB_GADGET_XILINX is not set
# CONFIG_BRCMSTB_GISB_ARB is not set
# CONFIG_SUNGEM is not set
# CONFIG_FB_SAVAGE is not set
@@ -830,7 +815,6 @@ CONFIG_SND_SOC_TS3A227E=m
# CONFIG_MMC_TMIO is not set
# CONFIG_PINCTRL_IMX35 is not set
# CONFIG_DVB_USB_PCTV452E is not set
-# CONFIG_DWMAC_SOCFPGA is not set
# CONFIG_MFD_LP8788 is not set
# CONFIG_MFD_MAX77693 is not set
@@ -841,6 +825,11 @@ CONFIG_SND_SOC_TS3A227E=m
# CONFIG_MFD_AS3711 is not set
# CONFIG_PMIC_DA903X is not set
# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_INPUT_REGULATOR_HAPTIC is not set
+# CONFIG_INPUT_AXP20X_PEK is not set
+# CONFIG_POWER_RESET_BRCMSTB is not set
+# CONFIG_INPUT_TPS65218_PWRBUTTON is not set
+# CONFIG_CLK_QORIQ is not set
# Debug options. We need to deal with them at some point like x86
# CONFIG_DEBUG_USER is not set
diff --git a/config-armv7-lpae b/config-armv7-lpae
index c42b38c..87a209a 100644
--- a/config-armv7-lpae
+++ b/config-armv7-lpae
@@ -82,3 +82,4 @@ CONFIG_GPIO_SYSCON=m
# CONFIG_SND_SOC_TEGRA20_AC97 is not set
# CONFIG_SND_SOC_TEGRA20_DAS is not set
# CONFIG_SND_SOC_TEGRA20_SPDIF is not set
+# CONFIG_SND_SOC_TEGRA_RT5677 is not set
diff --git a/config-generic b/config-generic
index eb7287b..f0e5aa5 100644
--- a/config-generic
+++ b/config-generic
@@ -74,6 +74,7 @@ CONFIG_SLUB=y
CONFIG_SLUB_CPU_PARTIAL=y
# CONFIG_SLUB_STATS is not set
# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_KASAN is not set
# CONFIG_AD525X_DPOT is not set
@@ -147,9 +148,8 @@ CONFIG_MMC_REALTEK_USB=m
CONFIG_MMC_VUB300=m
CONFIG_MMC_TOSHIBA_PCI=m
# CONFIG_MMC_SPI is not set
-# CONFIG_MMC_SDHCI_PXAV2 is not set
-# CONFIG_MMC_SDHCI_PXAV3 is not set
# CONFIG_MMC_SDHCI_OF_ARASAN is not set
+# CONFIG_MMC_SDHCI_F_SDH30 is not set
# CONFIG_MMC_USDHI6ROL0 is not set
@@ -201,6 +201,7 @@ CONFIG_BINFMT_MISC=m
#
# CONFIG_COMMON_CLK_SI5351 is not set
+# CONFIG_COMMON_CLK_CDCE706 is not set
#
# Generic Driver Options
@@ -214,6 +215,9 @@ CONFIG_EXTRA_FIRMWARE=""
# CONFIG_FW_LOADER_USER_HELPER is not set
# CONFIG_FW_LOADER_USER_HELPER_FALLBACK is not set
+CONFIG_REGMAP=y
+CONFIG_REGMAP_I2C=m
+
# CONFIG_CMA is not set
# CONFIG_DMA_CMA is not set
# CONFIG_FENCE_TRACE is not set
@@ -306,6 +310,7 @@ CONFIG_MTD_CFI_I2=y
# CONFIG_MTD_ONENAND is not set
# CONFIG_MTD_NAND_ECC_BCH is not set
# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_HISI504 is not set
# CONFIG_MTD_LPDDR is not set
CONFIG_MTD_UBI=m
CONFIG_MTD_UBI_WL_THRESHOLD=4096
@@ -380,6 +385,7 @@ CONFIG_BLK_DEV_THROTTLING=y
CONFIG_SCSI_VIRTIO=m
CONFIG_VIRTIO_BLK=m
CONFIG_VIRTIO_PCI=m
+CONFIG_VIRTIO_PCI_LEGACY=y
CONFIG_VIRTIO_BALLOON=m
CONFIG_VIRTIO_MMIO=m
# CONFIG_VIRTIO_MMIO_CMDLINE_DEVICES is not set
@@ -529,7 +535,6 @@ CONFIG_SCSI_DC395x=m
# CONFIG_SCSI_NSP32 is not set
CONFIG_SCSI_WD719X=m
CONFIG_SCSI_DEBUG=m
-CONFIG_SCSI_DC390T=m
CONFIG_SCSI_QLA_FC=m
CONFIG_TCM_QLA2XXX=m
CONFIG_SCSI_QLA_ISCSI=m
@@ -1143,7 +1148,6 @@ CONFIG_IP_DCCP_CCID3=y
# TIPC Configuration (EXPERIMENTAL)
#
CONFIG_TIPC=m
-CONFIG_TIPC_PORTS=8192
# CONFIG_TIPC_MEDIA_IB is not set
CONFIG_NETLABEL=y
@@ -1212,6 +1216,8 @@ CONFIG_NET_ACT_POLICE=m
CONFIG_NET_ACT_SIMP=m
CONFIG_NET_ACT_SKBEDIT=m
CONFIG_NET_ACT_VLAN=m
+CONFIG_NET_ACT_BPF=m
+CONFIG_NET_ACT_CONNMARK=m
CONFIG_DCB=y
CONFIG_DNS_RESOLVER=m
@@ -1421,6 +1427,7 @@ CONFIG_IXGBEVF=m
CONFIG_IXGBE=m
CONFIG_IXGBE_DCA=y
CONFIG_IXGBE_DCB=y
+CONFIG_IXGBE_VXLAN=y
CONFIG_IXGBE_HWMON=y
CONFIG_I40E=m
CONFIG_I40E_VXLAN=y
@@ -1521,8 +1528,6 @@ CONFIG_NET_VENDOR_STMICRO=y
CONFIG_STMMAC_ETH=m
# CONFIG_STMMAC_PLATFORM is not set
# CONFIG_STMMAC_PCI is not set
-# CONFIG_STMMAC_DA is not set
-# CONFIG_STMMAC_DEBUG_FS is not set
CONFIG_NET_VENDOR_SUN=y
CONFIG_HAPPYMEAL=m
@@ -1535,6 +1540,7 @@ CONFIG_TEHUTI=m
CONFIG_NET_VENDOR_TI=y
CONFIG_TLAN=m
+# CONFIG_TI_CPSW_ALE is not set
CONFIG_NET_VENDOR_VIA=y
CONFIG_VIA_RHINE=m
@@ -1840,6 +1846,7 @@ CONFIG_MWIFIEX_PCIE=m
CONFIG_MWIFIEX_USB=m
CONFIG_IEEE802154=m
+CONFIG_IEEE802154_SOCKET=m
CONFIG_IEEE802154_6LOWPAN=m
CONFIG_IEEE802154_DRIVERS=m
CONFIG_IEEE802154_FAKELB=m
@@ -1964,6 +1971,7 @@ CONFIG_BT=m
CONFIG_BT_BREDR=y
CONFIG_BT_LE=y
CONFIG_BT_6LOWPAN=m
+# CONFIG_BT_SELFTEST is not set
CONFIG_BT_SCO=y
CONFIG_BT_CMTP=m
CONFIG_BT_RFCOMM=m
@@ -2309,6 +2317,7 @@ CONFIG_TOUCHSCREEN_ZFORCE=m
# CONFIG_TOUCHSCREEN_AR1021_I2C is not set
CONFIG_INPUT_MISC=y
+CONFIG_INPUT_E3X0_BUTTON=m
CONFIG_INPUT_PCSPKR=m
CONFIG_INPUT_RETU_PWRBUTTON=m
CONFIG_INPUT_UINPUT=m
@@ -2357,7 +2366,7 @@ CONFIG_TCG_TIS=m
CONFIG_TCG_NSC=m
CONFIG_TCG_ATMEL=m
# CONFIG_TCG_INFINEON is not set
-# CONFIG_TCG_ST33_I2C is not set
+# CONFIG_TCG_TIS_I2C_ST33 is not set
# CONFIG_TCG_XEN is not set
CONFIG_TELCLOCK=m
@@ -2402,6 +2411,7 @@ CONFIG_SERIAL_ARC=m
CONFIG_SERIAL_ARC_NR_PORTS=1
# CONFIG_SERIAL_RP2 is not set
# CONFIG_SERIAL_FSL_LPUART is not set
+# CONFIG_SERIAL_CONEXANT_DIGICOLOR is not set
# CONFIG_SERIAL_ST_ASC is not set
# CONFIG_SERIAL_PCH_UART is not set
# CONFIG_SERIAL_MAX3100 is not set
@@ -2664,6 +2674,7 @@ CONFIG_IIO_INTERRUPT_TRIGGER=m
CONFIG_HID_SENSOR_IIO_COMMON=m
CONFIG_HID_SENSOR_IIO_TRIGGER=m
# CONFIG_IIO_SYSFS_TRIGGER is not set
+# CONFIG_IIO_SSP_SENSORHUB is not set
# CONFIG_AD5446 is not set
# CONFIG_AD5380 is not set
# CONFIG_AD5064 is not set
@@ -2675,7 +2686,8 @@ CONFIG_HID_SENSOR_IIO_TRIGGER=m
# CONFIG_MCP4725 is not set
# CONFIG_ITG3200 is not set
# CONFIG_APDS9300 is not set
-# CONFIG_CM32181 is not set
+CONFIG_CM32181=m
+# CONFIG_CM3232 is not set
# CONFIG_CM36651 is not set
# CONFIG_GP2AP020A00F is not set
# CONFIG_TSL2583 is not set
@@ -2688,6 +2700,7 @@ CONFIG_HID_SENSOR_IIO_TRIGGER=m
# CONFIG_TI_ADC128S052 is not set
# CONFIG_VIPERBOARD_ADC is not set
# CONFIG_VF610_ADC is not set
+# CONFIG_CC10001_ADC is not set
# CONFIG_INV_MPU6050_IIO is not set
CONFIG_IIO_ST_GYRO_3AXIS=m
CONFIG_IIO_ST_MAGN_3AXIS=m
@@ -2708,6 +2721,8 @@ CONFIG_HID_SENSOR_DEVICE_ROTATION=m
# CONFIG_IIO_ST_PRESS is not set
# CONFIG_KXSD9 is not set
# CONFIG_MMA8452 is not set
+# CONFIG_MMA9551 is not set
+# CONFIG_MMA9553 is not set
# CONFIG_AD7266 is not set
# CONFIG_AD7298 is not set
# CONFIG_AD7476 is not set
@@ -2734,6 +2749,7 @@ CONFIG_HID_SENSOR_DEVICE_ROTATION=m
# CONFIG_ADIS16130 is not set
# CONFIG_ADIS16136 is not set
# CONFIG_ADIS16260 is not set
+# CONFIG_KMX61 is not set
# CONFIG_ADXRS450 is not set
# CONFIG_BMG160 is not set
# CONFIG_ADIS16400 is not set
@@ -2744,8 +2760,10 @@ CONFIG_HID_SENSOR_DEVICE_ROTATION=m
# CONFIG_SI7005 is not set
# CONFIG_SI7020 is not set
# CONFIG_AS3935 is not set
+# CONFIG_SX9500 is not set
CONFIG_KXCJK1013=m
# CONFIG_ISL29125 is not set
+# CONFIG_JSA1212 is not set
# CONFIG_TCS3414 is not set
# CONFIG_AK09911 is not set
# CONFIG_T5403 is not set
@@ -2904,6 +2922,9 @@ CONFIG_RTC_DRV_CMOS=y
CONFIG_RTC_DRV_DS1307=m
CONFIG_RTC_DRV_DS1511=m
CONFIG_RTC_DRV_DS1553=m
+CONFIG_RTC_DRV_DS1685_FAMILY=m
+# CONFIG_RTC_DS1685_PROC_REGS is not set
+CONFIG_RTC_DS1685_SYSFS_REGS=y
CONFIG_RTC_DRV_DS1672=m
CONFIG_RTC_DRV_DS1742=m
CONFIG_RTC_DRV_DS1374=m
@@ -2964,6 +2985,7 @@ CONFIG_RTC_DRV_PCF85063=m
# CONFIG_RTC_DRV_MOXART is not set
# CONFIG_RTC_DRV_ISL12057 is not set
# CONFIG_RTC_DRV_XGENE is not set
+# CONFIG_RTC_DRV_ABB5ZES3 is not set
CONFIG_R3964=m
# CONFIG_APPLICOM is not set
@@ -3020,6 +3042,9 @@ CONFIG_DRM_VMWGFX_FBCON=y
CONFIG_DRM_QXL=m
CONFIG_DRM_BOCHS=m
CONFIG_DRM_PTN3460=m
+# CONFIG_DRM_PANEL is not set
+# CONFIG_DRM_PANEL_SIMPLE is not set
+# CONFIG_DRM_PANEL_S6E8AA0 is not set
#
# PCMCIA character devices
@@ -3050,7 +3075,6 @@ CONFIG_MEDIA_CONTROLLER=y
CONFIG_VIDEO_DEV=m
# CONFIG_VIDEO_ADV_DEBUG is not set
CONFIG_VIDEO_V4L2=y
-# CONFIG_VIDEO_V4L2_INT_DEVICE is not set
CONFIG_VIDEO_V4L2_SUBDEV_API=y
# CONFIG_VIDEO_VIVI is not set
# CONFIG_USB_SI4713 is not set
@@ -3068,13 +3092,11 @@ CONFIG_VIDEO_V4L2_SUBDEV_API=y
CONFIG_VIDEO_AU0828=m
CONFIG_VIDEO_AU0828_V4L2=y
CONFIG_VIDEO_BT848=m
-CONFIG_VIDEO_BWQCAM=m
CONFIG_VIDEO_SR030PC30=m
CONFIG_VIDEO_NOON010PC30=m
CONFIG_VIDEO_CAFE_CCIC=m
# CONFIG_VIDEO_CPIA is not set
CONFIG_VIDEO_CPIA2=m
-CONFIG_VIDEO_CQCAM=m
CONFIG_VIDEO_CX23885=m
CONFIG_MEDIA_ALTERA_CI=m
CONFIG_VIDEO_CX18=m
@@ -3101,7 +3123,6 @@ CONFIG_VIDEO_IVTV=m
CONFIG_VIDEO_MEYE=m
CONFIG_VIDEO_MXB=m
CONFIG_VIDEO_PVRUSB2_DVB=y
-# CONFIG_VIDEO_PMS is not set
CONFIG_VIDEO_HDPVR=m
CONFIG_VIDEO_SAA6588=m
CONFIG_VIDEO_SAA7134=m
@@ -3113,7 +3134,6 @@ CONFIG_VIDEO_USBVISION=m
CONFIG_VIDEO_STK1160_COMMON=m
CONFIG_VIDEO_STK1160=m
CONFIG_VIDEO_STK1160_AC97=y
-CONFIG_VIDEO_W9966=m
CONFIG_VIDEO_ZORAN=m
CONFIG_VIDEO_ZORAN_AVS6EYES=m
CONFIG_VIDEO_ZORAN_BUZ=m
@@ -3128,7 +3148,6 @@ CONFIG_VIDEO_SAA7164=m
CONFIG_VIDEO_TM6000=m
CONFIG_VIDEO_TM6000_ALSA=m
CONFIG_VIDEO_TM6000_DVB=m
-CONFIG_VIDEO_TLG2300=m
# CONFIG_VIDEO_TIMBERDALE is not set
# CONFIG_VIDEO_M5MOLS is not set
# CONFIG_VIDEO_TW68 is not set
@@ -3252,7 +3271,6 @@ CONFIG_DVB_HOPPER=m
CONFIG_VIDEO_SAA7146=m
CONFIG_VIDEO_SAA7146_VV=m
CONFIG_VIDEO_TUNER=m
-CONFIG_VIDEO_BTCX=m
CONFIG_VIDEO_PVRUSB2=m
CONFIG_VIDEO_PVRUSB2_SYSFS=y
# CONFIG_VIDEO_PVRUSB2_DEBUGIFC is not set
@@ -3296,8 +3314,6 @@ CONFIG_V4L_MEM2MEM_DRIVERS=y
# CONFIG_VIDEO_RENESAS_VSP1 is not set
# CONFIG_V4L_TEST_DRIVERS is not set
-# CONFIG_VIDEO_MEM2MEM_TESTDEV is not set
-
#
# Broadcom Crystal HD video decoder driver
#
@@ -3389,6 +3405,8 @@ CONFIG_VGA_CONSOLE=y
CONFIG_VGACON_SOFT_SCROLLBACK=y
CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=64
CONFIG_DUMMY_CONSOLE=y
+CONFIG_DUMMY_CONSOLE_COLUMNS=80
+CONFIG_DUMMY_CONSOLE_ROWS=25
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
@@ -3550,6 +3568,10 @@ CONFIG_SND_USB_UA101=m
CONFIG_SND_USB_6FIRE=m
CONFIG_SND_USB_HIFACE=m
# CONFIG_SND_BCD2000 is not set
+CONFIG_SND_USB_POD=m
+CONFIG_SND_USB_PODHD=m
+CONFIG_SND_USB_TONEPORT=m
+CONFIG_SND_USB_VARIAX=m
#
# PCMCIA devices
@@ -3557,7 +3579,6 @@ CONFIG_SND_USB_HIFACE=m
# CONFIG_SND_PCMCIA is not set
CONFIG_SND_FIREWIRE=y
-CONFIG_SND_FIREWIRE_SPEAKERS=m
CONFIG_SND_ISIGHT=m
CONFIG_SND_SCS1X=m
CONFIG_SND_DICE=m
@@ -3598,7 +3619,7 @@ CONFIG_USB_EHCI_TT_NEWSCHED=y
# CONFIG_USB_EHCI_MV is not set
# CONFIG_USB_EHCI_HCD_PLATFORM is not set
# CONFIG_USB_ISP116X_HCD is not set
-# CONFIG_USB_ISP1760_HCD is not set
+# CONFIG_USB_ISP1760 is not set
CONFIG_USB_ISP1362_HCD=m
CONFIG_USB_FUSBH200_HCD=m
# CONFIG_USB_FOTG210_HCD is not set
@@ -3677,6 +3698,7 @@ CONFIG_HID_MULTITOUCH=m
CONFIG_HID_NTRIG=y
CONFIG_HID_PLANTRONICS=m
CONFIG_HID_PRIMAX=m
+CONFIG_HID_BETOP_FF=m
CONFIG_HID_PRODIKEYS=m
CONFIG_HID_DRAGONRISE=m
CONFIG_HID_GYRATION=m
@@ -3793,6 +3815,7 @@ CONFIG_USB_GSPCA_NW80X=m
CONFIG_USB_GSPCA_VICAM=m
CONFIG_USB_GSPCA_KINECT=m
CONFIG_USB_GSPCA_SE401=m
+CONFIG_USB_GSPCA_TOUPTEK=m
CONFIG_USB_S2255=m
# CONFIG_VIDEO_SH_MOBILE_CEU is not set
@@ -4023,6 +4046,8 @@ CONFIG_PCF50633_GPIO=m
CONFIG_INPUT_PCF50633_PMU=m
CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
+CONFIG_MFD_CORE=m
+
CONFIG_MFD_VX855=m
CONFIG_MFD_SM501=m
CONFIG_MFD_SM501_GPIO=y
@@ -4083,6 +4108,8 @@ CONFIG_MFD_VIPERBOARD=m
# CONFIG_MFD_HI6421_PMIC is not set
# CONFIG_MFD_RK808 is not set
# CONFIG_MFD_RN5T618 is not set
+# CONFIG_MFD_DA9150 is not set
+# CONFIG_MFD_RT5033 is not set
# CONFIG_EZX_PCAP is not set
# CONFIG_INTEL_SOC_PMIC is not set
@@ -4132,6 +4159,7 @@ CONFIG_AUTOFS4_FS=y
# CONFIG_EXOFS_FS is not set
# CONFIG_EXOFS_DEBUG is not set
CONFIG_NILFS2_FS=m
+# CONFIG_FS_DAX is not set
# CONFIG_LOGFS is not set
CONFIG_CEPH_FS=m
CONFIG_CEPH_FSCACHE=y
@@ -4228,6 +4256,7 @@ CONFIG_F2FS_FS_XATTR=y
CONFIG_F2FS_FS_POSIX_ACL=y
CONFIG_F2FS_FS_SECURITY=y
# CONFIG_F2FS_CHECK_FS is not set
+# CONFIG_F2FS_IO_TRACE is not set
#
# Network File Systems
@@ -4247,6 +4276,7 @@ CONFIG_NFSD=m
CONFIG_NFSD_V3=y
CONFIG_NFSD_V3_ACL=y
CONFIG_NFSD_V4=y
+CONFIG_NFSD_PNFS=y
CONFIG_NFSD_V4_SECURITY_LABEL=y
CONFIG_NFS_FSCACHE=y
# CONFIG_NFS_USE_LEGACY_DNS is not set
@@ -4465,7 +4495,6 @@ CONFIG_HWPOISON_INJECT=m
CONFIG_CROSS_MEMORY_ATTACH=y
# CONFIG_DEBUG_SECTION_MISMATCH is not set
# CONFIG_BACKTRACE_SELF_TEST is not set
-CONFIG_RESOURCE_COUNTERS=y
# CONFIG_COMPAT_BRK is not set
# CONFIG_DEBUG_VIRTUAL is not set
# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
@@ -4480,6 +4509,7 @@ CONFIG_KGDB_SERIAL_CONSOLE=y
CONFIG_KGDB_TESTS=y
CONFIG_KGDB_LOW_LEVEL_TRAP=y
# CONFIG_KGDB_TESTS_ON_BOOT is not set
+# CONFIG_GDB_SCRIPTS is not set
#
@@ -4502,7 +4532,8 @@ CONFIG_SECURITY_SELINUX_AVC_STATS=y
# CONFIG_SECURITY_SMACK is not set
# CONFIG_SECURITY_TOMOYO is not set
# CONFIG_SECURITY_APPARMOR is not set
-# CONFIG_SECURITY_YAMA is not set
+CONFIG_SECURITY_YAMA=y
+CONFIG_SECURITY_YAMA_STACKED=y
CONFIG_AUDIT=y
CONFIG_AUDITSYSCALL=y
# http://lists.fedoraproject.org/pipermail/kernel/2013-February/004125.html
@@ -4518,6 +4549,7 @@ CONFIG_CRYPTO=y
CONFIG_CRYPTO_FIPS=y
CONFIG_CRYPTO_USER_API_HASH=y
CONFIG_CRYPTO_USER_API_SKCIPHER=y
+CONFIG_CRYPTO_USER_API_RNG=y
CONFIG_CRYPTO_MANAGER=y
# Note, CONFIG_CRYPTO_MANAGER_DISABLE_TESTS needs to be unset, or FIPS will be disabled.
# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set
@@ -4622,14 +4654,11 @@ CONFIG_RD_XZ=y
CONFIG_RD_LZO=y
CONFIG_RD_LZ4=y
-CONFIG_INIT_FALLBACK=y
-
CONFIG_KEYS=y
CONFIG_PERSISTENT_KEYRINGS=y
CONFIG_BIG_KEYS=y
CONFIG_TRUSTED_KEYS=m
CONFIG_ENCRYPTED_KEYS=m
-CONFIG_KEYS_DEBUG_PROC_KEYS=y
CONFIG_CDROM_PKTCDVD=m
CONFIG_CDROM_PKTCDVD_BUFFERS=8
# CONFIG_CDROM_PKTCDVD_WCACHE is not set
@@ -4739,7 +4768,6 @@ CONFIG_PM_DEBUG=y
CONFIG_PM_TRACE=y
CONFIG_PM_TRACE_RTC=y
# CONFIG_PM_TEST_SUSPEND is not set
-CONFIG_PM_RUNTIME=y
# CONFIG_PM_OPP is not set
# CONFIG_PM_AUTOSLEEP is not set
# CONFIG_PM_WAKELOCKS is not set
@@ -4761,8 +4789,6 @@ CONFIG_CPU_FREQ_STAT_DETAILS=y
# CONFIG_MOUSE_ATIXL is not set
-# CONFIG_MEDIA_PARPORT_SUPPORT is not set
-
CONFIG_RADIO_ADAPTERS=y
CONFIG_RADIO_TEA5764=m
CONFIG_RADIO_SAA7706H=m
@@ -4867,6 +4893,8 @@ CONFIG_SND_SOC_GENERIC_DMAENGINE_PCM=y
# CONFIG_SND_SOC_TLV320AIC23_I2C is not set
# CONFIG_SND_SOC_TLV320AIC23_SPI is not set
# CONFIG_SND_SOC_TS3A227E is not set
+# CONFIG_SND_SOC_XTFPGA_I2S is not set
+# CONFIG_SND_SOC_STA32X is not set
CONFIG_BALLOON_COMPACTION=y
CONFIG_COMPACTION=y
@@ -4874,6 +4902,7 @@ CONFIG_MIGRATION=y
CONFIG_BOUNCE=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
+CONFIG_LEDS_CLASS_FLASH=m
# CONFIG_LEDS_LOCOMO is not set
# CONFIG_LEDS_NET48XX is not set
# CONFIG_LEDS_PCA9532 is not set
@@ -5004,6 +5033,8 @@ CONFIG_APM_POWER=m
CONFIG_POWER_RESET=y
# CONFIG_POWER_RESET_LTC2952 is not set
# CONFIG_POWER_RESET_SYSCON is not set
+# CONFIG_BATTERY_GAUGE_LTC2941 is not set
+# CONFIG_POWER_RESET_RESTART is not set
# CONFIG_PDA_POWER is not set
@@ -5028,7 +5059,6 @@ CONFIG_VFIO_PCI=m
# LIRC
CONFIG_LIRC_STAGING=y
CONFIG_LIRC_BT829=m
-CONFIG_LIRC_IGORPLUGUSB=m
CONFIG_LIRC_IMON=m
CONFIG_LIRC_ZILOG=m
CONFIG_LIRC_PARALLEL=m
@@ -5039,6 +5069,7 @@ CONFIG_LIRC_SIR=m
# CONFIG_SAMPLES is not set
+CONFIG_DEVMEM=y
# CONFIG_DEVKMEM is not set
CONFIG_NOZOMI=m
@@ -5053,7 +5084,6 @@ CONFIG_INPUT_GP2A=m
CONFIG_ENCLOSURE_SERVICES=m
CONFIG_IPWIRELESS=m
-# CONFIG_BLK_DEV_XIP is not set
CONFIG_MEMSTICK=m
# CONFIG_MEMSTICK_DEBUG is not set
# CONFIG_MEMSTICK_UNSAFE_RESUME is not set
@@ -5130,14 +5160,12 @@ CONFIG_STAGING_MEDIA=y
# CONFIG_FB_XGI is not set
# CONFIG_VIDEO_GO7007 is not set
# CONFIG_I2C_BCM2048 is not set
-# CONFIG_VIDEO_TCM825X is not set
# CONFIG_DT3155 is not set
# CONFIG_PRISM2_USB is not set
# CONFIG_ECHO is not set
CONFIG_USB_ATMEL=m
# CONFIG_COMEDI is not set
# CONFIG_PANEL is not set
-# CONFIG_LINE6_USB is not set
# CONFIG_VME_BUS is not set
# CONFIG_VT6656 is not set
# Larry Finger maintains these (rhbz 913753)
@@ -5156,11 +5184,9 @@ CONFIG_R8723AU=m # Jes Sorensen maintains this (rhbz 1100162)
# CONFIG_SOLO6X10 is not set
# CONFIG_LTE_GDM724X is not set
CONFIG_R8712U=m # Larry Finger maintains this (rhbz 699618)
-# CONFIG_BCM_WIMAX is not set
# CONFIG_FT1000 is not set
# CONFIG_SPEAKUP is not set
# CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4 is not set
-# CONFIG_TOUCHSCREEN_CLEARPAD_TM1217 is not set
CONFIG_ALTERA_STAPL=m
# CONFIG_DVB_CXD2099 is not set
# CONFIG_DVB_RTL2832_SDR is not set
@@ -5183,9 +5209,10 @@ CONFIG_USBIP_HOST=m
# CONFIG_UNISYSSPAR is not set
# CONFIG_MEDIA_TUNER_MSI001 is not set
# CONFIG_COMMON_CLK_XLNX_CLKWZRD is not set
-# CONFIG_VIDEO_SAA7191 is not set
# CONFIG_DVB_MN88472 is not set
# CONFIG_DVB_MN88473 is not set
+# CONFIG_FB_SM7XX is not set
+# CONFIG_FB_TFT is not set
# END OF STAGING
#
@@ -5219,8 +5246,11 @@ CONFIG_RCU_TORTURE_TEST=m
# CONFIG_RCU_CPU_STALL_INFO is not set
# CONFIG_TASKS_RCU is not set
# CONFIG_RCU_USER_QS is not set
+CONFIG_RCU_KTHREAD_PRIO=0
CONFIG_SPARSE_RCU_POINTER=y
+# CONFIG_LIVEPATCH is not set
+
CONFIG_KSM=y
CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
@@ -5251,6 +5281,7 @@ CONFIG_FRONTSWAP=y
CONFIG_ZSWAP=y
CONFIG_ZBUD=y
CONFIG_ZSMALLOC=y
+# CONFIG_ZSMALLOC_STAT is not set
# CONFIG_PGTABLE_MAPPING is not set
# CONFIG_MDIO_GPIO is not set
@@ -5298,6 +5329,7 @@ CONFIG_GPIO_VIPERBOARD=m
# CONFIG_GPIO_MAX7301 is not set
# CONFIG_GPIO_MC33880 is not set
# CONFIG_GPIO_MCP23S08 is not set
+# CONFIG_GPIO_XILINX is not set
# FIXME: Why?
@@ -5328,12 +5360,14 @@ CONFIG_HWSPINLOCK=m
CONFIG_PSTORE=y
CONFIG_PSTORE_RAM=m
# CONFIG_PSTORE_CONSOLE is not set
+# CONFIG_PSTORE_PMSG is not set
# CONFIG_PSTORE_FTRACE is not set
# CONFIG_TEST_LKM is not set
# CONFIG_TEST_USER_COPY is not set
# CONFIG_TEST_BPF is not set
# CONFIG_TEST_UDELAY is not set
+# CONFIG_TEST_HEXDUMP is not set
# CONFIG_TEST_RHASHTABLE is not set
# CONFIG_AVERAGE is not set
@@ -5354,8 +5388,11 @@ CONFIG_BCMA_DRIVER_GPIO=y
# CONFIG_GOOGLE_FIRMWARE is not set
# CONFIG_INTEL_MID_PTI is not set
CONFIG_IOMMU_SUPPORT=y
+# CONFIG_IOMMU_IO_PGTABLE_LPAE is not set
+# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set
# CONFIG_MAILBOX is not set
+# CONFIG_ALTERA_MBOX is not set
# CONFIG_RESET_CONTROLLER is not set
@@ -5375,10 +5412,12 @@ CONFIG_POWERCAP=y
# CONFIG_CPU_IDLE is not set
# CONFIG_ARM_ARCH_TIMER_EVTSTREAM is not set
+# CONFIG_ASM9260_TIMER is not set
# CONFIG_HMC_DRV is not set
# CONFIG_PM_DEVFREQ is not set
+# CONFIG_PM_DEVFREQ_EVENT is not set
# CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND is not set
# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set
# CONFIG_DEVFREQ_GOV_POWERSAVE is not set
@@ -5403,3 +5442,5 @@ CONFIG_POWERCAP=y
# set in x86-generic presently
# CONFIG_TOUCHSCREEN_GOODIX is not set
+
+CONFIG_PCI_ECAM=y
diff --git a/config-powerpc-generic b/config-powerpc-generic
index e3dbc6a..00aaace 100644
--- a/config-powerpc-generic
+++ b/config-powerpc-generic
@@ -76,7 +76,6 @@ CONFIG_MEMORY_HOTPLUG=y
# CONFIG_ATM_HORIZON is not set
# CONFIG_ATM_FIRESTREAM is not set
# CONFIG_ATM_AMBASSADOR is not set
-# CONFIG_SCSI_DC390T is not set
# CONFIG_SCSI_BUSLOGIC is not set
@@ -210,6 +209,10 @@ CONFIG_EXTRA_TARGETS=""
CONFIG_NET_VENDOR_IBM=y
+CONFIG_MLX4_EN=m
+CONFIG_MLX4_EN_DCB=y
+CONFIG_MLX4_EN_VXLAN=y
+
# CONFIG_SERIO_XILINX_XPS_PS2 is not set
# CONFIG_PPC_SMLPAR is not set
@@ -333,7 +336,7 @@ CONFIG_I2C_MPC=m
# CONFIG_CPU_IDLE is not set
# CONFIG_OF_UNITTEST is not set
-# CONFIG_OF_SELFTEST is not set
+# CONFIG_OF_OVERLAY is not set
# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set
# CONFIG_INPUT_GP2A is not set
# CONFIG_INPUT_GPIO_TILT_POLLED is not set
diff --git a/config-powerpc64 b/config-powerpc64
index 10bdd0b..e0eebe2 100644
--- a/config-powerpc64
+++ b/config-powerpc64
@@ -34,7 +34,6 @@ CONFIG_HVCS=m
CONFIG_HVC_CONSOLE=y
# CONFIG_HVC_OLD_HVSI is not set
CONFIG_HOTPLUG_PCI=y
-CONFIG_THERM_PM72=y
CONFIG_IBMVETH=m
CONFIG_SCSI_IBMVSCSI=m
# CONFIG_HOTPLUG_PCI_CPCI is not set
diff --git a/config-powerpc64p7 b/config-powerpc64p7
index 1c733eb..c3d9706 100644
--- a/config-powerpc64p7
+++ b/config-powerpc64p7
@@ -28,7 +28,6 @@ CONFIG_HVCS=m
CONFIG_HVC_CONSOLE=y
# CONFIG_HVC_OLD_HVSI is not set
CONFIG_HOTPLUG_PCI=y
-CONFIG_THERM_PM72=y
CONFIG_IBMVETH=m
CONFIG_SCSI_IBMVSCSI=m
# CONFIG_HOTPLUG_PCI_CPCI is not set
diff --git a/config-s390x b/config-s390x
index 5f35e49..829412f 100644
--- a/config-s390x
+++ b/config-s390x
@@ -206,6 +206,7 @@ CONFIG_VMCP=y
CONFIG_SCHED_MC=y
CONFIG_SCHED_BOOK=y
+CONFIG_SCHED_TOPOLOGY=y
# CONFIG_WARN_DYNAMIC_STACK is not set
@@ -301,6 +302,7 @@ CONFIG_HOTPLUG_PCI_S390=y
CONFIG_MLX4_EN=m
CONFIG_MLX4_EN_DCB=y
+CONFIG_MLX4_EN_VXLAN=y
CONFIG_INFINIBAND=m
CONFIG_INFINIBAND_USER_ACCESS=m
CONFIG_MLX4_INFINIBAND=m
diff --git a/config-x86-32-generic b/config-x86-32-generic
index bdf1b75..c2b2726 100644
--- a/config-x86-32-generic
+++ b/config-x86-32-generic
@@ -178,6 +178,7 @@ CONFIG_SERIAL_GRLIB_GAISLER_APBUART=m
# CONFIG_MMC_SDHCI_OF is not set
# CONFIG_X86_INTEL_MID is not set
+# CONFIG_X86_INTEL_QUARK is not set
CONFIG_MFD_CS5535=m
# CONFIG_MFD_SYSCON is not set
@@ -198,7 +199,7 @@ CONFIG_BACKLIGHT_PWM=m
# CONFIG_EDAC_SBRIDGE is not set
# CONFIG_OF_UNITTEST is not set
-# CONFIG_OF_SELFTEST is not set
+# CONFIG_OF_OVERLAY is not set
# CONFIG_TOUCHSCREEN_AUO_PIXCIR is not set
# CONFIG_INPUT_GP2A is not set
# CONFIG_INPUT_GPIO_TILT_POLLED is not set
@@ -217,3 +218,4 @@ CONFIG_BACKLIGHT_PWM=m
# CONFIG_PINCTRL_IPQ8064 is not set
# CONFIG_COMMON_CLK_SI570 is not set
# CONFIG_COMMON_CLK_QCOM is not set
+# CONFIG_DRM_PANEL_SHARP_LQ101R1SX01 is not set
diff --git a/config-x86-generic b/config-x86-generic
index a473db3..4889e21 100644
--- a/config-x86-generic
+++ b/config-x86-generic
@@ -40,7 +40,6 @@ CONFIG_X86_PM_TIMER=y
CONFIG_EFI=y
CONFIG_EFI_STUB=y
-# CONFIG_EFI_MIXED is not set
CONFIG_EFI_VARS=y
CONFIG_EFIVAR_FS=y
CONFIG_EFI_VARS_PSTORE=y
@@ -130,7 +129,6 @@ CONFIG_GENERIC_ISA_DMA=y
CONFIG_PCI_MMCONFIG=y
CONFIG_PCI_BIOS=y
-CONFIG_PCI_IOAPIC=y
CONFIG_HOTPLUG_PCI=y
CONFIG_HOTPLUG_PCI_COMPAQ=m
@@ -199,6 +197,7 @@ CONFIG_EDAC_IE31200=m
CONFIG_SCHED_MC=y
CONFIG_TCG_INFINEON=m
+CONFIG_TCG_CRB=m
CONFIG_HW_RANDOM_INTEL=m
CONFIG_HW_RANDOM_AMD=m
@@ -490,6 +489,9 @@ CONFIG_NFC_MICROREAD_MEI=m
# CONFIG_X86_GOLDFISH is not set
CONFIG_X86_INTEL_LPSS=y
+
+# CONFIG_X86_AMD_PLATFORM_DEVICE is not set
+
CONFIG_IOSF_MBI=m
# CONFIG_IOSF_MBI_DEBUG is not set
CONFIG_PWM_LPSS=m
@@ -511,6 +513,7 @@ CONFIG_SND_SOC_INTEL_BYT_RT5640_MACH=m
CONFIG_SND_SOC_INTEL_BYT_MAX98090_MACH=m
CONFIG_SND_SOC_INTEL_BYTCR_RT5640_MACH=m
CONFIG_SND_SOC_INTEL_CHT_BSW_RT5672_MACH=m
+CONFIG_SND_SOC_INTEL_CHT_BSW_RT5645_MACH=m
diff --git a/config-x86_64-generic b/config-x86_64-generic
index 3a2ef08..0289dcf 100644
--- a/config-x86_64-generic
+++ b/config-x86_64-generic
@@ -24,6 +24,9 @@ CONFIG_PHYSICAL_ALIGN=0x1000000
# https://lists.fedoraproject.org/pipermail/kernel/2013-December/004753.html
CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
+# enable the 32-bit entry point for Baytrail
+CONFIG_EFI_MIXED=y
+
CONFIG_IA32_EMULATION=y
# CONFIG_IA32_AOUT is not set
@@ -80,7 +83,6 @@ CONFIG_CRYPTO_TWOFISH_AVX_X86_64=m
CONFIG_CRYPTO_DES3_EDE_X86_64=m
# staging crypto
# CONFIG_CRYPTO_SKEIN is not set
-# CONFIG_CRYPTO_THREEFISH is not set
# CONFIG_I2C_ALI1535 is not set
# CONFIG_I2C_ALI1563 is not set
@@ -169,6 +171,7 @@ CONFIG_NTB_NETDEV=m
CONFIG_IP1000=m
CONFIG_MLX4_EN=m
CONFIG_MLX4_EN_DCB=y
+CONFIG_MLX4_EN_VXLAN=y
# CONFIG_MLX4_DEBUG is not set
CONFIG_SFC=m
CONFIG_SFC_MCDI_MON=y
diff --git a/drm-i915-Disable-verbose-state-checks.patch b/drm-i915-Disable-verbose-state-checks.patch
deleted file mode 100644
index 1f54790..0000000
--- a/drm-i915-Disable-verbose-state-checks.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From: Josh Boyer <jwboyer at fedoraproject.org>
-Date: Thu, 29 Jan 2015 14:03:17 -0500
-Subject: [PATCH] drm/i915: Disable verbose state checks
-
-For stable releases, we disable the verbose state checks in the i915 driver.
-They are mostly for development purposes and they fill the retrace server
-to the point of uselessness. We leave these enabled in rawhide kernels,
-where they are both more likely to get attention from upstream and more
-likely to be fixable.
-
-Signed-off-by: Josh Boyer <jwboyer at fedoraproject.org>
----
- drivers/gpu/drm/i915/i915_params.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
-index db07153b693f..c049fe3fbdff 100644
---- a/drivers/gpu/drm/i915/i915_params.c
-+++ b/drivers/gpu/drm/i915/i915_params.c
-@@ -51,7 +51,7 @@ struct i915_params i915 __read_mostly = {
- .disable_vtd_wa = 0,
- .use_mmio_flip = 0,
- .mmio_debug = 0,
-- .verbose_state_checks = 1,
-+ .verbose_state_checks = 0,
- };
-
- module_param_named(modeset, i915.modeset, int, 0400);
diff --git a/drm-i915-hush-check-crtc-state.patch b/drm-i915-hush-check-crtc-state.patch
index d4ee60f..7aef532 100644
--- a/drm-i915-hush-check-crtc-state.patch
+++ b/drm-i915-hush-check-crtc-state.patch
@@ -14,15 +14,15 @@ Upstream-status: http://lists.freedesktop.org/archives/intel-gfx/2013-November/0
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
-index 33d4d37fd614..6865ef2d3476 100644
+index f75173c20f47..1003782a38c4 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
-@@ -10873,7 +10873,7 @@ check_crtc_state(struct drm_device *dev)
+@@ -10917,7 +10917,7 @@ check_crtc_state(struct drm_device *dev)
if (active &&
- !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
+ !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
- I915_STATE_WARN(1, "pipe state doesn't match!\n");
+ DRM_DEBUG_KMS("pipe state doesn't match!\n");
intel_dump_pipe_config(crtc, &pipe_config,
"[hw state]");
- intel_dump_pipe_config(crtc, &crtc->config,
+ intel_dump_pipe_config(crtc, crtc->config,
diff --git a/drm-i915-tame-the-chattermouth-v2.patch b/drm-i915-tame-the-chattermouth-v2.patch
deleted file mode 100644
index 9b719e1..0000000
--- a/drm-i915-tame-the-chattermouth-v2.patch
+++ /dev/null
@@ -1,558 +0,0 @@
-From: Rob Clark <robdclark at gmail.com>
-Date: Mon, 15 Dec 2014 13:56:32 -0500
-Subject: [PATCH] drm/i915: tame the chattermouth (v2)
-
-Many distro's have mechanism in place to collect and automatically file
-bugs for failed WARN()s. And since i915 has a lot of hw state sanity
-checks which result in WARN(), it generates quite a lot of noise which
-is somewhat disconcerting to the end user.
-
-Separate out the internal hw-is-in-the-state-I-expected checks into
-I915_STATE_WARN()s and allow configuration via i915.verbose_checks module
-param about whether this will generate a full blown stacktrace or just
-DRM_ERROR(). The new moduleparam defaults to true, so by default there
-is no change in behavior. And even when disabled, you will still get
-an error message logged.
-
-v2: paint the macro names blue, clarify that the default behavior
- remains the same as before
-
-Signed-off-by: Rob Clark <robdclark at gmail.com>
-Acked-by: Jani Nikula <jani.nikula at intel.com>
-Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
----
- drivers/gpu/drm/i915/i915_drv.h | 30 ++++++++
- drivers/gpu/drm/i915/i915_params.c | 5 ++
- drivers/gpu/drm/i915/intel_display.c | 134 +++++++++++++++++------------------
- drivers/gpu/drm/i915/intel_dp.c | 4 +-
- 4 files changed, 104 insertions(+), 69 deletions(-)
-
-diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
-index 44a3c385eea2..757f000a1d14 100644
---- a/drivers/gpu/drm/i915/i915_drv.h
-+++ b/drivers/gpu/drm/i915/i915_drv.h
-@@ -60,6 +60,35 @@
- #undef WARN_ON
- #define WARN_ON(x) WARN(x, "WARN_ON(" #x ")")
-
-+/* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
-+ * WARN_ON()) for hw state sanity checks to check for unexpected conditions
-+ * which may not necessarily be a user visible problem. This will either
-+ * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
-+ * enable distros and users to tailor their preferred amount of i915 abrt
-+ * spam.
-+ */
-+#define I915_STATE_WARN(condition, format...) ({ \
-+ int __ret_warn_on = !!(condition); \
-+ if (unlikely(__ret_warn_on)) { \
-+ if (i915.verbose_state_checks) \
-+ __WARN_printf(format); \
-+ else \
-+ DRM_ERROR(format); \
-+ } \
-+ unlikely(__ret_warn_on); \
-+})
-+
-+#define I915_STATE_WARN_ON(condition) ({ \
-+ int __ret_warn_on = !!(condition); \
-+ if (unlikely(__ret_warn_on)) { \
-+ if (i915.verbose_state_checks) \
-+ __WARN_printf("WARN_ON(" #condition ")\n"); \
-+ else \
-+ DRM_ERROR("WARN_ON(" #condition ")\n"); \
-+ } \
-+ unlikely(__ret_warn_on); \
-+})
-+
- enum pipe {
- INVALID_PIPE = -1,
- PIPE_A = 0,
-@@ -2316,6 +2345,7 @@ struct i915_params {
- bool disable_vtd_wa;
- int use_mmio_flip;
- bool mmio_debug;
-+ bool verbose_state_checks;
- };
- extern struct i915_params i915 __read_mostly;
-
-diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
-index c91cb2033cc5..db07153b693f 100644
---- a/drivers/gpu/drm/i915/i915_params.c
-+++ b/drivers/gpu/drm/i915/i915_params.c
-@@ -51,6 +51,7 @@ struct i915_params i915 __read_mostly = {
- .disable_vtd_wa = 0,
- .use_mmio_flip = 0,
- .mmio_debug = 0,
-+ .verbose_state_checks = 1,
- };
-
- module_param_named(modeset, i915.modeset, int, 0400);
-@@ -173,3 +174,7 @@ module_param_named(mmio_debug, i915.mmio_debug, bool, 0600);
- MODULE_PARM_DESC(mmio_debug,
- "Enable the MMIO debug code (default: false). This may negatively "
- "affect performance.");
-+
-+module_param_named(verbose_state_checks, i915.verbose_state_checks, bool, 0600);
-+MODULE_PARM_DESC(verbose_state_checks,
-+ "Enable verbose logs (ie. WARN_ON()) in case of unexpected hw state conditions.");
-diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
-index 791b00e612d8..33d4d37fd614 100644
---- a/drivers/gpu/drm/i915/intel_display.c
-+++ b/drivers/gpu/drm/i915/intel_display.c
-@@ -1024,7 +1024,7 @@ void assert_pll(struct drm_i915_private *dev_priv,
- reg = DPLL(pipe);
- val = I915_READ(reg);
- cur_state = !!(val & DPLL_VCO_ENABLE);
-- WARN(cur_state != state,
-+ I915_STATE_WARN(cur_state != state,
- "PLL state assertion failure (expected %s, current %s)\n",
- state_string(state), state_string(cur_state));
- }
-@@ -1040,7 +1040,7 @@ static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
- mutex_unlock(&dev_priv->dpio_lock);
-
- cur_state = val & DSI_PLL_VCO_EN;
-- WARN(cur_state != state,
-+ I915_STATE_WARN(cur_state != state,
- "DSI PLL state assertion failure (expected %s, current %s)\n",
- state_string(state), state_string(cur_state));
- }
-@@ -1071,7 +1071,7 @@ void assert_shared_dpll(struct drm_i915_private *dev_priv,
- return;
-
- cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
-- WARN(cur_state != state,
-+ I915_STATE_WARN(cur_state != state,
- "%s assertion failure (expected %s, current %s)\n",
- pll->name, state_string(state), state_string(cur_state));
- }
-@@ -1095,7 +1095,7 @@ static void assert_fdi_tx(struct drm_i915_private *dev_priv,
- val = I915_READ(reg);
- cur_state = !!(val & FDI_TX_ENABLE);
- }
-- WARN(cur_state != state,
-+ I915_STATE_WARN(cur_state != state,
- "FDI TX state assertion failure (expected %s, current %s)\n",
- state_string(state), state_string(cur_state));
- }
-@@ -1112,7 +1112,7 @@ static void assert_fdi_rx(struct drm_i915_private *dev_priv,
- reg = FDI_RX_CTL(pipe);
- val = I915_READ(reg);
- cur_state = !!(val & FDI_RX_ENABLE);
-- WARN(cur_state != state,
-+ I915_STATE_WARN(cur_state != state,
- "FDI RX state assertion failure (expected %s, current %s)\n",
- state_string(state), state_string(cur_state));
- }
-@@ -1135,7 +1135,7 @@ static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
-
- reg = FDI_TX_CTL(pipe);
- val = I915_READ(reg);
-- WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
-+ I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
- }
-
- void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
-@@ -1148,7 +1148,7 @@ void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
- reg = FDI_RX_CTL(pipe);
- val = I915_READ(reg);
- cur_state = !!(val & FDI_RX_PLL_ENABLE);
-- WARN(cur_state != state,
-+ I915_STATE_WARN(cur_state != state,
- "FDI RX PLL assertion failure (expected %s, current %s)\n",
- state_string(state), state_string(cur_state));
- }
-@@ -1190,7 +1190,7 @@ void assert_panel_unlocked(struct drm_i915_private *dev_priv,
- ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
- locked = false;
-
-- WARN(panel_pipe == pipe && locked,
-+ I915_STATE_WARN(panel_pipe == pipe && locked,
- "panel assertion failure, pipe %c regs locked\n",
- pipe_name(pipe));
- }
-@@ -1206,7 +1206,7 @@ static void assert_cursor(struct drm_i915_private *dev_priv,
- else
- cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
-
-- WARN(cur_state != state,
-+ I915_STATE_WARN(cur_state != state,
- "cursor on pipe %c assertion failure (expected %s, current %s)\n",
- pipe_name(pipe), state_string(state), state_string(cur_state));
- }
-@@ -1236,7 +1236,7 @@ void assert_pipe(struct drm_i915_private *dev_priv,
- cur_state = !!(val & PIPECONF_ENABLE);
- }
-
-- WARN(cur_state != state,
-+ I915_STATE_WARN(cur_state != state,
- "pipe %c assertion failure (expected %s, current %s)\n",
- pipe_name(pipe), state_string(state), state_string(cur_state));
- }
-@@ -1251,7 +1251,7 @@ static void assert_plane(struct drm_i915_private *dev_priv,
- reg = DSPCNTR(plane);
- val = I915_READ(reg);
- cur_state = !!(val & DISPLAY_PLANE_ENABLE);
-- WARN(cur_state != state,
-+ I915_STATE_WARN(cur_state != state,
- "plane %c assertion failure (expected %s, current %s)\n",
- plane_name(plane), state_string(state), state_string(cur_state));
- }
-@@ -1271,7 +1271,7 @@ static void assert_planes_disabled(struct drm_i915_private *dev_priv,
- if (INTEL_INFO(dev)->gen >= 4) {
- reg = DSPCNTR(pipe);
- val = I915_READ(reg);
-- WARN(val & DISPLAY_PLANE_ENABLE,
-+ I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
- "plane %c assertion failure, should be disabled but not\n",
- plane_name(pipe));
- return;
-@@ -1283,7 +1283,7 @@ static void assert_planes_disabled(struct drm_i915_private *dev_priv,
- val = I915_READ(reg);
- cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
- DISPPLANE_SEL_PIPE_SHIFT;
-- WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
-+ I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
- "plane %c assertion failure, should be off on pipe %c but is still active\n",
- plane_name(i), pipe_name(pipe));
- }
-@@ -1299,7 +1299,7 @@ static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
- if (INTEL_INFO(dev)->gen >= 9) {
- for_each_sprite(pipe, sprite) {
- val = I915_READ(PLANE_CTL(pipe, sprite));
-- WARN(val & PLANE_CTL_ENABLE,
-+ I915_STATE_WARN(val & PLANE_CTL_ENABLE,
- "plane %d assertion failure, should be off on pipe %c but is still active\n",
- sprite, pipe_name(pipe));
- }
-@@ -1307,20 +1307,20 @@ static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
- for_each_sprite(pipe, sprite) {
- reg = SPCNTR(pipe, sprite);
- val = I915_READ(reg);
-- WARN(val & SP_ENABLE,
-+ I915_STATE_WARN(val & SP_ENABLE,
- "sprite %c assertion failure, should be off on pipe %c but is still active\n",
- sprite_name(pipe, sprite), pipe_name(pipe));
- }
- } else if (INTEL_INFO(dev)->gen >= 7) {
- reg = SPRCTL(pipe);
- val = I915_READ(reg);
-- WARN(val & SPRITE_ENABLE,
-+ I915_STATE_WARN(val & SPRITE_ENABLE,
- "sprite %c assertion failure, should be off on pipe %c but is still active\n",
- plane_name(pipe), pipe_name(pipe));
- } else if (INTEL_INFO(dev)->gen >= 5) {
- reg = DVSCNTR(pipe);
- val = I915_READ(reg);
-- WARN(val & DVS_ENABLE,
-+ I915_STATE_WARN(val & DVS_ENABLE,
- "sprite %c assertion failure, should be off on pipe %c but is still active\n",
- plane_name(pipe), pipe_name(pipe));
- }
-@@ -1328,7 +1328,7 @@ static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
-
- static void assert_vblank_disabled(struct drm_crtc *crtc)
- {
-- if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
-+ if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
- drm_crtc_vblank_put(crtc);
- }
-
-@@ -1337,12 +1337,12 @@ static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
- u32 val;
- bool enabled;
-
-- WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
-+ I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
-
- val = I915_READ(PCH_DREF_CONTROL);
- enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
- DREF_SUPERSPREAD_SOURCE_MASK));
-- WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
-+ I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
- }
-
- static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
-@@ -1355,7 +1355,7 @@ static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
- reg = PCH_TRANSCONF(pipe);
- val = I915_READ(reg);
- enabled = !!(val & TRANS_ENABLE);
-- WARN(enabled,
-+ I915_STATE_WARN(enabled,
- "transcoder assertion failed, should be off on pipe %c but is still active\n",
- pipe_name(pipe));
- }
-@@ -1435,11 +1435,11 @@ static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
- enum pipe pipe, int reg, u32 port_sel)
- {
- u32 val = I915_READ(reg);
-- WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
-+ I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
- "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
- reg, pipe_name(pipe));
-
-- WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
-+ I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
- && (val & DP_PIPEB_SELECT),
- "IBX PCH dp port still using transcoder B\n");
- }
-@@ -1448,11 +1448,11 @@ static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
- enum pipe pipe, int reg)
- {
- u32 val = I915_READ(reg);
-- WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
-+ I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
- "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
- reg, pipe_name(pipe));
-
-- WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
-+ I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
- && (val & SDVO_PIPE_B_SELECT),
- "IBX PCH hdmi port still using transcoder B\n");
- }
-@@ -1469,13 +1469,13 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
-
- reg = PCH_ADPA;
- val = I915_READ(reg);
-- WARN(adpa_pipe_enabled(dev_priv, pipe, val),
-+ I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
- "PCH VGA enabled on transcoder %c, should be disabled\n",
- pipe_name(pipe));
-
- reg = PCH_LVDS;
- val = I915_READ(reg);
-- WARN(lvds_pipe_enabled(dev_priv, pipe, val),
-+ I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
- "PCH LVDS enabled on transcoder %c, should be disabled\n",
- pipe_name(pipe));
-
-@@ -5388,25 +5388,25 @@ static void intel_connector_check_state(struct intel_connector *connector)
- if (connector->mst_port)
- return;
-
-- WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
-+ I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
- "wrong connector dpms state\n");
-- WARN(connector->base.encoder != &encoder->base,
-+ I915_STATE_WARN(connector->base.encoder != &encoder->base,
- "active connector not linked to encoder\n");
-
- if (encoder) {
-- WARN(!encoder->connectors_active,
-+ I915_STATE_WARN(!encoder->connectors_active,
- "encoder->connectors_active not set\n");
-
- encoder_enabled = encoder->get_hw_state(encoder, &pipe);
-- WARN(!encoder_enabled, "encoder not enabled\n");
-- if (WARN_ON(!encoder->base.crtc))
-+ I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
-+ if (I915_STATE_WARN_ON(!encoder->base.crtc))
- return;
-
- crtc = encoder->base.crtc;
-
-- WARN(!crtc->enabled, "crtc not enabled\n");
-- WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
-- WARN(pipe != to_intel_crtc(crtc)->pipe,
-+ I915_STATE_WARN(!crtc->enabled, "crtc not enabled\n");
-+ I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
-+ I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
- "encoder active on the wrong pipe\n");
- }
- }
-@@ -7814,24 +7814,24 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
- struct intel_crtc *crtc;
-
- for_each_intel_crtc(dev, crtc)
-- WARN(crtc->active, "CRTC for pipe %c enabled\n",
-+ I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
- pipe_name(crtc->pipe));
-
-- WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
-- WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
-- WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
-- WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
-- WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
-- WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
-+ I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
-+ I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
-+ I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
-+ I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
-+ I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
-+ I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
- "CPU PWM1 enabled\n");
- if (IS_HASWELL(dev))
-- WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
-+ I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
- "CPU PWM2 enabled\n");
-- WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
-+ I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
- "PCH PWM1 enabled\n");
-- WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
-+ I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
- "Utility pin enabled\n");
-- WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
-+ I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
-
- /*
- * In theory we can still leave IRQs enabled, as long as only the HPD
-@@ -7839,7 +7839,7 @@ static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
- * gen-specific and since we only disable LCPLL after we fully disable
- * the interrupts, the check below should be enough.
- */
-- WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
-+ I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
- }
-
- static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
-@@ -10746,7 +10746,7 @@ check_connector_state(struct drm_device *dev)
- * ->get_hw_state callbacks. */
- intel_connector_check_state(connector);
-
-- WARN(&connector->new_encoder->base != connector->base.encoder,
-+ I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
- "connector's staged encoder doesn't match current encoder\n");
- }
- }
-@@ -10766,9 +10766,9 @@ check_encoder_state(struct drm_device *dev)
- encoder->base.base.id,
- encoder->base.name);
-
-- WARN(&encoder->new_crtc->base != encoder->base.crtc,
-+ I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
- "encoder's stage crtc doesn't match current crtc\n");
-- WARN(encoder->connectors_active && !encoder->base.crtc,
-+ I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
- "encoder's active_connectors set, but no crtc\n");
-
- list_for_each_entry(connector, &dev->mode_config.connector_list,
-@@ -10787,19 +10787,19 @@ check_encoder_state(struct drm_device *dev)
- if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
- continue;
-
-- WARN(!!encoder->base.crtc != enabled,
-+ I915_STATE_WARN(!!encoder->base.crtc != enabled,
- "encoder's enabled state mismatch "
- "(expected %i, found %i)\n",
- !!encoder->base.crtc, enabled);
-- WARN(active && !encoder->base.crtc,
-+ I915_STATE_WARN(active && !encoder->base.crtc,
- "active encoder with no crtc\n");
-
-- WARN(encoder->connectors_active != active,
-+ I915_STATE_WARN(encoder->connectors_active != active,
- "encoder's computed active state doesn't match tracked active state "
- "(expected %i, found %i)\n", active, encoder->connectors_active);
-
- active = encoder->get_hw_state(encoder, &pipe);
-- WARN(active != encoder->connectors_active,
-+ I915_STATE_WARN(active != encoder->connectors_active,
- "encoder's hw state doesn't match sw tracking "
- "(expected %i, found %i)\n",
- encoder->connectors_active, active);
-@@ -10808,7 +10808,7 @@ check_encoder_state(struct drm_device *dev)
- continue;
-
- tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
-- WARN(active && pipe != tracked_pipe,
-+ I915_STATE_WARN(active && pipe != tracked_pipe,
- "active encoder's pipe doesn't match"
- "(expected %i, found %i)\n",
- tracked_pipe, pipe);
-@@ -10833,7 +10833,7 @@ check_crtc_state(struct drm_device *dev)
- DRM_DEBUG_KMS("[CRTC:%d]\n",
- crtc->base.base.id);
-
-- WARN(crtc->active && !crtc->base.enabled,
-+ I915_STATE_WARN(crtc->active && !crtc->base.enabled,
- "active crtc, but not enabled in sw tracking\n");
-
- for_each_intel_encoder(dev, encoder) {
-@@ -10844,10 +10844,10 @@ check_crtc_state(struct drm_device *dev)
- active = true;
- }
-
-- WARN(active != crtc->active,
-+ I915_STATE_WARN(active != crtc->active,
- "crtc's computed active state doesn't match tracked active state "
- "(expected %i, found %i)\n", active, crtc->active);
-- WARN(enabled != crtc->base.enabled,
-+ I915_STATE_WARN(enabled != crtc->base.enabled,
- "crtc's computed enabled state doesn't match tracked enabled state "
- "(expected %i, found %i)\n", enabled, crtc->base.enabled);
-
-@@ -10867,13 +10867,13 @@ check_crtc_state(struct drm_device *dev)
- encoder->get_config(encoder, &pipe_config);
- }
-
-- WARN(crtc->active != active,
-+ I915_STATE_WARN(crtc->active != active,
- "crtc active state doesn't match with hw state "
- "(expected %i, found %i)\n", crtc->active, active);
-
- if (active &&
- !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
-- WARN(1, "pipe state doesn't match!\n");
-+ I915_STATE_WARN(1, "pipe state doesn't match!\n");
- intel_dump_pipe_config(crtc, &pipe_config,
- "[hw state]");
- intel_dump_pipe_config(crtc, &crtc->config,
-@@ -10901,14 +10901,14 @@ check_shared_dpll_state(struct drm_device *dev)
-
- active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
-
-- WARN(pll->active > hweight32(pll->config.crtc_mask),
-+ I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
- "more active pll users than references: %i vs %i\n",
- pll->active, hweight32(pll->config.crtc_mask));
-- WARN(pll->active && !pll->on,
-+ I915_STATE_WARN(pll->active && !pll->on,
- "pll in active use but not on in sw tracking\n");
-- WARN(pll->on && !pll->active,
-+ I915_STATE_WARN(pll->on && !pll->active,
- "pll in on but not on in use in sw tracking\n");
-- WARN(pll->on != active,
-+ I915_STATE_WARN(pll->on != active,
- "pll on state mismatch (expected %i, found %i)\n",
- pll->on, active);
-
-@@ -10918,14 +10918,14 @@ check_shared_dpll_state(struct drm_device *dev)
- if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
- active_crtcs++;
- }
-- WARN(pll->active != active_crtcs,
-+ I915_STATE_WARN(pll->active != active_crtcs,
- "pll active crtcs mismatch (expected %i, found %i)\n",
- pll->active, active_crtcs);
-- WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
-+ I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
- "pll enabled crtcs mismatch (expected %i, found %i)\n",
- hweight32(pll->config.crtc_mask), enabled_crtcs);
-
-- WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
-+ I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
- sizeof(dpll_hw_state)),
- "pll hw state mismatch\n");
- }
-diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
-index 9f6c8971855c..67adf6437f78 100644
---- a/drivers/gpu/drm/i915/intel_dp.c
-+++ b/drivers/gpu/drm/i915/intel_dp.c
-@@ -1558,7 +1558,7 @@ void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
- vdd = edp_panel_vdd_on(intel_dp);
- pps_unlock(intel_dp);
-
-- WARN(!vdd, "eDP port %c VDD already requested on\n",
-+ I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
- port_name(dp_to_dig_port(intel_dp)->port));
- }
-
-@@ -1642,7 +1642,7 @@ static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
- if (!is_edp(intel_dp))
- return;
-
-- WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
-+ I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
- port_name(dp_to_dig_port(intel_dp)->port));
-
- intel_dp->want_panel_vdd = false;
diff --git a/efi-Add-esrt-support.patch b/efi-Add-esrt-support.patch
new file mode 100644
index 0000000..8bfc2fe
--- /dev/null
+++ b/efi-Add-esrt-support.patch
@@ -0,0 +1,780 @@
+From: Peter Jones <pjones at redhat.com>
+Date: Tue, 18 Nov 2014 10:18:22 -0500
+Subject: [PATCH] efi: Add esrt support.
+
+Add sysfs files for the EFI System Resource Table (ESRT) under
+/sys/firmware/efi/esrt and for each EFI System Resource Entry under
+entries/ as a subdir.
+
+The EFI System Resource Table (ESRT) provides a read-only catalog of
+system components for which the system accepts firmware upgrades via
+UEFI's "Capsule Update" feature. This module allows userland utilities
+to evaluate what firmware updates can be applied to this system, and
+potentially arrange for those updates to occur.
+
+The ESRT is described as part of the UEFI specification, in version 2.5
+which should be available from http://uefi.org/specifications in early
+2015. If you're a member of the UEFI Forum, information about its
+addition to the standard is available as UEFI Mantis 1090.
+
+For some hardware platforms, additional restrictions may be found at
+http://msdn.microsoft.com/en-us/library/windows/hardware/jj128256.aspx ,
+and additional documentation may be found at
+http://download.microsoft.com/download/5/F/5/5F5D16CD-2530-4289-8019-94C6A20BED3C/windows-uefi-firmware-update-platform.docx
+.
+
+Signed-off-by: Peter Jones <pjones at redhat.com>
+---
+ Documentation/ABI/testing/sysfs-firmware-efi-esrt | 81 ++++
+ arch/x86/platform/efi/efi.c | 2 +
+ drivers/firmware/efi/Makefile | 2 +-
+ drivers/firmware/efi/efi.c | 82 +++-
+ drivers/firmware/efi/esrt.c | 464 ++++++++++++++++++++++
+ include/linux/efi.h | 8 +
+ 6 files changed, 637 insertions(+), 2 deletions(-)
+ create mode 100644 Documentation/ABI/testing/sysfs-firmware-efi-esrt
+ create mode 100644 drivers/firmware/efi/esrt.c
+
+diff --git a/Documentation/ABI/testing/sysfs-firmware-efi-esrt b/Documentation/ABI/testing/sysfs-firmware-efi-esrt
+new file mode 100644
+index 000000000000..6e431d1a4e79
+--- /dev/null
++++ b/Documentation/ABI/testing/sysfs-firmware-efi-esrt
+@@ -0,0 +1,81 @@
++What: /sys/firmware/efi/esrt/
++Date: February 2015
++Contact: Peter Jones <pjones at redhat.com>
++Description: Provides userland access to read the EFI System Resource Table
++ (ESRT), a catalog of firmware for which can be updated with
++ the UEFI UpdateCapsule mechanism described in section 7.5 of
++ the UEFI Standard.
++Users: fwupdate - https://github.com/rhinstaller/fwupdate
++
++What: /sys/firmware/efi/esrt/fw_resource_count
++Date: February 2015
++Contact: Peter Jones <pjones at redhat.com>
++Description: The number of entries in the ESRT
++
++What: /sys/firmware/efi/esrt/fw_resource_count_max
++Date: February 2015
++Contact: Peter Jones <pjones at redhat.com>
++Description: The maximum number of entries that /could/ be registered
++ in the allocation the table is currently in. This is
++ really only useful to the system firmware itself.
++
++What: /sys/firmware/efi/esrt/fw_resource_version
++Date: February 2015
++Contact: Peter Jones <pjones at redhat.com>
++Description: The version of the ESRT structure provided by the firmware.
++
++What: /sys/firmware/efi/esrt/entries/entry$N/
++Date: February 2015
++Contact: Peter Jones <pjones at redhat.com>
++Description: Each ESRT entry is identified by a GUID, and each gets a
++ subdirectory under entries/ .
++ example: /sys/firmware/efi/esrt/entries/entry0/
++
++What: /sys/firmware/efi/esrt/entries/entry$N/fw_type
++Date: February 2015
++Contact: Peter Jones <pjones at redhat.com>
++Description: What kind of firmware entry this is:
++ 0 - Unknown
++ 1 - System Firmware
++ 2 - Device Firmware
++ 3 - UEFI Driver
++
++What: /sys/firmware/efi/esrt/entries/entry$N/fw_class
++Date: February 2015
++Contact: Peter Jones <pjones at redhat.com>
++Description: This is the entry's guid, and will match the directory name.
++
++What: /sys/firmware/efi/esrt/entries/entry$N/fw_version
++Date: February 2015
++Contact: Peter Jones <pjones at redhat.com>
++Description: The version of the firmware currently installed. This is a
++ 32-bit unsigned integer.
++
++What: /sys/firmware/efi/esrt/entries/entry$N/lowest_supported_fw_version
++Date: February 2015
++Contact: Peter Jones <pjones at redhat.com>
++Description: The lowest version of the firmware that can be installed.
++
++What: /sys/firmware/efi/esrt/entries/entry$N/capsule_flags
++Date: February 2015
++Contact: Peter Jones <pjones at redhat.com>
++Description: Flags that must be passed to UpdateCapsule()
++
++What: /sys/firmware/efi/esrt/entries/entry$N/last_attempt_version
++Date: February 2015
++Contact: Peter Jones <pjones at redhat.com>
++Description: The last firmware version for which an update was attempted.
++
++What: /sys/firmware/efi/esrt/entries/entry$N/last_attempt_status
++Date: February 2015
++Contact: Peter Jones <pjones at redhat.com>
++Description: The result of the last firmware update attempt for the
++ firmware resource entry.
++ 0 - Success
++ 1 - Insufficient resources
++ 2 - Incorrect version
++ 3 - Invalid format
++ 4 - Authentication error
++ 5 - AC power event
++ 6 - Battery power event
++
+diff --git a/arch/x86/platform/efi/efi.c b/arch/x86/platform/efi/efi.c
+index dbc8627a5cdf..b4c9fbbc9270 100644
+--- a/arch/x86/platform/efi/efi.c
++++ b/arch/x86/platform/efi/efi.c
+@@ -492,6 +492,8 @@ void __init efi_init(void)
+ return;
+
+ print_efi_memmap();
++
++ efi_esrt_init();
+ }
+
+ void __init efi_late_init(void)
+diff --git a/drivers/firmware/efi/Makefile b/drivers/firmware/efi/Makefile
+index d8be608a9f3b..26eabbc55341 100644
+--- a/drivers/firmware/efi/Makefile
++++ b/drivers/firmware/efi/Makefile
+@@ -1,7 +1,7 @@
+ #
+ # Makefile for linux kernel
+ #
+-obj-$(CONFIG_EFI) += efi.o vars.o reboot.o
++obj-$(CONFIG_EFI) += efi.o esrt.o vars.o reboot.o
+ obj-$(CONFIG_EFI_VARS) += efivars.o
+ obj-$(CONFIG_EFI_VARS_PSTORE) += efi-pstore.o
+ obj-$(CONFIG_UEFI_CPER) += cper.o
+diff --git a/drivers/firmware/efi/efi.c b/drivers/firmware/efi/efi.c
+index 3061bb8629dc..48b4c356740f 100644
+--- a/drivers/firmware/efi/efi.c
++++ b/drivers/firmware/efi/efi.c
+@@ -39,6 +39,7 @@ struct efi __read_mostly efi = {
+ .fw_vendor = EFI_INVALID_TABLE_ADDR,
+ .runtime = EFI_INVALID_TABLE_ADDR,
+ .config_table = EFI_INVALID_TABLE_ADDR,
++ .esrt = EFI_INVALID_TABLE_ADDR,
+ };
+ EXPORT_SYMBOL(efi);
+
+@@ -64,7 +65,7 @@ static int __init parse_efi_cmdline(char *str)
+ }
+ early_param("efi", parse_efi_cmdline);
+
+-static struct kobject *efi_kobj;
++struct kobject *efi_kobj;
+ static struct kobject *efivars_kobj;
+
+ /*
+@@ -232,6 +233,84 @@ err_put:
+
+ subsys_initcall(efisubsys_init);
+
++/*
++ * Find the efi memory descriptor for a given physical address. Given a
++ * physicall address, determine if it exists within an EFI Memory Map entry,
++ * and if so, populate the supplied memory descriptor with the appropriate
++ * data.
++ */
++int __init efi_mem_desc_lookup(u64 phys_addr, efi_memory_desc_t *out_md)
++{
++ struct efi_memory_map *map = efi.memmap;
++ void *p, *e;
++
++ if (!efi_enabled(EFI_MEMMAP)) {
++ pr_err_once("EFI_MEMMAP is not enabled.\n");
++ return -EINVAL;
++ }
++
++ if (!map) {
++ pr_err_once("efi.memmap is not set.\n");
++ return -EINVAL;
++ }
++ if (!out_md) {
++ pr_err_once("out_md is null.\n");
++ return -EINVAL;
++ }
++ if (WARN_ON_ONCE(!map->phys_map))
++ return -EINVAL;
++ if (WARN_ON_ONCE(map->nr_map == 0) || WARN_ON_ONCE(map->desc_size == 0))
++ return -EINVAL;
++
++ e = map->phys_map + map->nr_map * map->desc_size;
++ for (p = map->phys_map; p < e; p += map->desc_size) {
++ efi_memory_desc_t *md;
++ u64 size;
++ u64 end;
++
++ /*
++ * If a driver calls this after efi_free_boot_services,
++ * ->map will be NULL, and the target may also not be mapped.
++ * So just always get our own virtual map on the CPU.
++ *
++ */
++ md = early_memremap((phys_addr_t)p, sizeof (*md));
++ if (!md) {
++ pr_err_once("early_memremap(%p, %zu) failed.\n",
++ p, sizeof (*md));
++ return -ENOMEM;
++ }
++
++ if (!(md->attribute & EFI_MEMORY_RUNTIME) &&
++ md->type != EFI_BOOT_SERVICES_DATA &&
++ md->type != EFI_RUNTIME_SERVICES_DATA) {
++ early_memunmap(md, sizeof (*md));
++ continue;
++ }
++
++ size = md->num_pages << EFI_PAGE_SHIFT;
++ end = md->phys_addr + size;
++ if (phys_addr >= md->phys_addr && phys_addr < end) {
++ memcpy(out_md, md, sizeof(*out_md));
++ early_memunmap(md, sizeof (*md));
++ return 0;
++ }
++
++ early_memunmap(md, sizeof (*md));
++ }
++ pr_err_once("requested map not found.\n");
++ return -ENOENT;
++}
++
++/*
++ * Calculate the highest address of an efi memory descriptor.
++ */
++u64 __init efi_mem_desc_end(efi_memory_desc_t *md)
++{
++ u64 size = md->num_pages << EFI_PAGE_SHIFT;
++ u64 end = md->phys_addr + size;
++ return end;
++}
+
+ /*
+ * We can't ioremap data in EFI boot services RAM, because we've already mapped
+@@ -274,6 +353,7 @@ static __initdata efi_config_table_type_t common_tables[] = {
+ {SMBIOS_TABLE_GUID, "SMBIOS", &efi.smbios},
+ {SMBIOS3_TABLE_GUID, "SMBIOS 3.0", &efi.smbios3},
+ {UGA_IO_PROTOCOL_GUID, "UGA", &efi.uga},
++ {EFI_SYSTEM_RESOURCE_TABLE_GUID, "ESRT", &efi.esrt},
+ {NULL_GUID, NULL, NULL},
+ };
+
+diff --git a/drivers/firmware/efi/esrt.c b/drivers/firmware/efi/esrt.c
+new file mode 100644
+index 000000000000..20c0cbdb1c60
+--- /dev/null
++++ b/drivers/firmware/efi/esrt.c
+@@ -0,0 +1,464 @@
++/*
++ * esrt.c
++ *
++ * This module exports EFI System Resource Table (ESRT) entries into userspace
++ * through the sysfs file system. The ESRT provides a read-only catalog of
++ * system components for which the system accepts firmware upgrades via UEFI's
++ * "Capsule Update" feature. This module allows userland utilities to evaluate
++ * what firmware updates can be applied to this system, and potentially arrange
++ * for those updates to occur.
++ *
++ * Data is currently found below /sys/firmware/efi/esrt/...
++ */
++#define pr_fmt(fmt) "esrt: " fmt
++
++#include <linux/capability.h>
++#include <linux/device.h>
++#include <linux/efi.h>
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/kobject.h>
++#include <linux/list.h>
++#include <linux/memblock.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++#include <linux/types.h>
++
++#include <asm/io.h>
++#include <asm/early_ioremap.h>
++
++struct efi_system_resource_entry_v1 {
++ efi_guid_t fw_class;
++ u32 fw_type;
++ u32 fw_version;
++ u32 lowest_supported_fw_version;
++ u32 capsule_flags;
++ u32 last_attempt_version;
++ u32 last_attempt_status;
++};
++
++/*
++ * _count and _version are what they seem like. _max is actually just
++ * accounting info for the firmware when creating the table; it should never
++ * have been exposed to us. To wit, the spec says:
++ * The maximum number of resource array entries that can be within the
++ * table without reallocating the table, must not be zero.
++ * Since there's no guidance about what that means in terms of memory layout,
++ * it means nothing to us.
++ */
++struct efi_system_resource_table {
++ u32 fw_resource_count;
++ u32 fw_resource_count_max;
++ u64 fw_resource_version;
++ u8 entries[];
++};
++
++static phys_addr_t esrt_data;
++static size_t esrt_data_size;
++
++static struct efi_system_resource_table *esrt;
++
++struct esre_entry {
++ union {
++ struct efi_system_resource_entry_v1 *esre1;
++ } esre;
++
++ struct kobject kobj;
++ struct list_head list;
++};
++
++/* global list of esre_entry. */
++static LIST_HEAD(entry_list);
++
++/* entry attribute */
++struct esre_attribute {
++ struct attribute attr;
++ ssize_t (*show)(struct esre_entry *entry, char *buf);
++ ssize_t (*store)(struct esre_entry *entry,
++ const char *buf, size_t count);
++};
++
++static struct esre_entry *to_entry(struct kobject *kobj)
++{
++ return container_of(kobj, struct esre_entry, kobj);
++}
++
++static struct esre_attribute *to_attr(struct attribute *attr)
++{
++ return container_of(attr, struct esre_attribute, attr);
++}
++
++static ssize_t esre_attr_show(struct kobject *kobj,
++ struct attribute *_attr, char *buf)
++{
++ struct esre_entry *entry = to_entry(kobj);
++ struct esre_attribute *attr = to_attr(_attr);
++
++ /* Don't tell normal users what firmware versions we've got... */
++ if (!capable(CAP_SYS_ADMIN))
++ return -EACCES;
++
++ return attr->show(entry, buf);
++}
++
++static const struct sysfs_ops esre_attr_ops = {
++ .show = esre_attr_show,
++};
++
++/* Generic ESRT Entry ("ESRE") support. */
++static ssize_t esre_fw_class_show(struct esre_entry *entry, char *buf)
++{
++ char *str = buf;
++
++ efi_guid_to_str(&entry->esre.esre1->fw_class, str);
++ str += strlen(str);
++ str += sprintf(str, "\n");
++
++ return str - buf;
++}
++
++static struct esre_attribute esre_fw_class = __ATTR(fw_class, 0400,
++ esre_fw_class_show, NULL);
++
++#define esre_attr_decl(name, size, fmt) \
++static ssize_t esre_##name##_show(struct esre_entry *entry, char *buf) \
++{ \
++ return sprintf(buf, fmt "\n", \
++ le##size##_to_cpu(entry->esre.esre1->name)); \
++} \
++\
++static struct esre_attribute esre_##name = __ATTR(name, 0400, \
++ esre_##name##_show, NULL)
++
++esre_attr_decl(fw_type, 32, "%u");
++esre_attr_decl(fw_version, 32, "%u");
++esre_attr_decl(lowest_supported_fw_version, 32, "%u");
++esre_attr_decl(capsule_flags, 32, "0x%x");
++esre_attr_decl(last_attempt_version, 32, "%u");
++esre_attr_decl(last_attempt_status, 32, "%u");
++
++static struct attribute *esre1_attrs[] = {
++ &esre_fw_class.attr,
++ &esre_fw_type.attr,
++ &esre_fw_version.attr,
++ &esre_lowest_supported_fw_version.attr,
++ &esre_capsule_flags.attr,
++ &esre_last_attempt_version.attr,
++ &esre_last_attempt_status.attr,
++ NULL
++};
++static void esre_release(struct kobject *kobj)
++{
++ struct esre_entry *entry = to_entry(kobj);
++
++ list_del(&entry->list);
++ kfree(entry);
++}
++
++static struct kobj_type esre1_ktype = {
++ .release = esre_release,
++ .sysfs_ops = &esre_attr_ops,
++ .default_attrs = esre1_attrs,
++};
++
++
++static struct kobject *esrt_kobj;
++static struct kset *esrt_kset;
++
++static int esre_create_sysfs_entry(void *esre, int entry_num)
++{
++ int rc = 0;
++ struct esre_entry *entry;
++ char name[20];
++
++ entry = kzalloc(sizeof(*entry), GFP_KERNEL);
++ if (!entry)
++ return -ENOMEM;
++
++ sprintf(name, "entry%d", entry_num);
++
++ entry->kobj.kset = esrt_kset;
++
++ if (esrt->fw_resource_version == 1) {
++ entry->esre.esre1 = esre;
++ rc = kobject_init_and_add(&entry->kobj, &esre1_ktype, NULL,
++ "%s", name);
++ }
++ if (rc) {
++ kfree(entry);
++ return rc;
++ }
++
++ list_add_tail(&entry->list, &entry_list);
++ return 0;
++}
++
++/* support for displaying ESRT fields at the top level */
++#define esrt_attr_decl(name, size, fmt) \
++static ssize_t esrt_##name##_show(struct kobject *kobj, \
++ struct kobj_attribute *attr, char *buf)\
++{ \
++ return sprintf(buf, fmt "\n", le##size##_to_cpu(esrt->name)); \
++} \
++\
++static struct kobj_attribute esrt_##name = __ATTR(name, 0400, \
++ esrt_##name##_show, NULL)
++
++esrt_attr_decl(fw_resource_count, 32, "%u");
++esrt_attr_decl(fw_resource_count_max, 32, "%u");
++esrt_attr_decl(fw_resource_version, 64, "%llu");
++
++static struct attribute *esrt_attrs[] = {
++ &esrt_fw_resource_count.attr,
++ &esrt_fw_resource_count_max.attr,
++ &esrt_fw_resource_version.attr,
++ NULL,
++};
++
++static inline int esrt_table_exists(void)
++{
++ if (!efi_enabled(EFI_CONFIG_TABLES))
++ return 0;
++ if (efi.esrt == EFI_INVALID_TABLE_ADDR)
++ return 0;
++ return 1;
++}
++
++static umode_t esrt_attr_is_visible(struct kobject *kobj,
++ struct attribute *attr, int n)
++{
++ if (!esrt_table_exists())
++ return 0;
++ return attr->mode;
++}
++
++static struct attribute_group esrt_attr_group = {
++ .attrs = esrt_attrs,
++ .is_visible = esrt_attr_is_visible,
++};
++
++/*
++ * remap the table, copy it to kmalloced pages, and unmap it.
++ */
++void __init efi_esrt_init(void)
++{
++ void *va;
++ struct efi_system_resource_table tmpesrt;
++ struct efi_system_resource_entry_v1 *v1_entries;
++ size_t size, max, entry_size, entries_size;
++ efi_memory_desc_t md;
++ int rc;
++
++ pr_debug("esrt-init: loading.\n");
++ if (!esrt_table_exists())
++ return;
++
++ rc = efi_mem_desc_lookup(efi.esrt, &md);
++ if (rc < 0) {
++ pr_err("ESRT header is not in the memory map.\n");
++ return;
++ }
++
++ max = efi_mem_desc_end(&md);
++ if (max < efi.esrt) {
++ pr_err("EFI memory descriptor is invalid. (esrt: %p max: %p)\n",
++ (void *)efi.esrt, (void *)max);
++ return;
++ }
++
++ size = sizeof(*esrt);
++ max -= efi.esrt;
++
++ if (max < size) {
++ pr_err("ESRT header doen't fit on single memory map entry. (size: %zu max: %zu)\n",
++ size, max);
++ return;
++ }
++
++ va = early_memremap(efi.esrt, size);
++ if (!va) {
++ pr_err("early_memremap(%p, %zu) failed.\n", (void *)efi.esrt,
++ size);
++ return;
++ }
++
++ memcpy(&tmpesrt, va, sizeof(tmpesrt));
++
++ if (tmpesrt.fw_resource_version == 1) {
++ entry_size = sizeof (*v1_entries);
++ } else {
++ pr_err("Unsupported ESRT version %lld.\n",
++ tmpesrt.fw_resource_version);
++ return;
++ }
++
++ if (tmpesrt.fw_resource_count > 0 && max - size < entry_size) {
++ pr_err("ESRT memory map entry can only hold the header. (max: %zu size: %zu)\n",
++ max - size, entry_size);
++ goto err_memunmap;
++ }
++
++ /*
++ * The format doesn't really give us any boundary to test here,
++ * so I'm making up 128 as the max number of individually updatable
++ * components we support.
++ * 128 should be pretty excessive, but there's still some chance
++ * somebody will do that someday and we'll need to raise this.
++ */
++ if (tmpesrt.fw_resource_count > 128) {
++ pr_err("ESRT says fw_resource_count has very large value %d.\n",
++ tmpesrt.fw_resource_count);
++ goto err_memunmap;
++ }
++
++ /*
++ * We know it can't be larger than N * sizeof() here, and N is limited
++ * by the previous test to a small number, so there's no overflow.
++ */
++ entries_size = tmpesrt.fw_resource_count * entry_size;
++ if (max < size + entries_size) {
++ pr_err("ESRT does not fit on single memory map entry (size: %zu max: %zu)\n",
++ size, max);
++ goto err_memunmap;
++ }
++
++ /* remap it with our (plausible) new pages */
++ early_memunmap(va, size);
++ size += entries_size;
++ va = early_memremap(efi.esrt, size);
++ if (!va) {
++ pr_err("early_memremap(%p, %zu) failed.\n", (void *)efi.esrt,
++ size);
++ return;
++ }
++
++ esrt_data = (phys_addr_t)efi.esrt;
++ esrt_data_size = size;
++
++ pr_info("Reserving ESRT space from %p to %p.\n", (void *)esrt_data,
++ (char *)esrt_data + size);
++ memblock_reserve(esrt_data, esrt_data_size);
++
++ pr_debug("esrt-init: loaded.\n");
++err_memunmap:
++ early_memunmap(va, size);
++}
++
++static int __init register_entries(void)
++{
++ struct efi_system_resource_entry_v1 *v1_entries = (void *)esrt->entries;
++ int i, rc;
++
++ if (!esrt_table_exists())
++ return 0;
++
++ for (i = 0; i < le32_to_cpu(esrt->fw_resource_count); i++) {
++ void *entry;
++ if (esrt->fw_resource_version == 1) {
++ entry = &v1_entries[i];
++ }
++ rc = esre_create_sysfs_entry(entry, i);
++ if (rc < 0) {
++ pr_err("ESRT entry creation failed with error %d.\n",
++ rc);
++ return rc;
++ }
++ }
++ return 0;
++}
++
++static void cleanup_entry_list(void)
++{
++ struct esre_entry *entry, *next;
++
++ list_for_each_entry_safe(entry, next, &entry_list, list) {
++ kobject_put(&entry->kobj);
++ }
++}
++
++static int __init esrt_sysfs_init(void)
++{
++ int error;
++ struct efi_system_resource_table __iomem *ioesrt;
++
++ pr_debug("esrt-sysfs: loading.\n");
++ if (!esrt_data || !esrt_data_size)
++ return -ENOSYS;
++
++ ioesrt = ioremap(esrt_data, esrt_data_size);
++ if (!ioesrt) {
++ pr_err("ioremap(%p, %zu) failed.\n", (void *)esrt_data,
++ esrt_data_size);
++ return -ENOMEM;
++ }
++
++ esrt = kmalloc(esrt_data_size, GFP_KERNEL);
++ if (!esrt) {
++ pr_err("kmalloc failed. (wanted %zu bytes)\n", esrt_data_size);
++ iounmap(ioesrt);
++ return -ENOMEM;
++ }
++
++ memcpy_fromio(esrt, ioesrt, esrt_data_size);
++
++ esrt_kobj = kobject_create_and_add("esrt", efi_kobj);
++ if (!esrt_kobj) {
++ pr_err("Firmware table registration failed.\n");
++ error = -ENOMEM;
++ goto err;
++ }
++
++ error = sysfs_create_group(esrt_kobj, &esrt_attr_group);
++ if (error) {
++ pr_err("Sysfs attribute export failed with error %d.\n",
++ error);
++ goto err_remove_esrt;
++ }
++
++ esrt_kset = kset_create_and_add("entries", NULL, esrt_kobj);
++ if (!esrt_kset) {
++ pr_err("kset creation failed.\n");
++ error = -ENOMEM;
++ goto err_remove_group;
++ }
++
++ error = register_entries();
++ if (error)
++ goto err_cleanup_list;
++
++ memblock_remove(esrt_data, esrt_data_size);
++
++ pr_debug("esrt-sysfs: loaded.\n");
++
++ return 0;
++err_cleanup_list:
++ cleanup_entry_list();
++ kset_unregister(esrt_kset);
++err_remove_group:
++ sysfs_remove_group(esrt_kobj, &esrt_attr_group);
++err_remove_esrt:
++ kobject_put(esrt_kobj);
++err:
++ kfree(esrt);
++ esrt = NULL;
++ return error;
++}
++
++static void __exit esrt_sysfs_exit(void)
++{
++ pr_debug("esrt-sysfs: unloading.\n");
++ cleanup_entry_list();
++ kset_unregister(esrt_kset);
++ sysfs_remove_group(esrt_kobj, &esrt_attr_group);
++ kfree(esrt);
++ esrt = NULL;
++ kobject_del(esrt_kobj);
++ kobject_put(esrt_kobj);
++}
++
++module_init(esrt_sysfs_init);
++module_exit(esrt_sysfs_exit);
++
++MODULE_AUTHOR("Peter Jones <pjones at redhat.com>");
++MODULE_DESCRIPTION("EFI System Resource Table support");
++MODULE_LICENSE("GPL");
+diff --git a/include/linux/efi.h b/include/linux/efi.h
+index 470e8dfcb517..c15e1de5273c 100644
+--- a/include/linux/efi.h
++++ b/include/linux/efi.h
+@@ -583,6 +583,9 @@ void efi_native_runtime_setup(void);
+ #define EFI_FILE_INFO_ID \
+ EFI_GUID( 0x9576e92, 0x6d3f, 0x11d2, 0x8e, 0x39, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b )
+
++#define EFI_SYSTEM_RESOURCE_TABLE_GUID \
++ EFI_GUID( 0xb122a263, 0x3661, 0x4f68, 0x99, 0x29, 0x78, 0xf8, 0xb0, 0xd6, 0x21, 0x80 )
++
+ #define EFI_FILE_SYSTEM_GUID \
+ EFI_GUID( 0x964e5b22, 0x6459, 0x11d2, 0x8e, 0x39, 0x00, 0xa0, 0xc9, 0x69, 0x72, 0x3b )
+
+@@ -849,6 +852,7 @@ extern struct efi {
+ unsigned long fw_vendor; /* fw_vendor */
+ unsigned long runtime; /* runtime table */
+ unsigned long config_table; /* config tables */
++ unsigned long esrt; /* ESRT table */
+ efi_get_time_t *get_time;
+ efi_set_time_t *set_time;
+ efi_get_wakeup_time_t *get_wakeup_time;
+@@ -901,6 +905,7 @@ static inline efi_status_t efi_query_variable_store(u32 attributes, unsigned lon
+ #endif
+ extern void __iomem *efi_lookup_mapped_addr(u64 phys_addr);
+ extern int efi_config_init(efi_config_table_type_t *arch_tables);
++extern void __init efi_esrt_init(void);
+ extern int efi_config_parse_tables(void *config_tables, int count, int sz,
+ efi_config_table_type_t *arch_tables);
+ extern u64 efi_get_iobase (void);
+@@ -908,12 +913,15 @@ extern u32 efi_mem_type (unsigned long phys_addr);
+ extern u64 efi_mem_attributes (unsigned long phys_addr);
+ extern u64 efi_mem_attribute (unsigned long phys_addr, unsigned long size);
+ extern int __init efi_uart_console_only (void);
++extern u64 efi_mem_desc_end(efi_memory_desc_t *md);
++extern int efi_mem_desc_lookup(u64 phys_addr, efi_memory_desc_t *out_md);
+ extern void efi_initialize_iomem_resources(struct resource *code_resource,
+ struct resource *data_resource, struct resource *bss_resource);
+ extern void efi_get_time(struct timespec *now);
+ extern void efi_reserve_boot_services(void);
+ extern int efi_get_fdt_params(struct efi_fdt_params *params, int verbose);
+ extern struct efi_memory_map memmap;
++extern struct kobject *efi_kobj;
+
+ extern int efi_reboot_quirk_mode;
+ extern bool efi_poweroff_required(void);
diff --git a/iommu-exynos-Play-nice-in-multi-platform-builds.patch b/iommu-exynos-Play-nice-in-multi-platform-builds.patch
deleted file mode 100644
index 5dbb6e6..0000000
--- a/iommu-exynos-Play-nice-in-multi-platform-builds.patch
+++ /dev/null
@@ -1,46 +0,0 @@
-From: Thierry Reding <treding at nvidia.com>
-Date: Fri, 6 Feb 2015 11:44:05 +0100
-Subject: [PATCH] iommu/exynos: Play nice in multi-platform builds
-
-The Exynos System MMU driver unconditionally executes code and registers
-a struct iommu_ops with the platform bus irrespective of whether it runs
-on an Exynos SoC or not. This causes problems in multi-platform kernels
-where drivers for other SoCs will no longer be able to register their
-own struct iommu_ops or even try to use a struct iommu_ops for an IOMMU
-that obviously isn't there.
-
-The smallest fix I could think of is to check for the existence of any
-Exynos System MMU devices in the device tree and skip initialization
-otherwise.
-
-This fixes a problem on Tegra20 where the DRM driver will try to use the
-obviously non-existent Exynos System MMU.
-
-Reported-by: Nicolas Chauvet <kwizart at gmail.com>
-Cc: Kukjin Kim <kgene at kernel.org>
-Signed-off-by: Thierry Reding <treding at nvidia.com>
-Signed-off-by: Joerg Roedel <jroedel at suse.de>
----
- drivers/iommu/exynos-iommu.c | 7 +++++++
- 1 file changed, 7 insertions(+)
-
-diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c
-index 7ce52737c7a1..dc14fec4ede1 100644
---- a/drivers/iommu/exynos-iommu.c
-+++ b/drivers/iommu/exynos-iommu.c
-@@ -1186,8 +1186,15 @@ static const struct iommu_ops exynos_iommu_ops = {
-
- static int __init exynos_iommu_init(void)
- {
-+ struct device_node *np;
- int ret;
-
-+ np = of_find_matching_node(NULL, sysmmu_of_match);
-+ if (!np)
-+ return 0;
-+
-+ of_node_put(np);
-+
- lv2table_kmem_cache = kmem_cache_create("exynos-iommu-lv2table",
- LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL);
- if (!lv2table_kmem_cache) {
diff --git a/iommu-omap-Play-nice-in-multi-platform-builds.patch b/iommu-omap-Play-nice-in-multi-platform-builds.patch
deleted file mode 100644
index 693a66f..0000000
--- a/iommu-omap-Play-nice-in-multi-platform-builds.patch
+++ /dev/null
@@ -1,46 +0,0 @@
-From: Thierry Reding <treding at nvidia.com>
-Date: Fri, 6 Feb 2015 11:44:06 +0100
-Subject: [PATCH] iommu/omap: Play nice in multi-platform builds
-
-The OMAP IOMMU driver unconditionally executes code and registers a
-struct iommu_ops with the platform bus irrespective of whether it runs
-on an OMAP SoC or not. This causes problems in multi-platform kernels
-where drivers for other SoCs will no longer be able to register their
-own struct iommu_ops or even try to use a struct iommu_ops for an IOMMU
-that obviously isn't there.
-
-The smallest fix I could think of is to check for the existence of any
-OMAP IOMMU devices in the device tree and skip initialization otherwise.
-
-This fixes a problem on Tegra20 where the DRM driver will try to use the
-obviously non-existent OMAP IOMMU.
-
-Reported-by: Nicolas Chauvet <kwizart at gmail.com>
-Cc: Tony Lindgren <tony at atomide.com>
-Cc: Suman Anna <s-anna at ti.com>
-Cc: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
-Signed-off-by: Thierry Reding <treding at nvidia.com>
-Acked-by: Laurent Pinchart <laurent.pinchart at ideasonboard.com>
-Signed-off-by: Joerg Roedel <jroedel at suse.de>
----
- drivers/iommu/omap-iommu.c | 7 +++++++
- 1 file changed, 7 insertions(+)
-
-diff --git a/drivers/iommu/omap-iommu.c b/drivers/iommu/omap-iommu.c
-index bbb7dcef02d3..19db0b684b7f 100644
---- a/drivers/iommu/omap-iommu.c
-+++ b/drivers/iommu/omap-iommu.c
-@@ -1376,6 +1376,13 @@ static int __init omap_iommu_init(void)
- struct kmem_cache *p;
- const unsigned long flags = SLAB_HWCACHE_ALIGN;
- size_t align = 1 << 10; /* L2 pagetable alignement */
-+ struct device_node *np;
-+
-+ np = of_find_matching_node(NULL, omap_iommu_of_match);
-+ if (!np)
-+ return 0;
-+
-+ of_node_put(np);
-
- p = kmem_cache_create("iopte_cache", IOPTE_TABLE_SIZE, align, flags,
- iopte_cachep_ctor);
diff --git a/iommu-rockchip-Play-nice-in-multi-platform-builds.patch b/iommu-rockchip-Play-nice-in-multi-platform-builds.patch
deleted file mode 100644
index 8c9c9df..0000000
--- a/iommu-rockchip-Play-nice-in-multi-platform-builds.patch
+++ /dev/null
@@ -1,49 +0,0 @@
-From: Thierry Reding <treding at nvidia.com>
-Date: Fri, 6 Feb 2015 11:44:07 +0100
-Subject: [PATCH] iommu/rockchip: Play nice in multi-platform builds
-
-The Rockchip IOMMU driver unconditionally executes code and registers a
-struct iommu_ops with the platform bus irrespective of whether it runs
-on a Rockchip SoC or not. This causes problems in multi-platform kernels
-where drivers for other SoCs will no longer be able to register their
-own struct iommu_ops or even try to use a struct iommu_ops for an IOMMU
-that obviously isn't there.
-
-The smallest fix I could think of is to check for the existence of any
-Rockchip IOMMU devices in the device tree and skip initialization
-otherwise.
-
-This fixes a problem on Tegra20 where the DRM driver will try to use the
-obviously non-existent Rockchip IOMMU.
-
-Reported-by: Nicolas Chauvet <kwizart at gmail.com>
-Cc: Heiko Stuebner <heiko at sntech.de>
-Cc: Daniel Kurtz <djkurtz at chromium.org>
-Reviewed-by: Heiko Stuebner <heiko at sntech.de>
-Tested-by: Heiko Stuebner <heiko at sntech.de>
-Signed-off-by: Thierry Reding <treding at nvidia.com>
-Signed-off-by: Joerg Roedel <jroedel at suse.de>
----
- drivers/iommu/rockchip-iommu.c | 7 +++++++
- 1 file changed, 7 insertions(+)
-
-diff --git a/drivers/iommu/rockchip-iommu.c b/drivers/iommu/rockchip-iommu.c
-index 6a8b1ec4a48a..9f74fddcd304 100644
---- a/drivers/iommu/rockchip-iommu.c
-+++ b/drivers/iommu/rockchip-iommu.c
-@@ -1015,8 +1015,15 @@ static struct platform_driver rk_iommu_driver = {
-
- static int __init rk_iommu_init(void)
- {
-+ struct device_node *np;
- int ret;
-
-+ np = of_find_matching_node(NULL, rk_iommu_dt_ids);
-+ if (!np)
-+ return 0;
-+
-+ of_node_put(np);
-+
- ret = bus_set_iommu(&platform_bus_type, &rk_iommu_ops);
- if (ret)
- return ret;
diff --git a/kernel-arm64.patch b/kernel-arm64.patch
deleted file mode 100644
index df9c19d..0000000
--- a/kernel-arm64.patch
+++ /dev/null
@@ -1,6793 +0,0 @@
- Documentation/arm64/arm-acpi.txt | 323 ++++++++++
- Documentation/kernel-parameters.txt | 3 +-
- arch/arm/kvm/mmu.c | 4 +
- arch/arm64/Kconfig | 9 +
- arch/arm64/Makefile | 1 +
- arch/arm64/include/asm/acenv.h | 18 +
- arch/arm64/include/asm/acpi.h | 102 +++
- arch/arm64/include/asm/cpu_ops.h | 1 +
- arch/arm64/include/asm/elf.h | 3 +-
- arch/arm64/include/asm/pci.h | 51 ++
- arch/arm64/include/asm/psci.h | 3 +-
- arch/arm64/include/asm/smp.h | 10 +-
- arch/arm64/kernel/Makefile | 4 +-
- arch/arm64/kernel/acpi.c | 398 ++++++++++++
- arch/arm64/kernel/cpu_ops.c | 8 +-
- arch/arm64/kernel/efi.c | 37 ++
- arch/arm64/kernel/pci.c | 97 ++-
- arch/arm64/kernel/psci.c | 78 ++-
- arch/arm64/kernel/setup.c | 44 +-
- arch/arm64/kernel/smp.c | 2 +-
- arch/arm64/kernel/smp_parking_protocol.c | 110 ++++
- arch/arm64/kernel/time.c | 7 +
- arch/arm64/mm/dma-mapping.c | 112 ++++
- arch/arm64/pci/Makefile | 2 +
- arch/arm64/pci/mmconfig.c | 292 +++++++++
- arch/arm64/pci/pci.c | 461 ++++++++++++++
- drivers/acpi/Kconfig | 6 +-
- drivers/acpi/Makefile | 6 +-
- drivers/acpi/bus.c | 3 +
- drivers/acpi/internal.h | 5 +
- drivers/acpi/osl.c | 6 +-
- drivers/acpi/processor_core.c | 37 ++
- drivers/acpi/sleep-arm.c | 28 +
- drivers/acpi/tables.c | 48 +-
- drivers/acpi/utils.c | 26 +
- drivers/ata/Kconfig | 2 +-
- drivers/ata/ahci_platform.c | 13 +
- drivers/ata/ahci_xgene.c | 30 +-
- drivers/clocksource/arm_arch_timer.c | 136 +++-
- drivers/input/keyboard/gpio_keys_polled.c | 1 +
- drivers/iommu/arm-smmu.c | 8 +-
- drivers/irqchip/irq-gic-v3.c | 10 +
- drivers/irqchip/irq-gic.c | 118 ++++
- drivers/irqchip/irqchip.c | 3 +
- drivers/leds/leds-gpio.c | 1 +
- drivers/net/ethernet/amd/xgbe/xgbe-dev.c | 16 +-
- drivers/net/ethernet/amd/xgbe/xgbe-drv.c | 3 +
- drivers/net/ethernet/amd/xgbe/xgbe-main.c | 276 ++++++--
- drivers/net/ethernet/amd/xgbe/xgbe-mdio.c | 20 +-
- drivers/net/ethernet/amd/xgbe/xgbe-ptp.c | 4 +-
- drivers/net/ethernet/amd/xgbe/xgbe.h | 13 +
- drivers/net/ethernet/apm/xgene/xgene_enet_hw.c | 69 +-
- drivers/net/ethernet/apm/xgene/xgene_enet_main.c | 80 ++-
- drivers/net/ethernet/apm/xgene/xgene_enet_main.h | 1 +
- drivers/net/ethernet/smsc/smc91x.c | 10 +
- drivers/net/phy/amd-xgbe-phy.c | 777 ++++++++++++-----------
- drivers/pci/host/pci-xgene.c | 167 +++++
- drivers/pnp/resource.c | 2 +
- drivers/tty/Kconfig | 6 +
- drivers/tty/Makefile | 1 +
- drivers/tty/sbsauart.c | 358 +++++++++++
- drivers/tty/serial/8250/8250_dw.c | 9 +
- drivers/virtio/virtio_mmio.c | 12 +-
- include/acpi/acpi_bus.h | 2 +
- include/acpi/acpi_io.h | 6 +
- include/asm-generic/vmlinux.lds.h | 7 +
- include/kvm/arm_vgic.h | 20 +-
- include/linux/acpi.h | 1 +
- include/linux/clocksource.h | 6 +
- include/linux/irqchip/arm-gic-acpi.h | 31 +
- include/linux/irqchip/arm-gic.h | 2 +
- include/linux/pci.h | 37 +-
- virt/kvm/arm/arch_timer.c | 107 ++--
- virt/kvm/arm/vgic-v2.c | 86 ++-
- virt/kvm/arm/vgic-v3.c | 8 +-
- virt/kvm/arm/vgic.c | 30 +-
- 76 files changed, 4208 insertions(+), 626 deletions(-)
-
-diff --git a/Documentation/arm64/arm-acpi.txt b/Documentation/arm64/arm-acpi.txt
-new file mode 100644
-index 0000000..17cf96d
---- /dev/null
-+++ b/Documentation/arm64/arm-acpi.txt
-@@ -0,0 +1,323 @@
-+ACPI on ARMv8 Servers
-+---------------------
-+ACPI can be used for ARMv8 general purpose servers designed to follow
-+the ARM SBSA (Server Base System Architecture) specification, currently
-+available to those with an ARM login at http://silver.arm.com.
-+
-+The ARMv8 kernel implements the reduced hardware model of ACPI version
-+5.1 and its corresponding errata. Links to the specification and all
-+external documents it refers to are managed by the UEFI Forum. The
-+specification is available at http://www.uefi.org/specifications and
-+external documents can be found via http://www.uefi.org/acpi.
-+
-+If an ARMv8 system does not meet the requirements of the SBSA, or cannot
-+be described using the mechanisms defined in the required ACPI specifications,
-+then it is likely that Device Tree (DT) is more suitable than ACPI for the
-+hardware.
-+
-+
-+Relationship with Device Tree
-+-----------------------------
-+ACPI support in drivers and subsystems for ARMv8 should never be mutually
-+exclusive with DT support at compile time.
-+
-+At boot time the kernel will only use one description method depending on
-+parameters passed from the bootloader (including kernel bootargs).
-+
-+Regardless of whether DT or ACPI is used, the kernel must always be capable
-+of booting with either scheme (in kernels with both schemes enabled at compile
-+time).
-+
-+When booting using ACPI tables, the /chosen node in DT will still be parsed
-+to extract the kernel command line and initrd path. No other section of the
-+DT will be used.
-+
-+
-+Booting using ACPI tables
-+-------------------------
-+The only defined method for passing ACPI tables to the kernel on ARMv8
-+is via the UEFI system configuration table.
-+
-+Processing of ACPI tables may be disabled by passing acpi=off on the kernel
-+command line; this is the default behavior. If acpi=force is used, the kernel
-+will ONLY use device configuration information contained in the ACPI tables.
-+
-+In order for the kernel to load and use ACPI tables, the UEFI implementation
-+MUST set the ACPI_20_TABLE_GUID to point to the RSDP table (the table with
-+the ACPI signature "RSD PTR "). If this pointer is incorrect and acpi=force
-+is used, the kernel will disable ACPI and try to use DT to boot.
-+
-+If the pointer to the RSDP table is correct, the table will be mapped into
-+the kernel by the ACPI core, using the address provided by UEFI.
-+
-+The ACPI core will then locate and map in all other ACPI tables provided by
-+using the addresses in the RSDP table to find the XSDT (eXtended System
-+Description Table). The XSDT in turn provides the addresses to all other
-+ACPI tables provided by the system firmware; the ACPI core will then traverse
-+this table and map in the tables listed.
-+
-+The ACPI core will ignore any provided RSDT (Root System Description Table).
-+RSDTs have been deprecated and are ignored on arm64 since they only allow
-+for 32-bit addresses.
-+
-+Further, the ACPI core will only use the 64-bit address fields in the FADT
-+(Fixed ACPI Description Table). Any 32-bit address fields in the FADT will
-+be ignored on arm64.
-+
-+Hardware reduced mode (see Section 4.1 of the ACPI 5.1 specification) will
-+be enforced by the ACPI core on arm64. Doing so allows the ACPI core to
-+run less complex code since it no longer has to provide support for legacy
-+hardware from other architectures.
-+
-+For the ACPI core to operate properly, and in turn provide the information
-+the kernel needs to configure devices, it expects to find the following
-+tables (all section numbers refer to the ACPI 5.1 specfication):
-+
-+ -- RSDP (Root System Description Pointer), section 5.2.5
-+
-+ -- XSDT (eXtended System Description Table), section 5.2.8
-+
-+ -- FACS (Firmware ACPI Control Structure), section 5.2.10
-+
-+ -- FADT (Fixed ACPI Description Table), section 5.2.9
-+
-+ -- DSDT (Differentiated System Description Table), section
-+ 5.2.11.1
-+
-+ -- MADT (Multiple APIC Description Table), section 5.2.12
-+
-+ -- GTDT (Generic Timer Description Table), section 5.2.24
-+
-+ -- If PCI is supported, the MCFG (Memory mapped ConFiGuration
-+ Table), section 5.2.6, specifically Table 5-31.
-+
-+If the above tables are not all present, the kernel may or may not be
-+able to boot properly since it may not be able to configure all of the
-+devices available.
-+
-+
-+ACPI Detection
-+--------------
-+Drivers should determine their probe() type by checking for a null
-+value for ACPI_HANDLE, or checking .of_node, or other information in
-+the device structure. This is detailed further in the "Driver
-+Recommendations" section.
-+
-+In non-driver code, if the presence of ACPI needs to be detected at
-+runtime, then check the value of acpi_disabled. If CONFIG_ACPI is not
-+set, acpi_disabled will always be 1.
-+
-+
-+Device Enumeration
-+------------------
-+Device descriptions in ACPI should use standard recognized ACPI interfaces.
-+These can contain less information than is typically provided via a Device
-+Tree description for the same device. This is also one of the reasons that
-+ACPI can be useful -- the driver takes into account that it may have less
-+detailed information about the device and uses sensible defaults instead.
-+If done properly in the driver, the hardware can change and improve over
-+time without the driver having to change at all.
-+
-+Clocks provide an excellent example. In DT, clocks need to be specified
-+and the drivers need to take them into account. In ACPI, the assumption
-+is that UEFI will leave the device in a reasonable default state, including
-+any clock settings. If for some reason the driver needs to change a clock
-+value, this can be done in an ACPI method; all the driver needs to do is
-+invoke the method and not concern itself with what the method needs to do
-+to change the clock. Changing the hardware can then take place over time
-+by changing what the ACPI method does, and not the driver.
-+
-+ACPI drivers should only look at one specific ASL object -- the _DSD object
-+-- for device driver parameters (known in DT as "bindings", or "Device
-+Properties" in ACPI). Not all DT bindings will be recognized. The UEFI
-+Forum provides a mechanism for registering such bindings [URL TBD by ASWG]
-+so that they may be used on any operating system supporting ACPI. Device
-+properties that have not been registered with the UEFI Forum should not be
-+used.
-+
-+Drivers should look for device properties in the _DSD object ONLY; the _DSD
-+object is described in the ACPI specification section 6.2.5, but more
-+specifically, use the _DSD Device Properties UUID:
-+
-+ -- UUID: daffd814-6eba-4d8c-8a91-bc9bbf4aa301
-+
-+ -- http://www.uefi.org/sites/default/files/resources/_DSD-device-properties-UUID.pdf)
-+
-+The kernel has an interface for looking up device properties in a manner
-+independent of whether DT or ACPI is being used and that interface should
-+be used; it can eliminate some duplication of code paths in driver probing
-+functions and discourage divergence between DT bindings and ACPI device
-+properties.
-+
-+ACPI tables are described with a formal language called ASL, the ACPI
-+Source Language (section 19 of the specification). This means that there
-+are always multiple ways to describe the same thing -- including device
-+properties. For example, device properties could use an ASL construct
-+that looks like this: Name(KEY0, "value0"). An ACPI device driver would
-+then retrieve the value of the property by evaluating the KEY0 object.
-+However, using Name() this way has multiple problems: (1) ACPI limits
-+names ("KEY0") to four characters unlike DT; (2) there is no industry
-+wide registry that maintains a list of names, minimzing re-use; (3)
-+there is also no registry for the definition of property values ("value0"),
-+again making re-use difficult; and (4) how does one maintain backward
-+compatibility as new hardware comes out? The _DSD method was created
-+to solve precisely these sorts of problems; Linux drivers should ALWAYS
-+use the _DSD method for device properties and nothing else.
-+
-+The _DSM object (ACPI Section 9.14.1) could also be used for conveying
-+device properties to a driver. Linux drivers should only expect it to
-+be used if _DSD cannot represent the data required, and there is no way
-+to create a new UUID for the _DSD object. Note that there is even less
-+regulation of the use of _DSM than there is of _DSD. Drivers that depend
-+on the contents of _DSM objects will be more difficult to maintain over
-+time because of this.
-+
-+The _DSD object is a very flexible mechanism in ACPI, as are the registered
-+Device Properties. This flexibility allows _DSD to cover more than just the
-+generic server case and care should be taken in device drivers not to expect
-+it to replicate highly specific embedded behaviour from DT.
-+
-+Both DT bindings and ACPI device properties for device drivers have review
-+processes. Use them. And, before creating new device properties, check to
-+be sure that they have not been defined before and either registered in the
-+Linux kernel documentation or the UEFI Forum. If the device drivers supports
-+ACPI and DT, please make sure the device properties are consistent in both
-+places.
-+
-+
-+Programmable Power Control Resources
-+------------------------------------
-+Programmable power control resources include such resources as voltage/current
-+providers (regulators) and clock sources.
-+
-+The kernel assumes that power control of these resources is represented with
-+Power Resource Objects (ACPI section 7.1). The ACPI core will then handle
-+correctly enabling and disabling resources as they are needed. In order to
-+get that to work, ACPI assumes each device has defined D-states and that these
-+can be controlled through the optional ACPI methods _PS0, _PS1, _PS2, and _PS3;
-+in ACPI, _PS0 is the method to invoke to turn a device full on, and _PS3 is for
-+turning a device full off.
-+
-+The kernel ACPI code will also assume that the _PS? methods follow the normal
-+ACPI rules for such methods:
-+
-+ -- If either _PS0 or _PS3 is implemented, then the other method must also
-+ be implemented.
-+
-+ -- If a device requires usage or setup of a power resource when on, the ASL
-+ should organize that it is allocated/enabled using the _PS0 method.
-+
-+ -- Resources allocated or enabled in the _PS0 method should be disabled
-+ or de-allocated in the _PS3 method.
-+
-+ -- Firmware will leave the resources in a reasonable state before handing
-+ over control to the kernel.
-+
-+Such code in _PS? methods will of course be very platform specific. But,
-+this allows the driver to abstract out the interface for operating the device
-+and avoid having to read special non-standard values from ACPI tables. Further,
-+abstracting the use of these resources allows the hardware to change over time
-+without requiring updates to the driver.
-+
-+
-+Clocks
-+------
-+ACPI makes the assumption that clocks are initialized by the firmware --
-+UEFI, in this case -- to some working value before control is handed over
-+to the kernel. This has implications for devices such as UARTs, or SoC
-+driven LCD displays, for example.
-+
-+When the kernel boots, the clock is assumed to be set to reasonable
-+working value. If for some reason the frequency needs to change -- e.g.,
-+throttling for power management -- the device driver should expect that
-+process to be abstracted out into some ACPI method that can be invoked
-+(please see the ACPI specification for further recommendations on standard
-+methods to be expected). If is not, there is no direct way for ACPI to
-+control the clocks.
-+
-+
-+Driver Recommendations
-+----------------------
-+DO NOT remove any DT handling when adding ACPI support for a driver. The
-+same device may be used on many different systems.
-+
-+DO try to structure the driver so that it is data driven. That is, set up
-+a struct containing internal per-device state based on defaults and whatever
-+else must be discovered by the driver probe function. Then, have the rest
-+of the driver operate off of the contents of that struct. Doing so should
-+allow most divergence between ACPI and DT functionality to be kept local to
-+the probe function instead of being scattered throughout the driver. For
-+example:
-+
-+static int device_probe_dt(struct platform_device *pdev)
-+{
-+ /* DT specific functionality */
-+ ...
-+}
-+
-+static int device_probe_acpi(struct platform_device *pdev)
-+{
-+ /* ACPI specific functionality */
-+ ...
-+}
-+
-+static int device_probe(stuct platform_device *pdev)
-+{
-+ ...
-+ struct device_node node = pdev->dev.of_node;
-+ ...
-+
-+ if (node)
-+ ret = device_probe_dt(pdev);
-+ else if (ACPI_HANDLE(&pdev->dev))
-+ ret = device_probe_acpi(pdev);
-+ else
-+ /* other initialization */
-+ ...
-+ /* Continue with any generic probe operations */
-+ ...
-+}
-+
-+DO keep the MODULE_DEVICE_TABLE entries together in the driver to make it
-+clear the different names the driver is probed for, both from DT and from
-+ACPI:
-+
-+static struct of_device_id virtio_mmio_match[] = {
-+ { .compatible = "virtio,mmio", },
-+ { }
-+};
-+MODULE_DEVICE_TABLE(of, virtio_mmio_match);
-+
-+static const struct acpi_device_id virtio_mmio_acpi_match[] = {
-+ { "LNRO0005", },
-+ { }
-+};
-+MODULE_DEVICE_TABLE(acpi, virtio_mmio_acpi_match);
-+
-+
-+ASWG
-+----
-+The following areas are not yet fully defined for ARM in the 5.1 version
-+of the ACPI specification and are expected to be worked through in the
-+UEFI ACPI Specification Working Group (ASWG):
-+
-+ -- ACPI based CPU topology
-+ -- ACPI based Power management
-+ -- CPU idle control based on PSCI
-+ -- CPU performance control (CPPC)
-+ -- ACPI based SMMU
-+ -- ITS support for GIC in MADT
-+
-+Participation in this group is open to all UEFI members. Please see
-+http://www.uefi.org/workinggroup for details on group membership.
-+
-+It is the intent of the ARMv8 ACPI kernel code to follow the ACPI specification
-+as closely as possible, and to only implement functionality that complies with
-+the released standards from UEFI ASWG. As a practical matter, there will be
-+vendors that provide bad ACPI tables or violate the standards in some way.
-+If this is because of errors, quirks and fixups may be necessary, but will
-+be avoided if possible. If there are features missing from ACPI that preclude
-+it from being used on a platform, ECRs (Engineering Change Requests) should be
-+submitted to ASWG and go through the normal approval process; for those that
-+are not UEFI members, many other members of the Linux community are and would
-+likely be willing to assist in submitting ECRs.
-diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
-index 4df73da..4adfd50 100644
---- a/Documentation/kernel-parameters.txt
-+++ b/Documentation/kernel-parameters.txt
-@@ -165,7 +165,7 @@ multipliers 'Kilo', 'Mega', and 'Giga', equalling 2^10, 2^20, and 2^30
- bytes respectively. Such letter suffixes can also be entirely omitted.
-
-
-- acpi= [HW,ACPI,X86]
-+ acpi= [HW,ACPI,X86,ARM64]
- Advanced Configuration and Power Interface
- Format: { force | off | strict | noirq | rsdt }
- force -- enable ACPI if default was off
-@@ -175,6 +175,7 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
- strictly ACPI specification compliant.
- rsdt -- prefer RSDT over (default) XSDT
- copy_dsdt -- copy DSDT to memory
-+ For ARM64, ONLY "acpi=off" or "acpi=force" are available
-
- See also Documentation/power/runtime_pm.txt, pci=noacpi
-
-diff --git a/arch/arm/kvm/mmu.c b/arch/arm/kvm/mmu.c
-index 1dc9778..0b88d36 100644
---- a/arch/arm/kvm/mmu.c
-+++ b/arch/arm/kvm/mmu.c
-@@ -1315,6 +1315,10 @@ int kvm_arch_prepare_memory_region(struct kvm *kvm,
- (KVM_PHYS_SIZE >> PAGE_SHIFT))
- return -EFAULT;
-
-+ spin_lock(&kvm->mmu_lock);
-+ stage2_flush_memslot(kvm, memslot);
-+ spin_unlock(&kvm->mmu_lock);
-+
- /*
- * A memory region could potentially cover multiple VMAs, and any holes
- * between them, so iterate over all of them to find out if we can map
-diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
-index b1f9a20..d60e537 100644
---- a/arch/arm64/Kconfig
-+++ b/arch/arm64/Kconfig
-@@ -5,6 +5,7 @@ config ARM64
- select ARCH_HAS_GCOV_PROFILE_ALL
- select ARCH_HAS_SG_CHAIN
- select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
-+ select ACPI_REDUCED_HARDWARE_ONLY if ACPI
- select ARCH_USE_CMPXCHG_LOCKREF
- select ARCH_SUPPORTS_ATOMIC_RMW
- select ARCH_WANT_OPTIONAL_GPIOLIB
-@@ -193,6 +194,9 @@ config PCI_DOMAINS_GENERIC
- config PCI_SYSCALL
- def_bool PCI
-
-+config PCI_MMCONFIG
-+ def_bool y if PCI && ACPI
-+
- source "drivers/pci/Kconfig"
- source "drivers/pci/pcie/Kconfig"
- source "drivers/pci/hotplug/Kconfig"
-@@ -384,6 +388,9 @@ config SMP
-
- If you don't know what to do here, say N.
-
-+config ARM_PARKING_PROTOCOL
-+ def_bool y if SMP
-+
- config SCHED_MC
- bool "Multi-core scheduler support"
- depends on SMP
-@@ -646,6 +653,8 @@ source "drivers/Kconfig"
-
- source "drivers/firmware/Kconfig"
-
-+source "drivers/acpi/Kconfig"
-+
- source "fs/Kconfig"
-
- source "arch/arm64/kvm/Kconfig"
-diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile
-index 1c43cec..ab3b0b1 100644
---- a/arch/arm64/Makefile
-+++ b/arch/arm64/Makefile
-@@ -49,6 +49,7 @@ core-$(CONFIG_NET) += arch/arm64/net/
- core-$(CONFIG_KVM) += arch/arm64/kvm/
- core-$(CONFIG_XEN) += arch/arm64/xen/
- core-$(CONFIG_CRYPTO) += arch/arm64/crypto/
-+drivers-$(CONFIG_PCI) += arch/arm64/pci/
- libs-y := arch/arm64/lib/ $(libs-y)
- libs-y += $(LIBGCC)
- libs-$(CONFIG_EFI_STUB) += drivers/firmware/efi/libstub/
-diff --git a/arch/arm64/include/asm/acenv.h b/arch/arm64/include/asm/acenv.h
-new file mode 100644
-index 0000000..b49166f
---- /dev/null
-+++ b/arch/arm64/include/asm/acenv.h
-@@ -0,0 +1,18 @@
-+/*
-+ * ARM64 specific ACPICA environments and implementation
-+ *
-+ * Copyright (C) 2014, Linaro Ltd.
-+ * Author: Hanjun Guo <hanjun.guo at linaro.org>
-+ * Author: Graeme Gregory <graeme.gregory at linaro.org>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#ifndef _ASM_ACENV_H
-+#define _ASM_ACENV_H
-+
-+/* It is required unconditionally by ACPI core, update it when needed. */
-+
-+#endif /* _ASM_ACENV_H */
-diff --git a/arch/arm64/include/asm/acpi.h b/arch/arm64/include/asm/acpi.h
-new file mode 100644
-index 0000000..6e692f4
---- /dev/null
-+++ b/arch/arm64/include/asm/acpi.h
-@@ -0,0 +1,102 @@
-+/*
-+ * Copyright (C) 2013-2014, Linaro Ltd.
-+ * Author: Al Stone <al.stone at linaro.org>
-+ * Author: Graeme Gregory <graeme.gregory at linaro.org>
-+ * Author: Hanjun Guo <hanjun.guo at linaro.org>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation;
-+ */
-+
-+#ifndef _ASM_ACPI_H
-+#define _ASM_ACPI_H
-+
-+#include <asm/smp_plat.h>
-+
-+/* Basic configuration for ACPI */
-+#ifdef CONFIG_ACPI
-+#define acpi_strict 1 /* No out-of-spec workarounds on ARM64 */
-+extern int acpi_disabled;
-+extern int acpi_noirq;
-+extern int acpi_pci_disabled;
-+
-+/* 1 to indicate PSCI 0.2+ is implemented */
-+static inline bool acpi_psci_present(void)
-+{
-+ return acpi_gbl_FADT.arm_boot_flags & ACPI_FADT_PSCI_COMPLIANT;
-+}
-+
-+/* 1 to indicate HVC must be used instead of SMC as the PSCI conduit */
-+static inline bool acpi_psci_use_hvc(void)
-+{
-+ return acpi_gbl_FADT.arm_boot_flags & ACPI_FADT_PSCI_USE_HVC;
-+}
-+
-+static inline void disable_acpi(void)
-+{
-+ acpi_disabled = 1;
-+ acpi_pci_disabled = 1;
-+ acpi_noirq = 1;
-+}
-+
-+static inline void enable_acpi(void)
-+{
-+ acpi_disabled = 0;
-+ acpi_pci_disabled = 0;
-+ acpi_noirq = 0;
-+}
-+
-+/* MPIDR value provided in GICC structure is 64 bits, but the
-+ * existing apic_id (CPU hardware ID) using in acpi processor
-+ * driver is 32-bit, to conform to the same datatype we need
-+ * to repack the GICC structure MPIDR.
-+ *
-+ * Only 32 bits of MPIDR are used:
-+ *
-+ * Bits [0:7] Aff0;
-+ * Bits [8:15] Aff1;
-+ * Bits [16:23] Aff2;
-+ * Bits [32:39] Aff3;
-+ */
-+static inline u32 pack_mpidr(u64 mpidr)
-+{
-+ return (u32) ((mpidr & 0xff00000000) >> 8) | mpidr;
-+}
-+
-+/*
-+ * The ACPI processor driver for ACPI core code needs this macro
-+ * to find out this cpu was already mapped (mapping from CPU hardware
-+ * ID to CPU logical ID) or not.
-+ *
-+ * cpu_logical_map(cpu) is the mapping of MPIDR and the logical cpu,
-+ * and MPIDR is the cpu hardware ID we needed to pack.
-+ */
-+#define cpu_physical_id(cpu) pack_mpidr(cpu_logical_map(cpu))
-+
-+/*
-+ * It's used from ACPI core in kdump to boot UP system with SMP kernel,
-+ * with this check the ACPI core will not override the CPU index
-+ * obtained from GICC with 0 and not print some error message as well.
-+ * Since MADT must provide at least one GICC structure for GIC
-+ * initialization, CPU will be always available in MADT on ARM64.
-+ */
-+static inline bool acpi_has_cpu_in_madt(void)
-+{
-+ return true;
-+}
-+
-+static inline void arch_fix_phys_package_id(int num, u32 slot) { }
-+void __init acpi_smp_init_cpus(void);
-+
-+extern int acpi_get_cpu_parked_address(int cpu, u64 *addr);
-+
-+#else
-+static inline void disable_acpi(void) { }
-+static inline bool acpi_psci_present(void) { return false; }
-+static inline bool acpi_psci_use_hvc(void) { return false; }
-+static inline void acpi_smp_init_cpus(void) { }
-+static inline int acpi_get_cpu_parked_address(int cpu, u64 *addr) { return -EOPNOTSUPP; }
-+#endif /* CONFIG_ACPI */
-+
-+#endif /*_ASM_ACPI_H*/
-diff --git a/arch/arm64/include/asm/cpu_ops.h b/arch/arm64/include/asm/cpu_ops.h
-index 6f8e2ef..978f567 100644
---- a/arch/arm64/include/asm/cpu_ops.h
-+++ b/arch/arm64/include/asm/cpu_ops.h
-@@ -64,6 +64,7 @@ struct cpu_operations {
- };
-
- extern const struct cpu_operations *cpu_ops[NR_CPUS];
-+const struct cpu_operations *cpu_get_ops(const char *name);
- int __init cpu_read_ops(struct device_node *dn, int cpu);
- void __init cpu_read_bootcpu_ops(void);
-
-diff --git a/arch/arm64/include/asm/elf.h b/arch/arm64/include/asm/elf.h
-index 1f65be3..c0f89a0 100644
---- a/arch/arm64/include/asm/elf.h
-+++ b/arch/arm64/include/asm/elf.h
-@@ -114,7 +114,8 @@ typedef struct user_fpsimd_state elf_fpregset_t;
- */
- #define elf_check_arch(x) ((x)->e_machine == EM_AARCH64)
-
--#define elf_read_implies_exec(ex,stk) (stk != EXSTACK_DISABLE_X)
-+#define elf_read_implies_exec(ex,stk) (test_thread_flag(TIF_32BIT) \
-+ ? (stk == EXSTACK_ENABLE_X) : 0)
-
- #define CORE_DUMP_USE_REGSET
- #define ELF_EXEC_PAGESIZE PAGE_SIZE
-diff --git a/arch/arm64/include/asm/pci.h b/arch/arm64/include/asm/pci.h
-index 872ba93..2f287a6 100644
---- a/arch/arm64/include/asm/pci.h
-+++ b/arch/arm64/include/asm/pci.h
-@@ -33,5 +33,56 @@ static inline int pci_proc_domain(struct pci_bus *bus)
- }
- #endif /* CONFIG_PCI */
-
-+/* "PCI MMCONFIG %04x [bus %02x-%02x]" */
-+#define PCI_MMCFG_RESOURCE_NAME_LEN (22 + 4 + 2 + 2)
-+
-+#define PCI_MMCFG_BUS_OFFSET(bus) ((bus) << 20)
-+
-+struct acpi_device;
-+
-+struct pci_sysdata {
-+ int domain; /* PCI domain */
-+ int node; /* NUMA node */
-+ struct acpi_device *companion; /* ACPI companion device */
-+ void *iommu; /* IOMMU private data */
-+};
-+
-+struct acpi_pci_root;
-+struct pci_mmcfg_region;
-+
-+typedef int (*acpi_mcfg_fixup_t)(struct acpi_pci_root *root,
-+ struct pci_mmcfg_region *cfg);
-+
-+struct pci_mmcfg_region {
-+ struct list_head list;
-+ struct resource res;
-+ int (*read)(struct pci_mmcfg_region *cfg, unsigned int bus,
-+ unsigned int devfn, int reg, int len, u32 *value);
-+ int (*write)(struct pci_mmcfg_region *cfg, unsigned int bus,
-+ unsigned int devfn, int reg, int len, u32 value);
-+ acpi_mcfg_fixup_t fixup;
-+ void *data;
-+ u64 address;
-+ char __iomem *virt;
-+ u16 segment;
-+ u8 start_bus;
-+ u8 end_bus;
-+ char name[PCI_MMCFG_RESOURCE_NAME_LEN];
-+};
-+
-+struct acpi_mcfg_fixup {
-+ char oem_id[7];
-+ char oem_table_id[9];
-+ acpi_mcfg_fixup_t hook;
-+};
-+
-+/* Designate a routine to fix up buggy MCFG */
-+#define DECLARE_ACPI_MCFG_FIXUP(oem_id, table_id, hook) \
-+ static const struct acpi_mcfg_fixup __acpi_fixup_##hook __used \
-+ __attribute__((__section__(".acpi_fixup_mcfg"), aligned((sizeof(void *))))) \
-+ = { {oem_id}, {table_id}, hook };
-+
-+extern struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus);
-+
- #endif /* __KERNEL__ */
- #endif /* __ASM_PCI_H */
-diff --git a/arch/arm64/include/asm/psci.h b/arch/arm64/include/asm/psci.h
-index e5312ea..2454bc5 100644
---- a/arch/arm64/include/asm/psci.h
-+++ b/arch/arm64/include/asm/psci.h
-@@ -14,6 +14,7 @@
- #ifndef __ASM_PSCI_H
- #define __ASM_PSCI_H
-
--int psci_init(void);
-+int psci_dt_init(void);
-+int psci_acpi_init(void);
-
- #endif /* __ASM_PSCI_H */
-diff --git a/arch/arm64/include/asm/smp.h b/arch/arm64/include/asm/smp.h
-index 780f82c..3411561 100644
---- a/arch/arm64/include/asm/smp.h
-+++ b/arch/arm64/include/asm/smp.h
-@@ -39,9 +39,10 @@ extern void show_ipi_list(struct seq_file *p, int prec);
- extern void handle_IPI(int ipinr, struct pt_regs *regs);
-
- /*
-- * Setup the set of possible CPUs (via set_cpu_possible)
-+ * Discover the set of possible CPUs and determine their
-+ * SMP operations.
- */
--extern void smp_init_cpus(void);
-+extern void of_smp_init_cpus(void);
-
- /*
- * Provide a function to raise an IPI cross call on CPUs in callmap.
-@@ -51,6 +52,11 @@ extern void set_smp_cross_call(void (*)(const struct cpumask *, unsigned int));
- extern void (*__smp_cross_call)(const struct cpumask *, unsigned int);
-
- /*
-+ * Provide a function to signal a parked secondary CPU.
-+ */
-+extern void set_smp_boot_wakeup_call(void (*)(int cpu));
-+
-+/*
- * Called from the secondary holding pen, this is the secondary CPU entry point.
- */
- asmlinkage void secondary_start_kernel(void);
-diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
-index eaa77ed..63ffe3c 100644
---- a/arch/arm64/kernel/Makefile
-+++ b/arch/arm64/kernel/Makefile
-@@ -23,7 +23,8 @@ arm64-obj-$(CONFIG_COMPAT) += sys32.o kuser32.o signal32.o \
- ../../arm/kernel/opcodes.o
- arm64-obj-$(CONFIG_FUNCTION_TRACER) += ftrace.o entry-ftrace.o
- arm64-obj-$(CONFIG_MODULES) += arm64ksyms.o module.o
--arm64-obj-$(CONFIG_SMP) += smp.o smp_spin_table.o topology.o
-+arm64-obj-$(CONFIG_SMP) += smp.o smp_spin_table.o topology.o \
-+ smp_parking_protocol.o
- arm64-obj-$(CONFIG_PERF_EVENTS) += perf_regs.o
- arm64-obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o
- arm64-obj-$(CONFIG_HAVE_HW_BREAKPOINT) += hw_breakpoint.o
-@@ -33,6 +34,7 @@ arm64-obj-$(CONFIG_JUMP_LABEL) += jump_label.o
- arm64-obj-$(CONFIG_KGDB) += kgdb.o
- arm64-obj-$(CONFIG_EFI) += efi.o efi-stub.o efi-entry.o
- arm64-obj-$(CONFIG_PCI) += pci.o
-+arm64-obj-$(CONFIG_ACPI) += acpi.o
- arm64-obj-$(CONFIG_ARMV8_DEPRECATED) += armv8_deprecated.o
-
- obj-y += $(arm64-obj-y) vdso/
-diff --git a/arch/arm64/kernel/acpi.c b/arch/arm64/kernel/acpi.c
-new file mode 100644
-index 0000000..06a96be
---- /dev/null
-+++ b/arch/arm64/kernel/acpi.c
-@@ -0,0 +1,398 @@
-+/*
-+ * ARM64 Specific Low-Level ACPI Boot Support
-+ *
-+ * Copyright (C) 2013-2014, Linaro Ltd.
-+ * Author: Al Stone <al.stone at linaro.org>
-+ * Author: Graeme Gregory <graeme.gregory at linaro.org>
-+ * Author: Hanjun Guo <hanjun.guo at linaro.org>
-+ * Author: Tomasz Nowicki <tomasz.nowicki at linaro.org>
-+ * Author: Naresh Bhat <naresh.bhat at linaro.org>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#define pr_fmt(fmt) "ACPI: " fmt
-+
-+#include <linux/init.h>
-+#include <linux/acpi.h>
-+#include <linux/cpumask.h>
-+#include <linux/memblock.h>
-+#include <linux/irq.h>
-+#include <linux/irqdomain.h>
-+#include <linux/bootmem.h>
-+#include <linux/smp.h>
-+#include <linux/irqchip/arm-gic-acpi.h>
-+
-+#include <asm/cputype.h>
-+#include <asm/cpu_ops.h>
-+
-+int acpi_noirq; /* skip ACPI IRQ initialization */
-+int acpi_disabled;
-+EXPORT_SYMBOL(acpi_disabled);
-+
-+int acpi_pci_disabled; /* skip ACPI PCI scan and IRQ initialization */
-+EXPORT_SYMBOL(acpi_pci_disabled);
-+
-+static int enabled_cpus; /* Processors (GICC) with enabled flag in MADT */
-+
-+static char *boot_method;
-+static u64 parked_address[NR_CPUS];
-+
-+/*
-+ * Since we're on ARM, the default interrupt routing model
-+ * clearly has to be GIC.
-+ */
-+enum acpi_irq_model_id acpi_irq_model = ACPI_IRQ_MODEL_GIC;
-+
-+/*
-+ * __acpi_map_table() will be called before page_init(), so early_ioremap()
-+ * or early_memremap() should be called here to for ACPI table mapping.
-+ */
-+char *__init __acpi_map_table(unsigned long phys, unsigned long size)
-+{
-+ if (!phys || !size)
-+ return NULL;
-+
-+ return early_memremap(phys, size);
-+}
-+
-+void __init __acpi_unmap_table(char *map, unsigned long size)
-+{
-+ if (!map || !size)
-+ return;
-+
-+ early_memunmap(map, size);
-+}
-+
-+/**
-+ * acpi_map_gic_cpu_interface - generates a logical cpu number
-+ * and map to MPIDR represented by GICC structure
-+ * @mpidr: CPU's hardware id to register, MPIDR represented in MADT
-+ * @enabled: this cpu is enabled or not
-+ *
-+ * Returns the logical cpu number which maps to MPIDR
-+ */
-+static int acpi_map_gic_cpu_interface(u64 mpidr, u64 parked_addr, u8 enabled)
-+{
-+ int cpu;
-+
-+ if (mpidr == INVALID_HWID) {
-+ pr_info("Skip MADT cpu entry with invalid MPIDR\n");
-+ return -EINVAL;
-+ }
-+
-+ total_cpus++;
-+ if (!enabled)
-+ return -EINVAL;
-+
-+ if (enabled_cpus >= NR_CPUS) {
-+ pr_warn("NR_CPUS limit of %d reached, Processor %d/0x%llx ignored.\n",
-+ NR_CPUS, total_cpus, mpidr);
-+ return -EINVAL;
-+ }
-+
-+ /* No need to check duplicate MPIDRs for the first CPU */
-+ if (enabled_cpus) {
-+ /*
-+ * Duplicate MPIDRs are a recipe for disaster. Scan
-+ * all initialized entries and check for
-+ * duplicates. If any is found just ignore the CPU.
-+ */
-+ for_each_possible_cpu(cpu) {
-+ if (cpu_logical_map(cpu) == mpidr) {
-+ pr_err("Firmware bug, duplicate CPU MPIDR: 0x%llx in MADT\n",
-+ mpidr);
-+ return -EINVAL;
-+ }
-+ }
-+
-+ /* allocate a logical cpu id for the new comer */
-+ cpu = cpumask_next_zero(-1, cpu_possible_mask);
-+ } else {
-+ /*
-+ * First GICC entry must be BSP as ACPI spec said
-+ * in section 5.2.12.15
-+ */
-+ if (cpu_logical_map(0) != mpidr) {
-+ pr_err("First GICC entry with MPIDR 0x%llx is not BSP\n",
-+ mpidr);
-+ return -EINVAL;
-+ }
-+
-+ /*
-+ * boot_cpu_init() already hold bit 0 in cpu_present_mask
-+ * for BSP, no need to allocate again.
-+ */
-+ cpu = 0;
-+ }
-+
-+ parked_address[cpu] = parked_addr;
-+
-+ /* CPU 0 was already initialized */
-+ if (cpu) {
-+ cpu_ops[cpu] = cpu_get_ops(boot_method);
-+ if (!cpu_ops[cpu])
-+ return -EINVAL;
-+
-+ if (cpu_ops[cpu]->cpu_init(NULL, cpu))
-+ return -EOPNOTSUPP;
-+
-+ /* map the logical cpu id to cpu MPIDR */
-+ cpu_logical_map(cpu) = mpidr;
-+
-+ set_cpu_possible(cpu, true);
-+ } else {
-+ /* get cpu0's ops, no need to return if ops is null */
-+ cpu_ops[0] = cpu_get_ops(boot_method);
-+ }
-+
-+ enabled_cpus++;
-+ return cpu;
-+}
-+
-+static int __init
-+acpi_parse_gic_cpu_interface(struct acpi_subtable_header *header,
-+ const unsigned long end)
-+{
-+ struct acpi_madt_generic_interrupt *processor;
-+
-+ processor = (struct acpi_madt_generic_interrupt *)header;
-+
-+ if (BAD_MADT_ENTRY(processor, end))
-+ return -EINVAL;
-+
-+ acpi_table_print_madt_entry(header);
-+
-+ acpi_map_gic_cpu_interface(processor->arm_mpidr & MPIDR_HWID_BITMASK,
-+ processor->parked_address, processor->flags & ACPI_MADT_ENABLED);
-+
-+ return 0;
-+}
-+
-+/* Parse GIC cpu interface entries in MADT for SMP init */
-+void __init acpi_smp_init_cpus(void)
-+{
-+ int count;
-+
-+ /*
-+ * do a partial walk of MADT to determine how many CPUs
-+ * we have including disabled CPUs, and get information
-+ * we need for SMP init
-+ */
-+ count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
-+ acpi_parse_gic_cpu_interface, 0);
-+
-+ if (!count) {
-+ pr_err("No GIC CPU interface entries present\n");
-+ return;
-+ } else if (count < 0) {
-+ pr_err("Error parsing GIC CPU interface entry\n");
-+ return;
-+ }
-+
-+ /* Make boot-up look pretty */
-+ pr_info("%d CPUs enabled, %d CPUs total\n", enabled_cpus, total_cpus);
-+}
-+
-+int acpi_gsi_to_irq(u32 gsi, unsigned int *irq)
-+{
-+ *irq = irq_find_mapping(NULL, gsi);
-+
-+ return 0;
-+}
-+EXPORT_SYMBOL_GPL(acpi_gsi_to_irq);
-+
-+/*
-+ * success: return IRQ number (>0)
-+ * failure: return =< 0
-+ */
-+int acpi_register_gsi(struct device *dev, u32 gsi, int trigger, int polarity)
-+{
-+ unsigned int irq;
-+ unsigned int irq_type;
-+
-+ /*
-+ * ACPI have no bindings to indicate SPI or PPI, so we
-+ * use different mappings from DT in ACPI.
-+ *
-+ * For FDT
-+ * PPI interrupt: in the range [0, 15];
-+ * SPI interrupt: in the range [0, 987];
-+ *
-+ * For ACPI, GSI should be unique so using
-+ * the hwirq directly for the mapping:
-+ * PPI interrupt: in the range [16, 31];
-+ * SPI interrupt: in the range [32, 1019];
-+ */
-+
-+ if (trigger == ACPI_EDGE_SENSITIVE &&
-+ polarity == ACPI_ACTIVE_LOW)
-+ irq_type = IRQ_TYPE_EDGE_FALLING;
-+ else if (trigger == ACPI_EDGE_SENSITIVE &&
-+ polarity == ACPI_ACTIVE_HIGH)
-+ irq_type = IRQ_TYPE_EDGE_RISING;
-+ else if (trigger == ACPI_LEVEL_SENSITIVE &&
-+ polarity == ACPI_ACTIVE_LOW)
-+ irq_type = IRQ_TYPE_LEVEL_LOW;
-+ else if (trigger == ACPI_LEVEL_SENSITIVE &&
-+ polarity == ACPI_ACTIVE_HIGH)
-+ irq_type = IRQ_TYPE_LEVEL_HIGH;
-+ else
-+ irq_type = IRQ_TYPE_NONE;
-+
-+ /*
-+ * Since only one GIC is supported in ACPI 5.0, we can
-+ * create mapping refer to the default domain
-+ */
-+ irq = irq_create_mapping(NULL, gsi);
-+ if (!irq)
-+ return irq;
-+
-+ /* Set irq type if specified and different than the current one */
-+ if (irq_type != IRQ_TYPE_NONE &&
-+ irq_type != irq_get_trigger_type(irq))
-+ irq_set_irq_type(irq, irq_type);
-+ return irq;
-+}
-+EXPORT_SYMBOL_GPL(acpi_register_gsi);
-+
-+void acpi_unregister_gsi(u32 gsi)
-+{
-+}
-+EXPORT_SYMBOL_GPL(acpi_unregister_gsi);
-+
-+static int __init acpi_parse_fadt(struct acpi_table_header *table)
-+{
-+ struct acpi_table_fadt *fadt = (struct acpi_table_fadt *)table;
-+
-+ /*
-+ * Revision in table header is the FADT Major revision,
-+ * and there is a minor revision of FADT which was introduced
-+ * by ACPI 5.1, we only deal with ACPI 5.1 or newer revision
-+ * to get arm boot flags, or we will disable ACPI.
-+ */
-+ if (table->revision > 5 ||
-+ (table->revision == 5 && fadt->minor_revision >= 1)) {
-+ /*
-+ * ACPI 5.1 only has two explicit methods to boot up SMP,
-+ * PSCI and Parking protocol, but the Parking protocol is
-+ * only specified for ARMv7 now, so make PSCI as the only
-+ * way for the SMP boot protocol before some updates for
-+ * the ACPI spec or the Parking protocol spec.
-+ */
-+ if (acpi_psci_present())
-+ boot_method = "psci";
-+ else if (IS_ENABLED(CONFIG_ARM_PARKING_PROTOCOL))
-+ boot_method = "parking-protocol";
-+
-+ if (!boot_method)
-+ pr_warn("No boot method, will not bring up secondary CPUs\n");
-+ return -EOPNOTSUPP;
-+ }
-+
-+ pr_warn("Unsupported FADT revision %d.%d, should be 5.1+, will disable ACPI\n",
-+ table->revision, fadt->minor_revision);
-+ disable_acpi();
-+
-+ return -EINVAL;
-+}
-+
-+/*
-+ * acpi_boot_table_init() called from setup_arch(), always.
-+ * 1. find RSDP and get its address, and then find XSDT
-+ * 2. extract all tables and checksums them all
-+ * 3. check ACPI FADT revisoin
-+ *
-+ * We can parse ACPI boot-time tables such as MADT after
-+ * this function is called.
-+ */
-+void __init acpi_boot_table_init(void)
-+{
-+ /* If acpi_disabled, bail out */
-+ if (acpi_disabled)
-+ return;
-+
-+ /* Initialize the ACPI boot-time table parser. */
-+ if (acpi_table_init()) {
-+ disable_acpi();
-+ return;
-+ }
-+
-+ if (acpi_table_parse(ACPI_SIG_FADT, acpi_parse_fadt))
-+ pr_err("Can't find FADT or error happened during parsing FADT\n");
-+}
-+
-+void __init acpi_gic_init(void)
-+{
-+ struct acpi_table_header *table;
-+ acpi_status status;
-+ acpi_size tbl_size;
-+ int err;
-+
-+ status = acpi_get_table_with_size(ACPI_SIG_MADT, 0, &table, &tbl_size);
-+ if (ACPI_FAILURE(status)) {
-+ const char *msg = acpi_format_exception(status);
-+
-+ pr_err("Failed to get MADT table, %s\n", msg);
-+ return;
-+ }
-+
-+ err = gic_v2_acpi_init(table);
-+ if (err)
-+ pr_err("Failed to initialize GIC IRQ controller");
-+
-+ early_acpi_os_unmap_memory((char *)table, tbl_size);
-+}
-+
-+/*
-+ * Parked Address in ACPI GIC structure will be used as the CPU
-+ * release address
-+ */
-+int acpi_get_cpu_parked_address(int cpu, u64 *addr)
-+{
-+ if (!addr || !parked_address[cpu])
-+ return -EINVAL;
-+
-+ *addr = parked_address[cpu];
-+
-+ return 0;
-+}
-+
-+static int __init parse_acpi(char *arg)
-+{
-+ if (!arg)
-+ return -EINVAL;
-+
-+ /* "acpi=off" disables both ACPI table parsing and interpreter */
-+ if (strcmp(arg, "off") == 0)
-+ disable_acpi();
-+ else if (strcmp(arg, "force") == 0) /* force ACPI to be enabled */
-+ enable_acpi();
-+ else
-+ return -EINVAL; /* Core will print when we return error */
-+
-+ return 0;
-+}
-+early_param("acpi", parse_acpi);
-+
-+int acpi_isa_irq_to_gsi(unsigned isa_irq, u32 *gsi)
-+{
-+ return -1;
-+}
-+
-+int acpi_register_ioapic(acpi_handle handle, u64 phys_addr, u32 gsi_base)
-+{
-+ /* TBD */
-+ return -EINVAL;
-+}
-+EXPORT_SYMBOL(acpi_register_ioapic);
-+
-+int acpi_unregister_ioapic(acpi_handle handle, u32 gsi_base)
-+{
-+ /* TBD */
-+ return -EINVAL;
-+}
-+EXPORT_SYMBOL(acpi_unregister_ioapic);
-+
-diff --git a/arch/arm64/kernel/cpu_ops.c b/arch/arm64/kernel/cpu_ops.c
-index cce9524..1d90f31 100644
---- a/arch/arm64/kernel/cpu_ops.c
-+++ b/arch/arm64/kernel/cpu_ops.c
-@@ -23,19 +23,23 @@
- #include <linux/string.h>
-
- extern const struct cpu_operations smp_spin_table_ops;
-+extern const struct cpu_operations smp_parking_protocol_ops;
- extern const struct cpu_operations cpu_psci_ops;
-
- const struct cpu_operations *cpu_ops[NR_CPUS];
-
--static const struct cpu_operations *supported_cpu_ops[] __initconst = {
-+static const struct cpu_operations *supported_cpu_ops[] = {
- #ifdef CONFIG_SMP
- &smp_spin_table_ops,
-+#ifdef CONFIG_ARM_PARKING_PROTOCOL
-+ &smp_parking_protocol_ops,
-+#endif
- #endif
- &cpu_psci_ops,
- NULL,
- };
-
--static const struct cpu_operations * __init cpu_get_ops(const char *name)
-+const struct cpu_operations *cpu_get_ops(const char *name)
- {
- const struct cpu_operations **ops = supported_cpu_ops;
-
-diff --git a/arch/arm64/kernel/efi.c b/arch/arm64/kernel/efi.c
-index 6fac253..f9de195 100644
---- a/arch/arm64/kernel/efi.c
-+++ b/arch/arm64/kernel/efi.c
-@@ -484,3 +484,40 @@ static int __init arm64_dmi_init(void)
- return 0;
- }
- core_initcall(arm64_dmi_init);
-+
-+/*
-+ * If nothing else is handling pm_power_off, use EFI
-+ *
-+ * When Guenter Roeck's power-off handler call chain patches land,
-+ * we just need to return true unconditionally.
-+ */
-+bool efi_poweroff_required(void)
-+{
-+ return pm_power_off == NULL;
-+}
-+
-+static int arm64_efi_restart(struct notifier_block *this,
-+ unsigned long mode, void *cmd)
-+{
-+ efi_reboot(reboot_mode, cmd);
-+ return NOTIFY_DONE;
-+}
-+
-+static struct notifier_block arm64_efi_restart_nb = {
-+ .notifier_call = arm64_efi_restart,
-+ .priority = INT_MAX,
-+};
-+
-+static int __init arm64_register_efi_restart(void)
-+{
-+ int ret = 0;
-+
-+ if (efi_enabled(EFI_RUNTIME_SERVICES)) {
-+ ret = register_restart_handler(&arm64_efi_restart_nb);
-+ if (ret)
-+ pr_err("%s: cannot register restart handler, %d\n",
-+ __func__, ret);
-+ }
-+ return ret;
-+}
-+late_initcall(arm64_register_efi_restart);
-diff --git a/arch/arm64/kernel/pci.c b/arch/arm64/kernel/pci.c
-index ce5836c..978cd21 100644
---- a/arch/arm64/kernel/pci.c
-+++ b/arch/arm64/kernel/pci.c
-@@ -17,6 +17,8 @@
- #include <linux/of_pci.h>
- #include <linux/of_platform.h>
- #include <linux/slab.h>
-+#include <linux/acpi.h>
-+#include <linux/pci-acpi.h>
-
- #include <asm/pci-bridge.h>
-
-@@ -37,34 +39,99 @@ resource_size_t pcibios_align_resource(void *data, const struct resource *res,
- return res->start;
- }
-
-+int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
-+{
-+ struct pci_sysdata *sd;
-+
-+ if (!acpi_disabled) {
-+ sd = bridge->bus->sysdata;
-+ ACPI_COMPANION_SET(&bridge->dev, sd->companion);
-+ }
-+ return 0;
-+}
-+
- /*
- * Try to assign the IRQ number from DT when adding a new device
- */
- int pcibios_add_device(struct pci_dev *dev)
- {
-- dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
-+ if (acpi_disabled)
-+ dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
-
- return 0;
- }
-
-+void pcibios_add_bus(struct pci_bus *bus)
-+{
-+ if (!acpi_disabled)
-+ acpi_pci_add_bus(bus);
-+}
-
--#ifdef CONFIG_PCI_DOMAINS_GENERIC
--static bool dt_domain_found = false;
-+void pcibios_remove_bus(struct pci_bus *bus)
-+{
-+ if (!acpi_disabled)
-+ acpi_pci_remove_bus(bus);
-+}
-+
-+int pcibios_enable_irq(struct pci_dev *dev)
-+{
-+ if (!acpi_disabled && !pci_dev_msi_enabled(dev))
-+ acpi_pci_irq_enable(dev);
-+ return 0;
-+}
-+
-+int pcibios_disable_irq(struct pci_dev *dev)
-+{
-+ if (!acpi_disabled && !pci_dev_msi_enabled(dev))
-+ acpi_pci_irq_disable(dev);
-+ return 0;
-+}
-
-+int pcibios_enable_device(struct pci_dev *dev, int bars)
-+{
-+ int err;
-+
-+ err = pci_enable_resources(dev, bars);
-+ if (err < 0)
-+ return err;
-+
-+ if (!pci_dev_msi_enabled(dev))
-+ return pcibios_enable_irq(dev);
-+ return 0;
-+}
-+
-+#ifdef CONFIG_PCI_DOMAINS_GENERIC
- void pci_bus_assign_domain_nr(struct pci_bus *bus, struct device *parent)
- {
-- int domain = of_get_pci_domain_nr(parent->of_node);
--
-- if (domain >= 0) {
-- dt_domain_found = true;
-- } else if (dt_domain_found == true) {
-- dev_err(parent, "Node %s is missing \"linux,pci-domain\" property in DT\n",
-- parent->of_node->full_name);
-- return;
-- } else {
-- domain = pci_get_new_domain_nr();
-- }
-+ int domain = -1;
-
-- bus->domain_nr = domain;
-+ if (acpi_disabled)
-+ domain = of_get_pci_domain_nr(parent->of_node);
-+ else {
-+ struct pci_sysdata *sd = bus->sysdata;
-+
-+ domain = sd->domain;
-+ }
-+ if (domain >= 0)
-+ bus->domain_nr = domain;
- }
- #endif
-+
-+static int __init pcibios_assign_resources(void)
-+{
-+ struct pci_bus *root_bus;
-+
-+ if (acpi_disabled)
-+ return 0;
-+
-+ list_for_each_entry(root_bus, &pci_root_buses, node) {
-+ pcibios_resource_survey_bus(root_bus);
-+ pci_assign_unassigned_root_bus_resources(root_bus);
-+ }
-+ return 0;
-+}
-+/*
-+ * fs_initcall comes after subsys_initcall, so we know acpi scan
-+ * has run.
-+ */
-+fs_initcall(pcibios_assign_resources);
-diff --git a/arch/arm64/kernel/psci.c b/arch/arm64/kernel/psci.c
-index f1dbca7..dbb3945 100644
---- a/arch/arm64/kernel/psci.c
-+++ b/arch/arm64/kernel/psci.c
-@@ -15,6 +15,7 @@
-
- #define pr_fmt(fmt) "psci: " fmt
-
-+#include <linux/acpi.h>
- #include <linux/init.h>
- #include <linux/of.h>
- #include <linux/smp.h>
-@@ -24,6 +25,7 @@
- #include <linux/slab.h>
- #include <uapi/linux/psci.h>
-
-+#include <asm/acpi.h>
- #include <asm/compiler.h>
- #include <asm/cpu_ops.h>
- #include <asm/errno.h>
-@@ -304,6 +306,33 @@ static void psci_sys_poweroff(void)
- invoke_psci_fn(PSCI_0_2_FN_SYSTEM_OFF, 0, 0, 0);
- }
-
-+static void psci_0_2_set_functions(void)
-+{
-+ pr_info("Using standard PSCI v0.2 function IDs\n");
-+ psci_function_id[PSCI_FN_CPU_SUSPEND] = PSCI_0_2_FN64_CPU_SUSPEND;
-+ psci_ops.cpu_suspend = psci_cpu_suspend;
-+
-+ psci_function_id[PSCI_FN_CPU_OFF] = PSCI_0_2_FN_CPU_OFF;
-+ psci_ops.cpu_off = psci_cpu_off;
-+
-+ psci_function_id[PSCI_FN_CPU_ON] = PSCI_0_2_FN64_CPU_ON;
-+ psci_ops.cpu_on = psci_cpu_on;
-+
-+ psci_function_id[PSCI_FN_MIGRATE] = PSCI_0_2_FN64_MIGRATE;
-+ psci_ops.migrate = psci_migrate;
-+
-+ psci_function_id[PSCI_FN_AFFINITY_INFO] = PSCI_0_2_FN64_AFFINITY_INFO;
-+ psci_ops.affinity_info = psci_affinity_info;
-+
-+ psci_function_id[PSCI_FN_MIGRATE_INFO_TYPE] =
-+ PSCI_0_2_FN_MIGRATE_INFO_TYPE;
-+ psci_ops.migrate_info_type = psci_migrate_info_type;
-+
-+ arm_pm_restart = psci_sys_reset;
-+
-+ pm_power_off = psci_sys_poweroff;
-+}
-+
- /*
- * PSCI Function IDs for v0.2+ are well defined so use
- * standard values.
-@@ -337,29 +366,7 @@ static int __init psci_0_2_init(struct device_node *np)
- }
- }
-
-- pr_info("Using standard PSCI v0.2 function IDs\n");
-- psci_function_id[PSCI_FN_CPU_SUSPEND] = PSCI_0_2_FN64_CPU_SUSPEND;
-- psci_ops.cpu_suspend = psci_cpu_suspend;
--
-- psci_function_id[PSCI_FN_CPU_OFF] = PSCI_0_2_FN_CPU_OFF;
-- psci_ops.cpu_off = psci_cpu_off;
--
-- psci_function_id[PSCI_FN_CPU_ON] = PSCI_0_2_FN64_CPU_ON;
-- psci_ops.cpu_on = psci_cpu_on;
--
-- psci_function_id[PSCI_FN_MIGRATE] = PSCI_0_2_FN64_MIGRATE;
-- psci_ops.migrate = psci_migrate;
--
-- psci_function_id[PSCI_FN_AFFINITY_INFO] = PSCI_0_2_FN64_AFFINITY_INFO;
-- psci_ops.affinity_info = psci_affinity_info;
--
-- psci_function_id[PSCI_FN_MIGRATE_INFO_TYPE] =
-- PSCI_0_2_FN_MIGRATE_INFO_TYPE;
-- psci_ops.migrate_info_type = psci_migrate_info_type;
--
-- arm_pm_restart = psci_sys_reset;
--
-- pm_power_off = psci_sys_poweroff;
-+ psci_0_2_set_functions();
-
- out_put_node:
- of_node_put(np);
-@@ -412,7 +419,7 @@ static const struct of_device_id psci_of_match[] __initconst = {
- {},
- };
-
--int __init psci_init(void)
-+int __init psci_dt_init(void)
- {
- struct device_node *np;
- const struct of_device_id *matched_np;
-@@ -427,6 +434,29 @@ int __init psci_init(void)
- return init_fn(np);
- }
-
-+/*
-+ * We use PSCI 0.2+ when ACPI is deployed on ARM64 and it's
-+ * explicitly clarified in SBBR
-+ */
-+int __init psci_acpi_init(void)
-+{
-+ if (!acpi_psci_present()) {
-+ pr_info("is not implemented in ACPI.\n");
-+ return -EOPNOTSUPP;
-+ }
-+
-+ pr_info("probing for conduit method from ACPI.\n");
-+
-+ if (acpi_psci_use_hvc())
-+ invoke_psci_fn = __invoke_psci_fn_hvc;
-+ else
-+ invoke_psci_fn = __invoke_psci_fn_smc;
-+
-+ psci_0_2_set_functions();
-+
-+ return 0;
-+}
-+
- #ifdef CONFIG_SMP
-
- static int __init cpu_psci_cpu_init(struct device_node *dn, unsigned int cpu)
-diff --git a/arch/arm64/kernel/setup.c b/arch/arm64/kernel/setup.c
-index 20fe2932ad0c..cf4ab5661088 100644
---- a/arch/arm64/kernel/setup.c
-+++ b/arch/arm64/kernel/setup.c
-@@ -43,6 +43,7 @@
- #include <linux/of_fdt.h>
- #include <linux/of_platform.h>
- #include <linux/efi.h>
-+#include <linux/acpi.h>
- #include <linux/personality.h>
-
- #include <asm/fixmap.h>
-@@ -61,6 +62,7 @@
- #include <asm/memblock.h>
- #include <asm/psci.h>
- #include <asm/efi.h>
-+#include <asm/acpi.h>
-
- unsigned int processor_id;
- EXPORT_SYMBOL(processor_id);
-@@ -387,6 +389,8 @@ void __init setup_arch(char **cmdline_p)
- early_fixmap_init();
- early_ioremap_init();
-
-+ disable_acpi();
-+
- parse_early_param();
-
- /*
-@@ -398,19 +402,29 @@ void __init setup_arch(char **cmdline_p)
- efi_init();
- arm64_memblock_init();
-
-+ /* Parse the ACPI tables for possible boot-time configuration */
-+ acpi_boot_table_init();
-+
- paging_init();
- request_standard_resources();
-
- efi_idmap_init();
- early_ioremap_reset();
-
-- unflatten_device_tree();
--
-- psci_init();
-+ if (acpi_disabled) {
-+ unflatten_device_tree();
-+ psci_dt_init();
-+ cpu_read_bootcpu_ops();
-+#ifdef CONFIG_SMP
-+ of_smp_init_cpus();
-+#endif
-+ } else {
-+ psci_acpi_init();
-+ acpi_smp_init_cpus();
-+ }
-
- cpu_read_bootcpu_ops();
- #ifdef CONFIG_SMP
-- smp_init_cpus();
- smp_build_mpidr_hash();
- #endif
-
-@@ -565,3 +579,25 @@ const struct seq_operations cpuinfo_op = {
- .stop = c_stop,
- .show = c_show
- };
-+
-+/*
-+ * Temporary hack to avoid need for console= on command line
-+ */
-+static int __init arm64_console_setup(void)
-+{
-+ /* Allow cmdline to override our assumed preferences */
-+ if (console_set_on_cmdline)
-+ return 0;
-+
-+ if (IS_ENABLED(CONFIG_SBSAUART_TTY))
-+ add_preferred_console("ttySBSA", 0, "115200");
-+
-+ if (IS_ENABLED(CONFIG_SERIAL_AMBA_PL011))
-+ add_preferred_console("ttyAMA", 0, "115200");
-+
-+ if (IS_ENABLED(CONFIG_SERIAL_8250))
-+ add_preferred_console("ttyS", 0, "115200");
-+
-+ return 0;
-+}
-+early_initcall(arm64_console_setup);
-diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
-index 7ae6ee0..5aaf5a4 100644
---- a/arch/arm64/kernel/smp.c
-+++ b/arch/arm64/kernel/smp.c
-@@ -323,7 +323,7 @@ void __init smp_prepare_boot_cpu(void)
- * cpu logical map array containing MPIDR values related to logical
- * cpus. Assumes that cpu_logical_map(0) has already been initialized.
- */
--void __init smp_init_cpus(void)
-+void __init of_smp_init_cpus(void)
- {
- struct device_node *dn = NULL;
- unsigned int i, cpu = 1;
-diff --git a/arch/arm64/kernel/smp_parking_protocol.c b/arch/arm64/kernel/smp_parking_protocol.c
-new file mode 100644
-index 0000000..e1153ce
---- /dev/null
-+++ b/arch/arm64/kernel/smp_parking_protocol.c
-@@ -0,0 +1,110 @@
-+/*
-+ * Parking Protocol SMP initialisation
-+ *
-+ * Based largely on spin-table method.
-+ *
-+ * Copyright (C) 2013 ARM Ltd.
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
-+ */
-+#include <linux/delay.h>
-+#include <linux/init.h>
-+#include <linux/of.h>
-+#include <linux/smp.h>
-+#include <linux/types.h>
-+#include <linux/acpi.h>
-+
-+#include <asm/cacheflush.h>
-+#include <asm/cpu_ops.h>
-+#include <asm/cputype.h>
-+#include <asm/smp_plat.h>
-+
-+static phys_addr_t cpu_mailbox_addr[NR_CPUS];
-+
-+static void (*__smp_boot_wakeup)(int cpu);
-+
-+void set_smp_boot_wakeup_call(void (*fn)(int cpu))
-+{
-+ __smp_boot_wakeup = fn;
-+}
-+
-+static int smp_parking_protocol_cpu_init(struct device_node *dn,
-+ unsigned int cpu)
-+{
-+ /*
-+ * Determine the mailbox address.
-+ */
-+ if (!acpi_get_cpu_parked_address(cpu, &cpu_mailbox_addr[cpu])) {
-+ pr_info("%s: ACPI parked addr=%llx\n",
-+ __func__, cpu_mailbox_addr[cpu]);
-+ return 0;
-+ }
-+
-+ pr_err("CPU %d: missing or invalid parking protocol mailbox\n", cpu);
-+
-+ return -1;
-+}
-+
-+static int smp_parking_protocol_cpu_prepare(unsigned int cpu)
-+{
-+ return 0;
-+}
-+
-+struct parking_protocol_mailbox {
-+ __le32 cpu_id;
-+ __le32 reserved;
-+ __le64 entry_point;
-+};
-+
-+static int smp_parking_protocol_cpu_boot(unsigned int cpu)
-+{
-+ struct parking_protocol_mailbox __iomem *mailbox;
-+
-+ if (!cpu_mailbox_addr[cpu] || !__smp_boot_wakeup)
-+ return -ENODEV;
-+
-+ /*
-+ * The mailbox may or may not be inside the linear mapping.
-+ * As ioremap_cache will either give us a new mapping or reuse the
-+ * existing linear mapping, we can use it to cover both cases. In
-+ * either case the memory will be MT_NORMAL.
-+ */
-+ mailbox = ioremap_cache(cpu_mailbox_addr[cpu], sizeof(*mailbox));
-+ if (!mailbox)
-+ return -ENOMEM;
-+
-+ /*
-+ * We write the entry point and cpu id as LE regardless of the
-+ * native endianess of the kernel. Therefore, any boot-loaders
-+ * that read this address need to convert this address to the
-+ * Boot-Loader's endianess before jumping.
-+ */
-+ writeq(__pa(secondary_entry), &mailbox->entry_point);
-+ writel(cpu, &mailbox->cpu_id);
-+ __flush_dcache_area(mailbox, sizeof(*mailbox));
-+ __smp_boot_wakeup(cpu);
-+
-+ /* temp hack for broken firmware */
-+ sev();
-+
-+ iounmap(mailbox);
-+
-+ return 0;
-+}
-+
-+const struct cpu_operations smp_parking_protocol_ops = {
-+ .name = "parking-protocol",
-+ .cpu_init = smp_parking_protocol_cpu_init,
-+ .cpu_prepare = smp_parking_protocol_cpu_prepare,
-+ .cpu_boot = smp_parking_protocol_cpu_boot,
-+};
-diff --git a/arch/arm64/kernel/time.c b/arch/arm64/kernel/time.c
-index 1a7125c..42f9195 100644
---- a/arch/arm64/kernel/time.c
-+++ b/arch/arm64/kernel/time.c
-@@ -35,6 +35,7 @@
- #include <linux/delay.h>
- #include <linux/clocksource.h>
- #include <linux/clk-provider.h>
-+#include <linux/acpi.h>
-
- #include <clocksource/arm_arch_timer.h>
-
-@@ -72,6 +73,12 @@ void __init time_init(void)
-
- tick_setup_hrtimer_broadcast();
-
-+ /*
-+ * Since ACPI or FDT will only one be available in the system,
-+ * we can use acpi_generic_timer_init() here safely
-+ */
-+ acpi_generic_timer_init();
-+
- arch_timer_rate = arch_timer_get_rate();
- if (!arch_timer_rate)
- panic("Unable to initialise architected timer.\n");
-diff --git a/arch/arm64/mm/dma-mapping.c b/arch/arm64/mm/dma-mapping.c
-index d920942..cf890e3 100644
---- a/arch/arm64/mm/dma-mapping.c
-+++ b/arch/arm64/mm/dma-mapping.c
-@@ -23,8 +23,14 @@
- #include <linux/genalloc.h>
- #include <linux/dma-mapping.h>
- #include <linux/dma-contiguous.h>
-+#include <linux/of.h>
-+#include <linux/of_address.h>
-+#include <linux/platform_device.h>
- #include <linux/vmalloc.h>
- #include <linux/swiotlb.h>
-+#include <linux/amba/bus.h>
-+#include <linux/acpi.h>
-+#include <linux/pci.h>
-
- #include <asm/cacheflush.h>
-
-@@ -423,10 +429,116 @@ out:
- return -ENOMEM;
- }
-
-+#ifdef CONFIG_PCI
-+static void arm64_of_set_dma_ops(void *_dev)
-+{
-+ struct device *dev = _dev;
-+
-+ /*
-+ * PCI devices won't have an ACPI handle but the bridge will.
-+ * Search up the device chain until we find an of_node
-+ * to check.
-+ */
-+ while (dev) {
-+ if (dev->of_node) {
-+ if (of_dma_is_coherent(dev->of_node))
-+ set_dma_ops(_dev, &coherent_swiotlb_dma_ops);
-+ break;
-+ }
-+ dev = dev->parent;
-+ }
-+}
-+#else
-+static inline arm64_of_set_dma_ops(void *_dev) {}
-+#endif
-+
-+
-+#ifdef CONFIG_ACPI
-+static void arm64_acpi_set_dma_ops(void *_dev)
-+{
-+ struct device *dev = _dev;
-+
-+ /*
-+ * Kernel defaults to noncoherent ops but ACPI 5.1 spec says arm64
-+ * defaults to coherent. For PCI devices, the _CCA is only a default
-+ * setting. Individual devices on a PCIe bus may set transaction
-+ * ordering and caching attributes individually. Such drivers will
-+ * also be resonsible for using the correct DMA ops for the cache
-+ * conherence used.
-+ *
-+ * PCI devices won't have a handle but the bridge will.
-+ * Search up the device chain until we find an ACPI handle
-+ * to check.
-+ */
-+ while (dev) {
-+ if (ACPI_HANDLE(dev)) {
-+ acpi_status status;
-+ int coherent;
-+ struct dma_map_ops *ops;
-+
-+ status = acpi_check_coherency(ACPI_HANDLE(dev),
-+ &coherent);
-+ if (ACPI_FAILURE(status) || coherent)
-+ ops = &coherent_swiotlb_dma_ops;
-+ else
-+ ops = &noncoherent_swiotlb_dma_ops;
-+
-+ set_dma_ops(_dev, ops);
-+ break;
-+ }
-+ dev = dev->parent;
-+ }
-+}
-+#else
-+static inline arm64_acpi_set_dma_ops(void *_dev) {}
-+#endif
-+
-+static int dma_bus_notifier(struct notifier_block *nb,
-+ unsigned long event, void *_dev)
-+{
-+ if (event != BUS_NOTIFY_ADD_DEVICE)
-+ return NOTIFY_DONE;
-+
-+ if (acpi_disabled)
-+ arm64_of_set_dma_ops(_dev);
-+ else
-+ arm64_acpi_set_dma_ops(_dev);
-+
-+ return NOTIFY_OK;
-+}
-+
-+#ifdef CONFIG_ACPI
-+static struct notifier_block platform_bus_nb = {
-+ .notifier_call = dma_bus_notifier,
-+};
-+
-+static struct notifier_block amba_bus_nb = {
-+ .notifier_call = dma_bus_notifier,
-+};
-+#endif
-+
-+#ifdef CONFIG_PCI
-+static struct notifier_block pci_bus_nb = {
-+ .notifier_call = dma_bus_notifier,
-+};
-+#endif
-+
- static int __init swiotlb_late_init(void)
- {
- size_t swiotlb_size = min(SZ_64M, MAX_ORDER_NR_PAGES << PAGE_SHIFT);
-
-+ /*
-+ * These must be registered before of_platform_populate().
-+ */
-+#ifdef CONFIG_ACPI
-+ bus_register_notifier(&platform_bus_type, &platform_bus_nb);
-+ bus_register_notifier(&amba_bustype, &amba_bus_nb);
-+#endif
-+
-+#ifdef CONFIG_PCI
-+ bus_register_notifier(&pci_bus_type, &pci_bus_nb);
-+#endif
-+
- dma_ops = &noncoherent_swiotlb_dma_ops;
-
- return swiotlb_late_init_with_default_size(swiotlb_size);
-diff --git a/arch/arm64/pci/Makefile b/arch/arm64/pci/Makefile
-new file mode 100644
-index 0000000..7038b51
---- /dev/null
-+++ b/arch/arm64/pci/Makefile
-@@ -0,0 +1,2 @@
-+obj-y += pci.o
-+obj-$(CONFIG_ACPI) += mmconfig.o
-diff --git a/arch/arm64/pci/mmconfig.c b/arch/arm64/pci/mmconfig.c
-new file mode 100644
-index 0000000..e83e0d5
---- /dev/null
-+++ b/arch/arm64/pci/mmconfig.c
-@@ -0,0 +1,292 @@
-+/*
-+ * mmconfig.c - Low-level direct PCI config space access via MMCONFIG
-+ *
-+ * Borrowed heavily from x86
-+ */
-+
-+#include <linux/pci.h>
-+#include <linux/acpi.h>
-+#include <linux/init.h>
-+#include <linux/bitmap.h>
-+#include <linux/dmi.h>
-+#include <linux/slab.h>
-+#include <linux/mutex.h>
-+#include <linux/rculist.h>
-+#include <linux/rcupdate.h>
-+
-+#define PREFIX "PCI: "
-+
-+/* Indicate if the mmcfg resources have been placed into the resource table. */
-+static bool pci_mmcfg_running_state;
-+static bool pci_mmcfg_arch_init_failed;
-+static DEFINE_MUTEX(pci_mmcfg_lock);
-+
-+LIST_HEAD(pci_mmcfg_list);
-+
-+struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus)
-+{
-+ struct pci_mmcfg_region *cfg;
-+
-+ list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list)
-+ if (cfg->segment == segment &&
-+ cfg->start_bus <= bus && bus <= cfg->end_bus)
-+ return cfg;
-+
-+ return NULL;
-+}
-+
-+static void __iomem *mcfg_ioremap(struct pci_mmcfg_region *cfg)
-+{
-+ void __iomem *addr;
-+ u64 start, size;
-+ int num_buses;
-+
-+ start = cfg->address + PCI_MMCFG_BUS_OFFSET(cfg->start_bus);
-+ num_buses = cfg->end_bus - cfg->start_bus + 1;
-+ size = PCI_MMCFG_BUS_OFFSET(num_buses);
-+ addr = ioremap_nocache(start, size);
-+ if (addr)
-+ addr -= PCI_MMCFG_BUS_OFFSET(cfg->start_bus);
-+ return addr;
-+}
-+
-+void pci_mmcfg_arch_unmap(struct pci_mmcfg_region *cfg)
-+{
-+ if (cfg && cfg->virt) {
-+ iounmap(cfg->virt + PCI_MMCFG_BUS_OFFSET(cfg->start_bus));
-+ cfg->virt = NULL;
-+ }
-+}
-+
-+void __init pci_mmcfg_arch_free(void)
-+{
-+ struct pci_mmcfg_region *cfg;
-+
-+ list_for_each_entry(cfg, &pci_mmcfg_list, list)
-+ pci_mmcfg_arch_unmap(cfg);
-+}
-+
-+int pci_mmcfg_arch_map(struct pci_mmcfg_region *cfg)
-+{
-+ cfg->virt = mcfg_ioremap(cfg);
-+ if (!cfg->virt) {
-+ pr_err(PREFIX "can't map MMCONFIG at %pR\n", &cfg->res);
-+ return -ENOMEM;
-+ }
-+
-+ return 0;
-+}
-+
-+static void __init pci_mmconfig_remove(struct pci_mmcfg_region *cfg)
-+{
-+ if (cfg->res.parent)
-+ release_resource(&cfg->res);
-+ list_del(&cfg->list);
-+ kfree(cfg);
-+}
-+
-+static void __init free_all_mmcfg(void)
-+{
-+ struct pci_mmcfg_region *cfg, *tmp;
-+
-+ pci_mmcfg_arch_free();
-+ list_for_each_entry_safe(cfg, tmp, &pci_mmcfg_list, list)
-+ pci_mmconfig_remove(cfg);
-+}
-+
-+static void list_add_sorted(struct pci_mmcfg_region *new)
-+{
-+ struct pci_mmcfg_region *cfg;
-+
-+ /* keep list sorted by segment and starting bus number */
-+ list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list) {
-+ if (cfg->segment > new->segment ||
-+ (cfg->segment == new->segment &&
-+ cfg->start_bus >= new->start_bus)) {
-+ list_add_tail_rcu(&new->list, &cfg->list);
-+ return;
-+ }
-+ }
-+ list_add_tail_rcu(&new->list, &pci_mmcfg_list);
-+}
-+
-+static struct pci_mmcfg_region *pci_mmconfig_alloc(int segment, int start,
-+ int end, u64 addr)
-+{
-+ struct pci_mmcfg_region *new;
-+ struct resource *res;
-+
-+ if (addr == 0)
-+ return NULL;
-+
-+ new = kzalloc(sizeof(*new), GFP_KERNEL);
-+ if (!new)
-+ return NULL;
-+
-+ new->address = addr;
-+ new->segment = segment;
-+ new->start_bus = start;
-+ new->end_bus = end;
-+
-+ res = &new->res;
-+ res->start = addr + PCI_MMCFG_BUS_OFFSET(start);
-+ res->end = addr + PCI_MMCFG_BUS_OFFSET(end + 1) - 1;
-+ res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
-+ snprintf(new->name, PCI_MMCFG_RESOURCE_NAME_LEN,
-+ "PCI MMCONFIG %04x [bus %02x-%02x]", segment, start, end);
-+ res->name = new->name;
-+
-+ return new;
-+}
-+
-+static struct pci_mmcfg_region *__init pci_mmconfig_add(int segment, int start,
-+ int end, u64 addr)
-+{
-+ struct pci_mmcfg_region *new;
-+
-+ new = pci_mmconfig_alloc(segment, start, end, addr);
-+ if (new) {
-+ mutex_lock(&pci_mmcfg_lock);
-+ list_add_sorted(new);
-+ mutex_unlock(&pci_mmcfg_lock);
-+
-+ pr_info(PREFIX
-+ "MMCONFIG for domain %04x [bus %02x-%02x] at %pR "
-+ "(base %#lx)\n",
-+ segment, start, end, &new->res, (unsigned long)addr);
-+ }
-+
-+ return new;
-+}
-+
-+extern struct acpi_mcfg_fixup __start_acpi_mcfg_fixups[];
-+extern struct acpi_mcfg_fixup __end_acpi_mcfg_fixups[];
-+
-+static int __init pci_parse_mcfg(struct acpi_table_header *header)
-+{
-+ struct acpi_table_mcfg *mcfg;
-+ struct acpi_mcfg_allocation *cfg_table, *cfg;
-+ struct acpi_mcfg_fixup *fixup;
-+ struct pci_mmcfg_region *new;
-+ unsigned long i;
-+ int entries;
-+
-+ if (!header)
-+ return -EINVAL;
-+
-+ mcfg = (struct acpi_table_mcfg *)header;
-+
-+ /* how many config structures do we have */
-+ free_all_mmcfg();
-+ entries = 0;
-+ i = header->length - sizeof(struct acpi_table_mcfg);
-+ while (i >= sizeof(struct acpi_mcfg_allocation)) {
-+ entries++;
-+ i -= sizeof(struct acpi_mcfg_allocation);
-+ }
-+ if (entries == 0) {
-+ pr_err(PREFIX "MMCONFIG has no entries\n");
-+ return -ENODEV;
-+ }
-+
-+ fixup = __start_acpi_mcfg_fixups;
-+ while (fixup < __end_acpi_mcfg_fixups) {
-+ if (!strncmp(fixup->oem_id, header->oem_id, 6) &&
-+ !strncmp(fixup->oem_table_id, header->oem_table_id, 8))
-+ break;
-+ ++fixup;
-+ }
-+
-+ cfg_table = (struct acpi_mcfg_allocation *) &mcfg[1];
-+ for (i = 0; i < entries; i++) {
-+ cfg = &cfg_table[i];
-+
-+ new = pci_mmconfig_add(cfg->pci_segment, cfg->start_bus_number,
-+ cfg->end_bus_number, cfg->address);
-+ if (!new) {
-+ pr_warn(PREFIX "no memory for MCFG entries\n");
-+ free_all_mmcfg();
-+ return -ENOMEM;
-+ }
-+ if (fixup < __end_acpi_mcfg_fixups)
-+ new->fixup = fixup->hook;
-+ }
-+
-+ return 0;
-+}
-+
-+int __init pci_mmcfg_arch_init(void)
-+{
-+ struct pci_mmcfg_region *cfg;
-+
-+ list_for_each_entry(cfg, &pci_mmcfg_list, list)
-+ if (pci_mmcfg_arch_map(cfg)) {
-+ pci_mmcfg_arch_free();
-+ return 0;
-+ }
-+
-+ return 1;
-+}
-+
-+static void __init __pci_mmcfg_init(int early)
-+{
-+ if (list_empty(&pci_mmcfg_list)) {
-+ pr_info("No MCFG table found!\n");
-+ pci_mmcfg_arch_init_failed = true;
-+ return;
-+ }
-+
-+ if (!pci_mmcfg_arch_init()) {
-+ pr_info("pci_mmcfg_arch_init failed!\n");
-+ free_all_mmcfg();
-+ pci_mmcfg_arch_init_failed = true;
-+ }
-+}
-+
-+void __init pci_mmcfg_early_init(void)
-+{
-+ acpi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
-+
-+ __pci_mmcfg_init(1);
-+}
-+
-+static int __init pci_mmcfg_init(void)
-+{
-+ pci_mmcfg_early_init();
-+ return 0;
-+}
-+arch_initcall(pci_mmcfg_init);
-+
-+void __init pci_mmcfg_late_init(void)
-+{
-+ /* MMCONFIG hasn't been enabled yet, try again */
-+ if (pci_mmcfg_arch_init_failed) {
-+ acpi_table_parse(ACPI_SIG_MCFG, pci_parse_mcfg);
-+ __pci_mmcfg_init(0);
-+ }
-+}
-+
-+static int __init pci_mmcfg_late_insert_resources(void)
-+{
-+ struct pci_mmcfg_region *cfg;
-+
-+ pci_mmcfg_running_state = true;
-+
-+ /*
-+ * Attempt to insert the mmcfg resources but not with the busy flag
-+ * marked so it won't cause request errors when __request_region is
-+ * called.
-+ */
-+ list_for_each_entry(cfg, &pci_mmcfg_list, list)
-+ if (!cfg->res.parent)
-+ insert_resource(&iomem_resource, &cfg->res);
-+
-+ return 0;
-+}
-+
-+/*
-+ * Perform MMCONFIG resource insertion after PCI initialization to allow for
-+ * misprogrammed MCFG tables that state larger sizes but actually conflict
-+ * with other system resources.
-+ */
-+late_initcall(pci_mmcfg_late_insert_resources);
-diff --git a/arch/arm64/pci/pci.c b/arch/arm64/pci/pci.c
-new file mode 100644
-index 0000000..0166475
---- /dev/null
-+++ b/arch/arm64/pci/pci.c
-@@ -0,0 +1,461 @@
-+#include <linux/acpi.h>
-+#include <linux/of_address.h>
-+#include <linux/types.h>
-+#include <linux/kernel.h>
-+#include <linux/pci.h>
-+
-+struct pci_root_info {
-+ struct acpi_device *bridge;
-+ char name[16];
-+ unsigned int res_num;
-+ struct resource *res;
-+ resource_size_t *res_offset;
-+ struct pci_sysdata sd;
-+ u16 segment;
-+ u8 start_bus;
-+ u8 end_bus;
-+};
-+
-+static char __iomem *pci_dev_base(struct pci_mmcfg_region *cfg,
-+ unsigned int bus, unsigned int devfn)
-+{
-+ return cfg->virt + (PCI_MMCFG_BUS_OFFSET(bus) | (devfn << 12));
-+}
-+
-+static int __raw_pci_read(struct pci_mmcfg_region *cfg, unsigned int bus,
-+ unsigned int devfn, int reg, int len, u32 *value)
-+{
-+ char __iomem *addr = pci_dev_base(cfg, bus, devfn) + (reg & ~3);
-+ int shift = (reg & 3) * 8;
-+ u32 v;
-+
-+ v = readl(addr) >> shift;
-+ switch (len) {
-+ case 1:
-+ *value = v & 0xff;
-+ break;
-+ case 2:
-+ *value = v & 0xffff;
-+ break;
-+ case 4:
-+ *value = v;
-+ break;
-+ }
-+ return 0;
-+}
-+
-+static int __raw_pci_write(struct pci_mmcfg_region *cfg, unsigned int bus,
-+ unsigned int devfn, int reg, int len, u32 value)
-+{
-+ char __iomem *addr = pci_dev_base(cfg, bus, devfn) + (reg & ~3);
-+ int mask = 0, shift = (reg & 3) * 8;
-+ u32 v;
-+
-+ switch (len) {
-+ case 1:
-+ mask = 0xff << shift;
-+ break;
-+ case 2:
-+ mask = 0xffff << shift;
-+ break;
-+ }
-+
-+ if (mask) {
-+ v = readl(addr) & ~mask;
-+ writel(v | (value << shift), addr);
-+ } else
-+ writel(value, addr);
-+
-+ return 0;
-+}
-+
-+/*
-+ * raw_pci_read/write - Platform-specific PCI config space access.
-+ */
-+int raw_pci_read(unsigned int domain, unsigned int bus,
-+ unsigned int devfn, int reg, int len, u32 *val)
-+{
-+ struct pci_mmcfg_region *cfg;
-+ int ret;
-+
-+ if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095))) {
-+err: *val = -1;
-+ return -EINVAL;
-+ }
-+
-+ rcu_read_lock();
-+ cfg = pci_mmconfig_lookup(domain, bus);
-+ if (!cfg || !cfg->virt) {
-+ rcu_read_unlock();
-+ goto err;
-+ }
-+
-+ if (cfg->read)
-+ ret = (*cfg->read)(cfg, bus, devfn, reg, len, val);
-+ else
-+ ret = __raw_pci_read(cfg, bus, devfn, reg, len, val);
-+
-+ rcu_read_unlock();
-+
-+ return ret;
-+}
-+
-+int raw_pci_write(unsigned int domain, unsigned int bus,
-+ unsigned int devfn, int reg, int len, u32 val)
-+{
-+ struct pci_mmcfg_region *cfg;
-+ int ret;
-+
-+ if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095)))
-+ return -EINVAL;
-+
-+ rcu_read_lock();
-+ cfg = pci_mmconfig_lookup(domain, bus);
-+ if (!cfg || !cfg->virt) {
-+ rcu_read_unlock();
-+ return -EINVAL;
-+ }
-+
-+ if (cfg->write)
-+ ret = (*cfg->write)(cfg, bus, devfn, reg, len, val);
-+ else
-+ ret = __raw_pci_write(cfg, bus, devfn, reg, len, val);
-+
-+ rcu_read_unlock();
-+
-+ return ret;
-+}
-+
-+#ifdef CONFIG_ACPI
-+static int pci_read(struct pci_bus *bus, unsigned int devfn, int where,
-+ int size, u32 *value)
-+{
-+ return raw_pci_read(pci_domain_nr(bus), bus->number,
-+ devfn, where, size, value);
-+}
-+
-+static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
-+ int size, u32 value)
-+{
-+ return raw_pci_write(pci_domain_nr(bus), bus->number,
-+ devfn, where, size, value);
-+}
-+
-+struct pci_ops pci_root_ops = {
-+ .read = pci_read,
-+ .write = pci_write,
-+};
-+
-+static acpi_status resource_to_addr(struct acpi_resource *resource,
-+ struct acpi_resource_address64 *addr)
-+{
-+ acpi_status status;
-+
-+ memset(addr, 0, sizeof(*addr));
-+ switch (resource->type) {
-+ case ACPI_RESOURCE_TYPE_ADDRESS16:
-+ case ACPI_RESOURCE_TYPE_ADDRESS32:
-+ case ACPI_RESOURCE_TYPE_ADDRESS64:
-+ status = acpi_resource_to_address64(resource, addr);
-+ if (ACPI_SUCCESS(status) &&
-+ (addr->resource_type == ACPI_MEMORY_RANGE ||
-+ addr->resource_type == ACPI_IO_RANGE) &&
-+ addr->address_length > 0) {
-+ return AE_OK;
-+ }
-+ break;
-+ }
-+ return AE_ERROR;
-+}
-+
-+static acpi_status count_resource(struct acpi_resource *acpi_res, void *data)
-+{
-+ struct pci_root_info *info = data;
-+ struct acpi_resource_address64 addr;
-+ acpi_status status;
-+
-+ status = resource_to_addr(acpi_res, &addr);
-+ if (ACPI_SUCCESS(status))
-+ info->res_num++;
-+ return AE_OK;
-+}
-+
-+static acpi_status setup_resource(struct acpi_resource *acpi_res, void *data)
-+{
-+ struct pci_root_info *info = data;
-+ struct resource *res;
-+ struct acpi_resource_address64 addr;
-+ acpi_status status;
-+ unsigned long flags;
-+ u64 start, end;
-+
-+ status = resource_to_addr(acpi_res, &addr);
-+ if (!ACPI_SUCCESS(status))
-+ return AE_OK;
-+
-+ if (addr.resource_type == ACPI_MEMORY_RANGE) {
-+ flags = IORESOURCE_MEM;
-+ if (addr.info.mem.caching == ACPI_PREFETCHABLE_MEMORY)
-+ flags |= IORESOURCE_PREFETCH;
-+ } else if (addr.resource_type == ACPI_IO_RANGE) {
-+ flags = IORESOURCE_IO;
-+ } else
-+ return AE_OK;
-+
-+ start = addr.minimum + addr.translation_offset;
-+ end = addr.maximum + addr.translation_offset;
-+
-+ res = &info->res[info->res_num];
-+ res->name = info->name;
-+ res->flags = flags;
-+ res->start = start;
-+ res->end = end;
-+
-+ if (flags & IORESOURCE_IO) {
-+ unsigned long port;
-+ int err;
-+
-+ err = pci_register_io_range(start, addr.address_length);
-+ if (err)
-+ return AE_OK;
-+
-+ port = pci_address_to_pio(start);
-+ if (port == (unsigned long)-1) {
-+ res->start = -1;
-+ res->end = -1;
-+ return AE_OK;
-+ }
-+
-+ res->start = port;
-+ res->end = res->start + addr.address_length - 1;
-+
-+ if (pci_remap_iospace(res, start) < 0)
-+ return AE_OK;
-+
-+ info->res_offset[info->res_num] = 0;
-+ } else
-+ info->res_offset[info->res_num] = addr.translation_offset;
-+
-+ info->res_num++;
-+
-+ return AE_OK;
-+}
-+
-+static void coalesce_windows(struct pci_root_info *info, unsigned long type)
-+{
-+ int i, j;
-+ struct resource *res1, *res2;
-+
-+ for (i = 0; i < info->res_num; i++) {
-+ res1 = &info->res[i];
-+ if (!(res1->flags & type))
-+ continue;
-+
-+ for (j = i + 1; j < info->res_num; j++) {
-+ res2 = &info->res[j];
-+ if (!(res2->flags & type))
-+ continue;
-+
-+ /*
-+ * I don't like throwing away windows because then
-+ * our resources no longer match the ACPI _CRS, but
-+ * the kernel resource tree doesn't allow overlaps.
-+ */
-+ if (resource_overlaps(res1, res2)) {
-+ res2->start = min(res1->start, res2->start);
-+ res2->end = max(res1->end, res2->end);
-+ dev_info(&info->bridge->dev,
-+ "host bridge window expanded to %pR; %pR ignored\n",
-+ res2, res1);
-+ res1->flags = 0;
-+ }
-+ }
-+ }
-+}
-+
-+static void add_resources(struct pci_root_info *info,
-+ struct list_head *resources)
-+{
-+ int i;
-+ struct resource *res, *root, *conflict;
-+
-+ coalesce_windows(info, IORESOURCE_MEM);
-+ coalesce_windows(info, IORESOURCE_IO);
-+
-+ for (i = 0; i < info->res_num; i++) {
-+ res = &info->res[i];
-+
-+ if (res->flags & IORESOURCE_MEM)
-+ root = &iomem_resource;
-+ else if (res->flags & IORESOURCE_IO)
-+ root = &ioport_resource;
-+ else
-+ continue;
-+
-+ conflict = insert_resource_conflict(root, res);
-+ if (conflict)
-+ dev_info(&info->bridge->dev,
-+ "ignoring host bridge window %pR (conflicts with %s %pR)\n",
-+ res, conflict->name, conflict);
-+ else
-+ pci_add_resource_offset(resources, res,
-+ info->res_offset[i]);
-+ }
-+}
-+
-+static void free_pci_root_info_res(struct pci_root_info *info)
-+{
-+ kfree(info->res);
-+ info->res = NULL;
-+ kfree(info->res_offset);
-+ info->res_offset = NULL;
-+ info->res_num = 0;
-+}
-+
-+static void __release_pci_root_info(struct pci_root_info *info)
-+{
-+ int i;
-+ struct resource *res;
-+
-+ for (i = 0; i < info->res_num; i++) {
-+ res = &info->res[i];
-+
-+ if (!res->parent)
-+ continue;
-+
-+ if (!(res->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
-+ continue;
-+
-+ release_resource(res);
-+ }
-+
-+ free_pci_root_info_res(info);
-+
-+ kfree(info);
-+}
-+
-+static void release_pci_root_info(struct pci_host_bridge *bridge)
-+{
-+ struct pci_root_info *info = bridge->release_data;
-+
-+ __release_pci_root_info(info);
-+}
-+
-+static void probe_pci_root_info(struct pci_root_info *info,
-+ struct acpi_device *device,
-+ int busnum, int domain)
-+{
-+ size_t size;
-+
-+ sprintf(info->name, "PCI Bus %04x:%02x", domain, busnum);
-+ info->bridge = device;
-+
-+ info->res_num = 0;
-+ acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_resource,
-+ info);
-+ if (!info->res_num)
-+ return;
-+
-+ size = sizeof(*info->res) * info->res_num;
-+ info->res = kzalloc_node(size, GFP_KERNEL, info->sd.node);
-+ if (!info->res) {
-+ info->res_num = 0;
-+ return;
-+ }
-+
-+ size = sizeof(*info->res_offset) * info->res_num;
-+ info->res_num = 0;
-+ info->res_offset = kzalloc_node(size, GFP_KERNEL, info->sd.node);
-+ if (!info->res_offset) {
-+ kfree(info->res);
-+ info->res = NULL;
-+ return;
-+ }
-+
-+ acpi_walk_resources(device->handle, METHOD_NAME__CRS, setup_resource,
-+ info);
-+}
-+
-+/* Root bridge scanning */
-+struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
-+{
-+ struct acpi_device *device = root->device;
-+ struct pci_mmcfg_region *mcfg;
-+ struct pci_root_info *info;
-+ int domain = root->segment;
-+ int busnum = root->secondary.start;
-+ LIST_HEAD(resources);
-+ struct pci_bus *bus;
-+ struct pci_sysdata *sd;
-+ int node;
-+
-+ /* we need mmconfig */
-+ mcfg = pci_mmconfig_lookup(domain, busnum);
-+ if (!mcfg) {
-+ pr_err("pci_bus %04x:%02x has no MCFG table\n",
-+ domain, busnum);
-+ return NULL;
-+ }
-+
-+ /* temporary hack */
-+ if (mcfg->fixup)
-+ (*mcfg->fixup)(root, mcfg);
-+
-+ if (domain && !pci_domains_supported) {
-+ pr_warn("PCI %04x:%02x: multiple domains not supported.\n",
-+ domain, busnum);
-+ return NULL;
-+ }
-+
-+ node = NUMA_NO_NODE;
-+
-+ info = kzalloc_node(sizeof(*info), GFP_KERNEL, node);
-+ if (!info) {
-+ pr_warn("PCI %04x:%02x: ignored (out of memory)\n",
-+ domain, busnum);
-+ return NULL;
-+ }
-+ info->segment = domain;
-+ info->start_bus = busnum;
-+ info->end_bus = root->secondary.end;
-+
-+ sd = &info->sd;
-+ sd->domain = domain;
-+ sd->node = node;
-+ sd->companion = device;
-+
-+ probe_pci_root_info(info, device, busnum, domain);
-+
-+ /* insert busn res at first */
-+ pci_add_resource(&resources, &root->secondary);
-+
-+ /* then _CRS resources */
-+ add_resources(info, &resources);
-+
-+ bus = pci_create_root_bus(NULL, busnum, &pci_root_ops, sd, &resources);
-+ if (bus) {
-+ pci_scan_child_bus(bus);
-+ pci_set_host_bridge_release(to_pci_host_bridge(bus->bridge),
-+ release_pci_root_info, info);
-+ } else {
-+ pci_free_resource_list(&resources);
-+ __release_pci_root_info(info);
-+ }
-+
-+ /* After the PCI-E bus has been walked and all devices discovered,
-+ * configure any settings of the fabric that might be necessary.
-+ */
-+ if (bus) {
-+ struct pci_bus *child;
-+
-+ list_for_each_entry(child, &bus->children, node)
-+ pcie_bus_configure_settings(child);
-+ }
-+
-+ if (bus && node != NUMA_NO_NODE)
-+ dev_printk(KERN_DEBUG, &bus->dev, "on NUMA node %d\n", node);
-+
-+ return bus;
-+}
-+
-+#endif /* CONFIG_ACPI */
-diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig
-index 8951cef..63aa47c 100644
---- a/drivers/acpi/Kconfig
-+++ b/drivers/acpi/Kconfig
-@@ -5,8 +5,7 @@
- menuconfig ACPI
- bool "ACPI (Advanced Configuration and Power Interface) Support"
- depends on !IA64_HP_SIM
-- depends on IA64 || X86
-- depends on PCI
-+ depends on ((IA64 || X86) && PCI) || ARM64
- select PNP
- default y
- help
-@@ -163,6 +162,7 @@ config ACPI_PROCESSOR
- tristate "Processor"
- select THERMAL
- select CPU_IDLE
-+ depends on X86 || IA64
- default y
- help
- This driver installs ACPI as the idle handler for Linux and uses
-@@ -263,7 +263,7 @@ config ACPI_DEBUG
-
- config ACPI_PCI_SLOT
- bool "PCI slot detection driver"
-- depends on SYSFS
-+ depends on SYSFS && PCI
- default n
- help
- This driver creates entries in /sys/bus/pci/slots/ for all PCI
-diff --git a/drivers/acpi/Makefile b/drivers/acpi/Makefile
-index f74317c..c346011 100644
---- a/drivers/acpi/Makefile
-+++ b/drivers/acpi/Makefile
-@@ -23,7 +23,11 @@ acpi-y += nvs.o
-
- # Power management related files
- acpi-y += wakeup.o
-+ifeq ($(ARCH), arm64)
-+acpi-y += sleep-arm.o
-+else # X86, IA64
- acpi-y += sleep.o
-+endif
- acpi-y += device_pm.o
- acpi-$(CONFIG_ACPI_SLEEP) += proc.o
-
-@@ -39,7 +43,7 @@ acpi-y += processor_core.o
- acpi-$(CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC) += processor_pdc.o
- acpi-y += ec.o
- acpi-$(CONFIG_ACPI_DOCK) += dock.o
--acpi-y += pci_root.o pci_link.o pci_irq.o
-+acpi-$(CONFIG_PCI) += pci_root.o pci_link.o pci_irq.o
- acpi-y += acpi_lpss.o
- acpi-y += acpi_platform.o
- acpi-y += acpi_pnp.o
-diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c
-index 8b67bd0..c412fdb 100644
---- a/drivers/acpi/bus.c
-+++ b/drivers/acpi/bus.c
-@@ -448,6 +448,9 @@ static int __init acpi_bus_init_irq(void)
- case ACPI_IRQ_MODEL_IOSAPIC:
- message = "IOSAPIC";
- break;
-+ case ACPI_IRQ_MODEL_GIC:
-+ message = "GIC";
-+ break;
- case ACPI_IRQ_MODEL_PLATFORM:
- message = "platform specific model";
- break;
-diff --git a/drivers/acpi/internal.h b/drivers/acpi/internal.h
-index 163e82f..c5ff8ba 100644
---- a/drivers/acpi/internal.h
-+++ b/drivers/acpi/internal.h
-@@ -26,8 +26,13 @@
- acpi_status acpi_os_initialize1(void);
- int init_acpi_device_notify(void);
- int acpi_scan_init(void);
-+#ifdef CONFIG_PCI
- void acpi_pci_root_init(void);
- void acpi_pci_link_init(void);
-+#else
-+static inline void acpi_pci_root_init(void) {}
-+static inline void acpi_pci_link_init(void) {}
-+#endif
- void acpi_processor_init(void);
- void acpi_platform_init(void);
- void acpi_pnp_init(void);
-diff --git a/drivers/acpi/osl.c b/drivers/acpi/osl.c
-index f9eeae8..581b9f7 100644
---- a/drivers/acpi/osl.c
-+++ b/drivers/acpi/osl.c
-@@ -336,11 +336,11 @@ acpi_map_lookup_virt(void __iomem *virt, acpi_size size)
- return NULL;
- }
-
--#ifndef CONFIG_IA64
--#define should_use_kmap(pfn) page_is_ram(pfn)
--#else
-+#if defined(CONFIG_IA64) || defined(CONFIG_ARM) || defined(CONFIG_ARM64)
- /* ioremap will take care of cache attributes */
- #define should_use_kmap(pfn) 0
-+#else
-+#define should_use_kmap(pfn) page_is_ram(pfn)
- #endif
-
- static void __iomem *acpi_map(acpi_physical_address pg_off, unsigned long pg_sz)
-diff --git a/drivers/acpi/processor_core.c b/drivers/acpi/processor_core.c
-index 342942f..734c029 100644
---- a/drivers/acpi/processor_core.c
-+++ b/drivers/acpi/processor_core.c
-@@ -64,6 +64,38 @@ static int map_lsapic_id(struct acpi_subtable_header *entry,
- return 0;
- }
-
-+/*
-+ * On ARM platform, MPIDR value is the hardware ID as apic ID
-+ * on Intel platforms
-+ */
-+static int map_gicc_mpidr(struct acpi_subtable_header *entry,
-+ int device_declaration, u32 acpi_id, int *mpidr)
-+{
-+ struct acpi_madt_generic_interrupt *gicc =
-+ container_of(entry, struct acpi_madt_generic_interrupt, header);
-+
-+ if (!(gicc->flags & ACPI_MADT_ENABLED))
-+ return -ENODEV;
-+
-+ /* In the GIC interrupt model, logical processors are
-+ * required to have a Processor Device object in the DSDT,
-+ * so we should check device_declaration here
-+ */
-+ if (device_declaration && (gicc->uid == acpi_id)) {
-+ /*
-+ * Only bits [0:7] Aff0, bits [8:15] Aff1, bits [16:23] Aff2
-+ * and bits [32:39] Aff3 are meaningful, so pack the Affx
-+ * fields into a single 32 bit identifier to accommodate the
-+ * acpi processor drivers.
-+ */
-+ *mpidr = ((gicc->arm_mpidr & 0xff00000000) >> 8)
-+ | gicc->arm_mpidr;
-+ return 0;
-+ }
-+
-+ return -EINVAL;
-+}
-+
- static int map_madt_entry(int type, u32 acpi_id)
- {
- unsigned long madt_end, entry;
-@@ -99,6 +131,9 @@ static int map_madt_entry(int type, u32 acpi_id)
- } else if (header->type == ACPI_MADT_TYPE_LOCAL_SAPIC) {
- if (!map_lsapic_id(header, type, acpi_id, &phys_id))
- break;
-+ } else if (header->type == ACPI_MADT_TYPE_GENERIC_INTERRUPT) {
-+ if (!map_gicc_mpidr(header, type, acpi_id, &phys_id))
-+ break;
- }
- entry += header->length;
- }
-@@ -131,6 +166,8 @@ static int map_mat_entry(acpi_handle handle, int type, u32 acpi_id)
- map_lsapic_id(header, type, acpi_id, &phys_id);
- else if (header->type == ACPI_MADT_TYPE_LOCAL_X2APIC)
- map_x2apic_id(header, type, acpi_id, &phys_id);
-+ else if (header->type == ACPI_MADT_TYPE_GENERIC_INTERRUPT)
-+ map_gicc_mpidr(header, type, acpi_id, &phys_id);
-
- exit:
- kfree(buffer.pointer);
-diff --git a/drivers/acpi/sleep-arm.c b/drivers/acpi/sleep-arm.c
-new file mode 100644
-index 0000000..54578ef
---- /dev/null
-+++ b/drivers/acpi/sleep-arm.c
-@@ -0,0 +1,28 @@
-+/*
-+ * ARM64 Specific Sleep Functionality
-+ *
-+ * Copyright (C) 2013-2014, Linaro Ltd.
-+ * Author: Graeme Gregory <graeme.gregory at linaro.org>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#include <linux/acpi.h>
-+
-+/*
-+ * Currently the ACPI 5.1 standard does not define S states in a
-+ * manner which is usable for ARM64. These two stubs are sufficient
-+ * that system initialises and device PM works.
-+ */
-+u32 acpi_target_system_state(void)
-+{
-+ return ACPI_STATE_S0;
-+}
-+EXPORT_SYMBOL_GPL(acpi_target_system_state);
-+
-+int __init acpi_sleep_init(void)
-+{
-+ return -ENOSYS;
-+}
-diff --git a/drivers/acpi/tables.c b/drivers/acpi/tables.c
-index 93b8152..122b48f 100644
---- a/drivers/acpi/tables.c
-+++ b/drivers/acpi/tables.c
-@@ -183,6 +183,49 @@ void acpi_table_print_madt_entry(struct acpi_subtable_header *header)
- }
- break;
-
-+ case ACPI_MADT_TYPE_GENERIC_INTERRUPT:
-+ {
-+ struct acpi_madt_generic_interrupt *p =
-+ (struct acpi_madt_generic_interrupt *)header;
-+ pr_info("GICC (acpi_id[0x%04x] address[%p] MPDIR[0x%llx] %s)\n",
-+ p->uid, (void *)(unsigned long)p->base_address,
-+ p->arm_mpidr,
-+ (p->flags & ACPI_MADT_ENABLED) ? "enabled" : "disabled");
-+
-+ }
-+ break;
-+
-+ case ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR:
-+ {
-+ struct acpi_madt_generic_distributor *p =
-+ (struct acpi_madt_generic_distributor *)header;
-+ pr_info("GIC Distributor (gic_id[0x%04x] address[%p] gsi_base[%d])\n",
-+ p->gic_id,
-+ (void *)(unsigned long)p->base_address,
-+ p->global_irq_base);
-+ }
-+ break;
-+
-+ case ACPI_MADT_TYPE_GENERIC_MSI_FRAME:
-+ {
-+ struct acpi_madt_generic_msi_frame *p =
-+ (struct acpi_madt_generic_msi_frame *)header;
-+ pr_info("GIC MSI Frame (msi_fame_id[%d] address[%p])\n",
-+ p->msi_frame_id,
-+ (void *)(unsigned long)p->base_address);
-+ }
-+ break;
-+
-+ case ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR:
-+ {
-+ struct acpi_madt_generic_redistributor *p =
-+ (struct acpi_madt_generic_redistributor *)header;
-+ pr_info("GIC Redistributor (address[%p] region_size[0x%x])\n",
-+ (void *)(unsigned long)p->base_address,
-+ p->length);
-+ }
-+ break;
-+
- default:
- pr_warn("Found unsupported MADT entry (type = 0x%x)\n",
- header->type);
-@@ -210,7 +253,7 @@ acpi_parse_entries(char *id, unsigned long table_size,
- return -EINVAL;
-
- if (!table_header) {
-- pr_warn("%4.4s not present\n", id);
-+ pr_warn("Table header not present\n");
- return -ENODEV;
- }
-
-@@ -246,7 +289,8 @@ acpi_parse_entries(char *id, unsigned long table_size,
-
- if (max_entries && count > max_entries) {
- pr_warn("[%4.4s:0x%02x] ignored %i entries of %i found\n",
-- id, entry_id, count - max_entries, count);
-+ table_header->signature, entry_id, count - max_entries,
-+ count);
- }
-
- return count;
-diff --git a/drivers/acpi/utils.c b/drivers/acpi/utils.c
-index cd49a39..7f68f96 100644
---- a/drivers/acpi/utils.c
-+++ b/drivers/acpi/utils.c
-@@ -712,3 +712,29 @@ bool acpi_check_dsm(acpi_handle handle, const u8 *uuid, int rev, u64 funcs)
- return false;
- }
- EXPORT_SYMBOL(acpi_check_dsm);
-+
-+/**
-+ * acpi_check_coherency - check for memory coherency of a device
-+ * @handle: ACPI device handle
-+ * @val: Pointer to returned value
-+ *
-+ * Search a device and its parents for a _CCA method and return
-+ * its value.
-+ */
-+acpi_status acpi_check_coherency(acpi_handle handle, int *val)
-+{
-+ unsigned long long data;
-+ acpi_status status;
-+
-+ do {
-+ status = acpi_evaluate_integer(handle, "_CCA", NULL, &data);
-+ if (!ACPI_FAILURE(status)) {
-+ *val = data;
-+ break;
-+ }
-+ status = acpi_get_parent(handle, &handle);
-+ } while (!ACPI_FAILURE(status));
-+
-+ return status;
-+}
-+EXPORT_SYMBOL(acpi_check_coherency);
-diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
-index a3a1360..edca892 100644
---- a/drivers/ata/Kconfig
-+++ b/drivers/ata/Kconfig
-@@ -48,7 +48,7 @@ config ATA_VERBOSE_ERROR
-
- config ATA_ACPI
- bool "ATA ACPI Support"
-- depends on ACPI && PCI
-+ depends on ACPI
- default y
- help
- This option adds support for ATA-related ACPI objects.
-diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
-index 18d5398..999e577 100644
---- a/drivers/ata/ahci_platform.c
-+++ b/drivers/ata/ahci_platform.c
-@@ -20,6 +20,9 @@
- #include <linux/platform_device.h>
- #include <linux/libata.h>
- #include <linux/ahci_platform.h>
-+#ifdef CONFIG_ATA_ACPI
-+#include <linux/acpi.h>
-+#endif
- #include "ahci.h"
-
- static const struct ata_port_info ahci_port_info = {
-@@ -71,12 +74,22 @@ static const struct of_device_id ahci_of_match[] = {
- };
- MODULE_DEVICE_TABLE(of, ahci_of_match);
-
-+#ifdef CONFIG_ATA_ACPI
-+static const struct acpi_device_id ahci_acpi_match[] = {
-+ { "AMDI0600", 0 }, /* AMD Seattle AHCI */
-+ { },
-+};
-+#endif
-+
- static struct platform_driver ahci_driver = {
- .probe = ahci_probe,
- .remove = ata_platform_remove_one,
- .driver = {
- .name = "ahci",
- .of_match_table = ahci_of_match,
-+#ifdef CONFIG_ATA_ACPI
-+ .acpi_match_table = ACPI_PTR(ahci_acpi_match),
-+#endif
- .pm = &ahci_pm_ops,
- },
- };
-diff --git a/drivers/ata/ahci_xgene.c b/drivers/ata/ahci_xgene.c
-index feeb8f1..8f82267 100644
---- a/drivers/ata/ahci_xgene.c
-+++ b/drivers/ata/ahci_xgene.c
-@@ -28,6 +28,7 @@
- #include <linux/of_address.h>
- #include <linux/of_irq.h>
- #include <linux/phy/phy.h>
-+#include <linux/acpi.h>
- #include "ahci.h"
-
- /* Max # of disk per a controller */
-@@ -148,14 +150,6 @@ static unsigned int xgene_ahci_qc_issue(struct ata_queued_cmd *qc)
- return rc;
- }
-
--static bool xgene_ahci_is_memram_inited(struct xgene_ahci_context *ctx)
--{
-- void __iomem *diagcsr = ctx->csr_diag;
--
-- return (readl(diagcsr + CFG_MEM_RAM_SHUTDOWN) == 0 &&
-- readl(diagcsr + BLOCK_MEM_RDY) == 0xFFFFFFFF);
--}
--
- /**
- * xgene_ahci_read_id - Read ID data from the specified device
- * @dev: device
-@@ -501,11 +495,6 @@ static int xgene_ahci_probe(struct platform_device *pdev)
- return -ENODEV;
- }
-
-- if (xgene_ahci_is_memram_inited(ctx)) {
-- dev_info(dev, "skip clock and PHY initialization\n");
-- goto skip_clk_phy;
-- }
--
- /* Due to errata, HW requires full toggle transition */
- rc = ahci_platform_enable_clks(hpriv);
- if (rc)
-@@ -518,7 +507,7 @@ static int xgene_ahci_probe(struct platform_device *pdev)
-
- /* Configure the host controller */
- xgene_ahci_hw_init(hpriv);
--skip_clk_phy:
-+
- hpriv->flags = AHCI_HFLAG_NO_PMP | AHCI_HFLAG_NO_NCQ;
-
- rc = ahci_platform_init_host(pdev, hpriv, &xgene_ahci_port_info);
-@@ -533,6 +522,16 @@ disable_resources:
- return rc;
- }
-
-+#ifdef CONFIG_ACPI
-+static const struct acpi_device_id xgene_ahci_acpi_match[] = {
-+ { "APMC0D00", },
-+ { "APMC0D0D", },
-+ { "APMC0D09", },
-+ { }
-+};
-+MODULE_DEVICE_TABLE(acpi, xgene_ahci_acpi_match);
-+#endif
-+
- static const struct of_device_id xgene_ahci_of_match[] = {
- {.compatible = "apm,xgene-ahci"},
- {},
-@@ -545,6 +544,7 @@ static struct platform_driver xgene_ahci_driver = {
- .driver = {
- .name = "xgene-ahci",
- .of_match_table = xgene_ahci_of_match,
-+ .acpi_match_table = ACPI_PTR(xgene_ahci_acpi_match),
- },
- };
-
-diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
-index 095c177..fd5ebbf 100644
---- a/drivers/clocksource/arm_arch_timer.c
-+++ b/drivers/clocksource/arm_arch_timer.c
-@@ -21,6 +21,7 @@
- #include <linux/io.h>
- #include <linux/slab.h>
- #include <linux/sched_clock.h>
-+#include <linux/acpi.h>
-
- #include <asm/arch_timer.h>
- #include <asm/virt.h>
-@@ -61,7 +62,8 @@ enum ppi_nr {
- MAX_TIMER_PPI
- };
-
--static int arch_timer_ppi[MAX_TIMER_PPI];
-+int arch_timer_ppi[MAX_TIMER_PPI];
-+EXPORT_SYMBOL(arch_timer_ppi);
-
- static struct clock_event_device __percpu *arch_timer_evt;
-
-@@ -370,8 +372,12 @@ arch_timer_detect_rate(void __iomem *cntbase, struct device_node *np)
- if (arch_timer_rate)
- return;
-
-- /* Try to determine the frequency from the device tree or CNTFRQ */
-- if (of_property_read_u32(np, "clock-frequency", &arch_timer_rate)) {
-+ /*
-+ * Try to determine the frequency from the device tree or CNTFRQ,
-+ * if ACPI is enabled, get the frequency from CNTFRQ ONLY.
-+ */
-+ if (!acpi_disabled ||
-+ of_property_read_u32(np, "clock-frequency", &arch_timer_rate)) {
- if (cntbase)
- arch_timer_rate = readl_relaxed(cntbase + CNTFRQ);
- else
-@@ -690,28 +696,8 @@ static void __init arch_timer_common_init(void)
- arch_timer_arch_init();
- }
-
--static void __init arch_timer_init(struct device_node *np)
-+static void __init arch_timer_init(void)
- {
-- int i;
--
-- if (arch_timers_present & ARCH_CP15_TIMER) {
-- pr_warn("arch_timer: multiple nodes in dt, skipping\n");
-- return;
-- }
--
-- arch_timers_present |= ARCH_CP15_TIMER;
-- for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++)
-- arch_timer_ppi[i] = irq_of_parse_and_map(np, i);
-- arch_timer_detect_rate(NULL, np);
--
-- /*
-- * If we cannot rely on firmware initializing the timer registers then
-- * we should use the physical timers instead.
-- */
-- if (IS_ENABLED(CONFIG_ARM) &&
-- of_property_read_bool(np, "arm,cpu-registers-not-fw-configured"))
-- arch_timer_use_virtual = false;
--
- /*
- * If HYP mode is available, we know that the physical timer
- * has been configured to be accessible from PL1. Use it, so
-@@ -730,13 +716,39 @@ static void __init arch_timer_init(struct device_node *np)
- }
- }
-
-- arch_timer_c3stop = !of_property_read_bool(np, "always-on");
--
- arch_timer_register();
- arch_timer_common_init();
- }
--CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_init);
--CLOCKSOURCE_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_init);
-+
-+static void __init arch_timer_of_init(struct device_node *np)
-+{
-+ int i;
-+
-+ /*
-+ * If we cannot rely on firmware initializing the timer registers then
-+ * we should use the physical timers instead.
-+ */
-+ if (IS_ENABLED(CONFIG_ARM) &&
-+ of_property_read_bool(np, "arm,cpu-registers-not-fw-configured"))
-+ arch_timer_use_virtual = false;
-+
-+ if (arch_timers_present & ARCH_CP15_TIMER) {
-+ pr_warn("arch_timer: multiple nodes in dt, skipping\n");
-+ return;
-+ }
-+
-+ arch_timers_present |= ARCH_CP15_TIMER;
-+ for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++)
-+ arch_timer_ppi[i] = irq_of_parse_and_map(np, i);
-+
-+ arch_timer_detect_rate(NULL, np);
-+
-+ arch_timer_c3stop = !of_property_read_bool(np, "always-on");
-+
-+ arch_timer_init();
-+}
-+CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_of_init);
-+CLOCKSOURCE_OF_DECLARE(armv8_arch_timer, "arm,armv8-timer", arch_timer_of_init);
-
- static void __init arch_timer_mem_init(struct device_node *np)
- {
-@@ -803,3 +815,71 @@ static void __init arch_timer_mem_init(struct device_node *np)
- }
- CLOCKSOURCE_OF_DECLARE(armv7_arch_timer_mem, "arm,armv7-timer-mem",
- arch_timer_mem_init);
-+
-+#ifdef CONFIG_ACPI
-+static int __init
-+map_generic_timer_interrupt(u32 interrupt, u32 flags)
-+{
-+ int trigger, polarity;
-+
-+ if (!interrupt)
-+ return 0;
-+
-+ trigger = (flags & ACPI_GTDT_INTERRUPT_MODE) ? ACPI_EDGE_SENSITIVE
-+ : ACPI_LEVEL_SENSITIVE;
-+
-+ polarity = (flags & ACPI_GTDT_INTERRUPT_POLARITY) ? ACPI_ACTIVE_LOW
-+ : ACPI_ACTIVE_HIGH;
-+
-+ return acpi_register_gsi(NULL, interrupt, trigger, polarity);
-+}
-+
-+/* Initialize per-processor generic timer */
-+static int __init arch_timer_acpi_init(struct acpi_table_header *table)
-+{
-+ struct acpi_table_gtdt *gtdt;
-+
-+ if (arch_timers_present & ARCH_CP15_TIMER) {
-+ pr_warn("arch_timer: already initialized, skipping\n");
-+ return -EINVAL;
-+ }
-+
-+ gtdt = container_of(table, struct acpi_table_gtdt, header);
-+
-+ arch_timers_present |= ARCH_CP15_TIMER;
-+
-+ arch_timer_ppi[PHYS_SECURE_PPI] =
-+ map_generic_timer_interrupt(gtdt->secure_el1_interrupt,
-+ gtdt->secure_el1_flags);
-+
-+ arch_timer_ppi[PHYS_NONSECURE_PPI] =
-+ map_generic_timer_interrupt(gtdt->non_secure_el1_interrupt,
-+ gtdt->non_secure_el1_flags);
-+
-+ arch_timer_ppi[VIRT_PPI] =
-+ map_generic_timer_interrupt(gtdt->virtual_timer_interrupt,
-+ gtdt->virtual_timer_flags);
-+
-+ arch_timer_ppi[HYP_PPI] =
-+ map_generic_timer_interrupt(gtdt->non_secure_el2_interrupt,
-+ gtdt->non_secure_el2_flags);
-+
-+ /* Get the frequency from CNTFRQ */
-+ arch_timer_detect_rate(NULL, NULL);
-+
-+ /* Always-on capability */
-+ arch_timer_c3stop = !(gtdt->non_secure_el1_flags & ACPI_GTDT_ALWAYS_ON);
-+
-+ arch_timer_init();
-+ return 0;
-+}
-+
-+/* Initialize all the generic timers presented in GTDT */
-+void __init acpi_generic_timer_init(void)
-+{
-+ if (acpi_disabled)
-+ return;
-+
-+ acpi_table_parse(ACPI_SIG_GTDT, arch_timer_acpi_init);
-+}
-+#endif
-diff --git a/drivers/input/keyboard/gpio_keys_polled.c b/drivers/input/keyboard/gpio_keys_polled.c
-index 90df4df..c9c1c8c 100644
---- a/drivers/input/keyboard/gpio_keys_polled.c
-+++ b/drivers/input/keyboard/gpio_keys_polled.c
-@@ -297,6 +297,7 @@ static struct platform_driver gpio_keys_polled_driver = {
- .probe = gpio_keys_polled_probe,
- .driver = {
- .name = DRV_NAME,
-+ .owner = THIS_MODULE,
- .of_match_table = gpio_keys_polled_of_match,
- },
- };
-diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
-index 6cd47b7..09f904a 100644
---- a/drivers/iommu/arm-smmu.c
-+++ b/drivers/iommu/arm-smmu.c
-@@ -451,7 +451,10 @@ static struct device_node *dev_get_dev_node(struct device *dev)
-
- while (!pci_is_root_bus(bus))
- bus = bus->parent;
-- return bus->bridge->parent->of_node;
-+ if (bus->bridge->parent)
-+ return bus->bridge->parent->of_node;
-+ else
-+ return NULL;
- }
-
- return dev->of_node;
-@@ -567,6 +570,9 @@ static struct arm_smmu_device *find_smmu_for_device(struct device *dev)
- struct arm_smmu_master *master = NULL;
- struct device_node *dev_node = dev_get_dev_node(dev);
-
-+ if (!dev_node)
-+ return NULL;
-+
- spin_lock(&arm_smmu_devices_lock);
- list_for_each_entry(smmu, &arm_smmu_devices, list) {
- master = find_smmu_master(smmu, dev_node);
-diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
-index 1a146cc..ab7dfe2 100644
---- a/drivers/irqchip/irq-gic-v3.c
-+++ b/drivers/irqchip/irq-gic-v3.c
-@@ -520,9 +520,19 @@ static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
- isb();
- }
-
-+#ifdef CONFIG_ARM_PARKING_PROTOCOL
-+static void gic_wakeup_parked_cpu(int cpu)
-+{
-+ gic_raise_softirq(cpumask_of(cpu), 0);
-+}
-+#endif
-+
- static void gic_smp_init(void)
- {
- set_smp_cross_call(gic_raise_softirq);
-+#ifdef CONFIG_ARM_PARKING_PROTOCOL
-+ set_smp_boot_wakeup_call(gic_wakeup_parked_cpu);
-+#endif
- register_cpu_notifier(&gic_cpu_notifier);
- }
-
-diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
-index d617ee5..da0cd51 100644
---- a/drivers/irqchip/irq-gic.c
-+++ b/drivers/irqchip/irq-gic.c
-@@ -33,12 +33,14 @@
- #include <linux/of.h>
- #include <linux/of_address.h>
- #include <linux/of_irq.h>
-+#include <linux/acpi.h>
- #include <linux/irqdomain.h>
- #include <linux/interrupt.h>
- #include <linux/percpu.h>
- #include <linux/slab.h>
- #include <linux/irqchip/chained_irq.h>
- #include <linux/irqchip/arm-gic.h>
-+#include <linux/irqchip/arm-gic-acpi.h>
-
- #include <asm/cputype.h>
- #include <asm/irq.h>
-@@ -641,6 +643,13 @@ static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
-
- raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
- }
-+
-+#ifdef CONFIG_ARM_PARKING_PROTOCOL
-+static void gic_wakeup_parked_cpu(int cpu)
-+{
-+ gic_raise_softirq(cpumask_of(cpu), GIC_DIST_SOFTINT_NSATT);
-+}
-+#endif
- #endif
-
- #ifdef CONFIG_BL_SWITCHER
-@@ -1025,6 +1034,9 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
- #ifdef CONFIG_SMP
- set_smp_cross_call(gic_raise_softirq);
- register_cpu_notifier(&gic_cpu_notifier);
-+#ifdef CONFIG_ARM_PARKING_PROTOCOL
-+ set_smp_boot_wakeup_call(gic_wakeup_parked_cpu);
-+#endif
- #endif
- set_handle_irq(gic_handle_irq);
- }
-@@ -1083,3 +1095,109 @@ IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
- IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
-
- #endif
-+
-+#ifdef CONFIG_ACPI
-+static phys_addr_t dist_phy_base, cpu_phy_base;
-+static int cpu_base_assigned;
-+
-+static int __init
-+gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header,
-+ const unsigned long end)
-+{
-+ struct acpi_madt_generic_interrupt *processor;
-+ phys_addr_t gic_cpu_base;
-+
-+ processor = (struct acpi_madt_generic_interrupt *)header;
-+
-+ if (BAD_MADT_ENTRY(processor, end))
-+ return -EINVAL;
-+
-+ /*
-+ * There is no support for non-banked GICv1/2 register in ACPI spec.
-+ * All CPU interface addresses have to be the same.
-+ */
-+ gic_cpu_base = processor->base_address;
-+ if (cpu_base_assigned && gic_cpu_base != cpu_phy_base)
-+ return -EFAULT;
-+
-+ cpu_phy_base = gic_cpu_base;
-+ cpu_base_assigned = 1;
-+ return 0;
-+}
-+
-+static int __init
-+gic_acpi_parse_madt_distributor(struct acpi_subtable_header *header,
-+ const unsigned long end)
-+{
-+ struct acpi_madt_generic_distributor *dist;
-+
-+ dist = (struct acpi_madt_generic_distributor *)header;
-+
-+ if (BAD_MADT_ENTRY(dist, end))
-+ return -EINVAL;
-+
-+ dist_phy_base = dist->base_address;
-+ return 0;
-+}
-+
-+int __init
-+gic_v2_acpi_init(struct acpi_table_header *table)
-+{
-+ void __iomem *cpu_base, *dist_base;
-+ int count;
-+
-+ /* Collect CPU base addresses */
-+ count = acpi_parse_entries(ACPI_SIG_MADT,
-+ sizeof(struct acpi_table_madt),
-+ gic_acpi_parse_madt_cpu, table,
-+ ACPI_MADT_TYPE_GENERIC_INTERRUPT, 0);
-+ if (count < 0) {
-+ pr_err("Error during GICC entries parsing\n");
-+ return -EFAULT;
-+ } else if (!count) {
-+ pr_err("No valid GICC entries exist\n");
-+ return -EINVAL;
-+ }
-+
-+ /*
-+ * Find distributor base address. We expect one distributor entry since
-+ * ACPI 5.1 spec neither support multi-GIC instances nor GIC cascade.
-+ */
-+ count = acpi_parse_entries(ACPI_SIG_MADT,
-+ sizeof(struct acpi_table_madt),
-+ gic_acpi_parse_madt_distributor, table,
-+ ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 0);
-+ if (count <= 0) {
-+ pr_err("Error during GICD entries parsing\n");
-+ return -EFAULT;
-+ } else if (!count) {
-+ pr_err("No valid GICD entries exist\n");
-+ return -EINVAL;
-+ } else if (count > 1) {
-+ pr_err("More than one GICD entry detected\n");
-+ return -EINVAL;
-+ }
-+
-+ cpu_base = ioremap(cpu_phy_base, ACPI_GIC_CPU_IF_MEM_SIZE);
-+ if (!cpu_base) {
-+ pr_err("Unable to map GICC registers\n");
-+ return -ENOMEM;
-+ }
-+
-+ dist_base = ioremap(dist_phy_base, ACPI_GICV2_DIST_MEM_SIZE);
-+ if (!dist_base) {
-+ pr_err("Unable to map GICD registers\n");
-+ iounmap(cpu_base);
-+ return -ENOMEM;
-+ }
-+
-+ /*
-+ * Initialize zero GIC instance (no multi-GIC support). Also, set GIC
-+ * as default IRQ domain to allow for GSI registration and GSI to IRQ
-+ * number translation (see acpi_register_gsi() and acpi_gsi_to_irq()).
-+ */
-+ gic_init_bases(0, -1, dist_base, cpu_base, 0, NULL);
-+ irq_set_default_host(gic_data[0].domain);
-+ return 0;
-+}
-+#endif
-diff --git a/drivers/irqchip/irqchip.c b/drivers/irqchip/irqchip.c
-index 0fe2f71..9106c6d 100644
---- a/drivers/irqchip/irqchip.c
-+++ b/drivers/irqchip/irqchip.c
-@@ -11,6 +11,7 @@
- #include <linux/init.h>
- #include <linux/of_irq.h>
- #include <linux/irqchip.h>
-+#include <linux/irqchip/arm-gic-acpi.h>
-
- /*
- * This special of_device_id is the sentinel at the end of the
-@@ -26,4 +27,6 @@ extern struct of_device_id __irqchip_of_table[];
- void __init irqchip_init(void)
- {
- of_irq_init(__irqchip_of_table);
-+
-+ acpi_gic_init();
- }
-diff --git a/drivers/leds/leds-gpio.c b/drivers/leds/leds-gpio.c
-index 7ea1ea42..5fb4440 100644
---- a/drivers/leds/leds-gpio.c
-+++ b/drivers/leds/leds-gpio.c
-@@ -291,6 +291,7 @@ static struct platform_driver gpio_led_driver = {
- .remove = gpio_led_remove,
- .driver = {
- .name = "leds-gpio",
-+ .owner = THIS_MODULE,
- .of_match_table = of_gpio_leds_match,
- },
- };
-diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
-index 53f5f66..3957e63 100644
---- a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
-+++ b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
-@@ -130,7 +130,7 @@ static unsigned int xgbe_usec_to_riwt(struct xgbe_prv_data *pdata,
-
- DBGPR("-->xgbe_usec_to_riwt\n");
-
-- rate = clk_get_rate(pdata->sysclk);
-+ rate = pdata->sysclk_rate;
-
- /*
- * Convert the input usec value to the watchdog timer value. Each
-@@ -153,7 +153,7 @@ static unsigned int xgbe_riwt_to_usec(struct xgbe_prv_data *pdata,
-
- DBGPR("-->xgbe_riwt_to_usec\n");
-
-- rate = clk_get_rate(pdata->sysclk);
-+ rate = pdata->sysclk_rate;
-
- /*
- * Convert the input watchdog timer value to the usec value. Each
-@@ -854,6 +854,18 @@ static int xgbe_read_mmd_regs(struct xgbe_prv_data *pdata, int prtad,
- else
- mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
-
-+ if (XGBE_SEATTLE_A0) {
-+ /* The PCS implementation has reversed the devices in
-+ * package registers so we need to change 05 to 06 and
-+ * 06 to 05 if being read (these registers are readonly
-+ * so no need to do this in the write function)
-+ */
-+ if ((mmd_address & 0xffff) == 0x05)
-+ mmd_address = (mmd_address & ~0xffff) | 0x06;
-+ else if ((mmd_address & 0xffff) == 0x06)
-+ mmd_address = (mmd_address & ~0xffff) | 0x05;
-+ }
-+
- /* The PCS registers are accessed using mmio. The underlying APB3
- * management interface uses indirect addressing to access the MMD
- * register sets. This requires accessing of the PCS register in two
-diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-main.c b/drivers/net/ethernet/amd/xgbe/xgbe-main.c
-index dbd3850..74be78e 100644
---- a/drivers/net/ethernet/amd/xgbe/xgbe-main.c
-+++ b/drivers/net/ethernet/amd/xgbe/xgbe-main.c
-@@ -124,6 +124,7 @@
- #include <linux/of.h>
- #include <linux/of_net.h>
- #include <linux/clk.h>
-+#include <linux/acpi.h>
-
- #include "xgbe.h"
- #include "xgbe-common.h"
-@@ -161,6 +162,205 @@ static void xgbe_init_all_fptrs(struct xgbe_prv_data *pdata)
- xgbe_init_function_ptrs_desc(&pdata->desc_if);
- }
-
-+static int xgbe_map_resources(struct xgbe_prv_data *pdata)
-+{
-+ struct platform_device *pdev = pdata->pdev;
-+ struct device *dev = pdata->dev;
-+ struct resource *res;
-+
-+ /* Obtain the mmio areas for the device */
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ pdata->xgmac_regs = devm_ioremap_resource(dev, res);
-+ if (IS_ERR(pdata->xgmac_regs)) {
-+ dev_err(dev, "xgmac ioremap failed\n");
-+ return PTR_ERR(pdata->xgmac_regs);
-+ }
-+ DBGPR(" xgmac_regs = %p\n", pdata->xgmac_regs);
-+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-+ pdata->xpcs_regs = devm_ioremap_resource(dev, res);
-+ if (IS_ERR(pdata->xpcs_regs)) {
-+ dev_err(dev, "xpcs ioremap failed\n");
-+ return PTR_ERR(pdata->xpcs_regs);
-+ }
-+ DBGPR(" xpcs_regs = %p\n", pdata->xpcs_regs);
-+
-+ return 0;
-+}
-+
-+#ifdef CONFIG_ACPI
-+static int xgbe_acpi_support(struct xgbe_prv_data *pdata)
-+{
-+ struct acpi_device *adev = pdata->adev;
-+ struct device *dev = pdata->dev;
-+ const union acpi_object *property;
-+ acpi_status status;
-+ u64 cca;
-+ unsigned int i;
-+ int ret;
-+
-+ /* Map the memory resources */
-+ ret = xgbe_map_resources(pdata);
-+ if (ret)
-+ return ret;
-+
-+ /* Obtain the system clock setting */
-+ ret = acpi_dev_get_property(adev, XGBE_ACPI_DMA_FREQ, ACPI_TYPE_INTEGER,
-+ &property);
-+ if (ret) {
-+ dev_err(dev, "unable to obtain %s acpi property\n",
-+ XGBE_ACPI_DMA_FREQ);
-+ return ret;
-+ }
-+ pdata->sysclk_rate = property->integer.value;
-+
-+ /* Obtain the PTP clock setting */
-+ ret = acpi_dev_get_property(adev, XGBE_ACPI_PTP_FREQ, ACPI_TYPE_INTEGER,
-+ &property);
-+ if (ret) {
-+ dev_err(dev, "unable to obtain %s acpi property\n",
-+ XGBE_ACPI_PTP_FREQ);
-+ return ret;
-+ }
-+ pdata->ptpclk_rate = property->integer.value;
-+
-+ /* Retrieve the MAC address */
-+ ret = acpi_dev_get_property_array(adev, XGBE_ACPI_MAC_ADDR,
-+ ACPI_TYPE_INTEGER, &property);
-+ if (ret) {
-+ dev_err(dev, "unable to obtain %s acpi property\n",
-+ XGBE_ACPI_MAC_ADDR);
-+ return ret;
-+ }
-+ if (property->package.count != 6) {
-+ dev_err(dev, "invalid %s acpi property\n",
-+ XGBE_ACPI_MAC_ADDR);
-+ return -EINVAL;
-+ }
-+ for (i = 0; i < property->package.count; i++) {
-+ union acpi_object *obj = &property->package.elements[i];
-+
-+ pdata->mac_addr[i] = (u8)obj->integer.value;
-+ }
-+ if (!is_valid_ether_addr(pdata->mac_addr)) {
-+ dev_err(dev, "invalid %s acpi property\n",
-+ XGBE_ACPI_MAC_ADDR);
-+ return -EINVAL;
-+ }
-+
-+ /* Retrieve the PHY mode - it must be "xgmii" */
-+ ret = acpi_dev_get_property(adev, XGBE_ACPI_PHY_MODE, ACPI_TYPE_STRING,
-+ &property);
-+ if (ret) {
-+ dev_err(dev, "unable to obtain %s acpi property\n",
-+ XGBE_ACPI_PHY_MODE);
-+ return ret;
-+ }
-+ if (strcmp(property->string.pointer,
-+ phy_modes(PHY_INTERFACE_MODE_XGMII))) {
-+ dev_err(dev, "invalid %s acpi property\n",
-+ XGBE_ACPI_PHY_MODE);
-+ return -EINVAL;
-+ }
-+ pdata->phy_mode = PHY_INTERFACE_MODE_XGMII;
-+
-+#ifndef METHOD_NAME__CCA
-+#define METHOD_NAME__CCA "_CCA"
-+#endif
-+ /* Set the device cache coherency values */
-+ if (acpi_has_method(adev->handle, METHOD_NAME__CCA)) {
-+ status = acpi_evaluate_integer(adev->handle, METHOD_NAME__CCA,
-+ NULL, &cca);
-+ if (ACPI_FAILURE(status)) {
-+ dev_err(dev, "error obtaining acpi _CCA method\n");
-+ return -EINVAL;
-+ }
-+ } else {
-+ cca = 0;
-+ }
-+
-+ if (cca) {
-+ pdata->axdomain = XGBE_DMA_OS_AXDOMAIN;
-+ pdata->arcache = XGBE_DMA_OS_ARCACHE;
-+ pdata->awcache = XGBE_DMA_OS_AWCACHE;
-+ } else {
-+ pdata->axdomain = XGBE_DMA_SYS_AXDOMAIN;
-+ pdata->arcache = XGBE_DMA_SYS_ARCACHE;
-+ pdata->awcache = XGBE_DMA_SYS_AWCACHE;
-+ }
-+
-+ return 0;
-+}
-+#else /* CONFIG_ACPI */
-+static int xgbe_acpi_support(struct xgbe_prv_data *pdata)
-+{
-+ return -EINVAL;
-+}
-+#endif /* CONFIG_ACPI */
-+
-+#ifdef CONFIG_OF
-+static int xgbe_of_support(struct xgbe_prv_data *pdata)
-+{
-+ struct device *dev = pdata->dev;
-+ const u8 *mac_addr;
-+ int ret;
-+
-+ /* Map the memory resources */
-+ ret = xgbe_map_resources(pdata);
-+ if (ret)
-+ return ret;
-+
-+ /* Obtain the system clock setting */
-+ pdata->sysclk = devm_clk_get(dev, XGBE_DMA_CLOCK);
-+ if (IS_ERR(pdata->sysclk)) {
-+ dev_err(dev, "dma devm_clk_get failed\n");
-+ return PTR_ERR(pdata->sysclk);
-+ }
-+ pdata->sysclk_rate = clk_get_rate(pdata->sysclk);
-+
-+ /* Obtain the PTP clock setting */
-+ pdata->ptpclk = devm_clk_get(dev, XGBE_PTP_CLOCK);
-+ if (IS_ERR(pdata->ptpclk)) {
-+ dev_err(dev, "ptp devm_clk_get failed\n");
-+ return PTR_ERR(pdata->ptpclk);
-+ }
-+ pdata->ptpclk_rate = clk_get_rate(pdata->ptpclk);
-+
-+ /* Retrieve the MAC address */
-+ mac_addr = of_get_mac_address(dev->of_node);
-+ if (!mac_addr) {
-+ dev_err(dev, "invalid mac address for this device\n");
-+ return -EINVAL;
-+ }
-+ memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
-+
-+ /* Retrieve the PHY mode - it must be "xgmii" */
-+ pdata->phy_mode = of_get_phy_mode(dev->of_node);
-+ if (pdata->phy_mode != PHY_INTERFACE_MODE_XGMII) {
-+ dev_err(dev, "invalid phy-mode specified for this device\n");
-+ return -EINVAL;
-+ }
-+
-+ /* Set the device cache coherency values */
-+ if (of_property_read_bool(dev->of_node, "dma-coherent")) {
-+ pdata->axdomain = XGBE_DMA_OS_AXDOMAIN;
-+ pdata->arcache = XGBE_DMA_OS_ARCACHE;
-+ pdata->awcache = XGBE_DMA_OS_AWCACHE;
-+ } else {
-+ pdata->axdomain = XGBE_DMA_SYS_AXDOMAIN;
-+ pdata->arcache = XGBE_DMA_SYS_ARCACHE;
-+ pdata->awcache = XGBE_DMA_SYS_AWCACHE;
-+ }
-+
-+ return 0;
-+}
-+#else /* CONFIG_OF */
-+static int xgbe_of_support(struct xgbe_prv_data *pdata)
-+{
-+ return -EINVAL;
-+}
-+#endif /*CONFIG_OF */
-+
- static int xgbe_probe(struct platform_device *pdev)
- {
- struct xgbe_prv_data *pdata;
-@@ -186,6 +386,7 @@ static int xgbe_probe(struct platform_device *pdev)
- pdata = netdev_priv(netdev);
- pdata->netdev = netdev;
- pdata->pdev = pdev;
-+ pdata->adev = ACPI_COMPANION(dev);
- pdata->dev = dev;
- platform_set_drvdata(pdev, netdev);
-
-@@ -212,40 +413,13 @@ static int xgbe_probe(struct platform_device *pdev)
- goto err_io;
- }
-
-- /* Obtain the system clock setting */
-- pdata->sysclk = devm_clk_get(dev, XGBE_DMA_CLOCK);
-- if (IS_ERR(pdata->sysclk)) {
-- dev_err(dev, "dma devm_clk_get failed\n");
-- ret = PTR_ERR(pdata->sysclk);
-- goto err_io;
-- }
--
-- /* Obtain the PTP clock setting */
-- pdata->ptpclk = devm_clk_get(dev, XGBE_PTP_CLOCK);
-- if (IS_ERR(pdata->ptpclk)) {
-- dev_err(dev, "ptp devm_clk_get failed\n");
-- ret = PTR_ERR(pdata->ptpclk);
-- goto err_io;
-- }
--
-- /* Obtain the mmio areas for the device */
-- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-- pdata->xgmac_regs = devm_ioremap_resource(dev, res);
-- if (IS_ERR(pdata->xgmac_regs)) {
-- dev_err(dev, "xgmac ioremap failed\n");
-- ret = PTR_ERR(pdata->xgmac_regs);
-- goto err_io;
-- }
-- DBGPR(" xgmac_regs = %p\n", pdata->xgmac_regs);
--
-- res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-- pdata->xpcs_regs = devm_ioremap_resource(dev, res);
-- if (IS_ERR(pdata->xpcs_regs)) {
-- dev_err(dev, "xpcs ioremap failed\n");
-- ret = PTR_ERR(pdata->xpcs_regs);
-+ /* Obtain device settings */
-+ if (pdata->adev && !acpi_disabled)
-+ ret = xgbe_acpi_support(pdata);
-+ else
-+ ret = xgbe_of_support(pdata);
-+ if (ret)
- goto err_io;
-- }
-- DBGPR(" xpcs_regs = %p\n", pdata->xpcs_regs);
-
- /* Set the DMA mask */
- if (!dev->dma_mask)
-@@ -275,10 +449,12 @@ static int xgbe_probe(struct platform_device *pdev)
- dev_err(dev, "platform_get_irq 0 failed\n");
- goto err_io;
- }
-+
- pdata->dev_irq = ret;
-
- netdev->irq = pdata->dev_irq;
- netdev->base_addr = (unsigned long)pdata->xgmac_regs;
-+ memcpy(netdev->dev_addr, pdata->mac_addr, netdev->addr_len);
-
- /* Set all the function pointers */
- xgbe_init_all_fptrs(pdata);
-@@ -291,23 +467,6 @@ static int xgbe_probe(struct platform_device *pdev)
- /* Populate the hardware features */
- xgbe_get_all_hw_features(pdata);
-
-- /* Retrieve the MAC address */
-- mac_addr = of_get_mac_address(dev->of_node);
-- if (!mac_addr) {
-- dev_err(dev, "invalid mac address for this device\n");
-- ret = -EINVAL;
-- goto err_io;
-- }
-- memcpy(netdev->dev_addr, mac_addr, netdev->addr_len);
--
-- /* Retrieve the PHY mode - it must be "xgmii" */
-- pdata->phy_mode = of_get_phy_mode(dev->of_node);
-- if (pdata->phy_mode != PHY_INTERFACE_MODE_XGMII) {
-- dev_err(dev, "invalid phy-mode specified for this device\n");
-- ret = -EINVAL;
-- goto err_io;
-- }
--
- /* Set default configuration data */
- xgbe_default_config(pdata);
-
-@@ -491,10 +650,22 @@ static int xgbe_resume(struct device *dev)
- }
- #endif /* CONFIG_PM */
-
-+#ifdef CONFIG_ACPI
-+static const struct acpi_device_id xgbe_acpi_match[] = {
-+ { "AMDI8000", 0 },
-+ {},
-+};
-+
-+MODULE_DEVICE_TABLE(acpi, xgbe_acpi_match);
-+#endif
-+
-+#ifdef CONFIG_OF
- static const struct of_device_id xgbe_of_match[] = {
-+ { .compatible = "amd,xgbe-seattle-v0a", },
- { .compatible = "amd,xgbe-seattle-v1a", },
- {},
- };
-+#endif
-
- MODULE_DEVICE_TABLE(of, xgbe_of_match);
- static SIMPLE_DEV_PM_OPS(xgbe_pm_ops, xgbe_suspend, xgbe_resume);
-@@ -502,7 +673,12 @@ static SIMPLE_DEV_PM_OPS(xgbe_pm_ops, xgbe_suspend, xgbe_resume);
- static struct platform_driver xgbe_driver = {
- .driver = {
- .name = "amd-xgbe",
-+#ifdef CONFIG_ACPI
-+ .acpi_match_table = xgbe_acpi_match,
-+#endif
-+#ifdef CONFIG_OF
- .of_match_table = xgbe_of_match,
-+#endif
- .pm = &xgbe_pm_ops,
- },
- .probe = xgbe_probe,
-diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c b/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c
-index 363b210..5d2c89b 100644
---- a/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c
-+++ b/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c
-@@ -119,6 +119,7 @@
- #include <linux/mdio.h>
- #include <linux/phy.h>
- #include <linux/of.h>
-+#include <linux/acpi.h>
-
- #include "xgbe.h"
- #include "xgbe-common.h"
-@@ -205,25 +206,16 @@ void xgbe_dump_phy_registers(struct xgbe_prv_data *pdata)
-
- int xgbe_mdio_register(struct xgbe_prv_data *pdata)
- {
-- struct device_node *phy_node;
- struct mii_bus *mii;
- struct phy_device *phydev;
- int ret = 0;
-
- DBGPR("-->xgbe_mdio_register\n");
-
-- /* Retrieve the phy-handle */
-- phy_node = of_parse_phandle(pdata->dev->of_node, "phy-handle", 0);
-- if (!phy_node) {
-- dev_err(pdata->dev, "unable to parse phy-handle\n");
-- return -EINVAL;
-- }
--
- mii = mdiobus_alloc();
- if (mii == NULL) {
- dev_err(pdata->dev, "mdiobus_alloc failed\n");
-- ret = -ENOMEM;
-- goto err_node_get;
-+ return -ENOMEM;
- }
-
- /* Register on the MDIO bus (don't probe any PHYs) */
-@@ -252,12 +244,9 @@ int xgbe_mdio_register(struct xgbe_prv_data *pdata)
- request_module(MDIO_MODULE_PREFIX MDIO_ID_FMT,
- MDIO_ID_ARGS(phydev->c45_ids.device_ids[MDIO_MMD_PCS]));
-
-- of_node_get(phy_node);
-- phydev->dev.of_node = phy_node;
- ret = phy_device_register(phydev);
- if (ret) {
- dev_err(pdata->dev, "phy_device_register failed\n");
-- of_node_put(phy_node);
- goto err_phy_device;
- }
-
-@@ -283,8 +272,6 @@ int xgbe_mdio_register(struct xgbe_prv_data *pdata)
-
- pdata->phydev = phydev;
-
-- of_node_put(phy_node);
--
- DBGPHY_REGS(pdata);
-
- DBGPR("<--xgbe_mdio_register\n");
-@@ -300,9 +287,6 @@ err_mdiobus_register:
- err_mdiobus_alloc:
- mdiobus_free(mii);
-
--err_node_get:
-- of_node_put(phy_node);
--
- return ret;
- }
-
-diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-ptp.c b/drivers/net/ethernet/amd/xgbe/xgbe-ptp.c
-index a1bf9d1c..fa67203 100644
---- a/drivers/net/ethernet/amd/xgbe/xgbe-ptp.c
-+++ b/drivers/net/ethernet/amd/xgbe/xgbe-ptp.c
-@@ -239,7 +239,7 @@ void xgbe_ptp_register(struct xgbe_prv_data *pdata)
- snprintf(info->name, sizeof(info->name), "%s",
- netdev_name(pdata->netdev));
- info->owner = THIS_MODULE;
-- info->max_adj = clk_get_rate(pdata->ptpclk);
-+ info->max_adj = pdata->ptpclk_rate;
- info->adjfreq = xgbe_adjfreq;
- info->adjtime = xgbe_adjtime;
- info->gettime = xgbe_gettime;
-@@ -260,7 +260,7 @@ void xgbe_ptp_register(struct xgbe_prv_data *pdata)
- */
- dividend = 50000000;
- dividend <<= 32;
-- pdata->tstamp_addend = div_u64(dividend, clk_get_rate(pdata->ptpclk));
-+ pdata->tstamp_addend = div_u64(dividend, pdata->ptpclk_rate);
-
- /* Setup the timecounter */
- cc->read = xgbe_cc_read;
-diff --git a/drivers/net/ethernet/amd/xgbe/xgbe.h b/drivers/net/ethernet/amd/xgbe/xgbe.h
-index f9ec762..6f3a39e 100644
---- a/drivers/net/ethernet/amd/xgbe/xgbe.h
-+++ b/drivers/net/ethernet/amd/xgbe/xgbe.h
-@@ -187,6 +187,12 @@
- #define XGBE_PTP_CLOCK "ptp_clk"
- #define XGBE_DMA_IRQS "amd,per-channel-interrupt"
-
-+/* ACPI property names */
-+#define XGBE_ACPI_MAC_ADDR "mac-address"
-+#define XGBE_ACPI_PHY_MODE "phy-mode"
-+#define XGBE_ACPI_DMA_FREQ "amd,dma-freq"
-+#define XGBE_ACPI_PTP_FREQ "amd,ptp-freq"
-+
- /* Timestamp support - values based on 50MHz PTP clock
- * 50MHz => 20 nsec
- */
-@@ -201,8 +207,11 @@
- #define XGBE_FIFO_SIZE_B(x) (x)
- #define XGBE_FIFO_SIZE_KB(x) (x * 1024)
-
-+#define XGBE_TC_CNT 2
- #define XGBE_TC_MIN_QUANTUM 10
-
-+#define XGBE_SEATTLE_A0 ((read_cpuid_id() & 0x00f0000f) == 0)
-+
- /* Helper macro for descriptor handling
- * Always use XGBE_GET_DESC_DATA to access the descriptor data
- * since the index is free-running and needs to be and-ed
-@@ -650,6 +659,7 @@ struct xgbe_hw_features {
- struct xgbe_prv_data {
- struct net_device *netdev;
- struct platform_device *pdev;
-+ struct acpi_device *adev;
- struct device *dev;
-
- /* XGMAC/XPCS related mmio registers */
-@@ -739,6 +749,7 @@ struct xgbe_prv_data {
- unsigned int phy_rx_pause;
-
- /* Netdev related settings */
-+ unsigned char mac_addr[MAX_ADDR_LEN];
- netdev_features_t netdev_features;
- struct napi_struct napi;
- struct xgbe_mmc_stats mmc_stats;
-@@ -748,7 +759,9 @@ struct xgbe_prv_data {
-
- /* Device clocks */
- struct clk *sysclk;
-+ unsigned long sysclk_rate;
- struct clk *ptpclk;
-+ unsigned long ptpclk_rate;
-
- /* Timestamp support */
- spinlock_t tstamp_lock;
-diff --git a/drivers/net/ethernet/apm/xgene/xgene_enet_hw.c b/drivers/net/ethernet/apm/xgene/xgene_enet_hw.c
-index 7ba83ff..29aad5e 100644
---- a/drivers/net/ethernet/apm/xgene/xgene_enet_hw.c
-+++ b/drivers/net/ethernet/apm/xgene/xgene_enet_hw.c
-@@ -663,15 +663,20 @@ static int xgene_enet_phy_connect(struct net_device *ndev)
- struct phy_device *phy_dev;
- struct device *dev = &pdata->pdev->dev;
-
-- phy_np = of_parse_phandle(dev->of_node, "phy-handle", 0);
-- if (!phy_np) {
-- netdev_dbg(ndev, "No phy-handle found\n");
-- return -ENODEV;
-+ if (dev->of_node) {
-+ phy_np = of_parse_phandle(dev->of_node, "phy-handle", 0);
-+ if (!phy_np) {
-+ netdev_dbg(ndev, "No phy-handle found in DT\n");
-+ return -ENODEV;
-+ }
-+ pdata->phy_dev = of_phy_find_device(phy_np);
- }
-
-- phy_dev = of_phy_connect(ndev, phy_np, &xgene_enet_adjust_link,
-- 0, pdata->phy_mode);
-- if (!phy_dev) {
-+ phy_dev = pdata->phy_dev;
-+
-+ if (phy_dev == NULL ||
-+ phy_connect_direct(ndev, phy_dev, &xgene_enet_adjust_link,
-+ pdata->phy_mode)) {
- netdev_err(ndev, "Could not connect to PHY\n");
- return -ENODEV;
- }
-@@ -681,11 +686,52 @@ static int xgene_enet_phy_connect(struct net_device *ndev)
- ~SUPPORTED_100baseT_Half &
- ~SUPPORTED_1000baseT_Half;
- phy_dev->advertising = phy_dev->supported;
-- pdata->phy_dev = phy_dev;
-
- return 0;
- }
-
-+#ifdef CONFIG_ACPI
-+static int xgene_acpi_mdiobus_register(struct xgene_enet_pdata *pdata,
-+ struct mii_bus *mdio)
-+{
-+ struct device *dev = &pdata->pdev->dev;
-+ struct phy_device *phy;
-+ int i, ret;
-+ u32 phy_id;
-+
-+ /* Mask out all PHYs from auto probing. */
-+ mdio->phy_mask = ~0;
-+
-+ /* Clear all the IRQ properties */
-+ if (mdio->irq)
-+ for (i = 0; i < PHY_MAX_ADDR; i++)
-+ mdio->irq[i] = PHY_POLL;
-+
-+ /* Register the MDIO bus */
-+ ret = mdiobus_register(mdio);
-+ if (ret)
-+ return ret;
-+
-+ ret = device_property_read_u32(dev, "phy-channel", &phy_id);
-+ if (ret)
-+ return -EINVAL;
-+
-+ phy = get_phy_device(mdio, phy_id, true);
-+ if (!phy || IS_ERR(phy))
-+ return -EIO;
-+
-+ ret = phy_device_register(phy);
-+ if (ret)
-+ phy_device_free(phy);
-+ else
-+ pdata->phy_dev = phy;
-+
-+ return ret;
-+}
-+#else
-+#define xgene_acpi_mdiobus_register(a, b) -1
-+#endif
-+
- int xgene_enet_mdio_config(struct xgene_enet_pdata *pdata)
- {
- struct net_device *ndev = pdata->ndev;
-@@ -702,7 +748,7 @@ int xgene_enet_mdio_config(struct xgene_enet_pdata *pdata)
- }
- }
-
-- if (!mdio_np) {
-+ if (dev->of_node && !mdio_np) {
- netdev_dbg(ndev, "No mdio node in the dts\n");
- return -ENXIO;
- }
-@@ -720,7 +766,10 @@ int xgene_enet_mdio_config(struct xgene_enet_pdata *pdata)
- mdio_bus->priv = pdata;
- mdio_bus->parent = &ndev->dev;
-
-- ret = of_mdiobus_register(mdio_bus, mdio_np);
-+ if (dev->of_node)
-+ ret = of_mdiobus_register(mdio_bus, mdio_np);
-+ else
-+ ret = xgene_acpi_mdiobus_register(pdata, mdio_bus);
- if (ret) {
- netdev_err(ndev, "Failed to register MDIO bus\n");
- mdiobus_free(mdio_bus);
-diff --git a/drivers/net/ethernet/apm/xgene/xgene_enet_main.c b/drivers/net/ethernet/apm/xgene/xgene_enet_main.c
-index 83a5028..f66598a 100644
---- a/drivers/net/ethernet/apm/xgene/xgene_enet_main.c
-+++ b/drivers/net/ethernet/apm/xgene/xgene_enet_main.c
-@@ -746,6 +746,42 @@ static const struct net_device_ops xgene_ndev_ops = {
- .ndo_set_mac_address = xgene_enet_set_mac_address,
- };
-
-+#ifdef CONFIG_ACPI
-+static int acpi_get_mac_address(struct device *dev,
-+ unsigned char *addr)
-+{
-+ int ret;
-+
-+ ret = device_property_read_u8_array(dev, "mac-address", addr, 6);
-+ if (ret)
-+ return 0;
-+
-+ return 6;
-+}
-+
-+static int acpi_get_phy_mode(struct device *dev)
-+{
-+ int i, ret, phy_mode;
-+ char *modestr;
-+
-+ ret = device_property_read_string(dev, "phy-mode", &modestr);
-+ if (ret)
-+ return -1;
-+
-+ phy_mode = -1;
-+ for (i = 0; i < PHY_INTERFACE_MODE_MAX; i++) {
-+ if (!strcasecmp(modestr, phy_modes(i))) {
-+ phy_mode = i;
-+ break;
-+ }
-+ }
-+ return phy_mode;
-+}
-+#else
-+#define acpi_get_mac_address(a, b, c) 0
-+#define acpi_get_phy_mode(a) -1
-+#endif
-+
- static int xgene_enet_get_resources(struct xgene_enet_pdata *pdata)
- {
- struct platform_device *pdev;
-@@ -761,6 +797,12 @@ static int xgene_enet_get_resources(struct xgene_enet_pdata *pdata)
- ndev = pdata->ndev;
-
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "enet_csr");
-+ if (!res)
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ if (!res) {
-+ dev_err(dev, "Resource enet_csr not defined\n");
-+ return -ENODEV;
-+ }
- pdata->base_addr = devm_ioremap_resource(dev, res);
- if (IS_ERR(pdata->base_addr)) {
- dev_err(dev, "Unable to retrieve ENET Port CSR region\n");
-@@ -768,6 +810,12 @@ static int xgene_enet_get_resources(struct xgene_enet_pdata *pdata)
- }
-
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ring_csr");
-+ if (!res)
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-+ if (!res) {
-+ dev_err(dev, "Resource ring_csr not defined\n");
-+ return -ENODEV;
-+ }
- pdata->ring_csr_addr = devm_ioremap_resource(dev, res);
- if (IS_ERR(pdata->ring_csr_addr)) {
- dev_err(dev, "Unable to retrieve ENET Ring CSR region\n");
-@@ -775,6 +823,12 @@ static int xgene_enet_get_resources(struct xgene_enet_pdata *pdata)
- }
-
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ring_cmd");
-+ if (!res)
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
-+ if (!res) {
-+ dev_err(dev, "Resource ring_cmd not defined\n");
-+ return -ENODEV;
-+ }
- pdata->ring_cmd_addr = devm_ioremap_resource(dev, res);
- if (IS_ERR(pdata->ring_cmd_addr)) {
- dev_err(dev, "Unable to retrieve ENET Ring command region\n");
-@@ -792,11 +846,13 @@ static int xgene_enet_get_resources(struct xgene_enet_pdata *pdata)
- mac = of_get_mac_address(dev->of_node);
- if (mac)
- memcpy(ndev->dev_addr, mac, ndev->addr_len);
-- else
-+ else if (!acpi_get_mac_address(dev, ndev->dev_addr))
- eth_hw_addr_random(ndev);
- memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
-
- pdata->phy_mode = of_get_phy_mode(pdev->dev.of_node);
-+ if (pdata->phy_mode < 0)
-+ pdata->phy_mode = acpi_get_phy_mode(dev);
- if (pdata->phy_mode < 0) {
- dev_err(dev, "Unable to get phy-connection-type\n");
- return pdata->phy_mode;
-@@ -809,11 +865,12 @@ static int xgene_enet_get_resources(struct xgene_enet_pdata *pdata)
- }
-
- pdata->clk = devm_clk_get(&pdev->dev, NULL);
-- ret = IS_ERR(pdata->clk);
- if (IS_ERR(pdata->clk)) {
-- dev_err(&pdev->dev, "can't get clock\n");
-- ret = PTR_ERR(pdata->clk);
-- return ret;
-+ /*
-+ * Not necessarily an error. Firmware may have
-+ * set up the clock already.
-+ */
-+ pdata->clk = NULL;
- }
-
- base_addr = pdata->base_addr;
-@@ -863,7 +920,7 @@ static int xgene_enet_init_hw(struct xgene_enet_pdata *pdata)
- pdata->port_ops->cle_bypass(pdata, dst_ring_num, buf_pool->id);
- pdata->mac_ops->init(pdata);
-
-- return ret;
-+ return 0;
- }
-
- static void xgene_enet_setup_ops(struct xgene_enet_pdata *pdata)
-@@ -924,7 +981,7 @@ static int xgene_enet_probe(struct platform_device *pdev)
- goto err;
- }
-
-- ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
-+ ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(64));
- if (ret) {
- netdev_err(ndev, "No usable DMA configuration\n");
- goto err;
-@@ -972,6 +1029,14 @@ static int xgene_enet_remove(struct platform_device *pdev)
- return 0;
- }
-
-+#ifdef CONFIG_ACPI
-+static const struct acpi_device_id xgene_enet_acpi_match[] = {
-+ { "APMC0D05", },
-+ { }
-+};
-+MODULE_DEVICE_TABLE(acpi, xgene_enet_acpi_match);
-+#endif
-+
- static struct of_device_id xgene_enet_match[] = {
- {.compatible = "apm,xgene-enet",},
- {},
-@@ -983,6 +1048,7 @@ static struct platform_driver xgene_enet_driver = {
- .driver = {
- .name = "xgene-enet",
- .of_match_table = xgene_enet_match,
-+ .acpi_match_table = ACPI_PTR(xgene_enet_acpi_match),
- },
- .probe = xgene_enet_probe,
- .remove = xgene_enet_remove,
-diff --git a/drivers/net/ethernet/apm/xgene/xgene_enet_main.h b/drivers/net/ethernet/apm/xgene/xgene_enet_main.h
-index f9958fa..0e06cad 100644
---- a/drivers/net/ethernet/apm/xgene/xgene_enet_main.h
-+++ b/drivers/net/ethernet/apm/xgene/xgene_enet_main.h
-@@ -31,6 +31,7 @@
- #include <linux/prefetch.h>
- #include <linux/if_vlan.h>
- #include <linux/phy.h>
-+#include <linux/acpi.h>
- #include "xgene_enet_hw.h"
-
- #define XGENE_DRV_VERSION "v1.0"
-diff --git a/drivers/net/ethernet/smsc/smc91x.c b/drivers/net/ethernet/smsc/smc91x.c
-index 88a55f9..944b177 100644
---- a/drivers/net/ethernet/smsc/smc91x.c
-+++ b/drivers/net/ethernet/smsc/smc91x.c
-@@ -82,6 +82,7 @@ static const char version[] =
- #include <linux/of.h>
- #include <linux/of_device.h>
- #include <linux/of_gpio.h>
-+#include <linux/acpi.h>
-
- #include <linux/netdevice.h>
- #include <linux/etherdevice.h>
-@@ -2467,6 +2468,14 @@ static struct dev_pm_ops smc_drv_pm_ops = {
- .resume = smc_drv_resume,
- };
-
-+#ifdef CONFIG_ACPI
-+static const struct acpi_device_id smc91x_acpi_match[] = {
-+ { "LNRO0003", },
-+ { }
-+};
-+MODULE_DEVICE_TABLE(acpi, smc91x_acpi_match);
-+#endif
-+
- static struct platform_driver smc_driver = {
- .probe = smc_drv_probe,
- .remove = smc_drv_remove,
-@@ -2474,6 +2483,7 @@ static struct platform_driver smc_driver = {
- .name = CARDNAME,
- .pm = &smc_drv_pm_ops,
- .of_match_table = of_match_ptr(smc91x_match),
-+ .acpi_match_table = ACPI_PTR(smc91x_acpi_match),
- },
- };
-
-diff --git a/drivers/net/phy/amd-xgbe-phy.c b/drivers/net/phy/amd-xgbe-phy.c
-index 903dc3d..fcc4fc7 100644
---- a/drivers/net/phy/amd-xgbe-phy.c
-+++ b/drivers/net/phy/amd-xgbe-phy.c
-@@ -74,15 +74,19 @@
- #include <linux/of_platform.h>
- #include <linux/of_device.h>
- #include <linux/uaccess.h>
-+#include <linux/acpi.h>
-+
-
- MODULE_AUTHOR("Tom Lendacky <thomas.lendacky at amd.com>");
- MODULE_LICENSE("Dual BSD/GPL");
--MODULE_VERSION("1.0.0-a");
-+MODULE_VERSION("0.0.0-a");
- MODULE_DESCRIPTION("AMD 10GbE (amd-xgbe) PHY driver");
-
--#define XGBE_PHY_ID 0x000162d0
-+#define XGBE_PHY_ID 0x7996ced0
- #define XGBE_PHY_MASK 0xfffffff0
-
-+#define XGBE_PHY_SERDES_RETRY 32
-+#define XGBE_PHY_CHANNEL_PROPERTY "amd,serdes-channel"
- #define XGBE_PHY_SPEEDSET_PROPERTY "amd,speed-set"
-
- #define XGBE_AN_INT_CMPLT 0x01
-@@ -99,11 +103,9 @@ MODULE_DESCRIPTION("AMD 10GbE (amd-xgbe) PHY driver");
- #ifndef MDIO_PMA_10GBR_PMD_CTRL
- #define MDIO_PMA_10GBR_PMD_CTRL 0x0096
- #endif
--
- #ifndef MDIO_PMA_10GBR_FEC_CTRL
- #define MDIO_PMA_10GBR_FEC_CTRL 0x00ab
- #endif
--
- #ifndef MDIO_AN_XNP
- #define MDIO_AN_XNP 0x0016
- #endif
-@@ -111,93 +113,14 @@ MODULE_DESCRIPTION("AMD 10GbE (amd-xgbe) PHY driver");
- #ifndef MDIO_AN_INTMASK
- #define MDIO_AN_INTMASK 0x8001
- #endif
--
- #ifndef MDIO_AN_INT
- #define MDIO_AN_INT 0x8002
- #endif
-
--#ifndef MDIO_AN_KR_CTRL
--#define MDIO_AN_KR_CTRL 0x8003
--#endif
--
- #ifndef MDIO_CTRL1_SPEED1G
- #define MDIO_CTRL1_SPEED1G (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100)
- #endif
-
--#ifndef MDIO_KR_CTRL_PDETECT
--#define MDIO_KR_CTRL_PDETECT 0x01
--#endif
--
--/* SerDes integration register offsets */
--#define SIR0_KR_RT_1 0x002c
--#define SIR0_STATUS 0x0040
--#define SIR1_SPEED 0x0000
--
--/* SerDes integration register entry bit positions and sizes */
--#define SIR0_KR_RT_1_RESET_INDEX 11
--#define SIR0_KR_RT_1_RESET_WIDTH 1
--#define SIR0_STATUS_RX_READY_INDEX 0
--#define SIR0_STATUS_RX_READY_WIDTH 1
--#define SIR0_STATUS_TX_READY_INDEX 8
--#define SIR0_STATUS_TX_READY_WIDTH 1
--#define SIR1_SPEED_DATARATE_INDEX 4
--#define SIR1_SPEED_DATARATE_WIDTH 2
--#define SIR1_SPEED_PI_SPD_SEL_INDEX 12
--#define SIR1_SPEED_PI_SPD_SEL_WIDTH 4
--#define SIR1_SPEED_PLLSEL_INDEX 3
--#define SIR1_SPEED_PLLSEL_WIDTH 1
--#define SIR1_SPEED_RATECHANGE_INDEX 6
--#define SIR1_SPEED_RATECHANGE_WIDTH 1
--#define SIR1_SPEED_TXAMP_INDEX 8
--#define SIR1_SPEED_TXAMP_WIDTH 4
--#define SIR1_SPEED_WORDMODE_INDEX 0
--#define SIR1_SPEED_WORDMODE_WIDTH 3
--
--#define SPEED_10000_CDR 0x7
--#define SPEED_10000_PLL 0x1
--#define SPEED_10000_RATE 0x0
--#define SPEED_10000_TXAMP 0xa
--#define SPEED_10000_WORD 0x7
--
--#define SPEED_2500_CDR 0x2
--#define SPEED_2500_PLL 0x0
--#define SPEED_2500_RATE 0x1
--#define SPEED_2500_TXAMP 0xf
--#define SPEED_2500_WORD 0x1
--
--#define SPEED_1000_CDR 0x2
--#define SPEED_1000_PLL 0x0
--#define SPEED_1000_RATE 0x3
--#define SPEED_1000_TXAMP 0xf
--#define SPEED_1000_WORD 0x1
--
--/* SerDes RxTx register offsets */
--#define RXTX_REG20 0x0050
--#define RXTX_REG114 0x01c8
--
--/* SerDes RxTx register entry bit positions and sizes */
--#define RXTX_REG20_BLWC_ENA_INDEX 2
--#define RXTX_REG20_BLWC_ENA_WIDTH 1
--#define RXTX_REG114_PQ_REG_INDEX 9
--#define RXTX_REG114_PQ_REG_WIDTH 7
--
--#define RXTX_10000_BLWC 0
--#define RXTX_10000_PQ 0x1e
--
--#define RXTX_2500_BLWC 1
--#define RXTX_2500_PQ 0xa
--
--#define RXTX_1000_BLWC 1
--#define RXTX_1000_PQ 0xa
--
--/* Bit setting and getting macros
-- * The get macro will extract the current bit field value from within
-- * the variable
-- *
-- * The set macro will clear the current bit field value within the
-- * variable and then set the bit field of the variable to the
-- * specified value
-- */
- #define GET_BITS(_var, _index, _width) \
- (((_var) >> (_index)) & ((0x1 << (_width)) - 1))
-
-@@ -207,70 +130,12 @@ do { \
- (_var) |= (((_val) & ((0x1 << (_width)) - 1)) << (_index)); \
- } while (0)
-
--#define XSIR_GET_BITS(_var, _prefix, _field) \
-- GET_BITS((_var), \
-- _prefix##_##_field##_INDEX, \
-- _prefix##_##_field##_WIDTH)
--
--#define XSIR_SET_BITS(_var, _prefix, _field, _val) \
-- SET_BITS((_var), \
-- _prefix##_##_field##_INDEX, \
-- _prefix##_##_field##_WIDTH, (_val))
--
--/* Macros for reading or writing SerDes integration registers
-- * The ioread macros will get bit fields or full values using the
-- * register definitions formed using the input names
-- *
-- * The iowrite macros will set bit fields or full values using the
-- * register definitions formed using the input names
-- */
--#define XSIR0_IOREAD(_priv, _reg) \
-- ioread16((_priv)->sir0_regs + _reg)
--
--#define XSIR0_IOREAD_BITS(_priv, _reg, _field) \
-- GET_BITS(XSIR0_IOREAD((_priv), _reg), \
-- _reg##_##_field##_INDEX, \
-- _reg##_##_field##_WIDTH)
--
--#define XSIR0_IOWRITE(_priv, _reg, _val) \
-- iowrite16((_val), (_priv)->sir0_regs + _reg)
--
--#define XSIR0_IOWRITE_BITS(_priv, _reg, _field, _val) \
--do { \
-- u16 reg_val = XSIR0_IOREAD((_priv), _reg); \
-- SET_BITS(reg_val, \
-- _reg##_##_field##_INDEX, \
-- _reg##_##_field##_WIDTH, (_val)); \
-- XSIR0_IOWRITE((_priv), _reg, reg_val); \
--} while (0)
--
--#define XSIR1_IOREAD(_priv, _reg) \
-- ioread16((_priv)->sir1_regs + _reg)
--
--#define XSIR1_IOREAD_BITS(_priv, _reg, _field) \
-- GET_BITS(XSIR1_IOREAD((_priv), _reg), \
-- _reg##_##_field##_INDEX, \
-- _reg##_##_field##_WIDTH)
-+#define XCMU_IOREAD(_priv, _reg) \
-+ ioread16((_priv)->cmu_regs + _reg)
-
--#define XSIR1_IOWRITE(_priv, _reg, _val) \
-- iowrite16((_val), (_priv)->sir1_regs + _reg)
-+#define XCMU_IOWRITE(_priv, _reg, _val) \
-+ iowrite16((_val), (_priv)->cmu_regs + _reg)
-
--#define XSIR1_IOWRITE_BITS(_priv, _reg, _field, _val) \
--do { \
-- u16 reg_val = XSIR1_IOREAD((_priv), _reg); \
-- SET_BITS(reg_val, \
-- _reg##_##_field##_INDEX, \
-- _reg##_##_field##_WIDTH, (_val)); \
-- XSIR1_IOWRITE((_priv), _reg, reg_val); \
--} while (0)
--
--/* Macros for reading or writing SerDes RxTx registers
-- * The ioread macros will get bit fields or full values using the
-- * register definitions formed using the input names
-- *
-- * The iowrite macros will set bit fields or full values using the
-- * register definitions formed using the input names
-- */
- #define XRXTX_IOREAD(_priv, _reg) \
- ioread16((_priv)->rxtx_regs + _reg)
-
-@@ -291,6 +156,78 @@ do { \
- XRXTX_IOWRITE((_priv), _reg, reg_val); \
- } while (0)
-
-+/* SerDes CMU register offsets */
-+#define CMU_REG15 0x003c
-+#define CMU_REG16 0x0040
-+
-+/* SerDes CMU register entry bit positions and sizes */
-+#define CMU_REG16_TX_RATE_CHANGE_BASE 15
-+#define CMU_REG16_RX_RATE_CHANGE_BASE 14
-+#define CMU_REG16_RATE_CHANGE_DECR 2
-+
-+
-+/* SerDes RxTx register offsets */
-+#define RXTX_REG2 0x0008
-+#define RXTX_REG3 0x000c
-+#define RXTX_REG5 0x0014
-+#define RXTX_REG6 0x0018
-+#define RXTX_REG20 0x0050
-+#define RXTX_REG53 0x00d4
-+#define RXTX_REG114 0x01c8
-+#define RXTX_REG115 0x01cc
-+#define RXTX_REG142 0x0238
-+
-+/* SerDes RxTx register entry bit positions and sizes */
-+#define RXTX_REG2_RESETB_INDEX 15
-+#define RXTX_REG2_RESETB_WIDTH 1
-+#define RXTX_REG3_TX_DATA_RATE_INDEX 14
-+#define RXTX_REG3_TX_DATA_RATE_WIDTH 2
-+#define RXTX_REG3_TX_WORD_MODE_INDEX 11
-+#define RXTX_REG3_TX_WORD_MODE_WIDTH 3
-+#define RXTX_REG5_TXAMP_CNTL_INDEX 7
-+#define RXTX_REG5_TXAMP_CNTL_WIDTH 4
-+#define RXTX_REG6_RX_DATA_RATE_INDEX 9
-+#define RXTX_REG6_RX_DATA_RATE_WIDTH 2
-+#define RXTX_REG6_RX_WORD_MODE_INDEX 11
-+#define RXTX_REG6_RX_WORD_MODE_WIDTH 3
-+#define RXTX_REG20_BLWC_ENA_INDEX 2
-+#define RXTX_REG20_BLWC_ENA_WIDTH 1
-+#define RXTX_REG53_RX_PLLSELECT_INDEX 15
-+#define RXTX_REG53_RX_PLLSELECT_WIDTH 1
-+#define RXTX_REG53_TX_PLLSELECT_INDEX 14
-+#define RXTX_REG53_TX_PLLSELECT_WIDTH 1
-+#define RXTX_REG53_PI_SPD_SEL_CDR_INDEX 10
-+#define RXTX_REG53_PI_SPD_SEL_CDR_WIDTH 4
-+#define RXTX_REG114_PQ_REG_INDEX 9
-+#define RXTX_REG114_PQ_REG_WIDTH 7
-+#define RXTX_REG115_FORCE_LAT_CAL_START_INDEX 2
-+#define RXTX_REG115_FORCE_LAT_CAL_START_WIDTH 1
-+#define RXTX_REG115_FORCE_SUM_CAL_START_INDEX 1
-+#define RXTX_REG115_FORCE_SUM_CAL_START_WIDTH 1
-+#define RXTX_REG142_SUM_CALIB_DONE_INDEX 15
-+#define RXTX_REG142_SUM_CALIB_DONE_WIDTH 1
-+#define RXTX_REG142_SUM_CALIB_ERR_INDEX 14
-+#define RXTX_REG142_SUM_CALIB_ERR_WIDTH 1
-+#define RXTX_REG142_LAT_CALIB_DONE_INDEX 11
-+#define RXTX_REG142_LAT_CALIB_DONE_WIDTH 1
-+
-+#define RXTX_FULL_RATE 0x0
-+#define RXTX_HALF_RATE 0x1
-+#define RXTX_FIFTH_RATE 0x3
-+#define RXTX_66BIT_WORD 0x7
-+#define RXTX_10BIT_WORD 0x1
-+#define RXTX_10G_TX_AMP 0xa
-+#define RXTX_1G_TX_AMP 0xf
-+#define RXTX_10G_CDR 0x7
-+#define RXTX_1G_CDR 0x2
-+#define RXTX_10G_PLL 0x1
-+#define RXTX_1G_PLL 0x0
-+#define RXTX_10G_PQ 0x1e
-+#define RXTX_1G_PQ 0xa
-+
-+
-+DEFINE_SPINLOCK(cmu_lock);
-+
- enum amd_xgbe_phy_an {
- AMD_XGBE_AN_READY = 0,
- AMD_XGBE_AN_START,
-@@ -316,29 +253,31 @@ enum amd_xgbe_phy_mode {
- };
-
- enum amd_xgbe_phy_speedset {
-- AMD_XGBE_PHY_SPEEDSET_1000_10000,
-+ AMD_XGBE_PHY_SPEEDSET_1000_10000 = 0,
- AMD_XGBE_PHY_SPEEDSET_2500_10000,
- };
-
- struct amd_xgbe_phy_priv {
- struct platform_device *pdev;
-+ struct acpi_device *adev;
- struct device *dev;
-
- struct phy_device *phydev;
-
- /* SerDes related mmio resources */
- struct resource *rxtx_res;
-- struct resource *sir0_res;
-- struct resource *sir1_res;
-+ struct resource *cmu_res;
-
- /* SerDes related mmio registers */
- void __iomem *rxtx_regs; /* SerDes Rx/Tx CSRs */
-- void __iomem *sir0_regs; /* SerDes integration registers (1/2) */
-- void __iomem *sir1_regs; /* SerDes integration registers (2/2) */
-+ void __iomem *cmu_regs; /* SerDes CMU CSRs */
-+
-+ unsigned int serdes_channel;
-+ unsigned int speed_set;
-
- /* Maintain link status for re-starting auto-negotiation */
- unsigned int link;
-- unsigned int speed_set;
-+ enum amd_xgbe_phy_mode mode;
-
- /* Auto-negotiation state machine support */
- struct mutex an_mutex;
-@@ -348,7 +287,6 @@ struct amd_xgbe_phy_priv {
- enum amd_xgbe_phy_rx kx_state;
- struct work_struct an_work;
- struct workqueue_struct *an_workqueue;
-- unsigned int parallel_detect;
- };
-
- static int amd_xgbe_an_enable_kr_training(struct phy_device *phydev)
-@@ -401,33 +339,51 @@ static int amd_xgbe_phy_pcs_power_cycle(struct phy_device *phydev)
- static void amd_xgbe_phy_serdes_start_ratechange(struct phy_device *phydev)
- {
- struct amd_xgbe_phy_priv *priv = phydev->priv;
-+ u16 val, mask;
-+
-+ /* Assert Rx and Tx ratechange in CMU_reg16 */
-+ val = XCMU_IOREAD(priv, CMU_REG16);
-
-- /* Assert Rx and Tx ratechange */
-- XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, RATECHANGE, 1);
-+ mask = (1 << (CMU_REG16_TX_RATE_CHANGE_BASE -
-+ (priv->serdes_channel * CMU_REG16_RATE_CHANGE_DECR))) |
-+ (1 << (CMU_REG16_RX_RATE_CHANGE_BASE -
-+ (priv->serdes_channel * CMU_REG16_RATE_CHANGE_DECR)));
-+ val |= mask;
-+
-+ XCMU_IOWRITE(priv, CMU_REG16, val);
- }
-
- static void amd_xgbe_phy_serdes_complete_ratechange(struct phy_device *phydev)
- {
- struct amd_xgbe_phy_priv *priv = phydev->priv;
-+ u16 val, mask;
- unsigned int wait;
-- u16 status;
-
-- /* Release Rx and Tx ratechange */
-- XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, RATECHANGE, 0);
-+ /* Release Rx and Tx ratechange for proper channel in CMU_reg16 */
-+ val = XCMU_IOREAD(priv, CMU_REG16);
-+
-+ mask = (1 << (CMU_REG16_TX_RATE_CHANGE_BASE -
-+ (priv->serdes_channel * CMU_REG16_RATE_CHANGE_DECR))) |
-+ (1 << (CMU_REG16_RX_RATE_CHANGE_BASE -
-+ (priv->serdes_channel * CMU_REG16_RATE_CHANGE_DECR)));
-+ val &= ~mask;
-
-- /* Wait for Rx and Tx ready */
-+ XCMU_IOWRITE(priv, CMU_REG16, val);
-+
-+ /* Wait for Rx and Tx ready in CMU_reg15 */
-+ mask = (1 << priv->serdes_channel) |
-+ (1 << (priv->serdes_channel + 8));
- wait = XGBE_PHY_RATECHANGE_COUNT;
- while (wait--) {
-- usleep_range(50, 75);
-+ udelay(50);
-
-- status = XSIR0_IOREAD(priv, SIR0_STATUS);
-- if (XSIR_GET_BITS(status, SIR0_STATUS, RX_READY) &&
-- XSIR_GET_BITS(status, SIR0_STATUS, TX_READY))
-+ val = XCMU_IOREAD(priv, CMU_REG15);
-+ if ((val & mask) == mask)
- return;
- }
-
- netdev_dbg(phydev->attached_dev, "SerDes rx/tx not ready (%#hx)\n",
-- status);
-+ val);
- }
-
- static int amd_xgbe_phy_xgmii_mode(struct phy_device *phydev)
-@@ -435,8 +391,8 @@ static int amd_xgbe_phy_xgmii_mode(struct phy_device *phydev)
- struct amd_xgbe_phy_priv *priv = phydev->priv;
- int ret;
-
-- /* Enable KR training */
-- ret = amd_xgbe_an_enable_kr_training(phydev);
-+ /* Disable KR training */
-+ ret = amd_xgbe_an_disable_kr_training(phydev);
- if (ret < 0)
- return ret;
-
-@@ -462,19 +418,32 @@ static int amd_xgbe_phy_xgmii_mode(struct phy_device *phydev)
- return ret;
-
- /* Set SerDes to 10G speed */
-+ spin_lock(&cmu_lock);
-+
- amd_xgbe_phy_serdes_start_ratechange(phydev);
-
-- XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, DATARATE, SPEED_10000_RATE);
-- XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, WORDMODE, SPEED_10000_WORD);
-- XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, TXAMP, SPEED_10000_TXAMP);
-- XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PLLSEL, SPEED_10000_PLL);
-- XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PI_SPD_SEL, SPEED_10000_CDR);
-+ XRXTX_IOWRITE_BITS(priv, RXTX_REG3, TX_DATA_RATE, RXTX_FULL_RATE);
-+ XRXTX_IOWRITE_BITS(priv, RXTX_REG3, TX_WORD_MODE, RXTX_66BIT_WORD);
-
-- XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA, RXTX_10000_BLWC);
-- XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG, RXTX_10000_PQ);
-+ XRXTX_IOWRITE_BITS(priv, RXTX_REG5, TXAMP_CNTL, RXTX_10G_TX_AMP);
-+
-+ XRXTX_IOWRITE_BITS(priv, RXTX_REG6, RX_DATA_RATE, RXTX_FULL_RATE);
-+ XRXTX_IOWRITE_BITS(priv, RXTX_REG6, RX_WORD_MODE, RXTX_66BIT_WORD);
-+
-+ XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA, 0);
-+
-+ XRXTX_IOWRITE_BITS(priv, RXTX_REG53, RX_PLLSELECT, RXTX_10G_PLL);
-+ XRXTX_IOWRITE_BITS(priv, RXTX_REG53, TX_PLLSELECT, RXTX_10G_PLL);
-+ XRXTX_IOWRITE_BITS(priv, RXTX_REG53, PI_SPD_SEL_CDR, RXTX_10G_CDR);
-+
-+ XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG, RXTX_10G_PQ);
-
- amd_xgbe_phy_serdes_complete_ratechange(phydev);
-
-+ spin_unlock(&cmu_lock);
-+
-+ priv->mode = AMD_XGBE_MODE_KR;
-+
- return 0;
- }
-
-@@ -510,19 +479,32 @@ static int amd_xgbe_phy_gmii_2500_mode(struct phy_device *phydev)
- return ret;
-
- /* Set SerDes to 2.5G speed */
-+ spin_lock(&cmu_lock);
-+
- amd_xgbe_phy_serdes_start_ratechange(phydev);
-
-- XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, DATARATE, SPEED_2500_RATE);
-- XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, WORDMODE, SPEED_2500_WORD);
-- XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, TXAMP, SPEED_2500_TXAMP);
-- XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PLLSEL, SPEED_2500_PLL);
-- XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PI_SPD_SEL, SPEED_2500_CDR);
-+ XRXTX_IOWRITE_BITS(priv, RXTX_REG3, TX_DATA_RATE, RXTX_HALF_RATE);
-+ XRXTX_IOWRITE_BITS(priv, RXTX_REG3, TX_WORD_MODE, RXTX_10BIT_WORD);
-+
-+ XRXTX_IOWRITE_BITS(priv, RXTX_REG5, TXAMP_CNTL, RXTX_1G_TX_AMP);
-+
-+ XRXTX_IOWRITE_BITS(priv, RXTX_REG6, RX_DATA_RATE, RXTX_HALF_RATE);
-+ XRXTX_IOWRITE_BITS(priv, RXTX_REG6, RX_WORD_MODE, RXTX_10BIT_WORD);
-
-- XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA, RXTX_2500_BLWC);
-- XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG, RXTX_2500_PQ);
-+ XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA, 1);
-+
-+ XRXTX_IOWRITE_BITS(priv, RXTX_REG53, RX_PLLSELECT, RXTX_1G_PLL);
-+ XRXTX_IOWRITE_BITS(priv, RXTX_REG53, TX_PLLSELECT, RXTX_1G_PLL);
-+ XRXTX_IOWRITE_BITS(priv, RXTX_REG53, PI_SPD_SEL_CDR, RXTX_1G_CDR);
-+
-+ XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG, RXTX_1G_PQ);
-
- amd_xgbe_phy_serdes_complete_ratechange(phydev);
-
-+ spin_unlock(&cmu_lock);
-+
-+ priv->mode = AMD_XGBE_MODE_KX;
-+
- return 0;
- }
-
-@@ -558,47 +540,33 @@ static int amd_xgbe_phy_gmii_mode(struct phy_device *phydev)
- return ret;
-
- /* Set SerDes to 1G speed */
-+ spin_lock(&cmu_lock);
-+
- amd_xgbe_phy_serdes_start_ratechange(phydev);
-
-- XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, DATARATE, SPEED_1000_RATE);
-- XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, WORDMODE, SPEED_1000_WORD);
-- XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, TXAMP, SPEED_1000_TXAMP);
-- XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PLLSEL, SPEED_1000_PLL);
-- XSIR1_IOWRITE_BITS(priv, SIR1_SPEED, PI_SPD_SEL, SPEED_1000_CDR);
-+ XRXTX_IOWRITE_BITS(priv, RXTX_REG3, TX_DATA_RATE, RXTX_FIFTH_RATE);
-+ XRXTX_IOWRITE_BITS(priv, RXTX_REG3, TX_WORD_MODE, RXTX_10BIT_WORD);
-
-- XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA, RXTX_1000_BLWC);
-- XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG, RXTX_1000_PQ);
-+ XRXTX_IOWRITE_BITS(priv, RXTX_REG5, TXAMP_CNTL, RXTX_1G_TX_AMP);
-
-- amd_xgbe_phy_serdes_complete_ratechange(phydev);
-+ XRXTX_IOWRITE_BITS(priv, RXTX_REG6, RX_DATA_RATE, RXTX_FIFTH_RATE);
-+ XRXTX_IOWRITE_BITS(priv, RXTX_REG6, RX_WORD_MODE, RXTX_10BIT_WORD);
-
-- return 0;
--}
-+ XRXTX_IOWRITE_BITS(priv, RXTX_REG20, BLWC_ENA, 1);
-
--static int amd_xgbe_phy_cur_mode(struct phy_device *phydev,
-- enum amd_xgbe_phy_mode *mode)
--{
-- int ret;
--
-- ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
-- if (ret < 0)
-- return ret;
-+ XRXTX_IOWRITE_BITS(priv, RXTX_REG53, RX_PLLSELECT, RXTX_1G_PLL);
-+ XRXTX_IOWRITE_BITS(priv, RXTX_REG53, TX_PLLSELECT, RXTX_1G_PLL);
-+ XRXTX_IOWRITE_BITS(priv, RXTX_REG53, PI_SPD_SEL_CDR, RXTX_1G_CDR);
-
-- if ((ret & MDIO_PCS_CTRL2_TYPE) == MDIO_PCS_CTRL2_10GBR)
-- *mode = AMD_XGBE_MODE_KR;
-- else
-- *mode = AMD_XGBE_MODE_KX;
-+ XRXTX_IOWRITE_BITS(priv, RXTX_REG114, PQ_REG, RXTX_1G_PQ);
-
-- return 0;
--}
-+ amd_xgbe_phy_serdes_complete_ratechange(phydev);
-
--static bool amd_xgbe_phy_in_kr_mode(struct phy_device *phydev)
--{
-- enum amd_xgbe_phy_mode mode;
-+ spin_unlock(&cmu_lock);
-
-- if (amd_xgbe_phy_cur_mode(phydev, &mode))
-- return false;
-+ priv->mode = AMD_XGBE_MODE_KX;
-
-- return (mode == AMD_XGBE_MODE_KR);
-+ return 0;
- }
-
- static int amd_xgbe_phy_switch_mode(struct phy_device *phydev)
-@@ -607,7 +575,7 @@ static int amd_xgbe_phy_switch_mode(struct phy_device *phydev)
- int ret;
-
- /* If we are in KR switch to KX, and vice-versa */
-- if (amd_xgbe_phy_in_kr_mode(phydev)) {
-+ if (priv->mode == AMD_XGBE_MODE_KR) {
- if (priv->speed_set == AMD_XGBE_PHY_SPEEDSET_1000_10000)
- ret = amd_xgbe_phy_gmii_mode(phydev);
- else
-@@ -619,20 +587,15 @@ static int amd_xgbe_phy_switch_mode(struct phy_device *phydev)
- return ret;
- }
-
--static int amd_xgbe_phy_set_mode(struct phy_device *phydev,
-- enum amd_xgbe_phy_mode mode)
-+static enum amd_xgbe_phy_an amd_xgbe_an_switch_mode(struct phy_device *phydev)
- {
-- enum amd_xgbe_phy_mode cur_mode;
- int ret;
-
-- ret = amd_xgbe_phy_cur_mode(phydev, &cur_mode);
-- if (ret)
-- return ret;
--
-- if (mode != cur_mode)
-- ret = amd_xgbe_phy_switch_mode(phydev);
-+ ret = amd_xgbe_phy_switch_mode(phydev);
-+ if (ret < 0)
-+ return AMD_XGBE_AN_ERROR;
-
-- return ret;
-+ return AMD_XGBE_AN_START;
- }
-
- static enum amd_xgbe_phy_an amd_xgbe_an_tx_training(struct phy_device *phydev,
-@@ -643,8 +606,8 @@ static enum amd_xgbe_phy_an amd_xgbe_an_tx_training(struct phy_device *phydev,
-
- *state = AMD_XGBE_RX_COMPLETE;
-
-- /* If we're not in KR mode then we're done */
-- if (!amd_xgbe_phy_in_kr_mode(phydev))
-+ /* If we're in KX mode then we're done */
-+ if (priv->mode == AMD_XGBE_MODE_KX)
- return AMD_XGBE_AN_EVENT;
-
- /* Enable/Disable FEC */
-@@ -672,13 +635,9 @@ static enum amd_xgbe_phy_an amd_xgbe_an_tx_training(struct phy_device *phydev,
- if (ret < 0)
- return AMD_XGBE_AN_ERROR;
-
-- XSIR0_IOWRITE_BITS(priv, SIR0_KR_RT_1, RESET, 1);
--
- ret |= 0x01;
- phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_PMD_CTRL, ret);
-
-- XSIR0_IOWRITE_BITS(priv, SIR0_KR_RT_1, RESET, 0);
--
- return AMD_XGBE_AN_EVENT;
- }
-
-@@ -702,6 +661,7 @@ static enum amd_xgbe_phy_an amd_xgbe_an_tx_xnp(struct phy_device *phydev,
- static enum amd_xgbe_phy_an amd_xgbe_an_rx_bpa(struct phy_device *phydev,
- enum amd_xgbe_phy_rx *state)
- {
-+ struct amd_xgbe_phy_priv *priv = phydev->priv;
- unsigned int link_support;
- int ret, ad_reg, lp_reg;
-
-@@ -711,9 +671,9 @@ static enum amd_xgbe_phy_an amd_xgbe_an_rx_bpa(struct phy_device *phydev,
- return AMD_XGBE_AN_ERROR;
-
- /* Check for a supported mode, otherwise restart in a different one */
-- link_support = amd_xgbe_phy_in_kr_mode(phydev) ? 0x80 : 0x20;
-+ link_support = (priv->mode == AMD_XGBE_MODE_KR) ? 0x80 : 0x20;
- if (!(ret & link_support))
-- return AMD_XGBE_AN_INCOMPAT_LINK;
-+ return amd_xgbe_an_switch_mode(phydev);
-
- /* Check Extended Next Page support */
- ad_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
-@@ -754,7 +714,7 @@ static enum amd_xgbe_phy_an amd_xgbe_an_start(struct phy_device *phydev)
- int ret;
-
- /* Be sure we aren't looping trying to negotiate */
-- if (amd_xgbe_phy_in_kr_mode(phydev)) {
-+ if (priv->mode == AMD_XGBE_MODE_KR) {
- if (priv->kr_state != AMD_XGBE_RX_READY)
- return AMD_XGBE_AN_NO_LINK;
- priv->kr_state = AMD_XGBE_RX_BPA;
-@@ -817,13 +777,6 @@ static enum amd_xgbe_phy_an amd_xgbe_an_start(struct phy_device *phydev)
- /* Enable and start auto-negotiation */
- phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0);
-
-- ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_KR_CTRL);
-- if (ret < 0)
-- return AMD_XGBE_AN_ERROR;
--
-- ret |= MDIO_KR_CTRL_PDETECT;
-- phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_KR_CTRL, ret);
--
- ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
- if (ret < 0)
- return AMD_XGBE_AN_ERROR;
-@@ -864,8 +817,8 @@ static enum amd_xgbe_phy_an amd_xgbe_an_page_received(struct phy_device *phydev)
- enum amd_xgbe_phy_rx *state;
- int ret;
-
-- state = amd_xgbe_phy_in_kr_mode(phydev) ? &priv->kr_state
-- : &priv->kx_state;
-+ state = (priv->mode == AMD_XGBE_MODE_KR) ? &priv->kr_state
-+ : &priv->kx_state;
-
- switch (*state) {
- case AMD_XGBE_RX_BPA:
-@@ -885,13 +838,7 @@ static enum amd_xgbe_phy_an amd_xgbe_an_page_received(struct phy_device *phydev)
-
- static enum amd_xgbe_phy_an amd_xgbe_an_incompat_link(struct phy_device *phydev)
- {
-- int ret;
--
-- ret = amd_xgbe_phy_switch_mode(phydev);
-- if (ret)
-- return AMD_XGBE_AN_ERROR;
--
-- return AMD_XGBE_AN_START;
-+ return amd_xgbe_an_switch_mode(phydev);
- }
-
- static void amd_xgbe_an_state_machine(struct work_struct *work)
-@@ -904,10 +851,6 @@ static void amd_xgbe_an_state_machine(struct work_struct *work)
- int sleep;
- unsigned int an_supported = 0;
-
-- /* Start in KX mode */
-- if (amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KX))
-- priv->an_state = AMD_XGBE_AN_ERROR;
--
- while (1) {
- mutex_lock(&priv->an_mutex);
-
-@@ -915,9 +858,8 @@ static void amd_xgbe_an_state_machine(struct work_struct *work)
-
- switch (priv->an_state) {
- case AMD_XGBE_AN_START:
-- an_supported = 0;
-- priv->parallel_detect = 0;
- priv->an_state = amd_xgbe_an_start(phydev);
-+ an_supported = 0;
- break;
-
- case AMD_XGBE_AN_EVENT:
-@@ -934,7 +876,6 @@ static void amd_xgbe_an_state_machine(struct work_struct *work)
- break;
-
- case AMD_XGBE_AN_COMPLETE:
-- priv->parallel_detect = an_supported ? 0 : 1;
- netdev_info(phydev->attached_dev, "%s successful\n",
- an_supported ? "Auto negotiation"
- : "Parallel detection");
-@@ -1070,6 +1011,7 @@ static int amd_xgbe_phy_config_aneg(struct phy_device *phydev)
- {
- struct amd_xgbe_phy_priv *priv = phydev->priv;
- u32 mmd_mask = phydev->c45_ids.devices_in_package;
-+ int ret;
-
- if (phydev->autoneg != AUTONEG_ENABLE)
- return amd_xgbe_phy_setup_forced(phydev);
-@@ -1078,6 +1020,11 @@ static int amd_xgbe_phy_config_aneg(struct phy_device *phydev)
- if (!(mmd_mask & MDIO_DEVS_AN))
- return -EINVAL;
-
-+ /* Get the current speed mode */
-+ ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
-+ if (ret < 0)
-+ return ret;
-+
- /* Start/Restart the auto-negotiation state machine */
- mutex_lock(&priv->an_mutex);
- priv->an_result = AMD_XGBE_AN_READY;
-@@ -1167,14 +1114,18 @@ static int amd_xgbe_phy_read_status(struct phy_device *phydev)
- {
- struct amd_xgbe_phy_priv *priv = phydev->priv;
- u32 mmd_mask = phydev->c45_ids.devices_in_package;
-- int ret, ad_ret, lp_ret;
-+ int ret, mode, ad_ret, lp_ret;
-
- ret = amd_xgbe_phy_update_link(phydev);
- if (ret)
- return ret;
-
-- if ((phydev->autoneg == AUTONEG_ENABLE) &&
-- !priv->parallel_detect) {
-+ mode = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
-+ if (mode < 0)
-+ return mode;
-+ mode &= MDIO_PCS_CTRL2_TYPE;
-+
-+ if (phydev->autoneg == AUTONEG_ENABLE) {
- if (!(mmd_mask & MDIO_DEVS_AN))
- return -EINVAL;
-
-@@ -1205,39 +1156,40 @@ static int amd_xgbe_phy_read_status(struct phy_device *phydev)
- ad_ret &= lp_ret;
- if (ad_ret & 0x80) {
- phydev->speed = SPEED_10000;
-- ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KR);
-- if (ret)
-- return ret;
-+ if (mode != MDIO_PCS_CTRL2_10GBR) {
-+ ret = amd_xgbe_phy_xgmii_mode(phydev);
-+ if (ret < 0)
-+ return ret;
-+ }
- } else {
-- switch (priv->speed_set) {
-- case AMD_XGBE_PHY_SPEEDSET_1000_10000:
-- phydev->speed = SPEED_1000;
-- break;
-+ int (*mode_fcn)(struct phy_device *);
-
-- case AMD_XGBE_PHY_SPEEDSET_2500_10000:
-+ if (priv->speed_set ==
-+ AMD_XGBE_PHY_SPEEDSET_1000_10000) {
-+ phydev->speed = SPEED_1000;
-+ mode_fcn = amd_xgbe_phy_gmii_mode;
-+ } else {
- phydev->speed = SPEED_2500;
-- break;
-+ mode_fcn = amd_xgbe_phy_gmii_2500_mode;
- }
-
-- ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KX);
-- if (ret)
-- return ret;
-+ if (mode == MDIO_PCS_CTRL2_10GBR) {
-+ ret = mode_fcn(phydev);
-+ if (ret < 0)
-+ return ret;
-+ }
- }
-
- phydev->duplex = DUPLEX_FULL;
- } else {
-- if (amd_xgbe_phy_in_kr_mode(phydev)) {
-+ if (mode == MDIO_PCS_CTRL2_10GBR) {
- phydev->speed = SPEED_10000;
- } else {
-- switch (priv->speed_set) {
-- case AMD_XGBE_PHY_SPEEDSET_1000_10000:
-+ if (priv->speed_set ==
-+ AMD_XGBE_PHY_SPEEDSET_1000_10000)
- phydev->speed = SPEED_1000;
-- break;
--
-- case AMD_XGBE_PHY_SPEEDSET_2500_10000:
-+ else
- phydev->speed = SPEED_2500;
-- break;
-- }
- }
- phydev->duplex = DUPLEX_FULL;
- phydev->pause = 0;
-@@ -1289,29 +1241,188 @@ unlock:
- return ret;
- }
-
-+static int amd_xgbe_phy_map_resources(struct amd_xgbe_phy_priv *priv,
-+ struct platform_device *phy_pdev,
-+ unsigned int phy_resnum)
-+{
-+ struct device *dev = priv->dev;
-+ int ret;
-+
-+ /* Get the device mmio areas */
-+ priv->rxtx_res = platform_get_resource(phy_pdev, IORESOURCE_MEM,
-+ phy_resnum++);
-+ priv->rxtx_regs = devm_ioremap_resource(dev, priv->rxtx_res);
-+ if (IS_ERR(priv->rxtx_regs)) {
-+ dev_err(dev, "rxtx ioremap failed\n");
-+ return PTR_ERR(priv->rxtx_regs);
-+ }
-+
-+ /* All xgbe phy devices share the CMU registers so retrieve
-+ * the resource and do the ioremap directly rather than
-+ * the devm_ioremap_resource call
-+ */
-+ priv->cmu_res = platform_get_resource(phy_pdev, IORESOURCE_MEM,
-+ phy_resnum++);
-+ if (!priv->cmu_res) {
-+ dev_err(dev, "cmu invalid resource\n");
-+ ret = -EINVAL;
-+ goto err_rxtx;
-+ }
-+ priv->cmu_regs = devm_ioremap_nocache(dev, priv->cmu_res->start,
-+ resource_size(priv->cmu_res));
-+ if (!priv->cmu_regs) {
-+ dev_err(dev, "cmu ioremap failed\n");
-+ ret = -ENOMEM;
-+ goto err_rxtx;
-+ }
-+
-+ return 0;
-+
-+err_rxtx:
-+ devm_iounmap(dev, priv->rxtx_regs);
-+ devm_release_mem_region(dev, priv->rxtx_res->start,
-+ resource_size(priv->rxtx_res));
-+
-+ return ret;
-+}
-+
-+static void amd_xgbe_phy_unmap_resources(struct amd_xgbe_phy_priv *priv)
-+{
-+ struct device *dev = priv->dev;
-+
-+ devm_iounmap(dev, priv->cmu_regs);
-+
-+ devm_iounmap(dev, priv->rxtx_regs);
-+ devm_release_mem_region(dev, priv->rxtx_res->start,
-+ resource_size(priv->rxtx_res));
-+}
-+
-+#ifdef CONFIG_ACPI
-+static int amd_xgbe_phy_acpi_support(struct amd_xgbe_phy_priv *priv)
-+{
-+ struct platform_device *phy_pdev = priv->pdev;
-+ struct acpi_device *adev = priv->adev;
-+ struct device *dev = priv->dev;
-+ const union acpi_object *property;
-+ int ret;
-+
-+ /* Map the memory resources */
-+ ret = amd_xgbe_phy_map_resources(priv, phy_pdev, 2);
-+ if (ret)
-+ return ret;
-+
-+ /* Get the device serdes channel property */
-+ ret = acpi_dev_get_property(adev, XGBE_PHY_CHANNEL_PROPERTY,
-+ ACPI_TYPE_INTEGER, &property);
-+ if (ret) {
-+ dev_err(dev, "unable to obtain %s acpi property\n",
-+ XGBE_PHY_CHANNEL_PROPERTY);
-+ goto err_resources;
-+ }
-+ priv->serdes_channel = property->integer.value;
-+
-+ /* Get the device speed set property */
-+ ret = acpi_dev_get_property(adev, XGBE_PHY_SPEEDSET_PROPERTY,
-+ ACPI_TYPE_INTEGER, &property);
-+ if (ret) {
-+ dev_err(dev, "unable to obtain %s acpi property\n",
-+ XGBE_PHY_SPEEDSET_PROPERTY);
-+ goto err_resources;
-+ }
-+ priv->speed_set = property->integer.value;
-+
-+ return 0;
-+
-+err_resources:
-+ amd_xgbe_phy_unmap_resources(priv);
-+
-+ return ret;
-+}
-+#else /* CONFIG_ACPI */
-+static int amd_xgbe_phy_acpi_support(struct amd_xgbe_phy_priv *priv)
-+{
-+ return -EINVAL;
-+}
-+#endif /* CONFIG_ACPI */
-+
-+#ifdef CONFIG_OF
-+static int amd_xgbe_phy_of_support(struct amd_xgbe_phy_priv *priv)
-+{
-+ struct platform_device *phy_pdev;
-+ struct device_node *bus_node;
-+ struct device_node *phy_node;
-+ struct device *dev = priv->dev;
-+ const __be32 *property;
-+ int ret;
-+
-+ bus_node = priv->dev->of_node;
-+ phy_node = of_parse_phandle(bus_node, "phy-handle", 0);
-+ if (!phy_node) {
-+ dev_err(dev, "unable to parse phy-handle\n");
-+ return -EINVAL;
-+ }
-+
-+ phy_pdev = of_find_device_by_node(phy_node);
-+ if (!phy_pdev) {
-+ dev_err(dev, "unable to obtain phy device\n");
-+ ret = -EINVAL;
-+ goto err_put;
-+ }
-+
-+ /* Map the memory resources */
-+ ret = amd_xgbe_phy_map_resources(priv, phy_pdev, 0);
-+ if (ret)
-+ goto err_put;
-+
-+ /* Get the device serdes channel property */
-+ property = of_get_property(phy_node, XGBE_PHY_CHANNEL_PROPERTY, NULL);
-+ if (!property) {
-+ dev_err(dev, "unable to obtain %s property\n",
-+ XGBE_PHY_CHANNEL_PROPERTY);
-+ ret = -EINVAL;
-+ goto err_resources;
-+ }
-+ priv->serdes_channel = be32_to_cpu(*property);
-+
-+ /* Get the device speed set property */
-+ property = of_get_property(phy_node, XGBE_PHY_SPEEDSET_PROPERTY, NULL);
-+ if (property)
-+ priv->speed_set = be32_to_cpu(*property);
-+
-+ of_node_put(phy_node);
-+
-+ return 0;
-+
-+err_resources:
-+ amd_xgbe_phy_unmap_resources(priv);
-+
-+err_put:
-+ of_node_put(phy_node);
-+
-+ return ret;
-+}
-+#else /* CONFIG_OF */
-+static int amd_xgbe_phy_of_support(struct amd_xgbe_phy_priv *priv)
-+{
-+ return -EINVAL;
-+}
-+#endif /* CONFIG_OF */
-+
- static int amd_xgbe_phy_probe(struct phy_device *phydev)
- {
- struct amd_xgbe_phy_priv *priv;
-- struct platform_device *pdev;
- struct device *dev;
- char *wq_name;
-- const __be32 *property;
-- unsigned int speed_set;
- int ret;
-
-- if (!phydev->dev.of_node)
-+ if (!phydev->bus || !phydev->bus->parent)
- return -EINVAL;
-
-- pdev = of_find_device_by_node(phydev->dev.of_node);
-- if (!pdev)
-- return -EINVAL;
-- dev = &pdev->dev;
-+ dev = phydev->bus->parent;
-
- wq_name = kasprintf(GFP_KERNEL, "%s-amd-xgbe-phy", phydev->bus->name);
-- if (!wq_name) {
-- ret = -ENOMEM;
-- goto err_pdev;
-- }
-+ if (!wq_name)
-+ return -ENOMEM;
-
- priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
- if (!priv) {
-@@ -1319,86 +1430,54 @@ static int amd_xgbe_phy_probe(struct phy_device *phydev)
- goto err_name;
- }
-
-- priv->pdev = pdev;
-+ priv->pdev = to_platform_device(dev);
-+ priv->adev = ACPI_COMPANION(dev);
- priv->dev = dev;
- priv->phydev = phydev;
-
-- /* Get the device mmio areas */
-- priv->rxtx_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-- priv->rxtx_regs = devm_ioremap_resource(dev, priv->rxtx_res);
-- if (IS_ERR(priv->rxtx_regs)) {
-- dev_err(dev, "rxtx ioremap failed\n");
-- ret = PTR_ERR(priv->rxtx_regs);
-+ if (priv->adev && !acpi_disabled)
-+ ret = amd_xgbe_phy_acpi_support(priv);
-+ else
-+ ret = amd_xgbe_phy_of_support(priv);
-+ if (ret)
- goto err_priv;
-- }
--
-- priv->sir0_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-- priv->sir0_regs = devm_ioremap_resource(dev, priv->sir0_res);
-- if (IS_ERR(priv->sir0_regs)) {
-- dev_err(dev, "sir0 ioremap failed\n");
-- ret = PTR_ERR(priv->sir0_regs);
-- goto err_rxtx;
-- }
--
-- priv->sir1_res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
-- priv->sir1_regs = devm_ioremap_resource(dev, priv->sir1_res);
-- if (IS_ERR(priv->sir1_regs)) {
-- dev_err(dev, "sir1 ioremap failed\n");
-- ret = PTR_ERR(priv->sir1_regs);
-- goto err_sir0;
-- }
-
-- /* Get the device speed set property */
-- speed_set = 0;
-- property = of_get_property(dev->of_node, XGBE_PHY_SPEEDSET_PROPERTY,
-- NULL);
-- if (property)
-- speed_set = be32_to_cpu(*property);
--
-- switch (speed_set) {
-- case 0:
-- priv->speed_set = AMD_XGBE_PHY_SPEEDSET_1000_10000;
-- break;
-- case 1:
-- priv->speed_set = AMD_XGBE_PHY_SPEEDSET_2500_10000;
-+ switch (priv->speed_set) {
-+ case AMD_XGBE_PHY_SPEEDSET_1000_10000:
-+ case AMD_XGBE_PHY_SPEEDSET_2500_10000:
- break;
- default:
- dev_err(dev, "invalid amd,speed-set property\n");
- ret = -EINVAL;
-- goto err_sir1;
-+ goto err_resources;
- }
-
- priv->link = 1;
-
-+ ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
-+ if (ret < 0)
-+ goto err_resources;
-+ if ((ret & MDIO_PCS_CTRL2_TYPE) == MDIO_PCS_CTRL2_10GBR)
-+ priv->mode = AMD_XGBE_MODE_KR;
-+ else
-+ priv->mode = AMD_XGBE_MODE_KX;
-+
- mutex_init(&priv->an_mutex);
- INIT_WORK(&priv->an_work, amd_xgbe_an_state_machine);
- priv->an_workqueue = create_singlethread_workqueue(wq_name);
- if (!priv->an_workqueue) {
- ret = -ENOMEM;
-- goto err_sir1;
-+ goto err_resources;
- }
-
- phydev->priv = priv;
-
- kfree(wq_name);
-- of_dev_put(pdev);
-
- return 0;
-
--err_sir1:
-- devm_iounmap(dev, priv->sir1_regs);
-- devm_release_mem_region(dev, priv->sir1_res->start,
-- resource_size(priv->sir1_res));
--
--err_sir0:
-- devm_iounmap(dev, priv->sir0_regs);
-- devm_release_mem_region(dev, priv->sir0_res->start,
-- resource_size(priv->sir0_res));
--
--err_rxtx:
-- devm_iounmap(dev, priv->rxtx_regs);
-- devm_release_mem_region(dev, priv->rxtx_res->start,
-- resource_size(priv->rxtx_res));
-+err_resources:
-+ amd_xgbe_phy_unmap_resources(priv);
-
- err_priv:
- devm_kfree(dev, priv);
-@@ -1406,9 +1485,6 @@ err_priv:
- err_name:
- kfree(wq_name);
-
--err_pdev:
-- of_dev_put(pdev);
--
- return ret;
- }
-
-@@ -1425,18 +1501,7 @@ static void amd_xgbe_phy_remove(struct phy_device *phydev)
- flush_workqueue(priv->an_workqueue);
- destroy_workqueue(priv->an_workqueue);
-
-- /* Release resources */
-- devm_iounmap(dev, priv->sir1_regs);
-- devm_release_mem_region(dev, priv->sir1_res->start,
-- resource_size(priv->sir1_res));
--
-- devm_iounmap(dev, priv->sir0_regs);
-- devm_release_mem_region(dev, priv->sir0_res->start,
-- resource_size(priv->sir0_res));
--
-- devm_iounmap(dev, priv->rxtx_regs);
-- devm_release_mem_region(dev, priv->rxtx_res->start,
-- resource_size(priv->rxtx_res));
-+ amd_xgbe_phy_unmap_resources(priv);
-
- devm_kfree(dev, priv);
- }
-diff --git a/drivers/pci/host/pci-xgene.c b/drivers/pci/host/pci-xgene.c
-index b1d0596..06b8f97 100644
---- a/drivers/pci/host/pci-xgene.c
-+++ b/drivers/pci/host/pci-xgene.c
-@@ -29,6 +29,7 @@
- #include <linux/pci.h>
- #include <linux/platform_device.h>
- #include <linux/slab.h>
-+#include <linux/acpi.h>
-
- #define PCIECORE_CTLANDSTATUS 0x50
- #define PIM1_1L 0x80
-@@ -235,6 +236,13 @@ static int xgene_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
- break;
- case 2:
- xgene_pcie_cfg_in16(addr, offset, val);
-+ /* FIXME.
-+ * Something wrong with Configuration Request Retry Status
-+ * on this hw. Pretend it isn't supported until the problem
-+ * gets sorted out properly.
-+ */
-+ if (pci_is_root_bus(bus) && offset == (0x40 + PCI_EXP_RTCAP))
-+ *val &= ~PCI_EXP_RTCAP_CRSVIS;
- break;
- default:
- xgene_pcie_cfg_in32(addr, offset, val);
-@@ -600,6 +608,165 @@ static int xgene_pcie_setup(struct xgene_pcie_port *port,
- return 0;
- }
-
-+#ifdef CONFIG_ACPI
-+struct xgene_mcfg_info {
-+ void __iomem *csr_base;
-+};
-+
-+/*
-+ * When the address bit [17:16] is 2'b01, the Configuration access will be
-+ * treated as Type 1 and it will be forwarded to external PCIe device.
-+ */
-+static void __iomem *__get_cfg_base(struct pci_mmcfg_region *cfg,
-+ unsigned int bus)
-+{
-+ if (bus > cfg->start_bus)
-+ return cfg->virt + AXI_EP_CFG_ACCESS;
-+
-+ return cfg->virt;
-+}
-+
-+/*
-+ * For Configuration request, RTDID register is used as Bus Number,
-+ * Device Number and Function number of the header fields.
-+ */
-+static void __set_rtdid_reg(struct pci_mmcfg_region *cfg,
-+ unsigned int bus, unsigned int devfn)
-+{
-+ struct xgene_mcfg_info *info = cfg->data;
-+ unsigned int b, d, f;
-+ u32 rtdid_val = 0;
-+
-+ b = bus;
-+ d = PCI_SLOT(devfn);
-+ f = PCI_FUNC(devfn);
-+
-+ if (bus != cfg->start_bus)
-+ rtdid_val = (b << 8) | (d << 3) | f;
-+
-+ writel(rtdid_val, info->csr_base + RTDID);
-+ /* read the register back to ensure flush */
-+ readl(info->csr_base + RTDID);
-+}
-+
-+static int xgene_raw_pci_read(struct pci_mmcfg_region *cfg, unsigned int bus,
-+ unsigned int devfn, int offset, int len, u32 *val)
-+{
-+ void __iomem *addr;
-+
-+ if (bus == cfg->start_bus) {
-+ if (devfn != 0) {
-+ *val = 0xffffffff;
-+ return PCIBIOS_DEVICE_NOT_FOUND;
-+ }
-+
-+ /* see xgene_pcie_hide_rc_bars() above */
-+ if (offset == PCI_BASE_ADDRESS_0 ||
-+ offset == PCI_BASE_ADDRESS_1) {
-+ *val = 0;
-+ return PCIBIOS_SUCCESSFUL;
-+ }
-+ }
-+
-+ __set_rtdid_reg(cfg, bus, devfn);
-+ addr = __get_cfg_base(cfg, bus);
-+ switch (len) {
-+ case 1:
-+ xgene_pcie_cfg_in8(addr, offset, val);
-+ break;
-+ case 2:
-+ xgene_pcie_cfg_in16(addr, offset, val);
-+ /* FIXME.
-+ * Something wrong with Configuration Request Retry Status
-+ * on this hw. Pretend it isn't supported until the problem
-+ * gets sorted out properly.
-+ */
-+ if (bus == cfg->start_bus && offset == (0x40 + PCI_EXP_RTCAP))
-+ *val &= ~PCI_EXP_RTCAP_CRSVIS;
-+ break;
-+ default:
-+ xgene_pcie_cfg_in32(addr, offset, val);
-+ break;
-+ }
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static int xgene_raw_pci_write(struct pci_mmcfg_region *cfg, unsigned int bus,
-+ unsigned int devfn, int offset, int len, u32 val)
-+{
-+ void __iomem *addr;
-+
-+ if (bus == cfg->start_bus && devfn != 0)
-+ return PCIBIOS_DEVICE_NOT_FOUND;
-+
-+ __set_rtdid_reg(cfg, bus, devfn);
-+ addr = __get_cfg_base(cfg, bus);
-+ switch (len) {
-+ case 1:
-+ xgene_pcie_cfg_out8(addr, offset, (u8)val);
-+ break;
-+ case 2:
-+ xgene_pcie_cfg_out16(addr, offset, (u16)val);
-+ break;
-+ default:
-+ xgene_pcie_cfg_out32(addr, offset, val);
-+ break;
-+ }
-+ return PCIBIOS_SUCCESSFUL;
-+}
-+
-+static acpi_status find_csr_base(struct acpi_resource *acpi_res, void *data)
-+{
-+ struct pci_mmcfg_region *cfg = data;
-+ struct xgene_mcfg_info *info = cfg->data;
-+ struct acpi_resource_fixed_memory32 *fixed32;
-+
-+ if (acpi_res->type == ACPI_RESOURCE_TYPE_FIXED_MEMORY32) {
-+ fixed32 = &acpi_res->data.fixed_memory32;
-+ info->csr_base = ioremap(fixed32->address,
-+ fixed32->address_length);
-+ return AE_CTRL_TERMINATE;
-+ }
-+ return AE_OK;
-+}
-+
-+static int xgene_mcfg_fixup(struct acpi_pci_root *root,
-+ struct pci_mmcfg_region *cfg)
-+{
-+ struct acpi_device *device = root->device;
-+ struct xgene_mcfg_info *info;
-+
-+ info = kzalloc(sizeof(*info), GFP_KERNEL);
-+ if (info == NULL)
-+ return -ENOMEM;
-+
-+ cfg->data = info;
-+
-+ acpi_walk_resources(device->handle, METHOD_NAME__CRS,
-+ find_csr_base, cfg);
-+
-+ if (!info->csr_base) {
-+ kfree(info);
-+ cfg->data = NULL;
-+ return -ENODEV;
-+ }
-+
-+ cfg->read = xgene_raw_pci_read;
-+ cfg->write = xgene_raw_pci_write;
-+
-+ /* actual last bus reachable through this mmconfig */
-+ cfg->end_bus = root->secondary.end;
-+
-+ /* firmware should have done this */
-+ xgene_raw_pci_write(cfg, cfg->start_bus, 0, PCI_PRIMARY_BUS, 4,
-+ cfg->start_bus | ((cfg->start_bus + 1) << 8) |
-+ (cfg->end_bus << 16));
-+
-+ return 0;
-+}
-+DECLARE_ACPI_MCFG_FIXUP("APM ", "XGENE ", xgene_mcfg_fixup);
-+#endif /* CONFIG_ACPI */
-+
- static int xgene_pcie_probe_bridge(struct platform_device *pdev)
- {
- struct device_node *dn = pdev->dev.of_node;
-diff --git a/drivers/pnp/resource.c b/drivers/pnp/resource.c
-index 782e822..d952462 100644
---- a/drivers/pnp/resource.c
-+++ b/drivers/pnp/resource.c
-@@ -313,6 +313,7 @@ static int pci_dev_uses_irq(struct pnp_dev *pnp, struct pci_dev *pci,
- progif = class & 0xff;
- class >>= 8;
-
-+#ifdef HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ
- if (class == PCI_CLASS_STORAGE_IDE) {
- /*
- * Unless both channels are native-PCI mode only,
-@@ -326,6 +327,7 @@ static int pci_dev_uses_irq(struct pnp_dev *pnp, struct pci_dev *pci,
- return 1;
- }
- }
-+#endif /* HAVE_ARCH_PCI_GET_LEGACY_IDE_IRQ */
-
- return 0;
- }
-diff --git a/drivers/tty/Kconfig b/drivers/tty/Kconfig
-index b24aa01..50fe279 100644
---- a/drivers/tty/Kconfig
-+++ b/drivers/tty/Kconfig
-@@ -419,4 +419,10 @@ config DA_CONSOLE
- help
- This enables a console on a Dash channel.
-
-+config SBSAUART_TTY
-+ tristate "SBSA UART TTY Driver"
-+ help
-+ Console and system TTY driver for the SBSA UART which is defined
-+ in the Server Base System Architecure document for ARM64 servers.
-+
- endif # TTY
-diff --git a/drivers/tty/Makefile b/drivers/tty/Makefile
-index 58ad1c0..c3211c0 100644
---- a/drivers/tty/Makefile
-+++ b/drivers/tty/Makefile
-@@ -29,5 +29,6 @@ obj-$(CONFIG_SYNCLINK) += synclink.o
- obj-$(CONFIG_PPC_EPAPR_HV_BYTECHAN) += ehv_bytechan.o
- obj-$(CONFIG_GOLDFISH_TTY) += goldfish.o
- obj-$(CONFIG_DA_TTY) += metag_da.o
-+obj-$(CONFIG_SBSAUART_TTY) += sbsauart.o
-
- obj-y += ipwireless/
-diff --git a/drivers/tty/sbsauart.c b/drivers/tty/sbsauart.c
-new file mode 100644
-index 0000000..0f44624
---- /dev/null
-+++ b/drivers/tty/sbsauart.c
-@@ -0,0 +1,358 @@
-+/*
-+ * SBSA (Server Base System Architecture) Compatible UART driver
-+ *
-+ * Copyright (C) 2014 Linaro Ltd
-+ *
-+ * Author: Graeme Gregory <graeme.gregory at linaro.org>
-+ *
-+ * This software is licensed under the terms of the GNU General Public
-+ * License version 2, as published by the Free Software Foundation, and
-+ * may be copied, distributed, and modified under those terms.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ */
-+
-+#include <linux/acpi.h>
-+#include <linux/amba/serial.h>
-+#include <linux/console.h>
-+#include <linux/delay.h>
-+#include <linux/interrupt.h>
-+#include <linux/io.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/slab.h>
-+#include <linux/serial_core.h>
-+#include <linux/tty.h>
-+#include <linux/tty_flip.h>
-+
-+struct sbsa_tty {
-+ struct tty_port port;
-+ spinlock_t lock;
-+ void __iomem *base;
-+ u32 irq;
-+ int opencount;
-+ struct console console;
-+};
-+
-+static struct tty_driver *sbsa_tty_driver;
-+static struct sbsa_tty *sbsa_tty;
-+
-+#define SBSAUART_CHAR_MASK 0xFF
-+
-+static void sbsa_raw_putc(struct uart_port *port, int c)
-+{
-+ while (readw(port->membase + UART01x_FR) & UART01x_FR_TXFF)
-+ ;
-+ writew(c & 0xFF, port->membase + UART01x_DR);
-+}
-+
-+static void sbsa_uart_early_write(struct console *con, const char *buf,
-+ unsigned count)
-+{
-+ struct earlycon_device *dev = con->data;
-+
-+ uart_console_write(&dev->port, buf, count, sbsa_raw_putc);
-+}
-+
-+static int __init sbsa_uart_early_console_setup(struct earlycon_device *device,
-+ const char *opt)
-+{
-+ if (!device->port.membase)
-+ return -ENODEV;
-+
-+ device->con->write = sbsa_uart_early_write;
-+ return 0;
-+}
-+EARLYCON_DECLARE(sbsauart, sbsa_uart_early_console_setup);
-+
-+static void sbsa_tty_do_write(const char *buf, unsigned count)
-+{
-+ unsigned long irq_flags;
-+ struct sbsa_tty *qtty = sbsa_tty;
-+ void __iomem *base = qtty->base;
-+ unsigned n;
-+
-+ spin_lock_irqsave(&qtty->lock, irq_flags);
-+ for (n = 0; n < count; n++) {
-+ while (readw(base + UART01x_FR) & UART01x_FR_TXFF)
-+ ;
-+ writew(buf[n], base + UART01x_DR);
-+ }
-+ spin_unlock_irqrestore(&qtty->lock, irq_flags);
-+}
-+
-+static void sbsauart_fifo_to_tty(struct sbsa_tty *qtty)
-+{
-+ void __iomem *base = qtty->base;
-+ unsigned int flag, max_count = 32;
-+ u16 status, ch;
-+
-+ while (max_count--) {
-+ status = readw(base + UART01x_FR);
-+ if (status & UART01x_FR_RXFE)
-+ break;
-+
-+ /* Take chars from the FIFO and update status */
-+ ch = readw(base + UART01x_DR);
-+ flag = TTY_NORMAL;
-+
-+ if (ch & UART011_DR_BE)
-+ flag = TTY_BREAK;
-+ else if (ch & UART011_DR_PE)
-+ flag = TTY_PARITY;
-+ else if (ch & UART011_DR_FE)
-+ flag = TTY_FRAME;
-+ else if (ch & UART011_DR_OE)
-+ flag = TTY_OVERRUN;
-+
-+ ch &= SBSAUART_CHAR_MASK;
-+
-+ tty_insert_flip_char(&qtty->port, ch, flag);
-+ }
-+
-+ tty_schedule_flip(&qtty->port);
-+
-+ /* Clear the RX IRQ */
-+ writew(UART011_RXIC | UART011_RXIC, base + UART011_ICR);
-+}
-+
-+static irqreturn_t sbsa_tty_interrupt(int irq, void *dev_id)
-+{
-+ struct sbsa_tty *qtty = sbsa_tty;
-+ unsigned long irq_flags;
-+
-+ spin_lock_irqsave(&qtty->lock, irq_flags);
-+ sbsauart_fifo_to_tty(qtty);
-+ spin_unlock_irqrestore(&qtty->lock, irq_flags);
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static int sbsa_tty_open(struct tty_struct *tty, struct file *filp)
-+{
-+ struct sbsa_tty *qtty = sbsa_tty;
-+
-+ return tty_port_open(&qtty->port, tty, filp);
-+}
-+
-+static void sbsa_tty_close(struct tty_struct *tty, struct file *filp)
-+{
-+ tty_port_close(tty->port, tty, filp);
-+}
-+
-+static void sbsa_tty_hangup(struct tty_struct *tty)
-+{
-+ tty_port_hangup(tty->port);
-+}
-+
-+static int sbsa_tty_write(struct tty_struct *tty, const unsigned char *buf,
-+ int count)
-+{
-+ sbsa_tty_do_write(buf, count);
-+ return count;
-+}
-+
-+static int sbsa_tty_write_room(struct tty_struct *tty)
-+{
-+ return 32;
-+}
-+
-+static void sbsa_tty_console_write(struct console *co, const char *b,
-+ unsigned count)
-+{
-+ sbsa_tty_do_write(b, count);
-+
-+ if (b[count - 1] == '\n')
-+ sbsa_tty_do_write("\r", 1);
-+}
-+
-+static struct tty_driver *sbsa_tty_console_device(struct console *c,
-+ int *index)
-+{
-+ *index = c->index;
-+ return sbsa_tty_driver;
-+}
-+
-+static int sbsa_tty_console_setup(struct console *co, char *options)
-+{
-+ if ((unsigned)co->index > 0)
-+ return -ENODEV;
-+ if (sbsa_tty->base == NULL)
-+ return -ENODEV;
-+ return 0;
-+}
-+
-+static struct tty_port_operations sbsa_port_ops = {
-+};
-+
-+static const struct tty_operations sbsa_tty_ops = {
-+ .open = sbsa_tty_open,
-+ .close = sbsa_tty_close,
-+ .hangup = sbsa_tty_hangup,
-+ .write = sbsa_tty_write,
-+ .write_room = sbsa_tty_write_room,
-+};
-+
-+static int sbsa_tty_create_driver(void)
-+{
-+ int ret;
-+ struct tty_driver *tty;
-+
-+ sbsa_tty = kzalloc(sizeof(*sbsa_tty), GFP_KERNEL);
-+ if (sbsa_tty == NULL) {
-+ ret = -ENOMEM;
-+ goto err_alloc_sbsa_tty_failed;
-+ }
-+ tty = alloc_tty_driver(1);
-+ if (tty == NULL) {
-+ ret = -ENOMEM;
-+ goto err_alloc_tty_driver_failed;
-+ }
-+ tty->driver_name = "sbsauart";
-+ tty->name = "ttySBSA";
-+ tty->type = TTY_DRIVER_TYPE_SERIAL;
-+ tty->subtype = SERIAL_TYPE_NORMAL;
-+ tty->init_termios = tty_std_termios;
-+ tty->flags = TTY_DRIVER_RESET_TERMIOS | TTY_DRIVER_REAL_RAW |
-+ TTY_DRIVER_DYNAMIC_DEV;
-+ tty_set_operations(tty, &sbsa_tty_ops);
-+ ret = tty_register_driver(tty);
-+ if (ret)
-+ goto err_tty_register_driver_failed;
-+
-+ sbsa_tty_driver = tty;
-+ return 0;
-+
-+err_tty_register_driver_failed:
-+ put_tty_driver(tty);
-+err_alloc_tty_driver_failed:
-+ kfree(sbsa_tty);
-+ sbsa_tty = NULL;
-+err_alloc_sbsa_tty_failed:
-+ return ret;
-+}
-+
-+static void sbsa_tty_delete_driver(void)
-+{
-+ tty_unregister_driver(sbsa_tty_driver);
-+ put_tty_driver(sbsa_tty_driver);
-+ sbsa_tty_driver = NULL;
-+ kfree(sbsa_tty);
-+ sbsa_tty = NULL;
-+}
-+
-+static int sbsa_tty_probe(struct platform_device *pdev)
-+{
-+ struct sbsa_tty *qtty;
-+ int ret = -EINVAL;
-+ int i;
-+ struct resource *r;
-+ struct device *ttydev;
-+ void __iomem *base;
-+ u32 irq;
-+
-+ r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ if (r == NULL)
-+ return -EINVAL;
-+
-+ base = ioremap(r->start, r->end - r->start);
-+ if (base == NULL)
-+ pr_err("sbsa_tty: unable to remap base\n");
-+
-+ r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-+ if (r == NULL)
-+ goto err_unmap;
-+
-+ irq = r->start;
-+
-+ if (pdev->id > 0)
-+ goto err_unmap;
-+
-+ ret = sbsa_tty_create_driver();
-+ if (ret)
-+ goto err_unmap;
-+
-+ qtty = sbsa_tty;
-+ spin_lock_init(&qtty->lock);
-+ tty_port_init(&qtty->port);
-+ qtty->port.ops = &sbsa_port_ops;
-+ qtty->base = base;
-+ qtty->irq = irq;
-+
-+ /* Clear and Mask all IRQs */
-+ writew(0, base + UART011_IMSC);
-+ writew(0xFFFF, base + UART011_ICR);
-+
-+ ret = request_irq(irq, sbsa_tty_interrupt, IRQF_SHARED,
-+ "sbsa_tty", pdev);
-+ if (ret)
-+ goto err_request_irq_failed;
-+
-+ /* Unmask the RX IRQ */
-+ writew(UART011_RXIM | UART011_RTIM, base + UART011_IMSC);
-+
-+ ttydev = tty_port_register_device(&qtty->port, sbsa_tty_driver,
-+ 0, &pdev->dev);
-+ if (IS_ERR(ttydev)) {
-+ ret = PTR_ERR(ttydev);
-+ goto err_tty_register_device_failed;
-+ }
-+
-+ strcpy(qtty->console.name, "ttySBSA");
-+ qtty->console.write = sbsa_tty_console_write;
-+ qtty->console.device = sbsa_tty_console_device;
-+ qtty->console.setup = sbsa_tty_console_setup;
-+ qtty->console.flags = CON_PRINTBUFFER;
-+ /* if no console= on cmdline, make this the console device */
-+ if (!console_set_on_cmdline)
-+ qtty->console.flags |= CON_CONSDEV;
-+ qtty->console.index = pdev->id;
-+ register_console(&qtty->console);
-+
-+ return 0;
-+
-+ tty_unregister_device(sbsa_tty_driver, i);
-+err_tty_register_device_failed:
-+ free_irq(irq, pdev);
-+err_request_irq_failed:
-+ sbsa_tty_delete_driver();
-+err_unmap:
-+ iounmap(base);
-+ return ret;
-+}
-+
-+static int sbsa_tty_remove(struct platform_device *pdev)
-+{
-+ struct sbsa_tty *qtty;
-+
-+ qtty = sbsa_tty;
-+ unregister_console(&qtty->console);
-+ tty_unregister_device(sbsa_tty_driver, pdev->id);
-+ iounmap(qtty->base);
-+ qtty->base = 0;
-+ free_irq(qtty->irq, pdev);
-+ sbsa_tty_delete_driver();
-+ return 0;
-+}
-+
-+static const struct acpi_device_id sbsa_acpi_match[] = {
-+ { "ARMH0011", 0 },
-+ { }
-+};
-+
-+static struct platform_driver sbsa_tty_platform_driver = {
-+ .probe = sbsa_tty_probe,
-+ .remove = sbsa_tty_remove,
-+ .driver = {
-+ .name = "sbsa_tty",
-+ .acpi_match_table = ACPI_PTR(sbsa_acpi_match),
-+ }
-+};
-+
-+module_platform_driver(sbsa_tty_platform_driver);
-+
-+MODULE_LICENSE("GPL v2");
-diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c
-index 555de07..3991aa0 100644
---- a/drivers/tty/serial/8250/8250_dw.c
-+++ b/drivers/tty/serial/8250/8250_dw.c
-@@ -351,10 +351,18 @@ static int dw8250_probe_of(struct uart_port *p,
- static int dw8250_probe_acpi(struct uart_8250_port *up,
- struct dw8250_data *data)
- {
-+ const struct acpi_device_id *id;
- struct uart_port *p = &up->port;
-
- dw8250_setup_port(up);
-
-+ id = acpi_match_device(p->dev->driver->acpi_match_table, p->dev);
-+ if (!id)
-+ return -ENODEV;
-+
-+ if (!p->uartclk)
-+ p->uartclk = (unsigned int)id->driver_data;
-+
- p->iotype = UPIO_MEM32;
- p->serial_in = dw8250_serial_in32;
- p->serial_out = dw8250_serial_out32;
-@@ -577,6 +585,7 @@ static const struct acpi_device_id dw8250_acpi_match[] = {
- { "INT3435", 0 },
- { "80860F0A", 0 },
- { "8086228A", 0 },
-+ { "APMC0D08", 50000000},
- { },
- };
- MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
-diff --git a/drivers/virtio/virtio_mmio.c b/drivers/virtio/virtio_mmio.c
-index 00d115b..cd9b974 100644
---- a/drivers/virtio/virtio_mmio.c
-+++ b/drivers/virtio/virtio_mmio.c
-@@ -100,8 +100,7 @@
- #include <linux/virtio_config.h>
- #include <linux/virtio_mmio.h>
- #include <linux/virtio_ring.h>
--
--
-+#include <linux/acpi.h>
-
- /* The alignment to use between consumer and producer parts of vring.
- * Currently hardcoded to the page size. */
-@@ -635,12 +634,21 @@ static struct of_device_id virtio_mmio_match[] = {
- };
- MODULE_DEVICE_TABLE(of, virtio_mmio_match);
-
-+#ifdef CONFIG_ACPI
-+static const struct acpi_device_id virtio_mmio_acpi_match[] = {
-+ { "LNRO0005", },
-+ { }
-+};
-+MODULE_DEVICE_TABLE(acpi, virtio_mmio_acpi_match);
-+#endif
-+
- static struct platform_driver virtio_mmio_driver = {
- .probe = virtio_mmio_probe,
- .remove = virtio_mmio_remove,
- .driver = {
- .name = "virtio-mmio",
- .of_match_table = virtio_mmio_match,
-+ .acpi_match_table = ACPI_PTR(virtio_mmio_acpi_match),
- },
- };
-
-diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h
-index 61e32ec..1fec6f5 100644
---- a/include/acpi/acpi_bus.h
-+++ b/include/acpi/acpi_bus.h
-@@ -69,6 +69,8 @@ bool acpi_check_dsm(acpi_handle handle, const u8 *uuid, int rev, u64 funcs);
- union acpi_object *acpi_evaluate_dsm(acpi_handle handle, const u8 *uuid,
- int rev, int func, union acpi_object *argv4);
-
-+acpi_status acpi_check_coherency(acpi_handle handle, int *val);
-+
- static inline union acpi_object *
- acpi_evaluate_dsm_typed(acpi_handle handle, const u8 *uuid, int rev, int func,
- union acpi_object *argv4, acpi_object_type type)
-diff --git a/include/acpi/acpi_io.h b/include/acpi/acpi_io.h
-index 444671e..9d573db 100644
---- a/include/acpi/acpi_io.h
-+++ b/include/acpi/acpi_io.h
-@@ -1,11 +1,17 @@
- #ifndef _ACPI_IO_H_
- #define _ACPI_IO_H_
-
-+#include <linux/mm.h>
- #include <linux/io.h>
-
- static inline void __iomem *acpi_os_ioremap(acpi_physical_address phys,
- acpi_size size)
- {
-+#ifdef CONFIG_ARM64
-+ if (!page_is_ram(phys >> PAGE_SHIFT))
-+ return ioremap(phys, size);
-+#endif
-+
- return ioremap_cache(phys, size);
- }
-
-diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h
-index bee5d68..140d514 100644
---- a/include/asm-generic/vmlinux.lds.h
-+++ b/include/asm-generic/vmlinux.lds.h
-@@ -276,6 +276,13 @@
- VMLINUX_SYMBOL(__end_pci_fixups_suspend_late) = .; \
- } \
- \
-+ /* ACPI quirks */ \
-+ .acpi_fixup : AT(ADDR(.acpi_fixup) - LOAD_OFFSET) { \
-+ VMLINUX_SYMBOL(__start_acpi_mcfg_fixups) = .; \
-+ *(.acpi_fixup_mcfg) \
-+ VMLINUX_SYMBOL(__end_acpi_mcfg_fixups) = .; \
-+ } \
-+ \
- /* Built-in firmware blobs */ \
- .builtin_fw : AT(ADDR(.builtin_fw) - LOAD_OFFSET) { \
- VMLINUX_SYMBOL(__start_builtin_fw) = .; \
-diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h
-index ac4888d..d68268d 100644
---- a/include/kvm/arm_vgic.h
-+++ b/include/kvm/arm_vgic.h
-@@ -290,17 +290,19 @@ bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
- #define vgic_initialized(k) (!!((k)->arch.vgic.nr_cpus))
- #define vgic_ready(k) ((k)->arch.vgic.ready)
-
--int vgic_v2_probe(struct device_node *vgic_node,
-- const struct vgic_ops **ops,
-- const struct vgic_params **params);
-+int vgic_v2_dt_probe(struct device_node *vgic_node,
-+ const struct vgic_ops **ops,
-+ const struct vgic_params **params);
-+int vgic_v2_acpi_probe(const struct vgic_ops **ops,
-+ const struct vgic_params **params);
- #ifdef CONFIG_ARM_GIC_V3
--int vgic_v3_probe(struct device_node *vgic_node,
-- const struct vgic_ops **ops,
-- const struct vgic_params **params);
-+int vgic_v3_dt_probe(struct device_node *vgic_node,
-+ const struct vgic_ops **ops,
-+ const struct vgic_params **params);
- #else
--static inline int vgic_v3_probe(struct device_node *vgic_node,
-- const struct vgic_ops **ops,
-- const struct vgic_params **params)
-+static inline int vgic_v3_dt_probe(struct device_node *vgic_node,
-+ const struct vgic_ops **ops,
-+ const struct vgic_params **params)
- {
- return -ENODEV;
- }
-diff --git a/include/linux/acpi.h b/include/linux/acpi.h
-index 856d381..13e6200 100644
---- a/include/linux/acpi.h
-+++ b/include/linux/acpi.h
-@@ -72,6 +72,7 @@ enum acpi_irq_model_id {
- ACPI_IRQ_MODEL_IOAPIC,
- ACPI_IRQ_MODEL_IOSAPIC,
- ACPI_IRQ_MODEL_PLATFORM,
-+ ACPI_IRQ_MODEL_GIC,
- ACPI_IRQ_MODEL_COUNT
- };
-
-diff --git a/include/linux/clocksource.h b/include/linux/clocksource.h
-index abcafaa..4f5caa1 100644
---- a/include/linux/clocksource.h
-+++ b/include/linux/clocksource.h
-@@ -346,4 +346,10 @@ extern void clocksource_of_init(void);
- static inline void clocksource_of_init(void) {}
- #endif
-
-+#ifdef CONFIG_ACPI
-+void acpi_generic_timer_init(void);
-+#else
-+static inline void acpi_generic_timer_init(void) {}
-+#endif
-+
- #endif /* _LINUX_CLOCKSOURCE_H */
-diff --git a/include/linux/irqchip/arm-gic-acpi.h b/include/linux/irqchip/arm-gic-acpi.h
-new file mode 100644
-index 0000000..ad5b577
---- /dev/null
-+++ b/include/linux/irqchip/arm-gic-acpi.h
-@@ -0,0 +1,31 @@
-+/*
-+ * Copyright (C) 2014, Linaro Ltd.
-+ * Author: Tomasz Nowicki <tomasz.nowicki at linaro.org>
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * published by the Free Software Foundation.
-+ */
-+
-+#ifndef ARM_GIC_ACPI_H_
-+#define ARM_GIC_ACPI_H_
-+
-+#ifdef CONFIG_ACPI
-+
-+/*
-+ * Hard code here, we can not get memory size from MADT (but FDT does),
-+ * Actually no need to do that, because this size can be inferred
-+ * from GIC spec.
-+ */
-+#define ACPI_GICV2_DIST_MEM_SIZE (SZ_4K)
-+#define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K)
-+
-+struct acpi_table_header;
-+
-+void acpi_gic_init(void);
-+int gic_v2_acpi_init(struct acpi_table_header *table);
-+#else
-+static inline void acpi_gic_init(void) { }
-+#endif
-+
-+#endif /* ARM_GIC_ACPI_H_ */
-diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
-index 71d706d..5c55f37 100644
---- a/include/linux/irqchip/arm-gic.h
-+++ b/include/linux/irqchip/arm-gic.h
-@@ -55,6 +55,8 @@
- (GICD_INT_DEF_PRI << 8) |\
- GICD_INT_DEF_PRI)
-
-+#define GIC_DIST_SOFTINT_NSATT 0x8000
-+
- #define GICH_HCR 0x0
- #define GICH_VTR 0x4
- #define GICH_VMCR 0x8
-diff --git a/include/linux/pci.h b/include/linux/pci.h
-index 360a966..1476a66 100644
---- a/include/linux/pci.h
-+++ b/include/linux/pci.h
-@@ -564,15 +564,6 @@ struct pci_ops {
- int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
- };
-
--/*
-- * ACPI needs to be able to access PCI config space before we've done a
-- * PCI bus scan and created pci_bus structures.
-- */
--int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
-- int reg, int len, u32 *val);
--int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
-- int reg, int len, u32 val);
--
- struct pci_bus_region {
- dma_addr_t start;
- dma_addr_t end;
-@@ -1329,6 +1320,16 @@ typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
- unsigned int command_bits, u32 flags);
- void pci_register_set_vga_state(arch_set_vga_state_t func);
-
-+/*
-+ * ACPI needs to be able to access PCI config space before we've done a
-+ * PCI bus scan and created pci_bus structures.
-+ */
-+int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
-+ int reg, int len, u32 *val);
-+int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
-+ int reg, int len, u32 val);
-+void pcibios_penalize_isa_irq(int irq, int active);
-+
- #else /* CONFIG_PCI is not enabled */
-
- /*
-@@ -1430,6 +1431,23 @@ static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
- unsigned int devfn)
- { return NULL; }
-
-+static inline struct pci_bus *pci_find_bus(int domain, int busnr)
-+{ return NULL; }
-+
-+static inline int pci_bus_write_config_byte(struct pci_bus *bus,
-+ unsigned int devfn, int where, u8 val)
-+{ return -ENOSYS; }
-+
-+static inline int raw_pci_read(unsigned int domain, unsigned int bus,
-+ unsigned int devfn, int reg, int len, u32 *val)
-+{ return -ENOSYS; }
-+
-+static inline int raw_pci_write(unsigned int domain, unsigned int bus,
-+ unsigned int devfn, int reg, int len, u32 val)
-+{ return -ENOSYS; }
-+
-+static inline void pcibios_penalize_isa_irq(int irq, int active) { }
-+
- static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
- static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
- static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
-@@ -1639,7 +1657,6 @@ int pcibios_set_pcie_reset_state(struct pci_dev *dev,
- enum pcie_reset_state state);
- int pcibios_add_device(struct pci_dev *dev);
- void pcibios_release_device(struct pci_dev *dev);
--void pcibios_penalize_isa_irq(int irq, int active);
-
- #ifdef CONFIG_HIBERNATE_CALLBACKS
- extern struct dev_pm_ops pcibios_pm_ops;
-diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c
-index 1c0772b..b9d11aa 100644
---- a/virt/kvm/arm/arch_timer.c
-+++ b/virt/kvm/arm/arch_timer.c
-@@ -21,9 +21,11 @@
- #include <linux/kvm.h>
- #include <linux/kvm_host.h>
- #include <linux/interrupt.h>
-+#include <linux/acpi.h>
-
- #include <clocksource/arm_arch_timer.h>
- #include <asm/arch_timer.h>
-+#include <asm/acpi.h>
-
- #include <kvm/arm_vgic.h>
- #include <kvm/arm_arch_timer.h>
-@@ -246,60 +248,91 @@ static const struct of_device_id arch_timer_of_match[] = {
- {},
- };
-
--int kvm_timer_hyp_init(void)
-+static int kvm_timer_ppi_parse_dt(unsigned int *ppi)
- {
- struct device_node *np;
-- unsigned int ppi;
-- int err;
--
-- timecounter = arch_timer_get_timecounter();
-- if (!timecounter)
-- return -ENODEV;
-
- np = of_find_matching_node(NULL, arch_timer_of_match);
- if (!np) {
-- kvm_err("kvm_arch_timer: can't find DT node\n");
- return -ENODEV;
- }
-
-- ppi = irq_of_parse_and_map(np, 2);
-- if (!ppi) {
-- kvm_err("kvm_arch_timer: no virtual timer interrupt\n");
-- err = -EINVAL;
-- goto out;
-+ *ppi = irq_of_parse_and_map(np, 2);
-+ if (*ppi == 0) {
-+ of_node_put(np);
-+ return -EINVAL;
- }
-
-- err = request_percpu_irq(ppi, kvm_arch_timer_handler,
-- "kvm guest timer", kvm_get_running_vcpus());
-- if (err) {
-- kvm_err("kvm_arch_timer: can't request interrupt %d (%d)\n",
-- ppi, err);
-- goto out;
-- }
-+ return 0;
-+}
-
-- host_vtimer_irq = ppi;
-+extern int arch_timer_ppi[];
-
-- err = __register_cpu_notifier(&kvm_timer_cpu_nb);
-- if (err) {
-- kvm_err("Cannot register timer CPU notifier\n");
-- goto out_free;
-- }
-+static int kvm_timer_ppi_parse_acpi(unsigned int *ppi)
-
-- wqueue = create_singlethread_workqueue("kvm_arch_timer");
-- if (!wqueue) {
-- err = -ENOMEM;
-- goto out_free;
-- }
-+{
-+ /* retrieve VIRT_PPI info */
-+ *ppi = arch_timer_ppi[2];
-
-- kvm_info("%s IRQ%d\n", np->name, ppi);
-- on_each_cpu(kvm_timer_init_interrupt, NULL, 1);
-+ if (*ppi == 0)
-+ return -EINVAL;
-+ else
-+ return 0;
-+}
-+
-+int kvm_timer_hyp_init(void)
-+{
-+ unsigned int ppi;
-+ int err;
-+
-+ timecounter = arch_timer_get_timecounter();
-+ if (!timecounter)
-+ return -ENODEV;
-+
-+ /* PPI DT parsing */
-+ err = kvm_timer_ppi_parse_dt(&ppi);
-
-- goto out;
-+ /* if DT parsing fails, try ACPI next */
-+ if (err && !acpi_disabled)
-+ err = kvm_timer_ppi_parse_acpi(&ppi);
-+
-+ if (err) {
-+ kvm_err("kvm_timer_hyp_init: can't find virtual timer info or "
-+ "config virtual timer interrupt\n");
-+ return err;
-+ }
-+
-+ /* configure IRQ handler */
-+ err = request_percpu_irq(ppi, kvm_arch_timer_handler,
-+ "kvm guest timer", kvm_get_running_vcpus());
-+ if (err) {
-+ kvm_err("kvm_arch_timer: can't request interrupt %d (%d)\n",
-+ ppi, err);
-+ goto out;
-+ }
-+
-+ host_vtimer_irq = ppi;
-+
-+ err = __register_cpu_notifier(&kvm_timer_cpu_nb);
-+ if (err) {
-+ kvm_err("Cannot register timer CPU notifier\n");
-+ goto out_free;
-+ }
-+
-+ wqueue = create_singlethread_workqueue("kvm_arch_timer");
-+ if (!wqueue) {
-+ err = -ENOMEM;
-+ goto out_free;
-+ }
-+
-+ kvm_info("timer IRQ%d\n", ppi);
-+ on_each_cpu(kvm_timer_init_interrupt, NULL, 1);
-+
-+ goto out;
- out_free:
-- free_percpu_irq(ppi, kvm_get_running_vcpus());
-+ free_percpu_irq(ppi, kvm_get_running_vcpus());
- out:
-- of_node_put(np);
-- return err;
-+ return err;
- }
-
- void kvm_timer_vcpu_terminate(struct kvm_vcpu *vcpu)
-diff --git a/virt/kvm/arm/vgic-v2.c b/virt/kvm/arm/vgic-v2.c
-index 2935405..510049c 100644
---- a/virt/kvm/arm/vgic-v2.c
-+++ b/virt/kvm/arm/vgic-v2.c
-@@ -19,6 +19,7 @@
- #include <linux/kvm.h>
- #include <linux/kvm_host.h>
- #include <linux/interrupt.h>
-+#include <linux/acpi.h>
- #include <linux/io.h>
- #include <linux/of.h>
- #include <linux/of_address.h>
-@@ -26,6 +27,7 @@
-
- #include <linux/irqchip/arm-gic.h>
-
-+#include <asm/acpi.h>
- #include <asm/kvm_emulate.h>
- #include <asm/kvm_arm.h>
- #include <asm/kvm_mmu.h>
-@@ -159,7 +161,7 @@ static const struct vgic_ops vgic_v2_ops = {
- static struct vgic_params vgic_v2_params;
-
- /**
-- * vgic_v2_probe - probe for a GICv2 compatible interrupt controller in DT
-+ * vgic_v2_dt_probe - probe for a GICv2 compatible interrupt controller in DT
- * @node: pointer to the DT node
- * @ops: address of a pointer to the GICv2 operations
- * @params: address of a pointer to HW-specific parameters
-@@ -168,7 +170,7 @@ static struct vgic_params vgic_v2_params;
- * in *ops and the HW parameters in *params. Returns an error code
- * otherwise.
- */
--int vgic_v2_probe(struct device_node *vgic_node,
-+int vgic_v2_dt_probe(struct device_node *vgic_node,
- const struct vgic_ops **ops,
- const struct vgic_params **params)
- {
-@@ -222,11 +224,22 @@ int vgic_v2_probe(struct device_node *vgic_node,
- }
-
- if (!PAGE_ALIGNED(resource_size(&vcpu_res))) {
-+#if 0
- kvm_err("GICV size 0x%llx not a multiple of page size 0x%lx\n",
- (unsigned long long)resource_size(&vcpu_res),
- PAGE_SIZE);
- ret = -ENXIO;
- goto out_unmap;
-+#else
-+ /*
-+ * The check fails for arm64 with 64K pagesize and certain firmware.
-+ * Ignore for now until firmware takes care of the problem.
-+ */
-+ kvm_info("GICV size 0x%llx not a multiple of page size 0x%lx\n",
-+ (unsigned long long)resource_size(&vcpu_res),
-+ PAGE_SIZE);
-+ kvm_info("Update DT to assign GICV a multiple of kernel page size \n");
-+#endif
- }
-
- vgic->vcpu_base = vcpu_res.start;
-@@ -245,3 +258,72 @@ out:
- of_node_put(vgic_node);
- return ret;
- }
-+
-+struct acpi_madt_generic_interrupt *vgic_acpi;
-+static void gic_get_acpi_header(struct acpi_subtable_header *header)
-+{
-+ vgic_acpi = (struct acpi_madt_generic_interrupt *)header;
-+}
-+
-+int vgic_v2_acpi_probe(const struct vgic_ops **ops,
-+ const struct vgic_params **params)
-+{
-+ struct vgic_params *vgic = &vgic_v2_params;
-+ int irq_mode, ret;
-+
-+ /* MADT table */
-+ ret = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT,
-+ (acpi_tbl_entry_handler)gic_get_acpi_header, 0);
-+ if (!ret) {
-+ pr_err("Failed to get MADT VGIC CPU entry\n");
-+ ret = -ENODEV;
-+ goto out;
-+ }
-+
-+ /* IRQ trigger mode */
-+ irq_mode = (vgic_acpi->flags & ACPI_MADT_VGIC_IRQ_MODE) ?
-+ ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE;
-+ /* According to GIC-400 manual, all PPIs are active-LOW, level
-+ * sensative. We register IRQ as active-low.
-+ */
-+ vgic->maint_irq = acpi_register_gsi(NULL, vgic_acpi->vgic_interrupt,
-+ irq_mode, ACPI_ACTIVE_LOW);
-+ if (!vgic->maint_irq) {
-+ pr_err("Cannot register VGIC ACPI maintenance irq\n");
-+ ret = -ENXIO;
-+ goto out;
-+ }
-+
-+ /* GICH resource */
-+ vgic->vctrl_base = ioremap(vgic_acpi->gich_base_address, SZ_8K);
-+ if (!vgic->vctrl_base) {
-+ pr_err("cannot ioremap GICH memory\n");
-+ ret = -ENOMEM;
-+ goto out;
-+ }
-+
-+ vgic->nr_lr = readl_relaxed(vgic->vctrl_base + GICH_VTR);
-+ vgic->nr_lr = (vgic->nr_lr & 0x3f) + 1;
-+
-+ ret = create_hyp_io_mappings(vgic->vctrl_base,
-+ vgic->vctrl_base + SZ_8K,
-+ vgic_acpi->gich_base_address);
-+ if (ret) {
-+ kvm_err("Cannot map GICH into hyp\n");
-+ goto out;
-+ }
-+
-+ vgic->vcpu_base = vgic_acpi->gicv_base_address;
-+
-+ kvm_info("GICH base=0x%llx, GICV base=0x%llx, IRQ=%d\n",
-+ (unsigned long long)vgic_acpi->gich_base_address,
-+ (unsigned long long)vgic_acpi->gicv_base_address,
-+ vgic->maint_irq);
-+
-+ vgic->type = VGIC_V2;
-+ *ops = &vgic_v2_ops;
-+ *params = vgic;
-+
-+out:
-+ return ret;
-+}
-diff --git a/virt/kvm/arm/vgic-v3.c b/virt/kvm/arm/vgic-v3.c
-index 1c2c8ee..8b56920 100644
---- a/virt/kvm/arm/vgic-v3.c
-+++ b/virt/kvm/arm/vgic-v3.c
-@@ -173,7 +173,7 @@ static const struct vgic_ops vgic_v3_ops = {
- static struct vgic_params vgic_v3_params;
-
- /**
-- * vgic_v3_probe - probe for a GICv3 compatible interrupt controller in DT
-+ * vgic_v3_dt_probe - probe for a GICv3 compatible interrupt controller in DT
- * @node: pointer to the DT node
- * @ops: address of a pointer to the GICv3 operations
- * @params: address of a pointer to HW-specific parameters
-@@ -182,9 +182,9 @@ static struct vgic_params vgic_v3_params;
- * in *ops and the HW parameters in *params. Returns an error code
- * otherwise.
- */
--int vgic_v3_probe(struct device_node *vgic_node,
-- const struct vgic_ops **ops,
-- const struct vgic_params **params)
-+int vgic_v3_dt_probe(struct device_node *vgic_node,
-+ const struct vgic_ops **ops,
-+ const struct vgic_params **params)
- {
- int ret = 0;
- u32 gicv_idx;
-diff --git a/virt/kvm/arm/vgic.c b/virt/kvm/arm/vgic.c
-index 03affc7..cdd4c64 100644
---- a/virt/kvm/arm/vgic.c
-+++ b/virt/kvm/arm/vgic.c
-@@ -25,9 +25,11 @@
- #include <linux/of_address.h>
- #include <linux/of_irq.h>
- #include <linux/uaccess.h>
-+#include <linux/acpi.h>
-
- #include <linux/irqchip/arm-gic.h>
-
-+#include <asm/acpi.h>
- #include <asm/kvm_emulate.h>
- #include <asm/kvm_arm.h>
- #include <asm/kvm_mmu.h>
-@@ -2431,8 +2433,8 @@ static struct notifier_block vgic_cpu_nb = {
- };
-
- static const struct of_device_id vgic_ids[] = {
-- { .compatible = "arm,cortex-a15-gic", .data = vgic_v2_probe, },
-- { .compatible = "arm,gic-v3", .data = vgic_v3_probe, },
-+ { .compatible = "arm,cortex-a15-gic", .data = vgic_v2_dt_probe, },
-+ { .compatible = "arm,gic-v3", .data = vgic_v3_dt_probe, },
- {},
- };
-
-@@ -2442,20 +2444,26 @@ int kvm_vgic_hyp_init(void)
- const int (*vgic_probe)(struct device_node *,const struct vgic_ops **,
- const struct vgic_params **);
- struct device_node *vgic_node;
-- int ret;
-+ int ret = -ENODEV;
-
-- vgic_node = of_find_matching_node_and_match(NULL,
-- vgic_ids, &matched_id);
-- if (!vgic_node) {
-- kvm_err("error: no compatible GIC node found\n");
-- return -ENODEV;
-+ /* probe VGIC */
-+ if ((vgic_node = of_find_matching_node_and_match(NULL,
-+ vgic_ids, &matched_id))) {
-+ /* probe VGIC in DT */
-+ vgic_probe = matched_id->data;
-+ ret = vgic_probe(vgic_node, &vgic_ops, &vgic);
-+ }
-+ else if (!acpi_disabled) {
-+ /* probe VGIC in ACPI */
-+ ret = vgic_v2_acpi_probe(&vgic_ops, &vgic);
- }
-
-- vgic_probe = matched_id->data;
-- ret = vgic_probe(vgic_node, &vgic_ops, &vgic);
-- if (ret)
-+ if (ret) {
-+ kvm_err("error: no compatible GIC info found\n");
- return ret;
-+ }
-
-+ /* configuration */
- ret = request_percpu_irq(vgic->maint_irq, vgic_maintenance_handler,
- "vgic", kvm_get_running_vcpus());
- if (ret) {
diff --git a/kernel.spec b/kernel.spec
index 00edda2..ca26ca0 100644
--- a/kernel.spec
+++ b/kernel.spec
@@ -48,19 +48,19 @@ Summary: The Linux kernel
# base_sublevel is the kernel version we're starting with and patching
# on top of -- for example, 3.1-rc7-git1 starts with a 3.0 base,
# which yields a base_sublevel of 0.
-%define base_sublevel 19
+%define base_sublevel 0
## If this is a released kernel ##
%if 0%{?released_kernel}
# Do we have a -stable update to apply?
-%define stable_update 8
+%define stable_update 3
# Set rpm version accordingly
%if 0%{?stable_update}
%define stablerev %{stable_update}
%define stable_base %{stable_update}
%endif
-%define rpmversion 3.%{base_sublevel}.%{stable_update}
+%define rpmversion 4.%{base_sublevel}.%{stable_update}
## The not-released-kernel case ##
%else
@@ -71,7 +71,7 @@ Summary: The Linux kernel
# The git snapshot level
%define gitrev 0
# Set rpm version accordingly
-%define rpmversion 3.%{upstream_sublevel}.0
+%define rpmversion 4.%{upstream_sublevel}.0
%endif
# Nb: The above rcrev and gitrev values automagically define Patch00 and Patch01 below.
@@ -152,7 +152,7 @@ Summary: The Linux kernel
%endif
# The kernel tarball/base version
-%define kversion 3.%{base_sublevel}
+%define kversion 4.%{base_sublevel}
%define make_target bzImage
@@ -409,7 +409,7 @@ BuildRequires: binutils-%{_build_arch}-linux-gnu, gcc-%{_build_arch}-linux-gnu
%define cross_opts CROSS_COMPILE=%{_build_arch}-linux-gnu-
%endif
-Source0: ftp://ftp.kernel.org/pub/linux/kernel/v3.0/linux-%{kversion}.tar.xz
+Source0: ftp://ftp.kernel.org/pub/linux/kernel/v4.0/linux-%{kversion}.tar.xz
Source10: perf-man-%{kversion}.tar.gz
Source11: x509.genkey
@@ -471,7 +471,7 @@ Source2001: cpupower.config
# For a stable release kernel
%if 0%{?stable_update}
%if 0%{?stable_base}
-%define stable_patch_00 patch-3.%{base_sublevel}.%{stable_base}.xz
+%define stable_patch_00 patch-4.%{base_sublevel}.%{stable_base}.xz
Patch00: %{stable_patch_00}
%endif
@@ -480,14 +480,14 @@ Patch00: %{stable_patch_00}
# near the top of this spec file.
%else
%if 0%{?rcrev}
-Patch00: patch-3.%{upstream_sublevel}-rc%{rcrev}.xz
+Patch00: patch-4.%{upstream_sublevel}-rc%{rcrev}.xz
%if 0%{?gitrev}
-Patch01: patch-3.%{upstream_sublevel}-rc%{rcrev}-git%{gitrev}.xz
+Patch01: patch-4.%{upstream_sublevel}-rc%{rcrev}-git%{gitrev}.xz
%endif
%else
# pre-{base_sublevel+1}-rc1 case
%if 0%{?gitrev}
-Patch00: patch-3.%{base_sublevel}-git%{gitrev}.xz
+Patch00: patch-4.%{base_sublevel}-git%{gitrev}.xz
%endif
%endif
%endif
@@ -550,15 +550,16 @@ Patch1018: MODSIGN-Support-not-importing-certs-from-db.patch
Patch1019: Add-sysrq-option-to-disable-secure-boot-mode.patch
+# esrt
+Patch1020: efi-Add-esrt-support.patch
+
# virt + ksm patches
# DRM
# nouveau + drm fixes
# intel drm is all merged upstream
-Patch1825: drm-i915-tame-the-chattermouth-v2.patch
Patch1826: drm-i915-hush-check-crtc-state.patch
-Patch1827: drm-i915-Disable-verbose-state-checks.patch
# Quiet boot fixes
@@ -578,6 +579,10 @@ Patch15000: watchdog-Disable-watchdog-on-virtual-machines.patch
# PPC
# ARM64
+Patch21000: net-amd-Add-xgbe-a0-driver.patch
+Patch21001: amd-xgbe-phy-a0-Add-support-for-XGBE-PHY-on-A0.patch
+Patch21002: arm64-avoid-needing-console-to-enable-serial-console.patch
+Patch21003: usb-make-xhci-platform-driver-use-64-bit-or-32-bit-D.patch
# ARMv7
Patch21020: ARM-tegra-usb-no-reset.patch
@@ -587,14 +592,9 @@ Patch21023: arm-dts-am335x-bone-common-enable-and-use-i2c2.patch
Patch21024: arm-dts-am335x-bone-common-setup-default-pinmux-http.patch
Patch21025: arm-dts-am335x-bone-common-add-uart2_pins-uart4_pins.patch
Patch21026: pinctrl-pinctrl-single-must-be-initialized-early.patch
-
+Patch21027: 0001-drivers-rtc-rtc-em3027.c-add-device-tree-support.patch
Patch21028: arm-i.MX6-Utilite-device-dtb.patch
-# IOMMU crash fixes - https://lists.linuxfoundation.org/pipermail/iommu/2015-February/012329.html
-Patch21030: iommu-omap-Play-nice-in-multi-platform-builds.patch
-Patch21031: iommu-exynos-Play-nice-in-multi-platform-builds.patch
-Patch21032: iommu-rockchip-Play-nice-in-multi-platform-builds.patch
-
Patch21100: arm-highbank-l2-reverts.patch
#rhbz 754518
@@ -611,21 +611,11 @@ Patch22000: weird-root-dentry-name-debug.patch
#rhbz 1094948
Patch26131: acpi-video-Add-disable_native_backlight-quirk-for-Sa.patch
-#rhbz 1186097
-Patch26135: acpi-video-add-disable_native_backlight_quirk_for_samsung_510r.patch
-
-#CVE-XXXX-XXXX rhbz 1189864 1192079
-Patch26136: vhost-scsi-potential-memory-corruption.patch
-
#CVE-2015-0275 rhbz 1193907 1195178
Patch26138: ext4-Allocate-entire-range-in-zero-range.patch
-#rhbz 1200777 1200778
-Patch26159: Input-synaptics-retrieve-the-extended-capabilities-i.patch
-Patch26160: Input-synaptics-remove-TOPBUTTONPAD-property-for-Len.patch
-Patch26161: Input-synaptics-re-route-tracksticks-buttons-on-the-.patch
-Patch26162: Input-synaptics-remove-X1-Carbon-3rd-gen-from-the-to.patch
-Patch26163: Input-synaptics-remove-X250-from-the-topbuttonpad-li.patch
+#rhbz 1196825
+Patch26140: security-yama-Remove-unnecessary-selects-from-Kconfi.patch
#rhbz 1201532
Patch26168: HID-multitouch-add-support-of-clickpads.patch
@@ -634,29 +624,26 @@ Patch26168: HID-multitouch-add-support-of-clickpads.patch
Patch26170: acpi-video-Allow-forcing-native-backlight-on-non-win.patch
Patch26171: acpi-video-Add-force-native-backlight-quirk-for-Leno.patch
-#CVE-2015-2666 rhbz 1204724 1204722
-Patch26172: x86-microcode-intel-Guard-against-stack-overflow-in-.patch
-
-# git clone ssh://git.fedorahosted.org/git/kernel-arm64.git, git diff master...devel
-Patch30000: kernel-arm64.patch
-
#CVE-2015-2150 rhbz 1196266 1200397
Patch26175: xen-pciback-Don-t-disable-PCI_COMMAND-on-PCI-device-.patch
#rhbz 1208953
-Patch26179: pty-Fix-input-race-when-closing.patch
+Patch26178: pty-Fix-input-race-when-closing.patch
#rhbz 1210801
-Patch26180: HID-logitech-hidpp-add-a-module-parameter-to-keep-fi.patch
+Patch26179: HID-logitech-hidpp-add-a-module-parameter-to-keep-fi.patch
-#rhbz 1205083
-Patch26181: 0001-iwlwifi-mvm-remove-WARN_ON-for-invalid-BA-notificati.patch
+#rhbz 1209088
+Patch26180: Input-atmel_mxt_ts-implement-support-for-T100-touch-.patch
+Patch26181: Input-atmel_mxt_ts-split-out-touchpad-initialisation.patch
+Patch26182: Input-atmel_mxt_ts-add-support-for-Google-Pixel-2.patch
-#rhbz 1208999
-Patch26182: SCSI-add-1024-max-sectors-black-list-flag.patch
+#rhbz 1188741
+Patch26183: 0001-ALSA-hda-realtek-Support-Dell-headset-mode-for-ALC28.patch
+Patch26184: 0001-ALSA-hda-realtek-Support-headset-mode-for-ALC286-288.patch
-#rhbz 1204390
-Patch26189: 0001-cx18-add-missing-caps-for-the-PCM-video-device.patch
+#rhbz 1210857
+Patch26192: blk-loop-avoid-too-many-pending-per-work-IO.patch
#rhbz 1206036 1215989
Patch26193: toshiba_acpi-Do-not-register-vendor-backlight-when-a.patch
@@ -664,6 +651,12 @@ Patch26193: toshiba_acpi-Do-not-register-vendor-backlight-when-a.patch
#rhbz 1218662
Patch26199: libata-Blacklist-queued-TRIM-on-all-Samsung-800-seri.patch
+#rhbz 1219343
+Patch26200: 0001-HID-usbhid-Add-HID_QUIRK_NOGET-for-Aten-DVI-KVM-swit.patch
+
+#rhbz 1220915
+Patch26201: ovl-don-t-remove-non-empty-opaque-directory.patch
+
# END OF PATCH DEFINITIONS
%endif
@@ -1028,7 +1021,7 @@ ApplyPatch()
exit 1
fi
if ! grep -E "^Patch[0-9]+: $patch\$" %{_specdir}/${RPM_PACKAGE_NAME%%%%%{?variant}}.spec ; then
- if [ "${patch:0:8}" != "patch-3." ] ; then
+ if [ "${patch:0:8}" != "patch-4." ] ; then
echo "ERROR: Patch $patch not listed as a source patch in specfile"
exit 1
fi
@@ -1061,20 +1054,20 @@ ApplyOptionalPatch()
# Update to latest upstream.
%if 0%{?released_kernel}
-%define vanillaversion 3.%{base_sublevel}
+%define vanillaversion 4.%{base_sublevel}
# non-released_kernel case
%else
%if 0%{?rcrev}
-%define vanillaversion 3.%{upstream_sublevel}-rc%{rcrev}
+%define vanillaversion 4.%{upstream_sublevel}-rc%{rcrev}
%if 0%{?gitrev}
-%define vanillaversion 3.%{upstream_sublevel}-rc%{rcrev}-git%{gitrev}
+%define vanillaversion 4.%{upstream_sublevel}-rc%{rcrev}-git%{gitrev}
%endif
%else
# pre-{base_sublevel+1}-rc1 case
%if 0%{?gitrev}
-%define vanillaversion 3.%{base_sublevel}-git%{gitrev}
+%define vanillaversion 4.%{base_sublevel}-git%{gitrev}
%else
-%define vanillaversion 3.%{base_sublevel}
+%define vanillaversion 4.%{base_sublevel}
%endif
%endif
%endif
@@ -1087,7 +1080,7 @@ ApplyOptionalPatch()
# Build a list of the other top-level kernel tree directories.
# This will be used to hardlink identical vanilla subdirs.
-sharedirs=$(find "$PWD" -maxdepth 1 -type d -name 'kernel-3.*' \
+sharedirs=$(find "$PWD" -maxdepth 1 -type d -name 'kernel-4.*' \
| grep -x -v "$PWD"/kernel-%{kversion}%{?dist}) ||:
# Delete all old stale trees.
@@ -1158,14 +1151,14 @@ if [ ! -d kernel-%{kversion}%{?dist}/vanilla-%{vanillaversion} ]; then
# Update vanilla to the latest upstream.
# (non-released_kernel case only)
%if 0%{?rcrev}
- ApplyPatch patch-3.%{upstream_sublevel}-rc%{rcrev}.xz
+ ApplyPatch patch-4.%{upstream_sublevel}-rc%{rcrev}.xz
%if 0%{?gitrev}
- ApplyPatch patch-3.%{upstream_sublevel}-rc%{rcrev}-git%{gitrev}.xz
+ ApplyPatch patch-4.%{upstream_sublevel}-rc%{rcrev}-git%{gitrev}.xz
%endif
%else
# pre-{base_sublevel+1}-rc1 case
%if 0%{?gitrev}
- ApplyPatch patch-3.%{base_sublevel}-git%{gitrev}.xz
+ ApplyPatch patch-4.%{base_sublevel}-git%{gitrev}.xz
%endif
%endif
@@ -1236,25 +1229,24 @@ ApplyPatch lib-cpumask-Make-CPUMASK_OFFSTACK-usable-without-deb.patch
# PPC
# ARM64
+ApplyPatch net-amd-Add-xgbe-a0-driver.patch
+ApplyPatch amd-xgbe-phy-a0-Add-support-for-XGBE-PHY-on-A0.patch
+ApplyPatch arm64-avoid-needing-console-to-enable-serial-console.patch
+ApplyPatch usb-make-xhci-platform-driver-use-64-bit-or-32-bit-D.patch
#
# ARM
#
ApplyPatch ARM-tegra-usb-no-reset.patch
-
ApplyPatch arm-dts-am335x-boneblack-lcdc-add-panel-info.patch
ApplyPatch arm-dts-am335x-boneblack-add-cpu0-opp-points.patch
ApplyPatch arm-dts-am335x-bone-common-enable-and-use-i2c2.patch
ApplyPatch arm-dts-am335x-bone-common-setup-default-pinmux-http.patch
ApplyPatch arm-dts-am335x-bone-common-add-uart2_pins-uart4_pins.patch
ApplyPatch pinctrl-pinctrl-single-must-be-initialized-early.patch
-
+ApplyPatch 0001-drivers-rtc-rtc-em3027.c-add-device-tree-support.patch
ApplyPatch arm-i.MX6-Utilite-device-dtb.patch
-ApplyPatch iommu-omap-Play-nice-in-multi-platform-builds.patch
-ApplyPatch iommu-exynos-Play-nice-in-multi-platform-builds.patch
-ApplyPatch iommu-rockchip-Play-nice-in-multi-platform-builds.patch
-
ApplyPatch arm-highbank-l2-reverts.patch
#
@@ -1341,6 +1333,8 @@ ApplyPatch MODSIGN-Support-not-importing-certs-from-db.patch
ApplyPatch Add-sysrq-option-to-disable-secure-boot-mode.patch
+ApplyPatch efi-Add-esrt-support.patch
+
# Assorted Virt Fixes
# DRM core
@@ -1348,9 +1342,7 @@ ApplyPatch Add-sysrq-option-to-disable-secure-boot-mode.patch
# Nouveau DRM
# Intel DRM
-ApplyPatch drm-i915-tame-the-chattermouth-v2.patch
ApplyPatch drm-i915-hush-check-crtc-state.patch
-ApplyPatch drm-i915-Disable-verbose-state-checks.patch
# Radeon DRM
@@ -1379,21 +1371,11 @@ ApplyPatch ath9k-rx-dma-stop-check.patch
#rhbz 1094948
ApplyPatch acpi-video-Add-disable_native_backlight-quirk-for-Sa.patch
-#rhbz 1186097
-ApplyPatch acpi-video-add-disable_native_backlight_quirk_for_samsung_510r.patch
-
-#CVE-XXXX-XXXX rhbz 1189864 1192079
-ApplyPatch vhost-scsi-potential-memory-corruption.patch
-
#CVE-2015-0275 rhbz 1193907 1195178
ApplyPatch ext4-Allocate-entire-range-in-zero-range.patch
-#rhbz 1200777 1200778
-ApplyPatch Input-synaptics-retrieve-the-extended-capabilities-i.patch
-ApplyPatch Input-synaptics-remove-TOPBUTTONPAD-property-for-Len.patch
-ApplyPatch Input-synaptics-re-route-tracksticks-buttons-on-the-.patch
-ApplyPatch Input-synaptics-remove-X1-Carbon-3rd-gen-from-the-to.patch
-ApplyPatch Input-synaptics-remove-X250-from-the-topbuttonpad-li.patch
+#rhbz 1196825
+ApplyPatch security-yama-Remove-unnecessary-selects-from-Kconfi.patch
#rhbz 1201532
ApplyPatch HID-multitouch-add-support-of-clickpads.patch
@@ -1402,16 +1384,6 @@ ApplyPatch HID-multitouch-add-support-of-clickpads.patch
ApplyPatch acpi-video-Allow-forcing-native-backlight-on-non-win.patch
ApplyPatch acpi-video-Add-force-native-backlight-quirk-for-Leno.patch
-#CVE-2015-2666 rhbz 1204724 1204722
-ApplyPatch x86-microcode-intel-Guard-against-stack-overflow-in-.patch
-
-%if 0%{?aarch64patches}
-ApplyPatch kernel-arm64.patch
-%ifnarch aarch64 # this is stupid, but i want to notice before secondary koji does.
-ApplyPatch kernel-arm64.patch -R
-%endif
-%endif
-
#CVE-2015-2150 rhbz 1196266 1200397
ApplyPatch xen-pciback-Don-t-disable-PCI_COMMAND-on-PCI-device-.patch
@@ -1421,14 +1393,17 @@ ApplyPatch pty-Fix-input-race-when-closing.patch
#rhbz 1210801
ApplyPatch HID-logitech-hidpp-add-a-module-parameter-to-keep-fi.patch
-#rhbz 1205083
-ApplyPatch 0001-iwlwifi-mvm-remove-WARN_ON-for-invalid-BA-notificati.patch
+#rhbz 1209088
+ApplyPatch Input-atmel_mxt_ts-implement-support-for-T100-touch-.patch
+ApplyPatch Input-atmel_mxt_ts-split-out-touchpad-initialisation.patch
+ApplyPatch Input-atmel_mxt_ts-add-support-for-Google-Pixel-2.patch
-#rhbz 1208999
-ApplyPatch SCSI-add-1024-max-sectors-black-list-flag.patch
+#rhbz 1188741
+ApplyPatch 0001-ALSA-hda-realtek-Support-Dell-headset-mode-for-ALC28.patch
+ApplyPatch 0001-ALSA-hda-realtek-Support-headset-mode-for-ALC286-288.patch
-#rhbz 1204390
-ApplyPatch 0001-cx18-add-missing-caps-for-the-PCM-video-device.patch
+#rhbz 1210857
+ApplyPatch blk-loop-avoid-too-many-pending-per-work-IO.patch
#rhbz 1206036 1215989
ApplyPatch toshiba_acpi-Do-not-register-vendor-backlight-when-a.patch
@@ -1436,6 +1411,12 @@ ApplyPatch toshiba_acpi-Do-not-register-vendor-backlight-when-a.patch
#rhbz 1218662
ApplyPatch libata-Blacklist-queued-TRIM-on-all-Samsung-800-seri.patch
+#rhbz 1219343
+ApplyPatch 0001-HID-usbhid-Add-HID_QUIRK_NOGET-for-Aten-DVI-KVM-swit.patch
+
+#rhbz 1220915
+ApplyPatch ovl-don-t-remove-non-empty-opaque-directory.patch
+
# END OF PATCH APPLICATIONS
%endif
@@ -2295,6 +2276,9 @@ fi
# ||----w |
# || ||
%changelog
+* Thu May 14 2015 Justin M. Forbes <jforbes at fedoraproject.org> - 4.0.3-200
+- Linux v4.0.3
+
* Mon May 11 2015 Laura Abbott <labbott at fedoraproject.org> - 3.19.8-200
- Linux v3.19.8
diff --git a/net-amd-Add-xgbe-a0-driver.patch b/net-amd-Add-xgbe-a0-driver.patch
new file mode 100644
index 0000000..675df12
--- /dev/null
+++ b/net-amd-Add-xgbe-a0-driver.patch
@@ -0,0 +1,10436 @@
+From: Tom Lendacky <thomas.lendacky at amd.com>
+Date: Sat, 21 Feb 2015 12:25:12 -0500
+Subject: [PATCH] net: amd: Add xgbe-a0 driver
+
+Add support for A0 silicon xgbe driver. This won't be upstreamed because
+the HW is being replaced with a better version.
+
+Signed-off-by: Mark Salter <msalter at redhat.com>
+---
+ drivers/net/ethernet/amd/Makefile | 1 +
+ drivers/net/ethernet/amd/xgbe-a0/Makefile | 8 +
+ drivers/net/ethernet/amd/xgbe-a0/xgbe-common.h | 1142 +++++++++
+ drivers/net/ethernet/amd/xgbe-a0/xgbe-dcb.c | 269 ++
+ drivers/net/ethernet/amd/xgbe-a0/xgbe-debugfs.c | 373 +++
+ drivers/net/ethernet/amd/xgbe-a0/xgbe-desc.c | 636 +++++
+ drivers/net/ethernet/amd/xgbe-a0/xgbe-dev.c | 2964 +++++++++++++++++++++++
+ drivers/net/ethernet/amd/xgbe-a0/xgbe-drv.c | 2204 +++++++++++++++++
+ drivers/net/ethernet/amd/xgbe-a0/xgbe-ethtool.c | 616 +++++
+ drivers/net/ethernet/amd/xgbe-a0/xgbe-main.c | 643 +++++
+ drivers/net/ethernet/amd/xgbe-a0/xgbe-mdio.c | 312 +++
+ drivers/net/ethernet/amd/xgbe-a0/xgbe-ptp.c | 284 +++
+ drivers/net/ethernet/amd/xgbe-a0/xgbe.h | 868 +++++++
+ 13 files changed, 10320 insertions(+)
+ create mode 100644 drivers/net/ethernet/amd/xgbe-a0/Makefile
+ create mode 100644 drivers/net/ethernet/amd/xgbe-a0/xgbe-common.h
+ create mode 100644 drivers/net/ethernet/amd/xgbe-a0/xgbe-dcb.c
+ create mode 100644 drivers/net/ethernet/amd/xgbe-a0/xgbe-debugfs.c
+ create mode 100644 drivers/net/ethernet/amd/xgbe-a0/xgbe-desc.c
+ create mode 100644 drivers/net/ethernet/amd/xgbe-a0/xgbe-dev.c
+ create mode 100644 drivers/net/ethernet/amd/xgbe-a0/xgbe-drv.c
+ create mode 100644 drivers/net/ethernet/amd/xgbe-a0/xgbe-ethtool.c
+ create mode 100644 drivers/net/ethernet/amd/xgbe-a0/xgbe-main.c
+ create mode 100644 drivers/net/ethernet/amd/xgbe-a0/xgbe-mdio.c
+ create mode 100644 drivers/net/ethernet/amd/xgbe-a0/xgbe-ptp.c
+ create mode 100644 drivers/net/ethernet/amd/xgbe-a0/xgbe.h
+
+diff --git a/drivers/net/ethernet/amd/Makefile b/drivers/net/ethernet/amd/Makefile
+index a38a2dce3eb3..bf0cf2f8d2db 100644
+--- a/drivers/net/ethernet/amd/Makefile
++++ b/drivers/net/ethernet/amd/Makefile
+@@ -18,3 +18,4 @@ obj-$(CONFIG_PCNET32) += pcnet32.o
+ obj-$(CONFIG_SUN3LANCE) += sun3lance.o
+ obj-$(CONFIG_SUNLANCE) += sunlance.o
+ obj-$(CONFIG_AMD_XGBE) += xgbe/
++obj-$(CONFIG_AMD_XGBE) += xgbe-a0/
+diff --git a/drivers/net/ethernet/amd/xgbe-a0/Makefile b/drivers/net/ethernet/amd/xgbe-a0/Makefile
+new file mode 100644
+index 000000000000..561116faadae
+--- /dev/null
++++ b/drivers/net/ethernet/amd/xgbe-a0/Makefile
+@@ -0,0 +1,8 @@
++obj-$(CONFIG_AMD_XGBE) += amd-xgbe-a0.o
++
++amd-xgbe-a0-objs := xgbe-main.o xgbe-drv.o xgbe-dev.o \
++ xgbe-desc.o xgbe-ethtool.o xgbe-mdio.o \
++ xgbe-ptp.o
++
++amd-xgbe-a0-$(CONFIG_AMD_XGBE_DCB) += xgbe-dcb.o
++amd-xgbe-a0-$(CONFIG_DEBUG_FS) += xgbe-debugfs.o
+diff --git a/drivers/net/ethernet/amd/xgbe-a0/xgbe-common.h b/drivers/net/ethernet/amd/xgbe-a0/xgbe-common.h
+new file mode 100644
+index 000000000000..75b08c63d39f
+--- /dev/null
++++ b/drivers/net/ethernet/amd/xgbe-a0/xgbe-common.h
+@@ -0,0 +1,1142 @@
++/*
++ * AMD 10Gb Ethernet driver
++ *
++ * This file is available to you under your choice of the following two
++ * licenses:
++ *
++ * License 1: GPLv2
++ *
++ * Copyright (c) 2014 Advanced Micro Devices, Inc.
++ *
++ * This file is free software; you may copy, redistribute and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 2 of the License, or (at
++ * your option) any later version.
++ *
++ * This file is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ *
++ * This file incorporates work covered by the following copyright and
++ * permission notice:
++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation
++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
++ * Inc. unless otherwise expressly agreed to in writing between Synopsys
++ * and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product
++ * under any End User Software License Agreement or Agreement for Licensed
++ * Product with Synopsys or any supplement thereto. Permission is hereby
++ * granted, free of charge, to any person obtaining a copy of this software
++ * annotated with this license and the Software, to deal in the Software
++ * without restriction, including without limitation the rights to use,
++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
++ * of the Software, and to permit persons to whom the Software is furnished
++ * to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
++ * THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ *
++ * License 2: Modified BSD
++ *
++ * Copyright (c) 2014 Advanced Micro Devices, Inc.
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * * Neither the name of Advanced Micro Devices, Inc. nor the
++ * names of its contributors may be used to endorse or promote products
++ * derived from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * This file incorporates work covered by the following copyright and
++ * permission notice:
++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation
++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
++ * Inc. unless otherwise expressly agreed to in writing between Synopsys
++ * and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product
++ * under any End User Software License Agreement or Agreement for Licensed
++ * Product with Synopsys or any supplement thereto. Permission is hereby
++ * granted, free of charge, to any person obtaining a copy of this software
++ * annotated with this license and the Software, to deal in the Software
++ * without restriction, including without limitation the rights to use,
++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
++ * of the Software, and to permit persons to whom the Software is furnished
++ * to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
++ * THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef __XGBE_COMMON_H__
++#define __XGBE_COMMON_H__
++
++/* DMA register offsets */
++#define DMA_MR 0x3000
++#define DMA_SBMR 0x3004
++#define DMA_ISR 0x3008
++#define DMA_AXIARCR 0x3010
++#define DMA_AXIAWCR 0x3018
++#define DMA_DSR0 0x3020
++#define DMA_DSR1 0x3024
++
++/* DMA register entry bit positions and sizes */
++#define DMA_AXIARCR_DRC_INDEX 0
++#define DMA_AXIARCR_DRC_WIDTH 4
++#define DMA_AXIARCR_DRD_INDEX 4
++#define DMA_AXIARCR_DRD_WIDTH 2
++#define DMA_AXIARCR_TEC_INDEX 8
++#define DMA_AXIARCR_TEC_WIDTH 4
++#define DMA_AXIARCR_TED_INDEX 12
++#define DMA_AXIARCR_TED_WIDTH 2
++#define DMA_AXIARCR_THC_INDEX 16
++#define DMA_AXIARCR_THC_WIDTH 4
++#define DMA_AXIARCR_THD_INDEX 20
++#define DMA_AXIARCR_THD_WIDTH 2
++#define DMA_AXIAWCR_DWC_INDEX 0
++#define DMA_AXIAWCR_DWC_WIDTH 4
++#define DMA_AXIAWCR_DWD_INDEX 4
++#define DMA_AXIAWCR_DWD_WIDTH 2
++#define DMA_AXIAWCR_RPC_INDEX 8
++#define DMA_AXIAWCR_RPC_WIDTH 4
++#define DMA_AXIAWCR_RPD_INDEX 12
++#define DMA_AXIAWCR_RPD_WIDTH 2
++#define DMA_AXIAWCR_RHC_INDEX 16
++#define DMA_AXIAWCR_RHC_WIDTH 4
++#define DMA_AXIAWCR_RHD_INDEX 20
++#define DMA_AXIAWCR_RHD_WIDTH 2
++#define DMA_AXIAWCR_TDC_INDEX 24
++#define DMA_AXIAWCR_TDC_WIDTH 4
++#define DMA_AXIAWCR_TDD_INDEX 28
++#define DMA_AXIAWCR_TDD_WIDTH 2
++#define DMA_ISR_MACIS_INDEX 17
++#define DMA_ISR_MACIS_WIDTH 1
++#define DMA_ISR_MTLIS_INDEX 16
++#define DMA_ISR_MTLIS_WIDTH 1
++#define DMA_MR_SWR_INDEX 0
++#define DMA_MR_SWR_WIDTH 1
++#define DMA_SBMR_EAME_INDEX 11
++#define DMA_SBMR_EAME_WIDTH 1
++#define DMA_SBMR_BLEN_256_INDEX 7
++#define DMA_SBMR_BLEN_256_WIDTH 1
++#define DMA_SBMR_UNDEF_INDEX 0
++#define DMA_SBMR_UNDEF_WIDTH 1
++
++/* DMA register values */
++#define DMA_DSR_RPS_WIDTH 4
++#define DMA_DSR_TPS_WIDTH 4
++#define DMA_DSR_Q_WIDTH (DMA_DSR_RPS_WIDTH + DMA_DSR_TPS_WIDTH)
++#define DMA_DSR0_RPS_START 8
++#define DMA_DSR0_TPS_START 12
++#define DMA_DSRX_FIRST_QUEUE 3
++#define DMA_DSRX_INC 4
++#define DMA_DSRX_QPR 4
++#define DMA_DSRX_RPS_START 0
++#define DMA_DSRX_TPS_START 4
++#define DMA_TPS_STOPPED 0x00
++#define DMA_TPS_SUSPENDED 0x06
++
++/* DMA channel register offsets
++ * Multiple channels can be active. The first channel has registers
++ * that begin at 0x3100. Each subsequent channel has registers that
++ * are accessed using an offset of 0x80 from the previous channel.
++ */
++#define DMA_CH_BASE 0x3100
++#define DMA_CH_INC 0x80
++
++#define DMA_CH_CR 0x00
++#define DMA_CH_TCR 0x04
++#define DMA_CH_RCR 0x08
++#define DMA_CH_TDLR_HI 0x10
++#define DMA_CH_TDLR_LO 0x14
++#define DMA_CH_RDLR_HI 0x18
++#define DMA_CH_RDLR_LO 0x1c
++#define DMA_CH_TDTR_LO 0x24
++#define DMA_CH_RDTR_LO 0x2c
++#define DMA_CH_TDRLR 0x30
++#define DMA_CH_RDRLR 0x34
++#define DMA_CH_IER 0x38
++#define DMA_CH_RIWT 0x3c
++#define DMA_CH_CATDR_LO 0x44
++#define DMA_CH_CARDR_LO 0x4c
++#define DMA_CH_CATBR_HI 0x50
++#define DMA_CH_CATBR_LO 0x54
++#define DMA_CH_CARBR_HI 0x58
++#define DMA_CH_CARBR_LO 0x5c
++#define DMA_CH_SR 0x60
++
++/* DMA channel register entry bit positions and sizes */
++#define DMA_CH_CR_PBLX8_INDEX 16
++#define DMA_CH_CR_PBLX8_WIDTH 1
++#define DMA_CH_CR_SPH_INDEX 24
++#define DMA_CH_CR_SPH_WIDTH 1
++#define DMA_CH_IER_AIE_INDEX 15
++#define DMA_CH_IER_AIE_WIDTH 1
++#define DMA_CH_IER_FBEE_INDEX 12
++#define DMA_CH_IER_FBEE_WIDTH 1
++#define DMA_CH_IER_NIE_INDEX 16
++#define DMA_CH_IER_NIE_WIDTH 1
++#define DMA_CH_IER_RBUE_INDEX 7
++#define DMA_CH_IER_RBUE_WIDTH 1
++#define DMA_CH_IER_RIE_INDEX 6
++#define DMA_CH_IER_RIE_WIDTH 1
++#define DMA_CH_IER_RSE_INDEX 8
++#define DMA_CH_IER_RSE_WIDTH 1
++#define DMA_CH_IER_TBUE_INDEX 2
++#define DMA_CH_IER_TBUE_WIDTH 1
++#define DMA_CH_IER_TIE_INDEX 0
++#define DMA_CH_IER_TIE_WIDTH 1
++#define DMA_CH_IER_TXSE_INDEX 1
++#define DMA_CH_IER_TXSE_WIDTH 1
++#define DMA_CH_RCR_PBL_INDEX 16
++#define DMA_CH_RCR_PBL_WIDTH 6
++#define DMA_CH_RCR_RBSZ_INDEX 1
++#define DMA_CH_RCR_RBSZ_WIDTH 14
++#define DMA_CH_RCR_SR_INDEX 0
++#define DMA_CH_RCR_SR_WIDTH 1
++#define DMA_CH_RIWT_RWT_INDEX 0
++#define DMA_CH_RIWT_RWT_WIDTH 8
++#define DMA_CH_SR_FBE_INDEX 12
++#define DMA_CH_SR_FBE_WIDTH 1
++#define DMA_CH_SR_RBU_INDEX 7
++#define DMA_CH_SR_RBU_WIDTH 1
++#define DMA_CH_SR_RI_INDEX 6
++#define DMA_CH_SR_RI_WIDTH 1
++#define DMA_CH_SR_RPS_INDEX 8
++#define DMA_CH_SR_RPS_WIDTH 1
++#define DMA_CH_SR_TBU_INDEX 2
++#define DMA_CH_SR_TBU_WIDTH 1
++#define DMA_CH_SR_TI_INDEX 0
++#define DMA_CH_SR_TI_WIDTH 1
++#define DMA_CH_SR_TPS_INDEX 1
++#define DMA_CH_SR_TPS_WIDTH 1
++#define DMA_CH_TCR_OSP_INDEX 4
++#define DMA_CH_TCR_OSP_WIDTH 1
++#define DMA_CH_TCR_PBL_INDEX 16
++#define DMA_CH_TCR_PBL_WIDTH 6
++#define DMA_CH_TCR_ST_INDEX 0
++#define DMA_CH_TCR_ST_WIDTH 1
++#define DMA_CH_TCR_TSE_INDEX 12
++#define DMA_CH_TCR_TSE_WIDTH 1
++
++/* DMA channel register values */
++#define DMA_OSP_DISABLE 0x00
++#define DMA_OSP_ENABLE 0x01
++#define DMA_PBL_1 1
++#define DMA_PBL_2 2
++#define DMA_PBL_4 4
++#define DMA_PBL_8 8
++#define DMA_PBL_16 16
++#define DMA_PBL_32 32
++#define DMA_PBL_64 64 /* 8 x 8 */
++#define DMA_PBL_128 128 /* 8 x 16 */
++#define DMA_PBL_256 256 /* 8 x 32 */
++#define DMA_PBL_X8_DISABLE 0x00
++#define DMA_PBL_X8_ENABLE 0x01
++
++/* MAC register offsets */
++#define MAC_TCR 0x0000
++#define MAC_RCR 0x0004
++#define MAC_PFR 0x0008
++#define MAC_WTR 0x000c
++#define MAC_HTR0 0x0010
++#define MAC_VLANTR 0x0050
++#define MAC_VLANHTR 0x0058
++#define MAC_VLANIR 0x0060
++#define MAC_IVLANIR 0x0064
++#define MAC_RETMR 0x006c
++#define MAC_Q0TFCR 0x0070
++#define MAC_RFCR 0x0090
++#define MAC_RQC0R 0x00a0
++#define MAC_RQC1R 0x00a4
++#define MAC_RQC2R 0x00a8
++#define MAC_RQC3R 0x00ac
++#define MAC_ISR 0x00b0
++#define MAC_IER 0x00b4
++#define MAC_RTSR 0x00b8
++#define MAC_PMTCSR 0x00c0
++#define MAC_RWKPFR 0x00c4
++#define MAC_LPICSR 0x00d0
++#define MAC_LPITCR 0x00d4
++#define MAC_VR 0x0110
++#define MAC_DR 0x0114
++#define MAC_HWF0R 0x011c
++#define MAC_HWF1R 0x0120
++#define MAC_HWF2R 0x0124
++#define MAC_GPIOCR 0x0278
++#define MAC_GPIOSR 0x027c
++#define MAC_MACA0HR 0x0300
++#define MAC_MACA0LR 0x0304
++#define MAC_MACA1HR 0x0308
++#define MAC_MACA1LR 0x030c
++#define MAC_RSSCR 0x0c80
++#define MAC_RSSAR 0x0c88
++#define MAC_RSSDR 0x0c8c
++#define MAC_TSCR 0x0d00
++#define MAC_SSIR 0x0d04
++#define MAC_STSR 0x0d08
++#define MAC_STNR 0x0d0c
++#define MAC_STSUR 0x0d10
++#define MAC_STNUR 0x0d14
++#define MAC_TSAR 0x0d18
++#define MAC_TSSR 0x0d20
++#define MAC_TXSNR 0x0d30
++#define MAC_TXSSR 0x0d34
++
++#define MAC_QTFCR_INC 4
++#define MAC_MACA_INC 4
++#define MAC_HTR_INC 4
++
++#define MAC_RQC2_INC 4
++#define MAC_RQC2_Q_PER_REG 4
++
++/* MAC register entry bit positions and sizes */
++#define MAC_HWF0R_ADDMACADRSEL_INDEX 18
++#define MAC_HWF0R_ADDMACADRSEL_WIDTH 5
++#define MAC_HWF0R_ARPOFFSEL_INDEX 9
++#define MAC_HWF0R_ARPOFFSEL_WIDTH 1
++#define MAC_HWF0R_EEESEL_INDEX 13
++#define MAC_HWF0R_EEESEL_WIDTH 1
++#define MAC_HWF0R_GMIISEL_INDEX 1
++#define MAC_HWF0R_GMIISEL_WIDTH 1
++#define MAC_HWF0R_MGKSEL_INDEX 7
++#define MAC_HWF0R_MGKSEL_WIDTH 1
++#define MAC_HWF0R_MMCSEL_INDEX 8
++#define MAC_HWF0R_MMCSEL_WIDTH 1
++#define MAC_HWF0R_RWKSEL_INDEX 6
++#define MAC_HWF0R_RWKSEL_WIDTH 1
++#define MAC_HWF0R_RXCOESEL_INDEX 16
++#define MAC_HWF0R_RXCOESEL_WIDTH 1
++#define MAC_HWF0R_SAVLANINS_INDEX 27
++#define MAC_HWF0R_SAVLANINS_WIDTH 1
++#define MAC_HWF0R_SMASEL_INDEX 5
++#define MAC_HWF0R_SMASEL_WIDTH 1
++#define MAC_HWF0R_TSSEL_INDEX 12
++#define MAC_HWF0R_TSSEL_WIDTH 1
++#define MAC_HWF0R_TSSTSSEL_INDEX 25
++#define MAC_HWF0R_TSSTSSEL_WIDTH 2
++#define MAC_HWF0R_TXCOESEL_INDEX 14
++#define MAC_HWF0R_TXCOESEL_WIDTH 1
++#define MAC_HWF0R_VLHASH_INDEX 4
++#define MAC_HWF0R_VLHASH_WIDTH 1
++#define MAC_HWF1R_ADVTHWORD_INDEX 13
++#define MAC_HWF1R_ADVTHWORD_WIDTH 1
++#define MAC_HWF1R_DBGMEMA_INDEX 19
++#define MAC_HWF1R_DBGMEMA_WIDTH 1
++#define MAC_HWF1R_DCBEN_INDEX 16
++#define MAC_HWF1R_DCBEN_WIDTH 1
++#define MAC_HWF1R_HASHTBLSZ_INDEX 24
++#define MAC_HWF1R_HASHTBLSZ_WIDTH 3
++#define MAC_HWF1R_L3L4FNUM_INDEX 27
++#define MAC_HWF1R_L3L4FNUM_WIDTH 4
++#define MAC_HWF1R_NUMTC_INDEX 21
++#define MAC_HWF1R_NUMTC_WIDTH 3
++#define MAC_HWF1R_RSSEN_INDEX 20
++#define MAC_HWF1R_RSSEN_WIDTH 1
++#define MAC_HWF1R_RXFIFOSIZE_INDEX 0
++#define MAC_HWF1R_RXFIFOSIZE_WIDTH 5
++#define MAC_HWF1R_SPHEN_INDEX 17
++#define MAC_HWF1R_SPHEN_WIDTH 1
++#define MAC_HWF1R_TSOEN_INDEX 18
++#define MAC_HWF1R_TSOEN_WIDTH 1
++#define MAC_HWF1R_TXFIFOSIZE_INDEX 6
++#define MAC_HWF1R_TXFIFOSIZE_WIDTH 5
++#define MAC_HWF2R_AUXSNAPNUM_INDEX 28
++#define MAC_HWF2R_AUXSNAPNUM_WIDTH 3
++#define MAC_HWF2R_PPSOUTNUM_INDEX 24
++#define MAC_HWF2R_PPSOUTNUM_WIDTH 3
++#define MAC_HWF2R_RXCHCNT_INDEX 12
++#define MAC_HWF2R_RXCHCNT_WIDTH 4
++#define MAC_HWF2R_RXQCNT_INDEX 0
++#define MAC_HWF2R_RXQCNT_WIDTH 4
++#define MAC_HWF2R_TXCHCNT_INDEX 18
++#define MAC_HWF2R_TXCHCNT_WIDTH 4
++#define MAC_HWF2R_TXQCNT_INDEX 6
++#define MAC_HWF2R_TXQCNT_WIDTH 4
++#define MAC_IER_TSIE_INDEX 12
++#define MAC_IER_TSIE_WIDTH 1
++#define MAC_ISR_MMCRXIS_INDEX 9
++#define MAC_ISR_MMCRXIS_WIDTH 1
++#define MAC_ISR_MMCTXIS_INDEX 10
++#define MAC_ISR_MMCTXIS_WIDTH 1
++#define MAC_ISR_PMTIS_INDEX 4
++#define MAC_ISR_PMTIS_WIDTH 1
++#define MAC_ISR_TSIS_INDEX 12
++#define MAC_ISR_TSIS_WIDTH 1
++#define MAC_MACA1HR_AE_INDEX 31
++#define MAC_MACA1HR_AE_WIDTH 1
++#define MAC_PFR_HMC_INDEX 2
++#define MAC_PFR_HMC_WIDTH 1
++#define MAC_PFR_HPF_INDEX 10
++#define MAC_PFR_HPF_WIDTH 1
++#define MAC_PFR_HUC_INDEX 1
++#define MAC_PFR_HUC_WIDTH 1
++#define MAC_PFR_PM_INDEX 4
++#define MAC_PFR_PM_WIDTH 1
++#define MAC_PFR_PR_INDEX 0
++#define MAC_PFR_PR_WIDTH 1
++#define MAC_PFR_VTFE_INDEX 16
++#define MAC_PFR_VTFE_WIDTH 1
++#define MAC_PMTCSR_MGKPKTEN_INDEX 1
++#define MAC_PMTCSR_MGKPKTEN_WIDTH 1
++#define MAC_PMTCSR_PWRDWN_INDEX 0
++#define MAC_PMTCSR_PWRDWN_WIDTH 1
++#define MAC_PMTCSR_RWKFILTRST_INDEX 31
++#define MAC_PMTCSR_RWKFILTRST_WIDTH 1
++#define MAC_PMTCSR_RWKPKTEN_INDEX 2
++#define MAC_PMTCSR_RWKPKTEN_WIDTH 1
++#define MAC_Q0TFCR_PT_INDEX 16
++#define MAC_Q0TFCR_PT_WIDTH 16
++#define MAC_Q0TFCR_TFE_INDEX 1
++#define MAC_Q0TFCR_TFE_WIDTH 1
++#define MAC_RCR_ACS_INDEX 1
++#define MAC_RCR_ACS_WIDTH 1
++#define MAC_RCR_CST_INDEX 2
++#define MAC_RCR_CST_WIDTH 1
++#define MAC_RCR_DCRCC_INDEX 3
++#define MAC_RCR_DCRCC_WIDTH 1
++#define MAC_RCR_HDSMS_INDEX 12
++#define MAC_RCR_HDSMS_WIDTH 3
++#define MAC_RCR_IPC_INDEX 9
++#define MAC_RCR_IPC_WIDTH 1
++#define MAC_RCR_JE_INDEX 8
++#define MAC_RCR_JE_WIDTH 1
++#define MAC_RCR_LM_INDEX 10
++#define MAC_RCR_LM_WIDTH 1
++#define MAC_RCR_RE_INDEX 0
++#define MAC_RCR_RE_WIDTH 1
++#define MAC_RFCR_PFCE_INDEX 8
++#define MAC_RFCR_PFCE_WIDTH 1
++#define MAC_RFCR_RFE_INDEX 0
++#define MAC_RFCR_RFE_WIDTH 1
++#define MAC_RFCR_UP_INDEX 1
++#define MAC_RFCR_UP_WIDTH 1
++#define MAC_RQC0R_RXQ0EN_INDEX 0
++#define MAC_RQC0R_RXQ0EN_WIDTH 2
++#define MAC_RSSAR_ADDRT_INDEX 2
++#define MAC_RSSAR_ADDRT_WIDTH 1
++#define MAC_RSSAR_CT_INDEX 1
++#define MAC_RSSAR_CT_WIDTH 1
++#define MAC_RSSAR_OB_INDEX 0
++#define MAC_RSSAR_OB_WIDTH 1
++#define MAC_RSSAR_RSSIA_INDEX 8
++#define MAC_RSSAR_RSSIA_WIDTH 8
++#define MAC_RSSCR_IP2TE_INDEX 1
++#define MAC_RSSCR_IP2TE_WIDTH 1
++#define MAC_RSSCR_RSSE_INDEX 0
++#define MAC_RSSCR_RSSE_WIDTH 1
++#define MAC_RSSCR_TCP4TE_INDEX 2
++#define MAC_RSSCR_TCP4TE_WIDTH 1
++#define MAC_RSSCR_UDP4TE_INDEX 3
++#define MAC_RSSCR_UDP4TE_WIDTH 1
++#define MAC_RSSDR_DMCH_INDEX 0
++#define MAC_RSSDR_DMCH_WIDTH 4
++#define MAC_SSIR_SNSINC_INDEX 8
++#define MAC_SSIR_SNSINC_WIDTH 8
++#define MAC_SSIR_SSINC_INDEX 16
++#define MAC_SSIR_SSINC_WIDTH 8
++#define MAC_TCR_SS_INDEX 29
++#define MAC_TCR_SS_WIDTH 2
++#define MAC_TCR_TE_INDEX 0
++#define MAC_TCR_TE_WIDTH 1
++#define MAC_TSCR_AV8021ASMEN_INDEX 28
++#define MAC_TSCR_AV8021ASMEN_WIDTH 1
++#define MAC_TSCR_SNAPTYPSEL_INDEX 16
++#define MAC_TSCR_SNAPTYPSEL_WIDTH 2
++#define MAC_TSCR_TSADDREG_INDEX 5
++#define MAC_TSCR_TSADDREG_WIDTH 1
++#define MAC_TSCR_TSCFUPDT_INDEX 1
++#define MAC_TSCR_TSCFUPDT_WIDTH 1
++#define MAC_TSCR_TSCTRLSSR_INDEX 9
++#define MAC_TSCR_TSCTRLSSR_WIDTH 1
++#define MAC_TSCR_TSENA_INDEX 0
++#define MAC_TSCR_TSENA_WIDTH 1
++#define MAC_TSCR_TSENALL_INDEX 8
++#define MAC_TSCR_TSENALL_WIDTH 1
++#define MAC_TSCR_TSEVNTENA_INDEX 14
++#define MAC_TSCR_TSEVNTENA_WIDTH 1
++#define MAC_TSCR_TSINIT_INDEX 2
++#define MAC_TSCR_TSINIT_WIDTH 1
++#define MAC_TSCR_TSIPENA_INDEX 11
++#define MAC_TSCR_TSIPENA_WIDTH 1
++#define MAC_TSCR_TSIPV4ENA_INDEX 13
++#define MAC_TSCR_TSIPV4ENA_WIDTH 1
++#define MAC_TSCR_TSIPV6ENA_INDEX 12
++#define MAC_TSCR_TSIPV6ENA_WIDTH 1
++#define MAC_TSCR_TSMSTRENA_INDEX 15
++#define MAC_TSCR_TSMSTRENA_WIDTH 1
++#define MAC_TSCR_TSVER2ENA_INDEX 10
++#define MAC_TSCR_TSVER2ENA_WIDTH 1
++#define MAC_TSCR_TXTSSTSM_INDEX 24
++#define MAC_TSCR_TXTSSTSM_WIDTH 1
++#define MAC_TSSR_TXTSC_INDEX 15
++#define MAC_TSSR_TXTSC_WIDTH 1
++#define MAC_TXSNR_TXTSSTSMIS_INDEX 31
++#define MAC_TXSNR_TXTSSTSMIS_WIDTH 1
++#define MAC_VLANHTR_VLHT_INDEX 0
++#define MAC_VLANHTR_VLHT_WIDTH 16
++#define MAC_VLANIR_VLTI_INDEX 20
++#define MAC_VLANIR_VLTI_WIDTH 1
++#define MAC_VLANIR_CSVL_INDEX 19
++#define MAC_VLANIR_CSVL_WIDTH 1
++#define MAC_VLANTR_DOVLTC_INDEX 20
++#define MAC_VLANTR_DOVLTC_WIDTH 1
++#define MAC_VLANTR_ERSVLM_INDEX 19
++#define MAC_VLANTR_ERSVLM_WIDTH 1
++#define MAC_VLANTR_ESVL_INDEX 18
++#define MAC_VLANTR_ESVL_WIDTH 1
++#define MAC_VLANTR_ETV_INDEX 16
++#define MAC_VLANTR_ETV_WIDTH 1
++#define MAC_VLANTR_EVLS_INDEX 21
++#define MAC_VLANTR_EVLS_WIDTH 2
++#define MAC_VLANTR_EVLRXS_INDEX 24
++#define MAC_VLANTR_EVLRXS_WIDTH 1
++#define MAC_VLANTR_VL_INDEX 0
++#define MAC_VLANTR_VL_WIDTH 16
++#define MAC_VLANTR_VTHM_INDEX 25
++#define MAC_VLANTR_VTHM_WIDTH 1
++#define MAC_VLANTR_VTIM_INDEX 17
++#define MAC_VLANTR_VTIM_WIDTH 1
++#define MAC_VR_DEVID_INDEX 8
++#define MAC_VR_DEVID_WIDTH 8
++#define MAC_VR_SNPSVER_INDEX 0
++#define MAC_VR_SNPSVER_WIDTH 8
++#define MAC_VR_USERVER_INDEX 16
++#define MAC_VR_USERVER_WIDTH 8
++
++/* MMC register offsets */
++#define MMC_CR 0x0800
++#define MMC_RISR 0x0804
++#define MMC_TISR 0x0808
++#define MMC_RIER 0x080c
++#define MMC_TIER 0x0810
++#define MMC_TXOCTETCOUNT_GB_LO 0x0814
++#define MMC_TXOCTETCOUNT_GB_HI 0x0818
++#define MMC_TXFRAMECOUNT_GB_LO 0x081c
++#define MMC_TXFRAMECOUNT_GB_HI 0x0820
++#define MMC_TXBROADCASTFRAMES_G_LO 0x0824
++#define MMC_TXBROADCASTFRAMES_G_HI 0x0828
++#define MMC_TXMULTICASTFRAMES_G_LO 0x082c
++#define MMC_TXMULTICASTFRAMES_G_HI 0x0830
++#define MMC_TX64OCTETS_GB_LO 0x0834
++#define MMC_TX64OCTETS_GB_HI 0x0838
++#define MMC_TX65TO127OCTETS_GB_LO 0x083c
++#define MMC_TX65TO127OCTETS_GB_HI 0x0840
++#define MMC_TX128TO255OCTETS_GB_LO 0x0844
++#define MMC_TX128TO255OCTETS_GB_HI 0x0848
++#define MMC_TX256TO511OCTETS_GB_LO 0x084c
++#define MMC_TX256TO511OCTETS_GB_HI 0x0850
++#define MMC_TX512TO1023OCTETS_GB_LO 0x0854
++#define MMC_TX512TO1023OCTETS_GB_HI 0x0858
++#define MMC_TX1024TOMAXOCTETS_GB_LO 0x085c
++#define MMC_TX1024TOMAXOCTETS_GB_HI 0x0860
++#define MMC_TXUNICASTFRAMES_GB_LO 0x0864
++#define MMC_TXUNICASTFRAMES_GB_HI 0x0868
++#define MMC_TXMULTICASTFRAMES_GB_LO 0x086c
++#define MMC_TXMULTICASTFRAMES_GB_HI 0x0870
++#define MMC_TXBROADCASTFRAMES_GB_LO 0x0874
++#define MMC_TXBROADCASTFRAMES_GB_HI 0x0878
++#define MMC_TXUNDERFLOWERROR_LO 0x087c
++#define MMC_TXUNDERFLOWERROR_HI 0x0880
++#define MMC_TXOCTETCOUNT_G_LO 0x0884
++#define MMC_TXOCTETCOUNT_G_HI 0x0888
++#define MMC_TXFRAMECOUNT_G_LO 0x088c
++#define MMC_TXFRAMECOUNT_G_HI 0x0890
++#define MMC_TXPAUSEFRAMES_LO 0x0894
++#define MMC_TXPAUSEFRAMES_HI 0x0898
++#define MMC_TXVLANFRAMES_G_LO 0x089c
++#define MMC_TXVLANFRAMES_G_HI 0x08a0
++#define MMC_RXFRAMECOUNT_GB_LO 0x0900
++#define MMC_RXFRAMECOUNT_GB_HI 0x0904
++#define MMC_RXOCTETCOUNT_GB_LO 0x0908
++#define MMC_RXOCTETCOUNT_GB_HI 0x090c
++#define MMC_RXOCTETCOUNT_G_LO 0x0910
++#define MMC_RXOCTETCOUNT_G_HI 0x0914
++#define MMC_RXBROADCASTFRAMES_G_LO 0x0918
++#define MMC_RXBROADCASTFRAMES_G_HI 0x091c
++#define MMC_RXMULTICASTFRAMES_G_LO 0x0920
++#define MMC_RXMULTICASTFRAMES_G_HI 0x0924
++#define MMC_RXCRCERROR_LO 0x0928
++#define MMC_RXCRCERROR_HI 0x092c
++#define MMC_RXRUNTERROR 0x0930
++#define MMC_RXJABBERERROR 0x0934
++#define MMC_RXUNDERSIZE_G 0x0938
++#define MMC_RXOVERSIZE_G 0x093c
++#define MMC_RX64OCTETS_GB_LO 0x0940
++#define MMC_RX64OCTETS_GB_HI 0x0944
++#define MMC_RX65TO127OCTETS_GB_LO 0x0948
++#define MMC_RX65TO127OCTETS_GB_HI 0x094c
++#define MMC_RX128TO255OCTETS_GB_LO 0x0950
++#define MMC_RX128TO255OCTETS_GB_HI 0x0954
++#define MMC_RX256TO511OCTETS_GB_LO 0x0958
++#define MMC_RX256TO511OCTETS_GB_HI 0x095c
++#define MMC_RX512TO1023OCTETS_GB_LO 0x0960
++#define MMC_RX512TO1023OCTETS_GB_HI 0x0964
++#define MMC_RX1024TOMAXOCTETS_GB_LO 0x0968
++#define MMC_RX1024TOMAXOCTETS_GB_HI 0x096c
++#define MMC_RXUNICASTFRAMES_G_LO 0x0970
++#define MMC_RXUNICASTFRAMES_G_HI 0x0974
++#define MMC_RXLENGTHERROR_LO 0x0978
++#define MMC_RXLENGTHERROR_HI 0x097c
++#define MMC_RXOUTOFRANGETYPE_LO 0x0980
++#define MMC_RXOUTOFRANGETYPE_HI 0x0984
++#define MMC_RXPAUSEFRAMES_LO 0x0988
++#define MMC_RXPAUSEFRAMES_HI 0x098c
++#define MMC_RXFIFOOVERFLOW_LO 0x0990
++#define MMC_RXFIFOOVERFLOW_HI 0x0994
++#define MMC_RXVLANFRAMES_GB_LO 0x0998
++#define MMC_RXVLANFRAMES_GB_HI 0x099c
++#define MMC_RXWATCHDOGERROR 0x09a0
++
++/* MMC register entry bit positions and sizes */
++#define MMC_CR_CR_INDEX 0
++#define MMC_CR_CR_WIDTH 1
++#define MMC_CR_CSR_INDEX 1
++#define MMC_CR_CSR_WIDTH 1
++#define MMC_CR_ROR_INDEX 2
++#define MMC_CR_ROR_WIDTH 1
++#define MMC_CR_MCF_INDEX 3
++#define MMC_CR_MCF_WIDTH 1
++#define MMC_CR_MCT_INDEX 4
++#define MMC_CR_MCT_WIDTH 2
++#define MMC_RIER_ALL_INTERRUPTS_INDEX 0
++#define MMC_RIER_ALL_INTERRUPTS_WIDTH 23
++#define MMC_RISR_RXFRAMECOUNT_GB_INDEX 0
++#define MMC_RISR_RXFRAMECOUNT_GB_WIDTH 1
++#define MMC_RISR_RXOCTETCOUNT_GB_INDEX 1
++#define MMC_RISR_RXOCTETCOUNT_GB_WIDTH 1
++#define MMC_RISR_RXOCTETCOUNT_G_INDEX 2
++#define MMC_RISR_RXOCTETCOUNT_G_WIDTH 1
++#define MMC_RISR_RXBROADCASTFRAMES_G_INDEX 3
++#define MMC_RISR_RXBROADCASTFRAMES_G_WIDTH 1
++#define MMC_RISR_RXMULTICASTFRAMES_G_INDEX 4
++#define MMC_RISR_RXMULTICASTFRAMES_G_WIDTH 1
++#define MMC_RISR_RXCRCERROR_INDEX 5
++#define MMC_RISR_RXCRCERROR_WIDTH 1
++#define MMC_RISR_RXRUNTERROR_INDEX 6
++#define MMC_RISR_RXRUNTERROR_WIDTH 1
++#define MMC_RISR_RXJABBERERROR_INDEX 7
++#define MMC_RISR_RXJABBERERROR_WIDTH 1
++#define MMC_RISR_RXUNDERSIZE_G_INDEX 8
++#define MMC_RISR_RXUNDERSIZE_G_WIDTH 1
++#define MMC_RISR_RXOVERSIZE_G_INDEX 9
++#define MMC_RISR_RXOVERSIZE_G_WIDTH 1
++#define MMC_RISR_RX64OCTETS_GB_INDEX 10
++#define MMC_RISR_RX64OCTETS_GB_WIDTH 1
++#define MMC_RISR_RX65TO127OCTETS_GB_INDEX 11
++#define MMC_RISR_RX65TO127OCTETS_GB_WIDTH 1
++#define MMC_RISR_RX128TO255OCTETS_GB_INDEX 12
++#define MMC_RISR_RX128TO255OCTETS_GB_WIDTH 1
++#define MMC_RISR_RX256TO511OCTETS_GB_INDEX 13
++#define MMC_RISR_RX256TO511OCTETS_GB_WIDTH 1
++#define MMC_RISR_RX512TO1023OCTETS_GB_INDEX 14
++#define MMC_RISR_RX512TO1023OCTETS_GB_WIDTH 1
++#define MMC_RISR_RX1024TOMAXOCTETS_GB_INDEX 15
++#define MMC_RISR_RX1024TOMAXOCTETS_GB_WIDTH 1
++#define MMC_RISR_RXUNICASTFRAMES_G_INDEX 16
++#define MMC_RISR_RXUNICASTFRAMES_G_WIDTH 1
++#define MMC_RISR_RXLENGTHERROR_INDEX 17
++#define MMC_RISR_RXLENGTHERROR_WIDTH 1
++#define MMC_RISR_RXOUTOFRANGETYPE_INDEX 18
++#define MMC_RISR_RXOUTOFRANGETYPE_WIDTH 1
++#define MMC_RISR_RXPAUSEFRAMES_INDEX 19
++#define MMC_RISR_RXPAUSEFRAMES_WIDTH 1
++#define MMC_RISR_RXFIFOOVERFLOW_INDEX 20
++#define MMC_RISR_RXFIFOOVERFLOW_WIDTH 1
++#define MMC_RISR_RXVLANFRAMES_GB_INDEX 21
++#define MMC_RISR_RXVLANFRAMES_GB_WIDTH 1
++#define MMC_RISR_RXWATCHDOGERROR_INDEX 22
++#define MMC_RISR_RXWATCHDOGERROR_WIDTH 1
++#define MMC_TIER_ALL_INTERRUPTS_INDEX 0
++#define MMC_TIER_ALL_INTERRUPTS_WIDTH 18
++#define MMC_TISR_TXOCTETCOUNT_GB_INDEX 0
++#define MMC_TISR_TXOCTETCOUNT_GB_WIDTH 1
++#define MMC_TISR_TXFRAMECOUNT_GB_INDEX 1
++#define MMC_TISR_TXFRAMECOUNT_GB_WIDTH 1
++#define MMC_TISR_TXBROADCASTFRAMES_G_INDEX 2
++#define MMC_TISR_TXBROADCASTFRAMES_G_WIDTH 1
++#define MMC_TISR_TXMULTICASTFRAMES_G_INDEX 3
++#define MMC_TISR_TXMULTICASTFRAMES_G_WIDTH 1
++#define MMC_TISR_TX64OCTETS_GB_INDEX 4
++#define MMC_TISR_TX64OCTETS_GB_WIDTH 1
++#define MMC_TISR_TX65TO127OCTETS_GB_INDEX 5
++#define MMC_TISR_TX65TO127OCTETS_GB_WIDTH 1
++#define MMC_TISR_TX128TO255OCTETS_GB_INDEX 6
++#define MMC_TISR_TX128TO255OCTETS_GB_WIDTH 1
++#define MMC_TISR_TX256TO511OCTETS_GB_INDEX 7
++#define MMC_TISR_TX256TO511OCTETS_GB_WIDTH 1
++#define MMC_TISR_TX512TO1023OCTETS_GB_INDEX 8
++#define MMC_TISR_TX512TO1023OCTETS_GB_WIDTH 1
++#define MMC_TISR_TX1024TOMAXOCTETS_GB_INDEX 9
++#define MMC_TISR_TX1024TOMAXOCTETS_GB_WIDTH 1
++#define MMC_TISR_TXUNICASTFRAMES_GB_INDEX 10
++#define MMC_TISR_TXUNICASTFRAMES_GB_WIDTH 1
++#define MMC_TISR_TXMULTICASTFRAMES_GB_INDEX 11
++#define MMC_TISR_TXMULTICASTFRAMES_GB_WIDTH 1
++#define MMC_TISR_TXBROADCASTFRAMES_GB_INDEX 12
++#define MMC_TISR_TXBROADCASTFRAMES_GB_WIDTH 1
++#define MMC_TISR_TXUNDERFLOWERROR_INDEX 13
++#define MMC_TISR_TXUNDERFLOWERROR_WIDTH 1
++#define MMC_TISR_TXOCTETCOUNT_G_INDEX 14
++#define MMC_TISR_TXOCTETCOUNT_G_WIDTH 1
++#define MMC_TISR_TXFRAMECOUNT_G_INDEX 15
++#define MMC_TISR_TXFRAMECOUNT_G_WIDTH 1
++#define MMC_TISR_TXPAUSEFRAMES_INDEX 16
++#define MMC_TISR_TXPAUSEFRAMES_WIDTH 1
++#define MMC_TISR_TXVLANFRAMES_G_INDEX 17
++#define MMC_TISR_TXVLANFRAMES_G_WIDTH 1
++
++/* MTL register offsets */
++#define MTL_OMR 0x1000
++#define MTL_FDCR 0x1008
++#define MTL_FDSR 0x100c
++#define MTL_FDDR 0x1010
++#define MTL_ISR 0x1020
++#define MTL_RQDCM0R 0x1030
++#define MTL_TCPM0R 0x1040
++#define MTL_TCPM1R 0x1044
++
++#define MTL_RQDCM_INC 4
++#define MTL_RQDCM_Q_PER_REG 4
++#define MTL_TCPM_INC 4
++#define MTL_TCPM_TC_PER_REG 4
++
++/* MTL register entry bit positions and sizes */
++#define MTL_OMR_ETSALG_INDEX 5
++#define MTL_OMR_ETSALG_WIDTH 2
++#define MTL_OMR_RAA_INDEX 2
++#define MTL_OMR_RAA_WIDTH 1
++
++/* MTL queue register offsets
++ * Multiple queues can be active. The first queue has registers
++ * that begin at 0x1100. Each subsequent queue has registers that
++ * are accessed using an offset of 0x80 from the previous queue.
++ */
++#define MTL_Q_BASE 0x1100
++#define MTL_Q_INC 0x80
++
++#define MTL_Q_TQOMR 0x00
++#define MTL_Q_TQUR 0x04
++#define MTL_Q_TQDR 0x08
++#define MTL_Q_RQOMR 0x40
++#define MTL_Q_RQMPOCR 0x44
++#define MTL_Q_RQDR 0x4c
++#define MTL_Q_IER 0x70
++#define MTL_Q_ISR 0x74
++
++/* MTL queue register entry bit positions and sizes */
++#define MTL_Q_RQOMR_EHFC_INDEX 7
++#define MTL_Q_RQOMR_EHFC_WIDTH 1
++#define MTL_Q_RQOMR_RFA_INDEX 8
++#define MTL_Q_RQOMR_RFA_WIDTH 3
++#define MTL_Q_RQOMR_RFD_INDEX 13
++#define MTL_Q_RQOMR_RFD_WIDTH 3
++#define MTL_Q_RQOMR_RQS_INDEX 16
++#define MTL_Q_RQOMR_RQS_WIDTH 9
++#define MTL_Q_RQOMR_RSF_INDEX 5
++#define MTL_Q_RQOMR_RSF_WIDTH 1
++#define MTL_Q_RQOMR_RTC_INDEX 0
++#define MTL_Q_RQOMR_RTC_WIDTH 2
++#define MTL_Q_TQOMR_FTQ_INDEX 0
++#define MTL_Q_TQOMR_FTQ_WIDTH 1
++#define MTL_Q_TQOMR_Q2TCMAP_INDEX 8
++#define MTL_Q_TQOMR_Q2TCMAP_WIDTH 3
++#define MTL_Q_TQOMR_TQS_INDEX 16
++#define MTL_Q_TQOMR_TQS_WIDTH 10
++#define MTL_Q_TQOMR_TSF_INDEX 1
++#define MTL_Q_TQOMR_TSF_WIDTH 1
++#define MTL_Q_TQOMR_TTC_INDEX 4
++#define MTL_Q_TQOMR_TTC_WIDTH 3
++#define MTL_Q_TQOMR_TXQEN_INDEX 2
++#define MTL_Q_TQOMR_TXQEN_WIDTH 2
++
++/* MTL queue register value */
++#define MTL_RSF_DISABLE 0x00
++#define MTL_RSF_ENABLE 0x01
++#define MTL_TSF_DISABLE 0x00
++#define MTL_TSF_ENABLE 0x01
++
++#define MTL_RX_THRESHOLD_64 0x00
++#define MTL_RX_THRESHOLD_96 0x02
++#define MTL_RX_THRESHOLD_128 0x03
++#define MTL_TX_THRESHOLD_32 0x01
++#define MTL_TX_THRESHOLD_64 0x00
++#define MTL_TX_THRESHOLD_96 0x02
++#define MTL_TX_THRESHOLD_128 0x03
++#define MTL_TX_THRESHOLD_192 0x04
++#define MTL_TX_THRESHOLD_256 0x05
++#define MTL_TX_THRESHOLD_384 0x06
++#define MTL_TX_THRESHOLD_512 0x07
++
++#define MTL_ETSALG_WRR 0x00
++#define MTL_ETSALG_WFQ 0x01
++#define MTL_ETSALG_DWRR 0x02
++#define MTL_RAA_SP 0x00
++#define MTL_RAA_WSP 0x01
++
++#define MTL_Q_DISABLED 0x00
++#define MTL_Q_ENABLED 0x02
++
++/* MTL traffic class register offsets
++ * Multiple traffic classes can be active. The first class has registers
++ * that begin at 0x1100. Each subsequent queue has registers that
++ * are accessed using an offset of 0x80 from the previous queue.
++ */
++#define MTL_TC_BASE MTL_Q_BASE
++#define MTL_TC_INC MTL_Q_INC
++
++#define MTL_TC_ETSCR 0x10
++#define MTL_TC_ETSSR 0x14
++#define MTL_TC_QWR 0x18
++
++/* MTL traffic class register entry bit positions and sizes */
++#define MTL_TC_ETSCR_TSA_INDEX 0
++#define MTL_TC_ETSCR_TSA_WIDTH 2
++#define MTL_TC_QWR_QW_INDEX 0
++#define MTL_TC_QWR_QW_WIDTH 21
++
++/* MTL traffic class register value */
++#define MTL_TSA_SP 0x00
++#define MTL_TSA_ETS 0x02
++
++/* PCS MMD select register offset
++ * The MMD select register is used for accessing PCS registers
++ * when the underlying APB3 interface is using indirect addressing.
++ * Indirect addressing requires accessing registers in two phases,
++ * an address phase and a data phase. The address phases requires
++ * writing an address selection value to the MMD select regiesters.
++ */
++#define PCS_MMD_SELECT 0xff
++
++/* Descriptor/Packet entry bit positions and sizes */
++#define RX_PACKET_ERRORS_CRC_INDEX 2
++#define RX_PACKET_ERRORS_CRC_WIDTH 1
++#define RX_PACKET_ERRORS_FRAME_INDEX 3
++#define RX_PACKET_ERRORS_FRAME_WIDTH 1
++#define RX_PACKET_ERRORS_LENGTH_INDEX 0
++#define RX_PACKET_ERRORS_LENGTH_WIDTH 1
++#define RX_PACKET_ERRORS_OVERRUN_INDEX 1
++#define RX_PACKET_ERRORS_OVERRUN_WIDTH 1
++
++#define RX_PACKET_ATTRIBUTES_CSUM_DONE_INDEX 0
++#define RX_PACKET_ATTRIBUTES_CSUM_DONE_WIDTH 1
++#define RX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX 1
++#define RX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH 1
++#define RX_PACKET_ATTRIBUTES_INCOMPLETE_INDEX 2
++#define RX_PACKET_ATTRIBUTES_INCOMPLETE_WIDTH 1
++#define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_INDEX 3
++#define RX_PACKET_ATTRIBUTES_CONTEXT_NEXT_WIDTH 1
++#define RX_PACKET_ATTRIBUTES_CONTEXT_INDEX 4
++#define RX_PACKET_ATTRIBUTES_CONTEXT_WIDTH 1
++#define RX_PACKET_ATTRIBUTES_RX_TSTAMP_INDEX 5
++#define RX_PACKET_ATTRIBUTES_RX_TSTAMP_WIDTH 1
++#define RX_PACKET_ATTRIBUTES_RSS_HASH_INDEX 6
++#define RX_PACKET_ATTRIBUTES_RSS_HASH_WIDTH 1
++
++#define RX_NORMAL_DESC0_OVT_INDEX 0
++#define RX_NORMAL_DESC0_OVT_WIDTH 16
++#define RX_NORMAL_DESC2_HL_INDEX 0
++#define RX_NORMAL_DESC2_HL_WIDTH 10
++#define RX_NORMAL_DESC3_CDA_INDEX 27
++#define RX_NORMAL_DESC3_CDA_WIDTH 1
++#define RX_NORMAL_DESC3_CTXT_INDEX 30
++#define RX_NORMAL_DESC3_CTXT_WIDTH 1
++#define RX_NORMAL_DESC3_ES_INDEX 15
++#define RX_NORMAL_DESC3_ES_WIDTH 1
++#define RX_NORMAL_DESC3_ETLT_INDEX 16
++#define RX_NORMAL_DESC3_ETLT_WIDTH 4
++#define RX_NORMAL_DESC3_FD_INDEX 29
++#define RX_NORMAL_DESC3_FD_WIDTH 1
++#define RX_NORMAL_DESC3_INTE_INDEX 30
++#define RX_NORMAL_DESC3_INTE_WIDTH 1
++#define RX_NORMAL_DESC3_L34T_INDEX 20
++#define RX_NORMAL_DESC3_L34T_WIDTH 4
++#define RX_NORMAL_DESC3_LD_INDEX 28
++#define RX_NORMAL_DESC3_LD_WIDTH 1
++#define RX_NORMAL_DESC3_OWN_INDEX 31
++#define RX_NORMAL_DESC3_OWN_WIDTH 1
++#define RX_NORMAL_DESC3_PL_INDEX 0
++#define RX_NORMAL_DESC3_PL_WIDTH 14
++#define RX_NORMAL_DESC3_RSV_INDEX 26
++#define RX_NORMAL_DESC3_RSV_WIDTH 1
++
++#define RX_DESC3_L34T_IPV4_TCP 1
++#define RX_DESC3_L34T_IPV4_UDP 2
++#define RX_DESC3_L34T_IPV4_ICMP 3
++#define RX_DESC3_L34T_IPV6_TCP 9
++#define RX_DESC3_L34T_IPV6_UDP 10
++#define RX_DESC3_L34T_IPV6_ICMP 11
++
++#define RX_CONTEXT_DESC3_TSA_INDEX 4
++#define RX_CONTEXT_DESC3_TSA_WIDTH 1
++#define RX_CONTEXT_DESC3_TSD_INDEX 6
++#define RX_CONTEXT_DESC3_TSD_WIDTH 1
++
++#define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_INDEX 0
++#define TX_PACKET_ATTRIBUTES_CSUM_ENABLE_WIDTH 1
++#define TX_PACKET_ATTRIBUTES_TSO_ENABLE_INDEX 1
++#define TX_PACKET_ATTRIBUTES_TSO_ENABLE_WIDTH 1
++#define TX_PACKET_ATTRIBUTES_VLAN_CTAG_INDEX 2
++#define TX_PACKET_ATTRIBUTES_VLAN_CTAG_WIDTH 1
++#define TX_PACKET_ATTRIBUTES_PTP_INDEX 3
++#define TX_PACKET_ATTRIBUTES_PTP_WIDTH 1
++
++#define TX_CONTEXT_DESC2_MSS_INDEX 0
++#define TX_CONTEXT_DESC2_MSS_WIDTH 15
++#define TX_CONTEXT_DESC3_CTXT_INDEX 30
++#define TX_CONTEXT_DESC3_CTXT_WIDTH 1
++#define TX_CONTEXT_DESC3_TCMSSV_INDEX 26
++#define TX_CONTEXT_DESC3_TCMSSV_WIDTH 1
++#define TX_CONTEXT_DESC3_VLTV_INDEX 16
++#define TX_CONTEXT_DESC3_VLTV_WIDTH 1
++#define TX_CONTEXT_DESC3_VT_INDEX 0
++#define TX_CONTEXT_DESC3_VT_WIDTH 16
++
++#define TX_NORMAL_DESC2_HL_B1L_INDEX 0
++#define TX_NORMAL_DESC2_HL_B1L_WIDTH 14
++#define TX_NORMAL_DESC2_IC_INDEX 31
++#define TX_NORMAL_DESC2_IC_WIDTH 1
++#define TX_NORMAL_DESC2_TTSE_INDEX 30
++#define TX_NORMAL_DESC2_TTSE_WIDTH 1
++#define TX_NORMAL_DESC2_VTIR_INDEX 14
++#define TX_NORMAL_DESC2_VTIR_WIDTH 2
++#define TX_NORMAL_DESC3_CIC_INDEX 16
++#define TX_NORMAL_DESC3_CIC_WIDTH 2
++#define TX_NORMAL_DESC3_CPC_INDEX 26
++#define TX_NORMAL_DESC3_CPC_WIDTH 2
++#define TX_NORMAL_DESC3_CTXT_INDEX 30
++#define TX_NORMAL_DESC3_CTXT_WIDTH 1
++#define TX_NORMAL_DESC3_FD_INDEX 29
++#define TX_NORMAL_DESC3_FD_WIDTH 1
++#define TX_NORMAL_DESC3_FL_INDEX 0
++#define TX_NORMAL_DESC3_FL_WIDTH 15
++#define TX_NORMAL_DESC3_LD_INDEX 28
++#define TX_NORMAL_DESC3_LD_WIDTH 1
++#define TX_NORMAL_DESC3_OWN_INDEX 31
++#define TX_NORMAL_DESC3_OWN_WIDTH 1
++#define TX_NORMAL_DESC3_TCPHDRLEN_INDEX 19
++#define TX_NORMAL_DESC3_TCPHDRLEN_WIDTH 4
++#define TX_NORMAL_DESC3_TCPPL_INDEX 0
++#define TX_NORMAL_DESC3_TCPPL_WIDTH 18
++#define TX_NORMAL_DESC3_TSE_INDEX 18
++#define TX_NORMAL_DESC3_TSE_WIDTH 1
++
++#define TX_NORMAL_DESC2_VLAN_INSERT 0x2
++
++/* MDIO undefined or vendor specific registers */
++#ifndef MDIO_AN_COMP_STAT
++#define MDIO_AN_COMP_STAT 0x0030
++#endif
++
++/* Bit setting and getting macros
++ * The get macro will extract the current bit field value from within
++ * the variable
++ *
++ * The set macro will clear the current bit field value within the
++ * variable and then set the bit field of the variable to the
++ * specified value
++ */
++#define GET_BITS(_var, _index, _width) \
++ (((_var) >> (_index)) & ((0x1 << (_width)) - 1))
++
++#define SET_BITS(_var, _index, _width, _val) \
++do { \
++ (_var) &= ~(((0x1 << (_width)) - 1) << (_index)); \
++ (_var) |= (((_val) & ((0x1 << (_width)) - 1)) << (_index)); \
++} while (0)
++
++#define GET_BITS_LE(_var, _index, _width) \
++ ((le32_to_cpu((_var)) >> (_index)) & ((0x1 << (_width)) - 1))
++
++#define SET_BITS_LE(_var, _index, _width, _val) \
++do { \
++ (_var) &= cpu_to_le32(~(((0x1 << (_width)) - 1) << (_index))); \
++ (_var) |= cpu_to_le32((((_val) & \
++ ((0x1 << (_width)) - 1)) << (_index))); \
++} while (0)
++
++/* Bit setting and getting macros based on register fields
++ * The get macro uses the bit field definitions formed using the input
++ * names to extract the current bit field value from within the
++ * variable
++ *
++ * The set macro uses the bit field definitions formed using the input
++ * names to set the bit field of the variable to the specified value
++ */
++#define XGMAC_GET_BITS(_var, _prefix, _field) \
++ GET_BITS((_var), \
++ _prefix##_##_field##_INDEX, \
++ _prefix##_##_field##_WIDTH)
++
++#define XGMAC_SET_BITS(_var, _prefix, _field, _val) \
++ SET_BITS((_var), \
++ _prefix##_##_field##_INDEX, \
++ _prefix##_##_field##_WIDTH, (_val))
++
++#define XGMAC_GET_BITS_LE(_var, _prefix, _field) \
++ GET_BITS_LE((_var), \
++ _prefix##_##_field##_INDEX, \
++ _prefix##_##_field##_WIDTH)
++
++#define XGMAC_SET_BITS_LE(_var, _prefix, _field, _val) \
++ SET_BITS_LE((_var), \
++ _prefix##_##_field##_INDEX, \
++ _prefix##_##_field##_WIDTH, (_val))
++
++/* Macros for reading or writing registers
++ * The ioread macros will get bit fields or full values using the
++ * register definitions formed using the input names
++ *
++ * The iowrite macros will set bit fields or full values using the
++ * register definitions formed using the input names
++ */
++#define XGMAC_IOREAD(_pdata, _reg) \
++ ioread32((_pdata)->xgmac_regs + _reg)
++
++#define XGMAC_IOREAD_BITS(_pdata, _reg, _field) \
++ GET_BITS(XGMAC_IOREAD((_pdata), _reg), \
++ _reg##_##_field##_INDEX, \
++ _reg##_##_field##_WIDTH)
++
++#define XGMAC_IOWRITE(_pdata, _reg, _val) \
++ iowrite32((_val), (_pdata)->xgmac_regs + _reg)
++
++#define XGMAC_IOWRITE_BITS(_pdata, _reg, _field, _val) \
++do { \
++ u32 reg_val = XGMAC_IOREAD((_pdata), _reg); \
++ SET_BITS(reg_val, \
++ _reg##_##_field##_INDEX, \
++ _reg##_##_field##_WIDTH, (_val)); \
++ XGMAC_IOWRITE((_pdata), _reg, reg_val); \
++} while (0)
++
++/* Macros for reading or writing MTL queue or traffic class registers
++ * Similar to the standard read and write macros except that the
++ * base register value is calculated by the queue or traffic class number
++ */
++#define XGMAC_MTL_IOREAD(_pdata, _n, _reg) \
++ ioread32((_pdata)->xgmac_regs + \
++ MTL_Q_BASE + ((_n) * MTL_Q_INC) + _reg)
++
++#define XGMAC_MTL_IOREAD_BITS(_pdata, _n, _reg, _field) \
++ GET_BITS(XGMAC_MTL_IOREAD((_pdata), (_n), _reg), \
++ _reg##_##_field##_INDEX, \
++ _reg##_##_field##_WIDTH)
++
++#define XGMAC_MTL_IOWRITE(_pdata, _n, _reg, _val) \
++ iowrite32((_val), (_pdata)->xgmac_regs + \
++ MTL_Q_BASE + ((_n) * MTL_Q_INC) + _reg)
++
++#define XGMAC_MTL_IOWRITE_BITS(_pdata, _n, _reg, _field, _val) \
++do { \
++ u32 reg_val = XGMAC_MTL_IOREAD((_pdata), (_n), _reg); \
++ SET_BITS(reg_val, \
++ _reg##_##_field##_INDEX, \
++ _reg##_##_field##_WIDTH, (_val)); \
++ XGMAC_MTL_IOWRITE((_pdata), (_n), _reg, reg_val); \
++} while (0)
++
++/* Macros for reading or writing DMA channel registers
++ * Similar to the standard read and write macros except that the
++ * base register value is obtained from the ring
++ */
++#define XGMAC_DMA_IOREAD(_channel, _reg) \
++ ioread32((_channel)->dma_regs + _reg)
++
++#define XGMAC_DMA_IOREAD_BITS(_channel, _reg, _field) \
++ GET_BITS(XGMAC_DMA_IOREAD((_channel), _reg), \
++ _reg##_##_field##_INDEX, \
++ _reg##_##_field##_WIDTH)
++
++#define XGMAC_DMA_IOWRITE(_channel, _reg, _val) \
++ iowrite32((_val), (_channel)->dma_regs + _reg)
++
++#define XGMAC_DMA_IOWRITE_BITS(_channel, _reg, _field, _val) \
++do { \
++ u32 reg_val = XGMAC_DMA_IOREAD((_channel), _reg); \
++ SET_BITS(reg_val, \
++ _reg##_##_field##_INDEX, \
++ _reg##_##_field##_WIDTH, (_val)); \
++ XGMAC_DMA_IOWRITE((_channel), _reg, reg_val); \
++} while (0)
++
++/* Macros for building, reading or writing register values or bits
++ * within the register values of XPCS registers.
++ */
++#define XPCS_IOWRITE(_pdata, _off, _val) \
++ iowrite32(_val, (_pdata)->xpcs_regs + (_off))
++
++#define XPCS_IOREAD(_pdata, _off) \
++ ioread32((_pdata)->xpcs_regs + (_off))
++
++/* Macros for building, reading or writing register values or bits
++ * using MDIO. Different from above because of the use of standardized
++ * Linux include values. No shifting is performed with the bit
++ * operations, everything works on mask values.
++ */
++#define XMDIO_READ(_pdata, _mmd, _reg) \
++ ((_pdata)->hw_if.read_mmd_regs((_pdata), 0, \
++ MII_ADDR_C45 | (_mmd << 16) | ((_reg) & 0xffff)))
++
++#define XMDIO_READ_BITS(_pdata, _mmd, _reg, _mask) \
++ (XMDIO_READ((_pdata), _mmd, _reg) & _mask)
++
++#define XMDIO_WRITE(_pdata, _mmd, _reg, _val) \
++ ((_pdata)->hw_if.write_mmd_regs((_pdata), 0, \
++ MII_ADDR_C45 | (_mmd << 16) | ((_reg) & 0xffff), (_val)))
++
++#define XMDIO_WRITE_BITS(_pdata, _mmd, _reg, _mask, _val) \
++do { \
++ u32 mmd_val = XMDIO_READ((_pdata), _mmd, _reg); \
++ mmd_val &= ~_mask; \
++ mmd_val |= (_val); \
++ XMDIO_WRITE((_pdata), _mmd, _reg, mmd_val); \
++} while (0)
++
++#endif
+diff --git a/drivers/net/ethernet/amd/xgbe-a0/xgbe-dcb.c b/drivers/net/ethernet/amd/xgbe-a0/xgbe-dcb.c
+new file mode 100644
+index 000000000000..343301cbf7b4
+--- /dev/null
++++ b/drivers/net/ethernet/amd/xgbe-a0/xgbe-dcb.c
+@@ -0,0 +1,269 @@
++/*
++ * AMD 10Gb Ethernet driver
++ *
++ * This file is available to you under your choice of the following two
++ * licenses:
++ *
++ * License 1: GPLv2
++ *
++ * Copyright (c) 2014 Advanced Micro Devices, Inc.
++ *
++ * This file is free software; you may copy, redistribute and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 2 of the License, or (at
++ * your option) any later version.
++ *
++ * This file is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ *
++ * This file incorporates work covered by the following copyright and
++ * permission notice:
++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation
++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
++ * Inc. unless otherwise expressly agreed to in writing between Synopsys
++ * and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product
++ * under any End User Software License Agreement or Agreement for Licensed
++ * Product with Synopsys or any supplement thereto. Permission is hereby
++ * granted, free of charge, to any person obtaining a copy of this software
++ * annotated with this license and the Software, to deal in the Software
++ * without restriction, including without limitation the rights to use,
++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
++ * of the Software, and to permit persons to whom the Software is furnished
++ * to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
++ * THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ *
++ * License 2: Modified BSD
++ *
++ * Copyright (c) 2014 Advanced Micro Devices, Inc.
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * * Neither the name of Advanced Micro Devices, Inc. nor the
++ * names of its contributors may be used to endorse or promote products
++ * derived from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * This file incorporates work covered by the following copyright and
++ * permission notice:
++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation
++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
++ * Inc. unless otherwise expressly agreed to in writing between Synopsys
++ * and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product
++ * under any End User Software License Agreement or Agreement for Licensed
++ * Product with Synopsys or any supplement thereto. Permission is hereby
++ * granted, free of charge, to any person obtaining a copy of this software
++ * annotated with this license and the Software, to deal in the Software
++ * without restriction, including without limitation the rights to use,
++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
++ * of the Software, and to permit persons to whom the Software is furnished
++ * to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
++ * THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include <linux/netdevice.h>
++#include <net/dcbnl.h>
++
++#include "xgbe.h"
++#include "xgbe-common.h"
++
++static int xgbe_dcb_ieee_getets(struct net_device *netdev,
++ struct ieee_ets *ets)
++{
++ struct xgbe_prv_data *pdata = netdev_priv(netdev);
++
++ /* Set number of supported traffic classes */
++ ets->ets_cap = pdata->hw_feat.tc_cnt;
++
++ if (pdata->ets) {
++ ets->cbs = pdata->ets->cbs;
++ memcpy(ets->tc_tx_bw, pdata->ets->tc_tx_bw,
++ sizeof(ets->tc_tx_bw));
++ memcpy(ets->tc_tsa, pdata->ets->tc_tsa,
++ sizeof(ets->tc_tsa));
++ memcpy(ets->prio_tc, pdata->ets->prio_tc,
++ sizeof(ets->prio_tc));
++ }
++
++ return 0;
++}
++
++static int xgbe_dcb_ieee_setets(struct net_device *netdev,
++ struct ieee_ets *ets)
++{
++ struct xgbe_prv_data *pdata = netdev_priv(netdev);
++ unsigned int i, tc_ets, tc_ets_weight;
++
++ tc_ets = 0;
++ tc_ets_weight = 0;
++ for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) {
++ DBGPR(" TC%u: tx_bw=%hhu, rx_bw=%hhu, tsa=%hhu\n", i,
++ ets->tc_tx_bw[i], ets->tc_rx_bw[i], ets->tc_tsa[i]);
++ DBGPR(" PRIO%u: TC=%hhu\n", i, ets->prio_tc[i]);
++
++ if ((ets->tc_tx_bw[i] || ets->tc_tsa[i]) &&
++ (i >= pdata->hw_feat.tc_cnt))
++ return -EINVAL;
++
++ if (ets->prio_tc[i] >= pdata->hw_feat.tc_cnt)
++ return -EINVAL;
++
++ switch (ets->tc_tsa[i]) {
++ case IEEE_8021QAZ_TSA_STRICT:
++ break;
++ case IEEE_8021QAZ_TSA_ETS:
++ tc_ets = 1;
++ tc_ets_weight += ets->tc_tx_bw[i];
++ break;
++
++ default:
++ return -EINVAL;
++ }
++ }
++
++ /* Weights must add up to 100% */
++ if (tc_ets && (tc_ets_weight != 100))
++ return -EINVAL;
++
++ if (!pdata->ets) {
++ pdata->ets = devm_kzalloc(pdata->dev, sizeof(*pdata->ets),
++ GFP_KERNEL);
++ if (!pdata->ets)
++ return -ENOMEM;
++ }
++
++ memcpy(pdata->ets, ets, sizeof(*pdata->ets));
++
++ pdata->hw_if.config_dcb_tc(pdata);
++
++ return 0;
++}
++
++static int xgbe_dcb_ieee_getpfc(struct net_device *netdev,
++ struct ieee_pfc *pfc)
++{
++ struct xgbe_prv_data *pdata = netdev_priv(netdev);
++
++ /* Set number of supported PFC traffic classes */
++ pfc->pfc_cap = pdata->hw_feat.tc_cnt;
++
++ if (pdata->pfc) {
++ pfc->pfc_en = pdata->pfc->pfc_en;
++ pfc->mbc = pdata->pfc->mbc;
++ pfc->delay = pdata->pfc->delay;
++ }
++
++ return 0;
++}
++
++static int xgbe_dcb_ieee_setpfc(struct net_device *netdev,
++ struct ieee_pfc *pfc)
++{
++ struct xgbe_prv_data *pdata = netdev_priv(netdev);
++
++ DBGPR(" cap=%hhu, en=%hhx, mbc=%hhu, delay=%hhu\n",
++ pfc->pfc_cap, pfc->pfc_en, pfc->mbc, pfc->delay);
++
++ if (!pdata->pfc) {
++ pdata->pfc = devm_kzalloc(pdata->dev, sizeof(*pdata->pfc),
++ GFP_KERNEL);
++ if (!pdata->pfc)
++ return -ENOMEM;
++ }
++
++ memcpy(pdata->pfc, pfc, sizeof(*pdata->pfc));
++
++ pdata->hw_if.config_dcb_pfc(pdata);
++
++ return 0;
++}
++
++static u8 xgbe_dcb_getdcbx(struct net_device *netdev)
++{
++ return DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_IEEE;
++}
++
++static u8 xgbe_dcb_setdcbx(struct net_device *netdev, u8 dcbx)
++{
++ u8 support = xgbe_dcb_getdcbx(netdev);
++
++ DBGPR(" DCBX=%#hhx\n", dcbx);
++
++ if (dcbx & ~support)
++ return 1;
++
++ if ((dcbx & support) != support)
++ return 1;
++
++ return 0;
++}
++
++static const struct dcbnl_rtnl_ops xgbe_dcbnl_ops = {
++ /* IEEE 802.1Qaz std */
++ .ieee_getets = xgbe_dcb_ieee_getets,
++ .ieee_setets = xgbe_dcb_ieee_setets,
++ .ieee_getpfc = xgbe_dcb_ieee_getpfc,
++ .ieee_setpfc = xgbe_dcb_ieee_setpfc,
++
++ /* DCBX configuration */
++ .getdcbx = xgbe_dcb_getdcbx,
++ .setdcbx = xgbe_dcb_setdcbx,
++};
++
++const struct dcbnl_rtnl_ops *xgbe_a0_get_dcbnl_ops(void)
++{
++ return &xgbe_dcbnl_ops;
++}
+diff --git a/drivers/net/ethernet/amd/xgbe-a0/xgbe-debugfs.c b/drivers/net/ethernet/amd/xgbe-a0/xgbe-debugfs.c
+new file mode 100644
+index 000000000000..ecfa6f91da22
+--- /dev/null
++++ b/drivers/net/ethernet/amd/xgbe-a0/xgbe-debugfs.c
+@@ -0,0 +1,373 @@
++/*
++ * AMD 10Gb Ethernet driver
++ *
++ * This file is available to you under your choice of the following two
++ * licenses:
++ *
++ * License 1: GPLv2
++ *
++ * Copyright (c) 2014 Advanced Micro Devices, Inc.
++ *
++ * This file is free software; you may copy, redistribute and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 2 of the License, or (at
++ * your option) any later version.
++ *
++ * This file is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ *
++ * This file incorporates work covered by the following copyright and
++ * permission notice:
++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation
++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
++ * Inc. unless otherwise expressly agreed to in writing between Synopsys
++ * and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product
++ * under any End User Software License Agreement or Agreement for Licensed
++ * Product with Synopsys or any supplement thereto. Permission is hereby
++ * granted, free of charge, to any person obtaining a copy of this software
++ * annotated with this license and the Software, to deal in the Software
++ * without restriction, including without limitation the rights to use,
++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
++ * of the Software, and to permit persons to whom the Software is furnished
++ * to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
++ * THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ *
++ * License 2: Modified BSD
++ *
++ * Copyright (c) 2014 Advanced Micro Devices, Inc.
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * * Neither the name of Advanced Micro Devices, Inc. nor the
++ * names of its contributors may be used to endorse or promote products
++ * derived from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * This file incorporates work covered by the following copyright and
++ * permission notice:
++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation
++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
++ * Inc. unless otherwise expressly agreed to in writing between Synopsys
++ * and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product
++ * under any End User Software License Agreement or Agreement for Licensed
++ * Product with Synopsys or any supplement thereto. Permission is hereby
++ * granted, free of charge, to any person obtaining a copy of this software
++ * annotated with this license and the Software, to deal in the Software
++ * without restriction, including without limitation the rights to use,
++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
++ * of the Software, and to permit persons to whom the Software is furnished
++ * to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
++ * THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include <linux/debugfs.h>
++#include <linux/module.h>
++#include <linux/slab.h>
++
++#include "xgbe.h"
++#include "xgbe-common.h"
++
++static ssize_t xgbe_common_read(char __user *buffer, size_t count,
++ loff_t *ppos, unsigned int value)
++{
++ char *buf;
++ ssize_t len;
++
++ if (*ppos != 0)
++ return 0;
++
++ buf = kasprintf(GFP_KERNEL, "0x%08x\n", value);
++ if (!buf)
++ return -ENOMEM;
++
++ if (count < strlen(buf)) {
++ kfree(buf);
++ return -ENOSPC;
++ }
++
++ len = simple_read_from_buffer(buffer, count, ppos, buf, strlen(buf));
++ kfree(buf);
++
++ return len;
++}
++
++static ssize_t xgbe_common_write(const char __user *buffer, size_t count,
++ loff_t *ppos, unsigned int *value)
++{
++ char workarea[32];
++ ssize_t len;
++ int ret;
++
++ if (*ppos != 0)
++ return 0;
++
++ if (count >= sizeof(workarea))
++ return -ENOSPC;
++
++ len = simple_write_to_buffer(workarea, sizeof(workarea) - 1, ppos,
++ buffer, count);
++ if (len < 0)
++ return len;
++
++ workarea[len] = '\0';
++ ret = kstrtouint(workarea, 16, value);
++ if (ret)
++ return -EIO;
++
++ return len;
++}
++
++static ssize_t xgmac_reg_addr_read(struct file *filp, char __user *buffer,
++ size_t count, loff_t *ppos)
++{
++ struct xgbe_prv_data *pdata = filp->private_data;
++
++ return xgbe_common_read(buffer, count, ppos, pdata->debugfs_xgmac_reg);
++}
++
++static ssize_t xgmac_reg_addr_write(struct file *filp,
++ const char __user *buffer,
++ size_t count, loff_t *ppos)
++{
++ struct xgbe_prv_data *pdata = filp->private_data;
++
++ return xgbe_common_write(buffer, count, ppos,
++ &pdata->debugfs_xgmac_reg);
++}
++
++static ssize_t xgmac_reg_value_read(struct file *filp, char __user *buffer,
++ size_t count, loff_t *ppos)
++{
++ struct xgbe_prv_data *pdata = filp->private_data;
++ unsigned int value;
++
++ value = XGMAC_IOREAD(pdata, pdata->debugfs_xgmac_reg);
++
++ return xgbe_common_read(buffer, count, ppos, value);
++}
++
++static ssize_t xgmac_reg_value_write(struct file *filp,
++ const char __user *buffer,
++ size_t count, loff_t *ppos)
++{
++ struct xgbe_prv_data *pdata = filp->private_data;
++ unsigned int value;
++ ssize_t len;
++
++ len = xgbe_common_write(buffer, count, ppos, &value);
++ if (len < 0)
++ return len;
++
++ XGMAC_IOWRITE(pdata, pdata->debugfs_xgmac_reg, value);
++
++ return len;
++}
++
++static const struct file_operations xgmac_reg_addr_fops = {
++ .owner = THIS_MODULE,
++ .open = simple_open,
++ .read = xgmac_reg_addr_read,
++ .write = xgmac_reg_addr_write,
++};
++
++static const struct file_operations xgmac_reg_value_fops = {
++ .owner = THIS_MODULE,
++ .open = simple_open,
++ .read = xgmac_reg_value_read,
++ .write = xgmac_reg_value_write,
++};
++
++static ssize_t xpcs_mmd_read(struct file *filp, char __user *buffer,
++ size_t count, loff_t *ppos)
++{
++ struct xgbe_prv_data *pdata = filp->private_data;
++
++ return xgbe_common_read(buffer, count, ppos, pdata->debugfs_xpcs_mmd);
++}
++
++static ssize_t xpcs_mmd_write(struct file *filp, const char __user *buffer,
++ size_t count, loff_t *ppos)
++{
++ struct xgbe_prv_data *pdata = filp->private_data;
++
++ return xgbe_common_write(buffer, count, ppos,
++ &pdata->debugfs_xpcs_mmd);
++}
++
++static ssize_t xpcs_reg_addr_read(struct file *filp, char __user *buffer,
++ size_t count, loff_t *ppos)
++{
++ struct xgbe_prv_data *pdata = filp->private_data;
++
++ return xgbe_common_read(buffer, count, ppos, pdata->debugfs_xpcs_reg);
++}
++
++static ssize_t xpcs_reg_addr_write(struct file *filp, const char __user *buffer,
++ size_t count, loff_t *ppos)
++{
++ struct xgbe_prv_data *pdata = filp->private_data;
++
++ return xgbe_common_write(buffer, count, ppos,
++ &pdata->debugfs_xpcs_reg);
++}
++
++static ssize_t xpcs_reg_value_read(struct file *filp, char __user *buffer,
++ size_t count, loff_t *ppos)
++{
++ struct xgbe_prv_data *pdata = filp->private_data;
++ unsigned int value;
++
++ value = XMDIO_READ(pdata, pdata->debugfs_xpcs_mmd,
++ pdata->debugfs_xpcs_reg);
++
++ return xgbe_common_read(buffer, count, ppos, value);
++}
++
++static ssize_t xpcs_reg_value_write(struct file *filp,
++ const char __user *buffer,
++ size_t count, loff_t *ppos)
++{
++ struct xgbe_prv_data *pdata = filp->private_data;
++ unsigned int value;
++ ssize_t len;
++
++ len = xgbe_common_write(buffer, count, ppos, &value);
++ if (len < 0)
++ return len;
++
++ XMDIO_WRITE(pdata, pdata->debugfs_xpcs_mmd, pdata->debugfs_xpcs_reg,
++ value);
++
++ return len;
++}
++
++static const struct file_operations xpcs_mmd_fops = {
++ .owner = THIS_MODULE,
++ .open = simple_open,
++ .read = xpcs_mmd_read,
++ .write = xpcs_mmd_write,
++};
++
++static const struct file_operations xpcs_reg_addr_fops = {
++ .owner = THIS_MODULE,
++ .open = simple_open,
++ .read = xpcs_reg_addr_read,
++ .write = xpcs_reg_addr_write,
++};
++
++static const struct file_operations xpcs_reg_value_fops = {
++ .owner = THIS_MODULE,
++ .open = simple_open,
++ .read = xpcs_reg_value_read,
++ .write = xpcs_reg_value_write,
++};
++
++void xgbe_a0_debugfs_init(struct xgbe_prv_data *pdata)
++{
++ struct dentry *pfile;
++ char *buf;
++
++ /* Set defaults */
++ pdata->debugfs_xgmac_reg = 0;
++ pdata->debugfs_xpcs_mmd = 1;
++ pdata->debugfs_xpcs_reg = 0;
++
++ buf = kasprintf(GFP_KERNEL, "amd-xgbe-a0-%s", pdata->netdev->name);
++ pdata->xgbe_debugfs = debugfs_create_dir(buf, NULL);
++ if (!pdata->xgbe_debugfs) {
++ netdev_err(pdata->netdev, "debugfs_create_dir failed\n");
++ return;
++ }
++
++ pfile = debugfs_create_file("xgmac_register", 0600,
++ pdata->xgbe_debugfs, pdata,
++ &xgmac_reg_addr_fops);
++ if (!pfile)
++ netdev_err(pdata->netdev, "debugfs_create_file failed\n");
++
++ pfile = debugfs_create_file("xgmac_register_value", 0600,
++ pdata->xgbe_debugfs, pdata,
++ &xgmac_reg_value_fops);
++ if (!pfile)
++ netdev_err(pdata->netdev, "debugfs_create_file failed\n");
++
++ pfile = debugfs_create_file("xpcs_mmd", 0600,
++ pdata->xgbe_debugfs, pdata,
++ &xpcs_mmd_fops);
++ if (!pfile)
++ netdev_err(pdata->netdev, "debugfs_create_file failed\n");
++
++ pfile = debugfs_create_file("xpcs_register", 0600,
++ pdata->xgbe_debugfs, pdata,
++ &xpcs_reg_addr_fops);
++ if (!pfile)
++ netdev_err(pdata->netdev, "debugfs_create_file failed\n");
++
++ pfile = debugfs_create_file("xpcs_register_value", 0600,
++ pdata->xgbe_debugfs, pdata,
++ &xpcs_reg_value_fops);
++ if (!pfile)
++ netdev_err(pdata->netdev, "debugfs_create_file failed\n");
++
++ kfree(buf);
++}
++
++void xgbe_a0_debugfs_exit(struct xgbe_prv_data *pdata)
++{
++ debugfs_remove_recursive(pdata->xgbe_debugfs);
++ pdata->xgbe_debugfs = NULL;
++}
+diff --git a/drivers/net/ethernet/amd/xgbe-a0/xgbe-desc.c b/drivers/net/ethernet/amd/xgbe-a0/xgbe-desc.c
+new file mode 100644
+index 000000000000..5dd57779c82c
+--- /dev/null
++++ b/drivers/net/ethernet/amd/xgbe-a0/xgbe-desc.c
+@@ -0,0 +1,636 @@
++/*
++ * AMD 10Gb Ethernet driver
++ *
++ * This file is available to you under your choice of the following two
++ * licenses:
++ *
++ * License 1: GPLv2
++ *
++ * Copyright (c) 2014 Advanced Micro Devices, Inc.
++ *
++ * This file is free software; you may copy, redistribute and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 2 of the License, or (at
++ * your option) any later version.
++ *
++ * This file is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ *
++ * This file incorporates work covered by the following copyright and
++ * permission notice:
++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation
++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
++ * Inc. unless otherwise expressly agreed to in writing between Synopsys
++ * and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product
++ * under any End User Software License Agreement or Agreement for Licensed
++ * Product with Synopsys or any supplement thereto. Permission is hereby
++ * granted, free of charge, to any person obtaining a copy of this software
++ * annotated with this license and the Software, to deal in the Software
++ * without restriction, including without limitation the rights to use,
++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
++ * of the Software, and to permit persons to whom the Software is furnished
++ * to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
++ * THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ *
++ * License 2: Modified BSD
++ *
++ * Copyright (c) 2014 Advanced Micro Devices, Inc.
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * * Neither the name of Advanced Micro Devices, Inc. nor the
++ * names of its contributors may be used to endorse or promote products
++ * derived from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * This file incorporates work covered by the following copyright and
++ * permission notice:
++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation
++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
++ * Inc. unless otherwise expressly agreed to in writing between Synopsys
++ * and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product
++ * under any End User Software License Agreement or Agreement for Licensed
++ * Product with Synopsys or any supplement thereto. Permission is hereby
++ * granted, free of charge, to any person obtaining a copy of this software
++ * annotated with this license and the Software, to deal in the Software
++ * without restriction, including without limitation the rights to use,
++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
++ * of the Software, and to permit persons to whom the Software is furnished
++ * to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
++ * THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include "xgbe.h"
++#include "xgbe-common.h"
++
++static void xgbe_unmap_rdata(struct xgbe_prv_data *, struct xgbe_ring_data *);
++
++static void xgbe_free_ring(struct xgbe_prv_data *pdata,
++ struct xgbe_ring *ring)
++{
++ struct xgbe_ring_data *rdata;
++ unsigned int i;
++
++ if (!ring)
++ return;
++
++ if (ring->rdata) {
++ for (i = 0; i < ring->rdesc_count; i++) {
++ rdata = XGBE_GET_DESC_DATA(ring, i);
++ xgbe_unmap_rdata(pdata, rdata);
++ }
++
++ kfree(ring->rdata);
++ ring->rdata = NULL;
++ }
++
++ if (ring->rx_hdr_pa.pages) {
++ dma_unmap_page(pdata->dev, ring->rx_hdr_pa.pages_dma,
++ ring->rx_hdr_pa.pages_len, DMA_FROM_DEVICE);
++ put_page(ring->rx_hdr_pa.pages);
++
++ ring->rx_hdr_pa.pages = NULL;
++ ring->rx_hdr_pa.pages_len = 0;
++ ring->rx_hdr_pa.pages_offset = 0;
++ ring->rx_hdr_pa.pages_dma = 0;
++ }
++
++ if (ring->rx_buf_pa.pages) {
++ dma_unmap_page(pdata->dev, ring->rx_buf_pa.pages_dma,
++ ring->rx_buf_pa.pages_len, DMA_FROM_DEVICE);
++ put_page(ring->rx_buf_pa.pages);
++
++ ring->rx_buf_pa.pages = NULL;
++ ring->rx_buf_pa.pages_len = 0;
++ ring->rx_buf_pa.pages_offset = 0;
++ ring->rx_buf_pa.pages_dma = 0;
++ }
++
++ if (ring->rdesc) {
++ dma_free_coherent(pdata->dev,
++ (sizeof(struct xgbe_ring_desc) *
++ ring->rdesc_count),
++ ring->rdesc, ring->rdesc_dma);
++ ring->rdesc = NULL;
++ }
++}
++
++static void xgbe_free_ring_resources(struct xgbe_prv_data *pdata)
++{
++ struct xgbe_channel *channel;
++ unsigned int i;
++
++ DBGPR("-->xgbe_free_ring_resources\n");
++
++ channel = pdata->channel;
++ for (i = 0; i < pdata->channel_count; i++, channel++) {
++ xgbe_free_ring(pdata, channel->tx_ring);
++ xgbe_free_ring(pdata, channel->rx_ring);
++ }
++
++ DBGPR("<--xgbe_free_ring_resources\n");
++}
++
++static int xgbe_init_ring(struct xgbe_prv_data *pdata,
++ struct xgbe_ring *ring, unsigned int rdesc_count)
++{
++ DBGPR("-->xgbe_init_ring\n");
++
++ if (!ring)
++ return 0;
++
++ /* Descriptors */
++ ring->rdesc_count = rdesc_count;
++ ring->rdesc = dma_alloc_coherent(pdata->dev,
++ (sizeof(struct xgbe_ring_desc) *
++ rdesc_count), &ring->rdesc_dma,
++ GFP_KERNEL);
++ if (!ring->rdesc)
++ return -ENOMEM;
++
++ /* Descriptor information */
++ ring->rdata = kcalloc(rdesc_count, sizeof(struct xgbe_ring_data),
++ GFP_KERNEL);
++ if (!ring->rdata)
++ return -ENOMEM;
++
++ DBGPR(" rdesc=0x%p, rdesc_dma=0x%llx, rdata=0x%p\n",
++ ring->rdesc, ring->rdesc_dma, ring->rdata);
++
++ DBGPR("<--xgbe_init_ring\n");
++
++ return 0;
++}
++
++static int xgbe_alloc_ring_resources(struct xgbe_prv_data *pdata)
++{
++ struct xgbe_channel *channel;
++ unsigned int i;
++ int ret;
++
++ DBGPR("-->xgbe_alloc_ring_resources\n");
++
++ channel = pdata->channel;
++ for (i = 0; i < pdata->channel_count; i++, channel++) {
++ DBGPR(" %s - tx_ring:\n", channel->name);
++ ret = xgbe_init_ring(pdata, channel->tx_ring,
++ pdata->tx_desc_count);
++ if (ret) {
++ netdev_alert(pdata->netdev,
++ "error initializing Tx ring\n");
++ goto err_ring;
++ }
++
++ DBGPR(" %s - rx_ring:\n", channel->name);
++ ret = xgbe_init_ring(pdata, channel->rx_ring,
++ pdata->rx_desc_count);
++ if (ret) {
++ netdev_alert(pdata->netdev,
++ "error initializing Tx ring\n");
++ goto err_ring;
++ }
++ }
++
++ DBGPR("<--xgbe_alloc_ring_resources\n");
++
++ return 0;
++
++err_ring:
++ xgbe_free_ring_resources(pdata);
++
++ return ret;
++}
++
++static int xgbe_alloc_pages(struct xgbe_prv_data *pdata,
++ struct xgbe_page_alloc *pa, gfp_t gfp, int order)
++{
++ struct page *pages = NULL;
++ dma_addr_t pages_dma;
++ int ret;
++
++ /* Try to obtain pages, decreasing order if necessary */
++ gfp |= __GFP_COLD | __GFP_COMP;
++ while (order >= 0) {
++ pages = alloc_pages(gfp, order);
++ if (pages)
++ break;
++
++ order--;
++ }
++ if (!pages)
++ return -ENOMEM;
++
++ /* Map the pages */
++ pages_dma = dma_map_page(pdata->dev, pages, 0,
++ PAGE_SIZE << order, DMA_FROM_DEVICE);
++ ret = dma_mapping_error(pdata->dev, pages_dma);
++ if (ret) {
++ put_page(pages);
++ return ret;
++ }
++
++ pa->pages = pages;
++ pa->pages_len = PAGE_SIZE << order;
++ pa->pages_offset = 0;
++ pa->pages_dma = pages_dma;
++
++ return 0;
++}
++
++static void xgbe_set_buffer_data(struct xgbe_buffer_data *bd,
++ struct xgbe_page_alloc *pa,
++ unsigned int len)
++{
++ get_page(pa->pages);
++ bd->pa = *pa;
++
++ bd->dma = pa->pages_dma + pa->pages_offset;
++ bd->dma_len = len;
++
++ pa->pages_offset += len;
++ if ((pa->pages_offset + len) > pa->pages_len) {
++ /* This data descriptor is responsible for unmapping page(s) */
++ bd->pa_unmap = *pa;
++
++ /* Get a new allocation next time */
++ pa->pages = NULL;
++ pa->pages_len = 0;
++ pa->pages_offset = 0;
++ pa->pages_dma = 0;
++ }
++}
++
++static int xgbe_map_rx_buffer(struct xgbe_prv_data *pdata,
++ struct xgbe_ring *ring,
++ struct xgbe_ring_data *rdata)
++{
++ int order, ret;
++
++ if (!ring->rx_hdr_pa.pages) {
++ ret = xgbe_alloc_pages(pdata, &ring->rx_hdr_pa, GFP_ATOMIC, 0);
++ if (ret)
++ return ret;
++ }
++
++ if (!ring->rx_buf_pa.pages) {
++ order = max_t(int, PAGE_ALLOC_COSTLY_ORDER - 1, 0);
++ ret = xgbe_alloc_pages(pdata, &ring->rx_buf_pa, GFP_ATOMIC,
++ order);
++ if (ret)
++ return ret;
++ }
++
++ /* Set up the header page info */
++ xgbe_set_buffer_data(&rdata->rx.hdr, &ring->rx_hdr_pa,
++ XGBE_SKB_ALLOC_SIZE);
++
++ /* Set up the buffer page info */
++ xgbe_set_buffer_data(&rdata->rx.buf, &ring->rx_buf_pa,
++ pdata->rx_buf_size);
++
++ return 0;
++}
++
++static void xgbe_wrapper_tx_descriptor_init(struct xgbe_prv_data *pdata)
++{
++ struct xgbe_hw_if *hw_if = &pdata->hw_if;
++ struct xgbe_channel *channel;
++ struct xgbe_ring *ring;
++ struct xgbe_ring_data *rdata;
++ struct xgbe_ring_desc *rdesc;
++ dma_addr_t rdesc_dma;
++ unsigned int i, j;
++
++ DBGPR("-->xgbe_wrapper_tx_descriptor_init\n");
++
++ channel = pdata->channel;
++ for (i = 0; i < pdata->channel_count; i++, channel++) {
++ ring = channel->tx_ring;
++ if (!ring)
++ break;
++
++ rdesc = ring->rdesc;
++ rdesc_dma = ring->rdesc_dma;
++
++ for (j = 0; j < ring->rdesc_count; j++) {
++ rdata = XGBE_GET_DESC_DATA(ring, j);
++
++ rdata->rdesc = rdesc;
++ rdata->rdesc_dma = rdesc_dma;
++
++ rdesc++;
++ rdesc_dma += sizeof(struct xgbe_ring_desc);
++ }
++
++ ring->cur = 0;
++ ring->dirty = 0;
++ memset(&ring->tx, 0, sizeof(ring->tx));
++
++ hw_if->tx_desc_init(channel);
++ }
++
++ DBGPR("<--xgbe_wrapper_tx_descriptor_init\n");
++}
++
++static void xgbe_wrapper_rx_descriptor_init(struct xgbe_prv_data *pdata)
++{
++ struct xgbe_hw_if *hw_if = &pdata->hw_if;
++ struct xgbe_channel *channel;
++ struct xgbe_ring *ring;
++ struct xgbe_ring_desc *rdesc;
++ struct xgbe_ring_data *rdata;
++ dma_addr_t rdesc_dma;
++ unsigned int i, j;
++
++ DBGPR("-->xgbe_wrapper_rx_descriptor_init\n");
++
++ channel = pdata->channel;
++ for (i = 0; i < pdata->channel_count; i++, channel++) {
++ ring = channel->rx_ring;
++ if (!ring)
++ break;
++
++ rdesc = ring->rdesc;
++ rdesc_dma = ring->rdesc_dma;
++
++ for (j = 0; j < ring->rdesc_count; j++) {
++ rdata = XGBE_GET_DESC_DATA(ring, j);
++
++ rdata->rdesc = rdesc;
++ rdata->rdesc_dma = rdesc_dma;
++
++ if (xgbe_map_rx_buffer(pdata, ring, rdata))
++ break;
++
++ rdesc++;
++ rdesc_dma += sizeof(struct xgbe_ring_desc);
++ }
++
++ ring->cur = 0;
++ ring->dirty = 0;
++
++ hw_if->rx_desc_init(channel);
++ }
++
++ DBGPR("<--xgbe_wrapper_rx_descriptor_init\n");
++}
++
++static void xgbe_unmap_rdata(struct xgbe_prv_data *pdata,
++ struct xgbe_ring_data *rdata)
++{
++ if (rdata->skb_dma) {
++ if (rdata->mapped_as_page) {
++ dma_unmap_page(pdata->dev, rdata->skb_dma,
++ rdata->skb_dma_len, DMA_TO_DEVICE);
++ } else {
++ dma_unmap_single(pdata->dev, rdata->skb_dma,
++ rdata->skb_dma_len, DMA_TO_DEVICE);
++ }
++ rdata->skb_dma = 0;
++ rdata->skb_dma_len = 0;
++ }
++
++ if (rdata->skb) {
++ dev_kfree_skb_any(rdata->skb);
++ rdata->skb = NULL;
++ }
++
++ if (rdata->rx.hdr.pa.pages)
++ put_page(rdata->rx.hdr.pa.pages);
++
++ if (rdata->rx.hdr.pa_unmap.pages) {
++ dma_unmap_page(pdata->dev, rdata->rx.hdr.pa_unmap.pages_dma,
++ rdata->rx.hdr.pa_unmap.pages_len,
++ DMA_FROM_DEVICE);
++ put_page(rdata->rx.hdr.pa_unmap.pages);
++ }
++
++ if (rdata->rx.buf.pa.pages)
++ put_page(rdata->rx.buf.pa.pages);
++
++ if (rdata->rx.buf.pa_unmap.pages) {
++ dma_unmap_page(pdata->dev, rdata->rx.buf.pa_unmap.pages_dma,
++ rdata->rx.buf.pa_unmap.pages_len,
++ DMA_FROM_DEVICE);
++ put_page(rdata->rx.buf.pa_unmap.pages);
++ }
++
++ memset(&rdata->tx, 0, sizeof(rdata->tx));
++ memset(&rdata->rx, 0, sizeof(rdata->rx));
++
++ rdata->mapped_as_page = 0;
++
++ if (rdata->state_saved) {
++ rdata->state_saved = 0;
++ rdata->state.incomplete = 0;
++ rdata->state.context_next = 0;
++ rdata->state.skb = NULL;
++ rdata->state.len = 0;
++ rdata->state.error = 0;
++ }
++}
++
++static int xgbe_map_tx_skb(struct xgbe_channel *channel, struct sk_buff *skb)
++{
++ struct xgbe_prv_data *pdata = channel->pdata;
++ struct xgbe_ring *ring = channel->tx_ring;
++ struct xgbe_ring_data *rdata;
++ struct xgbe_packet_data *packet;
++ struct skb_frag_struct *frag;
++ dma_addr_t skb_dma;
++ unsigned int start_index, cur_index;
++ unsigned int offset, tso, vlan, datalen, len;
++ unsigned int i;
++
++ DBGPR("-->xgbe_map_tx_skb: cur = %d\n", ring->cur);
++
++ offset = 0;
++ start_index = ring->cur;
++ cur_index = ring->cur;
++
++ packet = &ring->packet_data;
++ packet->rdesc_count = 0;
++ packet->length = 0;
++
++ tso = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
++ TSO_ENABLE);
++ vlan = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
++ VLAN_CTAG);
++
++ /* Save space for a context descriptor if needed */
++ if ((tso && (packet->mss != ring->tx.cur_mss)) ||
++ (vlan && (packet->vlan_ctag != ring->tx.cur_vlan_ctag)))
++ cur_index++;
++ rdata = XGBE_GET_DESC_DATA(ring, cur_index);
++
++ if (tso) {
++ DBGPR(" TSO packet\n");
++
++ /* Map the TSO header */
++ skb_dma = dma_map_single(pdata->dev, skb->data,
++ packet->header_len, DMA_TO_DEVICE);
++ if (dma_mapping_error(pdata->dev, skb_dma)) {
++ netdev_alert(pdata->netdev, "dma_map_single failed\n");
++ goto err_out;
++ }
++ rdata->skb_dma = skb_dma;
++ rdata->skb_dma_len = packet->header_len;
++
++ offset = packet->header_len;
++
++ packet->length += packet->header_len;
++
++ cur_index++;
++ rdata = XGBE_GET_DESC_DATA(ring, cur_index);
++ }
++
++ /* Map the (remainder of the) packet */
++ for (datalen = skb_headlen(skb) - offset; datalen; ) {
++ len = min_t(unsigned int, datalen, XGBE_TX_MAX_BUF_SIZE);
++
++ skb_dma = dma_map_single(pdata->dev, skb->data + offset, len,
++ DMA_TO_DEVICE);
++ if (dma_mapping_error(pdata->dev, skb_dma)) {
++ netdev_alert(pdata->netdev, "dma_map_single failed\n");
++ goto err_out;
++ }
++ rdata->skb_dma = skb_dma;
++ rdata->skb_dma_len = len;
++ DBGPR(" skb data: index=%u, dma=0x%llx, len=%u\n",
++ cur_index, skb_dma, len);
++
++ datalen -= len;
++ offset += len;
++
++ packet->length += len;
++
++ cur_index++;
++ rdata = XGBE_GET_DESC_DATA(ring, cur_index);
++ }
++
++ for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
++ DBGPR(" mapping frag %u\n", i);
++
++ frag = &skb_shinfo(skb)->frags[i];
++ offset = 0;
++
++ for (datalen = skb_frag_size(frag); datalen; ) {
++ len = min_t(unsigned int, datalen,
++ XGBE_TX_MAX_BUF_SIZE);
++
++ skb_dma = skb_frag_dma_map(pdata->dev, frag, offset,
++ len, DMA_TO_DEVICE);
++ if (dma_mapping_error(pdata->dev, skb_dma)) {
++ netdev_alert(pdata->netdev,
++ "skb_frag_dma_map failed\n");
++ goto err_out;
++ }
++ rdata->skb_dma = skb_dma;
++ rdata->skb_dma_len = len;
++ rdata->mapped_as_page = 1;
++ DBGPR(" skb data: index=%u, dma=0x%llx, len=%u\n",
++ cur_index, skb_dma, len);
++
++ datalen -= len;
++ offset += len;
++
++ packet->length += len;
++
++ cur_index++;
++ rdata = XGBE_GET_DESC_DATA(ring, cur_index);
++ }
++ }
++
++ /* Save the skb address in the last entry. We always have some data
++ * that has been mapped so rdata is always advanced past the last
++ * piece of mapped data - use the entry pointed to by cur_index - 1.
++ */
++ rdata = XGBE_GET_DESC_DATA(ring, cur_index - 1);
++ rdata->skb = skb;
++
++ /* Save the number of descriptor entries used */
++ packet->rdesc_count = cur_index - start_index;
++
++ DBGPR("<--xgbe_map_tx_skb: count=%u\n", packet->rdesc_count);
++
++ return packet->rdesc_count;
++
++err_out:
++ while (start_index < cur_index) {
++ rdata = XGBE_GET_DESC_DATA(ring, start_index++);
++ xgbe_unmap_rdata(pdata, rdata);
++ }
++
++ DBGPR("<--xgbe_map_tx_skb: count=0\n");
++
++ return 0;
++}
++
++void xgbe_a0_init_function_ptrs_desc(struct xgbe_desc_if *desc_if)
++{
++ DBGPR("-->xgbe_a0_init_function_ptrs_desc\n");
++
++ desc_if->alloc_ring_resources = xgbe_alloc_ring_resources;
++ desc_if->free_ring_resources = xgbe_free_ring_resources;
++ desc_if->map_tx_skb = xgbe_map_tx_skb;
++ desc_if->map_rx_buffer = xgbe_map_rx_buffer;
++ desc_if->unmap_rdata = xgbe_unmap_rdata;
++ desc_if->wrapper_tx_desc_init = xgbe_wrapper_tx_descriptor_init;
++ desc_if->wrapper_rx_desc_init = xgbe_wrapper_rx_descriptor_init;
++
++ DBGPR("<--xgbe_a0_init_function_ptrs_desc\n");
++}
+diff --git a/drivers/net/ethernet/amd/xgbe-a0/xgbe-dev.c b/drivers/net/ethernet/amd/xgbe-a0/xgbe-dev.c
+new file mode 100644
+index 000000000000..f6a3a581cc21
+--- /dev/null
++++ b/drivers/net/ethernet/amd/xgbe-a0/xgbe-dev.c
+@@ -0,0 +1,2964 @@
++/*
++ * AMD 10Gb Ethernet driver
++ *
++ * This file is available to you under your choice of the following two
++ * licenses:
++ *
++ * License 1: GPLv2
++ *
++ * Copyright (c) 2014 Advanced Micro Devices, Inc.
++ *
++ * This file is free software; you may copy, redistribute and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 2 of the License, or (at
++ * your option) any later version.
++ *
++ * This file is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ *
++ * This file incorporates work covered by the following copyright and
++ * permission notice:
++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation
++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
++ * Inc. unless otherwise expressly agreed to in writing between Synopsys
++ * and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product
++ * under any End User Software License Agreement or Agreement for Licensed
++ * Product with Synopsys or any supplement thereto. Permission is hereby
++ * granted, free of charge, to any person obtaining a copy of this software
++ * annotated with this license and the Software, to deal in the Software
++ * without restriction, including without limitation the rights to use,
++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
++ * of the Software, and to permit persons to whom the Software is furnished
++ * to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
++ * THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ *
++ * License 2: Modified BSD
++ *
++ * Copyright (c) 2014 Advanced Micro Devices, Inc.
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * * Neither the name of Advanced Micro Devices, Inc. nor the
++ * names of its contributors may be used to endorse or promote products
++ * derived from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * This file incorporates work covered by the following copyright and
++ * permission notice:
++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation
++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
++ * Inc. unless otherwise expressly agreed to in writing between Synopsys
++ * and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product
++ * under any End User Software License Agreement or Agreement for Licensed
++ * Product with Synopsys or any supplement thereto. Permission is hereby
++ * granted, free of charge, to any person obtaining a copy of this software
++ * annotated with this license and the Software, to deal in the Software
++ * without restriction, including without limitation the rights to use,
++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
++ * of the Software, and to permit persons to whom the Software is furnished
++ * to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
++ * THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include <linux/phy.h>
++#include <linux/mdio.h>
++#include <linux/clk.h>
++#include <linux/bitrev.h>
++#include <linux/crc32.h>
++
++#include "xgbe.h"
++#include "xgbe-common.h"
++
++static unsigned int xgbe_usec_to_riwt(struct xgbe_prv_data *pdata,
++ unsigned int usec)
++{
++ unsigned long rate;
++ unsigned int ret;
++
++ DBGPR("-->xgbe_usec_to_riwt\n");
++
++ rate = pdata->sysclk_rate;
++
++ /*
++ * Convert the input usec value to the watchdog timer value. Each
++ * watchdog timer value is equivalent to 256 clock cycles.
++ * Calculate the required value as:
++ * ( usec * ( system_clock_mhz / 10^6 ) / 256
++ */
++ ret = (usec * (rate / 1000000)) / 256;
++
++ DBGPR("<--xgbe_usec_to_riwt\n");
++
++ return ret;
++}
++
++static unsigned int xgbe_riwt_to_usec(struct xgbe_prv_data *pdata,
++ unsigned int riwt)
++{
++ unsigned long rate;
++ unsigned int ret;
++
++ DBGPR("-->xgbe_riwt_to_usec\n");
++
++ rate = pdata->sysclk_rate;
++
++ /*
++ * Convert the input watchdog timer value to the usec value. Each
++ * watchdog timer value is equivalent to 256 clock cycles.
++ * Calculate the required value as:
++ * ( riwt * 256 ) / ( system_clock_mhz / 10^6 )
++ */
++ ret = (riwt * 256) / (rate / 1000000);
++
++ DBGPR("<--xgbe_riwt_to_usec\n");
++
++ return ret;
++}
++
++static int xgbe_config_pblx8(struct xgbe_prv_data *pdata)
++{
++ struct xgbe_channel *channel;
++ unsigned int i;
++
++ channel = pdata->channel;
++ for (i = 0; i < pdata->channel_count; i++, channel++)
++ XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_CR, PBLX8,
++ pdata->pblx8);
++
++ return 0;
++}
++
++static int xgbe_get_tx_pbl_val(struct xgbe_prv_data *pdata)
++{
++ return XGMAC_DMA_IOREAD_BITS(pdata->channel, DMA_CH_TCR, PBL);
++}
++
++static int xgbe_config_tx_pbl_val(struct xgbe_prv_data *pdata)
++{
++ struct xgbe_channel *channel;
++ unsigned int i;
++
++ channel = pdata->channel;
++ for (i = 0; i < pdata->channel_count; i++, channel++) {
++ if (!channel->tx_ring)
++ break;
++
++ XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, PBL,
++ pdata->tx_pbl);
++ }
++
++ return 0;
++}
++
++static int xgbe_get_rx_pbl_val(struct xgbe_prv_data *pdata)
++{
++ return XGMAC_DMA_IOREAD_BITS(pdata->channel, DMA_CH_RCR, PBL);
++}
++
++static int xgbe_config_rx_pbl_val(struct xgbe_prv_data *pdata)
++{
++ struct xgbe_channel *channel;
++ unsigned int i;
++
++ channel = pdata->channel;
++ for (i = 0; i < pdata->channel_count; i++, channel++) {
++ if (!channel->rx_ring)
++ break;
++
++ XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, PBL,
++ pdata->rx_pbl);
++ }
++
++ return 0;
++}
++
++static int xgbe_config_osp_mode(struct xgbe_prv_data *pdata)
++{
++ struct xgbe_channel *channel;
++ unsigned int i;
++
++ channel = pdata->channel;
++ for (i = 0; i < pdata->channel_count; i++, channel++) {
++ if (!channel->tx_ring)
++ break;
++
++ XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, OSP,
++ pdata->tx_osp_mode);
++ }
++
++ return 0;
++}
++
++static int xgbe_config_rsf_mode(struct xgbe_prv_data *pdata, unsigned int val)
++{
++ unsigned int i;
++
++ for (i = 0; i < pdata->rx_q_count; i++)
++ XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RSF, val);
++
++ return 0;
++}
++
++static int xgbe_config_tsf_mode(struct xgbe_prv_data *pdata, unsigned int val)
++{
++ unsigned int i;
++
++ for (i = 0; i < pdata->tx_q_count; i++)
++ XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TSF, val);
++
++ return 0;
++}
++
++static int xgbe_config_rx_threshold(struct xgbe_prv_data *pdata,
++ unsigned int val)
++{
++ unsigned int i;
++
++ for (i = 0; i < pdata->rx_q_count; i++)
++ XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RTC, val);
++
++ return 0;
++}
++
++static int xgbe_config_tx_threshold(struct xgbe_prv_data *pdata,
++ unsigned int val)
++{
++ unsigned int i;
++
++ for (i = 0; i < pdata->tx_q_count; i++)
++ XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TTC, val);
++
++ return 0;
++}
++
++static int xgbe_config_rx_coalesce(struct xgbe_prv_data *pdata)
++{
++ struct xgbe_channel *channel;
++ unsigned int i;
++
++ channel = pdata->channel;
++ for (i = 0; i < pdata->channel_count; i++, channel++) {
++ if (!channel->rx_ring)
++ break;
++
++ XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RIWT, RWT,
++ pdata->rx_riwt);
++ }
++
++ return 0;
++}
++
++static int xgbe_config_tx_coalesce(struct xgbe_prv_data *pdata)
++{
++ return 0;
++}
++
++static void xgbe_config_rx_buffer_size(struct xgbe_prv_data *pdata)
++{
++ struct xgbe_channel *channel;
++ unsigned int i;
++
++ channel = pdata->channel;
++ for (i = 0; i < pdata->channel_count; i++, channel++) {
++ if (!channel->rx_ring)
++ break;
++
++ XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, RBSZ,
++ pdata->rx_buf_size);
++ }
++}
++
++static void xgbe_config_tso_mode(struct xgbe_prv_data *pdata)
++{
++ struct xgbe_channel *channel;
++ unsigned int i;
++
++ channel = pdata->channel;
++ for (i = 0; i < pdata->channel_count; i++, channel++) {
++ if (!channel->tx_ring)
++ break;
++
++ XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, TSE, 1);
++ }
++}
++
++static void xgbe_config_sph_mode(struct xgbe_prv_data *pdata)
++{
++ struct xgbe_channel *channel;
++ unsigned int i;
++
++ channel = pdata->channel;
++ for (i = 0; i < pdata->channel_count; i++, channel++) {
++ if (!channel->rx_ring)
++ break;
++
++ XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_CR, SPH, 1);
++ }
++
++ XGMAC_IOWRITE_BITS(pdata, MAC_RCR, HDSMS, XGBE_SPH_HDSMS_SIZE);
++}
++
++static int xgbe_write_rss_reg(struct xgbe_prv_data *pdata, unsigned int type,
++ unsigned int index, unsigned int val)
++{
++ unsigned int wait;
++ int ret = 0;
++
++ mutex_lock(&pdata->rss_mutex);
++
++ if (XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB)) {
++ ret = -EBUSY;
++ goto unlock;
++ }
++
++ XGMAC_IOWRITE(pdata, MAC_RSSDR, val);
++
++ XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, RSSIA, index);
++ XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, ADDRT, type);
++ XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, CT, 0);
++ XGMAC_IOWRITE_BITS(pdata, MAC_RSSAR, OB, 1);
++
++ wait = 1000;
++ while (wait--) {
++ if (!XGMAC_IOREAD_BITS(pdata, MAC_RSSAR, OB))
++ goto unlock;
++
++ usleep_range(1000, 1500);
++ }
++
++ ret = -EBUSY;
++
++unlock:
++ mutex_unlock(&pdata->rss_mutex);
++
++ return ret;
++}
++
++static int xgbe_write_rss_hash_key(struct xgbe_prv_data *pdata)
++{
++ unsigned int key_regs = sizeof(pdata->rss_key) / sizeof(u32);
++ unsigned int *key = (unsigned int *)&pdata->rss_key;
++ int ret;
++
++ while (key_regs--) {
++ ret = xgbe_write_rss_reg(pdata, XGBE_RSS_HASH_KEY_TYPE,
++ key_regs, *key++);
++ if (ret)
++ return ret;
++ }
++
++ return 0;
++}
++
++static int xgbe_write_rss_lookup_table(struct xgbe_prv_data *pdata)
++{
++ unsigned int i;
++ int ret;
++
++ for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++) {
++ ret = xgbe_write_rss_reg(pdata,
++ XGBE_RSS_LOOKUP_TABLE_TYPE, i,
++ pdata->rss_table[i]);
++ if (ret)
++ return ret;
++ }
++
++ return 0;
++}
++
++static int xgbe_set_rss_hash_key(struct xgbe_prv_data *pdata, const u8 *key)
++{
++ memcpy(pdata->rss_key, key, sizeof(pdata->rss_key));
++
++ return xgbe_write_rss_hash_key(pdata);
++}
++
++static int xgbe_set_rss_lookup_table(struct xgbe_prv_data *pdata,
++ const u32 *table)
++{
++ unsigned int i;
++
++ for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++)
++ XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, table[i]);
++
++ return xgbe_write_rss_lookup_table(pdata);
++}
++
++static int xgbe_enable_rss(struct xgbe_prv_data *pdata)
++{
++ int ret;
++
++ if (!pdata->hw_feat.rss)
++ return -EOPNOTSUPP;
++
++ /* Program the hash key */
++ ret = xgbe_write_rss_hash_key(pdata);
++ if (ret)
++ return ret;
++
++ /* Program the lookup table */
++ ret = xgbe_write_rss_lookup_table(pdata);
++ if (ret)
++ return ret;
++
++ /* Set the RSS options */
++ XGMAC_IOWRITE(pdata, MAC_RSSCR, pdata->rss_options);
++
++ /* Enable RSS */
++ XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 1);
++
++ return 0;
++}
++
++static int xgbe_disable_rss(struct xgbe_prv_data *pdata)
++{
++ if (!pdata->hw_feat.rss)
++ return -EOPNOTSUPP;
++
++ XGMAC_IOWRITE_BITS(pdata, MAC_RSSCR, RSSE, 0);
++
++ return 0;
++}
++
++static void xgbe_config_rss(struct xgbe_prv_data *pdata)
++{
++ int ret;
++
++ if (!pdata->hw_feat.rss)
++ return;
++
++ if (pdata->netdev->features & NETIF_F_RXHASH)
++ ret = xgbe_enable_rss(pdata);
++ else
++ ret = xgbe_disable_rss(pdata);
++
++ if (ret)
++ netdev_err(pdata->netdev,
++ "error configuring RSS, RSS disabled\n");
++}
++
++static int xgbe_disable_tx_flow_control(struct xgbe_prv_data *pdata)
++{
++ unsigned int max_q_count, q_count;
++ unsigned int reg, reg_val;
++ unsigned int i;
++
++ /* Clear MTL flow control */
++ for (i = 0; i < pdata->rx_q_count; i++)
++ XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 0);
++
++ /* Clear MAC flow control */
++ max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES;
++ q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count);
++ reg = MAC_Q0TFCR;
++ for (i = 0; i < q_count; i++) {
++ reg_val = XGMAC_IOREAD(pdata, reg);
++ XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 0);
++ XGMAC_IOWRITE(pdata, reg, reg_val);
++
++ reg += MAC_QTFCR_INC;
++ }
++
++ return 0;
++}
++
++static int xgbe_enable_tx_flow_control(struct xgbe_prv_data *pdata)
++{
++ unsigned int max_q_count, q_count;
++ unsigned int reg, reg_val;
++ unsigned int i;
++
++ /* Set MTL flow control */
++ for (i = 0; i < pdata->rx_q_count; i++)
++ XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, EHFC, 1);
++
++ /* Set MAC flow control */
++ max_q_count = XGMAC_MAX_FLOW_CONTROL_QUEUES;
++ q_count = min_t(unsigned int, pdata->tx_q_count, max_q_count);
++ reg = MAC_Q0TFCR;
++ for (i = 0; i < q_count; i++) {
++ reg_val = XGMAC_IOREAD(pdata, reg);
++
++ /* Enable transmit flow control */
++ XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 1);
++ /* Set pause time */
++ XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, 0xffff);
++
++ XGMAC_IOWRITE(pdata, reg, reg_val);
++
++ reg += MAC_QTFCR_INC;
++ }
++
++ return 0;
++}
++
++static int xgbe_disable_rx_flow_control(struct xgbe_prv_data *pdata)
++{
++ XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 0);
++
++ return 0;
++}
++
++static int xgbe_enable_rx_flow_control(struct xgbe_prv_data *pdata)
++{
++ XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, RFE, 1);
++
++ return 0;
++}
++
++static int xgbe_config_tx_flow_control(struct xgbe_prv_data *pdata)
++{
++ struct ieee_pfc *pfc = pdata->pfc;
++
++ if (pdata->tx_pause || (pfc && pfc->pfc_en))
++ xgbe_enable_tx_flow_control(pdata);
++ else
++ xgbe_disable_tx_flow_control(pdata);
++
++ return 0;
++}
++
++static int xgbe_config_rx_flow_control(struct xgbe_prv_data *pdata)
++{
++ struct ieee_pfc *pfc = pdata->pfc;
++
++ if (pdata->rx_pause || (pfc && pfc->pfc_en))
++ xgbe_enable_rx_flow_control(pdata);
++ else
++ xgbe_disable_rx_flow_control(pdata);
++
++ return 0;
++}
++
++static void xgbe_config_flow_control(struct xgbe_prv_data *pdata)
++{
++ struct ieee_pfc *pfc = pdata->pfc;
++
++ xgbe_config_tx_flow_control(pdata);
++ xgbe_config_rx_flow_control(pdata);
++
++ XGMAC_IOWRITE_BITS(pdata, MAC_RFCR, PFCE,
++ (pfc && pfc->pfc_en) ? 1 : 0);
++}
++
++static void xgbe_enable_dma_interrupts(struct xgbe_prv_data *pdata)
++{
++ struct xgbe_channel *channel;
++ unsigned int dma_ch_isr, dma_ch_ier;
++ unsigned int i;
++
++ channel = pdata->channel;
++ for (i = 0; i < pdata->channel_count; i++, channel++) {
++ /* Clear all the interrupts which are set */
++ dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
++ XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
++
++ /* Clear all interrupt enable bits */
++ dma_ch_ier = 0;
++
++ /* Enable following interrupts
++ * NIE - Normal Interrupt Summary Enable
++ * AIE - Abnormal Interrupt Summary Enable
++ * FBEE - Fatal Bus Error Enable
++ */
++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, NIE, 1);
++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, AIE, 1);
++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 1);
++
++ if (channel->tx_ring) {
++ /* Enable the following Tx interrupts
++ * TIE - Transmit Interrupt Enable (unless using
++ * per channel interrupts)
++ */
++ if (!pdata->per_channel_irq)
++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1);
++ }
++ if (channel->rx_ring) {
++ /* Enable following Rx interrupts
++ * RBUE - Receive Buffer Unavailable Enable
++ * RIE - Receive Interrupt Enable (unless using
++ * per channel interrupts)
++ */
++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 1);
++ if (!pdata->per_channel_irq)
++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1);
++ }
++
++ XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier);
++ }
++}
++
++static void xgbe_enable_mtl_interrupts(struct xgbe_prv_data *pdata)
++{
++ unsigned int mtl_q_isr;
++ unsigned int q_count, i;
++
++ q_count = max(pdata->hw_feat.tx_q_cnt, pdata->hw_feat.rx_q_cnt);
++ for (i = 0; i < q_count; i++) {
++ /* Clear all the interrupts which are set */
++ mtl_q_isr = XGMAC_MTL_IOREAD(pdata, i, MTL_Q_ISR);
++ XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_ISR, mtl_q_isr);
++
++ /* No MTL interrupts to be enabled */
++ XGMAC_MTL_IOWRITE(pdata, i, MTL_Q_IER, 0);
++ }
++}
++
++static void xgbe_enable_mac_interrupts(struct xgbe_prv_data *pdata)
++{
++ unsigned int mac_ier = 0;
++
++ /* Enable Timestamp interrupt */
++ XGMAC_SET_BITS(mac_ier, MAC_IER, TSIE, 1);
++
++ XGMAC_IOWRITE(pdata, MAC_IER, mac_ier);
++
++ /* Enable all counter interrupts */
++ XGMAC_IOWRITE_BITS(pdata, MMC_RIER, ALL_INTERRUPTS, 0xffffffff);
++ XGMAC_IOWRITE_BITS(pdata, MMC_TIER, ALL_INTERRUPTS, 0xffffffff);
++}
++
++static int xgbe_set_gmii_speed(struct xgbe_prv_data *pdata)
++{
++ if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) == 0x3)
++ return 0;
++
++ XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0x3);
++
++ return 0;
++}
++
++static int xgbe_set_gmii_2500_speed(struct xgbe_prv_data *pdata)
++{
++ if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) == 0x2)
++ return 0;
++
++ XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0x2);
++
++ return 0;
++}
++
++static int xgbe_set_xgmii_speed(struct xgbe_prv_data *pdata)
++{
++ if (XGMAC_IOREAD_BITS(pdata, MAC_TCR, SS) == 0)
++ return 0;
++
++ XGMAC_IOWRITE_BITS(pdata, MAC_TCR, SS, 0);
++
++ return 0;
++}
++
++static int xgbe_set_promiscuous_mode(struct xgbe_prv_data *pdata,
++ unsigned int enable)
++{
++ unsigned int val = enable ? 1 : 0;
++
++ if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PR) == val)
++ return 0;
++
++ DBGPR(" %s promiscuous mode\n", enable ? "entering" : "leaving");
++ XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PR, val);
++
++ return 0;
++}
++
++static int xgbe_set_all_multicast_mode(struct xgbe_prv_data *pdata,
++ unsigned int enable)
++{
++ unsigned int val = enable ? 1 : 0;
++
++ if (XGMAC_IOREAD_BITS(pdata, MAC_PFR, PM) == val)
++ return 0;
++
++ DBGPR(" %s allmulti mode\n", enable ? "entering" : "leaving");
++ XGMAC_IOWRITE_BITS(pdata, MAC_PFR, PM, val);
++
++ return 0;
++}
++
++static void xgbe_set_mac_reg(struct xgbe_prv_data *pdata,
++ struct netdev_hw_addr *ha, unsigned int *mac_reg)
++{
++ unsigned int mac_addr_hi, mac_addr_lo;
++ u8 *mac_addr;
++
++ mac_addr_lo = 0;
++ mac_addr_hi = 0;
++
++ if (ha) {
++ mac_addr = (u8 *)&mac_addr_lo;
++ mac_addr[0] = ha->addr[0];
++ mac_addr[1] = ha->addr[1];
++ mac_addr[2] = ha->addr[2];
++ mac_addr[3] = ha->addr[3];
++ mac_addr = (u8 *)&mac_addr_hi;
++ mac_addr[0] = ha->addr[4];
++ mac_addr[1] = ha->addr[5];
++
++ DBGPR(" adding mac address %pM at 0x%04x\n", ha->addr,
++ *mac_reg);
++
++ XGMAC_SET_BITS(mac_addr_hi, MAC_MACA1HR, AE, 1);
++ }
++
++ XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_hi);
++ *mac_reg += MAC_MACA_INC;
++ XGMAC_IOWRITE(pdata, *mac_reg, mac_addr_lo);
++ *mac_reg += MAC_MACA_INC;
++}
++
++static void xgbe_set_mac_addn_addrs(struct xgbe_prv_data *pdata)
++{
++ struct net_device *netdev = pdata->netdev;
++ struct netdev_hw_addr *ha;
++ unsigned int mac_reg;
++ unsigned int addn_macs;
++
++ mac_reg = MAC_MACA1HR;
++ addn_macs = pdata->hw_feat.addn_mac;
++
++ if (netdev_uc_count(netdev) > addn_macs) {
++ xgbe_set_promiscuous_mode(pdata, 1);
++ } else {
++ netdev_for_each_uc_addr(ha, netdev) {
++ xgbe_set_mac_reg(pdata, ha, &mac_reg);
++ addn_macs--;
++ }
++
++ if (netdev_mc_count(netdev) > addn_macs) {
++ xgbe_set_all_multicast_mode(pdata, 1);
++ } else {
++ netdev_for_each_mc_addr(ha, netdev) {
++ xgbe_set_mac_reg(pdata, ha, &mac_reg);
++ addn_macs--;
++ }
++ }
++ }
++
++ /* Clear remaining additional MAC address entries */
++ while (addn_macs--)
++ xgbe_set_mac_reg(pdata, NULL, &mac_reg);
++}
++
++static void xgbe_set_mac_hash_table(struct xgbe_prv_data *pdata)
++{
++ struct net_device *netdev = pdata->netdev;
++ struct netdev_hw_addr *ha;
++ unsigned int hash_reg;
++ unsigned int hash_table_shift, hash_table_count;
++ u32 hash_table[XGBE_MAC_HASH_TABLE_SIZE];
++ u32 crc;
++ unsigned int i;
++
++ hash_table_shift = 26 - (pdata->hw_feat.hash_table_size >> 7);
++ hash_table_count = pdata->hw_feat.hash_table_size / 32;
++ memset(hash_table, 0, sizeof(hash_table));
++
++ /* Build the MAC Hash Table register values */
++ netdev_for_each_uc_addr(ha, netdev) {
++ crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN));
++ crc >>= hash_table_shift;
++ hash_table[crc >> 5] |= (1 << (crc & 0x1f));
++ }
++
++ netdev_for_each_mc_addr(ha, netdev) {
++ crc = bitrev32(~crc32_le(~0, ha->addr, ETH_ALEN));
++ crc >>= hash_table_shift;
++ hash_table[crc >> 5] |= (1 << (crc & 0x1f));
++ }
++
++ /* Set the MAC Hash Table registers */
++ hash_reg = MAC_HTR0;
++ for (i = 0; i < hash_table_count; i++) {
++ XGMAC_IOWRITE(pdata, hash_reg, hash_table[i]);
++ hash_reg += MAC_HTR_INC;
++ }
++}
++
++static int xgbe_add_mac_addresses(struct xgbe_prv_data *pdata)
++{
++ if (pdata->hw_feat.hash_table_size)
++ xgbe_set_mac_hash_table(pdata);
++ else
++ xgbe_set_mac_addn_addrs(pdata);
++
++ return 0;
++}
++
++static int xgbe_set_mac_address(struct xgbe_prv_data *pdata, u8 *addr)
++{
++ unsigned int mac_addr_hi, mac_addr_lo;
++
++ mac_addr_hi = (addr[5] << 8) | (addr[4] << 0);
++ mac_addr_lo = (addr[3] << 24) | (addr[2] << 16) |
++ (addr[1] << 8) | (addr[0] << 0);
++
++ XGMAC_IOWRITE(pdata, MAC_MACA0HR, mac_addr_hi);
++ XGMAC_IOWRITE(pdata, MAC_MACA0LR, mac_addr_lo);
++
++ return 0;
++}
++
++static int xgbe_read_mmd_regs(struct xgbe_prv_data *pdata, int prtad,
++ int mmd_reg)
++{
++ unsigned int mmd_address;
++ int mmd_data;
++
++ if (mmd_reg & MII_ADDR_C45)
++ mmd_address = mmd_reg & ~MII_ADDR_C45;
++ else
++ mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
++
++ /* The PCS implementation has reversed the devices in
++ * package registers so we need to change 05 to 06 and
++ * 06 to 05 if being read (these registers are readonly
++ * so no need to do this in the write function)
++ */
++ if ((mmd_address & 0xffff) == 0x05)
++ mmd_address = (mmd_address & ~0xffff) | 0x06;
++ else if ((mmd_address & 0xffff) == 0x06)
++ mmd_address = (mmd_address & ~0xffff) | 0x05;
++
++ /* The PCS registers are accessed using mmio. The underlying APB3
++ * management interface uses indirect addressing to access the MMD
++ * register sets. This requires accessing of the PCS register in two
++ * phases, an address phase and a data phase.
++ *
++ * The mmio interface is based on 32-bit offsets and values. All
++ * register offsets must therefore be adjusted by left shifting the
++ * offset 2 bits and reading 32 bits of data.
++ */
++ mutex_lock(&pdata->xpcs_mutex);
++ XPCS_IOWRITE(pdata, PCS_MMD_SELECT << 2, mmd_address >> 8);
++ mmd_data = XPCS_IOREAD(pdata, (mmd_address & 0xff) << 2);
++ mutex_unlock(&pdata->xpcs_mutex);
++
++ return mmd_data;
++}
++
++static void xgbe_write_mmd_regs(struct xgbe_prv_data *pdata, int prtad,
++ int mmd_reg, int mmd_data)
++{
++ unsigned int mmd_address;
++
++ if (mmd_reg & MII_ADDR_C45)
++ mmd_address = mmd_reg & ~MII_ADDR_C45;
++ else
++ mmd_address = (pdata->mdio_mmd << 16) | (mmd_reg & 0xffff);
++
++ /* If the PCS is changing modes, match the MAC speed to it */
++ if (((mmd_address >> 16) == MDIO_MMD_PCS) &&
++ ((mmd_address & 0xffff) == MDIO_CTRL2)) {
++ struct phy_device *phydev = pdata->phydev;
++
++ if (mmd_data & MDIO_PCS_CTRL2_TYPE) {
++ /* KX mode */
++ if (phydev->supported & SUPPORTED_1000baseKX_Full)
++ xgbe_set_gmii_speed(pdata);
++ else
++ xgbe_set_gmii_2500_speed(pdata);
++ } else {
++ /* KR mode */
++ xgbe_set_xgmii_speed(pdata);
++ }
++ }
++
++ /* The PCS registers are accessed using mmio. The underlying APB3
++ * management interface uses indirect addressing to access the MMD
++ * register sets. This requires accessing of the PCS register in two
++ * phases, an address phase and a data phase.
++ *
++ * The mmio interface is based on 32-bit offsets and values. All
++ * register offsets must therefore be adjusted by left shifting the
++ * offset 2 bits and reading 32 bits of data.
++ */
++ mutex_lock(&pdata->xpcs_mutex);
++ XPCS_IOWRITE(pdata, PCS_MMD_SELECT << 2, mmd_address >> 8);
++ XPCS_IOWRITE(pdata, (mmd_address & 0xff) << 2, mmd_data);
++ mutex_unlock(&pdata->xpcs_mutex);
++}
++
++static int xgbe_tx_complete(struct xgbe_ring_desc *rdesc)
++{
++ return !XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN);
++}
++
++static int xgbe_disable_rx_csum(struct xgbe_prv_data *pdata)
++{
++ XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 0);
++
++ return 0;
++}
++
++static int xgbe_enable_rx_csum(struct xgbe_prv_data *pdata)
++{
++ XGMAC_IOWRITE_BITS(pdata, MAC_RCR, IPC, 1);
++
++ return 0;
++}
++
++static int xgbe_enable_rx_vlan_stripping(struct xgbe_prv_data *pdata)
++{
++ /* Put the VLAN tag in the Rx descriptor */
++ XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLRXS, 1);
++
++ /* Don't check the VLAN type */
++ XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, DOVLTC, 1);
++
++ /* Check only C-TAG (0x8100) packets */
++ XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ERSVLM, 0);
++
++ /* Don't consider an S-TAG (0x88A8) packet as a VLAN packet */
++ XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ESVL, 0);
++
++ /* Enable VLAN tag stripping */
++ XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0x3);
++
++ return 0;
++}
++
++static int xgbe_disable_rx_vlan_stripping(struct xgbe_prv_data *pdata)
++{
++ XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, EVLS, 0);
++
++ return 0;
++}
++
++static int xgbe_enable_rx_vlan_filtering(struct xgbe_prv_data *pdata)
++{
++ /* Enable VLAN filtering */
++ XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 1);
++
++ /* Enable VLAN Hash Table filtering */
++ XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTHM, 1);
++
++ /* Disable VLAN tag inverse matching */
++ XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VTIM, 0);
++
++ /* Only filter on the lower 12-bits of the VLAN tag */
++ XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, ETV, 1);
++
++ /* In order for the VLAN Hash Table filtering to be effective,
++ * the VLAN tag identifier in the VLAN Tag Register must not
++ * be zero. Set the VLAN tag identifier to "1" to enable the
++ * VLAN Hash Table filtering. This implies that a VLAN tag of
++ * 1 will always pass filtering.
++ */
++ XGMAC_IOWRITE_BITS(pdata, MAC_VLANTR, VL, 1);
++
++ return 0;
++}
++
++static int xgbe_disable_rx_vlan_filtering(struct xgbe_prv_data *pdata)
++{
++ /* Disable VLAN filtering */
++ XGMAC_IOWRITE_BITS(pdata, MAC_PFR, VTFE, 0);
++
++ return 0;
++}
++
++#ifndef CRCPOLY_LE
++#define CRCPOLY_LE 0xedb88320
++#endif
++static u32 xgbe_vid_crc32_le(__le16 vid_le)
++{
++ u32 poly = CRCPOLY_LE;
++ u32 crc = ~0;
++ u32 temp = 0;
++ unsigned char *data = (unsigned char *)&vid_le;
++ unsigned char data_byte = 0;
++ int i, bits;
++
++ bits = get_bitmask_order(VLAN_VID_MASK);
++ for (i = 0; i < bits; i++) {
++ if ((i % 8) == 0)
++ data_byte = data[i / 8];
++
++ temp = ((crc & 1) ^ data_byte) & 1;
++ crc >>= 1;
++ data_byte >>= 1;
++
++ if (temp)
++ crc ^= poly;
++ }
++
++ return crc;
++}
++
++static int xgbe_update_vlan_hash_table(struct xgbe_prv_data *pdata)
++{
++ u32 crc;
++ u16 vid;
++ __le16 vid_le;
++ u16 vlan_hash_table = 0;
++
++ /* Generate the VLAN Hash Table value */
++ for_each_set_bit(vid, pdata->active_vlans, VLAN_N_VID) {
++ /* Get the CRC32 value of the VLAN ID */
++ vid_le = cpu_to_le16(vid);
++ crc = bitrev32(~xgbe_vid_crc32_le(vid_le)) >> 28;
++
++ vlan_hash_table |= (1 << crc);
++ }
++
++ /* Set the VLAN Hash Table filtering register */
++ XGMAC_IOWRITE_BITS(pdata, MAC_VLANHTR, VLHT, vlan_hash_table);
++
++ return 0;
++}
++
++static void xgbe_tx_desc_reset(struct xgbe_ring_data *rdata)
++{
++ struct xgbe_ring_desc *rdesc = rdata->rdesc;
++
++ /* Reset the Tx descriptor
++ * Set buffer 1 (lo) address to zero
++ * Set buffer 1 (hi) address to zero
++ * Reset all other control bits (IC, TTSE, B2L & B1L)
++ * Reset all other control bits (OWN, CTXT, FD, LD, CPC, CIC, etc)
++ */
++ rdesc->desc0 = 0;
++ rdesc->desc1 = 0;
++ rdesc->desc2 = 0;
++ rdesc->desc3 = 0;
++
++ /* Make sure ownership is written to the descriptor */
++ wmb();
++}
++
++static void xgbe_tx_desc_init(struct xgbe_channel *channel)
++{
++ struct xgbe_ring *ring = channel->tx_ring;
++ struct xgbe_ring_data *rdata;
++ int i;
++ int start_index = ring->cur;
++
++ DBGPR("-->tx_desc_init\n");
++
++ /* Initialze all descriptors */
++ for (i = 0; i < ring->rdesc_count; i++) {
++ rdata = XGBE_GET_DESC_DATA(ring, i);
++
++ /* Initialize Tx descriptor */
++ xgbe_tx_desc_reset(rdata);
++ }
++
++ /* Update the total number of Tx descriptors */
++ XGMAC_DMA_IOWRITE(channel, DMA_CH_TDRLR, ring->rdesc_count - 1);
++
++ /* Update the starting address of descriptor ring */
++ rdata = XGBE_GET_DESC_DATA(ring, start_index);
++ XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_HI,
++ upper_32_bits(rdata->rdesc_dma));
++ XGMAC_DMA_IOWRITE(channel, DMA_CH_TDLR_LO,
++ lower_32_bits(rdata->rdesc_dma));
++
++ DBGPR("<--tx_desc_init\n");
++}
++
++static void xgbe_rx_desc_reset(struct xgbe_ring_data *rdata)
++{
++ struct xgbe_ring_desc *rdesc = rdata->rdesc;
++
++ /* Reset the Rx descriptor
++ * Set buffer 1 (lo) address to header dma address (lo)
++ * Set buffer 1 (hi) address to header dma address (hi)
++ * Set buffer 2 (lo) address to buffer dma address (lo)
++ * Set buffer 2 (hi) address to buffer dma address (hi) and
++ * set control bits OWN and INTE
++ */
++ rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->rx.hdr.dma));
++ rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->rx.hdr.dma));
++ rdesc->desc2 = cpu_to_le32(lower_32_bits(rdata->rx.buf.dma));
++ rdesc->desc3 = cpu_to_le32(upper_32_bits(rdata->rx.buf.dma));
++
++ XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, INTE,
++ rdata->interrupt ? 1 : 0);
++
++ /* Since the Rx DMA engine is likely running, make sure everything
++ * is written to the descriptor(s) before setting the OWN bit
++ * for the descriptor
++ */
++ wmb();
++
++ XGMAC_SET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN, 1);
++
++ /* Make sure ownership is written to the descriptor */
++ wmb();
++}
++
++static void xgbe_rx_desc_init(struct xgbe_channel *channel)
++{
++ struct xgbe_prv_data *pdata = channel->pdata;
++ struct xgbe_ring *ring = channel->rx_ring;
++ struct xgbe_ring_data *rdata;
++ unsigned int start_index = ring->cur;
++ unsigned int rx_coalesce, rx_frames;
++ unsigned int i;
++
++ DBGPR("-->rx_desc_init\n");
++
++ rx_coalesce = (pdata->rx_riwt || pdata->rx_frames) ? 1 : 0;
++ rx_frames = pdata->rx_frames;
++
++ /* Initialize all descriptors */
++ for (i = 0; i < ring->rdesc_count; i++) {
++ rdata = XGBE_GET_DESC_DATA(ring, i);
++
++ /* Set interrupt on completion bit as appropriate */
++ if (rx_coalesce && (!rx_frames || ((i + 1) % rx_frames)))
++ rdata->interrupt = 0;
++ else
++ rdata->interrupt = 1;
++
++ /* Initialize Rx descriptor */
++ xgbe_rx_desc_reset(rdata);
++ }
++
++ /* Update the total number of Rx descriptors */
++ XGMAC_DMA_IOWRITE(channel, DMA_CH_RDRLR, ring->rdesc_count - 1);
++
++ /* Update the starting address of descriptor ring */
++ rdata = XGBE_GET_DESC_DATA(ring, start_index);
++ XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_HI,
++ upper_32_bits(rdata->rdesc_dma));
++ XGMAC_DMA_IOWRITE(channel, DMA_CH_RDLR_LO,
++ lower_32_bits(rdata->rdesc_dma));
++
++ /* Update the Rx Descriptor Tail Pointer */
++ rdata = XGBE_GET_DESC_DATA(ring, start_index + ring->rdesc_count - 1);
++ XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO,
++ lower_32_bits(rdata->rdesc_dma));
++
++ DBGPR("<--rx_desc_init\n");
++}
++
++static void xgbe_update_tstamp_addend(struct xgbe_prv_data *pdata,
++ unsigned int addend)
++{
++ /* Set the addend register value and tell the device */
++ XGMAC_IOWRITE(pdata, MAC_TSAR, addend);
++ XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSADDREG, 1);
++
++ /* Wait for addend update to complete */
++ while (XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSADDREG))
++ udelay(5);
++}
++
++static void xgbe_set_tstamp_time(struct xgbe_prv_data *pdata, unsigned int sec,
++ unsigned int nsec)
++{
++ /* Set the time values and tell the device */
++ XGMAC_IOWRITE(pdata, MAC_STSUR, sec);
++ XGMAC_IOWRITE(pdata, MAC_STNUR, nsec);
++ XGMAC_IOWRITE_BITS(pdata, MAC_TSCR, TSINIT, 1);
++
++ /* Wait for time update to complete */
++ while (XGMAC_IOREAD_BITS(pdata, MAC_TSCR, TSINIT))
++ udelay(5);
++}
++
++static u64 xgbe_get_tstamp_time(struct xgbe_prv_data *pdata)
++{
++ u64 nsec;
++
++ nsec = XGMAC_IOREAD(pdata, MAC_STSR);
++ nsec *= NSEC_PER_SEC;
++ nsec += XGMAC_IOREAD(pdata, MAC_STNR);
++
++ return nsec;
++}
++
++static u64 xgbe_get_tx_tstamp(struct xgbe_prv_data *pdata)
++{
++ unsigned int tx_snr;
++ u64 nsec;
++
++ tx_snr = XGMAC_IOREAD(pdata, MAC_TXSNR);
++ if (XGMAC_GET_BITS(tx_snr, MAC_TXSNR, TXTSSTSMIS))
++ return 0;
++
++ nsec = XGMAC_IOREAD(pdata, MAC_TXSSR);
++ nsec *= NSEC_PER_SEC;
++ nsec += tx_snr;
++
++ return nsec;
++}
++
++static void xgbe_get_rx_tstamp(struct xgbe_packet_data *packet,
++ struct xgbe_ring_desc *rdesc)
++{
++ u64 nsec;
++
++ if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSA) &&
++ !XGMAC_GET_BITS_LE(rdesc->desc3, RX_CONTEXT_DESC3, TSD)) {
++ nsec = le32_to_cpu(rdesc->desc1);
++ nsec <<= 32;
++ nsec |= le32_to_cpu(rdesc->desc0);
++ if (nsec != 0xffffffffffffffffULL) {
++ packet->rx_tstamp = nsec;
++ XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
++ RX_TSTAMP, 1);
++ }
++ }
++}
++
++static int xgbe_config_tstamp(struct xgbe_prv_data *pdata,
++ unsigned int mac_tscr)
++{
++ /* Set one nano-second accuracy */
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCTRLSSR, 1);
++
++ /* Set fine timestamp update */
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSCFUPDT, 1);
++
++ /* Overwrite earlier timestamps */
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TXTSSTSM, 1);
++
++ XGMAC_IOWRITE(pdata, MAC_TSCR, mac_tscr);
++
++ /* Exit if timestamping is not enabled */
++ if (!XGMAC_GET_BITS(mac_tscr, MAC_TSCR, TSENA))
++ return 0;
++
++ /* Initialize time registers */
++ XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SSINC, XGBE_TSTAMP_SSINC);
++ XGMAC_IOWRITE_BITS(pdata, MAC_SSIR, SNSINC, XGBE_TSTAMP_SNSINC);
++ xgbe_update_tstamp_addend(pdata, pdata->tstamp_addend);
++ xgbe_set_tstamp_time(pdata, 0, 0);
++
++ /* Initialize the timecounter */
++ timecounter_init(&pdata->tstamp_tc, &pdata->tstamp_cc,
++ ktime_to_ns(ktime_get_real()));
++
++ return 0;
++}
++
++static void xgbe_config_dcb_tc(struct xgbe_prv_data *pdata)
++{
++ struct ieee_ets *ets = pdata->ets;
++ unsigned int total_weight, min_weight, weight;
++ unsigned int i;
++
++ if (!ets)
++ return;
++
++ /* Set Tx to deficit weighted round robin scheduling algorithm (when
++ * traffic class is using ETS algorithm)
++ */
++ XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_DWRR);
++
++ /* Set Traffic Class algorithms */
++ total_weight = pdata->netdev->mtu * pdata->hw_feat.tc_cnt;
++ min_weight = total_weight / 100;
++ if (!min_weight)
++ min_weight = 1;
++
++ for (i = 0; i < pdata->hw_feat.tc_cnt; i++) {
++ switch (ets->tc_tsa[i]) {
++ case IEEE_8021QAZ_TSA_STRICT:
++ DBGPR(" TC%u using SP\n", i);
++ XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
++ MTL_TSA_SP);
++ break;
++ case IEEE_8021QAZ_TSA_ETS:
++ weight = total_weight * ets->tc_tx_bw[i] / 100;
++ weight = clamp(weight, min_weight, total_weight);
++
++ DBGPR(" TC%u using DWRR (weight %u)\n", i, weight);
++ XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
++ MTL_TSA_ETS);
++ XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW,
++ weight);
++ break;
++ }
++ }
++}
++
++static void xgbe_config_dcb_pfc(struct xgbe_prv_data *pdata)
++{
++ struct ieee_pfc *pfc = pdata->pfc;
++ struct ieee_ets *ets = pdata->ets;
++ unsigned int mask, reg, reg_val;
++ unsigned int tc, prio;
++
++ if (!pfc || !ets)
++ return;
++
++ for (tc = 0; tc < pdata->hw_feat.tc_cnt; tc++) {
++ mask = 0;
++ for (prio = 0; prio < IEEE_8021QAZ_MAX_TCS; prio++) {
++ if ((pfc->pfc_en & (1 << prio)) &&
++ (ets->prio_tc[prio] == tc))
++ mask |= (1 << prio);
++ }
++ mask &= 0xff;
++
++ DBGPR(" TC%u PFC mask=%#x\n", tc, mask);
++ reg = MTL_TCPM0R + (MTL_TCPM_INC * (tc / MTL_TCPM_TC_PER_REG));
++ reg_val = XGMAC_IOREAD(pdata, reg);
++
++ reg_val &= ~(0xff << ((tc % MTL_TCPM_TC_PER_REG) << 3));
++ reg_val |= (mask << ((tc % MTL_TCPM_TC_PER_REG) << 3));
++
++ XGMAC_IOWRITE(pdata, reg, reg_val);
++ }
++
++ xgbe_config_flow_control(pdata);
++}
++
++static void xgbe_tx_start_xmit(struct xgbe_channel *channel,
++ struct xgbe_ring *ring)
++{
++ struct xgbe_prv_data *pdata = channel->pdata;
++ struct xgbe_ring_data *rdata;
++
++ /* Issue a poll command to Tx DMA by writing address
++ * of next immediate free descriptor */
++ rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
++ XGMAC_DMA_IOWRITE(channel, DMA_CH_TDTR_LO,
++ lower_32_bits(rdata->rdesc_dma));
++
++ /* Start the Tx coalescing timer */
++ if (pdata->tx_usecs && !channel->tx_timer_active) {
++ channel->tx_timer_active = 1;
++ hrtimer_start(&channel->tx_timer,
++ ktime_set(0, pdata->tx_usecs * NSEC_PER_USEC),
++ HRTIMER_MODE_REL);
++ }
++
++ ring->tx.xmit_more = 0;
++}
++
++static void xgbe_dev_xmit(struct xgbe_channel *channel)
++{
++ struct xgbe_prv_data *pdata = channel->pdata;
++ struct xgbe_ring *ring = channel->tx_ring;
++ struct xgbe_ring_data *rdata;
++ struct xgbe_ring_desc *rdesc;
++ struct xgbe_packet_data *packet = &ring->packet_data;
++ unsigned int csum, tso, vlan;
++ unsigned int tso_context, vlan_context;
++ unsigned int tx_set_ic;
++ int start_index = ring->cur;
++ int cur_index = ring->cur;
++ int i;
++
++ DBGPR("-->xgbe_dev_xmit\n");
++
++ csum = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
++ CSUM_ENABLE);
++ tso = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
++ TSO_ENABLE);
++ vlan = XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
++ VLAN_CTAG);
++
++ if (tso && (packet->mss != ring->tx.cur_mss))
++ tso_context = 1;
++ else
++ tso_context = 0;
++
++ if (vlan && (packet->vlan_ctag != ring->tx.cur_vlan_ctag))
++ vlan_context = 1;
++ else
++ vlan_context = 0;
++
++ /* Determine if an interrupt should be generated for this Tx:
++ * Interrupt:
++ * - Tx frame count exceeds the frame count setting
++ * - Addition of Tx frame count to the frame count since the
++ * last interrupt was set exceeds the frame count setting
++ * No interrupt:
++ * - No frame count setting specified (ethtool -C ethX tx-frames 0)
++ * - Addition of Tx frame count to the frame count since the
++ * last interrupt was set does not exceed the frame count setting
++ */
++ ring->coalesce_count += packet->tx_packets;
++ if (!pdata->tx_frames)
++ tx_set_ic = 0;
++ else if (packet->tx_packets > pdata->tx_frames)
++ tx_set_ic = 1;
++ else if ((ring->coalesce_count % pdata->tx_frames) <
++ packet->tx_packets)
++ tx_set_ic = 1;
++ else
++ tx_set_ic = 0;
++
++ rdata = XGBE_GET_DESC_DATA(ring, cur_index);
++ rdesc = rdata->rdesc;
++
++ /* Create a context descriptor if this is a TSO packet */
++ if (tso_context || vlan_context) {
++ if (tso_context) {
++ DBGPR(" TSO context descriptor, mss=%u\n",
++ packet->mss);
++
++ /* Set the MSS size */
++ XGMAC_SET_BITS_LE(rdesc->desc2, TX_CONTEXT_DESC2,
++ MSS, packet->mss);
++
++ /* Mark it as a CONTEXT descriptor */
++ XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
++ CTXT, 1);
++
++ /* Indicate this descriptor contains the MSS */
++ XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
++ TCMSSV, 1);
++
++ ring->tx.cur_mss = packet->mss;
++ }
++
++ if (vlan_context) {
++ DBGPR(" VLAN context descriptor, ctag=%u\n",
++ packet->vlan_ctag);
++
++ /* Mark it as a CONTEXT descriptor */
++ XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
++ CTXT, 1);
++
++ /* Set the VLAN tag */
++ XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
++ VT, packet->vlan_ctag);
++
++ /* Indicate this descriptor contains the VLAN tag */
++ XGMAC_SET_BITS_LE(rdesc->desc3, TX_CONTEXT_DESC3,
++ VLTV, 1);
++
++ ring->tx.cur_vlan_ctag = packet->vlan_ctag;
++ }
++
++ cur_index++;
++ rdata = XGBE_GET_DESC_DATA(ring, cur_index);
++ rdesc = rdata->rdesc;
++ }
++
++ /* Update buffer address (for TSO this is the header) */
++ rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma));
++ rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma));
++
++ /* Update the buffer length */
++ XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L,
++ rdata->skb_dma_len);
++
++ /* VLAN tag insertion check */
++ if (vlan)
++ XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, VTIR,
++ TX_NORMAL_DESC2_VLAN_INSERT);
++
++ /* Timestamp enablement check */
++ if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP))
++ XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, TTSE, 1);
++
++ /* Mark it as First Descriptor */
++ XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FD, 1);
++
++ /* Mark it as a NORMAL descriptor */
++ XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0);
++
++ /* Set OWN bit if not the first descriptor */
++ if (cur_index != start_index)
++ XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
++
++ if (tso) {
++ /* Enable TSO */
++ XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TSE, 1);
++ XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPPL,
++ packet->tcp_payload_len);
++ XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, TCPHDRLEN,
++ packet->tcp_header_len / 4);
++ } else {
++ /* Enable CRC and Pad Insertion */
++ XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CPC, 0);
++
++ /* Enable HW CSUM */
++ if (csum)
++ XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3,
++ CIC, 0x3);
++
++ /* Set the total length to be transmitted */
++ XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, FL,
++ packet->length);
++ }
++
++ for (i = cur_index - start_index + 1; i < packet->rdesc_count; i++) {
++ cur_index++;
++ rdata = XGBE_GET_DESC_DATA(ring, cur_index);
++ rdesc = rdata->rdesc;
++
++ /* Update buffer address */
++ rdesc->desc0 = cpu_to_le32(lower_32_bits(rdata->skb_dma));
++ rdesc->desc1 = cpu_to_le32(upper_32_bits(rdata->skb_dma));
++
++ /* Update the buffer length */
++ XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, HL_B1L,
++ rdata->skb_dma_len);
++
++ /* Set OWN bit */
++ XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
++
++ /* Mark it as NORMAL descriptor */
++ XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT, 0);
++
++ /* Enable HW CSUM */
++ if (csum)
++ XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3,
++ CIC, 0x3);
++ }
++
++ /* Set LAST bit for the last descriptor */
++ XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD, 1);
++
++ /* Set IC bit based on Tx coalescing settings */
++ if (tx_set_ic)
++ XGMAC_SET_BITS_LE(rdesc->desc2, TX_NORMAL_DESC2, IC, 1);
++
++ /* Save the Tx info to report back during cleanup */
++ rdata->tx.packets = packet->tx_packets;
++ rdata->tx.bytes = packet->tx_bytes;
++
++ /* In case the Tx DMA engine is running, make sure everything
++ * is written to the descriptor(s) before setting the OWN bit
++ * for the first descriptor
++ */
++ wmb();
++
++ /* Set OWN bit for the first descriptor */
++ rdata = XGBE_GET_DESC_DATA(ring, start_index);
++ rdesc = rdata->rdesc;
++ XGMAC_SET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, OWN, 1);
++
++#ifdef XGMAC_ENABLE_TX_DESC_DUMP
++ xgbe_a0_dump_tx_desc(ring, start_index, packet->rdesc_count, 1);
++#endif
++
++ /* Make sure ownership is written to the descriptor */
++ wmb();
++
++ ring->cur = cur_index + 1;
++ if (!packet->skb->xmit_more ||
++ netif_xmit_stopped(netdev_get_tx_queue(pdata->netdev,
++ channel->queue_index)))
++ xgbe_tx_start_xmit(channel, ring);
++ else
++ ring->tx.xmit_more = 1;
++
++ DBGPR(" %s: descriptors %u to %u written\n",
++ channel->name, start_index & (ring->rdesc_count - 1),
++ (ring->cur - 1) & (ring->rdesc_count - 1));
++
++ DBGPR("<--xgbe_dev_xmit\n");
++}
++
++static int xgbe_dev_read(struct xgbe_channel *channel)
++{
++ struct xgbe_ring *ring = channel->rx_ring;
++ struct xgbe_ring_data *rdata;
++ struct xgbe_ring_desc *rdesc;
++ struct xgbe_packet_data *packet = &ring->packet_data;
++ struct net_device *netdev = channel->pdata->netdev;
++ unsigned int err, etlt, l34t;
++
++ DBGPR("-->xgbe_dev_read: cur = %d\n", ring->cur);
++
++ rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
++ rdesc = rdata->rdesc;
++
++ /* Check for data availability */
++ if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, OWN))
++ return 1;
++
++ /* Make sure descriptor fields are read after reading the OWN bit */
++ rmb();
++
++#ifdef XGMAC_ENABLE_RX_DESC_DUMP
++ xgbe_a0_dump_rx_desc(ring, rdesc, ring->cur);
++#endif
++
++ if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CTXT)) {
++ /* Timestamp Context Descriptor */
++ xgbe_get_rx_tstamp(packet, rdesc);
++
++ XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
++ CONTEXT, 1);
++ XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
++ CONTEXT_NEXT, 0);
++ return 0;
++ }
++
++ /* Normal Descriptor, be sure Context Descriptor bit is off */
++ XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, CONTEXT, 0);
++
++ /* Indicate if a Context Descriptor is next */
++ if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, CDA))
++ XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
++ CONTEXT_NEXT, 1);
++
++ /* Get the header length */
++ if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, FD))
++ rdata->rx.hdr_len = XGMAC_GET_BITS_LE(rdesc->desc2,
++ RX_NORMAL_DESC2, HL);
++
++ /* Get the RSS hash */
++ if (XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, RSV)) {
++ XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
++ RSS_HASH, 1);
++
++ packet->rss_hash = le32_to_cpu(rdesc->desc1);
++
++ l34t = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, L34T);
++ switch (l34t) {
++ case RX_DESC3_L34T_IPV4_TCP:
++ case RX_DESC3_L34T_IPV4_UDP:
++ case RX_DESC3_L34T_IPV6_TCP:
++ case RX_DESC3_L34T_IPV6_UDP:
++ packet->rss_hash_type = PKT_HASH_TYPE_L4;
++ break;
++ default:
++ packet->rss_hash_type = PKT_HASH_TYPE_L3;
++ }
++ }
++
++ /* Get the packet length */
++ rdata->rx.len = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, PL);
++
++ if (!XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, LD)) {
++ /* Not all the data has been transferred for this packet */
++ XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
++ INCOMPLETE, 1);
++ return 0;
++ }
++
++ /* This is the last of the data for this packet */
++ XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
++ INCOMPLETE, 0);
++
++ /* Set checksum done indicator as appropriate */
++ if (channel->pdata->netdev->features & NETIF_F_RXCSUM)
++ XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
++ CSUM_DONE, 1);
++
++ /* Check for errors (only valid in last descriptor) */
++ err = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ES);
++ etlt = XGMAC_GET_BITS_LE(rdesc->desc3, RX_NORMAL_DESC3, ETLT);
++ DBGPR(" err=%u, etlt=%#x\n", err, etlt);
++
++ if (!err || !etlt) {
++ /* No error if err is 0 or etlt is 0 */
++ if ((etlt == 0x09) &&
++ (netdev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
++ XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
++ VLAN_CTAG, 1);
++ packet->vlan_ctag = XGMAC_GET_BITS_LE(rdesc->desc0,
++ RX_NORMAL_DESC0,
++ OVT);
++ DBGPR(" vlan-ctag=0x%04x\n", packet->vlan_ctag);
++ }
++ } else {
++ if ((etlt == 0x05) || (etlt == 0x06))
++ XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
++ CSUM_DONE, 0);
++ else
++ XGMAC_SET_BITS(packet->errors, RX_PACKET_ERRORS,
++ FRAME, 1);
++ }
++
++ DBGPR("<--xgbe_dev_read: %s - descriptor=%u (cur=%d)\n", channel->name,
++ ring->cur & (ring->rdesc_count - 1), ring->cur);
++
++ return 0;
++}
++
++static int xgbe_is_context_desc(struct xgbe_ring_desc *rdesc)
++{
++ /* Rx and Tx share CTXT bit, so check TDES3.CTXT bit */
++ return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, CTXT);
++}
++
++static int xgbe_is_last_desc(struct xgbe_ring_desc *rdesc)
++{
++ /* Rx and Tx share LD bit, so check TDES3.LD bit */
++ return XGMAC_GET_BITS_LE(rdesc->desc3, TX_NORMAL_DESC3, LD);
++}
++
++static int xgbe_enable_int(struct xgbe_channel *channel,
++ enum xgbe_int int_id)
++{
++ unsigned int dma_ch_ier;
++
++ dma_ch_ier = XGMAC_DMA_IOREAD(channel, DMA_CH_IER);
++
++ switch (int_id) {
++ case XGMAC_INT_DMA_CH_SR_TI:
++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1);
++ break;
++ case XGMAC_INT_DMA_CH_SR_TPS:
++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TXSE, 1);
++ break;
++ case XGMAC_INT_DMA_CH_SR_TBU:
++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TBUE, 1);
++ break;
++ case XGMAC_INT_DMA_CH_SR_RI:
++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1);
++ break;
++ case XGMAC_INT_DMA_CH_SR_RBU:
++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 1);
++ break;
++ case XGMAC_INT_DMA_CH_SR_RPS:
++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RSE, 1);
++ break;
++ case XGMAC_INT_DMA_CH_SR_TI_RI:
++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 1);
++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 1);
++ break;
++ case XGMAC_INT_DMA_CH_SR_FBE:
++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 1);
++ break;
++ case XGMAC_INT_DMA_ALL:
++ dma_ch_ier |= channel->saved_ier;
++ break;
++ default:
++ return -1;
++ }
++
++ XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier);
++
++ return 0;
++}
++
++static int xgbe_disable_int(struct xgbe_channel *channel,
++ enum xgbe_int int_id)
++{
++ unsigned int dma_ch_ier;
++
++ dma_ch_ier = XGMAC_DMA_IOREAD(channel, DMA_CH_IER);
++
++ switch (int_id) {
++ case XGMAC_INT_DMA_CH_SR_TI:
++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 0);
++ break;
++ case XGMAC_INT_DMA_CH_SR_TPS:
++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TXSE, 0);
++ break;
++ case XGMAC_INT_DMA_CH_SR_TBU:
++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TBUE, 0);
++ break;
++ case XGMAC_INT_DMA_CH_SR_RI:
++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 0);
++ break;
++ case XGMAC_INT_DMA_CH_SR_RBU:
++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RBUE, 0);
++ break;
++ case XGMAC_INT_DMA_CH_SR_RPS:
++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RSE, 0);
++ break;
++ case XGMAC_INT_DMA_CH_SR_TI_RI:
++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, TIE, 0);
++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, RIE, 0);
++ break;
++ case XGMAC_INT_DMA_CH_SR_FBE:
++ XGMAC_SET_BITS(dma_ch_ier, DMA_CH_IER, FBEE, 0);
++ break;
++ case XGMAC_INT_DMA_ALL:
++ channel->saved_ier = dma_ch_ier & XGBE_DMA_INTERRUPT_MASK;
++ dma_ch_ier &= ~XGBE_DMA_INTERRUPT_MASK;
++ break;
++ default:
++ return -1;
++ }
++
++ XGMAC_DMA_IOWRITE(channel, DMA_CH_IER, dma_ch_ier);
++
++ return 0;
++}
++
++static int xgbe_exit(struct xgbe_prv_data *pdata)
++{
++ unsigned int count = 2000;
++
++ DBGPR("-->xgbe_exit\n");
++
++ /* Issue a software reset */
++ XGMAC_IOWRITE_BITS(pdata, DMA_MR, SWR, 1);
++ usleep_range(10, 15);
++
++ /* Poll Until Poll Condition */
++ while (count-- && XGMAC_IOREAD_BITS(pdata, DMA_MR, SWR))
++ usleep_range(500, 600);
++
++ if (!count)
++ return -EBUSY;
++
++ DBGPR("<--xgbe_exit\n");
++
++ return 0;
++}
++
++static int xgbe_flush_tx_queues(struct xgbe_prv_data *pdata)
++{
++ unsigned int i, count;
++
++ if (XGMAC_GET_BITS(pdata->hw_feat.version, MAC_VR, SNPSVER) < 0x21)
++ return 0;
++
++ for (i = 0; i < pdata->tx_q_count; i++)
++ XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, FTQ, 1);
++
++ /* Poll Until Poll Condition */
++ for (i = 0; i < pdata->tx_q_count; i++) {
++ count = 2000;
++ while (count-- && XGMAC_MTL_IOREAD_BITS(pdata, i,
++ MTL_Q_TQOMR, FTQ))
++ usleep_range(500, 600);
++
++ if (!count)
++ return -EBUSY;
++ }
++
++ return 0;
++}
++
++static void xgbe_config_dma_bus(struct xgbe_prv_data *pdata)
++{
++ /* Set enhanced addressing mode */
++ XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, EAME, 1);
++
++ /* Set the System Bus mode */
++ XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, UNDEF, 1);
++ XGMAC_IOWRITE_BITS(pdata, DMA_SBMR, BLEN_256, 1);
++}
++
++static void xgbe_config_dma_cache(struct xgbe_prv_data *pdata)
++{
++ unsigned int arcache, awcache;
++
++ arcache = 0;
++ XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRC, pdata->arcache);
++ XGMAC_SET_BITS(arcache, DMA_AXIARCR, DRD, pdata->axdomain);
++ XGMAC_SET_BITS(arcache, DMA_AXIARCR, TEC, pdata->arcache);
++ XGMAC_SET_BITS(arcache, DMA_AXIARCR, TED, pdata->axdomain);
++ XGMAC_SET_BITS(arcache, DMA_AXIARCR, THC, pdata->arcache);
++ XGMAC_SET_BITS(arcache, DMA_AXIARCR, THD, pdata->axdomain);
++ XGMAC_IOWRITE(pdata, DMA_AXIARCR, arcache);
++
++ awcache = 0;
++ XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWC, pdata->awcache);
++ XGMAC_SET_BITS(awcache, DMA_AXIAWCR, DWD, pdata->axdomain);
++ XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPC, pdata->awcache);
++ XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RPD, pdata->axdomain);
++ XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHC, pdata->awcache);
++ XGMAC_SET_BITS(awcache, DMA_AXIAWCR, RHD, pdata->axdomain);
++ XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDC, pdata->awcache);
++ XGMAC_SET_BITS(awcache, DMA_AXIAWCR, TDD, pdata->axdomain);
++ XGMAC_IOWRITE(pdata, DMA_AXIAWCR, awcache);
++}
++
++static void xgbe_config_mtl_mode(struct xgbe_prv_data *pdata)
++{
++ unsigned int i;
++
++ /* Set Tx to weighted round robin scheduling algorithm */
++ XGMAC_IOWRITE_BITS(pdata, MTL_OMR, ETSALG, MTL_ETSALG_WRR);
++
++ /* Set Tx traffic classes to use WRR algorithm with equal weights */
++ for (i = 0; i < pdata->hw_feat.tc_cnt; i++) {
++ XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_ETSCR, TSA,
++ MTL_TSA_ETS);
++ XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_TC_QWR, QW, 1);
++ }
++
++ /* Set Rx to strict priority algorithm */
++ XGMAC_IOWRITE_BITS(pdata, MTL_OMR, RAA, MTL_RAA_SP);
++}
++
++static unsigned int xgbe_calculate_per_queue_fifo(unsigned int fifo_size,
++ unsigned int queue_count)
++{
++ unsigned int q_fifo_size = 0;
++ enum xgbe_mtl_fifo_size p_fifo = XGMAC_MTL_FIFO_SIZE_256;
++
++ /* Calculate Tx/Rx fifo share per queue */
++ switch (fifo_size) {
++ case 0:
++ q_fifo_size = XGBE_FIFO_SIZE_B(128);
++ break;
++ case 1:
++ q_fifo_size = XGBE_FIFO_SIZE_B(256);
++ break;
++ case 2:
++ q_fifo_size = XGBE_FIFO_SIZE_B(512);
++ break;
++ case 3:
++ q_fifo_size = XGBE_FIFO_SIZE_KB(1);
++ break;
++ case 4:
++ q_fifo_size = XGBE_FIFO_SIZE_KB(2);
++ break;
++ case 5:
++ q_fifo_size = XGBE_FIFO_SIZE_KB(4);
++ break;
++ case 6:
++ q_fifo_size = XGBE_FIFO_SIZE_KB(8);
++ break;
++ case 7:
++ q_fifo_size = XGBE_FIFO_SIZE_KB(16);
++ break;
++ case 8:
++ q_fifo_size = XGBE_FIFO_SIZE_KB(32);
++ break;
++ case 9:
++ q_fifo_size = XGBE_FIFO_SIZE_KB(64);
++ break;
++ case 10:
++ q_fifo_size = XGBE_FIFO_SIZE_KB(128);
++ break;
++ case 11:
++ q_fifo_size = XGBE_FIFO_SIZE_KB(256);
++ break;
++ }
++
++ /* The configured value is not the actual amount of fifo RAM */
++ q_fifo_size = min_t(unsigned int, XGBE_FIFO_MAX, q_fifo_size);
++
++ q_fifo_size = q_fifo_size / queue_count;
++
++ /* Set the queue fifo size programmable value */
++ if (q_fifo_size >= XGBE_FIFO_SIZE_KB(256))
++ p_fifo = XGMAC_MTL_FIFO_SIZE_256K;
++ else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(128))
++ p_fifo = XGMAC_MTL_FIFO_SIZE_128K;
++ else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(64))
++ p_fifo = XGMAC_MTL_FIFO_SIZE_64K;
++ else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(32))
++ p_fifo = XGMAC_MTL_FIFO_SIZE_32K;
++ else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(16))
++ p_fifo = XGMAC_MTL_FIFO_SIZE_16K;
++ else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(8))
++ p_fifo = XGMAC_MTL_FIFO_SIZE_8K;
++ else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(4))
++ p_fifo = XGMAC_MTL_FIFO_SIZE_4K;
++ else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(2))
++ p_fifo = XGMAC_MTL_FIFO_SIZE_2K;
++ else if (q_fifo_size >= XGBE_FIFO_SIZE_KB(1))
++ p_fifo = XGMAC_MTL_FIFO_SIZE_1K;
++ else if (q_fifo_size >= XGBE_FIFO_SIZE_B(512))
++ p_fifo = XGMAC_MTL_FIFO_SIZE_512;
++ else if (q_fifo_size >= XGBE_FIFO_SIZE_B(256))
++ p_fifo = XGMAC_MTL_FIFO_SIZE_256;
++
++ return p_fifo;
++}
++
++static void xgbe_config_tx_fifo_size(struct xgbe_prv_data *pdata)
++{
++ enum xgbe_mtl_fifo_size fifo_size;
++ unsigned int i;
++
++ fifo_size = xgbe_calculate_per_queue_fifo(pdata->hw_feat.tx_fifo_size,
++ pdata->tx_q_count);
++
++ for (i = 0; i < pdata->tx_q_count; i++)
++ XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TQS, fifo_size);
++
++ netdev_notice(pdata->netdev, "%d Tx queues, %d byte fifo per queue\n",
++ pdata->tx_q_count, ((fifo_size + 1) * 256));
++}
++
++static void xgbe_config_rx_fifo_size(struct xgbe_prv_data *pdata)
++{
++ enum xgbe_mtl_fifo_size fifo_size;
++ unsigned int i;
++
++ fifo_size = xgbe_calculate_per_queue_fifo(pdata->hw_feat.rx_fifo_size,
++ pdata->rx_q_count);
++
++ for (i = 0; i < pdata->rx_q_count; i++)
++ XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RQS, fifo_size);
++
++ netdev_notice(pdata->netdev, "%d Rx queues, %d byte fifo per queue\n",
++ pdata->rx_q_count, ((fifo_size + 1) * 256));
++}
++
++static void xgbe_config_queue_mapping(struct xgbe_prv_data *pdata)
++{
++ unsigned int qptc, qptc_extra, queue;
++ unsigned int prio_queues;
++ unsigned int ppq, ppq_extra, prio;
++ unsigned int mask;
++ unsigned int i, j, reg, reg_val;
++
++ /* Map the MTL Tx Queues to Traffic Classes
++ * Note: Tx Queues >= Traffic Classes
++ */
++ qptc = pdata->tx_q_count / pdata->hw_feat.tc_cnt;
++ qptc_extra = pdata->tx_q_count % pdata->hw_feat.tc_cnt;
++
++ for (i = 0, queue = 0; i < pdata->hw_feat.tc_cnt; i++) {
++ for (j = 0; j < qptc; j++) {
++ DBGPR(" TXq%u mapped to TC%u\n", queue, i);
++ XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR,
++ Q2TCMAP, i);
++ pdata->q2tc_map[queue++] = i;
++ }
++
++ if (i < qptc_extra) {
++ DBGPR(" TXq%u mapped to TC%u\n", queue, i);
++ XGMAC_MTL_IOWRITE_BITS(pdata, queue, MTL_Q_TQOMR,
++ Q2TCMAP, i);
++ pdata->q2tc_map[queue++] = i;
++ }
++ }
++
++ /* Map the 8 VLAN priority values to available MTL Rx queues */
++ prio_queues = min_t(unsigned int, IEEE_8021QAZ_MAX_TCS,
++ pdata->rx_q_count);
++ ppq = IEEE_8021QAZ_MAX_TCS / prio_queues;
++ ppq_extra = IEEE_8021QAZ_MAX_TCS % prio_queues;
++
++ reg = MAC_RQC2R;
++ reg_val = 0;
++ for (i = 0, prio = 0; i < prio_queues;) {
++ mask = 0;
++ for (j = 0; j < ppq; j++) {
++ DBGPR(" PRIO%u mapped to RXq%u\n", prio, i);
++ mask |= (1 << prio);
++ pdata->prio2q_map[prio++] = i;
++ }
++
++ if (i < ppq_extra) {
++ DBGPR(" PRIO%u mapped to RXq%u\n", prio, i);
++ mask |= (1 << prio);
++ pdata->prio2q_map[prio++] = i;
++ }
++
++ reg_val |= (mask << ((i++ % MAC_RQC2_Q_PER_REG) << 3));
++
++ if ((i % MAC_RQC2_Q_PER_REG) && (i != prio_queues))
++ continue;
++
++ XGMAC_IOWRITE(pdata, reg, reg_val);
++ reg += MAC_RQC2_INC;
++ reg_val = 0;
++ }
++
++ /* Select dynamic mapping of MTL Rx queue to DMA Rx channel */
++ reg = MTL_RQDCM0R;
++ reg_val = 0;
++ for (i = 0; i < pdata->rx_q_count;) {
++ reg_val |= (0x80 << ((i++ % MTL_RQDCM_Q_PER_REG) << 3));
++
++ if ((i % MTL_RQDCM_Q_PER_REG) && (i != pdata->rx_q_count))
++ continue;
++
++ XGMAC_IOWRITE(pdata, reg, reg_val);
++
++ reg += MTL_RQDCM_INC;
++ reg_val = 0;
++ }
++}
++
++static void xgbe_config_flow_control_threshold(struct xgbe_prv_data *pdata)
++{
++ unsigned int i;
++
++ for (i = 0; i < pdata->rx_q_count; i++) {
++ /* Activate flow control when less than 4k left in fifo */
++ XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RFA, 2);
++
++ /* De-activate flow control when more than 6k left in fifo */
++ XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_RQOMR, RFD, 4);
++ }
++}
++
++static void xgbe_config_mac_address(struct xgbe_prv_data *pdata)
++{
++ xgbe_set_mac_address(pdata, pdata->netdev->dev_addr);
++
++ /* Filtering is done using perfect filtering and hash filtering */
++ if (pdata->hw_feat.hash_table_size) {
++ XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HPF, 1);
++ XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HUC, 1);
++ XGMAC_IOWRITE_BITS(pdata, MAC_PFR, HMC, 1);
++ }
++}
++
++static void xgbe_config_jumbo_enable(struct xgbe_prv_data *pdata)
++{
++ unsigned int val;
++
++ val = (pdata->netdev->mtu > XGMAC_STD_PACKET_MTU) ? 1 : 0;
++
++ XGMAC_IOWRITE_BITS(pdata, MAC_RCR, JE, val);
++}
++
++static void xgbe_config_mac_speed(struct xgbe_prv_data *pdata)
++{
++ switch (pdata->phy_speed) {
++ case SPEED_10000:
++ xgbe_set_xgmii_speed(pdata);
++ break;
++
++ case SPEED_2500:
++ xgbe_set_gmii_2500_speed(pdata);
++ break;
++
++ case SPEED_1000:
++ xgbe_set_gmii_speed(pdata);
++ break;
++ }
++}
++
++static void xgbe_config_checksum_offload(struct xgbe_prv_data *pdata)
++{
++ if (pdata->netdev->features & NETIF_F_RXCSUM)
++ xgbe_enable_rx_csum(pdata);
++ else
++ xgbe_disable_rx_csum(pdata);
++}
++
++static void xgbe_config_vlan_support(struct xgbe_prv_data *pdata)
++{
++ /* Indicate that VLAN Tx CTAGs come from context descriptors */
++ XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, CSVL, 0);
++ XGMAC_IOWRITE_BITS(pdata, MAC_VLANIR, VLTI, 1);
++
++ /* Set the current VLAN Hash Table register value */
++ xgbe_update_vlan_hash_table(pdata);
++
++ if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_FILTER)
++ xgbe_enable_rx_vlan_filtering(pdata);
++ else
++ xgbe_disable_rx_vlan_filtering(pdata);
++
++ if (pdata->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
++ xgbe_enable_rx_vlan_stripping(pdata);
++ else
++ xgbe_disable_rx_vlan_stripping(pdata);
++}
++
++static u64 xgbe_mmc_read(struct xgbe_prv_data *pdata, unsigned int reg_lo)
++{
++ bool read_hi;
++ u64 val;
++
++ switch (reg_lo) {
++ /* These registers are always 64 bit */
++ case MMC_TXOCTETCOUNT_GB_LO:
++ case MMC_TXOCTETCOUNT_G_LO:
++ case MMC_RXOCTETCOUNT_GB_LO:
++ case MMC_RXOCTETCOUNT_G_LO:
++ read_hi = true;
++ break;
++
++ default:
++ read_hi = false;
++ };
++
++ val = XGMAC_IOREAD(pdata, reg_lo);
++
++ if (read_hi)
++ val |= ((u64)XGMAC_IOREAD(pdata, reg_lo + 4) << 32);
++
++ return val;
++}
++
++static void xgbe_tx_mmc_int(struct xgbe_prv_data *pdata)
++{
++ struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
++ unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_TISR);
++
++ if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_GB))
++ stats->txoctetcount_gb +=
++ xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO);
++
++ if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_GB))
++ stats->txframecount_gb +=
++ xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO);
++
++ if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_G))
++ stats->txbroadcastframes_g +=
++ xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO);
++
++ if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_G))
++ stats->txmulticastframes_g +=
++ xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO);
++
++ if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX64OCTETS_GB))
++ stats->tx64octets_gb +=
++ xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO);
++
++ if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX65TO127OCTETS_GB))
++ stats->tx65to127octets_gb +=
++ xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO);
++
++ if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX128TO255OCTETS_GB))
++ stats->tx128to255octets_gb +=
++ xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO);
++
++ if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX256TO511OCTETS_GB))
++ stats->tx256to511octets_gb +=
++ xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO);
++
++ if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX512TO1023OCTETS_GB))
++ stats->tx512to1023octets_gb +=
++ xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO);
++
++ if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TX1024TOMAXOCTETS_GB))
++ stats->tx1024tomaxoctets_gb +=
++ xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO);
++
++ if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNICASTFRAMES_GB))
++ stats->txunicastframes_gb +=
++ xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO);
++
++ if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXMULTICASTFRAMES_GB))
++ stats->txmulticastframes_gb +=
++ xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO);
++
++ if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXBROADCASTFRAMES_GB))
++ stats->txbroadcastframes_g +=
++ xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO);
++
++ if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXUNDERFLOWERROR))
++ stats->txunderflowerror +=
++ xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO);
++
++ if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXOCTETCOUNT_G))
++ stats->txoctetcount_g +=
++ xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO);
++
++ if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXFRAMECOUNT_G))
++ stats->txframecount_g +=
++ xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO);
++
++ if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXPAUSEFRAMES))
++ stats->txpauseframes +=
++ xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO);
++
++ if (XGMAC_GET_BITS(mmc_isr, MMC_TISR, TXVLANFRAMES_G))
++ stats->txvlanframes_g +=
++ xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO);
++}
++
++static void xgbe_rx_mmc_int(struct xgbe_prv_data *pdata)
++{
++ struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
++ unsigned int mmc_isr = XGMAC_IOREAD(pdata, MMC_RISR);
++
++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFRAMECOUNT_GB))
++ stats->rxframecount_gb +=
++ xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO);
++
++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_GB))
++ stats->rxoctetcount_gb +=
++ xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO);
++
++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOCTETCOUNT_G))
++ stats->rxoctetcount_g +=
++ xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO);
++
++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXBROADCASTFRAMES_G))
++ stats->rxbroadcastframes_g +=
++ xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO);
++
++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXMULTICASTFRAMES_G))
++ stats->rxmulticastframes_g +=
++ xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO);
++
++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXCRCERROR))
++ stats->rxcrcerror +=
++ xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO);
++
++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXRUNTERROR))
++ stats->rxrunterror +=
++ xgbe_mmc_read(pdata, MMC_RXRUNTERROR);
++
++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXJABBERERROR))
++ stats->rxjabbererror +=
++ xgbe_mmc_read(pdata, MMC_RXJABBERERROR);
++
++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNDERSIZE_G))
++ stats->rxundersize_g +=
++ xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G);
++
++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOVERSIZE_G))
++ stats->rxoversize_g +=
++ xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G);
++
++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX64OCTETS_GB))
++ stats->rx64octets_gb +=
++ xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO);
++
++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX65TO127OCTETS_GB))
++ stats->rx65to127octets_gb +=
++ xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO);
++
++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX128TO255OCTETS_GB))
++ stats->rx128to255octets_gb +=
++ xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO);
++
++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX256TO511OCTETS_GB))
++ stats->rx256to511octets_gb +=
++ xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO);
++
++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX512TO1023OCTETS_GB))
++ stats->rx512to1023octets_gb +=
++ xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO);
++
++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RX1024TOMAXOCTETS_GB))
++ stats->rx1024tomaxoctets_gb +=
++ xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO);
++
++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXUNICASTFRAMES_G))
++ stats->rxunicastframes_g +=
++ xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO);
++
++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXLENGTHERROR))
++ stats->rxlengtherror +=
++ xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO);
++
++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXOUTOFRANGETYPE))
++ stats->rxoutofrangetype +=
++ xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO);
++
++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXPAUSEFRAMES))
++ stats->rxpauseframes +=
++ xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO);
++
++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXFIFOOVERFLOW))
++ stats->rxfifooverflow +=
++ xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO);
++
++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXVLANFRAMES_GB))
++ stats->rxvlanframes_gb +=
++ xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO);
++
++ if (XGMAC_GET_BITS(mmc_isr, MMC_RISR, RXWATCHDOGERROR))
++ stats->rxwatchdogerror +=
++ xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR);
++}
++
++static void xgbe_read_mmc_stats(struct xgbe_prv_data *pdata)
++{
++ struct xgbe_mmc_stats *stats = &pdata->mmc_stats;
++
++ /* Freeze counters */
++ XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 1);
++
++ stats->txoctetcount_gb +=
++ xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_GB_LO);
++
++ stats->txframecount_gb +=
++ xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_GB_LO);
++
++ stats->txbroadcastframes_g +=
++ xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_G_LO);
++
++ stats->txmulticastframes_g +=
++ xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_G_LO);
++
++ stats->tx64octets_gb +=
++ xgbe_mmc_read(pdata, MMC_TX64OCTETS_GB_LO);
++
++ stats->tx65to127octets_gb +=
++ xgbe_mmc_read(pdata, MMC_TX65TO127OCTETS_GB_LO);
++
++ stats->tx128to255octets_gb +=
++ xgbe_mmc_read(pdata, MMC_TX128TO255OCTETS_GB_LO);
++
++ stats->tx256to511octets_gb +=
++ xgbe_mmc_read(pdata, MMC_TX256TO511OCTETS_GB_LO);
++
++ stats->tx512to1023octets_gb +=
++ xgbe_mmc_read(pdata, MMC_TX512TO1023OCTETS_GB_LO);
++
++ stats->tx1024tomaxoctets_gb +=
++ xgbe_mmc_read(pdata, MMC_TX1024TOMAXOCTETS_GB_LO);
++
++ stats->txunicastframes_gb +=
++ xgbe_mmc_read(pdata, MMC_TXUNICASTFRAMES_GB_LO);
++
++ stats->txmulticastframes_gb +=
++ xgbe_mmc_read(pdata, MMC_TXMULTICASTFRAMES_GB_LO);
++
++ stats->txbroadcastframes_g +=
++ xgbe_mmc_read(pdata, MMC_TXBROADCASTFRAMES_GB_LO);
++
++ stats->txunderflowerror +=
++ xgbe_mmc_read(pdata, MMC_TXUNDERFLOWERROR_LO);
++
++ stats->txoctetcount_g +=
++ xgbe_mmc_read(pdata, MMC_TXOCTETCOUNT_G_LO);
++
++ stats->txframecount_g +=
++ xgbe_mmc_read(pdata, MMC_TXFRAMECOUNT_G_LO);
++
++ stats->txpauseframes +=
++ xgbe_mmc_read(pdata, MMC_TXPAUSEFRAMES_LO);
++
++ stats->txvlanframes_g +=
++ xgbe_mmc_read(pdata, MMC_TXVLANFRAMES_G_LO);
++
++ stats->rxframecount_gb +=
++ xgbe_mmc_read(pdata, MMC_RXFRAMECOUNT_GB_LO);
++
++ stats->rxoctetcount_gb +=
++ xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_GB_LO);
++
++ stats->rxoctetcount_g +=
++ xgbe_mmc_read(pdata, MMC_RXOCTETCOUNT_G_LO);
++
++ stats->rxbroadcastframes_g +=
++ xgbe_mmc_read(pdata, MMC_RXBROADCASTFRAMES_G_LO);
++
++ stats->rxmulticastframes_g +=
++ xgbe_mmc_read(pdata, MMC_RXMULTICASTFRAMES_G_LO);
++
++ stats->rxcrcerror +=
++ xgbe_mmc_read(pdata, MMC_RXCRCERROR_LO);
++
++ stats->rxrunterror +=
++ xgbe_mmc_read(pdata, MMC_RXRUNTERROR);
++
++ stats->rxjabbererror +=
++ xgbe_mmc_read(pdata, MMC_RXJABBERERROR);
++
++ stats->rxundersize_g +=
++ xgbe_mmc_read(pdata, MMC_RXUNDERSIZE_G);
++
++ stats->rxoversize_g +=
++ xgbe_mmc_read(pdata, MMC_RXOVERSIZE_G);
++
++ stats->rx64octets_gb +=
++ xgbe_mmc_read(pdata, MMC_RX64OCTETS_GB_LO);
++
++ stats->rx65to127octets_gb +=
++ xgbe_mmc_read(pdata, MMC_RX65TO127OCTETS_GB_LO);
++
++ stats->rx128to255octets_gb +=
++ xgbe_mmc_read(pdata, MMC_RX128TO255OCTETS_GB_LO);
++
++ stats->rx256to511octets_gb +=
++ xgbe_mmc_read(pdata, MMC_RX256TO511OCTETS_GB_LO);
++
++ stats->rx512to1023octets_gb +=
++ xgbe_mmc_read(pdata, MMC_RX512TO1023OCTETS_GB_LO);
++
++ stats->rx1024tomaxoctets_gb +=
++ xgbe_mmc_read(pdata, MMC_RX1024TOMAXOCTETS_GB_LO);
++
++ stats->rxunicastframes_g +=
++ xgbe_mmc_read(pdata, MMC_RXUNICASTFRAMES_G_LO);
++
++ stats->rxlengtherror +=
++ xgbe_mmc_read(pdata, MMC_RXLENGTHERROR_LO);
++
++ stats->rxoutofrangetype +=
++ xgbe_mmc_read(pdata, MMC_RXOUTOFRANGETYPE_LO);
++
++ stats->rxpauseframes +=
++ xgbe_mmc_read(pdata, MMC_RXPAUSEFRAMES_LO);
++
++ stats->rxfifooverflow +=
++ xgbe_mmc_read(pdata, MMC_RXFIFOOVERFLOW_LO);
++
++ stats->rxvlanframes_gb +=
++ xgbe_mmc_read(pdata, MMC_RXVLANFRAMES_GB_LO);
++
++ stats->rxwatchdogerror +=
++ xgbe_mmc_read(pdata, MMC_RXWATCHDOGERROR);
++
++ /* Un-freeze counters */
++ XGMAC_IOWRITE_BITS(pdata, MMC_CR, MCF, 0);
++}
++
++static void xgbe_config_mmc(struct xgbe_prv_data *pdata)
++{
++ /* Set counters to reset on read */
++ XGMAC_IOWRITE_BITS(pdata, MMC_CR, ROR, 1);
++
++ /* Reset the counters */
++ XGMAC_IOWRITE_BITS(pdata, MMC_CR, CR, 1);
++}
++
++static void xgbe_prepare_tx_stop(struct xgbe_prv_data *pdata,
++ struct xgbe_channel *channel)
++{
++ unsigned int tx_dsr, tx_pos, tx_qidx;
++ unsigned int tx_status;
++ unsigned long tx_timeout;
++
++ /* Calculate the status register to read and the position within */
++ if (channel->queue_index < DMA_DSRX_FIRST_QUEUE) {
++ tx_dsr = DMA_DSR0;
++ tx_pos = (channel->queue_index * DMA_DSR_Q_WIDTH) +
++ DMA_DSR0_TPS_START;
++ } else {
++ tx_qidx = channel->queue_index - DMA_DSRX_FIRST_QUEUE;
++
++ tx_dsr = DMA_DSR1 + ((tx_qidx / DMA_DSRX_QPR) * DMA_DSRX_INC);
++ tx_pos = ((tx_qidx % DMA_DSRX_QPR) * DMA_DSR_Q_WIDTH) +
++ DMA_DSRX_TPS_START;
++ }
++
++ /* The Tx engine cannot be stopped if it is actively processing
++ * descriptors. Wait for the Tx engine to enter the stopped or
++ * suspended state. Don't wait forever though...
++ */
++ tx_timeout = jiffies + (XGBE_DMA_STOP_TIMEOUT * HZ);
++ while (time_before(jiffies, tx_timeout)) {
++ tx_status = XGMAC_IOREAD(pdata, tx_dsr);
++ tx_status = GET_BITS(tx_status, tx_pos, DMA_DSR_TPS_WIDTH);
++ if ((tx_status == DMA_TPS_STOPPED) ||
++ (tx_status == DMA_TPS_SUSPENDED))
++ break;
++
++ usleep_range(500, 1000);
++ }
++
++ if (!time_before(jiffies, tx_timeout))
++ netdev_info(pdata->netdev,
++ "timed out waiting for Tx DMA channel %u to stop\n",
++ channel->queue_index);
++}
++
++static void xgbe_enable_tx(struct xgbe_prv_data *pdata)
++{
++ struct xgbe_channel *channel;
++ unsigned int i;
++
++ /* Enable each Tx DMA channel */
++ channel = pdata->channel;
++ for (i = 0; i < pdata->channel_count; i++, channel++) {
++ if (!channel->tx_ring)
++ break;
++
++ XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 1);
++ }
++
++ /* Enable each Tx queue */
++ for (i = 0; i < pdata->tx_q_count; i++)
++ XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN,
++ MTL_Q_ENABLED);
++
++ /* Enable MAC Tx */
++ XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1);
++}
++
++static void xgbe_disable_tx(struct xgbe_prv_data *pdata)
++{
++ struct xgbe_channel *channel;
++ unsigned int i;
++
++ /* Prepare for Tx DMA channel stop */
++ channel = pdata->channel;
++ for (i = 0; i < pdata->channel_count; i++, channel++) {
++ if (!channel->tx_ring)
++ break;
++
++ xgbe_prepare_tx_stop(pdata, channel);
++ }
++
++ /* Disable MAC Tx */
++ XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0);
++
++ /* Disable each Tx queue */
++ for (i = 0; i < pdata->tx_q_count; i++)
++ XGMAC_MTL_IOWRITE_BITS(pdata, i, MTL_Q_TQOMR, TXQEN, 0);
++
++ /* Disable each Tx DMA channel */
++ channel = pdata->channel;
++ for (i = 0; i < pdata->channel_count; i++, channel++) {
++ if (!channel->tx_ring)
++ break;
++
++ XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 0);
++ }
++
++ /*TODO: Poll to be sure the channels have stopped?
++ while (count--) {
++ if (XGMAC_IOREAD_BITS(pdata, DMA_DSR0, TPS) == 6)
++ break;
++ mdelay(1);
++ }
++ */
++}
++
++static void xgbe_enable_rx(struct xgbe_prv_data *pdata)
++{
++ struct xgbe_channel *channel;
++ unsigned int reg_val, i;
++
++ /* Enable each Rx DMA channel */
++ channel = pdata->channel;
++ for (i = 0; i < pdata->channel_count; i++, channel++) {
++ if (!channel->rx_ring)
++ break;
++
++ XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 1);
++ }
++
++ /* Enable each Rx queue */
++ reg_val = 0;
++ for (i = 0; i < pdata->rx_q_count; i++)
++ reg_val |= (0x02 << (i << 1));
++ XGMAC_IOWRITE(pdata, MAC_RQC0R, reg_val);
++
++ /* Enable MAC Rx */
++ XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 1);
++ XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 1);
++ XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 1);
++ XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 1);
++}
++
++static void xgbe_disable_rx(struct xgbe_prv_data *pdata)
++{
++ struct xgbe_channel *channel;
++ unsigned int i;
++
++ /* Disable MAC Rx */
++ XGMAC_IOWRITE_BITS(pdata, MAC_RCR, DCRCC, 0);
++ XGMAC_IOWRITE_BITS(pdata, MAC_RCR, CST, 0);
++ XGMAC_IOWRITE_BITS(pdata, MAC_RCR, ACS, 0);
++ XGMAC_IOWRITE_BITS(pdata, MAC_RCR, RE, 0);
++
++ /* Disable each Rx queue */
++ XGMAC_IOWRITE(pdata, MAC_RQC0R, 0);
++
++ /* Disable each Rx DMA channel */
++ channel = pdata->channel;
++ for (i = 0; i < pdata->channel_count; i++, channel++) {
++ if (!channel->rx_ring)
++ break;
++
++ XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 0);
++ }
++
++ /*TODO: Poll to be sure the channels have stopped?
++ while (count--) {
++ dma_sr0 = XGMAC_IOREAD_BITS(pdata, DMA_DSR0, RPS);
++ if (dma_sr0 == 3 || dma_sr0 == 4)
++ break;
++ mdelay(1);
++ }
++ */
++}
++
++static void xgbe_powerup_tx(struct xgbe_prv_data *pdata)
++{
++ struct xgbe_channel *channel;
++ unsigned int i;
++
++ /* Enable each Tx DMA channel */
++ channel = pdata->channel;
++ for (i = 0; i < pdata->channel_count; i++, channel++) {
++ if (!channel->tx_ring)
++ break;
++
++ XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 1);
++ }
++
++ /* Enable MAC Tx */
++ XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 1);
++}
++
++static void xgbe_powerdown_tx(struct xgbe_prv_data *pdata)
++{
++ struct xgbe_channel *channel;
++ unsigned int i;
++
++ /* Prepare for Tx DMA channel stop */
++ channel = pdata->channel;
++ for (i = 0; i < pdata->channel_count; i++, channel++) {
++ if (!channel->tx_ring)
++ break;
++
++ xgbe_prepare_tx_stop(pdata, channel);
++ }
++
++ /* Disable MAC Tx */
++ XGMAC_IOWRITE_BITS(pdata, MAC_TCR, TE, 0);
++
++ /* Disable each Tx DMA channel */
++ channel = pdata->channel;
++ for (i = 0; i < pdata->channel_count; i++, channel++) {
++ if (!channel->tx_ring)
++ break;
++
++ XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_TCR, ST, 0);
++ }
++
++ /*TODO: Poll to be sure the channels have stopped?
++ while (count--) {
++ if (XGMAC_IOREAD_BITS(pdata, DMA_DSR0, TPS) == 6)
++ break;
++ mdelay(1);
++ }
++ */
++}
++
++static void xgbe_powerup_rx(struct xgbe_prv_data *pdata)
++{
++ struct xgbe_channel *channel;
++ unsigned int i;
++
++ /* Enable each Rx DMA channel */
++ channel = pdata->channel;
++ for (i = 0; i < pdata->channel_count; i++, channel++) {
++ if (!channel->rx_ring)
++ break;
++
++ XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 1);
++ }
++}
++
++static void xgbe_powerdown_rx(struct xgbe_prv_data *pdata)
++{
++ struct xgbe_channel *channel;
++ unsigned int i;
++
++ /* Disable each Rx DMA channel */
++ channel = pdata->channel;
++ for (i = 0; i < pdata->channel_count; i++, channel++) {
++ if (!channel->rx_ring)
++ break;
++
++ XGMAC_DMA_IOWRITE_BITS(channel, DMA_CH_RCR, SR, 0);
++ }
++
++ /*TODO: Poll to be sure the channels have stopped?
++ while (count--) {
++ dma_sr0 = XGMAC_IOREAD_BITS(pdata, DMA_DSR0, RPS);
++ if (dma_sr0 == 3 || dma_sr0 == 4)
++ break;
++ mdelay(1);
++ }
++ */
++}
++
++static int xgbe_init(struct xgbe_prv_data *pdata)
++{
++ struct xgbe_desc_if *desc_if = &pdata->desc_if;
++ int ret;
++
++ DBGPR("-->xgbe_init\n");
++
++ /* Flush Tx queues */
++ ret = xgbe_flush_tx_queues(pdata);
++ if (ret)
++ return ret;
++
++ /*
++ * Initialize DMA related features
++ */
++ xgbe_config_dma_bus(pdata);
++ xgbe_config_dma_cache(pdata);
++ xgbe_config_osp_mode(pdata);
++ xgbe_config_pblx8(pdata);
++ xgbe_config_tx_pbl_val(pdata);
++ xgbe_config_rx_pbl_val(pdata);
++ xgbe_config_rx_coalesce(pdata);
++ xgbe_config_tx_coalesce(pdata);
++ xgbe_config_rx_buffer_size(pdata);
++ xgbe_config_tso_mode(pdata);
++ xgbe_config_sph_mode(pdata);
++ xgbe_config_rss(pdata);
++ desc_if->wrapper_tx_desc_init(pdata);
++ desc_if->wrapper_rx_desc_init(pdata);
++ xgbe_enable_dma_interrupts(pdata);
++
++ /*
++ * Initialize MTL related features
++ */
++ xgbe_config_mtl_mode(pdata);
++ xgbe_config_queue_mapping(pdata);
++ xgbe_config_tsf_mode(pdata, pdata->tx_sf_mode);
++ xgbe_config_rsf_mode(pdata, pdata->rx_sf_mode);
++ xgbe_config_tx_threshold(pdata, pdata->tx_threshold);
++ xgbe_config_rx_threshold(pdata, pdata->rx_threshold);
++ xgbe_config_tx_fifo_size(pdata);
++ xgbe_config_rx_fifo_size(pdata);
++ xgbe_config_flow_control_threshold(pdata);
++ /*TODO: Error Packet and undersized good Packet forwarding enable
++ (FEP and FUP)
++ */
++ xgbe_config_dcb_tc(pdata);
++ xgbe_config_dcb_pfc(pdata);
++ xgbe_enable_mtl_interrupts(pdata);
++
++ /*
++ * Initialize MAC related features
++ */
++ xgbe_config_mac_address(pdata);
++ xgbe_config_jumbo_enable(pdata);
++ xgbe_config_flow_control(pdata);
++ xgbe_config_mac_speed(pdata);
++ xgbe_config_checksum_offload(pdata);
++ xgbe_config_vlan_support(pdata);
++ xgbe_config_mmc(pdata);
++ xgbe_enable_mac_interrupts(pdata);
++
++ DBGPR("<--xgbe_init\n");
++
++ return 0;
++}
++
++void xgbe_a0_init_function_ptrs_dev(struct xgbe_hw_if *hw_if)
++{
++ DBGPR("-->xgbe_a0_init_function_ptrs\n");
++
++ hw_if->tx_complete = xgbe_tx_complete;
++
++ hw_if->set_promiscuous_mode = xgbe_set_promiscuous_mode;
++ hw_if->set_all_multicast_mode = xgbe_set_all_multicast_mode;
++ hw_if->add_mac_addresses = xgbe_add_mac_addresses;
++ hw_if->set_mac_address = xgbe_set_mac_address;
++
++ hw_if->enable_rx_csum = xgbe_enable_rx_csum;
++ hw_if->disable_rx_csum = xgbe_disable_rx_csum;
++
++ hw_if->enable_rx_vlan_stripping = xgbe_enable_rx_vlan_stripping;
++ hw_if->disable_rx_vlan_stripping = xgbe_disable_rx_vlan_stripping;
++ hw_if->enable_rx_vlan_filtering = xgbe_enable_rx_vlan_filtering;
++ hw_if->disable_rx_vlan_filtering = xgbe_disable_rx_vlan_filtering;
++ hw_if->update_vlan_hash_table = xgbe_update_vlan_hash_table;
++
++ hw_if->read_mmd_regs = xgbe_read_mmd_regs;
++ hw_if->write_mmd_regs = xgbe_write_mmd_regs;
++
++ hw_if->set_gmii_speed = xgbe_set_gmii_speed;
++ hw_if->set_gmii_2500_speed = xgbe_set_gmii_2500_speed;
++ hw_if->set_xgmii_speed = xgbe_set_xgmii_speed;
++
++ hw_if->enable_tx = xgbe_enable_tx;
++ hw_if->disable_tx = xgbe_disable_tx;
++ hw_if->enable_rx = xgbe_enable_rx;
++ hw_if->disable_rx = xgbe_disable_rx;
++
++ hw_if->powerup_tx = xgbe_powerup_tx;
++ hw_if->powerdown_tx = xgbe_powerdown_tx;
++ hw_if->powerup_rx = xgbe_powerup_rx;
++ hw_if->powerdown_rx = xgbe_powerdown_rx;
++
++ hw_if->dev_xmit = xgbe_dev_xmit;
++ hw_if->dev_read = xgbe_dev_read;
++ hw_if->enable_int = xgbe_enable_int;
++ hw_if->disable_int = xgbe_disable_int;
++ hw_if->init = xgbe_init;
++ hw_if->exit = xgbe_exit;
++
++ /* Descriptor related Sequences have to be initialized here */
++ hw_if->tx_desc_init = xgbe_tx_desc_init;
++ hw_if->rx_desc_init = xgbe_rx_desc_init;
++ hw_if->tx_desc_reset = xgbe_tx_desc_reset;
++ hw_if->rx_desc_reset = xgbe_rx_desc_reset;
++ hw_if->is_last_desc = xgbe_is_last_desc;
++ hw_if->is_context_desc = xgbe_is_context_desc;
++ hw_if->tx_start_xmit = xgbe_tx_start_xmit;
++
++ /* For FLOW ctrl */
++ hw_if->config_tx_flow_control = xgbe_config_tx_flow_control;
++ hw_if->config_rx_flow_control = xgbe_config_rx_flow_control;
++
++ /* For RX coalescing */
++ hw_if->config_rx_coalesce = xgbe_config_rx_coalesce;
++ hw_if->config_tx_coalesce = xgbe_config_tx_coalesce;
++ hw_if->usec_to_riwt = xgbe_usec_to_riwt;
++ hw_if->riwt_to_usec = xgbe_riwt_to_usec;
++
++ /* For RX and TX threshold config */
++ hw_if->config_rx_threshold = xgbe_config_rx_threshold;
++ hw_if->config_tx_threshold = xgbe_config_tx_threshold;
++
++ /* For RX and TX Store and Forward Mode config */
++ hw_if->config_rsf_mode = xgbe_config_rsf_mode;
++ hw_if->config_tsf_mode = xgbe_config_tsf_mode;
++
++ /* For TX DMA Operating on Second Frame config */
++ hw_if->config_osp_mode = xgbe_config_osp_mode;
++
++ /* For RX and TX PBL config */
++ hw_if->config_rx_pbl_val = xgbe_config_rx_pbl_val;
++ hw_if->get_rx_pbl_val = xgbe_get_rx_pbl_val;
++ hw_if->config_tx_pbl_val = xgbe_config_tx_pbl_val;
++ hw_if->get_tx_pbl_val = xgbe_get_tx_pbl_val;
++ hw_if->config_pblx8 = xgbe_config_pblx8;
++
++ /* For MMC statistics support */
++ hw_if->tx_mmc_int = xgbe_tx_mmc_int;
++ hw_if->rx_mmc_int = xgbe_rx_mmc_int;
++ hw_if->read_mmc_stats = xgbe_read_mmc_stats;
++
++ /* For PTP config */
++ hw_if->config_tstamp = xgbe_config_tstamp;
++ hw_if->update_tstamp_addend = xgbe_update_tstamp_addend;
++ hw_if->set_tstamp_time = xgbe_set_tstamp_time;
++ hw_if->get_tstamp_time = xgbe_get_tstamp_time;
++ hw_if->get_tx_tstamp = xgbe_get_tx_tstamp;
++
++ /* For Data Center Bridging config */
++ hw_if->config_dcb_tc = xgbe_config_dcb_tc;
++ hw_if->config_dcb_pfc = xgbe_config_dcb_pfc;
++
++ /* For Receive Side Scaling */
++ hw_if->enable_rss = xgbe_enable_rss;
++ hw_if->disable_rss = xgbe_disable_rss;
++ hw_if->set_rss_hash_key = xgbe_set_rss_hash_key;
++ hw_if->set_rss_lookup_table = xgbe_set_rss_lookup_table;
++
++ DBGPR("<--xgbe_a0_init_function_ptrs\n");
++}
+diff --git a/drivers/net/ethernet/amd/xgbe-a0/xgbe-drv.c b/drivers/net/ethernet/amd/xgbe-a0/xgbe-drv.c
+new file mode 100644
+index 000000000000..acaeaf56b63f
+--- /dev/null
++++ b/drivers/net/ethernet/amd/xgbe-a0/xgbe-drv.c
+@@ -0,0 +1,2204 @@
++/*
++ * AMD 10Gb Ethernet driver
++ *
++ * This file is available to you under your choice of the following two
++ * licenses:
++ *
++ * License 1: GPLv2
++ *
++ * Copyright (c) 2014 Advanced Micro Devices, Inc.
++ *
++ * This file is free software; you may copy, redistribute and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 2 of the License, or (at
++ * your option) any later version.
++ *
++ * This file is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ *
++ * This file incorporates work covered by the following copyright and
++ * permission notice:
++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation
++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
++ * Inc. unless otherwise expressly agreed to in writing between Synopsys
++ * and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product
++ * under any End User Software License Agreement or Agreement for Licensed
++ * Product with Synopsys or any supplement thereto. Permission is hereby
++ * granted, free of charge, to any person obtaining a copy of this software
++ * annotated with this license and the Software, to deal in the Software
++ * without restriction, including without limitation the rights to use,
++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
++ * of the Software, and to permit persons to whom the Software is furnished
++ * to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
++ * THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ *
++ * License 2: Modified BSD
++ *
++ * Copyright (c) 2014 Advanced Micro Devices, Inc.
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * * Neither the name of Advanced Micro Devices, Inc. nor the
++ * names of its contributors may be used to endorse or promote products
++ * derived from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * This file incorporates work covered by the following copyright and
++ * permission notice:
++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation
++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
++ * Inc. unless otherwise expressly agreed to in writing between Synopsys
++ * and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product
++ * under any End User Software License Agreement or Agreement for Licensed
++ * Product with Synopsys or any supplement thereto. Permission is hereby
++ * granted, free of charge, to any person obtaining a copy of this software
++ * annotated with this license and the Software, to deal in the Software
++ * without restriction, including without limitation the rights to use,
++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
++ * of the Software, and to permit persons to whom the Software is furnished
++ * to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
++ * THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include <linux/platform_device.h>
++#include <linux/spinlock.h>
++#include <linux/tcp.h>
++#include <linux/if_vlan.h>
++#include <net/busy_poll.h>
++#include <linux/clk.h>
++#include <linux/if_ether.h>
++#include <linux/net_tstamp.h>
++#include <linux/phy.h>
++
++#include "xgbe.h"
++#include "xgbe-common.h"
++
++static int xgbe_one_poll(struct napi_struct *, int);
++static int xgbe_all_poll(struct napi_struct *, int);
++static void xgbe_set_rx_mode(struct net_device *);
++
++static int xgbe_alloc_channels(struct xgbe_prv_data *pdata)
++{
++ struct xgbe_channel *channel_mem, *channel;
++ struct xgbe_ring *tx_ring, *rx_ring;
++ unsigned int count, i;
++ int ret = -ENOMEM;
++
++ count = max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count);
++
++ channel_mem = kcalloc(count, sizeof(struct xgbe_channel), GFP_KERNEL);
++ if (!channel_mem)
++ goto err_channel;
++
++ tx_ring = kcalloc(pdata->tx_ring_count, sizeof(struct xgbe_ring),
++ GFP_KERNEL);
++ if (!tx_ring)
++ goto err_tx_ring;
++
++ rx_ring = kcalloc(pdata->rx_ring_count, sizeof(struct xgbe_ring),
++ GFP_KERNEL);
++ if (!rx_ring)
++ goto err_rx_ring;
++
++ for (i = 0, channel = channel_mem; i < count; i++, channel++) {
++ snprintf(channel->name, sizeof(channel->name), "channel-%d", i);
++ channel->pdata = pdata;
++ channel->queue_index = i;
++ channel->dma_regs = pdata->xgmac_regs + DMA_CH_BASE +
++ (DMA_CH_INC * i);
++
++ if (pdata->per_channel_irq) {
++ /* Get the DMA interrupt (offset 1) */
++ ret = platform_get_irq(pdata->pdev, i + 1);
++ if (ret < 0) {
++ netdev_err(pdata->netdev,
++ "platform_get_irq %u failed\n",
++ i + 1);
++ goto err_irq;
++ }
++
++ channel->dma_irq = ret;
++ }
++
++ if (i < pdata->tx_ring_count) {
++ spin_lock_init(&tx_ring->lock);
++ channel->tx_ring = tx_ring++;
++ }
++
++ if (i < pdata->rx_ring_count) {
++ spin_lock_init(&rx_ring->lock);
++ channel->rx_ring = rx_ring++;
++ }
++
++ DBGPR(" %s: queue=%u, dma_regs=%p, dma_irq=%d, tx=%p, rx=%p\n",
++ channel->name, channel->queue_index, channel->dma_regs,
++ channel->dma_irq, channel->tx_ring, channel->rx_ring);
++ }
++
++ pdata->channel = channel_mem;
++ pdata->channel_count = count;
++
++ return 0;
++
++err_irq:
++ kfree(rx_ring);
++
++err_rx_ring:
++ kfree(tx_ring);
++
++err_tx_ring:
++ kfree(channel_mem);
++
++err_channel:
++ return ret;
++}
++
++static void xgbe_free_channels(struct xgbe_prv_data *pdata)
++{
++ if (!pdata->channel)
++ return;
++
++ kfree(pdata->channel->rx_ring);
++ kfree(pdata->channel->tx_ring);
++ kfree(pdata->channel);
++
++ pdata->channel = NULL;
++ pdata->channel_count = 0;
++}
++
++static inline unsigned int xgbe_tx_avail_desc(struct xgbe_ring *ring)
++{
++ return (ring->rdesc_count - (ring->cur - ring->dirty));
++}
++
++static inline unsigned int xgbe_rx_dirty_desc(struct xgbe_ring *ring)
++{
++ return (ring->cur - ring->dirty);
++}
++
++static int xgbe_maybe_stop_tx_queue(struct xgbe_channel *channel,
++ struct xgbe_ring *ring, unsigned int count)
++{
++ struct xgbe_prv_data *pdata = channel->pdata;
++
++ if (count > xgbe_tx_avail_desc(ring)) {
++ DBGPR(" Tx queue stopped, not enough descriptors available\n");
++ netif_stop_subqueue(pdata->netdev, channel->queue_index);
++ ring->tx.queue_stopped = 1;
++
++ /* If we haven't notified the hardware because of xmit_more
++ * support, tell it now
++ */
++ if (ring->tx.xmit_more)
++ pdata->hw_if.tx_start_xmit(channel, ring);
++
++ return NETDEV_TX_BUSY;
++ }
++
++ return 0;
++}
++
++static int xgbe_calc_rx_buf_size(struct net_device *netdev, unsigned int mtu)
++{
++ unsigned int rx_buf_size;
++
++ if (mtu > XGMAC_JUMBO_PACKET_MTU) {
++ netdev_alert(netdev, "MTU exceeds maximum supported value\n");
++ return -EINVAL;
++ }
++
++ rx_buf_size = mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
++ rx_buf_size = clamp_val(rx_buf_size, XGBE_RX_MIN_BUF_SIZE, PAGE_SIZE);
++
++ rx_buf_size = (rx_buf_size + XGBE_RX_BUF_ALIGN - 1) &
++ ~(XGBE_RX_BUF_ALIGN - 1);
++
++ return rx_buf_size;
++}
++
++static void xgbe_enable_rx_tx_ints(struct xgbe_prv_data *pdata)
++{
++ struct xgbe_hw_if *hw_if = &pdata->hw_if;
++ struct xgbe_channel *channel;
++ enum xgbe_int int_id;
++ unsigned int i;
++
++ channel = pdata->channel;
++ for (i = 0; i < pdata->channel_count; i++, channel++) {
++ if (channel->tx_ring && channel->rx_ring)
++ int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
++ else if (channel->tx_ring)
++ int_id = XGMAC_INT_DMA_CH_SR_TI;
++ else if (channel->rx_ring)
++ int_id = XGMAC_INT_DMA_CH_SR_RI;
++ else
++ continue;
++
++ hw_if->enable_int(channel, int_id);
++ }
++}
++
++static void xgbe_disable_rx_tx_ints(struct xgbe_prv_data *pdata)
++{
++ struct xgbe_hw_if *hw_if = &pdata->hw_if;
++ struct xgbe_channel *channel;
++ enum xgbe_int int_id;
++ unsigned int i;
++
++ channel = pdata->channel;
++ for (i = 0; i < pdata->channel_count; i++, channel++) {
++ if (channel->tx_ring && channel->rx_ring)
++ int_id = XGMAC_INT_DMA_CH_SR_TI_RI;
++ else if (channel->tx_ring)
++ int_id = XGMAC_INT_DMA_CH_SR_TI;
++ else if (channel->rx_ring)
++ int_id = XGMAC_INT_DMA_CH_SR_RI;
++ else
++ continue;
++
++ hw_if->disable_int(channel, int_id);
++ }
++}
++
++static irqreturn_t xgbe_isr(int irq, void *data)
++{
++ struct xgbe_prv_data *pdata = data;
++ struct xgbe_hw_if *hw_if = &pdata->hw_if;
++ struct xgbe_channel *channel;
++ unsigned int dma_isr, dma_ch_isr;
++ unsigned int mac_isr, mac_tssr;
++ unsigned int i;
++
++ /* The DMA interrupt status register also reports MAC and MTL
++ * interrupts. So for polling mode, we just need to check for
++ * this register to be non-zero
++ */
++ dma_isr = XGMAC_IOREAD(pdata, DMA_ISR);
++ if (!dma_isr)
++ goto isr_done;
++
++ DBGPR(" DMA_ISR = %08x\n", dma_isr);
++
++ for (i = 0; i < pdata->channel_count; i++) {
++ if (!(dma_isr & (1 << i)))
++ continue;
++
++ channel = pdata->channel + i;
++
++ dma_ch_isr = XGMAC_DMA_IOREAD(channel, DMA_CH_SR);
++ DBGPR(" DMA_CH%u_ISR = %08x\n", i, dma_ch_isr);
++
++ /* If we get a TI or RI interrupt that means per channel DMA
++ * interrupts are not enabled, so we use the private data napi
++ * structure, not the per channel napi structure
++ */
++ if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, TI) ||
++ XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, RI)) {
++ if (napi_schedule_prep(&pdata->napi)) {
++ /* Disable Tx and Rx interrupts */
++ xgbe_disable_rx_tx_ints(pdata);
++
++ /* Turn on polling */
++ __napi_schedule(&pdata->napi);
++ }
++ }
++
++ /* Restart the device on a Fatal Bus Error */
++ if (XGMAC_GET_BITS(dma_ch_isr, DMA_CH_SR, FBE))
++ schedule_work(&pdata->restart_work);
++
++ /* Clear all interrupt signals */
++ XGMAC_DMA_IOWRITE(channel, DMA_CH_SR, dma_ch_isr);
++ }
++
++ if (XGMAC_GET_BITS(dma_isr, DMA_ISR, MACIS)) {
++ mac_isr = XGMAC_IOREAD(pdata, MAC_ISR);
++
++ if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCTXIS))
++ hw_if->tx_mmc_int(pdata);
++
++ if (XGMAC_GET_BITS(mac_isr, MAC_ISR, MMCRXIS))
++ hw_if->rx_mmc_int(pdata);
++
++ if (XGMAC_GET_BITS(mac_isr, MAC_ISR, TSIS)) {
++ mac_tssr = XGMAC_IOREAD(pdata, MAC_TSSR);
++
++ if (XGMAC_GET_BITS(mac_tssr, MAC_TSSR, TXTSC)) {
++ /* Read Tx Timestamp to clear interrupt */
++ pdata->tx_tstamp =
++ hw_if->get_tx_tstamp(pdata);
++ schedule_work(&pdata->tx_tstamp_work);
++ }
++ }
++ }
++
++ DBGPR(" DMA_ISR = %08x\n", XGMAC_IOREAD(pdata, DMA_ISR));
++
++isr_done:
++ return IRQ_HANDLED;
++}
++
++static irqreturn_t xgbe_dma_isr(int irq, void *data)
++{
++ struct xgbe_channel *channel = data;
++
++ /* Per channel DMA interrupts are enabled, so we use the per
++ * channel napi structure and not the private data napi structure
++ */
++ if (napi_schedule_prep(&channel->napi)) {
++ /* Disable Tx and Rx interrupts */
++ disable_irq_nosync(channel->dma_irq);
++
++ /* Turn on polling */
++ __napi_schedule(&channel->napi);
++ }
++
++ return IRQ_HANDLED;
++}
++
++static enum hrtimer_restart xgbe_tx_timer(struct hrtimer *timer)
++{
++ struct xgbe_channel *channel = container_of(timer,
++ struct xgbe_channel,
++ tx_timer);
++ struct xgbe_prv_data *pdata = channel->pdata;
++ struct napi_struct *napi;
++
++ DBGPR("-->xgbe_tx_timer\n");
++
++ napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
++
++ if (napi_schedule_prep(napi)) {
++ /* Disable Tx and Rx interrupts */
++ if (pdata->per_channel_irq)
++ disable_irq(channel->dma_irq);
++ else
++ xgbe_disable_rx_tx_ints(pdata);
++
++ /* Turn on polling */
++ __napi_schedule(napi);
++ }
++
++ channel->tx_timer_active = 0;
++
++ DBGPR("<--xgbe_tx_timer\n");
++
++ return HRTIMER_NORESTART;
++}
++
++static void xgbe_init_tx_timers(struct xgbe_prv_data *pdata)
++{
++ struct xgbe_channel *channel;
++ unsigned int i;
++
++ DBGPR("-->xgbe_init_tx_timers\n");
++
++ channel = pdata->channel;
++ for (i = 0; i < pdata->channel_count; i++, channel++) {
++ if (!channel->tx_ring)
++ break;
++
++ DBGPR(" %s adding tx timer\n", channel->name);
++ hrtimer_init(&channel->tx_timer, CLOCK_MONOTONIC,
++ HRTIMER_MODE_REL);
++ channel->tx_timer.function = xgbe_tx_timer;
++ }
++
++ DBGPR("<--xgbe_init_tx_timers\n");
++}
++
++static void xgbe_stop_tx_timers(struct xgbe_prv_data *pdata)
++{
++ struct xgbe_channel *channel;
++ unsigned int i;
++
++ DBGPR("-->xgbe_stop_tx_timers\n");
++
++ channel = pdata->channel;
++ for (i = 0; i < pdata->channel_count; i++, channel++) {
++ if (!channel->tx_ring)
++ break;
++
++ DBGPR(" %s deleting tx timer\n", channel->name);
++ channel->tx_timer_active = 0;
++ hrtimer_cancel(&channel->tx_timer);
++ }
++
++ DBGPR("<--xgbe_stop_tx_timers\n");
++}
++
++void xgbe_a0_get_all_hw_features(struct xgbe_prv_data *pdata)
++{
++ unsigned int mac_hfr0, mac_hfr1, mac_hfr2;
++ struct xgbe_hw_features *hw_feat = &pdata->hw_feat;
++
++ DBGPR("-->xgbe_a0_get_all_hw_features\n");
++
++ mac_hfr0 = XGMAC_IOREAD(pdata, MAC_HWF0R);
++ mac_hfr1 = XGMAC_IOREAD(pdata, MAC_HWF1R);
++ mac_hfr2 = XGMAC_IOREAD(pdata, MAC_HWF2R);
++
++ memset(hw_feat, 0, sizeof(*hw_feat));
++
++ hw_feat->version = XGMAC_IOREAD(pdata, MAC_VR);
++
++ /* Hardware feature register 0 */
++ hw_feat->gmii = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, GMIISEL);
++ hw_feat->vlhash = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, VLHASH);
++ hw_feat->sma = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SMASEL);
++ hw_feat->rwk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RWKSEL);
++ hw_feat->mgk = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MGKSEL);
++ hw_feat->mmc = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, MMCSEL);
++ hw_feat->aoe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, ARPOFFSEL);
++ hw_feat->ts = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSEL);
++ hw_feat->eee = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, EEESEL);
++ hw_feat->tx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TXCOESEL);
++ hw_feat->rx_coe = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, RXCOESEL);
++ hw_feat->addn_mac = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R,
++ ADDMACADRSEL);
++ hw_feat->ts_src = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, TSSTSSEL);
++ hw_feat->sa_vlan_ins = XGMAC_GET_BITS(mac_hfr0, MAC_HWF0R, SAVLANINS);
++
++ /* Hardware feature register 1 */
++ hw_feat->rx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
++ RXFIFOSIZE);
++ hw_feat->tx_fifo_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
++ TXFIFOSIZE);
++ hw_feat->dcb = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DCBEN);
++ hw_feat->sph = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, SPHEN);
++ hw_feat->tso = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, TSOEN);
++ hw_feat->dma_debug = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, DBGMEMA);
++ hw_feat->tc_cnt = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R, NUMTC);
++ hw_feat->hash_table_size = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
++ HASHTBLSZ);
++ hw_feat->l3l4_filter_num = XGMAC_GET_BITS(mac_hfr1, MAC_HWF1R,
++ L3L4FNUM);
++
++ /* Hardware feature register 2 */
++ hw_feat->rx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXQCNT);
++ hw_feat->tx_q_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXQCNT);
++ hw_feat->rx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, RXCHCNT);
++ hw_feat->tx_ch_cnt = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, TXCHCNT);
++ hw_feat->pps_out_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, PPSOUTNUM);
++ hw_feat->aux_snap_num = XGMAC_GET_BITS(mac_hfr2, MAC_HWF2R, AUXSNAPNUM);
++
++ /* Translate the Hash Table size into actual number */
++ switch (hw_feat->hash_table_size) {
++ case 0:
++ break;
++ case 1:
++ hw_feat->hash_table_size = 64;
++ break;
++ case 2:
++ hw_feat->hash_table_size = 128;
++ break;
++ case 3:
++ hw_feat->hash_table_size = 256;
++ break;
++ }
++
++ /* The Queue and Channel counts are zero based so increment them
++ * to get the actual number
++ */
++ hw_feat->rx_q_cnt++;
++ hw_feat->tx_q_cnt++;
++ hw_feat->rx_ch_cnt++;
++ hw_feat->tx_ch_cnt++;
++
++#define XGBE_TC_CNT 2
++ hw_feat->tc_cnt = XGBE_TC_CNT;
++
++ DBGPR("<--xgbe_a0_get_all_hw_features\n");
++}
++
++static void xgbe_napi_enable(struct xgbe_prv_data *pdata, unsigned int add)
++{
++ struct xgbe_channel *channel;
++ unsigned int i;
++
++ if (pdata->per_channel_irq) {
++ channel = pdata->channel;
++ for (i = 0; i < pdata->channel_count; i++, channel++) {
++ if (add)
++ netif_napi_add(pdata->netdev, &channel->napi,
++ xgbe_one_poll, NAPI_POLL_WEIGHT);
++
++ napi_enable(&channel->napi);
++ }
++ } else {
++ if (add)
++ netif_napi_add(pdata->netdev, &pdata->napi,
++ xgbe_all_poll, NAPI_POLL_WEIGHT);
++
++ napi_enable(&pdata->napi);
++ }
++}
++
++static void xgbe_napi_disable(struct xgbe_prv_data *pdata, unsigned int del)
++{
++ struct xgbe_channel *channel;
++ unsigned int i;
++
++ if (pdata->per_channel_irq) {
++ channel = pdata->channel;
++ for (i = 0; i < pdata->channel_count; i++, channel++) {
++ napi_disable(&channel->napi);
++
++ if (del)
++ netif_napi_del(&channel->napi);
++ }
++ } else {
++ napi_disable(&pdata->napi);
++
++ if (del)
++ netif_napi_del(&pdata->napi);
++ }
++}
++
++void xgbe_a0_init_tx_coalesce(struct xgbe_prv_data *pdata)
++{
++ struct xgbe_hw_if *hw_if = &pdata->hw_if;
++
++ DBGPR("-->xgbe_a0_init_tx_coalesce\n");
++
++ pdata->tx_usecs = XGMAC_INIT_DMA_TX_USECS;
++ pdata->tx_frames = XGMAC_INIT_DMA_TX_FRAMES;
++
++ hw_if->config_tx_coalesce(pdata);
++
++ DBGPR("<--xgbe_a0_init_tx_coalesce\n");
++}
++
++void xgbe_a0_init_rx_coalesce(struct xgbe_prv_data *pdata)
++{
++ struct xgbe_hw_if *hw_if = &pdata->hw_if;
++
++ DBGPR("-->xgbe_a0_init_rx_coalesce\n");
++
++ pdata->rx_riwt = hw_if->usec_to_riwt(pdata, XGMAC_INIT_DMA_RX_USECS);
++ pdata->rx_frames = XGMAC_INIT_DMA_RX_FRAMES;
++
++ hw_if->config_rx_coalesce(pdata);
++
++ DBGPR("<--xgbe_a0_init_rx_coalesce\n");
++}
++
++static void xgbe_free_tx_data(struct xgbe_prv_data *pdata)
++{
++ struct xgbe_desc_if *desc_if = &pdata->desc_if;
++ struct xgbe_channel *channel;
++ struct xgbe_ring *ring;
++ struct xgbe_ring_data *rdata;
++ unsigned int i, j;
++
++ DBGPR("-->xgbe_free_tx_data\n");
++
++ channel = pdata->channel;
++ for (i = 0; i < pdata->channel_count; i++, channel++) {
++ ring = channel->tx_ring;
++ if (!ring)
++ break;
++
++ for (j = 0; j < ring->rdesc_count; j++) {
++ rdata = XGBE_GET_DESC_DATA(ring, j);
++ desc_if->unmap_rdata(pdata, rdata);
++ }
++ }
++
++ DBGPR("<--xgbe_free_tx_data\n");
++}
++
++static void xgbe_free_rx_data(struct xgbe_prv_data *pdata)
++{
++ struct xgbe_desc_if *desc_if = &pdata->desc_if;
++ struct xgbe_channel *channel;
++ struct xgbe_ring *ring;
++ struct xgbe_ring_data *rdata;
++ unsigned int i, j;
++
++ DBGPR("-->xgbe_free_rx_data\n");
++
++ channel = pdata->channel;
++ for (i = 0; i < pdata->channel_count; i++, channel++) {
++ ring = channel->rx_ring;
++ if (!ring)
++ break;
++
++ for (j = 0; j < ring->rdesc_count; j++) {
++ rdata = XGBE_GET_DESC_DATA(ring, j);
++ desc_if->unmap_rdata(pdata, rdata);
++ }
++ }
++
++ DBGPR("<--xgbe_free_rx_data\n");
++}
++
++static void xgbe_adjust_link(struct net_device *netdev)
++{
++ struct xgbe_prv_data *pdata = netdev_priv(netdev);
++ struct xgbe_hw_if *hw_if = &pdata->hw_if;
++ struct phy_device *phydev = pdata->phydev;
++ int new_state = 0;
++
++ if (!phydev)
++ return;
++
++ if (phydev->link) {
++ /* Flow control support */
++ if (pdata->pause_autoneg) {
++ if (phydev->pause || phydev->asym_pause) {
++ pdata->tx_pause = 1;
++ pdata->rx_pause = 1;
++ } else {
++ pdata->tx_pause = 0;
++ pdata->rx_pause = 0;
++ }
++ }
++
++ if (pdata->tx_pause != pdata->phy_tx_pause) {
++ hw_if->config_tx_flow_control(pdata);
++ pdata->phy_tx_pause = pdata->tx_pause;
++ }
++
++ if (pdata->rx_pause != pdata->phy_rx_pause) {
++ hw_if->config_rx_flow_control(pdata);
++ pdata->phy_rx_pause = pdata->rx_pause;
++ }
++
++ /* Speed support */
++ if (phydev->speed != pdata->phy_speed) {
++ new_state = 1;
++
++ switch (phydev->speed) {
++ case SPEED_10000:
++ hw_if->set_xgmii_speed(pdata);
++ break;
++
++ case SPEED_2500:
++ hw_if->set_gmii_2500_speed(pdata);
++ break;
++
++ case SPEED_1000:
++ hw_if->set_gmii_speed(pdata);
++ break;
++ }
++ pdata->phy_speed = phydev->speed;
++ }
++
++ if (phydev->link != pdata->phy_link) {
++ new_state = 1;
++ pdata->phy_link = 1;
++ }
++ } else if (pdata->phy_link) {
++ new_state = 1;
++ pdata->phy_link = 0;
++ pdata->phy_speed = SPEED_UNKNOWN;
++ }
++
++ if (new_state)
++ phy_print_status(phydev);
++}
++
++static int xgbe_phy_init(struct xgbe_prv_data *pdata)
++{
++ struct net_device *netdev = pdata->netdev;
++ struct phy_device *phydev = pdata->phydev;
++ int ret;
++
++ pdata->phy_link = -1;
++ pdata->phy_speed = SPEED_UNKNOWN;
++ pdata->phy_tx_pause = pdata->tx_pause;
++ pdata->phy_rx_pause = pdata->rx_pause;
++
++ ret = phy_connect_direct(netdev, phydev, &xgbe_adjust_link,
++ pdata->phy_mode);
++ if (ret) {
++ netdev_err(netdev, "phy_connect_direct failed\n");
++ return ret;
++ }
++
++ if (!phydev->drv || (phydev->drv->phy_id == 0)) {
++ netdev_err(netdev, "phy_id not valid\n");
++ ret = -ENODEV;
++ goto err_phy_connect;
++ }
++ DBGPR(" phy_connect_direct succeeded for PHY %s, link=%d\n",
++ dev_name(&phydev->dev), phydev->link);
++
++ return 0;
++
++err_phy_connect:
++ phy_disconnect(phydev);
++
++ return ret;
++}
++
++static void xgbe_phy_exit(struct xgbe_prv_data *pdata)
++{
++ if (!pdata->phydev)
++ return;
++
++ phy_disconnect(pdata->phydev);
++}
++
++int xgbe_a0_powerdown(struct net_device *netdev, unsigned int caller)
++{
++ struct xgbe_prv_data *pdata = netdev_priv(netdev);
++ struct xgbe_hw_if *hw_if = &pdata->hw_if;
++ unsigned long flags;
++
++ DBGPR("-->xgbe_a0_powerdown\n");
++
++ if (!netif_running(netdev) ||
++ (caller == XGMAC_IOCTL_CONTEXT && pdata->power_down)) {
++ netdev_alert(netdev, "Device is already powered down\n");
++ DBGPR("<--xgbe_a0_powerdown\n");
++ return -EINVAL;
++ }
++
++ phy_stop(pdata->phydev);
++
++ spin_lock_irqsave(&pdata->lock, flags);
++
++ if (caller == XGMAC_DRIVER_CONTEXT)
++ netif_device_detach(netdev);
++
++ netif_tx_stop_all_queues(netdev);
++ xgbe_napi_disable(pdata, 0);
++
++ /* Powerdown Tx/Rx */
++ hw_if->powerdown_tx(pdata);
++ hw_if->powerdown_rx(pdata);
++
++ pdata->power_down = 1;
++
++ spin_unlock_irqrestore(&pdata->lock, flags);
++
++ DBGPR("<--xgbe_a0_powerdown\n");
++
++ return 0;
++}
++
++int xgbe_a0_powerup(struct net_device *netdev, unsigned int caller)
++{
++ struct xgbe_prv_data *pdata = netdev_priv(netdev);
++ struct xgbe_hw_if *hw_if = &pdata->hw_if;
++ unsigned long flags;
++
++ DBGPR("-->xgbe_a0_powerup\n");
++
++ if (!netif_running(netdev) ||
++ (caller == XGMAC_IOCTL_CONTEXT && !pdata->power_down)) {
++ netdev_alert(netdev, "Device is already powered up\n");
++ DBGPR("<--xgbe_a0_powerup\n");
++ return -EINVAL;
++ }
++
++ spin_lock_irqsave(&pdata->lock, flags);
++
++ pdata->power_down = 0;
++
++ phy_start(pdata->phydev);
++
++ /* Enable Tx/Rx */
++ hw_if->powerup_tx(pdata);
++ hw_if->powerup_rx(pdata);
++
++ if (caller == XGMAC_DRIVER_CONTEXT)
++ netif_device_attach(netdev);
++
++ xgbe_napi_enable(pdata, 0);
++ netif_tx_start_all_queues(netdev);
++
++ spin_unlock_irqrestore(&pdata->lock, flags);
++
++ DBGPR("<--xgbe_a0_powerup\n");
++
++ return 0;
++}
++
++static int xgbe_start(struct xgbe_prv_data *pdata)
++{
++ struct xgbe_hw_if *hw_if = &pdata->hw_if;
++ struct net_device *netdev = pdata->netdev;
++
++ DBGPR("-->xgbe_start\n");
++
++ xgbe_set_rx_mode(netdev);
++
++ hw_if->init(pdata);
++
++ phy_start(pdata->phydev);
++
++ hw_if->enable_tx(pdata);
++ hw_if->enable_rx(pdata);
++
++ xgbe_init_tx_timers(pdata);
++
++ xgbe_napi_enable(pdata, 1);
++ netif_tx_start_all_queues(netdev);
++
++ DBGPR("<--xgbe_start\n");
++
++ return 0;
++}
++
++static void xgbe_stop(struct xgbe_prv_data *pdata)
++{
++ struct xgbe_hw_if *hw_if = &pdata->hw_if;
++ struct xgbe_channel *channel;
++ struct net_device *netdev = pdata->netdev;
++ struct netdev_queue *txq;
++ unsigned int i;
++
++ DBGPR("-->xgbe_stop\n");
++
++ phy_stop(pdata->phydev);
++
++ netif_tx_stop_all_queues(netdev);
++ xgbe_napi_disable(pdata, 1);
++
++ xgbe_stop_tx_timers(pdata);
++
++ hw_if->disable_tx(pdata);
++ hw_if->disable_rx(pdata);
++
++ channel = pdata->channel;
++ for (i = 0; i < pdata->channel_count; i++, channel++) {
++ if (!channel->tx_ring)
++ continue;
++
++ txq = netdev_get_tx_queue(netdev, channel->queue_index);
++ netdev_tx_reset_queue(txq);
++ }
++
++ DBGPR("<--xgbe_stop\n");
++}
++
++static void xgbe_restart_dev(struct xgbe_prv_data *pdata)
++{
++ struct xgbe_channel *channel;
++ struct xgbe_hw_if *hw_if = &pdata->hw_if;
++ unsigned int i;
++
++ DBGPR("-->xgbe_restart_dev\n");
++
++ /* If not running, "restart" will happen on open */
++ if (!netif_running(pdata->netdev))
++ return;
++
++ xgbe_stop(pdata);
++ synchronize_irq(pdata->dev_irq);
++ if (pdata->per_channel_irq) {
++ channel = pdata->channel;
++ for (i = 0; i < pdata->channel_count; i++, channel++)
++ synchronize_irq(channel->dma_irq);
++ }
++
++ xgbe_free_tx_data(pdata);
++ xgbe_free_rx_data(pdata);
++
++ /* Issue software reset to device */
++ hw_if->exit(pdata);
++
++ xgbe_start(pdata);
++
++ DBGPR("<--xgbe_restart_dev\n");
++}
++
++static void xgbe_restart(struct work_struct *work)
++{
++ struct xgbe_prv_data *pdata = container_of(work,
++ struct xgbe_prv_data,
++ restart_work);
++
++ rtnl_lock();
++
++ xgbe_restart_dev(pdata);
++
++ rtnl_unlock();
++}
++
++static void xgbe_tx_tstamp(struct work_struct *work)
++{
++ struct xgbe_prv_data *pdata = container_of(work,
++ struct xgbe_prv_data,
++ tx_tstamp_work);
++ struct skb_shared_hwtstamps hwtstamps;
++ u64 nsec;
++ unsigned long flags;
++
++ if (pdata->tx_tstamp) {
++ nsec = timecounter_cyc2time(&pdata->tstamp_tc,
++ pdata->tx_tstamp);
++
++ memset(&hwtstamps, 0, sizeof(hwtstamps));
++ hwtstamps.hwtstamp = ns_to_ktime(nsec);
++ skb_tstamp_tx(pdata->tx_tstamp_skb, &hwtstamps);
++ }
++
++ dev_kfree_skb_any(pdata->tx_tstamp_skb);
++
++ spin_lock_irqsave(&pdata->tstamp_lock, flags);
++ pdata->tx_tstamp_skb = NULL;
++ spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
++}
++
++static int xgbe_get_hwtstamp_settings(struct xgbe_prv_data *pdata,
++ struct ifreq *ifreq)
++{
++ if (copy_to_user(ifreq->ifr_data, &pdata->tstamp_config,
++ sizeof(pdata->tstamp_config)))
++ return -EFAULT;
++
++ return 0;
++}
++
++static int xgbe_set_hwtstamp_settings(struct xgbe_prv_data *pdata,
++ struct ifreq *ifreq)
++{
++ struct hwtstamp_config config;
++ unsigned int mac_tscr;
++
++ if (copy_from_user(&config, ifreq->ifr_data, sizeof(config)))
++ return -EFAULT;
++
++ if (config.flags)
++ return -EINVAL;
++
++ mac_tscr = 0;
++
++ switch (config.tx_type) {
++ case HWTSTAMP_TX_OFF:
++ break;
++
++ case HWTSTAMP_TX_ON:
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
++ break;
++
++ default:
++ return -ERANGE;
++ }
++
++ switch (config.rx_filter) {
++ case HWTSTAMP_FILTER_NONE:
++ break;
++
++ case HWTSTAMP_FILTER_ALL:
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENALL, 1);
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
++ break;
++
++ /* PTP v2, UDP, any kind of event packet */
++ case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
++ /* PTP v1, UDP, any kind of event packet */
++ case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
++ break;
++
++ /* PTP v2, UDP, Sync packet */
++ case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
++ /* PTP v1, UDP, Sync packet */
++ case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
++ break;
++
++ /* PTP v2, UDP, Delay_req packet */
++ case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
++ /* PTP v1, UDP, Delay_req packet */
++ case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
++ break;
++
++ /* 802.AS1, Ethernet, any kind of event packet */
++ case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
++ break;
++
++ /* 802.AS1, Ethernet, Sync packet */
++ case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
++ break;
++
++ /* 802.AS1, Ethernet, Delay_req packet */
++ case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, AV8021ASMEN, 1);
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
++ break;
++
++ /* PTP v2/802.AS1, any layer, any kind of event packet */
++ case HWTSTAMP_FILTER_PTP_V2_EVENT:
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, SNAPTYPSEL, 1);
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
++ break;
++
++ /* PTP v2/802.AS1, any layer, Sync packet */
++ case HWTSTAMP_FILTER_PTP_V2_SYNC:
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
++ break;
++
++ /* PTP v2/802.AS1, any layer, Delay_req packet */
++ case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSVER2ENA, 1);
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPENA, 1);
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV4ENA, 1);
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSIPV6ENA, 1);
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSMSTRENA, 1);
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSEVNTENA, 1);
++ XGMAC_SET_BITS(mac_tscr, MAC_TSCR, TSENA, 1);
++ break;
++
++ default:
++ return -ERANGE;
++ }
++
++ pdata->hw_if.config_tstamp(pdata, mac_tscr);
++
++ memcpy(&pdata->tstamp_config, &config, sizeof(config));
++
++ return 0;
++}
++
++static void xgbe_prep_tx_tstamp(struct xgbe_prv_data *pdata,
++ struct sk_buff *skb,
++ struct xgbe_packet_data *packet)
++{
++ unsigned long flags;
++
++ if (XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP)) {
++ spin_lock_irqsave(&pdata->tstamp_lock, flags);
++ if (pdata->tx_tstamp_skb) {
++ /* Another timestamp in progress, ignore this one */
++ XGMAC_SET_BITS(packet->attributes,
++ TX_PACKET_ATTRIBUTES, PTP, 0);
++ } else {
++ pdata->tx_tstamp_skb = skb_get(skb);
++ skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
++ }
++ spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
++ }
++
++ if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES, PTP))
++ skb_tx_timestamp(skb);
++}
++
++static void xgbe_prep_vlan(struct sk_buff *skb, struct xgbe_packet_data *packet)
++{
++ if (skb_vlan_tag_present(skb))
++ packet->vlan_ctag = skb_vlan_tag_get(skb);
++}
++
++static int xgbe_prep_tso(struct sk_buff *skb, struct xgbe_packet_data *packet)
++{
++ int ret;
++
++ if (!XGMAC_GET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
++ TSO_ENABLE))
++ return 0;
++
++ ret = skb_cow_head(skb, 0);
++ if (ret)
++ return ret;
++
++ packet->header_len = skb_transport_offset(skb) + tcp_hdrlen(skb);
++ packet->tcp_header_len = tcp_hdrlen(skb);
++ packet->tcp_payload_len = skb->len - packet->header_len;
++ packet->mss = skb_shinfo(skb)->gso_size;
++ DBGPR(" packet->header_len=%u\n", packet->header_len);
++ DBGPR(" packet->tcp_header_len=%u, packet->tcp_payload_len=%u\n",
++ packet->tcp_header_len, packet->tcp_payload_len);
++ DBGPR(" packet->mss=%u\n", packet->mss);
++
++ /* Update the number of packets that will ultimately be transmitted
++ * along with the extra bytes for each extra packet
++ */
++ packet->tx_packets = skb_shinfo(skb)->gso_segs;
++ packet->tx_bytes += (packet->tx_packets - 1) * packet->header_len;
++
++ return 0;
++}
++
++static int xgbe_is_tso(struct sk_buff *skb)
++{
++ if (skb->ip_summed != CHECKSUM_PARTIAL)
++ return 0;
++
++ if (!skb_is_gso(skb))
++ return 0;
++
++ DBGPR(" TSO packet to be processed\n");
++
++ return 1;
++}
++
++static void xgbe_packet_info(struct xgbe_prv_data *pdata,
++ struct xgbe_ring *ring, struct sk_buff *skb,
++ struct xgbe_packet_data *packet)
++{
++ struct skb_frag_struct *frag;
++ unsigned int context_desc;
++ unsigned int len;
++ unsigned int i;
++
++ packet->skb = skb;
++
++ context_desc = 0;
++ packet->rdesc_count = 0;
++
++ packet->tx_packets = 1;
++ packet->tx_bytes = skb->len;
++
++ if (xgbe_is_tso(skb)) {
++ /* TSO requires an extra descriptor if mss is different */
++ if (skb_shinfo(skb)->gso_size != ring->tx.cur_mss) {
++ context_desc = 1;
++ packet->rdesc_count++;
++ }
++
++ /* TSO requires an extra descriptor for TSO header */
++ packet->rdesc_count++;
++
++ XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
++ TSO_ENABLE, 1);
++ XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
++ CSUM_ENABLE, 1);
++ } else if (skb->ip_summed == CHECKSUM_PARTIAL)
++ XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
++ CSUM_ENABLE, 1);
++
++ if (skb_vlan_tag_present(skb)) {
++ /* VLAN requires an extra descriptor if tag is different */
++ if (skb_vlan_tag_get(skb) != ring->tx.cur_vlan_ctag)
++ /* We can share with the TSO context descriptor */
++ if (!context_desc) {
++ context_desc = 1;
++ packet->rdesc_count++;
++ }
++
++ XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
++ VLAN_CTAG, 1);
++ }
++
++ if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
++ (pdata->tstamp_config.tx_type == HWTSTAMP_TX_ON))
++ XGMAC_SET_BITS(packet->attributes, TX_PACKET_ATTRIBUTES,
++ PTP, 1);
++
++ for (len = skb_headlen(skb); len;) {
++ packet->rdesc_count++;
++ len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
++ }
++
++ for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
++ frag = &skb_shinfo(skb)->frags[i];
++ for (len = skb_frag_size(frag); len; ) {
++ packet->rdesc_count++;
++ len -= min_t(unsigned int, len, XGBE_TX_MAX_BUF_SIZE);
++ }
++ }
++}
++
++static int xgbe_open(struct net_device *netdev)
++{
++ struct xgbe_prv_data *pdata = netdev_priv(netdev);
++ struct xgbe_hw_if *hw_if = &pdata->hw_if;
++ struct xgbe_desc_if *desc_if = &pdata->desc_if;
++ struct xgbe_channel *channel = NULL;
++ unsigned int i = 0;
++ int ret;
++
++ DBGPR("-->xgbe_open\n");
++
++ /* Initialize the phy */
++ ret = xgbe_phy_init(pdata);
++ if (ret)
++ return ret;
++
++ /* Enable the clocks */
++ ret = clk_prepare_enable(pdata->sysclk);
++ if (ret) {
++ netdev_alert(netdev, "dma clk_prepare_enable failed\n");
++ goto err_phy_init;
++ }
++
++ ret = clk_prepare_enable(pdata->ptpclk);
++ if (ret) {
++ netdev_alert(netdev, "ptp clk_prepare_enable failed\n");
++ goto err_sysclk;
++ }
++
++ /* Calculate the Rx buffer size before allocating rings */
++ ret = xgbe_calc_rx_buf_size(netdev, netdev->mtu);
++ if (ret < 0)
++ goto err_ptpclk;
++ pdata->rx_buf_size = ret;
++
++ /* Allocate the channel and ring structures */
++ ret = xgbe_alloc_channels(pdata);
++ if (ret)
++ goto err_ptpclk;
++
++ /* Allocate the ring descriptors and buffers */
++ ret = desc_if->alloc_ring_resources(pdata);
++ if (ret)
++ goto err_channels;
++
++ /* Initialize the device restart and Tx timestamp work struct */
++ INIT_WORK(&pdata->restart_work, xgbe_restart);
++ INIT_WORK(&pdata->tx_tstamp_work, xgbe_tx_tstamp);
++
++ /* Request interrupts */
++ ret = devm_request_irq(pdata->dev, pdata->dev_irq, xgbe_isr, 0,
++ netdev->name, pdata);
++ if (ret) {
++ netdev_alert(netdev, "error requesting irq %d\n",
++ pdata->dev_irq);
++ goto err_rings;
++ }
++
++ if (pdata->per_channel_irq) {
++ channel = pdata->channel;
++ for (i = 0; i < pdata->channel_count; i++, channel++) {
++ snprintf(channel->dma_irq_name,
++ sizeof(channel->dma_irq_name) - 1,
++ "%s-TxRx-%u", netdev_name(netdev),
++ channel->queue_index);
++
++ ret = devm_request_irq(pdata->dev, channel->dma_irq,
++ xgbe_dma_isr, 0,
++ channel->dma_irq_name, channel);
++ if (ret) {
++ netdev_alert(netdev,
++ "error requesting irq %d\n",
++ channel->dma_irq);
++ goto err_irq;
++ }
++ }
++ }
++
++ ret = xgbe_start(pdata);
++ if (ret)
++ goto err_start;
++
++ DBGPR("<--xgbe_open\n");
++
++ return 0;
++
++err_start:
++ hw_if->exit(pdata);
++
++err_irq:
++ if (pdata->per_channel_irq) {
++ /* Using an unsigned int, 'i' will go to UINT_MAX and exit */
++ for (i--, channel--; i < pdata->channel_count; i--, channel--)
++ devm_free_irq(pdata->dev, channel->dma_irq, channel);
++ }
++
++ devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
++
++err_rings:
++ desc_if->free_ring_resources(pdata);
++
++err_channels:
++ xgbe_free_channels(pdata);
++
++err_ptpclk:
++ clk_disable_unprepare(pdata->ptpclk);
++
++err_sysclk:
++ clk_disable_unprepare(pdata->sysclk);
++
++err_phy_init:
++ xgbe_phy_exit(pdata);
++
++ return ret;
++}
++
++static int xgbe_close(struct net_device *netdev)
++{
++ struct xgbe_prv_data *pdata = netdev_priv(netdev);
++ struct xgbe_hw_if *hw_if = &pdata->hw_if;
++ struct xgbe_desc_if *desc_if = &pdata->desc_if;
++ struct xgbe_channel *channel;
++ unsigned int i;
++
++ DBGPR("-->xgbe_close\n");
++
++ /* Stop the device */
++ xgbe_stop(pdata);
++
++ /* Issue software reset to device */
++ hw_if->exit(pdata);
++
++ /* Free the ring descriptors and buffers */
++ desc_if->free_ring_resources(pdata);
++
++ /* Release the interrupts */
++ devm_free_irq(pdata->dev, pdata->dev_irq, pdata);
++ if (pdata->per_channel_irq) {
++ channel = pdata->channel;
++ for (i = 0; i < pdata->channel_count; i++, channel++)
++ devm_free_irq(pdata->dev, channel->dma_irq, channel);
++ }
++
++ /* Free the channel and ring structures */
++ xgbe_free_channels(pdata);
++
++ /* Disable the clocks */
++ clk_disable_unprepare(pdata->ptpclk);
++ clk_disable_unprepare(pdata->sysclk);
++
++ /* Release the phy */
++ xgbe_phy_exit(pdata);
++
++ DBGPR("<--xgbe_close\n");
++
++ return 0;
++}
++
++static int xgbe_xmit(struct sk_buff *skb, struct net_device *netdev)
++{
++ struct xgbe_prv_data *pdata = netdev_priv(netdev);
++ struct xgbe_hw_if *hw_if = &pdata->hw_if;
++ struct xgbe_desc_if *desc_if = &pdata->desc_if;
++ struct xgbe_channel *channel;
++ struct xgbe_ring *ring;
++ struct xgbe_packet_data *packet;
++ struct netdev_queue *txq;
++ int ret;
++
++ DBGPR("-->xgbe_xmit: skb->len = %d\n", skb->len);
++
++ channel = pdata->channel + skb->queue_mapping;
++ txq = netdev_get_tx_queue(netdev, channel->queue_index);
++ ring = channel->tx_ring;
++ packet = &ring->packet_data;
++
++ ret = NETDEV_TX_OK;
++
++ if (skb->len == 0) {
++ netdev_err(netdev, "empty skb received from stack\n");
++ dev_kfree_skb_any(skb);
++ goto tx_netdev_return;
++ }
++
++ /* Calculate preliminary packet info */
++ memset(packet, 0, sizeof(*packet));
++ xgbe_packet_info(pdata, ring, skb, packet);
++
++ /* Check that there are enough descriptors available */
++ ret = xgbe_maybe_stop_tx_queue(channel, ring, packet->rdesc_count);
++ if (ret)
++ goto tx_netdev_return;
++
++ ret = xgbe_prep_tso(skb, packet);
++ if (ret) {
++ netdev_err(netdev, "error processing TSO packet\n");
++ dev_kfree_skb_any(skb);
++ goto tx_netdev_return;
++ }
++ xgbe_prep_vlan(skb, packet);
++
++ if (!desc_if->map_tx_skb(channel, skb)) {
++ dev_kfree_skb_any(skb);
++ goto tx_netdev_return;
++ }
++
++ xgbe_prep_tx_tstamp(pdata, skb, packet);
++
++ /* Report on the actual number of bytes (to be) sent */
++ netdev_tx_sent_queue(txq, packet->tx_bytes);
++
++ /* Configure required descriptor fields for transmission */
++ hw_if->dev_xmit(channel);
++
++#ifdef XGMAC_ENABLE_TX_PKT_DUMP
++ xgbe_a0_print_pkt(netdev, skb, true);
++#endif
++
++ /* Stop the queue in advance if there may not be enough descriptors */
++ xgbe_maybe_stop_tx_queue(channel, ring, XGBE_TX_MAX_DESCS);
++
++ ret = NETDEV_TX_OK;
++
++tx_netdev_return:
++ return ret;
++}
++
++static void xgbe_set_rx_mode(struct net_device *netdev)
++{
++ struct xgbe_prv_data *pdata = netdev_priv(netdev);
++ struct xgbe_hw_if *hw_if = &pdata->hw_if;
++ unsigned int pr_mode, am_mode;
++
++ DBGPR("-->xgbe_set_rx_mode\n");
++
++ pr_mode = ((netdev->flags & IFF_PROMISC) != 0);
++ am_mode = ((netdev->flags & IFF_ALLMULTI) != 0);
++
++ hw_if->set_promiscuous_mode(pdata, pr_mode);
++ hw_if->set_all_multicast_mode(pdata, am_mode);
++
++ hw_if->add_mac_addresses(pdata);
++
++ DBGPR("<--xgbe_set_rx_mode\n");
++}
++
++static int xgbe_set_mac_address(struct net_device *netdev, void *addr)
++{
++ struct xgbe_prv_data *pdata = netdev_priv(netdev);
++ struct xgbe_hw_if *hw_if = &pdata->hw_if;
++ struct sockaddr *saddr = addr;
++
++ DBGPR("-->xgbe_set_mac_address\n");
++
++ if (!is_valid_ether_addr(saddr->sa_data))
++ return -EADDRNOTAVAIL;
++
++ memcpy(netdev->dev_addr, saddr->sa_data, netdev->addr_len);
++
++ hw_if->set_mac_address(pdata, netdev->dev_addr);
++
++ DBGPR("<--xgbe_set_mac_address\n");
++
++ return 0;
++}
++
++static int xgbe_ioctl(struct net_device *netdev, struct ifreq *ifreq, int cmd)
++{
++ struct xgbe_prv_data *pdata = netdev_priv(netdev);
++ int ret;
++
++ switch (cmd) {
++ case SIOCGHWTSTAMP:
++ ret = xgbe_get_hwtstamp_settings(pdata, ifreq);
++ break;
++
++ case SIOCSHWTSTAMP:
++ ret = xgbe_set_hwtstamp_settings(pdata, ifreq);
++ break;
++
++ default:
++ ret = -EOPNOTSUPP;
++ }
++
++ return ret;
++}
++
++static int xgbe_change_mtu(struct net_device *netdev, int mtu)
++{
++ struct xgbe_prv_data *pdata = netdev_priv(netdev);
++ int ret;
++
++ DBGPR("-->xgbe_change_mtu\n");
++
++ ret = xgbe_calc_rx_buf_size(netdev, mtu);
++ if (ret < 0)
++ return ret;
++
++ pdata->rx_buf_size = ret;
++ netdev->mtu = mtu;
++
++ xgbe_restart_dev(pdata);
++
++ DBGPR("<--xgbe_change_mtu\n");
++
++ return 0;
++}
++
++static struct rtnl_link_stats64 *xgbe_get_stats64(struct net_device *netdev,
++ struct rtnl_link_stats64 *s)
++{
++ struct xgbe_prv_data *pdata = netdev_priv(netdev);
++ struct xgbe_mmc_stats *pstats = &pdata->mmc_stats;
++
++ DBGPR("-->%s\n", __func__);
++
++ pdata->hw_if.read_mmc_stats(pdata);
++
++ s->rx_packets = pstats->rxframecount_gb;
++ s->rx_bytes = pstats->rxoctetcount_gb;
++ s->rx_errors = pstats->rxframecount_gb -
++ pstats->rxbroadcastframes_g -
++ pstats->rxmulticastframes_g -
++ pstats->rxunicastframes_g;
++ s->multicast = pstats->rxmulticastframes_g;
++ s->rx_length_errors = pstats->rxlengtherror;
++ s->rx_crc_errors = pstats->rxcrcerror;
++ s->rx_fifo_errors = pstats->rxfifooverflow;
++
++ s->tx_packets = pstats->txframecount_gb;
++ s->tx_bytes = pstats->txoctetcount_gb;
++ s->tx_errors = pstats->txframecount_gb - pstats->txframecount_g;
++ s->tx_dropped = netdev->stats.tx_dropped;
++
++ DBGPR("<--%s\n", __func__);
++
++ return s;
++}
++
++static int xgbe_vlan_rx_add_vid(struct net_device *netdev, __be16 proto,
++ u16 vid)
++{
++ struct xgbe_prv_data *pdata = netdev_priv(netdev);
++ struct xgbe_hw_if *hw_if = &pdata->hw_if;
++
++ DBGPR("-->%s\n", __func__);
++
++ set_bit(vid, pdata->active_vlans);
++ hw_if->update_vlan_hash_table(pdata);
++
++ DBGPR("<--%s\n", __func__);
++
++ return 0;
++}
++
++static int xgbe_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto,
++ u16 vid)
++{
++ struct xgbe_prv_data *pdata = netdev_priv(netdev);
++ struct xgbe_hw_if *hw_if = &pdata->hw_if;
++
++ DBGPR("-->%s\n", __func__);
++
++ clear_bit(vid, pdata->active_vlans);
++ hw_if->update_vlan_hash_table(pdata);
++
++ DBGPR("<--%s\n", __func__);
++
++ return 0;
++}
++
++#ifdef CONFIG_NET_POLL_CONTROLLER
++static void xgbe_poll_controller(struct net_device *netdev)
++{
++ struct xgbe_prv_data *pdata = netdev_priv(netdev);
++ struct xgbe_channel *channel;
++ unsigned int i;
++
++ DBGPR("-->xgbe_poll_controller\n");
++
++ if (pdata->per_channel_irq) {
++ channel = pdata->channel;
++ for (i = 0; i < pdata->channel_count; i++, channel++)
++ xgbe_dma_isr(channel->dma_irq, channel);
++ } else {
++ disable_irq(pdata->dev_irq);
++ xgbe_isr(pdata->dev_irq, pdata);
++ enable_irq(pdata->dev_irq);
++ }
++
++ DBGPR("<--xgbe_poll_controller\n");
++}
++#endif /* End CONFIG_NET_POLL_CONTROLLER */
++
++static int xgbe_setup_tc(struct net_device *netdev, u8 tc)
++{
++ struct xgbe_prv_data *pdata = netdev_priv(netdev);
++ unsigned int offset, queue;
++ u8 i;
++
++ if (tc && (tc != pdata->hw_feat.tc_cnt))
++ return -EINVAL;
++
++ if (tc) {
++ netdev_set_num_tc(netdev, tc);
++ for (i = 0, queue = 0, offset = 0; i < tc; i++) {
++ while ((queue < pdata->tx_q_count) &&
++ (pdata->q2tc_map[queue] == i))
++ queue++;
++
++ DBGPR(" TC%u using TXq%u-%u\n", i, offset, queue - 1);
++ netdev_set_tc_queue(netdev, i, queue - offset, offset);
++ offset = queue;
++ }
++ } else {
++ netdev_reset_tc(netdev);
++ }
++
++ return 0;
++}
++
++static int xgbe_set_features(struct net_device *netdev,
++ netdev_features_t features)
++{
++ struct xgbe_prv_data *pdata = netdev_priv(netdev);
++ struct xgbe_hw_if *hw_if = &pdata->hw_if;
++ netdev_features_t rxhash, rxcsum, rxvlan, rxvlan_filter;
++ int ret = 0;
++
++ rxhash = pdata->netdev_features & NETIF_F_RXHASH;
++ rxcsum = pdata->netdev_features & NETIF_F_RXCSUM;
++ rxvlan = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_RX;
++ rxvlan_filter = pdata->netdev_features & NETIF_F_HW_VLAN_CTAG_FILTER;
++
++ if ((features & NETIF_F_RXHASH) && !rxhash)
++ ret = hw_if->enable_rss(pdata);
++ else if (!(features & NETIF_F_RXHASH) && rxhash)
++ ret = hw_if->disable_rss(pdata);
++ if (ret)
++ return ret;
++
++ if ((features & NETIF_F_RXCSUM) && !rxcsum)
++ hw_if->enable_rx_csum(pdata);
++ else if (!(features & NETIF_F_RXCSUM) && rxcsum)
++ hw_if->disable_rx_csum(pdata);
++
++ if ((features & NETIF_F_HW_VLAN_CTAG_RX) && !rxvlan)
++ hw_if->enable_rx_vlan_stripping(pdata);
++ else if (!(features & NETIF_F_HW_VLAN_CTAG_RX) && rxvlan)
++ hw_if->disable_rx_vlan_stripping(pdata);
++
++ if ((features & NETIF_F_HW_VLAN_CTAG_FILTER) && !rxvlan_filter)
++ hw_if->enable_rx_vlan_filtering(pdata);
++ else if (!(features & NETIF_F_HW_VLAN_CTAG_FILTER) && rxvlan_filter)
++ hw_if->disable_rx_vlan_filtering(pdata);
++
++ pdata->netdev_features = features;
++
++ DBGPR("<--xgbe_set_features\n");
++
++ return 0;
++}
++
++static const struct net_device_ops xgbe_netdev_ops = {
++ .ndo_open = xgbe_open,
++ .ndo_stop = xgbe_close,
++ .ndo_start_xmit = xgbe_xmit,
++ .ndo_set_rx_mode = xgbe_set_rx_mode,
++ .ndo_set_mac_address = xgbe_set_mac_address,
++ .ndo_validate_addr = eth_validate_addr,
++ .ndo_do_ioctl = xgbe_ioctl,
++ .ndo_change_mtu = xgbe_change_mtu,
++ .ndo_get_stats64 = xgbe_get_stats64,
++ .ndo_vlan_rx_add_vid = xgbe_vlan_rx_add_vid,
++ .ndo_vlan_rx_kill_vid = xgbe_vlan_rx_kill_vid,
++#ifdef CONFIG_NET_POLL_CONTROLLER
++ .ndo_poll_controller = xgbe_poll_controller,
++#endif
++ .ndo_setup_tc = xgbe_setup_tc,
++ .ndo_set_features = xgbe_set_features,
++};
++
++struct net_device_ops *xgbe_a0_get_netdev_ops(void)
++{
++ return (struct net_device_ops *)&xgbe_netdev_ops;
++}
++
++static void xgbe_rx_refresh(struct xgbe_channel *channel)
++{
++ struct xgbe_prv_data *pdata = channel->pdata;
++ struct xgbe_hw_if *hw_if = &pdata->hw_if;
++ struct xgbe_desc_if *desc_if = &pdata->desc_if;
++ struct xgbe_ring *ring = channel->rx_ring;
++ struct xgbe_ring_data *rdata;
++
++ while (ring->dirty != ring->cur) {
++ rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
++
++ /* Reset rdata values */
++ desc_if->unmap_rdata(pdata, rdata);
++
++ if (desc_if->map_rx_buffer(pdata, ring, rdata))
++ break;
++
++ hw_if->rx_desc_reset(rdata);
++
++ ring->dirty++;
++ }
++
++ /* Update the Rx Tail Pointer Register with address of
++ * the last cleaned entry */
++ rdata = XGBE_GET_DESC_DATA(ring, ring->dirty - 1);
++ XGMAC_DMA_IOWRITE(channel, DMA_CH_RDTR_LO,
++ lower_32_bits(rdata->rdesc_dma));
++}
++
++static struct sk_buff *xgbe_create_skb(struct xgbe_prv_data *pdata,
++ struct xgbe_ring_data *rdata,
++ unsigned int *len)
++{
++ struct net_device *netdev = pdata->netdev;
++ struct sk_buff *skb;
++ u8 *packet;
++ unsigned int copy_len;
++
++ skb = netdev_alloc_skb_ip_align(netdev, rdata->rx.hdr.dma_len);
++ if (!skb)
++ return NULL;
++
++ packet = page_address(rdata->rx.hdr.pa.pages) +
++ rdata->rx.hdr.pa.pages_offset;
++ copy_len = (rdata->rx.hdr_len) ? rdata->rx.hdr_len : *len;
++ copy_len = min(rdata->rx.hdr.dma_len, copy_len);
++ skb_copy_to_linear_data(skb, packet, copy_len);
++ skb_put(skb, copy_len);
++
++ *len -= copy_len;
++
++ return skb;
++}
++
++static int xgbe_tx_poll(struct xgbe_channel *channel)
++{
++ struct xgbe_prv_data *pdata = channel->pdata;
++ struct xgbe_hw_if *hw_if = &pdata->hw_if;
++ struct xgbe_desc_if *desc_if = &pdata->desc_if;
++ struct xgbe_ring *ring = channel->tx_ring;
++ struct xgbe_ring_data *rdata;
++ struct xgbe_ring_desc *rdesc;
++ struct net_device *netdev = pdata->netdev;
++ struct netdev_queue *txq;
++ int processed = 0;
++ unsigned int tx_packets = 0, tx_bytes = 0;
++
++ DBGPR("-->xgbe_tx_poll\n");
++
++ /* Nothing to do if there isn't a Tx ring for this channel */
++ if (!ring)
++ return 0;
++
++ txq = netdev_get_tx_queue(netdev, channel->queue_index);
++
++ while ((processed < XGBE_TX_DESC_MAX_PROC) &&
++ (ring->dirty != ring->cur)) {
++ rdata = XGBE_GET_DESC_DATA(ring, ring->dirty);
++ rdesc = rdata->rdesc;
++
++ if (!hw_if->tx_complete(rdesc))
++ break;
++
++ /* Make sure descriptor fields are read after reading the OWN
++ * bit */
++ rmb();
++
++#ifdef XGMAC_ENABLE_TX_DESC_DUMP
++ xgbe_a0_dump_tx_desc(ring, ring->dirty, 1, 0);
++#endif
++
++ if (hw_if->is_last_desc(rdesc)) {
++ tx_packets += rdata->tx.packets;
++ tx_bytes += rdata->tx.bytes;
++ }
++
++ /* Free the SKB and reset the descriptor for re-use */
++ desc_if->unmap_rdata(pdata, rdata);
++ hw_if->tx_desc_reset(rdata);
++
++ processed++;
++ ring->dirty++;
++ }
++
++ if (!processed)
++ return 0;
++
++ netdev_tx_completed_queue(txq, tx_packets, tx_bytes);
++
++ if ((ring->tx.queue_stopped == 1) &&
++ (xgbe_tx_avail_desc(ring) > XGBE_TX_DESC_MIN_FREE)) {
++ ring->tx.queue_stopped = 0;
++ netif_tx_wake_queue(txq);
++ }
++
++ DBGPR("<--xgbe_tx_poll: processed=%d\n", processed);
++
++ return processed;
++}
++
++static int xgbe_rx_poll(struct xgbe_channel *channel, int budget)
++{
++ struct xgbe_prv_data *pdata = channel->pdata;
++ struct xgbe_hw_if *hw_if = &pdata->hw_if;
++ struct xgbe_ring *ring = channel->rx_ring;
++ struct xgbe_ring_data *rdata;
++ struct xgbe_packet_data *packet;
++ struct net_device *netdev = pdata->netdev;
++ struct napi_struct *napi;
++ struct sk_buff *skb;
++ struct skb_shared_hwtstamps *hwtstamps;
++ unsigned int incomplete, error, context_next, context;
++ unsigned int len, put_len, max_len;
++ unsigned int received = 0;
++ int packet_count = 0;
++
++ DBGPR("-->xgbe_rx_poll: budget=%d\n", budget);
++
++ /* Nothing to do if there isn't a Rx ring for this channel */
++ if (!ring)
++ return 0;
++
++ napi = (pdata->per_channel_irq) ? &channel->napi : &pdata->napi;
++
++ rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
++ packet = &ring->packet_data;
++ while (packet_count < budget) {
++ DBGPR(" cur = %d\n", ring->cur);
++
++ /* First time in loop see if we need to restore state */
++ if (!received && rdata->state_saved) {
++ incomplete = rdata->state.incomplete;
++ context_next = rdata->state.context_next;
++ skb = rdata->state.skb;
++ error = rdata->state.error;
++ len = rdata->state.len;
++ } else {
++ memset(packet, 0, sizeof(*packet));
++ incomplete = 0;
++ context_next = 0;
++ skb = NULL;
++ error = 0;
++ len = 0;
++ }
++
++read_again:
++ rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
++
++ if (xgbe_rx_dirty_desc(ring) > (XGBE_RX_DESC_CNT >> 3))
++ xgbe_rx_refresh(channel);
++
++ if (hw_if->dev_read(channel))
++ break;
++
++ received++;
++ ring->cur++;
++
++ incomplete = XGMAC_GET_BITS(packet->attributes,
++ RX_PACKET_ATTRIBUTES,
++ INCOMPLETE);
++ context_next = XGMAC_GET_BITS(packet->attributes,
++ RX_PACKET_ATTRIBUTES,
++ CONTEXT_NEXT);
++ context = XGMAC_GET_BITS(packet->attributes,
++ RX_PACKET_ATTRIBUTES,
++ CONTEXT);
++
++ /* Earlier error, just drain the remaining data */
++ if ((incomplete || context_next) && error)
++ goto read_again;
++
++ if (error || packet->errors) {
++ if (packet->errors)
++ DBGPR("Error in received packet\n");
++ dev_kfree_skb(skb);
++ goto next_packet;
++ }
++
++ if (!context) {
++ put_len = rdata->rx.len - len;
++ len += put_len;
++
++ if (!skb) {
++ dma_sync_single_for_cpu(pdata->dev,
++ rdata->rx.hdr.dma,
++ rdata->rx.hdr.dma_len,
++ DMA_FROM_DEVICE);
++
++ skb = xgbe_create_skb(pdata, rdata, &put_len);
++ if (!skb) {
++ error = 1;
++ goto skip_data;
++ }
++ }
++
++ if (put_len) {
++ dma_sync_single_for_cpu(pdata->dev,
++ rdata->rx.buf.dma,
++ rdata->rx.buf.dma_len,
++ DMA_FROM_DEVICE);
++
++ skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
++ rdata->rx.buf.pa.pages,
++ rdata->rx.buf.pa.pages_offset,
++ put_len, rdata->rx.buf.dma_len);
++ rdata->rx.buf.pa.pages = NULL;
++ }
++ }
++
++skip_data:
++ if (incomplete || context_next)
++ goto read_again;
++
++ if (!skb)
++ goto next_packet;
++
++ /* Be sure we don't exceed the configured MTU */
++ max_len = netdev->mtu + ETH_HLEN;
++ if (!(netdev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
++ (skb->protocol == htons(ETH_P_8021Q)))
++ max_len += VLAN_HLEN;
++
++ if (skb->len > max_len) {
++ DBGPR("packet length exceeds configured MTU\n");
++ dev_kfree_skb(skb);
++ goto next_packet;
++ }
++
++#ifdef XGMAC_ENABLE_RX_PKT_DUMP
++ xgbe_a0_print_pkt(netdev, skb, false);
++#endif
++
++ skb_checksum_none_assert(skb);
++ if (XGMAC_GET_BITS(packet->attributes,
++ RX_PACKET_ATTRIBUTES, CSUM_DONE))
++ skb->ip_summed = CHECKSUM_UNNECESSARY;
++
++ if (XGMAC_GET_BITS(packet->attributes,
++ RX_PACKET_ATTRIBUTES, VLAN_CTAG))
++ __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
++ packet->vlan_ctag);
++
++ if (XGMAC_GET_BITS(packet->attributes,
++ RX_PACKET_ATTRIBUTES, RX_TSTAMP)) {
++ u64 nsec;
++
++ nsec = timecounter_cyc2time(&pdata->tstamp_tc,
++ packet->rx_tstamp);
++ hwtstamps = skb_hwtstamps(skb);
++ hwtstamps->hwtstamp = ns_to_ktime(nsec);
++ }
++
++ if (XGMAC_GET_BITS(packet->attributes,
++ RX_PACKET_ATTRIBUTES, RSS_HASH))
++ skb_set_hash(skb, packet->rss_hash,
++ packet->rss_hash_type);
++
++ skb->dev = netdev;
++ skb->protocol = eth_type_trans(skb, netdev);
++ skb_record_rx_queue(skb, channel->queue_index);
++ skb_mark_napi_id(skb, napi);
++
++ netdev->last_rx = jiffies;
++ napi_gro_receive(napi, skb);
++
++next_packet:
++ packet_count++;
++ }
++
++ /* Check if we need to save state before leaving */
++ if (received && (incomplete || context_next)) {
++ rdata = XGBE_GET_DESC_DATA(ring, ring->cur);
++ rdata->state_saved = 1;
++ rdata->state.incomplete = incomplete;
++ rdata->state.context_next = context_next;
++ rdata->state.skb = skb;
++ rdata->state.len = len;
++ rdata->state.error = error;
++ }
++
++ DBGPR("<--xgbe_rx_poll: packet_count = %d\n", packet_count);
++
++ return packet_count;
++}
++
++static int xgbe_one_poll(struct napi_struct *napi, int budget)
++{
++ struct xgbe_channel *channel = container_of(napi, struct xgbe_channel,
++ napi);
++ int processed = 0;
++
++ DBGPR("-->xgbe_one_poll: budget=%d\n", budget);
++
++ /* Cleanup Tx ring first */
++ xgbe_tx_poll(channel);
++
++ /* Process Rx ring next */
++ processed = xgbe_rx_poll(channel, budget);
++
++ /* If we processed everything, we are done */
++ if (processed < budget) {
++ /* Turn off polling */
++ napi_complete(napi);
++
++ /* Enable Tx and Rx interrupts */
++ enable_irq(channel->dma_irq);
++ }
++
++ DBGPR("<--xgbe_one_poll: received = %d\n", processed);
++
++ return processed;
++}
++
++static int xgbe_all_poll(struct napi_struct *napi, int budget)
++{
++ struct xgbe_prv_data *pdata = container_of(napi, struct xgbe_prv_data,
++ napi);
++ struct xgbe_channel *channel;
++ int ring_budget;
++ int processed, last_processed;
++ unsigned int i;
++
++ DBGPR("-->xgbe_all_poll: budget=%d\n", budget);
++
++ processed = 0;
++ ring_budget = budget / pdata->rx_ring_count;
++ do {
++ last_processed = processed;
++
++ channel = pdata->channel;
++ for (i = 0; i < pdata->channel_count; i++, channel++) {
++ /* Cleanup Tx ring first */
++ xgbe_tx_poll(channel);
++
++ /* Process Rx ring next */
++ if (ring_budget > (budget - processed))
++ ring_budget = budget - processed;
++ processed += xgbe_rx_poll(channel, ring_budget);
++ }
++ } while ((processed < budget) && (processed != last_processed));
++
++ /* If we processed everything, we are done */
++ if (processed < budget) {
++ /* Turn off polling */
++ napi_complete(napi);
++
++ /* Enable Tx and Rx interrupts */
++ xgbe_enable_rx_tx_ints(pdata);
++ }
++
++ DBGPR("<--xgbe_all_poll: received = %d\n", processed);
++
++ return processed;
++}
++
++void xgbe_a0_dump_tx_desc(struct xgbe_ring *ring, unsigned int idx,
++ unsigned int count, unsigned int flag)
++{
++ struct xgbe_ring_data *rdata;
++ struct xgbe_ring_desc *rdesc;
++
++ while (count--) {
++ rdata = XGBE_GET_DESC_DATA(ring, idx);
++ rdesc = rdata->rdesc;
++ pr_alert("TX_NORMAL_DESC[%d %s] = %08x:%08x:%08x:%08x\n", idx,
++ (flag == 1) ? "QUEUED FOR TX" : "TX BY DEVICE",
++ le32_to_cpu(rdesc->desc0), le32_to_cpu(rdesc->desc1),
++ le32_to_cpu(rdesc->desc2), le32_to_cpu(rdesc->desc3));
++ idx++;
++ }
++}
++
++void xgbe_a0_dump_rx_desc(struct xgbe_ring *ring, struct xgbe_ring_desc *desc,
++ unsigned int idx)
++{
++ pr_alert("RX_NORMAL_DESC[%d RX BY DEVICE] = %08x:%08x:%08x:%08x\n", idx,
++ le32_to_cpu(desc->desc0), le32_to_cpu(desc->desc1),
++ le32_to_cpu(desc->desc2), le32_to_cpu(desc->desc3));
++}
++
++void xgbe_a0_print_pkt(struct net_device *netdev, struct sk_buff *skb, bool tx_rx)
++{
++ struct ethhdr *eth = (struct ethhdr *)skb->data;
++ unsigned char *buf = skb->data;
++ unsigned char buffer[128];
++ unsigned int i, j;
++
++ netdev_alert(netdev, "\n************** SKB dump ****************\n");
++
++ netdev_alert(netdev, "%s packet of %d bytes\n",
++ (tx_rx ? "TX" : "RX"), skb->len);
++
++ netdev_alert(netdev, "Dst MAC addr: %pM\n", eth->h_dest);
++ netdev_alert(netdev, "Src MAC addr: %pM\n", eth->h_source);
++ netdev_alert(netdev, "Protocol: 0x%04hx\n", ntohs(eth->h_proto));
++
++ for (i = 0, j = 0; i < skb->len;) {
++ j += snprintf(buffer + j, sizeof(buffer) - j, "%02hhx",
++ buf[i++]);
++
++ if ((i % 32) == 0) {
++ netdev_alert(netdev, " 0x%04x: %s\n", i - 32, buffer);
++ j = 0;
++ } else if ((i % 16) == 0) {
++ buffer[j++] = ' ';
++ buffer[j++] = ' ';
++ } else if ((i % 4) == 0) {
++ buffer[j++] = ' ';
++ }
++ }
++ if (i % 32)
++ netdev_alert(netdev, " 0x%04x: %s\n", i - (i % 32), buffer);
++
++ netdev_alert(netdev, "\n************** SKB dump ****************\n");
++}
+diff --git a/drivers/net/ethernet/amd/xgbe-a0/xgbe-ethtool.c b/drivers/net/ethernet/amd/xgbe-a0/xgbe-ethtool.c
+new file mode 100644
+index 000000000000..165ff1ceedcc
+--- /dev/null
++++ b/drivers/net/ethernet/amd/xgbe-a0/xgbe-ethtool.c
+@@ -0,0 +1,616 @@
++/*
++ * AMD 10Gb Ethernet driver
++ *
++ * This file is available to you under your choice of the following two
++ * licenses:
++ *
++ * License 1: GPLv2
++ *
++ * Copyright (c) 2014 Advanced Micro Devices, Inc.
++ *
++ * This file is free software; you may copy, redistribute and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 2 of the License, or (at
++ * your option) any later version.
++ *
++ * This file is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ *
++ * This file incorporates work covered by the following copyright and
++ * permission notice:
++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation
++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
++ * Inc. unless otherwise expressly agreed to in writing between Synopsys
++ * and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product
++ * under any End User Software License Agreement or Agreement for Licensed
++ * Product with Synopsys or any supplement thereto. Permission is hereby
++ * granted, free of charge, to any person obtaining a copy of this software
++ * annotated with this license and the Software, to deal in the Software
++ * without restriction, including without limitation the rights to use,
++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
++ * of the Software, and to permit persons to whom the Software is furnished
++ * to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
++ * THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ *
++ * License 2: Modified BSD
++ *
++ * Copyright (c) 2014 Advanced Micro Devices, Inc.
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * * Neither the name of Advanced Micro Devices, Inc. nor the
++ * names of its contributors may be used to endorse or promote products
++ * derived from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * This file incorporates work covered by the following copyright and
++ * permission notice:
++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation
++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
++ * Inc. unless otherwise expressly agreed to in writing between Synopsys
++ * and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product
++ * under any End User Software License Agreement or Agreement for Licensed
++ * Product with Synopsys or any supplement thereto. Permission is hereby
++ * granted, free of charge, to any person obtaining a copy of this software
++ * annotated with this license and the Software, to deal in the Software
++ * without restriction, including without limitation the rights to use,
++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
++ * of the Software, and to permit persons to whom the Software is furnished
++ * to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
++ * THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include <linux/spinlock.h>
++#include <linux/phy.h>
++#include <linux/net_tstamp.h>
++
++#include "xgbe.h"
++#include "xgbe-common.h"
++
++struct xgbe_stats {
++ char stat_string[ETH_GSTRING_LEN];
++ int stat_size;
++ int stat_offset;
++};
++
++#define XGMAC_MMC_STAT(_string, _var) \
++ { _string, \
++ FIELD_SIZEOF(struct xgbe_mmc_stats, _var), \
++ offsetof(struct xgbe_prv_data, mmc_stats._var), \
++ }
++
++static const struct xgbe_stats xgbe_gstring_stats[] = {
++ XGMAC_MMC_STAT("tx_bytes", txoctetcount_gb),
++ XGMAC_MMC_STAT("tx_packets", txframecount_gb),
++ XGMAC_MMC_STAT("tx_unicast_packets", txunicastframes_gb),
++ XGMAC_MMC_STAT("tx_broadcast_packets", txbroadcastframes_gb),
++ XGMAC_MMC_STAT("tx_multicast_packets", txmulticastframes_gb),
++ XGMAC_MMC_STAT("tx_vlan_packets", txvlanframes_g),
++ XGMAC_MMC_STAT("tx_64_byte_packets", tx64octets_gb),
++ XGMAC_MMC_STAT("tx_65_to_127_byte_packets", tx65to127octets_gb),
++ XGMAC_MMC_STAT("tx_128_to_255_byte_packets", tx128to255octets_gb),
++ XGMAC_MMC_STAT("tx_256_to_511_byte_packets", tx256to511octets_gb),
++ XGMAC_MMC_STAT("tx_512_to_1023_byte_packets", tx512to1023octets_gb),
++ XGMAC_MMC_STAT("tx_1024_to_max_byte_packets", tx1024tomaxoctets_gb),
++ XGMAC_MMC_STAT("tx_underflow_errors", txunderflowerror),
++ XGMAC_MMC_STAT("tx_pause_frames", txpauseframes),
++
++ XGMAC_MMC_STAT("rx_bytes", rxoctetcount_gb),
++ XGMAC_MMC_STAT("rx_packets", rxframecount_gb),
++ XGMAC_MMC_STAT("rx_unicast_packets", rxunicastframes_g),
++ XGMAC_MMC_STAT("rx_broadcast_packets", rxbroadcastframes_g),
++ XGMAC_MMC_STAT("rx_multicast_packets", rxmulticastframes_g),
++ XGMAC_MMC_STAT("rx_vlan_packets", rxvlanframes_gb),
++ XGMAC_MMC_STAT("rx_64_byte_packets", rx64octets_gb),
++ XGMAC_MMC_STAT("rx_65_to_127_byte_packets", rx65to127octets_gb),
++ XGMAC_MMC_STAT("rx_128_to_255_byte_packets", rx128to255octets_gb),
++ XGMAC_MMC_STAT("rx_256_to_511_byte_packets", rx256to511octets_gb),
++ XGMAC_MMC_STAT("rx_512_to_1023_byte_packets", rx512to1023octets_gb),
++ XGMAC_MMC_STAT("rx_1024_to_max_byte_packets", rx1024tomaxoctets_gb),
++ XGMAC_MMC_STAT("rx_undersize_packets", rxundersize_g),
++ XGMAC_MMC_STAT("rx_oversize_packets", rxoversize_g),
++ XGMAC_MMC_STAT("rx_crc_errors", rxcrcerror),
++ XGMAC_MMC_STAT("rx_crc_errors_small_packets", rxrunterror),
++ XGMAC_MMC_STAT("rx_crc_errors_giant_packets", rxjabbererror),
++ XGMAC_MMC_STAT("rx_length_errors", rxlengtherror),
++ XGMAC_MMC_STAT("rx_out_of_range_errors", rxoutofrangetype),
++ XGMAC_MMC_STAT("rx_fifo_overflow_errors", rxfifooverflow),
++ XGMAC_MMC_STAT("rx_watchdog_errors", rxwatchdogerror),
++ XGMAC_MMC_STAT("rx_pause_frames", rxpauseframes),
++};
++
++#define XGBE_STATS_COUNT ARRAY_SIZE(xgbe_gstring_stats)
++
++static void xgbe_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
++{
++ int i;
++
++ DBGPR("-->%s\n", __func__);
++
++ switch (stringset) {
++ case ETH_SS_STATS:
++ for (i = 0; i < XGBE_STATS_COUNT; i++) {
++ memcpy(data, xgbe_gstring_stats[i].stat_string,
++ ETH_GSTRING_LEN);
++ data += ETH_GSTRING_LEN;
++ }
++ break;
++ }
++
++ DBGPR("<--%s\n", __func__);
++}
++
++static void xgbe_get_ethtool_stats(struct net_device *netdev,
++ struct ethtool_stats *stats, u64 *data)
++{
++ struct xgbe_prv_data *pdata = netdev_priv(netdev);
++ u8 *stat;
++ int i;
++
++ DBGPR("-->%s\n", __func__);
++
++ pdata->hw_if.read_mmc_stats(pdata);
++ for (i = 0; i < XGBE_STATS_COUNT; i++) {
++ stat = (u8 *)pdata + xgbe_gstring_stats[i].stat_offset;
++ *data++ = *(u64 *)stat;
++ }
++
++ DBGPR("<--%s\n", __func__);
++}
++
++static int xgbe_get_sset_count(struct net_device *netdev, int stringset)
++{
++ int ret;
++
++ DBGPR("-->%s\n", __func__);
++
++ switch (stringset) {
++ case ETH_SS_STATS:
++ ret = XGBE_STATS_COUNT;
++ break;
++
++ default:
++ ret = -EOPNOTSUPP;
++ }
++
++ DBGPR("<--%s\n", __func__);
++
++ return ret;
++}
++
++static void xgbe_get_pauseparam(struct net_device *netdev,
++ struct ethtool_pauseparam *pause)
++{
++ struct xgbe_prv_data *pdata = netdev_priv(netdev);
++
++ DBGPR("-->xgbe_get_pauseparam\n");
++
++ pause->autoneg = pdata->pause_autoneg;
++ pause->tx_pause = pdata->tx_pause;
++ pause->rx_pause = pdata->rx_pause;
++
++ DBGPR("<--xgbe_get_pauseparam\n");
++}
++
++static int xgbe_set_pauseparam(struct net_device *netdev,
++ struct ethtool_pauseparam *pause)
++{
++ struct xgbe_prv_data *pdata = netdev_priv(netdev);
++ struct phy_device *phydev = pdata->phydev;
++ int ret = 0;
++
++ DBGPR("-->xgbe_set_pauseparam\n");
++
++ DBGPR(" autoneg = %d, tx_pause = %d, rx_pause = %d\n",
++ pause->autoneg, pause->tx_pause, pause->rx_pause);
++
++ pdata->pause_autoneg = pause->autoneg;
++ if (pause->autoneg) {
++ phydev->advertising |= ADVERTISED_Pause;
++ phydev->advertising |= ADVERTISED_Asym_Pause;
++
++ } else {
++ phydev->advertising &= ~ADVERTISED_Pause;
++ phydev->advertising &= ~ADVERTISED_Asym_Pause;
++
++ pdata->tx_pause = pause->tx_pause;
++ pdata->rx_pause = pause->rx_pause;
++ }
++
++ if (netif_running(netdev))
++ ret = phy_start_aneg(phydev);
++
++ DBGPR("<--xgbe_set_pauseparam\n");
++
++ return ret;
++}
++
++static int xgbe_get_settings(struct net_device *netdev,
++ struct ethtool_cmd *cmd)
++{
++ struct xgbe_prv_data *pdata = netdev_priv(netdev);
++ int ret;
++
++ DBGPR("-->xgbe_get_settings\n");
++
++ if (!pdata->phydev)
++ return -ENODEV;
++
++ ret = phy_ethtool_gset(pdata->phydev, cmd);
++ cmd->transceiver = XCVR_EXTERNAL;
++
++ DBGPR("<--xgbe_get_settings\n");
++
++ return ret;
++}
++
++static int xgbe_set_settings(struct net_device *netdev,
++ struct ethtool_cmd *cmd)
++{
++ struct xgbe_prv_data *pdata = netdev_priv(netdev);
++ struct phy_device *phydev = pdata->phydev;
++ u32 speed;
++ int ret;
++
++ DBGPR("-->xgbe_set_settings\n");
++
++ if (!pdata->phydev)
++ return -ENODEV;
++
++ speed = ethtool_cmd_speed(cmd);
++
++ if (cmd->phy_address != phydev->addr)
++ return -EINVAL;
++
++ if ((cmd->autoneg != AUTONEG_ENABLE) &&
++ (cmd->autoneg != AUTONEG_DISABLE))
++ return -EINVAL;
++
++ if (cmd->autoneg == AUTONEG_DISABLE) {
++ switch (speed) {
++ case SPEED_10000:
++ case SPEED_2500:
++ case SPEED_1000:
++ break;
++ default:
++ return -EINVAL;
++ }
++
++ if (cmd->duplex != DUPLEX_FULL)
++ return -EINVAL;
++ }
++
++ cmd->advertising &= phydev->supported;
++ if ((cmd->autoneg == AUTONEG_ENABLE) && !cmd->advertising)
++ return -EINVAL;
++
++ ret = 0;
++ phydev->autoneg = cmd->autoneg;
++ phydev->speed = speed;
++ phydev->duplex = cmd->duplex;
++ phydev->advertising = cmd->advertising;
++
++ if (cmd->autoneg == AUTONEG_ENABLE)
++ phydev->advertising |= ADVERTISED_Autoneg;
++ else
++ phydev->advertising &= ~ADVERTISED_Autoneg;
++
++ if (netif_running(netdev))
++ ret = phy_start_aneg(phydev);
++
++ DBGPR("<--xgbe_set_settings\n");
++
++ return ret;
++}
++
++static void xgbe_get_drvinfo(struct net_device *netdev,
++ struct ethtool_drvinfo *drvinfo)
++{
++ struct xgbe_prv_data *pdata = netdev_priv(netdev);
++ struct xgbe_hw_features *hw_feat = &pdata->hw_feat;
++
++ strlcpy(drvinfo->driver, XGBE_DRV_NAME, sizeof(drvinfo->driver));
++ strlcpy(drvinfo->version, XGBE_DRV_VERSION, sizeof(drvinfo->version));
++ strlcpy(drvinfo->bus_info, dev_name(pdata->dev),
++ sizeof(drvinfo->bus_info));
++ snprintf(drvinfo->fw_version, sizeof(drvinfo->fw_version), "%d.%d.%d",
++ XGMAC_GET_BITS(hw_feat->version, MAC_VR, USERVER),
++ XGMAC_GET_BITS(hw_feat->version, MAC_VR, DEVID),
++ XGMAC_GET_BITS(hw_feat->version, MAC_VR, SNPSVER));
++ drvinfo->n_stats = XGBE_STATS_COUNT;
++}
++
++static int xgbe_get_coalesce(struct net_device *netdev,
++ struct ethtool_coalesce *ec)
++{
++ struct xgbe_prv_data *pdata = netdev_priv(netdev);
++ struct xgbe_hw_if *hw_if = &pdata->hw_if;
++ unsigned int riwt;
++
++ DBGPR("-->xgbe_get_coalesce\n");
++
++ memset(ec, 0, sizeof(struct ethtool_coalesce));
++
++ riwt = pdata->rx_riwt;
++ ec->rx_coalesce_usecs = hw_if->riwt_to_usec(pdata, riwt);
++ ec->rx_max_coalesced_frames = pdata->rx_frames;
++
++ ec->tx_coalesce_usecs = pdata->tx_usecs;
++ ec->tx_max_coalesced_frames = pdata->tx_frames;
++
++ DBGPR("<--xgbe_get_coalesce\n");
++
++ return 0;
++}
++
++static int xgbe_set_coalesce(struct net_device *netdev,
++ struct ethtool_coalesce *ec)
++{
++ struct xgbe_prv_data *pdata = netdev_priv(netdev);
++ struct xgbe_hw_if *hw_if = &pdata->hw_if;
++ unsigned int rx_frames, rx_riwt, rx_usecs;
++ unsigned int tx_frames, tx_usecs;
++
++ DBGPR("-->xgbe_set_coalesce\n");
++
++ /* Check for not supported parameters */
++ if ((ec->rx_coalesce_usecs_irq) ||
++ (ec->rx_max_coalesced_frames_irq) ||
++ (ec->tx_coalesce_usecs_irq) ||
++ (ec->tx_max_coalesced_frames_irq) ||
++ (ec->stats_block_coalesce_usecs) ||
++ (ec->use_adaptive_rx_coalesce) ||
++ (ec->use_adaptive_tx_coalesce) ||
++ (ec->pkt_rate_low) ||
++ (ec->rx_coalesce_usecs_low) ||
++ (ec->rx_max_coalesced_frames_low) ||
++ (ec->tx_coalesce_usecs_low) ||
++ (ec->tx_max_coalesced_frames_low) ||
++ (ec->pkt_rate_high) ||
++ (ec->rx_coalesce_usecs_high) ||
++ (ec->rx_max_coalesced_frames_high) ||
++ (ec->tx_coalesce_usecs_high) ||
++ (ec->tx_max_coalesced_frames_high) ||
++ (ec->rate_sample_interval))
++ return -EOPNOTSUPP;
++
++ /* Can only change rx-frames when interface is down (see
++ * rx_descriptor_init in xgbe-dev.c)
++ */
++ rx_frames = pdata->rx_frames;
++ if (rx_frames != ec->rx_max_coalesced_frames && netif_running(netdev)) {
++ netdev_alert(netdev,
++ "interface must be down to change rx-frames\n");
++ return -EINVAL;
++ }
++
++ rx_riwt = hw_if->usec_to_riwt(pdata, ec->rx_coalesce_usecs);
++ rx_frames = ec->rx_max_coalesced_frames;
++
++ /* Use smallest possible value if conversion resulted in zero */
++ if (ec->rx_coalesce_usecs && !rx_riwt)
++ rx_riwt = 1;
++
++ /* Check the bounds of values for Rx */
++ if (rx_riwt > XGMAC_MAX_DMA_RIWT) {
++ rx_usecs = hw_if->riwt_to_usec(pdata, XGMAC_MAX_DMA_RIWT);
++ netdev_alert(netdev, "rx-usec is limited to %d usecs\n",
++ rx_usecs);
++ return -EINVAL;
++ }
++ if (rx_frames > pdata->rx_desc_count) {
++ netdev_alert(netdev, "rx-frames is limited to %d frames\n",
++ pdata->rx_desc_count);
++ return -EINVAL;
++ }
++
++ tx_usecs = ec->tx_coalesce_usecs;
++ tx_frames = ec->tx_max_coalesced_frames;
++
++ /* Check the bounds of values for Tx */
++ if (tx_frames > pdata->tx_desc_count) {
++ netdev_alert(netdev, "tx-frames is limited to %d frames\n",
++ pdata->tx_desc_count);
++ return -EINVAL;
++ }
++
++ pdata->rx_riwt = rx_riwt;
++ pdata->rx_frames = rx_frames;
++ hw_if->config_rx_coalesce(pdata);
++
++ pdata->tx_usecs = tx_usecs;
++ pdata->tx_frames = tx_frames;
++ hw_if->config_tx_coalesce(pdata);
++
++ DBGPR("<--xgbe_set_coalesce\n");
++
++ return 0;
++}
++
++static int xgbe_get_rxnfc(struct net_device *netdev,
++ struct ethtool_rxnfc *rxnfc, u32 *rule_locs)
++{
++ struct xgbe_prv_data *pdata = netdev_priv(netdev);
++
++ switch (rxnfc->cmd) {
++ case ETHTOOL_GRXRINGS:
++ rxnfc->data = pdata->rx_ring_count;
++ break;
++ default:
++ return -EOPNOTSUPP;
++ }
++
++ return 0;
++}
++
++static u32 xgbe_get_rxfh_key_size(struct net_device *netdev)
++{
++ struct xgbe_prv_data *pdata = netdev_priv(netdev);
++
++ return sizeof(pdata->rss_key);
++}
++
++static u32 xgbe_get_rxfh_indir_size(struct net_device *netdev)
++{
++ struct xgbe_prv_data *pdata = netdev_priv(netdev);
++
++ return ARRAY_SIZE(pdata->rss_table);
++}
++
++static int xgbe_get_rxfh(struct net_device *netdev, u32 *indir, u8 *key,
++ u8 *hfunc)
++{
++ struct xgbe_prv_data *pdata = netdev_priv(netdev);
++ unsigned int i;
++
++ if (indir) {
++ for (i = 0; i < ARRAY_SIZE(pdata->rss_table); i++)
++ indir[i] = XGMAC_GET_BITS(pdata->rss_table[i],
++ MAC_RSSDR, DMCH);
++ }
++
++ if (key)
++ memcpy(key, pdata->rss_key, sizeof(pdata->rss_key));
++
++ if (hfunc)
++ *hfunc = ETH_RSS_HASH_TOP;
++
++ return 0;
++}
++
++static int xgbe_set_rxfh(struct net_device *netdev, const u32 *indir,
++ const u8 *key, const u8 hfunc)
++{
++ struct xgbe_prv_data *pdata = netdev_priv(netdev);
++ struct xgbe_hw_if *hw_if = &pdata->hw_if;
++ unsigned int ret;
++
++ if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)
++ return -EOPNOTSUPP;
++
++ if (indir) {
++ ret = hw_if->set_rss_lookup_table(pdata, indir);
++ if (ret)
++ return ret;
++ }
++
++ if (key) {
++ ret = hw_if->set_rss_hash_key(pdata, key);
++ if (ret)
++ return ret;
++ }
++
++ return 0;
++}
++
++static int xgbe_get_ts_info(struct net_device *netdev,
++ struct ethtool_ts_info *ts_info)
++{
++ struct xgbe_prv_data *pdata = netdev_priv(netdev);
++
++ ts_info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
++ SOF_TIMESTAMPING_RX_SOFTWARE |
++ SOF_TIMESTAMPING_SOFTWARE |
++ SOF_TIMESTAMPING_TX_HARDWARE |
++ SOF_TIMESTAMPING_RX_HARDWARE |
++ SOF_TIMESTAMPING_RAW_HARDWARE;
++
++ if (pdata->ptp_clock)
++ ts_info->phc_index = ptp_clock_index(pdata->ptp_clock);
++ else
++ ts_info->phc_index = -1;
++
++ ts_info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
++ ts_info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
++ (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
++ (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
++ (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
++ (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
++ (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
++ (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
++ (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) |
++ (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) |
++ (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ) |
++ (1 << HWTSTAMP_FILTER_ALL);
++
++ return 0;
++}
++
++static const struct ethtool_ops xgbe_ethtool_ops = {
++ .get_settings = xgbe_get_settings,
++ .set_settings = xgbe_set_settings,
++ .get_drvinfo = xgbe_get_drvinfo,
++ .get_link = ethtool_op_get_link,
++ .get_coalesce = xgbe_get_coalesce,
++ .set_coalesce = xgbe_set_coalesce,
++ .get_pauseparam = xgbe_get_pauseparam,
++ .set_pauseparam = xgbe_set_pauseparam,
++ .get_strings = xgbe_get_strings,
++ .get_ethtool_stats = xgbe_get_ethtool_stats,
++ .get_sset_count = xgbe_get_sset_count,
++ .get_rxnfc = xgbe_get_rxnfc,
++ .get_rxfh_key_size = xgbe_get_rxfh_key_size,
++ .get_rxfh_indir_size = xgbe_get_rxfh_indir_size,
++ .get_rxfh = xgbe_get_rxfh,
++ .set_rxfh = xgbe_set_rxfh,
++ .get_ts_info = xgbe_get_ts_info,
++};
++
++struct ethtool_ops *xgbe_a0_get_ethtool_ops(void)
++{
++ return (struct ethtool_ops *)&xgbe_ethtool_ops;
++}
+diff --git a/drivers/net/ethernet/amd/xgbe-a0/xgbe-main.c b/drivers/net/ethernet/amd/xgbe-a0/xgbe-main.c
+new file mode 100644
+index 000000000000..a85fb4965835
+--- /dev/null
++++ b/drivers/net/ethernet/amd/xgbe-a0/xgbe-main.c
+@@ -0,0 +1,643 @@
++/*
++ * AMD 10Gb Ethernet driver
++ *
++ * This file is available to you under your choice of the following two
++ * licenses:
++ *
++ * License 1: GPLv2
++ *
++ * Copyright (c) 2014 Advanced Micro Devices, Inc.
++ *
++ * This file is free software; you may copy, redistribute and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 2 of the License, or (at
++ * your option) any later version.
++ *
++ * This file is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ *
++ * This file incorporates work covered by the following copyright and
++ * permission notice:
++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation
++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
++ * Inc. unless otherwise expressly agreed to in writing between Synopsys
++ * and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product
++ * under any End User Software License Agreement or Agreement for Licensed
++ * Product with Synopsys or any supplement thereto. Permission is hereby
++ * granted, free of charge, to any person obtaining a copy of this software
++ * annotated with this license and the Software, to deal in the Software
++ * without restriction, including without limitation the rights to use,
++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
++ * of the Software, and to permit persons to whom the Software is furnished
++ * to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
++ * THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ *
++ * License 2: Modified BSD
++ *
++ * Copyright (c) 2014 Advanced Micro Devices, Inc.
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * * Neither the name of Advanced Micro Devices, Inc. nor the
++ * names of its contributors may be used to endorse or promote products
++ * derived from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * This file incorporates work covered by the following copyright and
++ * permission notice:
++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation
++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
++ * Inc. unless otherwise expressly agreed to in writing between Synopsys
++ * and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product
++ * under any End User Software License Agreement or Agreement for Licensed
++ * Product with Synopsys or any supplement thereto. Permission is hereby
++ * granted, free of charge, to any person obtaining a copy of this software
++ * annotated with this license and the Software, to deal in the Software
++ * without restriction, including without limitation the rights to use,
++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
++ * of the Software, and to permit persons to whom the Software is furnished
++ * to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
++ * THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include <linux/module.h>
++#include <linux/device.h>
++#include <linux/platform_device.h>
++#include <linux/spinlock.h>
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/io.h>
++#include <linux/of.h>
++#include <linux/of_net.h>
++#include <linux/of_address.h>
++#include <linux/clk.h>
++#include <linux/property.h>
++#include <linux/acpi.h>
++
++#include "xgbe.h"
++#include "xgbe-common.h"
++
++MODULE_AUTHOR("Tom Lendacky <thomas.lendacky at amd.com>");
++MODULE_LICENSE("Dual BSD/GPL");
++MODULE_VERSION(XGBE_DRV_VERSION);
++MODULE_DESCRIPTION(XGBE_DRV_DESC);
++
++unsigned int speed = 0;
++module_param(speed, uint, 0444);
++MODULE_PARM_DESC(speed, " Select operating speed (1=1GbE, 2=2.5GbE, 10=10GbE, any other value implies auto-negotiation");
++
++static void xgbe_default_config(struct xgbe_prv_data *pdata)
++{
++ DBGPR("-->xgbe_default_config\n");
++
++ pdata->pblx8 = DMA_PBL_X8_ENABLE;
++ pdata->tx_sf_mode = MTL_TSF_ENABLE;
++ pdata->tx_threshold = MTL_TX_THRESHOLD_64;
++ pdata->tx_pbl = DMA_PBL_16;
++ pdata->tx_osp_mode = DMA_OSP_ENABLE;
++ pdata->rx_sf_mode = MTL_RSF_DISABLE;
++ pdata->rx_threshold = MTL_RX_THRESHOLD_64;
++ pdata->rx_pbl = DMA_PBL_16;
++ pdata->pause_autoneg = 1;
++ pdata->tx_pause = 1;
++ pdata->rx_pause = 1;
++ pdata->phy_speed = SPEED_UNKNOWN;
++ pdata->power_down = 0;
++
++ if (speed == 10) {
++ pdata->default_autoneg = AUTONEG_DISABLE;
++ pdata->default_speed = SPEED_10000;
++ } else if (speed == 2) {
++ pdata->default_autoneg = AUTONEG_DISABLE;
++ pdata->default_speed = SPEED_2500;
++ } else if (speed == 1) {
++ pdata->default_autoneg = AUTONEG_DISABLE;
++ pdata->default_speed = SPEED_1000;
++ } else {
++ pdata->default_autoneg = AUTONEG_ENABLE;
++ pdata->default_speed = SPEED_10000;
++ }
++
++ DBGPR("<--xgbe_default_config\n");
++}
++
++static void xgbe_init_all_fptrs(struct xgbe_prv_data *pdata)
++{
++ xgbe_a0_init_function_ptrs_dev(&pdata->hw_if);
++ xgbe_a0_init_function_ptrs_desc(&pdata->desc_if);
++}
++
++#ifdef CONFIG_ACPI
++static int xgbe_acpi_support(struct xgbe_prv_data *pdata)
++{
++ struct acpi_device *adev = pdata->adev;
++ struct device *dev = pdata->dev;
++ u32 property;
++ acpi_handle handle;
++ acpi_status status;
++ unsigned long long data;
++ int cca;
++ int ret;
++
++ /* Obtain the system clock setting */
++ ret = device_property_read_u32(dev, XGBE_ACPI_DMA_FREQ, &property);
++ if (ret) {
++ dev_err(dev, "unable to obtain %s property\n",
++ XGBE_ACPI_DMA_FREQ);
++ return ret;
++ }
++ pdata->sysclk_rate = property;
++
++ /* Obtain the PTP clock setting */
++ ret = device_property_read_u32(dev, XGBE_ACPI_PTP_FREQ, &property);
++ if (ret) {
++ dev_err(dev, "unable to obtain %s property\n",
++ XGBE_ACPI_PTP_FREQ);
++ return ret;
++ }
++ pdata->ptpclk_rate = property;
++
++ /* Retrieve the device cache coherency value */
++ handle = adev->handle;
++ do {
++ status = acpi_evaluate_integer(handle, "_CCA", NULL, &data);
++ if (!ACPI_FAILURE(status)) {
++ cca = data;
++ break;
++ }
++
++ status = acpi_get_parent(handle, &handle);
++ } while (!ACPI_FAILURE(status));
++
++ if (ACPI_FAILURE(status)) {
++ dev_err(dev, "error obtaining acpi coherency value\n");
++ return -EINVAL;
++ }
++ pdata->coherent = !!cca;
++
++ return 0;
++}
++#else /* CONFIG_ACPI */
++static int xgbe_acpi_support(struct xgbe_prv_data *pdata)
++{
++ return -EINVAL;
++}
++#endif /* CONFIG_ACPI */
++
++#ifdef CONFIG_OF
++static int xgbe_of_support(struct xgbe_prv_data *pdata)
++{
++ struct device *dev = pdata->dev;
++
++ /* Obtain the system clock setting */
++ pdata->sysclk = devm_clk_get(dev, XGBE_DMA_CLOCK);
++ if (IS_ERR(pdata->sysclk)) {
++ dev_err(dev, "dma devm_clk_get failed\n");
++ return PTR_ERR(pdata->sysclk);
++ }
++ pdata->sysclk_rate = clk_get_rate(pdata->sysclk);
++
++ /* Obtain the PTP clock setting */
++ pdata->ptpclk = devm_clk_get(dev, XGBE_PTP_CLOCK);
++ if (IS_ERR(pdata->ptpclk)) {
++ dev_err(dev, "ptp devm_clk_get failed\n");
++ return PTR_ERR(pdata->ptpclk);
++ }
++ pdata->ptpclk_rate = clk_get_rate(pdata->ptpclk);
++
++ /* Retrieve the device cache coherency value */
++ pdata->coherent = of_dma_is_coherent(dev->of_node);
++
++ return 0;
++}
++#else /* CONFIG_OF */
++static int xgbe_of_support(struct xgbe_prv_data *pdata)
++{
++ return -EINVAL;
++}
++#endif /*CONFIG_OF */
++
++static int xgbe_probe(struct platform_device *pdev)
++{
++ struct xgbe_prv_data *pdata;
++ struct xgbe_hw_if *hw_if;
++ struct xgbe_desc_if *desc_if;
++ struct net_device *netdev;
++ struct device *dev = &pdev->dev;
++ struct resource *res;
++ const char *phy_mode;
++ unsigned int i;
++ int ret;
++
++ DBGPR("--> xgbe_probe\n");
++
++ netdev = alloc_etherdev_mq(sizeof(struct xgbe_prv_data),
++ XGBE_MAX_DMA_CHANNELS);
++ if (!netdev) {
++ dev_err(dev, "alloc_etherdev failed\n");
++ ret = -ENOMEM;
++ goto err_alloc;
++ }
++ SET_NETDEV_DEV(netdev, dev);
++ pdata = netdev_priv(netdev);
++ pdata->netdev = netdev;
++ pdata->pdev = pdev;
++ pdata->adev = ACPI_COMPANION(dev);
++ pdata->dev = dev;
++ platform_set_drvdata(pdev, netdev);
++
++ spin_lock_init(&pdata->lock);
++ mutex_init(&pdata->xpcs_mutex);
++ mutex_init(&pdata->rss_mutex);
++ spin_lock_init(&pdata->tstamp_lock);
++
++ /* Check if we should use ACPI or DT */
++ pdata->use_acpi = (!pdata->adev || acpi_disabled) ? 0 : 1;
++
++ /* Set and validate the number of descriptors for a ring */
++ BUILD_BUG_ON_NOT_POWER_OF_2(XGBE_TX_DESC_CNT);
++ pdata->tx_desc_count = XGBE_TX_DESC_CNT;
++ if (pdata->tx_desc_count & (pdata->tx_desc_count - 1)) {
++ dev_err(dev, "tx descriptor count (%d) is not valid\n",
++ pdata->tx_desc_count);
++ ret = -EINVAL;
++ goto err_io;
++ }
++ BUILD_BUG_ON_NOT_POWER_OF_2(XGBE_RX_DESC_CNT);
++ pdata->rx_desc_count = XGBE_RX_DESC_CNT;
++ if (pdata->rx_desc_count & (pdata->rx_desc_count - 1)) {
++ dev_err(dev, "rx descriptor count (%d) is not valid\n",
++ pdata->rx_desc_count);
++ ret = -EINVAL;
++ goto err_io;
++ }
++
++ /* Obtain the mmio areas for the device */
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
++ pdata->xgmac_regs = devm_ioremap_resource(dev, res);
++ if (IS_ERR(pdata->xgmac_regs)) {
++ dev_err(dev, "xgmac ioremap failed\n");
++ ret = PTR_ERR(pdata->xgmac_regs);
++ goto err_io;
++ }
++ DBGPR(" xgmac_regs = %p\n", pdata->xgmac_regs);
++
++ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
++ pdata->xpcs_regs = devm_ioremap_resource(dev, res);
++ if (IS_ERR(pdata->xpcs_regs)) {
++ dev_err(dev, "xpcs ioremap failed\n");
++ ret = PTR_ERR(pdata->xpcs_regs);
++ goto err_io;
++ }
++ DBGPR(" xpcs_regs = %p\n", pdata->xpcs_regs);
++
++ /* Retrieve the MAC address */
++ ret = device_property_read_u8_array(dev, XGBE_MAC_ADDR_PROPERTY,
++ pdata->mac_addr,
++ sizeof(pdata->mac_addr));
++ if (ret || !is_valid_ether_addr(pdata->mac_addr)) {
++ dev_err(dev, "invalid %s property\n", XGBE_MAC_ADDR_PROPERTY);
++ if (!ret)
++ ret = -EINVAL;
++ goto err_io;
++ }
++
++ /* Retrieve the PHY mode - it must be "xgmii" */
++ ret = device_property_read_string(dev, XGBE_PHY_MODE_PROPERTY,
++ &phy_mode);
++ if (ret || strcmp(phy_mode, phy_modes(PHY_INTERFACE_MODE_XGMII))) {
++ dev_err(dev, "invalid %s property\n", XGBE_PHY_MODE_PROPERTY);
++ if (!ret)
++ ret = -EINVAL;
++ goto err_io;
++ }
++ pdata->phy_mode = PHY_INTERFACE_MODE_XGMII;
++
++ /* Check for per channel interrupt support */
++ if (device_property_present(dev, XGBE_DMA_IRQS_PROPERTY))
++ pdata->per_channel_irq = 1;
++
++ /* Obtain device settings unique to ACPI/OF */
++ if (pdata->use_acpi)
++ ret = xgbe_acpi_support(pdata);
++ else
++ ret = xgbe_of_support(pdata);
++ if (ret)
++ goto err_io;
++
++ /* Set the DMA coherency values */
++ if (pdata->coherent) {
++ pdata->axdomain = XGBE_DMA_OS_AXDOMAIN;
++ pdata->arcache = XGBE_DMA_OS_ARCACHE;
++ pdata->awcache = XGBE_DMA_OS_AWCACHE;
++ } else {
++ pdata->axdomain = XGBE_DMA_SYS_AXDOMAIN;
++ pdata->arcache = XGBE_DMA_SYS_ARCACHE;
++ pdata->awcache = XGBE_DMA_SYS_AWCACHE;
++ }
++
++ /* Set the DMA mask */
++ if (!dev->dma_mask)
++ dev->dma_mask = &dev->coherent_dma_mask;
++ ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(40));
++ if (ret) {
++ dev_err(dev, "dma_set_mask_and_coherent failed\n");
++ goto err_io;
++ }
++
++ /* Get the device interrupt */
++ ret = platform_get_irq(pdev, 0);
++ if (ret < 0) {
++ dev_err(dev, "platform_get_irq 0 failed\n");
++ goto err_io;
++ }
++ pdata->dev_irq = ret;
++
++ netdev->irq = pdata->dev_irq;
++ netdev->base_addr = (unsigned long)pdata->xgmac_regs;
++ memcpy(netdev->dev_addr, pdata->mac_addr, netdev->addr_len);
++
++ /* Set all the function pointers */
++ xgbe_init_all_fptrs(pdata);
++ hw_if = &pdata->hw_if;
++ desc_if = &pdata->desc_if;
++
++ /* Issue software reset to device */
++ hw_if->exit(pdata);
++
++ /* Populate the hardware features */
++ xgbe_a0_get_all_hw_features(pdata);
++
++ /* Set default configuration data */
++ xgbe_default_config(pdata);
++
++ /* Calculate the number of Tx and Rx rings to be created
++ * -Tx (DMA) Channels map 1-to-1 to Tx Queues so set
++ * the number of Tx queues to the number of Tx channels
++ * enabled
++ * -Rx (DMA) Channels do not map 1-to-1 so use the actual
++ * number of Rx queues
++ */
++ pdata->tx_ring_count = min_t(unsigned int, num_online_cpus(),
++ pdata->hw_feat.tx_ch_cnt);
++ pdata->tx_q_count = pdata->tx_ring_count;
++ ret = netif_set_real_num_tx_queues(netdev, pdata->tx_ring_count);
++ if (ret) {
++ dev_err(dev, "error setting real tx queue count\n");
++ goto err_io;
++ }
++
++ pdata->rx_ring_count = min_t(unsigned int,
++ netif_get_num_default_rss_queues(),
++ pdata->hw_feat.rx_ch_cnt);
++ pdata->rx_q_count = pdata->hw_feat.rx_q_cnt;
++ ret = netif_set_real_num_rx_queues(netdev, pdata->rx_ring_count);
++ if (ret) {
++ dev_err(dev, "error setting real rx queue count\n");
++ goto err_io;
++ }
++
++ /* Initialize RSS hash key and lookup table */
++ netdev_rss_key_fill(pdata->rss_key, sizeof(pdata->rss_key));
++
++ for (i = 0; i < XGBE_RSS_MAX_TABLE_SIZE; i++)
++ XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH,
++ i % pdata->rx_ring_count);
++
++ XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1);
++ XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1);
++ XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1);
++
++ /* Prepare to regsiter with MDIO */
++ pdata->mii_bus_id = kasprintf(GFP_KERNEL, "%s", pdev->name);
++ if (!pdata->mii_bus_id) {
++ dev_err(dev, "failed to allocate mii bus id\n");
++ ret = -ENOMEM;
++ goto err_io;
++ }
++ ret = xgbe_a0_mdio_register(pdata);
++ if (ret)
++ goto err_bus_id;
++
++ /* Set device operations */
++ netdev->netdev_ops = xgbe_a0_get_netdev_ops();
++ netdev->ethtool_ops = xgbe_a0_get_ethtool_ops();
++#ifdef CONFIG_AMD_XGBE_DCB
++ netdev->dcbnl_ops = xgbe_a0_get_dcbnl_ops();
++#endif
++
++ /* Set device features */
++ netdev->hw_features = NETIF_F_SG |
++ NETIF_F_IP_CSUM |
++ NETIF_F_IPV6_CSUM |
++ NETIF_F_RXCSUM |
++ NETIF_F_TSO |
++ NETIF_F_TSO6 |
++ NETIF_F_GRO |
++ NETIF_F_HW_VLAN_CTAG_RX |
++ NETIF_F_HW_VLAN_CTAG_TX |
++ NETIF_F_HW_VLAN_CTAG_FILTER;
++
++ if (pdata->hw_feat.rss)
++ netdev->hw_features |= NETIF_F_RXHASH;
++
++ netdev->vlan_features |= NETIF_F_SG |
++ NETIF_F_IP_CSUM |
++ NETIF_F_IPV6_CSUM |
++ NETIF_F_TSO |
++ NETIF_F_TSO6;
++
++ netdev->features |= netdev->hw_features;
++ pdata->netdev_features = netdev->features;
++
++ netdev->priv_flags |= IFF_UNICAST_FLT;
++
++ xgbe_a0_init_rx_coalesce(pdata);
++ xgbe_a0_init_tx_coalesce(pdata);
++
++ netif_carrier_off(netdev);
++ ret = register_netdev(netdev);
++ if (ret) {
++ dev_err(dev, "net device registration failed\n");
++ goto err_reg_netdev;
++ }
++
++ xgbe_a0_ptp_register(pdata);
++
++ xgbe_a0_debugfs_init(pdata);
++
++ netdev_notice(netdev, "net device enabled\n");
++
++ DBGPR("<-- xgbe_probe\n");
++
++ return 0;
++
++err_reg_netdev:
++ xgbe_a0_mdio_unregister(pdata);
++
++err_bus_id:
++ kfree(pdata->mii_bus_id);
++
++err_io:
++ free_netdev(netdev);
++
++err_alloc:
++ dev_notice(dev, "net device not enabled\n");
++
++ return ret;
++}
++
++static int xgbe_remove(struct platform_device *pdev)
++{
++ struct net_device *netdev = platform_get_drvdata(pdev);
++ struct xgbe_prv_data *pdata = netdev_priv(netdev);
++
++ DBGPR("-->xgbe_remove\n");
++
++ xgbe_a0_debugfs_exit(pdata);
++
++ xgbe_a0_ptp_unregister(pdata);
++
++ unregister_netdev(netdev);
++
++ xgbe_a0_mdio_unregister(pdata);
++
++ kfree(pdata->mii_bus_id);
++
++ free_netdev(netdev);
++
++ DBGPR("<--xgbe_remove\n");
++
++ return 0;
++}
++
++#ifdef CONFIG_PM
++static int xgbe_suspend(struct device *dev)
++{
++ struct net_device *netdev = dev_get_drvdata(dev);
++ int ret;
++
++ DBGPR("-->xgbe_suspend\n");
++
++ if (!netif_running(netdev)) {
++ DBGPR("<--xgbe_dev_suspend\n");
++ return -EINVAL;
++ }
++
++ ret = xgbe_a0_powerdown(netdev, XGMAC_DRIVER_CONTEXT);
++
++ DBGPR("<--xgbe_suspend\n");
++
++ return ret;
++}
++
++static int xgbe_resume(struct device *dev)
++{
++ struct net_device *netdev = dev_get_drvdata(dev);
++ int ret;
++
++ DBGPR("-->xgbe_resume\n");
++
++ if (!netif_running(netdev)) {
++ DBGPR("<--xgbe_dev_resume\n");
++ return -EINVAL;
++ }
++
++ ret = xgbe_a0_powerup(netdev, XGMAC_DRIVER_CONTEXT);
++
++ DBGPR("<--xgbe_resume\n");
++
++ return ret;
++}
++#endif /* CONFIG_PM */
++
++#ifdef CONFIG_ACPI
++static const struct acpi_device_id xgbe_a0_acpi_match[] = {
++ { "AMDI8000", 0 },
++ {},
++};
++
++MODULE_DEVICE_TABLE(acpi, xgbe_a0_acpi_match);
++#endif
++
++#ifdef CONFIG_OF
++static const struct of_device_id xgbe_a0_of_match[] = {
++ { .compatible = "amd,xgbe-seattle-v0a", },
++ {},
++};
++
++MODULE_DEVICE_TABLE(of, xgbe_a0_of_match);
++#endif
++
++static SIMPLE_DEV_PM_OPS(xgbe_pm_ops, xgbe_suspend, xgbe_resume);
++
++static struct platform_driver xgbe_a0_driver = {
++ .driver = {
++ .name = "amd-xgbe-a0",
++#ifdef CONFIG_ACPI
++ .acpi_match_table = xgbe_a0_acpi_match,
++#endif
++#ifdef CONFIG_OF
++ .of_match_table = xgbe_a0_of_match,
++#endif
++ .pm = &xgbe_pm_ops,
++ },
++ .probe = xgbe_probe,
++ .remove = xgbe_remove,
++};
++
++module_platform_driver(xgbe_a0_driver);
+diff --git a/drivers/net/ethernet/amd/xgbe-a0/xgbe-mdio.c b/drivers/net/ethernet/amd/xgbe-a0/xgbe-mdio.c
+new file mode 100644
+index 000000000000..b84d0481bed8
+--- /dev/null
++++ b/drivers/net/ethernet/amd/xgbe-a0/xgbe-mdio.c
+@@ -0,0 +1,312 @@
++/*
++ * AMD 10Gb Ethernet driver
++ *
++ * This file is available to you under your choice of the following two
++ * licenses:
++ *
++ * License 1: GPLv2
++ *
++ * Copyright (c) 2014 Advanced Micro Devices, Inc.
++ *
++ * This file is free software; you may copy, redistribute and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 2 of the License, or (at
++ * your option) any later version.
++ *
++ * This file is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ *
++ * This file incorporates work covered by the following copyright and
++ * permission notice:
++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation
++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
++ * Inc. unless otherwise expressly agreed to in writing between Synopsys
++ * and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product
++ * under any End User Software License Agreement or Agreement for Licensed
++ * Product with Synopsys or any supplement thereto. Permission is hereby
++ * granted, free of charge, to any person obtaining a copy of this software
++ * annotated with this license and the Software, to deal in the Software
++ * without restriction, including without limitation the rights to use,
++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
++ * of the Software, and to permit persons to whom the Software is furnished
++ * to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
++ * THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ *
++ * License 2: Modified BSD
++ *
++ * Copyright (c) 2014 Advanced Micro Devices, Inc.
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * * Neither the name of Advanced Micro Devices, Inc. nor the
++ * names of its contributors may be used to endorse or promote products
++ * derived from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * This file incorporates work covered by the following copyright and
++ * permission notice:
++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation
++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
++ * Inc. unless otherwise expressly agreed to in writing between Synopsys
++ * and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product
++ * under any End User Software License Agreement or Agreement for Licensed
++ * Product with Synopsys or any supplement thereto. Permission is hereby
++ * granted, free of charge, to any person obtaining a copy of this software
++ * annotated with this license and the Software, to deal in the Software
++ * without restriction, including without limitation the rights to use,
++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
++ * of the Software, and to permit persons to whom the Software is furnished
++ * to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
++ * THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include <linux/module.h>
++#include <linux/kmod.h>
++#include <linux/mdio.h>
++#include <linux/phy.h>
++#include <linux/of.h>
++
++#include "xgbe.h"
++#include "xgbe-common.h"
++
++static int xgbe_mdio_read(struct mii_bus *mii, int prtad, int mmd_reg)
++{
++ struct xgbe_prv_data *pdata = mii->priv;
++ struct xgbe_hw_if *hw_if = &pdata->hw_if;
++ int mmd_data;
++
++ DBGPR_MDIO("-->xgbe_mdio_read: prtad=%#x mmd_reg=%#x\n",
++ prtad, mmd_reg);
++
++ mmd_data = hw_if->read_mmd_regs(pdata, prtad, mmd_reg);
++
++ DBGPR_MDIO("<--xgbe_mdio_read: mmd_data=%#x\n", mmd_data);
++
++ return mmd_data;
++}
++
++static int xgbe_mdio_write(struct mii_bus *mii, int prtad, int mmd_reg,
++ u16 mmd_val)
++{
++ struct xgbe_prv_data *pdata = mii->priv;
++ struct xgbe_hw_if *hw_if = &pdata->hw_if;
++ int mmd_data = mmd_val;
++
++ DBGPR_MDIO("-->xgbe_mdio_write: prtad=%#x mmd_reg=%#x mmd_data=%#x\n",
++ prtad, mmd_reg, mmd_data);
++
++ hw_if->write_mmd_regs(pdata, prtad, mmd_reg, mmd_data);
++
++ DBGPR_MDIO("<--xgbe_mdio_write\n");
++
++ return 0;
++}
++
++void xgbe_a0_dump_phy_registers(struct xgbe_prv_data *pdata)
++{
++ struct device *dev = pdata->dev;
++ struct phy_device *phydev = pdata->mii->phy_map[XGBE_PRTAD];
++ int i;
++
++ dev_alert(dev, "\n************* PHY Reg dump **********************\n");
++
++ dev_alert(dev, "PCS Control Reg (%#04x) = %#04x\n", MDIO_CTRL1,
++ XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_CTRL1));
++ dev_alert(dev, "PCS Status Reg (%#04x) = %#04x\n", MDIO_STAT1,
++ XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_STAT1));
++ dev_alert(dev, "Phy Id (PHYS ID 1 %#04x)= %#04x\n", MDIO_DEVID1,
++ XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID1));
++ dev_alert(dev, "Phy Id (PHYS ID 2 %#04x)= %#04x\n", MDIO_DEVID2,
++ XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVID2));
++ dev_alert(dev, "Devices in Package (%#04x)= %#04x\n", MDIO_DEVS1,
++ XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS1));
++ dev_alert(dev, "Devices in Package (%#04x)= %#04x\n", MDIO_DEVS2,
++ XMDIO_READ(pdata, MDIO_MMD_PCS, MDIO_DEVS2));
++
++ dev_alert(dev, "Auto-Neg Control Reg (%#04x) = %#04x\n", MDIO_CTRL1,
++ XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_CTRL1));
++ dev_alert(dev, "Auto-Neg Status Reg (%#04x) = %#04x\n", MDIO_STAT1,
++ XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_STAT1));
++ dev_alert(dev, "Auto-Neg Ad Reg 1 (%#04x) = %#04x\n",
++ MDIO_AN_ADVERTISE,
++ XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE));
++ dev_alert(dev, "Auto-Neg Ad Reg 2 (%#04x) = %#04x\n",
++ MDIO_AN_ADVERTISE + 1,
++ XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 1));
++ dev_alert(dev, "Auto-Neg Ad Reg 3 (%#04x) = %#04x\n",
++ MDIO_AN_ADVERTISE + 2,
++ XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_ADVERTISE + 2));
++ dev_alert(dev, "Auto-Neg Completion Reg (%#04x) = %#04x\n",
++ MDIO_AN_COMP_STAT,
++ XMDIO_READ(pdata, MDIO_MMD_AN, MDIO_AN_COMP_STAT));
++
++ dev_alert(dev, "MMD Device Mask = %#x\n",
++ phydev->c45_ids.devices_in_package);
++ for (i = 0; i < ARRAY_SIZE(phydev->c45_ids.device_ids); i++)
++ dev_alert(dev, " MMD %d: ID = %#08x\n", i,
++ phydev->c45_ids.device_ids[i]);
++
++ dev_alert(dev, "\n*************************************************\n");
++}
++
++int xgbe_a0_mdio_register(struct xgbe_prv_data *pdata)
++{
++ struct mii_bus *mii;
++ struct phy_device *phydev;
++ int ret = 0;
++
++ DBGPR("-->xgbe_a0_mdio_register\n");
++
++ mii = mdiobus_alloc();
++ if (!mii) {
++ dev_err(pdata->dev, "mdiobus_alloc failed\n");
++ return -ENOMEM;
++ }
++
++ /* Register on the MDIO bus (don't probe any PHYs) */
++ mii->name = XGBE_PHY_NAME;
++ mii->read = xgbe_mdio_read;
++ mii->write = xgbe_mdio_write;
++ snprintf(mii->id, sizeof(mii->id), "%s", pdata->mii_bus_id);
++ mii->priv = pdata;
++ mii->phy_mask = ~0;
++ mii->parent = pdata->dev;
++ ret = mdiobus_register(mii);
++ if (ret) {
++ dev_err(pdata->dev, "mdiobus_register failed\n");
++ goto err_mdiobus_alloc;
++ }
++ DBGPR(" mdiobus_register succeeded for %s\n", pdata->mii_bus_id);
++
++ /* Probe the PCS using Clause 45 */
++ phydev = get_phy_device(mii, XGBE_PRTAD, true);
++ if (IS_ERR(phydev) || !phydev ||
++ !phydev->c45_ids.device_ids[MDIO_MMD_PCS]) {
++ dev_err(pdata->dev, "get_phy_device failed\n");
++ ret = phydev ? PTR_ERR(phydev) : -ENOLINK;
++ goto err_mdiobus_register;
++ }
++ request_module(MDIO_MODULE_PREFIX MDIO_ID_FMT,
++ MDIO_ID_ARGS(phydev->c45_ids.device_ids[MDIO_MMD_PCS]));
++
++ ret = phy_device_register(phydev);
++ if (ret) {
++ dev_err(pdata->dev, "phy_device_register failed\n");
++ goto err_phy_device;
++ }
++ if (!phydev->dev.driver) {
++ dev_err(pdata->dev, "phy driver probe failed\n");
++ ret = -EIO;
++ goto err_phy_device;
++ }
++
++ /* Add a reference to the PHY driver so it can't be unloaded */
++ pdata->phy_module = phydev->dev.driver->owner;
++ if (!try_module_get(pdata->phy_module)) {
++ dev_err(pdata->dev, "try_module_get failed\n");
++ ret = -EIO;
++ goto err_phy_device;
++ }
++
++ pdata->mii = mii;
++ pdata->mdio_mmd = MDIO_MMD_PCS;
++
++ phydev->autoneg = pdata->default_autoneg;
++ if (phydev->autoneg == AUTONEG_DISABLE) {
++ phydev->speed = pdata->default_speed;
++ phydev->duplex = DUPLEX_FULL;
++
++ phydev->advertising &= ~ADVERTISED_Autoneg;
++ }
++
++ pdata->phydev = phydev;
++
++ DBGPHY_REGS(pdata);
++
++ DBGPR("<--xgbe_a0_mdio_register\n");
++
++ return 0;
++
++err_phy_device:
++ phy_device_free(phydev);
++
++err_mdiobus_register:
++ mdiobus_unregister(mii);
++
++err_mdiobus_alloc:
++ mdiobus_free(mii);
++
++ return ret;
++}
++
++void xgbe_a0_mdio_unregister(struct xgbe_prv_data *pdata)
++{
++ DBGPR("-->xgbe_a0_mdio_unregister\n");
++
++ pdata->phydev = NULL;
++
++ module_put(pdata->phy_module);
++ pdata->phy_module = NULL;
++
++ mdiobus_unregister(pdata->mii);
++ pdata->mii->priv = NULL;
++
++ mdiobus_free(pdata->mii);
++ pdata->mii = NULL;
++
++ DBGPR("<--xgbe_a0_mdio_unregister\n");
++}
+diff --git a/drivers/net/ethernet/amd/xgbe-a0/xgbe-ptp.c b/drivers/net/ethernet/amd/xgbe-a0/xgbe-ptp.c
+new file mode 100644
+index 000000000000..c53c7b2a4b08
+--- /dev/null
++++ b/drivers/net/ethernet/amd/xgbe-a0/xgbe-ptp.c
+@@ -0,0 +1,284 @@
++/*
++ * AMD 10Gb Ethernet driver
++ *
++ * This file is available to you under your choice of the following two
++ * licenses:
++ *
++ * License 1: GPLv2
++ *
++ * Copyright (c) 2014 Advanced Micro Devices, Inc.
++ *
++ * This file is free software; you may copy, redistribute and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 2 of the License, or (at
++ * your option) any later version.
++ *
++ * This file is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ *
++ * This file incorporates work covered by the following copyright and
++ * permission notice:
++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation
++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
++ * Inc. unless otherwise expressly agreed to in writing between Synopsys
++ * and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product
++ * under any End User Software License Agreement or Agreement for Licensed
++ * Product with Synopsys or any supplement thereto. Permission is hereby
++ * granted, free of charge, to any person obtaining a copy of this software
++ * annotated with this license and the Software, to deal in the Software
++ * without restriction, including without limitation the rights to use,
++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
++ * of the Software, and to permit persons to whom the Software is furnished
++ * to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
++ * THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ *
++ * License 2: Modified BSD
++ *
++ * Copyright (c) 2014 Advanced Micro Devices, Inc.
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * * Neither the name of Advanced Micro Devices, Inc. nor the
++ * names of its contributors may be used to endorse or promote products
++ * derived from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * This file incorporates work covered by the following copyright and
++ * permission notice:
++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation
++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
++ * Inc. unless otherwise expressly agreed to in writing between Synopsys
++ * and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product
++ * under any End User Software License Agreement or Agreement for Licensed
++ * Product with Synopsys or any supplement thereto. Permission is hereby
++ * granted, free of charge, to any person obtaining a copy of this software
++ * annotated with this license and the Software, to deal in the Software
++ * without restriction, including without limitation the rights to use,
++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
++ * of the Software, and to permit persons to whom the Software is furnished
++ * to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
++ * THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#include <linux/clk.h>
++#include <linux/clocksource.h>
++#include <linux/ptp_clock_kernel.h>
++#include <linux/net_tstamp.h>
++
++#include "xgbe.h"
++#include "xgbe-common.h"
++
++static cycle_t xgbe_cc_read(const struct cyclecounter *cc)
++{
++ struct xgbe_prv_data *pdata = container_of(cc,
++ struct xgbe_prv_data,
++ tstamp_cc);
++ u64 nsec;
++
++ nsec = pdata->hw_if.get_tstamp_time(pdata);
++
++ return nsec;
++}
++
++static int xgbe_adjfreq(struct ptp_clock_info *info, s32 delta)
++{
++ struct xgbe_prv_data *pdata = container_of(info,
++ struct xgbe_prv_data,
++ ptp_clock_info);
++ unsigned long flags;
++ u64 adjust;
++ u32 addend, diff;
++ unsigned int neg_adjust = 0;
++
++ if (delta < 0) {
++ neg_adjust = 1;
++ delta = -delta;
++ }
++
++ adjust = pdata->tstamp_addend;
++ adjust *= delta;
++ diff = div_u64(adjust, 1000000000UL);
++
++ addend = (neg_adjust) ? pdata->tstamp_addend - diff :
++ pdata->tstamp_addend + diff;
++
++ spin_lock_irqsave(&pdata->tstamp_lock, flags);
++
++ pdata->hw_if.update_tstamp_addend(pdata, addend);
++
++ spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
++
++ return 0;
++}
++
++static int xgbe_adjtime(struct ptp_clock_info *info, s64 delta)
++{
++ struct xgbe_prv_data *pdata = container_of(info,
++ struct xgbe_prv_data,
++ ptp_clock_info);
++ unsigned long flags;
++ u64 nsec;
++
++ spin_lock_irqsave(&pdata->tstamp_lock, flags);
++
++ nsec = timecounter_read(&pdata->tstamp_tc);
++
++ nsec += delta;
++ timecounter_init(&pdata->tstamp_tc, &pdata->tstamp_cc, nsec);
++
++ spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
++
++ return 0;
++}
++
++static int xgbe_gettime(struct ptp_clock_info *info, struct timespec *ts)
++{
++ struct xgbe_prv_data *pdata = container_of(info,
++ struct xgbe_prv_data,
++ ptp_clock_info);
++ unsigned long flags;
++ u64 nsec;
++
++ spin_lock_irqsave(&pdata->tstamp_lock, flags);
++
++ nsec = timecounter_read(&pdata->tstamp_tc);
++
++ spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
++
++ *ts = ns_to_timespec(nsec);
++
++ return 0;
++}
++
++static int xgbe_settime(struct ptp_clock_info *info, const struct timespec *ts)
++{
++ struct xgbe_prv_data *pdata = container_of(info,
++ struct xgbe_prv_data,
++ ptp_clock_info);
++ unsigned long flags;
++ u64 nsec;
++
++ nsec = timespec_to_ns(ts);
++
++ spin_lock_irqsave(&pdata->tstamp_lock, flags);
++
++ timecounter_init(&pdata->tstamp_tc, &pdata->tstamp_cc, nsec);
++
++ spin_unlock_irqrestore(&pdata->tstamp_lock, flags);
++
++ return 0;
++}
++
++static int xgbe_enable(struct ptp_clock_info *info,
++ struct ptp_clock_request *request, int on)
++{
++ return -EOPNOTSUPP;
++}
++
++void xgbe_a0_ptp_register(struct xgbe_prv_data *pdata)
++{
++ struct ptp_clock_info *info = &pdata->ptp_clock_info;
++ struct ptp_clock *clock;
++ struct cyclecounter *cc = &pdata->tstamp_cc;
++ u64 dividend;
++
++ snprintf(info->name, sizeof(info->name), "%s",
++ netdev_name(pdata->netdev));
++ info->owner = THIS_MODULE;
++ info->max_adj = pdata->ptpclk_rate;
++ info->adjfreq = xgbe_adjfreq;
++ info->adjtime = xgbe_adjtime;
++ info->gettime = xgbe_gettime;
++ info->settime = xgbe_settime;
++ info->enable = xgbe_enable;
++
++ clock = ptp_clock_register(info, pdata->dev);
++ if (IS_ERR(clock)) {
++ dev_err(pdata->dev, "ptp_clock_register failed\n");
++ return;
++ }
++
++ pdata->ptp_clock = clock;
++
++ /* Calculate the addend:
++ * addend = 2^32 / (PTP ref clock / 50Mhz)
++ * = (2^32 * 50Mhz) / PTP ref clock
++ */
++ dividend = 50000000;
++ dividend <<= 32;
++ pdata->tstamp_addend = div_u64(dividend, pdata->ptpclk_rate);
++
++ /* Setup the timecounter */
++ cc->read = xgbe_cc_read;
++ cc->mask = CLOCKSOURCE_MASK(64);
++ cc->mult = 1;
++ cc->shift = 0;
++
++ timecounter_init(&pdata->tstamp_tc, &pdata->tstamp_cc,
++ ktime_to_ns(ktime_get_real()));
++
++ /* Disable all timestamping to start */
++ XGMAC_IOWRITE(pdata, MAC_TCR, 0);
++ pdata->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
++ pdata->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
++}
++
++void xgbe_a0_ptp_unregister(struct xgbe_prv_data *pdata)
++{
++ if (pdata->ptp_clock)
++ ptp_clock_unregister(pdata->ptp_clock);
++}
+diff --git a/drivers/net/ethernet/amd/xgbe-a0/xgbe.h b/drivers/net/ethernet/amd/xgbe-a0/xgbe.h
+new file mode 100644
+index 000000000000..dd8500da98a6
+--- /dev/null
++++ b/drivers/net/ethernet/amd/xgbe-a0/xgbe.h
+@@ -0,0 +1,868 @@
++/*
++ * AMD 10Gb Ethernet driver
++ *
++ * This file is available to you under your choice of the following two
++ * licenses:
++ *
++ * License 1: GPLv2
++ *
++ * Copyright (c) 2014 Advanced Micro Devices, Inc.
++ *
++ * This file is free software; you may copy, redistribute and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation, either version 2 of the License, or (at
++ * your option) any later version.
++ *
++ * This file is distributed in the hope that it will be useful, but
++ * WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
++ * General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program. If not, see <http://www.gnu.org/licenses/>.
++ *
++ * This file incorporates work covered by the following copyright and
++ * permission notice:
++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation
++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
++ * Inc. unless otherwise expressly agreed to in writing between Synopsys
++ * and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product
++ * under any End User Software License Agreement or Agreement for Licensed
++ * Product with Synopsys or any supplement thereto. Permission is hereby
++ * granted, free of charge, to any person obtaining a copy of this software
++ * annotated with this license and the Software, to deal in the Software
++ * without restriction, including without limitation the rights to use,
++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
++ * of the Software, and to permit persons to whom the Software is furnished
++ * to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
++ * THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ *
++ * License 2: Modified BSD
++ *
++ * Copyright (c) 2014 Advanced Micro Devices, Inc.
++ * All rights reserved.
++ *
++ * Redistribution and use in source and binary forms, with or without
++ * modification, are permitted provided that the following conditions are met:
++ * * Redistributions of source code must retain the above copyright
++ * notice, this list of conditions and the following disclaimer.
++ * * Redistributions in binary form must reproduce the above copyright
++ * notice, this list of conditions and the following disclaimer in the
++ * documentation and/or other materials provided with the distribution.
++ * * Neither the name of Advanced Micro Devices, Inc. nor the
++ * names of its contributors may be used to endorse or promote products
++ * derived from this software without specific prior written permission.
++ *
++ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
++ * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
++ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
++ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
++ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
++ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
++ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
++ *
++ * This file incorporates work covered by the following copyright and
++ * permission notice:
++ * The Synopsys DWC ETHER XGMAC Software Driver and documentation
++ * (hereinafter "Software") is an unsupported proprietary work of Synopsys,
++ * Inc. unless otherwise expressly agreed to in writing between Synopsys
++ * and you.
++ *
++ * The Software IS NOT an item of Licensed Software or Licensed Product
++ * under any End User Software License Agreement or Agreement for Licensed
++ * Product with Synopsys or any supplement thereto. Permission is hereby
++ * granted, free of charge, to any person obtaining a copy of this software
++ * annotated with this license and the Software, to deal in the Software
++ * without restriction, including without limitation the rights to use,
++ * copy, modify, merge, publish, distribute, sublicense, and/or sell copies
++ * of the Software, and to permit persons to whom the Software is furnished
++ * to do so, subject to the following conditions:
++ *
++ * The above copyright notice and this permission notice shall be included
++ * in all copies or substantial portions of the Software.
++ *
++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
++ * BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
++ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
++ * PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
++ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
++ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
++ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
++ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
++ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
++ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
++ * THE POSSIBILITY OF SUCH DAMAGE.
++ */
++
++#ifndef __XGBE_H__
++#define __XGBE_H__
++
++#include <linux/dma-mapping.h>
++#include <linux/netdevice.h>
++#include <linux/workqueue.h>
++#include <linux/phy.h>
++#include <linux/if_vlan.h>
++#include <linux/bitops.h>
++#include <linux/ptp_clock_kernel.h>
++#include <linux/clocksource.h>
++#include <linux/net_tstamp.h>
++#include <net/dcbnl.h>
++
++#define XGBE_DRV_NAME "amd-xgbe"
++#define XGBE_DRV_VERSION "0.0.0-a"
++#define XGBE_DRV_DESC "AMD 10 Gigabit Ethernet Driver"
++
++/* Descriptor related defines */
++#define XGBE_TX_DESC_CNT 512
++#define XGBE_TX_DESC_MIN_FREE (XGBE_TX_DESC_CNT >> 3)
++#define XGBE_TX_DESC_MAX_PROC (XGBE_TX_DESC_CNT >> 1)
++#define XGBE_RX_DESC_CNT 512
++
++#define XGBE_TX_MAX_BUF_SIZE (0x3fff & ~(64 - 1))
++
++/* Descriptors required for maximum contigous TSO/GSO packet */
++#define XGBE_TX_MAX_SPLIT ((GSO_MAX_SIZE / XGBE_TX_MAX_BUF_SIZE) + 1)
++
++/* Maximum possible descriptors needed for an SKB:
++ * - Maximum number of SKB frags
++ * - Maximum descriptors for contiguous TSO/GSO packet
++ * - Possible context descriptor
++ * - Possible TSO header descriptor
++ */
++#define XGBE_TX_MAX_DESCS (MAX_SKB_FRAGS + XGBE_TX_MAX_SPLIT + 2)
++
++#define XGBE_RX_MIN_BUF_SIZE (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
++#define XGBE_RX_BUF_ALIGN 64
++#define XGBE_SKB_ALLOC_SIZE 256
++#define XGBE_SPH_HDSMS_SIZE 2 /* Keep in sync with SKB_ALLOC_SIZE */
++
++#define XGBE_MAX_DMA_CHANNELS 16
++#define XGBE_MAX_QUEUES 16
++#define XGBE_DMA_STOP_TIMEOUT 5
++
++/* DMA cache settings - Outer sharable, write-back, write-allocate */
++#define XGBE_DMA_OS_AXDOMAIN 0x2
++#define XGBE_DMA_OS_ARCACHE 0xb
++#define XGBE_DMA_OS_AWCACHE 0xf
++
++/* DMA cache settings - System, no caches used */
++#define XGBE_DMA_SYS_AXDOMAIN 0x3
++#define XGBE_DMA_SYS_ARCACHE 0x0
++#define XGBE_DMA_SYS_AWCACHE 0x0
++
++#define XGBE_DMA_INTERRUPT_MASK 0x31c7
++
++#define XGMAC_MIN_PACKET 60
++#define XGMAC_STD_PACKET_MTU 1500
++#define XGMAC_MAX_STD_PACKET 1518
++#define XGMAC_JUMBO_PACKET_MTU 9000
++#define XGMAC_MAX_JUMBO_PACKET 9018
++
++/* MDIO bus phy name */
++#define XGBE_PHY_NAME "amd_xgbe_phy_a0"
++#define XGBE_PRTAD 0
++
++/* Common property names */
++#define XGBE_MAC_ADDR_PROPERTY "mac-address"
++#define XGBE_PHY_MODE_PROPERTY "phy-mode"
++#define XGBE_DMA_IRQS_PROPERTY "amd,per-channel-interrupt"
++
++/* Device-tree clock names */
++#define XGBE_DMA_CLOCK "dma_clk"
++#define XGBE_PTP_CLOCK "ptp_clk"
++
++/* ACPI property names */
++#define XGBE_ACPI_DMA_FREQ "amd,dma-freq"
++#define XGBE_ACPI_PTP_FREQ "amd,ptp-freq"
++
++/* Timestamp support - values based on 50MHz PTP clock
++ * 50MHz => 20 nsec
++ */
++#define XGBE_TSTAMP_SSINC 20
++#define XGBE_TSTAMP_SNSINC 0
++
++/* Driver PMT macros */
++#define XGMAC_DRIVER_CONTEXT 1
++#define XGMAC_IOCTL_CONTEXT 2
++
++#define XGBE_FIFO_MAX 81920
++#define XGBE_FIFO_SIZE_B(x) (x)
++#define XGBE_FIFO_SIZE_KB(x) (x * 1024)
++
++#define XGBE_TC_MIN_QUANTUM 10
++
++/* Helper macro for descriptor handling
++ * Always use XGBE_GET_DESC_DATA to access the descriptor data
++ * since the index is free-running and needs to be and-ed
++ * with the descriptor count value of the ring to index to
++ * the proper descriptor data.
++ */
++#define XGBE_GET_DESC_DATA(_ring, _idx) \
++ ((_ring)->rdata + \
++ ((_idx) & ((_ring)->rdesc_count - 1)))
++
++/* Default coalescing parameters */
++#define XGMAC_INIT_DMA_TX_USECS 50
++#define XGMAC_INIT_DMA_TX_FRAMES 25
++
++#define XGMAC_MAX_DMA_RIWT 0xff
++#define XGMAC_INIT_DMA_RX_USECS 30
++#define XGMAC_INIT_DMA_RX_FRAMES 25
++
++/* Flow control queue count */
++#define XGMAC_MAX_FLOW_CONTROL_QUEUES 8
++
++/* Maximum MAC address hash table size (256 bits = 8 bytes) */
++#define XGBE_MAC_HASH_TABLE_SIZE 8
++
++/* Receive Side Scaling */
++#define XGBE_RSS_HASH_KEY_SIZE 40
++#define XGBE_RSS_MAX_TABLE_SIZE 256
++#define XGBE_RSS_LOOKUP_TABLE_TYPE 0
++#define XGBE_RSS_HASH_KEY_TYPE 1
++
++struct xgbe_prv_data;
++
++struct xgbe_packet_data {
++ struct sk_buff *skb;
++
++ unsigned int attributes;
++
++ unsigned int errors;
++
++ unsigned int rdesc_count;
++ unsigned int length;
++
++ unsigned int header_len;
++ unsigned int tcp_header_len;
++ unsigned int tcp_payload_len;
++ unsigned short mss;
++
++ unsigned short vlan_ctag;
++
++ u64 rx_tstamp;
++
++ u32 rss_hash;
++ enum pkt_hash_types rss_hash_type;
++
++ unsigned int tx_packets;
++ unsigned int tx_bytes;
++};
++
++/* Common Rx and Tx descriptor mapping */
++struct xgbe_ring_desc {
++ __le32 desc0;
++ __le32 desc1;
++ __le32 desc2;
++ __le32 desc3;
++};
++
++/* Page allocation related values */
++struct xgbe_page_alloc {
++ struct page *pages;
++ unsigned int pages_len;
++ unsigned int pages_offset;
++
++ dma_addr_t pages_dma;
++};
++
++/* Ring entry buffer data */
++struct xgbe_buffer_data {
++ struct xgbe_page_alloc pa;
++ struct xgbe_page_alloc pa_unmap;
++
++ dma_addr_t dma;
++ unsigned int dma_len;
++};
++
++/* Tx-related ring data */
++struct xgbe_tx_ring_data {
++ unsigned int packets; /* BQL packet count */
++ unsigned int bytes; /* BQL byte count */
++};
++
++/* Rx-related ring data */
++struct xgbe_rx_ring_data {
++ struct xgbe_buffer_data hdr; /* Header locations */
++ struct xgbe_buffer_data buf; /* Payload locations */
++
++ unsigned short hdr_len; /* Length of received header */
++ unsigned short len; /* Length of received packet */
++};
++
++/* Structure used to hold information related to the descriptor
++ * and the packet associated with the descriptor (always use
++ * use the XGBE_GET_DESC_DATA macro to access this data from the ring)
++ */
++struct xgbe_ring_data {
++ struct xgbe_ring_desc *rdesc; /* Virtual address of descriptor */
++ dma_addr_t rdesc_dma; /* DMA address of descriptor */
++
++ struct sk_buff *skb; /* Virtual address of SKB */
++ dma_addr_t skb_dma; /* DMA address of SKB data */
++ unsigned int skb_dma_len; /* Length of SKB DMA area */
++
++ struct xgbe_tx_ring_data tx; /* Tx-related data */
++ struct xgbe_rx_ring_data rx; /* Rx-related data */
++
++ unsigned int interrupt; /* Interrupt indicator */
++
++ unsigned int mapped_as_page;
++
++ /* Incomplete receive save location. If the budget is exhausted
++ * or the last descriptor (last normal descriptor or a following
++ * context descriptor) has not been DMA'd yet the current state
++ * of the receive processing needs to be saved.
++ */
++ unsigned int state_saved;
++ struct {
++ unsigned int incomplete;
++ unsigned int context_next;
++ struct sk_buff *skb;
++ unsigned int len;
++ unsigned int error;
++ } state;
++};
++
++struct xgbe_ring {
++ /* Ring lock - used just for TX rings at the moment */
++ spinlock_t lock;
++
++ /* Per packet related information */
++ struct xgbe_packet_data packet_data;
++
++ /* Virtual/DMA addresses and count of allocated descriptor memory */
++ struct xgbe_ring_desc *rdesc;
++ dma_addr_t rdesc_dma;
++ unsigned int rdesc_count;
++
++ /* Array of descriptor data corresponding the descriptor memory
++ * (always use the XGBE_GET_DESC_DATA macro to access this data)
++ */
++ struct xgbe_ring_data *rdata;
++
++ /* Page allocation for RX buffers */
++ struct xgbe_page_alloc rx_hdr_pa;
++ struct xgbe_page_alloc rx_buf_pa;
++
++ /* Ring index values
++ * cur - Tx: index of descriptor to be used for current transfer
++ * Rx: index of descriptor to check for packet availability
++ * dirty - Tx: index of descriptor to check for transfer complete
++ * Rx: index of descriptor to check for buffer reallocation
++ */
++ unsigned int cur;
++ unsigned int dirty;
++
++ /* Coalesce frame count used for interrupt bit setting */
++ unsigned int coalesce_count;
++
++ union {
++ struct {
++ unsigned int queue_stopped;
++ unsigned int xmit_more;
++ unsigned short cur_mss;
++ unsigned short cur_vlan_ctag;
++ } tx;
++ };
++} ____cacheline_aligned;
++
++/* Structure used to describe the descriptor rings associated with
++ * a DMA channel.
++ */
++struct xgbe_channel {
++ char name[16];
++
++ /* Address of private data area for device */
++ struct xgbe_prv_data *pdata;
++
++ /* Queue index and base address of queue's DMA registers */
++ unsigned int queue_index;
++ void __iomem *dma_regs;
++
++ /* Per channel interrupt irq number */
++ int dma_irq;
++ char dma_irq_name[IFNAMSIZ + 32];
++
++ /* Netdev related settings */
++ struct napi_struct napi;
++
++ unsigned int saved_ier;
++
++ unsigned int tx_timer_active;
++ struct hrtimer tx_timer;
++
++ struct xgbe_ring *tx_ring;
++ struct xgbe_ring *rx_ring;
++} ____cacheline_aligned;
++
++enum xgbe_int {
++ XGMAC_INT_DMA_CH_SR_TI,
++ XGMAC_INT_DMA_CH_SR_TPS,
++ XGMAC_INT_DMA_CH_SR_TBU,
++ XGMAC_INT_DMA_CH_SR_RI,
++ XGMAC_INT_DMA_CH_SR_RBU,
++ XGMAC_INT_DMA_CH_SR_RPS,
++ XGMAC_INT_DMA_CH_SR_TI_RI,
++ XGMAC_INT_DMA_CH_SR_FBE,
++ XGMAC_INT_DMA_ALL,
++};
++
++enum xgbe_int_state {
++ XGMAC_INT_STATE_SAVE,
++ XGMAC_INT_STATE_RESTORE,
++};
++
++enum xgbe_mtl_fifo_size {
++ XGMAC_MTL_FIFO_SIZE_256 = 0x00,
++ XGMAC_MTL_FIFO_SIZE_512 = 0x01,
++ XGMAC_MTL_FIFO_SIZE_1K = 0x03,
++ XGMAC_MTL_FIFO_SIZE_2K = 0x07,
++ XGMAC_MTL_FIFO_SIZE_4K = 0x0f,
++ XGMAC_MTL_FIFO_SIZE_8K = 0x1f,
++ XGMAC_MTL_FIFO_SIZE_16K = 0x3f,
++ XGMAC_MTL_FIFO_SIZE_32K = 0x7f,
++ XGMAC_MTL_FIFO_SIZE_64K = 0xff,
++ XGMAC_MTL_FIFO_SIZE_128K = 0x1ff,
++ XGMAC_MTL_FIFO_SIZE_256K = 0x3ff,
++};
++
++struct xgbe_mmc_stats {
++ /* Tx Stats */
++ u64 txoctetcount_gb;
++ u64 txframecount_gb;
++ u64 txbroadcastframes_g;
++ u64 txmulticastframes_g;
++ u64 tx64octets_gb;
++ u64 tx65to127octets_gb;
++ u64 tx128to255octets_gb;
++ u64 tx256to511octets_gb;
++ u64 tx512to1023octets_gb;
++ u64 tx1024tomaxoctets_gb;
++ u64 txunicastframes_gb;
++ u64 txmulticastframes_gb;
++ u64 txbroadcastframes_gb;
++ u64 txunderflowerror;
++ u64 txoctetcount_g;
++ u64 txframecount_g;
++ u64 txpauseframes;
++ u64 txvlanframes_g;
++
++ /* Rx Stats */
++ u64 rxframecount_gb;
++ u64 rxoctetcount_gb;
++ u64 rxoctetcount_g;
++ u64 rxbroadcastframes_g;
++ u64 rxmulticastframes_g;
++ u64 rxcrcerror;
++ u64 rxrunterror;
++ u64 rxjabbererror;
++ u64 rxundersize_g;
++ u64 rxoversize_g;
++ u64 rx64octets_gb;
++ u64 rx65to127octets_gb;
++ u64 rx128to255octets_gb;
++ u64 rx256to511octets_gb;
++ u64 rx512to1023octets_gb;
++ u64 rx1024tomaxoctets_gb;
++ u64 rxunicastframes_g;
++ u64 rxlengtherror;
++ u64 rxoutofrangetype;
++ u64 rxpauseframes;
++ u64 rxfifooverflow;
++ u64 rxvlanframes_gb;
++ u64 rxwatchdogerror;
++};
++
++struct xgbe_hw_if {
++ int (*tx_complete)(struct xgbe_ring_desc *);
++
++ int (*set_promiscuous_mode)(struct xgbe_prv_data *, unsigned int);
++ int (*set_all_multicast_mode)(struct xgbe_prv_data *, unsigned int);
++ int (*add_mac_addresses)(struct xgbe_prv_data *);
++ int (*set_mac_address)(struct xgbe_prv_data *, u8 *addr);
++
++ int (*enable_rx_csum)(struct xgbe_prv_data *);
++ int (*disable_rx_csum)(struct xgbe_prv_data *);
++
++ int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *);
++ int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *);
++ int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *);
++ int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *);
++ int (*update_vlan_hash_table)(struct xgbe_prv_data *);
++
++ int (*read_mmd_regs)(struct xgbe_prv_data *, int, int);
++ void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int);
++ int (*set_gmii_speed)(struct xgbe_prv_data *);
++ int (*set_gmii_2500_speed)(struct xgbe_prv_data *);
++ int (*set_xgmii_speed)(struct xgbe_prv_data *);
++
++ void (*enable_tx)(struct xgbe_prv_data *);
++ void (*disable_tx)(struct xgbe_prv_data *);
++ void (*enable_rx)(struct xgbe_prv_data *);
++ void (*disable_rx)(struct xgbe_prv_data *);
++
++ void (*powerup_tx)(struct xgbe_prv_data *);
++ void (*powerdown_tx)(struct xgbe_prv_data *);
++ void (*powerup_rx)(struct xgbe_prv_data *);
++ void (*powerdown_rx)(struct xgbe_prv_data *);
++
++ int (*init)(struct xgbe_prv_data *);
++ int (*exit)(struct xgbe_prv_data *);
++
++ int (*enable_int)(struct xgbe_channel *, enum xgbe_int);
++ int (*disable_int)(struct xgbe_channel *, enum xgbe_int);
++ void (*dev_xmit)(struct xgbe_channel *);
++ int (*dev_read)(struct xgbe_channel *);
++ void (*tx_desc_init)(struct xgbe_channel *);
++ void (*rx_desc_init)(struct xgbe_channel *);
++ void (*rx_desc_reset)(struct xgbe_ring_data *);
++ void (*tx_desc_reset)(struct xgbe_ring_data *);
++ int (*is_last_desc)(struct xgbe_ring_desc *);
++ int (*is_context_desc)(struct xgbe_ring_desc *);
++ void (*tx_start_xmit)(struct xgbe_channel *, struct xgbe_ring *);
++
++ /* For FLOW ctrl */
++ int (*config_tx_flow_control)(struct xgbe_prv_data *);
++ int (*config_rx_flow_control)(struct xgbe_prv_data *);
++
++ /* For RX coalescing */
++ int (*config_rx_coalesce)(struct xgbe_prv_data *);
++ int (*config_tx_coalesce)(struct xgbe_prv_data *);
++ unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int);
++ unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int);
++
++ /* For RX and TX threshold config */
++ int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int);
++ int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int);
++
++ /* For RX and TX Store and Forward Mode config */
++ int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int);
++ int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int);
++
++ /* For TX DMA Operate on Second Frame config */
++ int (*config_osp_mode)(struct xgbe_prv_data *);
++
++ /* For RX and TX PBL config */
++ int (*config_rx_pbl_val)(struct xgbe_prv_data *);
++ int (*get_rx_pbl_val)(struct xgbe_prv_data *);
++ int (*config_tx_pbl_val)(struct xgbe_prv_data *);
++ int (*get_tx_pbl_val)(struct xgbe_prv_data *);
++ int (*config_pblx8)(struct xgbe_prv_data *);
++
++ /* For MMC statistics */
++ void (*rx_mmc_int)(struct xgbe_prv_data *);
++ void (*tx_mmc_int)(struct xgbe_prv_data *);
++ void (*read_mmc_stats)(struct xgbe_prv_data *);
++
++ /* For Timestamp config */
++ int (*config_tstamp)(struct xgbe_prv_data *, unsigned int);
++ void (*update_tstamp_addend)(struct xgbe_prv_data *, unsigned int);
++ void (*set_tstamp_time)(struct xgbe_prv_data *, unsigned int sec,
++ unsigned int nsec);
++ u64 (*get_tstamp_time)(struct xgbe_prv_data *);
++ u64 (*get_tx_tstamp)(struct xgbe_prv_data *);
++
++ /* For Data Center Bridging config */
++ void (*config_dcb_tc)(struct xgbe_prv_data *);
++ void (*config_dcb_pfc)(struct xgbe_prv_data *);
++
++ /* For Receive Side Scaling */
++ int (*enable_rss)(struct xgbe_prv_data *);
++ int (*disable_rss)(struct xgbe_prv_data *);
++ int (*set_rss_hash_key)(struct xgbe_prv_data *, const u8 *);
++ int (*set_rss_lookup_table)(struct xgbe_prv_data *, const u32 *);
++};
++
++struct xgbe_desc_if {
++ int (*alloc_ring_resources)(struct xgbe_prv_data *);
++ void (*free_ring_resources)(struct xgbe_prv_data *);
++ int (*map_tx_skb)(struct xgbe_channel *, struct sk_buff *);
++ int (*map_rx_buffer)(struct xgbe_prv_data *, struct xgbe_ring *,
++ struct xgbe_ring_data *);
++ void (*unmap_rdata)(struct xgbe_prv_data *, struct xgbe_ring_data *);
++ void (*wrapper_tx_desc_init)(struct xgbe_prv_data *);
++ void (*wrapper_rx_desc_init)(struct xgbe_prv_data *);
++};
++
++/* This structure contains flags that indicate what hardware features
++ * or configurations are present in the device.
++ */
++struct xgbe_hw_features {
++ /* HW Version */
++ unsigned int version;
++
++ /* HW Feature Register0 */
++ unsigned int gmii; /* 1000 Mbps support */
++ unsigned int vlhash; /* VLAN Hash Filter */
++ unsigned int sma; /* SMA(MDIO) Interface */
++ unsigned int rwk; /* PMT remote wake-up packet */
++ unsigned int mgk; /* PMT magic packet */
++ unsigned int mmc; /* RMON module */
++ unsigned int aoe; /* ARP Offload */
++ unsigned int ts; /* IEEE 1588-2008 Adavanced Timestamp */
++ unsigned int eee; /* Energy Efficient Ethernet */
++ unsigned int tx_coe; /* Tx Checksum Offload */
++ unsigned int rx_coe; /* Rx Checksum Offload */
++ unsigned int addn_mac; /* Additional MAC Addresses */
++ unsigned int ts_src; /* Timestamp Source */
++ unsigned int sa_vlan_ins; /* Source Address or VLAN Insertion */
++
++ /* HW Feature Register1 */
++ unsigned int rx_fifo_size; /* MTL Receive FIFO Size */
++ unsigned int tx_fifo_size; /* MTL Transmit FIFO Size */
++ unsigned int adv_ts_hi; /* Advance Timestamping High Word */
++ unsigned int dcb; /* DCB Feature */
++ unsigned int sph; /* Split Header Feature */
++ unsigned int tso; /* TCP Segmentation Offload */
++ unsigned int dma_debug; /* DMA Debug Registers */
++ unsigned int rss; /* Receive Side Scaling */
++ unsigned int tc_cnt; /* Number of Traffic Classes */
++ unsigned int hash_table_size; /* Hash Table Size */
++ unsigned int l3l4_filter_num; /* Number of L3-L4 Filters */
++
++ /* HW Feature Register2 */
++ unsigned int rx_q_cnt; /* Number of MTL Receive Queues */
++ unsigned int tx_q_cnt; /* Number of MTL Transmit Queues */
++ unsigned int rx_ch_cnt; /* Number of DMA Receive Channels */
++ unsigned int tx_ch_cnt; /* Number of DMA Transmit Channels */
++ unsigned int pps_out_num; /* Number of PPS outputs */
++ unsigned int aux_snap_num; /* Number of Aux snapshot inputs */
++};
++
++struct xgbe_prv_data {
++ struct net_device *netdev;
++ struct platform_device *pdev;
++ struct acpi_device *adev;
++ struct device *dev;
++
++ /* ACPI or DT flag */
++ unsigned int use_acpi;
++
++ /* XGMAC/XPCS related mmio registers */
++ void __iomem *xgmac_regs; /* XGMAC CSRs */
++ void __iomem *xpcs_regs; /* XPCS MMD registers */
++
++ /* Overall device lock */
++ spinlock_t lock;
++
++ /* XPCS indirect addressing mutex */
++ struct mutex xpcs_mutex;
++
++ /* RSS addressing mutex */
++ struct mutex rss_mutex;
++
++ int dev_irq;
++ unsigned int per_channel_irq;
++
++ struct xgbe_hw_if hw_if;
++ struct xgbe_desc_if desc_if;
++
++ /* AXI DMA settings */
++ unsigned int coherent;
++ unsigned int axdomain;
++ unsigned int arcache;
++ unsigned int awcache;
++
++ /* Rings for Tx/Rx on a DMA channel */
++ struct xgbe_channel *channel;
++ unsigned int channel_count;
++ unsigned int tx_ring_count;
++ unsigned int tx_desc_count;
++ unsigned int rx_ring_count;
++ unsigned int rx_desc_count;
++
++ unsigned int tx_q_count;
++ unsigned int rx_q_count;
++
++ /* Tx/Rx common settings */
++ unsigned int pblx8;
++
++ /* Tx settings */
++ unsigned int tx_sf_mode;
++ unsigned int tx_threshold;
++ unsigned int tx_pbl;
++ unsigned int tx_osp_mode;
++
++ /* Rx settings */
++ unsigned int rx_sf_mode;
++ unsigned int rx_threshold;
++ unsigned int rx_pbl;
++
++ /* Tx coalescing settings */
++ unsigned int tx_usecs;
++ unsigned int tx_frames;
++
++ /* Rx coalescing settings */
++ unsigned int rx_riwt;
++ unsigned int rx_frames;
++
++ /* Current Rx buffer size */
++ unsigned int rx_buf_size;
++
++ /* Flow control settings */
++ unsigned int pause_autoneg;
++ unsigned int tx_pause;
++ unsigned int rx_pause;
++
++ /* Receive Side Scaling settings */
++ u8 rss_key[XGBE_RSS_HASH_KEY_SIZE];
++ u32 rss_table[XGBE_RSS_MAX_TABLE_SIZE];
++ u32 rss_options;
++
++ /* MDIO settings */
++ struct module *phy_module;
++ char *mii_bus_id;
++ struct mii_bus *mii;
++ int mdio_mmd;
++ struct phy_device *phydev;
++ int default_autoneg;
++ int default_speed;
++
++ /* Current PHY settings */
++ phy_interface_t phy_mode;
++ int phy_link;
++ int phy_speed;
++ unsigned int phy_tx_pause;
++ unsigned int phy_rx_pause;
++
++ /* Netdev related settings */
++ unsigned char mac_addr[ETH_ALEN];
++ netdev_features_t netdev_features;
++ struct napi_struct napi;
++ struct xgbe_mmc_stats mmc_stats;
++
++ /* Filtering support */
++ unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
++
++ /* Device clocks */
++ struct clk *sysclk;
++ unsigned long sysclk_rate;
++ struct clk *ptpclk;
++ unsigned long ptpclk_rate;
++
++ /* Timestamp support */
++ spinlock_t tstamp_lock;
++ struct ptp_clock_info ptp_clock_info;
++ struct ptp_clock *ptp_clock;
++ struct hwtstamp_config tstamp_config;
++ struct cyclecounter tstamp_cc;
++ struct timecounter tstamp_tc;
++ unsigned int tstamp_addend;
++ struct work_struct tx_tstamp_work;
++ struct sk_buff *tx_tstamp_skb;
++ u64 tx_tstamp;
++
++ /* DCB support */
++ struct ieee_ets *ets;
++ struct ieee_pfc *pfc;
++ unsigned int q2tc_map[XGBE_MAX_QUEUES];
++ unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS];
++
++ /* Hardware features of the device */
++ struct xgbe_hw_features hw_feat;
++
++ /* Device restart work structure */
++ struct work_struct restart_work;
++
++ /* Keeps track of power mode */
++ unsigned int power_down;
++
++#ifdef CONFIG_DEBUG_FS
++ struct dentry *xgbe_debugfs;
++
++ unsigned int debugfs_xgmac_reg;
++
++ unsigned int debugfs_xpcs_mmd;
++ unsigned int debugfs_xpcs_reg;
++#endif
++};
++
++/* Function prototypes*/
++
++void xgbe_a0_init_function_ptrs_dev(struct xgbe_hw_if *);
++void xgbe_a0_init_function_ptrs_desc(struct xgbe_desc_if *);
++struct net_device_ops *xgbe_a0_get_netdev_ops(void);
++struct ethtool_ops *xgbe_a0_get_ethtool_ops(void);
++#ifdef CONFIG_AMD_XGBE_DCB
++const struct dcbnl_rtnl_ops *xgbe_a0_get_dcbnl_ops(void);
++#endif
++
++int xgbe_a0_mdio_register(struct xgbe_prv_data *);
++void xgbe_a0_mdio_unregister(struct xgbe_prv_data *);
++void xgbe_a0_dump_phy_registers(struct xgbe_prv_data *);
++void xgbe_a0_ptp_register(struct xgbe_prv_data *);
++void xgbe_a0_ptp_unregister(struct xgbe_prv_data *);
++void xgbe_a0_dump_tx_desc(struct xgbe_ring *, unsigned int, unsigned int,
++ unsigned int);
++void xgbe_a0_dump_rx_desc(struct xgbe_ring *, struct xgbe_ring_desc *,
++ unsigned int);
++void xgbe_a0_print_pkt(struct net_device *, struct sk_buff *, bool);
++void xgbe_a0_get_all_hw_features(struct xgbe_prv_data *);
++int xgbe_a0_powerup(struct net_device *, unsigned int);
++int xgbe_a0_powerdown(struct net_device *, unsigned int);
++void xgbe_a0_init_rx_coalesce(struct xgbe_prv_data *);
++void xgbe_a0_init_tx_coalesce(struct xgbe_prv_data *);
++
++#ifdef CONFIG_DEBUG_FS
++void xgbe_a0_debugfs_init(struct xgbe_prv_data *);
++void xgbe_a0_debugfs_exit(struct xgbe_prv_data *);
++#else
++static inline void xgbe_a0_debugfs_init(struct xgbe_prv_data *pdata) {}
++static inline void xgbe_a0_debugfs_exit(struct xgbe_prv_data *pdata) {}
++#endif /* CONFIG_DEBUG_FS */
++
++/* NOTE: Uncomment for TX and RX DESCRIPTOR DUMP in KERNEL LOG */
++#if 0
++#define XGMAC_ENABLE_TX_DESC_DUMP
++#define XGMAC_ENABLE_RX_DESC_DUMP
++#endif
++
++/* NOTE: Uncomment for TX and RX PACKET DUMP in KERNEL LOG */
++#if 0
++#define XGMAC_ENABLE_TX_PKT_DUMP
++#define XGMAC_ENABLE_RX_PKT_DUMP
++#endif
++
++/* NOTE: Uncomment for function trace log messages in KERNEL LOG */
++#if 0
++#define YDEBUG
++#define YDEBUG_MDIO
++#endif
++
++/* For debug prints */
++#ifdef YDEBUG
++#define DBGPR(x...) pr_alert(x)
++#define DBGPHY_REGS(x...) xgbe_a0_dump_phy_registers(x)
++#else
++#define DBGPR(x...) do { } while (0)
++#define DBGPHY_REGS(x...) do { } while (0)
++#endif
++
++#ifdef YDEBUG_MDIO
++#define DBGPR_MDIO(x...) pr_alert(x)
++#else
++#define DBGPR_MDIO(x...) do { } while (0)
++#endif
++
++#endif
diff --git a/ovl-don-t-remove-non-empty-opaque-directory.patch b/ovl-don-t-remove-non-empty-opaque-directory.patch
new file mode 100644
index 0000000..1f29e1e
--- /dev/null
+++ b/ovl-don-t-remove-non-empty-opaque-directory.patch
@@ -0,0 +1,57 @@
+From: Miklos Szeredi <mszeredi at suse.cz>
+Date: Thu, 14 May 2015 10:04:44 +0200
+Subject: [PATCH] ovl: don't remove non-empty opaque directory
+
+When removing an opaque directory we can't just call rmdir() to check for
+emptiness, because the directory will need to be replaced with a whiteout.
+The replacement is done with RENAME_EXCHANGE, which doesn't check
+emptiness.
+
+Solution is just to check emptiness by reading the directory. In the
+future we could add a new rename flag to check for emptiness even for
+RENAME_EXCHANGE to optimize this case.
+
+Reported-by: Vincent Batts <vbatts at gmail.com>
+Signed-off-by: Miklos Szeredi <mszeredi at suse.cz>
+Tested-by: Jordi Pujol Palomer <jordipujolp at gmail.com>
+Fixes: 263b4a0fee43 ("ovl: dont replace opaque dir")
+Cc: <stable at vger.kernel.org> # v4.0+
+---
+ fs/overlayfs/dir.c | 24 +++++++++++++++++++-----
+ 1 file changed, 19 insertions(+), 5 deletions(-)
+
+diff --git a/fs/overlayfs/dir.c b/fs/overlayfs/dir.c
+index d139405d2bfa..2578a0c0677d 100644
+--- a/fs/overlayfs/dir.c
++++ b/fs/overlayfs/dir.c
+@@ -506,11 +506,25 @@ static int ovl_remove_and_whiteout(struct dentry *dentry, bool is_dir)
+ struct dentry *opaquedir = NULL;
+ int err;
+
+- if (is_dir && OVL_TYPE_MERGE_OR_LOWER(ovl_path_type(dentry))) {
+- opaquedir = ovl_check_empty_and_clear(dentry);
+- err = PTR_ERR(opaquedir);
+- if (IS_ERR(opaquedir))
+- goto out;
++ if (is_dir) {
++ if (OVL_TYPE_MERGE_OR_LOWER(ovl_path_type(dentry))) {
++ opaquedir = ovl_check_empty_and_clear(dentry);
++ err = PTR_ERR(opaquedir);
++ if (IS_ERR(opaquedir))
++ goto out;
++ } else {
++ LIST_HEAD(list);
++
++ /*
++ * When removing an empty opaque directory, then it
++ * makes no sense to replace it with an exact replica of
++ * itself. But emptiness still needs to be checked.
++ */
++ err = ovl_check_empty_dir(dentry, &list);
++ ovl_cache_free(&list);
++ if (err)
++ goto out;
++ }
+ }
+
+ err = ovl_lock_rename_workdir(workdir, upperdir);
diff --git a/pty-Fix-input-race-when-closing.patch b/pty-Fix-input-race-when-closing.patch
index 364416e..fa9bb97 100644
--- a/pty-Fix-input-race-when-closing.patch
+++ b/pty-Fix-input-race-when-closing.patch
@@ -105,11 +105,11 @@ index 644ddb841d9f..bbc4ce66c2c1 100644
if (tty_hung_up_p(filp))
mask |= POLLHUP;
diff --git a/drivers/tty/n_tty.c b/drivers/tty/n_tty.c
-index 6f8cf3a52861..f9d9ed3f7e18 100644
+index cf6e0f2e1331..cc57a3a6b02b 100644
--- a/drivers/tty/n_tty.c
+++ b/drivers/tty/n_tty.c
-@@ -1960,6 +1960,18 @@ static inline int input_available_p(struct tty_struct *tty, int poll)
- return read_cnt(ldata) >= amt;
+@@ -1949,6 +1949,18 @@ static inline int input_available_p(struct tty_struct *tty, int poll)
+ return ldata->commit_head - ldata->read_tail >= amt;
}
+static inline int check_other_done(struct tty_struct *tty)
@@ -127,7 +127,7 @@ index 6f8cf3a52861..f9d9ed3f7e18 100644
/**
* copy_from_read_buf - copy read data directly
* @tty: terminal device
-@@ -2177,7 +2189,7 @@ static ssize_t n_tty_read(struct tty_struct *tty, struct file *file,
+@@ -2167,7 +2179,7 @@ static ssize_t n_tty_read(struct tty_struct *tty, struct file *file,
struct n_tty_data *ldata = tty->disc_data;
unsigned char __user *b = buf;
DEFINE_WAIT_FUNC(wait, woken_wake_function);
@@ -136,7 +136,7 @@ index 6f8cf3a52861..f9d9ed3f7e18 100644
int minimum, time;
ssize_t retval = 0;
long timeout;
-@@ -2243,8 +2255,10 @@ static ssize_t n_tty_read(struct tty_struct *tty, struct file *file,
+@@ -2235,8 +2247,10 @@ static ssize_t n_tty_read(struct tty_struct *tty, struct file *file,
((minimum - (b - buf)) >= 1))
ldata->minimum_to_wake = (minimum - (b - buf));
@@ -148,7 +148,7 @@ index 6f8cf3a52861..f9d9ed3f7e18 100644
retval = -EIO;
break;
}
-@@ -2451,12 +2465,12 @@ static unsigned int n_tty_poll(struct tty_struct *tty, struct file *file,
+@@ -2443,12 +2457,12 @@ static unsigned int n_tty_poll(struct tty_struct *tty, struct file *file,
poll_wait(file, &tty->read_wait, wait);
poll_wait(file, &tty->write_wait, wait);
@@ -164,7 +164,7 @@ index 6f8cf3a52861..f9d9ed3f7e18 100644
mask |= POLLHUP;
if (!(mask & (POLLHUP | POLLIN | POLLRDNORM))) {
diff --git a/drivers/tty/pty.c b/drivers/tty/pty.c
-index 6e1f1505f04e..ca7b68968203 100644
+index e72ee629cead..4d5e8409769c 100644
--- a/drivers/tty/pty.c
+++ b/drivers/tty/pty.c
@@ -53,9 +53,8 @@ static void pty_close(struct tty_struct *tty, struct file *filp)
@@ -178,7 +178,7 @@ index 6e1f1505f04e..ca7b68968203 100644
wake_up_interruptible(&tty->link->write_wait);
if (tty->driver->subtype == PTY_TYPE_MASTER) {
set_bit(TTY_OTHER_CLOSED, &tty->flags);
-@@ -250,7 +249,9 @@ static int pty_open(struct tty_struct *tty, struct file *filp)
+@@ -243,7 +242,9 @@ static int pty_open(struct tty_struct *tty, struct file *filp)
goto out;
clear_bit(TTY_IO_ERROR, &tty->flags);
@@ -189,7 +189,7 @@ index 6e1f1505f04e..ca7b68968203 100644
return 0;
diff --git a/drivers/tty/tty_buffer.c b/drivers/tty/tty_buffer.c
-index 3605103fc1ac..79bcdf93568b 100644
+index 75661641f5fe..2f78b77f0f81 100644
--- a/drivers/tty/tty_buffer.c
+++ b/drivers/tty/tty_buffer.c
@@ -37,6 +37,28 @@
@@ -263,10 +263,10 @@ index 3605103fc1ac..79bcdf93568b 100644
* @port: tty port to push
*
diff --git a/include/linux/tty.h b/include/linux/tty.h
-index 7d66ae508e5c..8716524f0b25 100644
+index 358a337af598..790752ac074a 100644
--- a/include/linux/tty.h
+++ b/include/linux/tty.h
-@@ -316,6 +316,7 @@ struct tty_file_private {
+@@ -339,6 +339,7 @@ struct tty_file_private {
#define TTY_EXCLUSIVE 3 /* Exclusive open mode */
#define TTY_DEBUG 4 /* Debugging */
#define TTY_DO_WRITE_WAKEUP 5 /* Call write_wakeup after queuing new */
@@ -274,7 +274,7 @@ index 7d66ae508e5c..8716524f0b25 100644
#define TTY_LDISC_OPEN 11 /* Line discipline is open */
#define TTY_PTY_LOCK 16 /* pty private */
#define TTY_NO_WRITE_SPLIT 17 /* Preserve write boundaries to driver */
-@@ -439,7 +440,6 @@ extern int tty_hung_up_p(struct file *filp);
+@@ -462,7 +463,6 @@ extern int tty_hung_up_p(struct file *filp);
extern void do_SAK(struct tty_struct *tty);
extern void __do_SAK(struct tty_struct *tty);
extern void no_tty(void);
diff --git a/security-yama-Remove-unnecessary-selects-from-Kconfi.patch b/security-yama-Remove-unnecessary-selects-from-Kconfi.patch
new file mode 100644
index 0000000..4e0171b
--- /dev/null
+++ b/security-yama-Remove-unnecessary-selects-from-Kconfi.patch
@@ -0,0 +1,25 @@
+From: Stephen Smalley <sds at tycho.nsa.gov>
+Date: Fri, 27 Feb 2015 16:23:59 -0500
+Subject: [PATCH] security/yama: Remove unnecessary selects from Kconfig.
+
+Yama selects SECURITYFS and SECURITY_PATH, but requires neither.
+Remove them.
+
+Signed-off-by: Stephen Smalley <sds at tycho.nsa.gov>
+---
+ security/yama/Kconfig | 2 --
+ 1 file changed, 2 deletions(-)
+
+diff --git a/security/yama/Kconfig b/security/yama/Kconfig
+index 20ef5143c0c0..3123e1da2fed 100644
+--- a/security/yama/Kconfig
++++ b/security/yama/Kconfig
+@@ -1,8 +1,6 @@
+ config SECURITY_YAMA
+ bool "Yama support"
+ depends on SECURITY
+- select SECURITYFS
+- select SECURITY_PATH
+ default n
+ help
+ This selects Yama, which extends DAC support with additional
diff --git a/sources b/sources
index 1312b7c..8f13e05 100644
--- a/sources
+++ b/sources
@@ -1,3 +1,3 @@
-d3fc8316d4d4d04b65cbc2d70799e763 linux-3.19.tar.xz
-15d8d2f97ce056488451a5bfb2944603 perf-man-3.19.tar.gz
-a450d6f46c2397dec767ac409111c144 patch-3.19.8.xz
+a86916bd12798220da9eb4a1eec3616d linux-4.0.tar.xz
+d125eecce68ab6fb5f1f23523c2c04b8 perf-man-4.0.tar.gz
+0ccd3969e595402f4f6bed790d5481a6 patch-4.0.3.xz
diff --git a/toshiba_acpi-Do-not-register-vendor-backlight-when-a.patch b/toshiba_acpi-Do-not-register-vendor-backlight-when-a.patch
index 7289d58..94b3bcf 100644
--- a/toshiba_acpi-Do-not-register-vendor-backlight-when-a.patch
+++ b/toshiba_acpi-Do-not-register-vendor-backlight-when-a.patch
@@ -1,5 +1,5 @@
From: Hans de Goede <hdegoede at redhat.com>
-Date: Tue, 14 Apr 2015 11:15:24 +0200
+Date: Tue, 21 Apr 2015 12:01:32 +0200
Subject: [PATCH] toshiba_acpi: Do not register vendor backlight when
acpi_video bl is available
@@ -22,14 +22,18 @@ acpi-video implementation while the toshiba vendor backlight interface does
work, this commit adds an empty dmi_id table where such systems can be added,
this is identical to how other drivers handle such systems.
+BugLink: https://bugzilla.redhat.com/show_bug.cgi?id=1206036
+BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=86521
Signed-off-by: Hans de Goede <hdegoede at redhat.com>
+Reviewed-and-tested-by: Azael Avalos <coproscefalo at gmail.com>
+Signed-off-by: Darren Hart <dvhart at linux.intel.com>
---
drivers/platform/x86/Kconfig | 1 +
drivers/platform/x86/toshiba_acpi.c | 23 +++++++++++++++++++++++
2 files changed, 24 insertions(+)
diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig
-index 638e797037da..c3fd78820d07 100644
+index 97527614141b..f9f205cb1f11 100644
--- a/drivers/platform/x86/Kconfig
+++ b/drivers/platform/x86/Kconfig
@@ -614,6 +614,7 @@ config ACPI_TOSHIBA
@@ -41,22 +45,21 @@ index 638e797037da..c3fd78820d07 100644
select INPUT_SPARSEKMAP
---help---
diff --git a/drivers/platform/x86/toshiba_acpi.c b/drivers/platform/x86/toshiba_acpi.c
-index fc34a71866ed..1c5879ae3b53 100644
+index dbcb7a8915b8..2da716c3b648 100644
--- a/drivers/platform/x86/toshiba_acpi.c
+++ b/drivers/platform/x86/toshiba_acpi.c
-@@ -57,6 +57,7 @@
- #include <linux/i8042.h>
+@@ -51,6 +51,7 @@
#include <linux/acpi.h>
#include <linux/dmi.h>
+ #include <linux/uaccess.h>
+#include <acpi/video.h>
- #include <asm/uaccess.h>
MODULE_AUTHOR("John Belmonte");
-@@ -264,6 +265,14 @@ static const struct key_entry toshiba_acpi_alt_keymap[] = {
- { KE_END, 0 },
+ MODULE_DESCRIPTION("Toshiba Laptop ACPI Extras Driver");
+@@ -281,6 +282,14 @@ static const struct key_entry toshiba_acpi_alt_keymap[] = {
};
-+/*
+ /*
+ * List of models which have a broken acpi-video backlight interface and thus
+ * need to use the toshiba (vendor) interface instead.
+ */
@@ -64,10 +67,11 @@ index fc34a71866ed..1c5879ae3b53 100644
+ {}
+};
+
- /* utility
++/*
+ * Utility
*/
-@@ -1798,6 +1807,20 @@ static int toshiba_acpi_setup_backlight(struct toshiba_acpi_dev *dev)
+@@ -2541,6 +2550,20 @@ static int toshiba_acpi_setup_backlight(struct toshiba_acpi_dev *dev)
ret = get_tr_backlight_status(dev, &enabled);
dev->tr_backlight_supported = !ret;
diff --git a/usb-make-xhci-platform-driver-use-64-bit-or-32-bit-D.patch b/usb-make-xhci-platform-driver-use-64-bit-or-32-bit-D.patch
new file mode 100644
index 0000000..da38d70
--- /dev/null
+++ b/usb-make-xhci-platform-driver-use-64-bit-or-32-bit-D.patch
@@ -0,0 +1,40 @@
+From: Mark Langsdorf <mlangsdo at redhat.com>
+Date: Wed, 25 Mar 2015 14:12:51 -0400
+Subject: [PATCH] usb: make xhci platform driver use 64 bit or 32 bit DMA
+
+The xhci platform driver needs to work on systems that either only
+support 64-bit DMA or only support 32-bit DMA. Attempt to set a
+coherent dma mask for 64-bit DMA, and attempt again with 32-bit
+DMA if that fails.
+
+Signed-off-by: Mark Langsdorf <mlangsdo at redhat.com>
+---
+ drivers/usb/host/xhci-plat.c | 15 +++++++--------
+ 1 file changed, 7 insertions(+), 8 deletions(-)
+
+diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
+index 0e11d61408ff..cc5ca2cac706 100644
+--- a/drivers/usb/host/xhci-plat.c
++++ b/drivers/usb/host/xhci-plat.c
+@@ -83,14 +83,13 @@ static int xhci_plat_probe(struct platform_device *pdev)
+ if (irq < 0)
+ return -ENODEV;
+
+- /* Initialize dma_mask and coherent_dma_mask to 32-bits */
+- ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
+- if (ret)
+- return ret;
+- if (!pdev->dev.dma_mask)
+- pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
+- else
+- dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
++ /* Try setting the coherent_dma_mask to 64 bits, then try 32 bits */
++ ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
++ if (ret) {
++ ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
++ if (ret)
++ return ret;
++ }
+
+ hcd = usb_create_hcd(driver, &pdev->dev, dev_name(&pdev->dev));
+ if (!hcd)
diff --git a/vhost-scsi-potential-memory-corruption.patch b/vhost-scsi-potential-memory-corruption.patch
deleted file mode 100644
index 3628d35..0000000
--- a/vhost-scsi-potential-memory-corruption.patch
+++ /dev/null
@@ -1,50 +0,0 @@
-From: Dan Carpenter <dan.carpenter at oracle.com>
-Date: Thu, 5 Feb 2015 10:37:33 +0300
-Subject: [PATCH] vhost/scsi: potential memory corruption
-
-This code in vhost_scsi_make_tpg() is confusing because we limit "tpgt"
-to UINT_MAX but the data type of "tpg->tport_tpgt" and that is a u16.
-
-I looked at the context and it turns out that in
-vhost_scsi_set_endpoint(), "tpg->tport_tpgt" is used as an offset into
-the vs_tpg[] array which has VHOST_SCSI_MAX_TARGET (256) elements so
-anything higher than 255 then it is invalid. I have made that the limit
-now.
-
-In vhost_scsi_send_evt() we mask away values higher than 255, but now
-that the limit has changed, we don't need the mask.
-
-Signed-off-by: Dan Carpenter <dan.carpenter at oracle.com>
-Signed-off-by: Nicholas Bellinger <nab at linux-iscsi.org>
----
- drivers/vhost/scsi.c | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
-diff --git a/drivers/vhost/scsi.c b/drivers/vhost/scsi.c
-index d695b1673ae5..f5c98e6f7b58 100644
---- a/drivers/vhost/scsi.c
-+++ b/drivers/vhost/scsi.c
-@@ -1253,7 +1253,7 @@ tcm_vhost_send_evt(struct vhost_scsi *vs,
- * lun[4-7] need to be zero according to virtio-scsi spec.
- */
- evt->event.lun[0] = 0x01;
-- evt->event.lun[1] = tpg->tport_tpgt & 0xFF;
-+ evt->event.lun[1] = tpg->tport_tpgt;
- if (lun->unpacked_lun >= 256)
- evt->event.lun[2] = lun->unpacked_lun >> 8 | 0x40 ;
- evt->event.lun[3] = lun->unpacked_lun & 0xFF;
-@@ -2124,12 +2124,12 @@ tcm_vhost_make_tpg(struct se_wwn *wwn,
- struct tcm_vhost_tport, tport_wwn);
-
- struct tcm_vhost_tpg *tpg;
-- unsigned long tpgt;
-+ u16 tpgt;
- int ret;
-
- if (strstr(name, "tpgt_") != name)
- return ERR_PTR(-EINVAL);
-- if (kstrtoul(name + 5, 10, &tpgt) || tpgt > UINT_MAX)
-+ if (kstrtou16(name + 5, 10, &tpgt) || tpgt > VHOST_SCSI_MAX_TARGET)
- return ERR_PTR(-EINVAL);
-
- tpg = kzalloc(sizeof(struct tcm_vhost_tpg), GFP_KERNEL);
diff --git a/x86-Lock-down-IO-port-access-when-module-security-is.patch b/x86-Lock-down-IO-port-access-when-module-security-is.patch
index 9243f43..697f5b1 100644
--- a/x86-Lock-down-IO-port-access-when-module-security-is.patch
+++ b/x86-Lock-down-IO-port-access-when-module-security-is.patch
@@ -44,7 +44,7 @@ index 4ddaf66ea35f..00b440307419 100644
}
regs->flags = (regs->flags & ~X86_EFLAGS_IOPL) | (level << 12);
diff --git a/drivers/char/mem.c b/drivers/char/mem.c
-index 4c58333b4257..fc9637812d78 100644
+index 297110c12635..efe38c1bc234 100644
--- a/drivers/char/mem.c
+++ b/drivers/char/mem.c
@@ -27,6 +27,7 @@
@@ -53,9 +53,9 @@ index 4c58333b4257..fc9637812d78 100644
#include <linux/aio.h>
+#include <linux/module.h>
- #include <asm/uaccess.h>
+ #include <linux/uaccess.h>
-@@ -571,6 +572,9 @@ static ssize_t write_port(struct file *file, const char __user *buf,
+@@ -577,6 +578,9 @@ static ssize_t write_port(struct file *file, const char __user *buf,
unsigned long i = *ppos;
const char __user *tmp = buf;
diff --git a/x86-microcode-intel-Guard-against-stack-overflow-in-.patch b/x86-microcode-intel-Guard-against-stack-overflow-in-.patch
deleted file mode 100644
index 4e71e84..0000000
--- a/x86-microcode-intel-Guard-against-stack-overflow-in-.patch
+++ /dev/null
@@ -1,32 +0,0 @@
-From: Quentin Casasnovas <quentin.casasnovas at oracle.com>
-Date: Tue, 3 Feb 2015 13:00:22 +0100
-Subject: [PATCH] x86/microcode/intel: Guard against stack overflow in the
- loader
-
-mc_saved_tmp is a static array allocated on the stack, we need to make
-sure mc_saved_count stays within its bounds, otherwise we're overflowing
-the stack in _save_mc(). A specially crafted microcode header could lead
-to a kernel crash or potentially kernel execution.
-
-Signed-off-by: Quentin Casasnovas <quentin.casasnovas at oracle.com>
-Cc: "H. Peter Anvin" <hpa at zytor.com>
-Cc: Fenghua Yu <fenghua.yu at intel.com>
-Link: http://lkml.kernel.org/r/1422964824-22056-1-git-send-email-quentin.casasnovas@oracle.com
-Signed-off-by: Borislav Petkov <bp at suse.de>
----
- arch/x86/kernel/cpu/microcode/intel_early.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/arch/x86/kernel/cpu/microcode/intel_early.c b/arch/x86/kernel/cpu/microcode/intel_early.c
-index ec9df6f9cd47..5e109a31f62b 100644
---- a/arch/x86/kernel/cpu/microcode/intel_early.c
-+++ b/arch/x86/kernel/cpu/microcode/intel_early.c
-@@ -321,7 +321,7 @@ get_matching_model_microcode(int cpu, unsigned long start,
- unsigned int mc_saved_count = mc_saved_data->mc_saved_count;
- int i;
-
-- while (leftover) {
-+ while (leftover && mc_saved_count < ARRAY_SIZE(mc_saved_tmp)) {
- mc_header = (struct microcode_header_intel *)ucode_ptr;
-
- mc_size = get_totalsize(mc_header);
--
cgit v0.10.2
http://pkgs.fedoraproject.org/cgit/kernel.git/commit/?h=f21&id=09b06469de7217f71af2e46fd943585623d7b33c
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