[free-electronic-lab] vasy giving a Segmentation Fault

[Ashwith Rego]

Hi,

I wrote some verilog code and from this I generated an equivaltent
VHDL code using Icarus Verilog's VHDL code generator. vasy didn't take
this so I made some changes going by the errors it gave. The last time
I tried it, it gave a Segmentation fault. I ran the following
commands:

iverilog -t vhdl alu8.v -o alu8.vhdl

vasy -Vao alu8.vhdl

I have attached my verilog code and the code generated by Icarus (with
the changes I made). Is there something in the VHDL code that
shouldn't be there? Is there a way to get around this or fix it?

Thanks
--
Ashwith J. Rego
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