hi Robert nice to hear from you. cutting below to relevant context....
On Sunday, February 7, 2021, Robert Scheck robert@fedoraproject.org wrote:
switched from RISC-V to Power. During FOSDEM 2021, I noticed their LibreSOC Project stand [5] and asked multiple beginner questions, which Luke Kenneth Casson Leighton (on Cc) nicely took care of (thank you!).
:)
Given an idea is a Power-based SBC [6], I wondered whether I could just run a Fedora for ppc64le (which seems to currently target POWER8 LE and later), on it. Unfortunately Luke's answer was no, because LibreSOC won't support VSX [7], which are IBM's SIMD (six hundred?) instructions,
with the Optional VSX cut out we can comply with the "Embedded Floating Point Compliancy" subset, and under the Compliancy rules add a RADIX4 MMU, XICS and other features to fully run a standard linux kernel.
and this may be achieved in a sane amount of time and resources.
OpenPOWER v3.0B integer is only around 150 instructions. FP is around 30 more. VSX which was great in 2003 is SIX HUNDRED and does not even have predication which is critically important for modern 3D GPU Shader Applications.
but the LibreSOC Project plans to have Simple-V Vectorisation according to their FOSDEM talk [8]. Note, the A2O POWER processor core [9] doesn't support VSX, too (same seems to apply to A2I and Microwatt, but they're either POWER7 or likely not powerful enough for typical PC usage anyway -> outside of Fedora's target?).
A2O and A2I are v2.07 / v2.08, microwatt is v3.0B with no legacy.
A common misunderstanding is to conflate IBM proprietary ASIC product numbers with OpenPOWER ISA numbers.
this assumption then turns into, "well it is in IBM's proprietary implementation therefore obviously all other implementations MUST have all the same features because POWER9===v3.0B"
and that unfortunately is a misunderstanding that is causing huge problems.
Trying to follow the path on how to get Fedora for ppc64le to a "POWER-Pi", I had to learn that glibc developers seem to treat IBM POWER9 strictly equal to ABI rules rather handling the different features more fine granulated.
#ifdef POWER9 rather than #ifdef VSX, or #ifdef NE_OTHER_HW_FEATURE, yes.
in speaking with Mendy from the OpenPOWER Foundation I learned that this practice is a misunderstanding of the intention behind the Compliancy Subsets
My understanding here might be imprecise or wrong, this is what I understood and I'm no expert at this topic. Nevertheless I'm trying to precise it a bit more:
The IBM Power ISA Version 3.1 [10] specifies on page 8 compliancy subsets, where the Linux Compliancy Subset (LCS) is explained on page 10 ff. Page 11 refers specifically to the "Scalar Float Optional Features" and mentions in the first row of the table VSX. However what seems to be implemented e.g. in glibc is something like "#ifdef POWER9" rather "#ifdef HARDWAREFEATURE", which effectively makes VSX support mandatory rather optional.
exactly.
this therefore effectively and accidentally discriminates against *all* Libre / Open Hardware implementations of OpenPOWER.
* A2O and A2I: prevented and prohibited due to no VSX (and unlikely to add it due to the high development cost) * Libre-SOC: likewise * Microwatt: Paul is making an effort to add experimental bare minimum VSX, it is a losing battle with every new #ifdef POWER9 patch accepted in glibc6.
Given the only publicly known modern implementor of VSX right now, not on an EOL schedule,
(the NXP Quorl is going EOL).
going through the Compliancy Levels I notice and confirm what you spotted, Robert: *VSX is OPTIONAL*, it is *NOT* mandatory.
thus, glibc6 is not compliant with the v3.1B spec (or the v3.0C Spec).
the features below, copied from v3.1B, basically define what ppc HWCAPS should contain, in effect, although some of these are kernelspace many of them (VSX/SIMD, QFP, SIMD, OV, LSM) are definitely candidates for HWCAPS.
Linux Optional Features
The following features are **OPTIONAL** for the Linux Compliancy Subset, the Scalar Fixed-Point + Floating-Point Compliancy Subset, and the Scalar Fixed-Point Compliancy Subset.
AIL/HAIL programmability (AIL) Atomic Memory Operations (AMO) Big Endian (BE) (LE is required for LCS) Branch History Rolling Buffer (BHRB) Event-Based Branching (EBB) SLB / HPT translation (HPT) Load/Store Multiple instructions (LM) Processor Compatibility Register (PCR) Quad-precision floating-point (QFP) Broadcast TLB shootdown (TLBIE) (tlbiel not optional) SMT (SMT) visor/ultravior messaging not optional)
Scalar Float Optional Features
The following features are **OPTIONAL** for the Scalar Fixed-Point + Floating-Point Compliancy Subset and the Scalar Fixed-Point Compliancy Subset.
SIMD (SIMD) (VMX and VSX) SF=1 (64-bit) Little Endian (LE) Fixed-point instructions that modify OV indicate whether overflow occurred (OV) Nested radix translation (ROR) (single-level radix translation not optional)